; --------------------------------------------------------------------------------
; @Title: RCARS4 On-Chip Peripherals
; @Props: Confidential
; @Author: RSA, DAB, PIW, KRZ
; @Changelog: 2022-01-24 RSA
;             2022-03-04 DAB
;             2022-05-20 PIW
;             2023-02-20 KRZ
; @Manufacturer: RENESAS - Renesas Technology, Corp.
; @Doc: SVD generated (SVD2PER 1.8.6), based on:
;       Renesas_R-Car_s4_cpu.svd (Ver. 1.0)
; @Core: Cortex-A55, Cortex-R52
; @Chip: RCARS4, RCARS4-CR52
; @Copyright: (C) 1989-2023 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: perrcars4.per 15779 2023-02-20 16:21:48Z kwisniewski $

sif (CORENAME()=="CORTEXA55")
tree "Core Registers (Cortex-A55)"
AUTOINDENT.PUSH
AUTOINDENT.ON center tree
tree.open "AArch64"
tree "ID Registers"
rgroup.quad spr:0x30000++0x00
line.quad 0x00 "MIDR_EL1,Main ID Register"
hexmask.quad.byte 0x0 24.--31. 1. "IMPL,Implementer code"
bitfld.quad 0x00 20.--23. "VAR,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 16.--19. "ARCH, Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,CPUID scheme"
newline
hexmask.quad.word 0x00 4.--15. 1. "PART,Primary Part Number"
bitfld.quad 0x00 0.--3. "REV,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
if (CORENAME()=="CORTEXA75")
rgroup.quad spr:0x30040++0x00
line.quad 0x00 "ID_AA64PFR0_EL1,Processor Feature Register 0"
bitfld.quad 0x00 60.--63. "CSV3,Speculative use of faulting data" "Cannot be used,?..."
bitfld.quad 0x00 56.--59. "CSV2,Speculative use of out of context branch targets" "Cannot effect,?..."
newline
bitfld.quad 0x00 28.--31. "RAS,RAS extension version" "Reserved,Version 1,?..."
bitfld.quad 0x00 24.--27. "GIC,GIC CPU interface" "Disabled,Enabled,?..."
newline
bitfld.quad 0x00 20.--23. "ASIMD,Advanced SIMD" "Reserved,Implemented,?..."
bitfld.quad 0x00 16.--19. "FP,Floating-point" "Reserved,Implemented,?..."
newline
bitfld.quad 0x00 12.--15. "EL3_ELH,EL3 exception level handling" "Reserved,Reserved,AArch64/AArch32,?..."
bitfld.quad 0x00 8.--11. "EL2_ELH,EL2 exception level handling" "Reserved,Reserved,AArch64/AArch32,?..."
newline
bitfld.quad 0x00 4.--7. "EL1_ELH,EL1 exception level handling" "Reserved,Reserved,AArch64/AArch32,?..."
bitfld.quad 0x00 0.--3. "EL0_ELH,EL0 exception level handling" "Reserved,Reserved,AArch64/AArch32,?..."
elif (CORENAME()=="CORTEXA55")
rgroup.quad spr:0x30040++0x00
line.quad 0x00 "ID_AA64PFR0_EL1,Processor Feature Register 0"
bitfld.quad 0x00 60.--63. "CSV3,Speculative use of faulting data" "Reserved,Forbidden,?..."
bitfld.quad 0x00 56.--59. "CSV2,Speculative use of faulting data" "Reserved,Forbidden,?..."
newline
bitfld.quad 0x00 28.--31. "RAS,RAS extension version" "Reserved,Version 1,?..."
bitfld.quad 0x00 24.--27. "GIC,GIC CPU interface" "Disabled,Enabled,?..."
newline
bitfld.quad 0x00 20.--23. "ASIMD,Advanced SIMD" "Reserved,Implemented,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Not implemented"
bitfld.quad 0x00 16.--19. "FP,Floating-point" "Reserved,Implemented,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Not implemented"
newline
bitfld.quad 0x00 12.--15. "EL3_ELH,EL3 exception level handling" "Reserved,Reserved,AArch64/AArch32,?..."
bitfld.quad 0x00 8.--11. "EL2_ELH,EL2 exception level handling" "Reserved,Reserved,AArch64/AArch32,?..."
newline
bitfld.quad 0x00 4.--7. "EL1_ELH,EL1 exception level handling" "Reserved,Reserved,AArch64/AArch32,?..."
bitfld.quad 0x00 0.--3. "EL0_ELH,EL0 exception level handling" "Reserved,Reserved,AArch64/AArch32,?..."
rgroup.quad spr:0x30041++0x00
line.quad 0x00 "ID_AA64PFR1_EL1,Processor Feature Register 1"
bitfld.quad 0x00 4.--7. "SSBS,Speculative store bypassing safe mechanism implemented" "Reserved,Implemented,?..."
endif
rgroup.quad spr:0x30050++0x00
line.quad 0x00 "ID_AA64DFR0_EL1,AArch64 Debug Feature Register"
bitfld.quad 0x00 28.--31. "CTX_CMPS,Number of breakpoints that are context-aware" "Reserved,2,?..."
bitfld.quad 0x00 20.--23. "WRPS,Number of watchpoints" "Reserved,Reserved,Reserved,4,?..."
bitfld.quad 0x00 12.--15. "BRPS,Number of breakpoints" "Reserved,Reserved,Reserved,Reserved,Reserved,6,?..."
newline
bitfld.quad 0x00 8.--11. "PMEV,Performance monitor extension version" "Reserved,Reserved,Reserved,Reserved,Version 3/16 bit evtCount,?..."
bitfld.quad 0x00 4.--7. "TEV,Trace extension version" "Not implemented,?..."
bitfld.quad 0x00 0.--3. "DAV,Debug architecture version" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,v8-A,?..."
rgroup.quad spr:0x30060++0x00
line.quad 0x00 "ID_AA64ISAR0_EL1,Instruction Set Attribute Register 0"
bitfld.quad 0x00 44.--47. "DP,Implemented UDOT and SDOT instructions" "Reserved,Implemented,?..."
newline
bitfld.quad 0x00 28.--31. "RDM,Rounding Double Multiply Add/Subtract instructions Support" "Reserved,Implemented,?..."
bitfld.quad 0x00 20.--23. "ATOMIC,Atomic instructions in AArch64" "Reserved,Reserved,Implemented,?..."
bitfld.quad 0x00 16.--19. "CRC32,Indicates whether CRC32 instructions are implemented" "Reserved,Implemented,?..."
newline
bitfld.quad 0x00 12.--15. "SHA2,SHA2 instructions in AArch64" "Not implemented,Implemented,?..."
bitfld.quad 0x00 8.--11. "SHA1,SHA1 instructions in AArch64" "Not implemented,Implemented,?..."
bitfld.quad 0x00 4.--7. "AES,AES instruction in AArch64" "Not implemented,Reserved,AESE/AESD/AESMC/AESIMC/PMULL/PMULL2,?..."
if (CORENAME()=="CORTEXA75")
rgroup.quad spr:0x30070++0x00
line.quad 0x00 "ID_AA64MMFR0_EL1,Memory Model Feature Register 0"
bitfld.quad 0x00 28.--31. "TGRAN4,4KB granule supported" "Supported,?..."
bitfld.quad 0x00 24.--27. "TGRAN64,64KB granule supported" "Supported,?..."
bitfld.quad 0x00 20.--23. "TGRAN16,16KB granule supported" "Reserved,Supported,?..."
newline
bitfld.quad 0x00 16.--19. "BIGENDEL0,Mixed-endian support at EL0" "Not supported,?..."
bitfld.quad 0x00 12.--15. "SNSMEM,Secure versus Non-secure Memory distinction" "Reserved,Supported,?..."
bitfld.quad 0x00 8.--11. "BIGEND,Mixed-endian configuration support" "Reserved,Supported,?..."
newline
bitfld.quad 0x00 4.--7. "ASIDBITS,Number of ASID bits" "Reserved,Reserved,16 bits,?..."
bitfld.quad 0x00 0.--3. "PARANGE,Physical address range supported" "Reserved,Reserved,Reserved,Reserved,44 bits/16 TB,?..."
elif (CORENAME()=="CORTEXA55")
rgroup.quad spr:0x30070++0x00
line.quad 0x00 "ID_AA64MMFR0_EL1,Memory Model Feature Register 0"
bitfld.quad 0x00 20.--23. "TGRAN16,16KB granule supported" "Reserved,Supported,?..."
bitfld.quad 0x00 16.--19. "BIGENDEL0,Mixed-endian support at EL0" "Not supported,?..."
bitfld.quad 0x00 12.--15. "SNSMEM,Secure versus Non-secure Memory distinction" "Reserved,Supported,?..."
newline
bitfld.quad 0x00 8.--11. "BIGEND,Mixed-endian configuration support" "Reserved,Supported,?..."
bitfld.quad 0x00 4.--7. "ASIDBITS,Number of ASID bits" "Reserved,Reserved,16 bits,?..."
bitfld.quad 0x00 0.--3. "PARANGE,Physical address range supported" "Reserved,Reserved,40 bits/1 TB,?..."
endif
rgroup.quad spr:0x30041++0x00
line.quad 0x00 "ID_AA64PFR1_EL1,Processor Feature Register 1"
bitfld.quad 0x00 4.--7. "SSBS,Speculative Store Bypassing Safe (SSBS) mechanism support" "Reserved,Supported,?..."
rgroup.quad spr:0x30051++0x00
line.quad 0x00 "ID_AA64DFR1_EL1,Debug Feature Register 1"
rgroup.quad spr:0x30061++0x00
line.quad 0x00 "ID_AA64ISAR1_EL1,Instruction Set Attribute Register 1"
bitfld.quad 0x00 20.--23. "LRCPC,Indicates whether load-acquire (LDA) instructions are implemented for an Release Consistent processor consistent RCPC model" "Reserved,Implemented,?..."
bitfld.quad 0x00 0.--3. "DPB,DC CVAP support in AArch64" "Reserved,Implemented,?..."
rgroup.quad spr:0x30071++0x00
line.quad 0x00 "ID_AA64MMFR1_EL1,Memory Model Feature Register 1"
bitfld.quad 0x00 28.--31. "XNX,EL0/EL1 execute control distinction at stage2 bit support" "Reserved,Supported,?..."
bitfld.quad 0x00 20.--23. "PAN,Privileged Access Never Support" "Reserved,Reserved,Extended,?..."
bitfld.quad 0x00 16.--19. "LO,Limited Order Regions Support" "Reserved,Supported,?..."
newline
bitfld.quad 0x00 12.--15. "HD,Hierarchical Permission Disabled Support" "Reserved,Reserved,Extended,?..."
bitfld.quad 0x00 8.--11. "VH,Virtualization Host Extensions Support" "Reserved,Supported,?..."
bitfld.quad 0x00 4.--7. "VMID,Number of VMID bits" "Reserved,Reserved,16 bits,?..."
newline
bitfld.quad 0x00 0.--3. "HAFDBS,Hardware updates of the Access and Dirty" "Reserved,Reserved,Access/Dirty supported,?..."
if (CORENAME()=="CORTEXA75")
rgroup.quad spr:0x30072++0x00
line.quad 0x00 "ID_AA64MMFR2_EL1,Memory Model Feature Register 2"
bitfld.quad 0x00 12.--15. "IESB, Indicates whether an implicit Error Synchronization Barrier has been inserted" "Reserved,Supported,?..."
bitfld.quad 0x00 8.--11. "LSM,Indicates whether LDM and STM are supported" "Not supported,?..."
bitfld.quad 0x00 4.--7. "UAO,User Access Override support" "Reserved,Supported,?..."
newline
bitfld.quad 0x00 0.--3. "CNP,Common not Private support" "Reserved,Supported,?..."
elif (CORENAME()=="CORTEXA55")
rgroup.quad spr:0x30072++0x00
line.quad 0x00 "ID_AA64MMFR2_EL1,Memory Model Feature Register 2"
bitfld.quad 0x00 16.--19. "VARANGE,Indicates support for a larger virtual address" "Not supported,?..."
bitfld.quad 0x00 12.--15. "IESB, Indicates whether an implicit Error Synchronization Barrier has been inserted" "Reserved,Supported,?..."
bitfld.quad 0x00 8.--11. "LSM,Indicates whether LDM and STM are supported" "Not supported,?..."
newline
bitfld.quad 0x00 4.--7. "UAO,User Access Override support" "Reserved,Supported,?..."
bitfld.quad 0x00 0.--3. "CNP,Common not Private support" "Reserved,Supported,?..."
endif
rgroup.quad spr:0x30054++0x00
line.quad 0x00 "ID_AA64AFR0_EL1,Auxiliary Feature Register 0"
rgroup.quad spr:0x30055++0x00
line.quad 0x00 "ID_AA64AFR1_EL1,Auxiliary Feature Register 1"
rgroup.quad spr:0x30010++0x00
line.quad 0x00 "ID_PFR0_EL1,AArch32 Processor Feature Register 0"
bitfld.quad 0x00 28.--31. "RAS,RAS extension version" "Reserved,Version 1,?..."
bitfld.quad 0x00 16.--19. "CSV2,Speculative use of faulting data" "Not disclosed,?..."
newline
bitfld.quad 0x00 12.--15. "STATE3,Thumb Execution Environment (Thumb-EE) Support" "Not supported,?..."
bitfld.quad 0x00 8.--11. "STATE2,Support for Jazelle extension" "Reserved,Trivial,?..."
bitfld.quad 0x00 4.--7. "STATE1,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,After Thumb-2,?..."
newline
bitfld.quad 0x00 0.--3. "STATE0,ARM Instruction Set Support" "Reserved,Supported,?..."
if (CORENAME()=="CORTEXA75")
rgroup.quad spr:0x30011++0x00
line.quad 0x00 "ID_PFR1_EL1,AArch32 Processor Feature Register 1"
bitfld.quad 0x00 28.--31. "GIC_CPU,GIC CPU Support" "Disabled,Enabled,?..."
bitfld.quad 0x00 24.--27. "VF,Virtualization fractional Support - Supported features from the ARMv7 Virtualization Extensions" "Not supported,?..."
bitfld.quad 0x00 20.--23. "SF,Security fractional Support - Supported features from the ARMv7 Security Extensions" "Not supported,?..."
newline
bitfld.quad 0x00 16.--19. "GT,Generic Timer Support" "Reserved,Supported,?..."
bitfld.quad 0x00 12.--15. "VE,Virtualization Extensions Support" "Reserved,Supported,?..."
bitfld.quad 0x00 8.--11. "MPM,Microcontroller Programmer's Model Support" "Not supported,?..."
newline
bitfld.quad 0x00 4.--7. "SE,Security Extensions Architecture v1 Support" "Reserved,Supported,?..."
bitfld.quad 0x00 0.--3. "PM,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..."
elif (CORENAME()=="CORTEXA55")
rgroup.quad spr:0x30011++0x00
line.quad 0x00 "ID_PFR1_EL1,AArch32 Processor Feature Register 1"
bitfld.quad 0x00 28.--31. "GIC_CPU,GIC CPU Support" "Disabled,Enabled,?..."
newline
bitfld.quad 0x00 16.--19. "GT,Generic Timer Support" "Reserved,Supported,?..."
bitfld.quad 0x00 12.--15. "VE,Virtualization Extensions Support" "Reserved,Supported,?..."
bitfld.quad 0x00 8.--11. "MPM,Microcontroller Programmer's Model Support" "Not supported,?..."
newline
bitfld.quad 0x00 4.--7. "SE,Security Extensions Architecture v1 Support" "Reserved,Supported,?..."
bitfld.quad 0x00 0.--3. "PM,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..."
endif
if (CORENAME()=="CORTEXA75")
rgroup.quad spr:0x30034++0x00
line.quad 0x00 "ID_PFR2_EL1,AArch32 Processor Feature Register 2"
bitfld.quad 0x00 0.--3. "CSV3,Speculative use of faulting data" "Reserved,Forbidden,?..."
elif (CORENAME()=="CORTEXA55")
rgroup.quad spr:0x30034++0x00
line.quad 0x00 "ID_PFR2_EL1,AArch32 Processor Feature Register 2"
bitfld.quad 0x00 4.--7. "SSBS,Speculative Store Bypassing Safe (SSBS) mechanism support" "Reserved,Supported,?..."
bitfld.quad 0x00 0.--3. "CSV3,Speculative use of faulting data" "Reserved,Cannot be used,?..."
endif
rgroup.quad spr:0x30013++0x00
line.quad 0x00 "ID_AFR0_EL1,AArch32 Auxiliary Feature Register 0"
rgroup.quad spr:0x30014++0x00
line.quad 0x00 "ID_MMFR0_EL1,Memory Model Feature Register 0"
bitfld.quad 0x00 28.--31. "IS,Indicates innermost shareability domain implemented" "Reserved,HW coherency,?..."
bitfld.quad 0x00 24.--27. "FCSE,Fast Context Switch Memory Mappings Support" "Not supported,?..."
bitfld.quad 0x00 20.--23. "AR,Auxiliary Register Support" "Reserved,Reserved,Control/Fault Status,?..."
newline
bitfld.quad 0x00 16.--19. "TCM,TCM and Associated DMA Support" "Not supported,?..."
bitfld.quad 0x00 12.--15. "SL,Shareability levels" "Reserved,Implemented 2 levels,?..."
bitfld.quad 0x00 8.--11. "OSS,Outer Shareable Support" "Reserved,HW coherency,?..."
newline
bitfld.quad 0x00 4.--7. "PMSA,Physical Memory System Architecture (PMSA) Support" "Not supported,?..."
bitfld.quad 0x00 0.--3. "VMSA,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,VMSAv7/PXN/L-DESC,?..."
rgroup.quad spr:0x30015++0x00
line.quad 0x00 "ID_MMFR1_EL1,Memory Model Feature Register 1"
bitfld.quad 0x00 28.--31. "BTB,Branch Predictor" "Reserved,Reserved,Reserved,Reserved,No flushing,?..."
bitfld.quad 0x00 24.--27. "L1TCO,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..."
bitfld.quad 0x00 20.--23. "L1UCMO,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..."
newline
bitfld.quad 0x00 16.--19. "L1HCMO,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Not supported,?..."
bitfld.quad 0x00 12.--15. "L1UCLMOSW,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..."
bitfld.quad 0x00 8.--11. "L1HCLMOSW,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Not supported,?..."
newline
bitfld.quad 0x00 4.--7. "L1UCLMOMVA,L1 Cache Line Maintenance Operations by VA/Unified Architecture Support" "Not supported,?..."
bitfld.quad 0x00 0.--3. "L1HCLMOMVA,L1 Cache Line Maintenance Operations by VA/Harvard Architecture" "Not supported,?..."
rgroup.quad spr:0x30016++0x00
line.quad 0x00 "ID_MMFR2_EL1,Memory Model Feature Register 2"
bitfld.quad 0x00 28.--31. "HAF,Hardware Access Flag Support" "Not supported,?..."
bitfld.quad 0x00 24.--27. "WFI,Wait for Interrupt Stalling Support" "Reserved,Supported,?..."
bitfld.quad 0x00 20.--23. "MBF,Memory Barrier Operations Support" "Reserved,Reserved,DSB/ISB/DMB,?..."
newline
bitfld.quad 0x00 16.--19. "UTLBMO,TLB Maintenance Operations/Unified Architecture Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,S2 operations,?..."
bitfld.quad 0x00 12.--15. "HTLBMO,TLB Maintenance Operations/Harvard Architecture Support" "Not supported,?..."
bitfld.quad 0x00 8.--11. "HL1CMRO,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..."
newline
bitfld.quad 0x00 4.--7. "HL1BPCRO,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
bitfld.quad 0x00 0.--3. "HL1FPCRO,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
rgroup.quad spr:0x30017++0x00
line.quad 0x00 "ID_MMFR3_EL1,AArch32 Memory Model Feature Register 3"
bitfld.quad 0x00 28.--31. "SS,Supersection support" "Supported,?..."
bitfld.quad 0x00 24.--27. "CMEMSZ,Cache memory size" "Reserved,Reserved,1TByte,?..."
bitfld.quad 0x00 20.--23. "CW,Indicates whether translation table updates require a clean to the point of unification" "Reserved,Not required,?..."
newline
bitfld.quad 0x00 16.--19. "PAN,Privileged Access Never Support" "Reserved,Reserved,Extended,?..."
bitfld.quad 0x00 12.--15. "MB,Maintenance broadcast Support" "Reserved,Reserved,Shareability/Defined behavior,?..."
bitfld.quad 0x00 8.--11. "BPM,Invalidate Branch predictor Support" "Reserved,Reserved,Invalidate All/VA,?..."
newline
bitfld.quad 0x00 4.--7. "CMSW,Cache maintenance by set/way" "Reserved,Supported,?..."
bitfld.quad 0x00 0.--3. "CMMVA,Cache maintenance by MVA" "Reserved,Supported,?..."
rgroup.quad spr:0x30026++0x00
line.quad 0x00 "ID_MMFR4_EL1,AArch32 Memory Model Feature Register 4"
bitfld.quad 0x00 20.--23. "LSM,LSMAOE and NTLSMD bits support" "Not supported,?..."
bitfld.quad 0x00 16.--19. "HD,Hierarchical Permission Disabled Support" "Reserved,Reserved,Extended,?..."
bitfld.quad 0x00 12.--15. "CNP,Common not Private support" "Reserved,Supported,?..."
newline
bitfld.quad 0x00 8.--11. "XNX,EL0/EL1 execute control distinction at stage2 bit support" "Not supported,Supported,?..."
bitfld.quad 0x00 4.--7. "AC2,Indicates the extension of the HACTLR register using HACTLR2" "Reserved,Supported,?..."
bitfld.quad 0x00 0.--3. "SPECSEI,Describes whether the PE can generate SError interrupt exceptions" "Not possible,?..."
rgroup.quad spr:0x30020++0x00
line.quad 0x00 "ID_ISAR0_EL1,AArch32 Instruction Set Attribute Register 0"
bitfld.quad 0x00 24.--27. "DIVI,Divide Instructions Support" "Reserved,Reserved,T32/A32,?..."
bitfld.quad 0x00 20.--23. "DEBI,Debug Instructions Support" "Reserved,Supported,?..."
bitfld.quad 0x00 16.--19. "CI,Coprocessor Instructions Support" "Not supported,?..."
newline
bitfld.quad 0x00 12.--15. "CBI,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..."
bitfld.quad 0x00 8.--11. "BI,Bitfield Instructions Support" "Reserved,Supported,?..."
bitfld.quad 0x00 4.--7. "BCI,Bit Counting Instructions Support" "Reserved,Supported,?..."
newline
bitfld.quad 0x00 0.--3. "SI,Swap Instructions Support" "Not supported,?..."
rgroup.quad spr:0x30021++0x00
line.quad 0x00 "ID_ISAR1_EL1,AArch32 Instruction Set Attribute Register 1"
bitfld.quad 0x00 28.--31. "JI,Jazelle Instructions Support" "Reserved,Supported,?..."
bitfld.quad 0x00 24.--27. "INTI,Interwork Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.quad 0x00 20.--23. "IMMI,Immediate Instructions Support" "Reserved,Supported,?..."
newline
bitfld.quad 0x00 16.--19. "ITEI,If Then Instructions Support" "Reserved,Supported,?..."
bitfld.quad 0x00 12.--15. "EXTI,Extend Instructions Support" "Reserved,Reserved,Full support,?..."
bitfld.quad 0x00 8.--11. "EARI,Exception A and R Instructions Support" "Reserved,Supported,?..."
newline
bitfld.quad 0x00 4.--7. "EXIN,Exception in ARM Instructions Support" "Reserved,Supported,?..."
bitfld.quad 0x00 0.--3. "ENDI,Endian Instructions Support" "Reserved,Supported,?..."
rgroup.quad spr:0x30022++0x00
line.quad 0x00 "ID_ISAR2_EL1,AArch32 Instruction Set Attribute Register 2"
bitfld.quad 0x00 28.--31. "RI,Reversal Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.quad 0x00 24.--27. "PSRI,PSR Instructions Support" "Not supported,Supported,?..."
bitfld.quad 0x00 20.--23. "UMI,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,UMAAL,?..."
newline
bitfld.quad 0x00 16.--19. "SMI,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
newline
bitfld.quad 0x00 12.--15. "MI,Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.quad 0x00 8.--11. "II,Multi-Access Interruptible Instructions Support" "Not supported,?..."
newline
bitfld.quad 0x00 4.--7. "MHI,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Reserved,PLD/PLI/PLDW,?..."
newline
bitfld.quad 0x00 0.--3. "LSI,Load and Store Instructions Support" "Reserved,Reserved,Supported,?..."
rgroup.quad spr:0x30023++0x00
line.quad 0x00 "ID_ISAR3_EL1, AArch32 Instruction Set Attribute Register 3"
bitfld.quad 0x00 28.--31. "TEEEI,Thumb-EE Extensions Support" "Not supported,?..."
bitfld.quad 0x00 24.--27. "NOPI,True NOP Instructions Support" "Reserved,Supported,?..."
bitfld.quad 0x00 20.--23. "TCI,Thumb Copy Instructions Support" "Reserved,Supported,?..."
newline
bitfld.quad 0x00 16.--19. "TBI,Table Branch Instructions Support" "Reserved,Supported,?..."
newline
bitfld.quad 0x00 12.--15. "SPI,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..."
newline
bitfld.quad 0x00 8.--11. "SVCI,SVC Instructions Support" "Reserved,Supported,?..."
bitfld.quad 0x00 4.--7. "SIMDI,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.quad 0x00 0.--3. "SI,Saturate Instructions Support" "Reserved,Supported,?..."
rgroup.quad spr:0x30024++0x00
line.quad 0x00 "ID_ISAR4_EL1, AArch32 Instruction Set Attribute Register 4"
bitfld.quad 0x00 28.--31. "SWP_FRAC,Memory System Locking Support" "Not supported,?..."
bitfld.quad 0x00 24.--27. "PSR_M_I,PSR_M Instructions Support" "Not supported,?..."
bitfld.quad 0x00 20.--23. "SPRI,Synchronization Primitive instructions" "Supported,?..."
newline
bitfld.quad 0x00 16.--19. "BI,Barrier Instructions Support" "Reserved,Supported,?..."
bitfld.quad 0x00 12.--15. "SMCI,SMC Instructions Support" "Reserved,Supported,?..."
bitfld.quad 0x00 8.--11. "WBI,Write-Back Instructions Support" "Reserved,Supported,?..."
newline
bitfld.quad 0x00 4.--7. "WSI,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
bitfld.quad 0x00 0.--3. "UI,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..."
rgroup.quad spr:0x30025++0x00
line.quad 0x00 "ID_ISAR5_EL1,AArch32 Instruction Set Attribute Register 5"
bitfld.quad 0x00 24.--27. "RDM,Rounding Double Multiply Add/Subtract instructions Support" "Reserved,Supported,?..."
bitfld.quad 0x00 16.--19. "CRC32,CRC32 Instructions Support" "Reserved,Supported,?..."
bitfld.quad 0x00 12.--15. "SHA2,SHA2 Instructions Support" "Not supported,Supported,?..."
newline
bitfld.quad 0x00 8.--11. "SHA1,SHA1 Instructions Support" "Not supported,Supported,?..."
bitfld.quad 0x00 4.--7. "AES,AES Instructions Support" "Not supported,Reserved,Supported,?..."
bitfld.quad 0x00 0.--3. "SEVL,   SEVL Instructions Support" "Reserved,Supported,?..."
rgroup.quad spr:0x30027++0x00
line.quad 0x00 "ID_ISAR6_EL1,AArch32 Instruction Set Attribute Register 6"
bitfld.quad 0x00 4.--7. "DP,UDOT and SDOT instructions support" "Reserved,Supported,?..."
rgroup.quad spr:0x33001++0x00
line.quad 0x00 "CTR_EL0,Cache Type Register"
bitfld.quad 0x0 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
bitfld.quad 0x0 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
newline
bitfld.quad 0x0 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
bitfld.quad 0x0 14.--15. "VIPT,L1 Instruction cache policy" "Reserved,Reserved,VIPT,?..."
newline
bitfld.quad 0x0 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
rgroup.quad spr:0x30005++0x00
line.quad 0x00 "MPIDR_EL1,MPIDR_EL1"
hexmask.quad.byte 0x00 32.--39. 1. "AFF3,Affinity level 3. Highest level affinity field"
bitfld.quad 0x00 30. "U,Uniprocessor" "Multiprocessor,?..."
bitfld.quad 0x00 24. "MT,Indicates whether the lowest level of affinity consists of logical processors that are implemented using a multi-threading type approach" "Reserved,Very inter"
newline
hexmask.quad.byte 0x00 16.--23. 1. "AFF2,Affinity level 2. Second highest level affinity field"
bitfld.quad 0x00 8.--10. "AFF1,Third highest level affinity field/Identification number for each CPU in cluster" "CPUID0,CPUID1,CPUID2,CPUID3,CPUID4,CPUID5,CPUID6,CPUID7"
hexmask.quad.byte 0x00 0.--7. 1. "AFF0,Affinity level 0. The level identifies individual threads within a multi-threaded core"
rgroup.quad spr:0x30006++0x00
line.quad 0x00 "REVIDR_EL1,Revision ID register"
rgroup.quad spr:0x33007++0x00
line.quad 0x00 "DCZID_EL0,DCZID_EL0"
bitfld.quad 0x00 4. "DZP,Data Zero prohibited" "Permitted,Prohibited"
bitfld.quad 0x00 0.--3. "BLOCK,Log2 of the block size in words" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
rgroup.quad spr:0x31007++0x00
line.quad 0x00 "AIDR_EL1,Auxiliary ID Register EL1"
group.quad spr:0x34000++0x00
line.quad 0x00 "VPIDR_EL2,Virtualization Processor ID register"
hexmask.quad.byte 0x0 24.--31. 1. "IMPL,Implementer code"
bitfld.quad 0x00 20.--23. "VAR,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 16.--19. "ARCH, Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,CPUID scheme"
newline
hexmask.quad.word 0x00 4.--15. 1. "PART,Primary Part Number"
bitfld.quad 0x00 0.--3. "REV,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.quad spr:0x34005++0x00
line.quad 0x00 "VMPIDR_EL2,Virtualization Multiprocessor ID registers"
hexmask.quad.byte 0x00 32.--39. 1. "AFF3,Affinity level 3. Highest level affinity field"
bitfld.quad 0x00 30. "U,Uniprocessor" "Multiprocessor,?..."
bitfld.quad 0x00 24. "MT,Indicates whether the lowest level of affinity consists of logical processors that are implemented using a multi-threading type approach" "Reserved,Very interdependent"
newline
hexmask.quad.byte 0x00 16.--23. 1. "AFF2,Affinity level 2. Second highest level affinity field"
bitfld.quad 0x00 8.--11. "AFF1,Third highest level affinity field/Identification number for each CPU in cluster" "CPUID0,CPUID1,CPUID2,CPUID3,CPUID4,CPUID5,CPUID6,CPUID7,?..."
hexmask.quad.byte 0x00 0.--7. 1. "AFF0,Affinity level 0. The level identifies individual threads within a multi-threaded core"
tree.end
tree "System Control and Configuration"
group.quad spr:0x36111++0x00
line.quad 0x00 "SDER32_EL3,Secure Debug Enable Register"
bitfld.quad 0x00 1. "SUNIDEN,Enable non-invasive debug features in Secure User mode" "Disabled,Enabled"
bitfld.quad 0x00 0. "SUIDEN,Enable debug exceptions in Secure User mode" "Disabled,Enabled"
if (CORENAME()=="CORTEXA75")
group.quad spr:0x30100++0x00
line.quad 0x00 "SCTLR_EL1,System Control Register EL1"
bitfld.quad 0x00 26. "UCI,EL0 access in AArch64 for DC CVAU/ DC CIVAC/ DC CVAC and IC IVAU instructions enable" "Disabled,Enabled"
bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big"
newline
bitfld.quad 0x00 24. "E0E,Endianness of explicit data accesses at EL0" "Little,Big"
bitfld.quad 0x00 23. "SPAN,Set PSTATE.PAN bit on taking an exception to the EL1 exception level" "Reserved,Unchanged"
newline
bitfld.quad 0x00 21. "IESB,Implicit Error Synchronization Barrier enable" "Disabled,Enabled"
bitfld.quad 0x00 19. "WXN,Write permission implies XN (Execute Never)" "Not forced,Forced"
newline
bitfld.quad 0x00 18. "NTWE,WFE instruction executed at EL0" "Executed,Not executed"
bitfld.quad 0x00 16. "NTWI,WFI instruction executed at EL0" "Executed,Not executed"
newline
bitfld.quad 0x00 15. "UCT,EL0 access in AArch64 to the CTR_EL0 enable" "Disabled,Enabled"
bitfld.quad 0x00 14. "DZE,Access to DC ZVA instruction at EL0" "Prohibited,Allowed"
newline
bitfld.quad 0x00 12. "I,Instruction Cache enable" "Disabled,Enabled"
bitfld.quad 0x00 9. "UMA,User Mask Access. Controls access to interrupt masks from EL0, when EL0 is using AArch64" "Disabled,Enabled"
newline
bitfld.quad 0x00 8. "SED,SETEND instruction disable" "No,Yes"
bitfld.quad 0x00 7. "ITD,IT Disable" "No,"
newline
bitfld.quad 0x00 5. "CP15BEN,CP15 Barrier Enable" "Disabled,Enabled"
bitfld.quad 0x00 4. "SA0,Stack Alignment Check Enable for EL0" "Disabled,Enabled"
newline
bitfld.quad 0x00 3. "SA,Stack Alignment Check Enable" "Disabled,Enabled"
bitfld.quad 0x00 2. "C,Data/Unified Cache enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 1. "A,Alignment Check" "Low,High"
bitfld.quad 0x00 0. "M,MMU Enable" "Disabled,Enabled"
elif (CORENAME()=="CORTEXA55")
group.quad spr:0x30100++0x00
line.quad 0x00 "SCTLR_EL1,System Control Register EL1"
bitfld.quad 0x00 26. "UCI,EL0 access in AArch64 for DC CVAU/ DC CIVAC/ DC CVAC and IC IVAU instructions enable" "Disabled,Enabled"
bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big"
newline
bitfld.quad 0x00 24. "E0E,Endianness of explicit data accesses at EL0" "Little,Big"
bitfld.quad 0x00 23. "SPAN,Set PSTATE.PAN bit on taking an exception to the EL1 exception level" "Reserved,Unchanged"
newline
bitfld.quad 0x00 19. "WXN,Write permission implies XN (Execute Never)" "Not forced,Forced"
bitfld.quad 0x00 18. "NTWE,WFE instruction executed at EL0" "Executed,Not executed"
newline
bitfld.quad 0x00 16. "NTWI,WFI instruction executed at EL0" "Executed,Not executed"
bitfld.quad 0x00 15. "UCT,EL0 access in AArch64 to the CTR_EL0 enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 14. "DZE,Access to DC ZVA instruction at EL0" "Prohibited,Allowed"
bitfld.quad 0x00 12. "I,Instruction Cache enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 9. "UMA,User Mask Access. Controls access to interrupt masks from EL0, when EL0 is using AArch64" "Disabled,Enabled"
bitfld.quad 0x00 8. "SED,SETEND instruction disable" "No,Yes"
newline
bitfld.quad 0x00 5. "CP15BEN,CP15 Barrier Enable" "Disabled,Enabled"
bitfld.quad 0x00 4. "SA0,Stack Alignment Check Enable for EL0" "Disabled,Enabled"
newline
bitfld.quad 0x00 3. "SA,Stack Alignment Check Enable" "Disabled,Enabled"
bitfld.quad 0x00 2. "C,Data/Unified Cache enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 1. "A,Alignment Check" "Low,High"
bitfld.quad 0x00 0. "M,MMU Enable" "Disabled,Enabled"
endif
group.quad spr:0x35100++0x00
line.quad 0x00 "SCTLR_EL12,System Control Register EL12"
bitfld.quad 0x00 26. "UCI,EL0 access in AArch64 for DC CVAU/ DC CIVAC/ DC CVAC and IC IVAU instructions enable" "Disabled,Enabled"
bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big"
newline
bitfld.quad 0x00 24. "E0E,Endianness of explicit data accesses at EL0" "Little,Big"
bitfld.quad 0x00 23. "SPAN,Set PSTATE.PAN bit on taking an exception to the EL1 exception level" "Reserved,Unchanged"
newline
bitfld.quad 0x00 21. "IESB,Implicit Error Synchronization Barrier enable" "Disabled,Enabled"
bitfld.quad 0x00 19. "WXN,Write permission implies XN (Execute Never)" "Not forced,Forced"
newline
bitfld.quad 0x00 18. "NTWE,WFE instruction executed at EL0" "Executed,Not executed"
bitfld.quad 0x00 16. "NTWI,WFI instruction executed at EL0" "Executed,Not executed"
newline
bitfld.quad 0x00 15. "UCT,EL0 access in AArch64 to the CTR_EL0 enable" "Disabled,Enabled"
bitfld.quad 0x00 14. "DZE,Access to DC ZVA instruction at EL0" "Prohibited,Allowed"
newline
bitfld.quad 0x00 12. "I,Instruction Cache enable" "Disabled,Enabled"
bitfld.quad 0x00 9. "UMA,User Mask Access. Controls access to interrupt masks from EL0, when EL0 is using AArch64" "Disabled,Enabled"
newline
bitfld.quad 0x00 8. "SED,SETEND instruction disable" "No,Yes"
bitfld.quad 0x00 7. "ITD,IT Disable" "No,"
newline
bitfld.quad 0x00 5. "CP15BEN,CP15 Barrier Enable" "Disabled,Enabled"
bitfld.quad 0x00 4. "SA0,Stack Alignment Check Enable for EL0" "Disabled,Enabled"
newline
bitfld.quad 0x00 3. "SA,Stack Alignment Check Enable" "Disabled,Enabled"
bitfld.quad 0x00 2. "C,Data/Unified Cache enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 1. "A,Alignment Check" "Low,High"
bitfld.quad 0x00 0. "M,MMU Enable" "Disabled,Enabled"
group.quad spr:0x34100++0x00
line.quad 0x00 "SCTLR_EL2,System Control Register EL2"
bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big"
bitfld.quad 0x00 19. "WXN,Write permission implies XN (Execute Never)" "Not forced,Forced"
newline
bitfld.quad 0x00 12. "I,Instruction Cache enable" "Disabled,Enabled"
bitfld.quad 0x00 3. "SA,Stack Alignment Check Enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 2. "C,Data/Unified Cache enable" "Disabled,Enabled"
bitfld.quad 0x00 1. "A,Alignment Check" "Low,High"
newline
bitfld.quad 0x00 0. "M,MMU Enable" "Disabled,Enabled"
group.quad spr:0x36100++0x00
line.quad 0x00 "SCTLR_EL3,System Control Register EL3"
bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big"
bitfld.quad 0x00 21. "IESB,Implicit Error Synchronization Barrier enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 19. "WXN,Write permission implies XN (Execute Never)" "Not forced,Forced"
bitfld.quad 0x00 12. "I,Instruction Cache enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 3. "SA,Stack Alignment Check Enable" "Disabled,Enabled"
bitfld.quad 0x00 2. "C,Data/Unified Cache enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 1. "A,Alignment Check" "Low,High"
bitfld.quad 0x00 0. "M,MMU Enable" "Disabled,Enabled"
if (CORENAME()=="CORTEXA55")
group.quad spr:0x30F70++0x00
line.quad 0x00 "ATCR_EL1,CPU Auxiliary Control Register"
bitfld.quad 0x00 13. "HWVAL160,Indicates the value of PBHA[1] on page table walks memory access targeting the base address defined by TTB1 if HWEN160 is set" "0,1"
bitfld.quad 0x00 12. "HWVAL159,Indicates the value of PBHA[0] on page table walks memory access targeting the base address defined by TTB1 if HWEN159 is set" "0,1"
newline
bitfld.quad 0x00 9. "HWVAL060,Indicates the value of PBHA[1] on page table walks memory access targeting the base address defined by TTB0 if HWEN060 is set" "0,1"
bitfld.quad 0x00 8. "HWVAL059,Indicates the value of PBHA[1] on page table walks memory access targeting the base address defined by TTB0 if HWEN059 is set" "0,1"
newline
bitfld.quad 0x00 5. "HWEN160,Enables PBHA[1] page table walks memory access targeting the base address defined by TTB1" "Disabled,Enabled"
bitfld.quad 0x00 4. "HWEN159,Enables PBHA[0] page table walks memory access targeting the base address defined by TTB1" "Disabled,Enabled"
newline
bitfld.quad 0x00 1. "HWEN060,Enables PBHA[1] page table walks memory access targeting the base address defined by TTB0" "Disabled,Enabled"
bitfld.quad 0x00 0. "HWEN059,Enables PBHA[0] page table walks memory access targeting the base address defined by TTB0" "Disabled,Enabled"
group.quad spr:0x35F70++0x00
line.quad 0x00 "ATCR_EL12,CPU Auxiliary Control Register"
bitfld.quad 0x00 13. "HWVAL160,Indicates the value of PBHA[1] on page table walks memory access targeting the base address defined by TTB1 if HWEN160 is set" "0,1"
bitfld.quad 0x00 12. "HWVAL159,Indicates the value of PBHA[0] on page table walks memory access targeting the base address defined by TTB1 if HWEN159 is set" "0,1"
newline
bitfld.quad 0x00 9. "HWVAL060,Indicates the value of PBHA[1] on page table walks memory access targeting the base address defined by TTB0 if HWEN060 is set" "0,1"
bitfld.quad 0x00 8. "HWVAL059,Indicates the value of PBHA[1] on page table walks memory access targeting the base address defined by TTB0 if HWEN059 is set" "0,1"
newline
bitfld.quad 0x00 5. "HWEN160,Enables PBHA[1] page table walks memory access targeting the base address defined by TTB1" "Disabled,Enabled"
bitfld.quad 0x00 4. "HWEN159,Enables PBHA[0] page table walks memory access targeting the base address defined by TTB1" "Disabled,Enabled"
newline
bitfld.quad 0x00 1. "HWEN060,Enables PBHA[1] page table walks memory access targeting the base address defined by TTB0" "Disabled,Enabled"
bitfld.quad 0x00 0. "HWEN059,Enables PBHA[0] page table walks memory access targeting the base address defined by TTB0" "Disabled,Enabled"
group.quad spr:0x34F70++0x00
line.quad 0x00 "ATCR_EL2,CPU Auxiliary Control Register"
bitfld.quad 0x00 13. "HWVAL160,Indicates the value of PBHA[1] on page table walks memory access targeting the base address defined by TTB1 if HWEN160 is set" "0,1"
bitfld.quad 0x00 12. "HWVAL159,Indicates the value of PBHA[0] on page table walks memory access targeting the base address defined by TTB1 if HWEN159 is set" "0,1"
newline
bitfld.quad 0x00 9. "HWVAL060,Indicates the value of PBHA[1] on page table walks memory access targeting the base address defined by TTB0 if HWEN060 is set" "0,1"
bitfld.quad 0x00 8. "HWVAL059,Indicates the value of PBHA[1] on page table walks memory access targeting the base address defined by TTB0 if HWEN059 is set" "0,1"
newline
bitfld.quad 0x00 5. "HWEN160,Enables PBHA[1] page table walks memory access targeting the base address defined by TTB1" "Disabled,Enabled"
bitfld.quad 0x00 4. "HWEN159,Enables PBHA[0] page table walks memory access targeting the base address defined by TTB1" "Disabled,Enabled"
newline
bitfld.quad 0x00 1. "HWEN060,Enables PBHA[1] page table walks memory access targeting the base address defined by TTB0" "Disabled,Enabled"
bitfld.quad 0x00 0. "HWEN059,Enables PBHA[0] page table walks memory access targeting the base address defined by TTB0" "Disabled,Enabled"
group.quad spr:0x36F70++0x00
line.quad 0x00 "ATCR_EL3,CPU Auxiliary Control Register"
bitfld.quad 0x00 9. "HWVAL060,Indicates the value of PBHA[1] on page table walks memory access targeting the base address defined by TTB0 if HWEN060 is set" "0,1"
bitfld.quad 0x00 8. "HWVAL059,Indicates the value of PBHA[1] on page table walks memory access targeting the base address defined by TTB0 if HWEN059 is set" "0,1"
newline
bitfld.quad 0x00 1. "HWEN060,Enables PBHA[1] page table walks memory access targeting the base address defined by TTB0" "Disabled,Enabled"
bitfld.quad 0x00 0. "HWEN059,Enables PBHA[0] page table walks memory access targeting the base address defined by TTB0" "Disabled,Enabled"
group.quad spr:0x34F71++0x00
line.quad 0x00 "AVTCR_EL2,CPU Auxiliary Control Register"
bitfld.quad 0x00 9. "HWVAL060,Indicates the value of PBHA[1] on page table walks memory access targeting the base address defined by TTB0 if HWEN060 is set" "0,1"
bitfld.quad 0x00 8. "HWVAL059,Indicates the value of PBHA[1] on page table walks memory access targeting the base address defined by TTB0 if HWEN059 is set" "0,1"
newline
bitfld.quad 0x00 1. "HWEN060,Enables PBHA[1] page table walks memory access targeting the base address defined by TTB0" "Disabled,Enabled"
bitfld.quad 0x00 0. "HWEN059,Enables PBHA[0] page table walks memory access targeting the base address defined by TTB0" "Disabled,Enabled"
endif
group.quad spr:0x30F10++0x00
line.quad 0x00 "CPUACTLR_EL1,CPU Auxiliary Control Register"
if (CORENAME()=="CORTEXA75")
group.quad spr:0x30F11++0x00
line.quad 0x00 "CPUACTLR2_EL1,CPU Auxiliary Control Register 2"
group.quad spr:0x30F14++0x00
line.quad 0x00 "CPUECTLR_EL1,CPU Extended Control Register"
bitfld.quad 0x00 63. "GBPP,Branch prediction structure invalidation" "0,1"
bitfld.quad 0x00 22.--23. "L4_STREAM,Threshold for direct stream to L4 cache on store" "512KB,1024KB,2048KB,Disabled"
newline
bitfld.quad 0x00 20.--21. "L3_STREAM,Threshold for direct stream to L3 cache on store" "64KB,256KB,512KB,Disabled"
bitfld.quad 0x00 18.--19. "L2_STREAM,Threshold for direct stream to L2 cache on store" "16KB,64KB,128KB,Disabled"
newline
bitfld.quad 0x00 10. "L3PF,Enable L3 prefetch requests sent by the stride prefetcher" "Disabled,Enabled"
bitfld.quad 0x00 9. "L2PF,Enable L2 prefetch requests sent by the stride prefetcher" "Disabled,Enabled"
newline
bitfld.quad 0x00 8. "L1PF,Enable L1 prefetch requests sent by the stride prefetcher" "Disabled,Enabled"
bitfld.quad 0x00 7. "RPF,Enable L2 region prefetch requests" "Disabled,Enabled"
newline
bitfld.quad 0x00 6. "MMUPF,Enable MMU prefetch requests" "Disabled,Enabled"
bitfld.quad 0x00 5. "RPF_AGGRO,L2 region prefetcher aggressivity" "Less,More"
newline
bitfld.quad 0x00 1. "RNSD_EXCL,Enables signaling of cacheable Exclusive loads on the internal interface between the core and the DSU" "Disabled,Enabled"
bitfld.quad 0x00 0. "EXTLLC,Type of last-level cache that is present in the system" "Internal,External"
elif (CORENAME()=="CORTEXA55")
group.quad spr:0x30F14++0x00
line.quad 0x00 "CPUECTLR_EL1,CPU Extended Control Register"
bitfld.quad 0x00 38.--39. "ATOM,Force most cacheable atomic instructions to be executed far in the L3 cache or beyond and near in the L1 cache" "Near - hit/unique | Far - miss/shared,Near,Far,Near - load | Far - store"
bitfld.quad 0x00 37. "L2FLUSH,L2 cache flush" "Enabled,Disabled"
newline
bitfld.quad 0x00 29.--30. "L3WSCTL,Write streaming no-L3-allocate threshold" "128th line,1024th line,4096th line,Disabled"
bitfld.quad 0x00 27.--28. "L2WSCTL,Write streaming no-L2-allocate threshold" "16th line,128th line,512th line,Disabled"
newline
bitfld.quad 0x00 25.--26. "L1WSCTL,Write streaming no-L1-allocate threshold" "4th line,64th line,128th line,Disabled"
bitfld.quad 0x00 13.--15. "L1PCTL,L1 Data prefetch control. Maximum number of outstanding data prefetches allowed in the L1 memory system" "Disabled,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 10.--12. "L3PCTL,L3 Data prefetch control. Maximum number of outstanding data prefetches allowed that can be sent to the L3 memory system" "16 lines,32 lines,Reserved,Reserved,Disabled,2 lines,4 lines,8 lines"
bitfld.quad 0x00 0. "EXTLLC,Indicates that an external Last-level cache is present in the system" "L3 cache,Present"
group.quad spr:0x36F81++0x00
line.quad 0x00 "CPUPCR_EL3,CPU Private Control Register"
group.quad spr:0x36F83++0x00
line.quad 0x00 "CPUPMR_EL3,CPU Private Mask Register"
group.quad spr:0x36F82++0x00
line.quad 0x00 "CPUPOR_EL3,CPU Private Operation Register"
group.quad spr:0x36F80++0x00
line.quad 0x00 "CPUPSELR_EL3,CPU Private Selection Register"
endif
group.quad spr:0x30101++0x00
line.quad 0x00 "ACTLR_EL1,Auxiliary Control register 1"
if (CORENAME()=="CORTEXA75")
group.quad spr:0x34101++0x00
line.quad 0x00 "ACTLR_EL2,Auxiliary Control register 2"
bitfld.quad 0x00 12. "CLUSTERPMUEN,Performance Management Registers write access control" "Not accessible,Accessible"
bitfld.quad 0x00 11. "SMEN,Scheme Management Registers write access control" "Not accessible,Accessible"
newline
bitfld.quad 0x00 10. "TSIDEN,Thread Scheme ID Register enable" "Not accessible,Accessible"
bitfld.quad 0x00 7. "PWREN,Power Control Registers access control" "Not accessible,Accessible"
newline
bitfld.quad 0x00 5. "ERXPFGEN,Error Record Registers write access control" "Not accessible,Accessible"
bitfld.quad 0x00 4. "AMEN,Activity Monitor enable" "Trapped,Not trapped"
newline
bitfld.quad 0x00 1. "ECTLREN,Extended Control Registers write access control" "Not accessible,Accessible"
bitfld.quad 0x00 0. "ACTLREN,Auxiliary Control Registers write access control" "Not accessible,Accessible"
group.quad spr:0x36101++0x00
line.quad 0x00 "ACTLR_EL3,Auxiliary Control register 3"
bitfld.quad 0x00 12. "CLUSTERPMUEN,Performance Management Registers write access control" "Not accessible,Accessible"
bitfld.quad 0x00 11. "SMEN,Scheme Management Registers write access control" "Not accessible,Accessible"
newline
bitfld.quad 0x00 7. "PWREN,Power Control Registers access control" "Not accessible,Accessible"
bitfld.quad 0x00 5. "ERXPFGEN,Error Record Registers write access control" "Not accessible,Accessible"
newline
bitfld.quad 0x00 4. "AMEN,Activity Monitor enable" "Trapped,Not trapped"
bitfld.quad 0x00 1. "ECTLREN,Extended Control Registers write access control" "Not accessible,Accessible"
newline
bitfld.quad 0x00 0. "ACTLREN,Auxiliary Control Registers write access control" "Not accessible,Accessible"
group.quad spr:0x30102++0x00
line.quad 0x00 "CPACR_EL1,Coprocessor Access Control Register 1"
bitfld.quad 0x00 28. "TTA,Traps EL0 and EL1 System register accesses to all implemented trace registers to EL1" "No trap,"
bitfld.quad 0x00 20.--21. "FPEN,Floating Point and Advanced SIMD execution to trap to EL1 when executed from EL0 or EL1" "EL0/EL1,EL0,EL0/EL1,No trap"
group.quad spr:0x35102++0x00
line.quad 0x00 "CPACR_EL12,Coprocessor Access Control Register 1"
bitfld.quad 0x00 28. "TTA,Traps EL0 and EL1 System register accesses to all implemented trace registers to EL1" "No trap,"
bitfld.quad 0x00 20.--21. "FPEN,Floating Point and Advanced SIMD execution to trap to EL1 when executed from EL0 or EL1" "EL0/EL1,EL0,EL0/EL1,No trap"
elif (CORENAME()=="CORTEXA55")
group.quad spr:0x34101++0x00
line.quad 0x00 "ACTLR_EL2,Auxiliary Control register 2"
bitfld.quad 0x00 12. "CLUSTERPMUEN,Performance Management Registers write access control" "Not accessible,Accessible"
bitfld.quad 0x00 11. "SMEN,Scheme Management Registers write access control" "Not accessible,Accessible"
newline
bitfld.quad 0x00 10. "TSIDEN,Thread Scheme ID Register enable" "Not accessible,Accessible"
bitfld.quad 0x00 7. "PWREN,Power Control Registers access control" "Not accessible,Accessible"
newline
bitfld.quad 0x00 5. "ERXPFGEN,Error Record Registers write access control" "Not accessible,Accessible"
bitfld.quad 0x00 1. "ECTLREN,Extended Control Registers write access control" "Not accessible,Accessible"
newline
bitfld.quad 0x00 0. "ACTLREN,Auxiliary Control Registers write access control" "Not accessible,Accessible"
group.quad spr:0x36101++0x00
line.quad 0x00 "ACTLR_EL3,Auxiliary Control register 3"
bitfld.quad 0x00 12. "CLUSTERPMUEN,Performance Management Registers write access control" "Not accessible,Accessible"
bitfld.quad 0x00 11. "SMEN,Scheme Management Registers write access control" "Not accessible,Accessible"
newline
bitfld.quad 0x00 10. "TSIDEN,Thread Scheme ID Register enable" "Not accessible,Accessible"
bitfld.quad 0x00 7. "PWREN,Power Control Registers access control" "Not accessible,Accessible"
newline
bitfld.quad 0x00 5. "ERXPFGEN,Error Record Registers write access control" "Not accessible,Accessible"
bitfld.quad 0x00 1. "ECTLREN,Extended Control Registers write access control" "Not accessible,Accessible"
newline
bitfld.quad 0x00 0. "ACTLREN,Auxiliary Control Registers write access control" "Not accessible,Accessible"
group.quad spr:0x30102++0x00
line.quad 0x00 "CPACR_EL1,Coprocessor Access Control Register 1"
bitfld.quad 0x00 20.--21. "FPEN,Floating Point and Advanced SIMD execution to trap to EL1 when executed from EL0 or EL1" "EL0/EL1,EL0,EL0/EL1,No trap"
group.quad spr:0x35102++0x00
line.quad 0x00 "CPACR_EL12,Coprocessor Access Control Register 1"
bitfld.quad 0x00 20.--21. "FPEN,Floating Point and Advanced SIMD execution to trap to EL1 when executed from EL0 or EL1" "EL0/EL1,EL0,EL0/EL1,No trap"
endif
group.quad spr:0x34112++0x00
line.quad 0x00 "CPTR_EL2,Coprocessor Access Control Register 2"
bitfld.quad 0x00 31. "TCPAC,Trap Coprocessor Access Control" "No trap,Trap"
bitfld.quad 0x00 10. "TFP,Trap Floating Point and Advanced SIMD execution" "No trap,Trap"
group.quad spr:0x36112++0x00
line.quad 0x00 "CPTR_EL3,Coprocessor Access Control Register 3"
bitfld.quad 0x00 31. "TCPAC,Trap Coprocessor Access Control" "No trap,Trap"
bitfld.quad 0x00 10. "TFP,Trap Floating Point and Advanced SIMD execution" "No trap,Trap"
group.quad spr:0x36110++0x00
line.quad 0x00 "SCR_EL3,Secure Configuration Register"
bitfld.quad 0x00 15. "TERR,Trap Error record accesses" "No Trap,Trap"
bitfld.quad 0x00 14. "TLOR,Trap access to the LOR Registers from Non-secure EL1 and EL2 to EL3" "No trap,Trap"
newline
bitfld.quad 0x00 13. "TWE,Trap WFE" "No trap,Trap"
bitfld.quad 0x00 12. "TWI,Trap WFI" "No trap,Trap"
newline
bitfld.quad 0x00 11. "ST,Enables Secure EL1 access to the CNTPS_TVAL_EL1 CNTPS_CTL_EL1 CNTPS_CVAL_EL1[63:0] registers" "Disabled,Enabled"
bitfld.quad 0x00 10. "RW,Register width control for lower exception levels" "AArch32,AArch64"
newline
bitfld.quad 0x00 9. "SIF,Secure Instruction Fetch" "Permitted,Not permitted"
bitfld.quad 0x00 8. "HCE,Hypervisor Call enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 7. "SMD,Secure Monitor Call disable at EL1, EL2, or EL3" "No,Yes"
bitfld.quad 0x00 3. "EA,External Abort exceptions handled in Abort mode or Monitor mode" "Abort,Monitor"
newline
bitfld.quad 0x00 2. "FIQ,FIQ exceptions handled in Abort mode or Monitor mode" "FIQ,Monitor"
bitfld.quad 0x00 1. "IRQ,IRQ exceptions handled in Abort mode or Monitor mode" "IRQ,Monitor"
newline
bitfld.quad 0x00 0. "NS,Secure mode " "Secure,Non-secure"
group.quad spr:0x34110++0x00
line.quad 0x00 "HCR_EL2,Hypervisor Configuration Register"
bitfld.quad 0x00 35. "TLOR,Trap access to the LOR Registers from Non-secure EL1 to EL2" "No trap,Trap"
bitfld.quad 0x00 34. "E2H,EL2 Host" "Disabled,Enabled"
newline
bitfld.quad 0x00 33. "ID,Stage 2 Instruction cache disable" "No,Yes"
bitfld.quad 0x00 32. "CD,Stage 2 Data cache disable" "No,Yes"
newline
bitfld.quad 0x00 31. "RW,Register width control for lower exception levels" "AArch32,EL1 is 64-bit"
bitfld.quad 0x00 30. "TRVM,Trap Read of Virtual Memory controls" "No trap,Trap"
newline
bitfld.quad 0x00 28. "TDZ,Trap DC ZVA instruction" "No trap,Trap"
bitfld.quad 0x00 27. "TGE,Trap General Exceptions has an enhanced role when EL2 is using AArch64" "No trap,Trap"
newline
bitfld.quad 0x00 26. "TVM,Trap Virtual Memory controls to EL2" "No trap,Trap"
bitfld.quad 0x00 25. "TTLB,Trap TLB maintenance instructions to EL2" "No trap,Trap"
newline
bitfld.quad 0x00 24. "TPU,Trap Cache maintenance instructions to Point of Unification to EL2" "No trap,Trap"
bitfld.quad 0x00 23. "TPC,Trap Data/Unified Cache maintenance instructions to Point of Coherency to EL2" "No trap,Trap"
newline
bitfld.quad 0x00 22. "TSW,Trap Data/Unified Cache maintenance instructions by Set/Way to EL2" "No trap,Trap"
bitfld.quad 0x00 21. "TACR,Trap Auxiliary Control Register" "No trap,Trap"
newline
bitfld.quad 0x00 20. "TIDCP,Trap Implementation Dependent functionality" "No trap,Trap"
bitfld.quad 0x00 19. "TSC,Trap SMC" "No trap,Trap"
newline
bitfld.quad 0x00 18. "TID3,Trap ID Group 3" "No trap,Trap"
bitfld.quad 0x00 17. "TID2,Trap ID Group 2" "No trap,Trap"
newline
bitfld.quad 0x00 16. "TID1,Trap ID Group 1" "No trap,Trap"
bitfld.quad 0x00 15. "TID0,Trap ID Group 0" "No trap,Trap"
newline
bitfld.quad 0x00 14. "TWE,Trap WFE" "No trap,Trap"
bitfld.quad 0x00 13. "TWI,Trap WFI" "No trap,Trap"
newline
bitfld.quad 0x00 12. "DC,Default Cacheable" "Disabled,Enabled"
bitfld.quad 0x00 10.--11. "BSU,Barrier Shareability upgrade. determines the minimum shareability domain that is applied to any barrier executed from EL1 or EL0" "No effect,Inner Shareable,Outer Shareable,Full System"
newline
bitfld.quad 0x00 9. "FB,Force broadcast" "Not forced,Forced"
bitfld.quad 0x00 8. "VSE,Virtual System Error/Asynchronous Abort:" "Not pending,Pending"
newline
bitfld.quad 0x00 7. "VI,Virtual IRQ Interrupt" "Not pending,Pending"
bitfld.quad 0x00 6. "VF,Virtual FIQ Interrupt" "Not pending,Pending"
newline
bitfld.quad 0x00 5. "AMO,Asynchronous abort and error interrupt routing" "Disabled,Enabled"
bitfld.quad 0x00 4. "IMO,Physical IRQ Routing" "Disabled,Enabled"
newline
bitfld.quad 0x00 3. "FMO,Physical FIQ Routing" "Disabled,Enabled"
bitfld.quad 0x00 2. "PTW,Protected Table Walk" "Disabled,Enabled"
newline
bitfld.quad 0x00 0. "VM,Second stage of Translation enable" "Disabled,Enabled"
group.quad spr:0x30510++0x00
line.quad 0x00 "AFSR0_EL1,Auxiliary Fault Status Registers"
group.quad spr:0x35510++0x00
line.quad 0x00 "AFSR0_EL12,Auxiliary Fault Status Registers"
group.quad spr:0x30511++0x00
line.quad 0x00 "AFSR1_EL1,Auxiliary Fault Status Registers"
group.quad spr:0x35511++0x00
line.quad 0x00 "AFSR1_EL12,Auxiliary Fault Status Registers"
group.quad spr:0x34510++0x00
line.quad 0x00 "AFSR0_EL2,Auxiliary Fault Status Registers"
group.quad spr:0x34511++0x00
line.quad 0x00 "AFSR1_EL2,Auxiliary Fault Status Registers"
group.quad spr:0x36510++0x00
line.quad 0x00 "AFSR0_EL3,Auxiliary Fault Status Registers"
group.quad spr:0x36511++0x00
line.quad 0x00 "AFSR1_EL3,Auxiliary Fault Status Registers"
tree.open "Exception Syndrome Registers"
if (((per.q(spr:0x30520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000))
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
elif (((per.q(spr:0x30520))&0xFC000000)==0x04000000)
if (((per.q(spr:0x30520))&0x1000000)==0x1000000)
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.quad 0x00 0. "TI,Trapped instruction" "WFI,WFE"
else
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
newline
bitfld.quad 0x00 0. "TI,Trapped instruction" "WFI,WFE"
endif
elif (((per.q(spr:0x30520))&0xFC000000)==(0x0C000000||0x14000000))
if (((per.q(spr:0x30520))&0x1000000)==0x1000000)
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.quad 0x00 17.--19. "OPC2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 14.--16. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
else
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
newline
bitfld.quad 0x00 17.--19. "OPC2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 14.--16. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
endif
elif (((per.q(spr:0x30520))&0xFC000000)==(0x10000000||0x30000000))
if (((per.q(spr:0x30520))&0x1000000)==0x1000000)
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.quad 0x00 16.--19. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 10.--14. "RT2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
else
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
newline
bitfld.quad 0x00 16.--19. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 10.--14. "RT2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
endif
elif (((per.q(spr:0x30520))&0xFC000000)==0x18000000)
if (((per.q(spr:0x30520))&0x1000000)==0x1000000)
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction"
bitfld.quad 0x00 5.--9. "RN,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved"
newline
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
else
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
newline
hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction"
bitfld.quad 0x00 5.--9. "RN,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved"
newline
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
endif
elif (((per.q(spr:0x30520))&0xFC000000)==0x1C000000)
if (((per.q(spr:0x30520))&0x1000000)==0x1000000)
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
else
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
endif
elif (((per.q(spr:0x30520))&0xFC000000)==(0x44000000||0x54000000))
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.quad.word 0x00 0.--15. 1. "IMM16,The value of the immediate field from the HVC or SVC instruction"
elif (((per.q(spr:0x30520))&0xFC000000)==0x60000000)
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 20.--21. "OP0,Op0 value from the issued instruction" "0,1,2,3"
bitfld.quad 0x00 17.--19. "OP2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 14.--16. "OP1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((per.q(spr:0x30520))&0xFC000000)==(0x80000000||0x84000000))
if (((per.q(spr:0x30520))&0x3F)==(0x10))
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 11.--12. "SET,Synchronous Error Type" "UER,UEO,UC,CE"
newline
bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.quad 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/L0/base register,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Sync. parity/ECC/L0,Sync. parity/ECC/L1,Sync. parity/ECC/L2,Sync. parity/ECC/L3,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..."
else
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
newline
bitfld.quad 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/L0/base register,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Sync. parity/ECC/L0,Sync. parity/ECC/L1,Sync. parity/ECC/L2,Sync. parity/ECC/L3,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..."
endif
elif (((per.q(spr:0x30520))&0xFD000000)==(0x91000000||0x95000000))
if (((per.q(spr:0x30520))&0x3F)==(0x10))
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
bitfld.quad 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword"
newline
bitfld.quad 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required"
bitfld.quad 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit"
bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes"
newline
bitfld.quad 0x00 11.--12. "SET,Synchronous Error Type" "UER,UEO,UC,CE"
newline
bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.quad 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/L0,Sync. parity/ECC/L1,Sync. parity/ECC/L2,Sync. parity/ECC/L3,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive/Atomic access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
else
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
bitfld.quad 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword"
newline
bitfld.quad 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required"
bitfld.quad 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit"
bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes"
newline
newline
bitfld.quad 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/L0,Sync. parity/ECC/L1,Sync. parity/ECC/L2,Sync. parity/ECC/L3,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive/Atomic access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
endif
elif (((per.q(spr:0x30520))&0xFD000000)==(0x90000000||0x94000000))
if (((per.q(spr:0x30520))&0x3F)==(0x10))
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
newline
newline
newline
bitfld.quad 0x00 11.--12. "SET,Synchronous Error Type" "UER,UEO,UC,CE"
newline
bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.quad 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/L0,Sync. parity/ECC/L1,Sync. parity/ECC/L2,Sync. parity/ECC/L3,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive/Atomic access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
else
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
newline
newline
newline
newline
bitfld.quad 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/L0,Sync. parity/ECC/L1,Sync. parity/ECC/L2,Sync. parity/ECC/L3,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive/Atomic access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
endif
elif (((per.q(spr:0x30520))&0xFC800000)==(0xA0800000||0xB0800000))
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred"
bitfld.quad 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.quad 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred"
bitfld.quad 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.quad 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred"
bitfld.quad 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred"
elif (((per.q(spr:0x30520))&0xFC800000)==(0xA0000000||0xB0000000))
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
elif (((per.q(spr:0x30520))&0xFD000000)==0xBD000000)
if (((per.q(spr:0x30520))&0x3F)==0x11)
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "IDS,Implementation defined syndrome" "Not hold,Hold"
bitfld.quad 0x00 13. "IESB,Implicit Error Synchronization Barrier" "Not synchronized,Synchronized"
newline
bitfld.quad 0x00 10.--12. "AET,Asynchronous Error Type" "UC,UEU,UEO,UER,CE,?..."
bitfld.quad 0x00 9. "EA,External abort type" "No,Yes"
newline
bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Uncategorized,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous,?..."
else
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "IDS,Implementation defined syndrome" "Not hold,Hold"
bitfld.quad 0x00 9. "EA,External abort type" "No,Yes"
newline
bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Uncategorized,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous,?..."
endif
elif (((per.q(spr:0x30520))&0xFD000000)==0xBC000000)
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "IDS,Implementation defined syndrome" "Not hold,Hold"
elif (((per.q(spr:0x30520))&0xFC000000)==(0xC0000000||0xC4000000))
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,Debug exception,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
elif (((per.q(spr:0x30520))&0xFC000000)==(0xC8000000||0xCC000000))
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,EX bit valid" "Not valid,Valid"
bitfld.quad 0x00 6. "EX,Exclusive operation" "No,Yes"
newline
bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,Debug exception,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
elif (((per.q(spr:0x30520))&0xFC000000)==(0xD0000000||0xD4000000))
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 8. "CM,Data came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write"
newline
bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,?..."
elif (((per.q(spr:0x30520))&0xFC000000)==(0xE0000000||0xF0000000))
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.quad.word 0x00 0.--15. 1. "COMMENT,Set to the instruction comment field value"
else
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
endif
if (((per.q(spr:0x35520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000))
group.quad spr:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
elif (((per.q(spr:0x35520))&0xFC000000)==0x04000000)
if (((per.q(spr:0x35520))&0x1000000)==0x1000000)
group.quad spr:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.quad 0x00 0. "TI,Trapped instruction" "WFI,WFE"
else
group.quad spr:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
newline
bitfld.quad 0x00 0. "TI,Trapped instruction" "WFI,WFE"
endif
elif (((per.q(spr:0x35520))&0xFC000000)==(0x0C000000||0x14000000))
if (((per.q(spr:0x35520))&0x1000000)==0x1000000)
group.quad spr:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.quad 0x00 17.--19. "OPC2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 14.--16. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
else
group.quad spr:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
newline
bitfld.quad 0x00 17.--19. "OPC2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 14.--16. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
endif
elif (((per.q(spr:0x35520))&0xFC000000)==(0x10000000||0x30000000))
if (((per.q(spr:0x35520))&0x1000000)==0x1000000)
group.quad spr:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.quad 0x00 16.--19. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 10.--14. "RT2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
else
group.quad spr:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
newline
bitfld.quad 0x00 16.--19. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 10.--14. "RT2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
endif
elif (((per.q(spr:0x35520))&0xFC000000)==0x18000000)
if (((per.q(spr:0x35520))&0x1000000)==0x1000000)
group.quad spr:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction"
bitfld.quad 0x00 5.--9. "RN,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved"
newline
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
else
group.quad spr:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
newline
hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction"
bitfld.quad 0x00 5.--9. "RN,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved"
newline
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
endif
elif (((per.q(spr:0x35520))&0xFC000000)==0x1C000000)
if (((per.q(spr:0x35520))&0x1000000)==0x1000000)
group.quad spr:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
else
group.quad spr:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
endif
elif (((per.q(spr:0x35520))&0xFC000000)==(0x44000000||0x54000000))
group.quad spr:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.quad.word 0x00 0.--15. 1. "IMM16,The value of the immediate field from the HVC or SVC instruction"
elif (((per.q(spr:0x35520))&0xFC000000)==0x60000000)
group.quad spr:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 20.--21. "OP0,Op0 value from the issued instruction" "0,1,2,3"
bitfld.quad 0x00 17.--19. "OP2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 14.--16. "OP1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((per.q(spr:0x35520))&0xFC000000)==(0x80000000||0x84000000))
if (((per.q(spr:0x35520))&0x3F)==(0x10))
group.quad spr:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 11.--12. "SET,Synchronous Error Type" "UER,UEO,UC,CE"
newline
bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.quad 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/L0/base register,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Sync. parity/ECC/L0,Sync. parity/ECC/L1,Sync. parity/ECC/L2,Sync. parity/ECC/L3,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..."
else
group.quad spr:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
newline
bitfld.quad 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/L0/base register,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Sync. parity/ECC/L0,Sync. parity/ECC/L1,Sync. parity/ECC/L2,Sync. parity/ECC/L3,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..."
endif
elif (((per.q(spr:0x35520))&0xFD000000)==(0x91000000||0x95000000))
if (((per.q(spr:0x35520))&0x3F)==(0x10))
group.quad spr:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
bitfld.quad 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword"
newline
bitfld.quad 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required"
bitfld.quad 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit"
bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes"
newline
bitfld.quad 0x00 11.--12. "SET,Synchronous Error Type" "UER,UEO,UC,CE"
newline
bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.quad 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/L0,Sync. parity/ECC/L1,Sync. parity/ECC/L2,Sync. parity/ECC/L3,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive/Atomic access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
else
group.quad spr:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
bitfld.quad 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword"
newline
bitfld.quad 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required"
bitfld.quad 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit"
bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes"
newline
newline
bitfld.quad 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/L0,Sync. parity/ECC/L1,Sync. parity/ECC/L2,Sync. parity/ECC/L3,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive/Atomic access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
endif
elif (((per.q(spr:0x35520))&0xFD000000)==(0x90000000||0x94000000))
if (((per.q(spr:0x35520))&0x3F)==(0x10))
group.quad spr:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
newline
newline
newline
bitfld.quad 0x00 11.--12. "SET,Synchronous Error Type" "UER,UEO,UC,CE"
newline
bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.quad 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/L0,Sync. parity/ECC/L1,Sync. parity/ECC/L2,Sync. parity/ECC/L3,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive/Atomic access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
else
group.quad spr:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
newline
newline
newline
newline
bitfld.quad 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/L0,Sync. parity/ECC/L1,Sync. parity/ECC/L2,Sync. parity/ECC/L3,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive/Atomic access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
endif
elif (((per.q(spr:0x35520))&0xFC800000)==(0xA0800000||0xB0800000))
group.quad spr:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred"
bitfld.quad 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.quad 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred"
bitfld.quad 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.quad 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred"
bitfld.quad 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred"
elif (((per.q(spr:0x35520))&0xFC800000)==(0xA0000000||0xB0000000))
group.quad spr:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
elif (((per.q(spr:0x35520))&0xFD000000)==0xBD000000)
if (((per.q(spr:0x35520))&0x3F)==0x11)
group.quad spr:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "IDS,Implementation defined syndrome" "Not hold,Hold"
bitfld.quad 0x00 13. "IESB,Implicit Error Synchronization Barrier" "Not synchronized,Synchronized"
newline
bitfld.quad 0x00 10.--12. "AET,Asynchronous Error Type" "UC,UEU,UEO,UER,CE,?..."
bitfld.quad 0x00 9. "EA,External abort type" "No,Yes"
newline
bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Uncategorized,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous,?..."
else
group.quad spr:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "IDS,Implementation defined syndrome" "Not hold,Hold"
bitfld.quad 0x00 9. "EA,External abort type" "No,Yes"
newline
bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Uncategorized,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous,?..."
endif
elif (((per.q(spr:0x35520))&0xFD000000)==0xBC000000)
group.quad spr:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "IDS,Implementation defined syndrome" "Not hold,Hold"
elif (((per.q(spr:0x35520))&0xFC000000)==(0xC0000000||0xC4000000))
group.quad spr:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,Debug exception,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
elif (((per.q(spr:0x35520))&0xFC000000)==(0xC8000000||0xCC000000))
group.quad spr:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,EX bit valid" "Not valid,Valid"
bitfld.quad 0x00 6. "EX,Exclusive operation" "No,Yes"
newline
bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,Debug exception,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
elif (((per.q(spr:0x35520))&0xFC000000)==(0xD0000000||0xD4000000))
group.quad spr:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 8. "CM,Data came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write"
newline
bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,?..."
elif (((per.q(spr:0x35520))&0xFC000000)==(0xE0000000||0xF0000000))
group.quad spr:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.quad.word 0x00 0.--15. 1. "COMMENT,Set to the instruction comment field value"
else
group.quad spr:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
endif
if (((per.q(spr:0x34520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000))
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
elif (((per.q(spr:0x34520))&0xFC000000)==0x04000000)
if (((per.q(spr:0x34520))&0x1000000)==0x1000000)
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.quad 0x00 0. "TI,Trapped instruction" "WFI,WFE"
else
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
newline
bitfld.quad 0x00 0. "TI,Trapped instruction" "WFI,WFE"
endif
elif (((per.q(spr:0x34520))&0xFC000000)==(0x0C000000||0x14000000||0x20000000))
if (((per.q(spr:0x34520))&0x1000000)==0x1000000)
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.quad 0x00 17.--19. "OPC2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 14.--16. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
else
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
newline
bitfld.quad 0x00 17.--19. "OPC2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 14.--16. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
endif
elif (((per.q(spr:0x34520))&0xFC000000)==(0x10000000||0x30000000))
if (((per.q(spr:0x34520))&0x1000000)==0x1000000)
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.quad 0x00 16.--19. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 10.--14. "RT2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
else
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
newline
bitfld.quad 0x00 16.--19. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 10.--14. "RT2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
endif
elif (((per.q(spr:0x34520))&0xFC000000)==0x18000000)
if (((per.q(spr:0x34520))&0x1000000)==0x1000000)
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction"
bitfld.quad 0x00 5.--9. "RN,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved"
newline
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
else
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
newline
hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction"
bitfld.quad 0x00 5.--9. "RN,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved"
newline
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
endif
elif (((per.q(spr:0x34520))&0xFC000000)==0x1C000000)
if (((per.q(spr:0x34520))&0x1000000)==0x1000000)
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
else
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
endif
elif (((per.q(spr:0x34520))&0xFC000000)==(0x44000000||0x48000000||0x54000000||0x58000000))
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.quad.word 0x00 0.--15. 1. "IMM16,The value of the immediate field from the HVC or SVC instruction"
elif (((per.q(spr:0x34520))&0xFC000000)==0x4C000000)
if ((((per.q(spr:0x34520))&0x1000000)==0x1000000)&&(((per.q(spr:0x34520))&0xF0000)==0x80000))
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.quad 0x00 19. "CCKNOWNPASS,Indicates whether the instruction might have failed its condition code check" "Unconditional,Conditional"
elif (((per.q(spr:0x34520))&0xF0000)==0x80000)
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
newline
bitfld.quad 0x00 19. "CCKNOWNPASS,Indicates whether the instruction might have failed its condition code check" "Unconditional,Conditional"
else
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
newline
bitfld.quad 0x00 19. "CCKNOWNPASS,Indicates whether the instruction might have failed its condition code check" "Unconditional,Conditional"
endif
elif (((per.q(spr:0x34520))&0xFC000000)==0x5C000000)
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.quad.word 0x00 0.--15. 1. "IMM16,The value of the immediate field from the issued SMC instruction"
elif (((per.q(spr:0x34520))&0xFC000000)==0x60000000)
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 20.--21. "OP0,Op0 value from the issued instruction" "0,1,2,3"
bitfld.quad 0x00 17.--19. "OP2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 14.--16. "OP1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((per.q(spr:0x34520))&0xFC000000)==(0x80000000||0x84000000))
if (((per.q(spr:0x34520))&0x3F)==(0x10))
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 11.--12. "SET,Synchronous Error Type" "UER,UEO,UC,CE"
newline
bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.quad 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/L0/base register,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Sync. parity/ECC/L0,Sync. parity/ECC/L1,Sync. parity/ECC/L2,Sync. parity/ECC/L3,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..."
else
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
newline
bitfld.quad 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/L0/base register,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Sync. parity/ECC/L0,Sync. parity/ECC/L1,Sync. parity/ECC/L2,Sync. parity/ECC/L3,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..."
endif
elif (((per.q(spr:0x34520))&0xFD000000)==(0x91000000||0x95000000))
if (((per.q(spr:0x34520))&0x3F)==(0x10))
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
bitfld.quad 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword"
newline
bitfld.quad 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required"
bitfld.quad 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit"
bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes"
newline
bitfld.quad 0x00 11.--12. "SET,Synchronous Error Type" "UER,UEO,UC,CE"
newline
bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.quad 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/L0,Sync. parity/ECC/L1,Sync. parity/ECC/L2,Sync. parity/ECC/L3,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive/Atomic access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
else
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
bitfld.quad 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword"
newline
bitfld.quad 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required"
bitfld.quad 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit"
bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes"
newline
newline
bitfld.quad 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/L0,Sync. parity/ECC/L1,Sync. parity/ECC/L2,Sync. parity/ECC/L3,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive/Atomic access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
endif
elif (((per.q(spr:0x34520))&0xFD000000)==(0x90000000||0x94000000))
if (((per.q(spr:0x34520))&0x3F)==(0x10))
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
newline
newline
newline
bitfld.quad 0x00 11.--12. "SET,Synchronous Error Type" "UER,UEO,UC,CE"
newline
bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.quad 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/L0,Sync. parity/ECC/L1,Sync. parity/ECC/L2,Sync. parity/ECC/L3,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive/Atomic access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
else
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
newline
newline
newline
newline
bitfld.quad 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/L0,Sync. parity/ECC/L1,Sync. parity/ECC/L2,Sync. parity/ECC/L3,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive/Atomic access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
endif
elif (((per.q(spr:0x34520))&0xFC800000)==(0xA0800000||0xB0800000))
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred"
bitfld.quad 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.quad 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred"
bitfld.quad 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.quad 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred"
bitfld.quad 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred"
elif (((per.q(spr:0x34520))&0xFC800000)==(0xA0000000||0xB0000000))
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
elif (((per.q(spr:0x34520))&0xFD000000)==0xBD000000)
if (((per.q(spr:0x34520))&0x3F)==0x11)
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "IDS,Implementation defined syndrome" "Not hold,Hold"
bitfld.quad 0x00 13. "IESB,Implicit Error Synchronization Barrier" "Not synchronized,Synchronized"
newline
bitfld.quad 0x00 10.--12. "AET,Asynchronous Error Type" "UC,UEU,UEO,UER,CE,?..."
newline
bitfld.quad 0x00 9. "EA,External abort type" "No,Yes"
bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Uncategorized,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous,?..."
else
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "IDS,Implementation defined syndrome" "Not hold,Hold"
newline
newline
bitfld.quad 0x00 9. "EA,External abort type" "No,Yes"
bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Uncategorized,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous,?..."
endif
elif (((per.q(spr:0x34520))&0xFD000000)==0xBC000000)
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "IDS,Implementation defined syndrome" "Not hold,Hold"
elif (((per.q(spr:0x34520))&0xFC000000)==(0xC0000000||0xC4000000||0xE8000000))
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,Debug exception,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
elif (((per.q(spr:0x34520))&0xFC000000)==(0xC8000000||0xCC000000))
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,EX bit valid" "Not valid,Valid"
bitfld.quad 0x00 6. "EX,Exclusive operation" "No,Yes"
newline
bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,Debug exception,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
elif (((per.q(spr:0x34520))&0xFC000000)==(0xD0000000||0xD4000000))
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 8. "CM,Data came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write"
newline
bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,?..."
elif (((per.q(spr:0x34520))&0xFC000000)==(0xE0000000||0xF0000000))
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.quad.word 0x00 0.--15. 1. "COMMENT,Set to the instruction comment field value"
else
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
endif
if (((per.q(spr:0x36520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000))
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
elif (((per.q(spr:0x36520))&0xFC000000)==0x04000000)
if (((per.q(spr:0x36520))&0x1000000)==0x1000000)
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.quad 0x00 0. "TI,Trapped instruction" "WFI,WFE"
else
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
newline
bitfld.quad 0x00 0. "TI,Trapped instruction" "WFI,WFE"
endif
elif (((per.q(spr:0x36520))&0xFC000000)==(0x0C000000||0x14000000))
if (((per.q(spr:0x36520))&0x1000000)==0x1000000)
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.quad 0x00 17.--19. "OPC2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 14.--16. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
else
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
newline
bitfld.quad 0x00 17.--19. "OPC2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 14.--16. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
endif
elif (((per.q(spr:0x36520))&0xFC000000)==(0x10000000||0x30000000))
if (((per.q(spr:0x36520))&0x1000000)==0x1000000)
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.quad 0x00 16.--19. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 10.--14. "RT2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
else
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
newline
bitfld.quad 0x00 16.--19. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 10.--14. "RT2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
endif
elif (((per.q(spr:0x36520))&0xFC000000)==0x18000000)
if (((per.q(spr:0x36520))&0x1000000)==0x1000000)
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction"
bitfld.quad 0x00 5.--9. "RN,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved"
newline
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
else
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
newline
hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction"
bitfld.quad 0x00 5.--9. "RN,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved"
newline
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
endif
elif (((per.q(spr:0x36520))&0xFC000000)==0x1C000000)
if (((per.q(spr:0x36520))&0x1000000)==0x1000000)
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
else
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
endif
elif (((per.q(spr:0x36520))&0xFC000000)==0x4C000000)
if ((((per.q(spr:0x36520))&0x1000000)==0x1000000)&&(((per.q(spr:0x36520))&0xF0000)==0x80000))
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.quad 0x00 19. "CCKNOWNPASS,Indicates whether the instruction might have failed its condition code check" "Unconditional,Conditional"
elif (((per.q(spr:0x36520))&0xF0000)==0x80000)
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
newline
bitfld.quad 0x00 19. "CCKNOWNPASS,Indicates whether the instruction might have failed its condition code check" "Unconditional,Conditional"
else
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
newline
bitfld.quad 0x00 19. "CCKNOWNPASS,Indicates whether the instruction might have failed its condition code check" "Unconditional,Conditional"
endif
elif (((per.q(spr:0x36520))&0xFC000000)==(0x54000000||0x58000000))
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.quad.word 0x00 0.--15. 1. "IMM16,The value of the immediate field from the HVC or SVC instruction"
elif (((per.q(spr:0x36520))&0xFC000000)==0x5C000000)
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.quad.word 0x00 0.--15. 1. "IMM16,The value of the immediate field from the issued SMC instruction"
elif (((per.q(spr:0x36520))&0xFC000000)==0x60000000)
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 20.--21. "OP0,Op0 value from the issued instruction" "0,1,2,3"
bitfld.quad 0x00 17.--19. "OP2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 14.--16. "OP1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((per.q(spr:0x36520))&0xFC000000)==0x7C000000)
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.quad.long 0x00 0.--24. 1. "IMPL_DEF,Implementation defined"
elif (((per.q(spr:0x36520))&0xFC000000)==(0x80000000||0x84000000))
if (((per.q(spr:0x36520))&0x3F)==(0x10))
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 11.--12. "SET,Synchronous Error Type" "UER,UEO,UC,CE"
newline
bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.quad 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/L0/base register,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Sync. parity/ECC/L0,Sync. parity/ECC/L1,Sync. parity/ECC/L2,Sync. parity/ECC/L3,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..."
else
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
newline
bitfld.quad 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/L0/base register,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Sync. parity/ECC/L0,Sync. parity/ECC/L1,Sync. parity/ECC/L2,Sync. parity/ECC/L3,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..."
endif
elif (((per.q(spr:0x36520))&0xFD000000)==(0x91000000||0x95000000))
if (((per.q(spr:0x36520))&0x3F)==(0x10))
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
bitfld.quad 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword"
newline
bitfld.quad 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required"
bitfld.quad 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit"
bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes"
newline
bitfld.quad 0x00 11.--12. "SET,Synchronous Error Type" "UER,UEO,UC,CE"
newline
bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.quad 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/L0,Sync. parity/ECC/L1,Sync. parity/ECC/L2,Sync. parity/ECC/L3,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive/Atomic access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
else
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
bitfld.quad 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword"
newline
bitfld.quad 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required"
bitfld.quad 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit"
bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes"
newline
newline
bitfld.quad 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/L0,Sync. parity/ECC/L1,Sync. parity/ECC/L2,Sync. parity/ECC/L3,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive/Atomic access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
endif
elif (((per.q(spr:0x36520))&0xFD000000)==(0x90000000||0x94000000))
if (((per.q(spr:0x36520))&0x3F)==(0x10))
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
newline
newline
newline
bitfld.quad 0x00 11.--12. "SET,Synchronous Error Type" "UER,UEO,UC,CE"
newline
bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.quad 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/L0,Sync. parity/ECC/L1,Sync. parity/ECC/L2,Sync. parity/ECC/L3,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive/Atomic access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
else
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
newline
newline
newline
newline
bitfld.quad 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/L0,Sync. parity/ECC/L1,Sync. parity/ECC/L2,Sync. parity/ECC/L3,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive/Atomic access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
endif
elif (((per.q(spr:0x36520))&0xFC800000)==0xB0800000)
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred"
bitfld.quad 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.quad 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred"
bitfld.quad 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.quad 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred"
bitfld.quad 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred"
elif (((per.q(spr:0x36520))&0xFC800000)==0xB0000000)
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
elif (((per.q(spr:0x36520))&0xFD000000)==0xBD000000)
if (((per.q(spr:0x36520))&0x3F)==0x11)
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "IDS,Implementation defined syndrome" "Not hold,Hold"
bitfld.quad 0x00 13. "IESB,Implicit Error Synchronization Barrier" "Not synchronized,Synchronized"
newline
bitfld.quad 0x00 10.--12. "AET,Asynchronous Error Type" "UC,UEU,UEO,UER,CE,?..."
newline
bitfld.quad 0x00 9. "EA,External abort type" "No,Yes"
bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Uncategorized,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous,?..."
else
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "IDS,Implementation defined syndrome" "Not hold,Hold"
newline
newline
bitfld.quad 0x00 9. "EA,External abort type" "No,Yes"
bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Uncategorized,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous,?..."
endif
elif (((per.q(spr:0x36520))&0xFD000000)==0xBC000000)
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "IDS,Implementation defined syndrome" "Not hold,Hold"
elif (((per.q(spr:0x36520))&0xFC000000)==0xF0000000)
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.quad.word 0x00 0.--15. 1. "COMMENT,Set to the instruction comment field value"
else
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
endif
tree.end
newline
if (CORENAME()=="CORTEXA75")
group.quad spr:0x30C11++0x00
line.quad 0x00 "DISR_EL1,Deferred Interrupt Status Register"
bitfld.quad 0x00 31. "A,Asynchronous SError interrupt deferred" "No,Yes"
bitfld.quad 0x00 24. "IDS,Indicates the type of format the deferred SError interrupt uses" "Architecturally-defined,"
newline
bitfld.quad 0x00 10.--12. "AET,Asynchronous Error Type" "UC/Uncontainable,?..."
bitfld.quad 0x00 0.--5. "DFSC,Fault status code" "Uncategorized,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Async. SError,?..."
elif (CORENAME()=="CORTEXA55")
if (((per.q(spr:0x30C11))&0x1000000)==0x00)&&(((per.q(spr:0x30C11))&0x3F)==0x11)
group.quad spr:0x30C11++0x00
line.quad 0x00 "DISR_EL1,Deferred Interrupt Status Register"
bitfld.quad 0x00 31. "A,Asynchronous SError interrupt deferred" "No,Yes"
bitfld.quad 0x00 24. "IDS,Indicates the type of format the deferred SError interrupt uses" "Architecturally-defined,"
newline
bitfld.quad 0x00 10.--12. "AET,Asynchronous Error Type" "Reserved,UEU/Unrecoverable,?..."
bitfld.quad 0x00 0.--5. "DFSC,Fault Status Code" "Uncategorized,Reserved,Reserved,Reserved,Reserved,Reserved,Async. SError/AArch32,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Async. SError/AArch64,?..."
else
group.quad spr:0x30C11++0x00
line.quad 0x00 "DISR_EL1,Deferred Interrupt Status Register"
bitfld.quad 0x00 31. "A,Asynchronous SError interrupt deferred" "No,Yes"
bitfld.quad 0x00 24. "IDS,Indicates the type of format the deferred SError interrupt uses" "Architecturally-defined,"
newline
bitfld.quad 0x00 0.--5. "DFSC,Fault Status Code" "Uncategorized,Reserved,Reserved,Reserved,Reserved,Reserved,Async. SError/AArch32,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Async. SError/AArch64,?..."
endif
endif
if (CORENAME()=="CORTEXA75")
group.quad spr:0x34523++0x00
line.quad 0x00 "VSESR_EL2,Virtual SError Exception Syndrome Register - EL1 using AArch32"
bitfld.quad 0x00 14.--15. "AET,Asynchronous Error Type" "UC/Uncontainable,?..."
bitfld.quad 0x00 12. "EXT,External Abort Type" "0,1"
group.quad spr:0x34523++0x00
line.quad 0x00 "VSESR_EL2,Virtual SError Exception Syndrome Register - EL1 using AArch64"
bitfld.quad 0x00 24. "IDS,Indicates the type of format the deferred SError interrupt uses" "Architecturally-defined,Implementation-defined"
hexmask.quad.tbyte 0x00 0.--23. 1. "ISS,Syndrome information"
if (((per.q(spr:0x34C11))&0x200)==0x00)
group.quad spr:0x34C11++0x00
line.quad 0x00 "VDISR_EL2,Virtual Deferred Interrupt Status Register - EL1 using the AArch32 Short-descriptor"
bitfld.quad 0x00 31. "A,Indicates when ESB defers a virtual SError interrupt" "Not deferred,Deferred"
bitfld.quad 0x00 14.--15. "AET,Asynchronous Error Type" "UC/Uncontainable,?..."
newline
bitfld.quad 0x00 9. "LPAE,Translation table format" "Short,Long"
bitfld.quad 0x00 0.--3. 10. "FS,Fault status code" ",,,,,,,,,,,,,,,,,,,,,,Asynchronous SError interrupt,?..."
else
group.quad spr:0x34C11++0x00
line.quad 0x00 "VDISR_EL2,Virtual Deferred Interrupt Status Register - EL1 using the AArch32 Long-descriptor"
bitfld.quad 0x00 31. "A,Indicates when ESB defers a virtual SError interrupt" "Not deferred,Deferred"
bitfld.quad 0x00 14.--15. "AET,Asynchronous Error Type" "UC/Uncontainable,?..."
newline
bitfld.quad 0x00 9. "LPAE,Translation table format" "Short,Long"
bitfld.quad 0x00 0.--5. "STATUS,Fault status code" ",,,,,,,,,,,,,,,,,Asynchronous SError interrupt,?..."
endif
group.quad spr:0x34C11++0x00
line.quad 0x00 "VDISR_EL2,Virtual Deferred Interrupt Status Register - EL1 using the AArch64"
bitfld.quad 0x00 31. "A,Indicates when ESB defers a virtual SError interrupt" "Not deferred,Deferred"
bitfld.quad 0x00 24. "IDS,Indicates the type of format the deferred SError interrupt uses" "Architecturally-defined,Implementation-defined"
newline
hexmask.quad.tbyte 0x00 0.--23. 1. "ISS,Syndrome information"
elif (CORENAME()=="CORTEXA55")
group.quad spr:0x34523++0x00
line.quad 0x00 "VSESR_EL2,Virtual SError Exception Syndrome Register - EL1 using AArch32"
bitfld.quad 0x00 14.--15. "AET,Asynchronous Error Type" "Reserved,UEU/Unrecoverable,?..."
group.quad spr:0x34523++0x00
line.quad 0x00 "VSESR_EL2,Virtual SError Exception Syndrome Register - EL1 using AArch64"
bitfld.quad 0x00 24. "IDS,Indicates the type of format the deferred SError interrupt uses" "Architecturally-defined,Implementation-defined"
hexmask.quad.tbyte 0x00 0.--23. 1. "ISS,Syndrome information"
if (((per.q(spr:0x34C11))&0x200)==0x00)
group.quad spr:0x34C11++0x00
line.quad 0x00 "VDISR_EL2,Virtual Deferred Interrupt Status Register - EL1 using the AArch32 Short-descriptor"
bitfld.quad 0x00 31. "A,Indicates when ESB defers a virtual SError interrupt" "Not deferred,Deferred"
bitfld.quad 0x00 14.--15. "AET,Asynchronous Error Type" "Reserved,UEU/Unrecoverable,?..."
newline
bitfld.quad 0x00 9. "LPAE,Translation table format" "Short,Long"
bitfld.quad 0x00 0.--3. 10. "FS,Fault status code" ",,,,,,,,,,,,,,,,,,,,,,Asynchronous SError interrupt,?..."
else
group.quad spr:0x34C11++0x00
line.quad 0x00 "VDISR_EL2,Virtual Deferred Interrupt Status Register - EL1 using the AArch32 Long-descriptor"
bitfld.quad 0x00 31. "A,Indicates when ESB defers a virtual SError interrupt" "Not deferred,Deferred"
bitfld.quad 0x00 14.--15. "AET,Asynchronous Error Type" "Reserved,UEU/Unrecoverable,?..."
newline
bitfld.quad 0x00 9. "LPAE,Translation table format" "Short,Long"
bitfld.quad 0x00 0.--5. "STATUS,Fault status code" ",,,,,,,,,,,,,,,,,Asynchronous SError interrupt,?..."
endif
group.quad spr:0x34C11++0x00
line.quad 0x00 "VDISR_EL2,Virtual Deferred Interrupt Status Register - EL1 using the AArch64"
bitfld.quad 0x00 31. "A,Indicates when ESB defers a virtual SError interrupt" "Not deferred,Deferred"
bitfld.quad 0x00 24. "IDS,Indicates the type of format the deferred SError interrupt uses" "Architecturally-defined,Implementation-defined"
newline
hexmask.quad.tbyte 0x00 0.--23. 1. "ISS,Syndrome information"
endif
if (((per.q(c15:0x0202))&0x80000000)==0x00000000)
group.quad spr:0x34501++0x00
line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register"
bitfld.quad 0x00 16. "FNV,FAR not Valid" "Valid,Not valid"
bitfld.quad 0x00 12. "EXT,External abort type" "0,1"
newline
bitfld.quad 0x00 9. "LPAE,Descriptor translation table format" "Short,Long"
bitfld.quad 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Reserved,Debug event,Access flag/section,Reserved,Translation/section,Access flag/page,Translation/page,Sync. external/non-translation,Domain/section,Reserved,Domain/page,Sync. external/on TTW/L1,Permission/section,Sync. external/on TTW/L2,Permission/page,TLB conflict,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/L1,Reserved,Sync. parity/on TTW/L2,?..."
else
group.quad spr:0x34501++0x00
line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register"
bitfld.quad 0x00 16. "FNV,FAR not Valid" "Valid,Not valid"
bitfld.quad 0x00 12. "EXT,External abort type" "0,1"
newline
bitfld.quad 0x00 9. "LPAE,Descriptor translation table format" "Short,Long"
bitfld.quad 0x00 0.--5. "STATUS,Fault Status" "Reserved,Reserved,Reserved,Reserved,Reserved,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external,Reserved,Reserved,Reserved,Reserved,Sync. external/on TTW/L1,Sync. external/on TTW/L2,Sync. external/on TTW/L3,Sync. parity/on memory access,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/L1,Sync. parity/on memory access/on TTW/L2,Sync. parity/on memory access/on TTW/L3,Reserved,Alignment,Debug event,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..."
endif
group.quad spr:0x30600++0x00
line.quad 0x00 "FAR_EL1,Fault Address Register"
group.quad spr:0x35600++0x00
line.quad 0x00 "FAR_EL12,Fault Address Register"
group.quad spr:0x34600++0x00
line.quad 0x00 "FAR_EL2,Fault Address Register"
group.quad spr:0x36600++0x00
line.quad 0x00 "FAR_EL3,Fault Address Register"
group.quad spr:0x34604++0x00
line.quad 0x00 "HPFAR_EL2,Hypervisor IPA Fault Address Register"
hexmask.quad 0x00 4.--43. 0x10 "FIPA[51:12],Bits [51:12] of the faulting intermediate physical address"
group.quad spr:0x31F30++0x00
line.quad 0x00 "CBAR_EL1,Configuration Base Address Register EL1"
hexmask.quad.long 0x00 18.--43. 0x4 "PERIPHBASE,Holds the physical base address of the memory-mapped GIC CPU interface registers"
group.quad spr:0x30C00++0x00
line.quad 0x00 "VBAR_EL1,Vector Base Address Register"
hexmask.quad 0x00 11.--63. 0x8 "VBA,Vector Base Address"
group.quad spr:0x35C00++0x00
line.quad 0x00 "VBAR_EL12,Vector Base Address Register"
hexmask.quad 0x00 11.--63. 0x8 "VBA,Vector Base Address"
group.quad spr:0x34C00++0x00
line.quad 0x00 "VBAR_EL2,Vector Base Address Register"
hexmask.quad 0x00 11.--63. 0x8 "VBA,Vector Base Address"
group.quad spr:0x36C00++0x00
line.quad 0x00 "VBAR_EL3,Vector Base Address Register"
hexmask.quad 0x00 11.--63. 0x8 "VBA,Vector Base Address"
if (CORENAME()=="CORTEXA75")
rgroup.quad spr:0x36C01++0x00
line.quad 0x00 "RVBAR_EL3,Reset Vector Base Address Register"
elif (CORENAME()=="CORTEXA55")
rgroup.quad spr:0x36C01++0x00
line.quad 0x00 "RVBAR_EL3,Reset Vector Base Address Register"
hexmask.quad 0x00 0.--39. 0x1 "RVBA,Reset Vector Base Address"
endif
group.quad spr:0x30C02++0x00
line.quad 0x00 "RMR_EL1,Reset Management Register"
bitfld.quad 0x00 1. "RR,Reset Request" "Not requested,Requested"
bitfld.quad 0x00 0. "AA64,Determines which execution state the processor boots into after a warm reset" "AArch32,AArch64"
group.quad spr:0x36C02++0x00
line.quad 0x00 "RMR_EL3,Reset Management Register"
bitfld.quad 0x00 1. "RR,Reset Request" "Not requested,Requested"
bitfld.quad 0x00 0. "AA64,Determines which execution state the processor boots into after a warm reset" "AArch32,AArch64"
rgroup.quad spr:0x30C10++0x00
line.quad 0x00 "ISR_EL1,Interrupt Status Register"
bitfld.quad 0x00 8. "A,SError interrupt pending bit" "Not pending,Pending"
bitfld.quad 0x00 7. "I,IRQ pending bit" "Not pending,Pending"
newline
bitfld.quad 0x00 6. "F,FIQ pending bit" "Not pending,Pending"
group.quad spr:0x30D01++0x00
line.quad 0x00 "CONTEXTIDR_EL1,Context ID Register"
group.quad spr:0x35D01++0x00
line.quad 0x00 "CONTEXTIDR_EL12,Context ID Register"
group.quad spr:0x34D01++0x00
line.quad 0x00 "CONTEXTIDR_EL2,Context ID Register"
group.quad spr:0x33D02++0x00
line.quad 0x00 "TPIDR_EL0,Software Thread ID registers"
group.quad spr:0x33D03++0x00
line.quad 0x00 "TPIDRRO_EL0,Software Thread ID registers"
group.quad spr:0x30D04++0x00
line.quad 0x00 "TPIDR_EL1,Software Thread ID registers"
group.quad spr:0x34D02++0x00
line.quad 0x00 "TPIDR_EL2,Software Thread ID registers"
group.quad spr:0x36D02++0x00
line.quad 0x00 "TPIDR_EL3,Software Thread ID registers"
tree "System Instructions"
wgroup.quad spr:0x10710++0x00
line.quad 0x00 "IC_IALLUIS,IC_IALLUIS"
wgroup.quad spr:0x10750++0x00
line.quad 0x00 "IC_IALLU,IC_IALLU"
wgroup.quad spr:0x13751++0x00
line.quad 0x00 "IC_IVAU,IC_IVAU"
wgroup.quad spr:0x13741++0x00
line.quad 0x00 "DC_ZVA,DC_ZVA"
wgroup.quad spr:0x10761++0x00
line.quad 0x00 "DC_IVAC,DC_IVAC"
wgroup.quad spr:0x10762++0x00
line.quad 0x00 "DC_ISW,DC_ISW"
wgroup.quad spr:0x137A1++0x00
line.quad 0x00 "DC_CVAC,DC_CVAC"
wgroup.quad spr:0x137C1++0x00
line.quad 0x00 "DC_CVAP,DC CVAP"
wgroup.quad spr:0x107A2++0x00
line.quad 0x00 "DC_CSW,DC_CSW"
wgroup.quad spr:0x137B1++0x00
line.quad 0x00 "DC_CVAU,DC_CVAU"
wgroup.quad spr:0x137E1++0x00
line.quad 0x00 "DC_CIVAC,DC_CIVAC"
wgroup.quad spr:0x107E2++0x00
line.quad 0x00 "DC_CISW,DC_CISW"
wgroup.quad spr:0x10780++0x00
line.quad 0x00 "AT_S1E1R,AT_S1E1R"
wgroup.quad spr:0x10781++0x00
line.quad 0x00 "AT_S1E1W,AT_S1E1W"
wgroup.quad spr:0x10782++0x00
line.quad 0x00 "AT_S1E0R,AT_S1E0R"
wgroup.quad spr:0x10790++0x00
line.quad 0x00 "AT_S1E1RP,AT_S1E1RP"
wgroup.quad spr:0x10791++0x00
line.quad 0x00 "AT_S1E1WP,AT_S1E1WP"
wgroup.quad spr:0x10783++0x00
line.quad 0x00 "AT_S1E0W,AT_S1E0W"
wgroup.quad spr:0x14784++0x00
line.quad 0x00 "AT_S12E1R,AT_S12E1R"
wgroup.quad spr:0x14785++0x00
line.quad 0x00 "AT_S12E1W,AT_S12E1W"
wgroup.quad spr:0x14786++0x00
line.quad 0x00 "AT_S12E0R,AT_S12E0R"
wgroup.quad spr:0x14787++0x00
line.quad 0x00 "AT_S12E0W,AT_S12E0W"
wgroup.quad spr:0x14780++0x00
line.quad 0x00 "AT_S1E2R,AT_S1E2R"
wgroup.quad spr:0x14781++0x00
line.quad 0x00 "AT_S1E2W,AT_S1E2W"
wgroup.quad spr:0x16780++0x00
line.quad 0x00 "AT_S1E3R,AT_S1E3R"
wgroup.quad spr:0x16781++0x00
line.quad 0x00 "AT_S1E3W,AT_S1E3W"
wgroup.quad spr:0x10870++0x00
line.quad 0x00 "TLBI_VMALLE1,TLBI_VMALLE1"
wgroup.quad spr:0x10871++0x00
line.quad 0x00 "TLBI_VAE1,TLBI_VAE1"
wgroup.quad spr:0x10872++0x00
line.quad 0x00 "TLBI_ASIDE1,TLBI_ASIDE1"
wgroup.quad spr:0x10873++0x00
line.quad 0x00 "TLBI_VAAE1,TLBI_VAAE1"
wgroup.quad spr:0x10875++0x00
line.quad 0x00 "TLBI_VALE1,TLBI_VALE1"
wgroup.quad spr:0x10877++0x00
line.quad 0x00 "TLBI_VAALE1,TLBI_VAALE1"
wgroup.quad spr:0x10830++0x00
line.quad 0x00 "TLBI_VMALLE1IS,TLBI_VMALLE1IS"
wgroup.quad spr:0x10831++0x00
line.quad 0x00 "TLBI_VAE1IS,TLBI_VAE1IS"
wgroup.quad spr:0x10832++0x00
line.quad 0x00 "TLBI_ASIDE1IS,TLBI_ASIDE1IS"
wgroup.quad spr:0x10833++0x00
line.quad 0x00 "TLBI_VAAE1IS,TLBI_VAAE1IS"
wgroup.quad spr:0x10835++0x00
line.quad 0x00 "TLBI_VALE1IS,TLBI_VALE1IS"
wgroup.quad spr:0x10837++0x00
line.quad 0x00 "TLBI_VAALE1IS,TLBI_VAALE1IS"
wgroup.quad spr:0x14801++0x00
line.quad 0x00 "TLBI_IPAS2E1IS,TLBI_IPAS2E1IS"
wgroup.quad spr:0x14805++0x00
line.quad 0x00 "TLBI_IPAS2LE1IS,TLBI_IPAS2LE1IS"
wgroup.quad spr:0x14841++0x00
line.quad 0x00 "TLBI_IPAS2E1,TLBI_IPAS2E1"
wgroup.quad spr:0x14845++0x00
line.quad 0x00 "TLBI_IPAS2LE1,TLBI_IPAS2LE1"
wgroup.quad spr:0x14871++0x00
line.quad 0x00 "TLBI_VAE2,TLBI_VAE2"
wgroup.quad spr:0x14875++0x00
line.quad 0x00 "TLBI_VALE2,TLBI_VALE2"
wgroup.quad spr:0x14876++0x00
line.quad 0x00 "TLBI_VMALLS12E1,TLBI_VMALLS12E1"
wgroup.quad spr:0x14831++0x00
line.quad 0x00 "TLBI_VAE2IS,TLBI_VAE2IS"
wgroup.quad spr:0x14835++0x00
line.quad 0x00 "TLBI_VALE2IS,TLBI_VALE2IS"
wgroup.quad spr:0x14836++0x00
line.quad 0x00 "TLBI_VMALLS12E1IS,TLBI_VMALLS12E1IS"
wgroup.quad spr:0x16871++0x00
line.quad 0x00 "TLBI_VAE3,TLBI_VAE3"
wgroup.quad spr:0x16875++0x00
line.quad 0x00 "TLBI_VALE3,TLBI_VALE3"
wgroup.quad spr:0x16831++0x00
line.quad 0x00 "TLBI_VAE3IS,TLBI_VAE3IS"
wgroup.quad spr:0x16835++0x00
line.quad 0x00 "TLBI_VALE3IS,TLBI_VALE3IS"
wgroup.quad spr:0x14870++0x00
line.quad 0x00 "TLBI_ALLE2,TLBI_ALLE2"
wgroup.quad spr:0x14830++0x00
line.quad 0x00 "TLBI_ALLE2IS,TLBI_ALLE2IS"
wgroup.quad spr:0x14874++0x00
line.quad 0x00 "TLBI_ALLE1,TLBI_ALLE1"
wgroup.quad spr:0x14834++0x00
line.quad 0x00 "TLBI_ALLE1IS,TLBI_ALLE1IS"
wgroup.quad spr:0x16870++0x00
line.quad 0x00 "TLBI_ALLE3,TLBI_ALLE3"
wgroup.quad spr:0x16830++0x00
line.quad 0x00 "TLBI_ALLE3IS,TLBI_ALLE3IS"
tree.end
tree.end
tree "Memory Management Unit"
tree.open "Hypervisor Configuration System Registers"
group.quad spr:0x34113++0x00
line.quad 0x00 "HSTR_EL2,Hypervisor System Trap Register"
bitfld.quad 0x00 15. "T15,Trap to Hypervisor mode Non-secure priv 15" "No trap,Trap"
bitfld.quad 0x00 13. "T13,Trap to Hypervisor mode Non-secure priv 13" "No trap,Trap"
bitfld.quad 0x00 12. "T12,Trap to Hypervisor mode Non-secure priv 12" "No trap,Trap"
newline
bitfld.quad 0x00 11. "T11,Trap to Hypervisor mode Non-secure priv 11" "No trap,Trap"
bitfld.quad 0x00 10. "T10,Trap to Hypervisor mode Non-secure priv 10" "No trap,Trap"
bitfld.quad 0x00 9. "T9,Trap to Hypervisor mode Non-secure priv 9" "No trap,Trap"
newline
bitfld.quad 0x00 8. "T8,Trap to Hypervisor mode Non-secure priv 8" "No trap,Trap"
bitfld.quad 0x00 7. "T7,Trap to Hypervisor mode Non-secure priv 7" "No trap,Trap"
bitfld.quad 0x00 6. "T6,Trap to Hypervisor mode Non-secure priv 6" "No trap,Trap"
newline
bitfld.quad 0x00 5. "T5,Trap to Hypervisor mode Non-secure priv 5" "No trap,Trap"
bitfld.quad 0x00 3. "T3,Trap to Hypervisor mode Non-secure priv 3" "No trap,Trap"
bitfld.quad 0x00 2. "T2,Trap to Hypervisor mode Non-secure priv 2" "No trap,Trap"
newline
bitfld.quad 0x00 1. "T1,Trap to Hypervisor mode Non-secure priv 1" "No trap,Trap"
bitfld.quad 0x00 0. "T0,Trap to Hypervisor mode Non-secure priv 0" "No trap,Trap"
group.quad spr:0x34117++0x00
line.quad 0x00 "HACR_EL2,Hypervisor Auxiliary Configuration Register"
tree.end
if (CORENAME()=="CORTEXA75")
group.quad spr:0x30200++0x00
line.quad 0x00 "TTBR0_EL1,Translation Table Base Registers"
hexmask.quad.word 0x00 48.--63. 1. "ASID,ASID for the translation table base address"
hexmask.quad 0x00 1.--47. 0x2 "BADDR[47:1],Translation table base address"
newline
bitfld.quad 0x00 0. "CNP,Common not Private" "Not supported,Supported"
group.quad spr:0x30201++0x00
line.quad 0x00 "TTBR1_EL1,Translation Table Base Registers"
hexmask.quad.word 0x00 48.--63. 1. "ASID,ASID for the translation table base address"
hexmask.quad 0x00 1.--47. 0x2 "BADDR[47:1],Translation table base address"
newline
bitfld.quad 0x00 0. "CNP,Common not Private" "Not supported,Supported"
group.quad spr:0x35200++0x00
line.quad 0x00 "TTBR0_EL12,Translation Table Base Registers"
hexmask.quad.word 0x00 48.--63. 1. "ASID,ASID for the translation table base address"
hexmask.quad 0x00 1.--47. 0x2 "BADDR[47:1],Translation table base address"
newline
bitfld.quad 0x00 0. "CNP,Common not Private" "Not supported,Supported"
group.quad spr:0x35201++0x00
line.quad 0x00 "TTBR1_EL12,Translation Table Base Registers"
hexmask.quad.word 0x00 48.--63. 1. "ASID,ASID for the translation table base address"
hexmask.quad 0x00 1.--47. 0x2 "BADDR[47:1],Translation table base address"
newline
bitfld.quad 0x00 0. "CNP,Common not Private" "Not supported,Supported"
group.quad spr:0x34200++0x00
line.quad 0x00 "TTBR0_EL2,Translation Table Base Registers"
hexmask.quad 0x00 2.--47. 0x4 "BADDR[47:2],Translation table base address"
bitfld.quad 0x00 0. "CNP,Common not Private" "Not supported,Supported"
group.quad spr:0x34201++0x00
line.quad 0x00 "TTBR1_EL2,Translation Table Base Registers"
hexmask.quad.word 0x00 48.--63. 1. "ASID,ASID for the translation table base address"
hexmask.quad 0x00 1.--47. 0x2 "BADDR[47:1],Translation table base address"
newline
bitfld.quad 0x00 0. "CNP,Common not Private" "Not supported,Supported"
group.quad spr:0x36200++0x00
line.quad 0x00 "TTBR0_EL3,Translation Table Base Registers"
hexmask.quad 0x00 1.--47. 0x2 "BADDR[47:1],Translation table base address"
bitfld.quad 0x00 0. "CNP,Common not Private" "Not supported,Supported"
group.quad spr:0x34210++0x00
line.quad 0x00 "VTTBR_EL2,Virtualization Translation Table Base Register"
hexmask.quad.byte 0x00 48.--55. 1. "VMID,The VMID for the translation table"
hexmask.quad 0x00 4.--47. 0x10 "BADDR[47:4],Translation table base address"
newline
bitfld.quad 0x00 0. "CNP,Common not Private" "Not supported,Supported"
elif (CORENAME()=="CORTEXA55")
group.quad spr:0x30200++0x00
line.quad 0x00 "TTBR0_EL1,Translation Table Base Registers"
hexmask.quad.word 0x00 48.--63. 1. "ASID,ASID for the translation table base address"
hexmask.quad 0x00 2.--47. 0x4 "BADDR[47:2],Translation table base address"
newline
bitfld.quad 0x00 0. "CNP,Common not Private" "Not supported,Supported"
group.quad spr:0x30201++0x00
line.quad 0x00 "TTBR1_EL1,Translation Table Base Registers"
hexmask.quad.word 0x00 48.--63. 1. "ASID,ASID for the translation table base address"
hexmask.quad 0x00 2.--47. 0x4 "BADDR[47:2],Translation table base address"
newline
bitfld.quad 0x00 0. "CNP,Common not Private" "Not supported,Supported"
group.quad spr:0x35200++0x00
line.quad 0x00 "TTBR0_EL12,Translation Table Base Registers"
hexmask.quad.word 0x00 48.--63. 1. "ASID,ASID for the translation table base address"
hexmask.quad 0x00 2.--47. 0x4 "BADDR[47:2],Translation table base address"
newline
bitfld.quad 0x00 0. "CNP,Common not Private" "Not supported,Supported"
group.quad spr:0x35201++0x00
line.quad 0x00 "TTBR1_EL12,Translation Table Base Registers"
hexmask.quad.word 0x00 48.--63. 1. "ASID,ASID for the translation table base address"
hexmask.quad 0x00 2.--47. 0x4 "BADDR[47:2],Translation table base address"
newline
bitfld.quad 0x00 0. "CNP,Common not Private" "Not supported,Supported"
group.quad spr:0x34200++0x00
line.quad 0x00 "TTBR0_EL2,Translation Table Base Registers"
hexmask.quad.word 0x00 48.--63. 1. "ASID,ASID for the translation table base address"
hexmask.quad 0x00 2.--47. 0x4 "BADDR[47:2],Translation table base address"
newline
bitfld.quad 0x00 0. "CNP,Common not Private" "Not supported,Supported"
group.quad spr:0x34201++0x00
line.quad 0x00 "TTBR1_EL2,Translation Table Base Registers"
hexmask.quad.word 0x00 48.--63. 1. "ASID,ASID for the translation table base address"
hexmask.quad 0x00 2.--47. 0x4 "BADDR[47:2],Translation table base address"
newline
bitfld.quad 0x00 0. "CNP,Common not Private" "Not supported,Supported"
group.quad spr:0x36200++0x00
line.quad 0x00 "TTBR0_EL3,Translation Table Base Registers"
hexmask.quad 0x00 2.--47. 0x4 "BADDR[47:2],Translation table base address"
bitfld.quad 0x00 0. "CNP,Common not Private" "Not supported,Supported"
group.quad spr:0x34210++0x00
line.quad 0x00 "VTTBR_EL2,Virtualization Translation Table Base Register"
hexmask.quad.word 0x00 48.--63. 1. "VMID,The VMID for the translation table"
hexmask.quad 0x00 2.--47. 0x04 "BADDR[47:1],Translation table base address"
newline
bitfld.quad 0x00 0. "CNP,Common not Private" "Not supported,"
endif
group.quad spr:0x30202++0x00
line.quad 0x00 "TCR_EL1,Translation Control Registers"
bitfld.quad 0x00 50. "HWU162,Hardware use of bit[62] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR1_EL1/EL2" "Not possible,Possible"
bitfld.quad 0x00 49. "HWU161,Hardware use of bit[61] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR1_EL1/EL2" "Not possible,Possible"
newline
bitfld.quad 0x00 48. "HWU160,Hardware use of bit[60] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR1_EL1/EL2" "Not possible,Possible"
bitfld.quad 0x00 47. "HWU159,Hardware use of bit[59] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR1_EL1/EL2" "Not possible,Possible"
newline
bitfld.quad 0x00 46. "HWU062,Hardware use of bit[62] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR0_EL1/EL2" "Not possible,Possible"
bitfld.quad 0x00 45. "HWU061,Hardware use of bit[61] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR0_EL1/EL2" "Not possible,Possible"
newline
bitfld.quad 0x00 44. "HWU060,Hardware use of bit[60] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR0_EL1/EL2" "Not possible,Possible"
bitfld.quad 0x00 43. "HWU059,Hardware use of bit[59] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR0_EL1/EL2" "Not possible,Possible"
newline
bitfld.quad 0x00 42. "HPD1,Hierarchical Permission Disable for the TTBR1 region" "No,Yes"
bitfld.quad 0x00 41. "HPD0,Hierarchical Permission Disable for the TTBR0 region" "No,Yes"
newline
bitfld.quad 0x00 40. "HD,Hardware Update of the Dirty Bit Enable - Stage 1" "Disabled,Enabled"
bitfld.quad 0x00 39. "HA,Hardware Update of the Access Bit Enable - Stage 1" "Disabled,Enabled"
newline
bitfld.quad 0x00 38. "TBI1,Top Byte ignored" "Used,Ignored"
bitfld.quad 0x00 37. "TBI0,Top Byte ignored" "Used,Ignored"
newline
bitfld.quad 0x00 36. "AS,ASID Size" "8 bit,16 bit"
bitfld.quad 0x00 32.--34. "IPS,IPASize" "4GByte,64GByte,1TByte,?..."
newline
bitfld.quad 0x00 30.--31. "TG1,TTBR1_EL1 Granule size" "Reserved,16KByte,4KByte,64KByte"
bitfld.quad 0x00 28.--29. "SH1,Shareability attributes for TTBR1 as described in LPAE" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
newline
bitfld.quad 0x00 26.--27. "ORGN1,Outer Cacheability attributes for TTBR1 as described in LPAE" "Outer Non-cacheable,Outer WB WA cacheable,Outer WT cacheable,Outer WB no WA cacheable"
bitfld.quad 0x00 24.--25. "IRGN1,Inner Cacheability attributes for TTBR1 as described in LPAE" "Inner Non-cacheable,Inner WB WA cacheable,Inner WT cacheable,Inner WB no WA cacheable"
newline
bitfld.quad 0x00 23. "EPD1,Translation Table walk disable for TTBR1 as described in LPAE" "No,Yes"
bitfld.quad 0x00 22. "A1,ASID definition from TTBR0 or TTBR1" "TTBR0_EL1,TTBR1_EL1"
newline
bitfld.quad 0x00 16.--21. "T1SZ,Size offset of the memory region for TTBR1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.quad 0x00 14.--15. "TG0,TTBR0_ELx Granule size" "4KByte,64KByte,16KByte,?..."
newline
bitfld.quad 0x00 12.--13. "SH0,Shareability attributes for TTBR0 as described in LPAE" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
bitfld.quad 0x00 10.--11. "ORGN0,Outer Cacheability attributes for TTBR0 as described in LPAE" "Outer Non-cacheable,Outer WB WA cacheable,Outer WT cacheable,Outer WB no WA cacheable"
newline
bitfld.quad 0x00 8.--9. "IRGN0,Inner Cacheability attributes for TTBR0 as described in LPAE" "Inner Non-cacheable,Inner WB WA cacheable,Inner WT cacheable,Inner WB no WA cacheable"
bitfld.quad 0x00 7. "EPD0,Translation Table walk disable for TTBR0 as described in LPAE" "No,Yes"
newline
bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region for TTBR0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.quad spr:0x35202++0x00
line.quad 0x00 "TCR_EL12,Translation Control Registers"
bitfld.quad 0x00 50. "HWU162,Hardware use of bit[62] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR1_EL1/EL2" "Not possible,Possible"
bitfld.quad 0x00 49. "HWU161,Hardware use of bit[61] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR1_EL1/EL2" "Not possible,Possible"
newline
bitfld.quad 0x00 48. "HWU160,Hardware use of bit[60] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR1_EL1/EL2" "Not possible,Possible"
bitfld.quad 0x00 47. "HWU159,Hardware use of bit[59] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR1_EL1/EL2" "Not possible,Possible"
newline
bitfld.quad 0x00 46. "HWU062,Hardware use of bit[62] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR0_EL1/EL2" "Not possible,Possible"
bitfld.quad 0x00 45. "HWU061,Hardware use of bit[61] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR0_EL1/EL2" "Not possible,Possible"
newline
bitfld.quad 0x00 44. "HWU060,Hardware use of bit[60] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR0_EL1/EL2" "Not possible,Possible"
bitfld.quad 0x00 43. "HWU059,Hardware use of bit[59] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR0_EL1/EL2" "Not possible,Possible"
newline
bitfld.quad 0x00 42. "HPD1,Hierarchical Permission Disable for the TTBR1 region" "No,Yes"
bitfld.quad 0x00 41. "HPD0,Hierarchical Permission Disable for the TTBR0 region" "No,Yes"
newline
bitfld.quad 0x00 40. "HD,Hardware Update of the Dirty Bit Enable - Stage 1" "Disabled,Enabled"
bitfld.quad 0x00 39. "HA,Hardware Update of the Access Bit Enable - Stage 1" "Disabled,Enabled"
newline
bitfld.quad 0x00 38. "TBI1,Top Byte ignored" "Used,Ignored"
bitfld.quad 0x00 37. "TBI0,Top Byte ignored" "Used,Ignored"
newline
bitfld.quad 0x00 36. "AS,ASID Size" "8 bit,16 bit"
bitfld.quad 0x00 32.--34. "IPS,IPASize" "4GByte,64GByte,1TByte,?..."
newline
bitfld.quad 0x00 30.--31. "TG1,TTBR1_EL1 Granule size" "Reserved,16KByte,4KByte,64KByte"
bitfld.quad 0x00 28.--29. "SH1,Shareability attributes for TTBR1 as described in LPAE" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
newline
bitfld.quad 0x00 26.--27. "ORGN1,Outer Cacheability attributes for TTBR1 as described in LPAE" "Outer Non-cacheable,Outer WB WA cacheable,Outer WT cacheable,Outer WB no WA cacheable"
bitfld.quad 0x00 24.--25. "IRGN1,Inner Cacheability attributes for TTBR1 as described in LPAE" "Inner Non-cacheable,Inner WB WA cacheable,Inner WT cacheable,Inner WB no WA cacheable"
newline
bitfld.quad 0x00 23. "EPD1,Translation Table walk disable for TTBR1 as described in LPAE" "No,Yes"
bitfld.quad 0x00 22. "A1,ASID definition from TTBR0 or TTBR1" "TTBR0_EL1,TTBR1_EL1"
newline
bitfld.quad 0x00 16.--21. "T1SZ,Size offset of the memory region for TTBR1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.quad 0x00 14.--15. "TG0,TTBR0_ELx Granule size" "4KByte,64KByte,16KByte,?..."
newline
bitfld.quad 0x00 12.--13. "SH0,Shareability attributes for TTBR0 as described in LPAE" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
bitfld.quad 0x00 10.--11. "ORGN0,Outer Cacheability attributes for TTBR0 as described in LPAE" "Outer Non-cacheable,Outer WB WA cacheable,Outer WT cacheable,Outer WB no WA cacheable"
newline
bitfld.quad 0x00 8.--9. "IRGN0,Inner Cacheability attributes for TTBR0 as described in LPAE" "Inner Non-cacheable,Inner WB WA cacheable,Inner WT cacheable,Inner WB no WA cacheable"
bitfld.quad 0x00 7. "EPD0,Translation Table walk disable for TTBR0 as described in LPAE" "No,Yes"
newline
bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region for TTBR0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
if (((per.q(spr:0x34110))&0x400000000)==0x000000000)
group.quad spr:0x34202++0x00
line.quad 0x00 "TCR_EL2,Translation Control Registers"
bitfld.quad 0x00 28. "HWU62,Hardware usage of bit[62] of the stage1 translation table block or level 3 entry" "Not possible,Possible"
bitfld.quad 0x00 27. "HWU61,Hardware usage of bit[61] of the stage1 translation table block or level 3 entry" "Not possible,Possible"
newline
bitfld.quad 0x00 26. "HWU60,Hardware usage of bit[60] of the stage1 translation table block or level 3 entry" "Not possible,Possible"
bitfld.quad 0x00 25. "HWU59,Hardware usage of bit[59] of the stage1 translation table block or level 3 entry" "Not possible,Possible"
newline
bitfld.quad 0x00 24. "HPD,Hierarchical Permission Disable" "No,Yes"
bitfld.quad 0x00 22. "HD,Hardware Update of the Dirty Bit Enable - Stage 1" "Disabled,Enabled"
newline
bitfld.quad 0x00 21. "HA,Hardware Update of the Access Bit Enable - Stage 1" "Disabled,Enabled"
bitfld.quad 0x00 20. "TBI,Top Byte ignored" "Used,Ignored"
newline
bitfld.quad 0x00 16.--18. "PS,PASize" "4GByte,64GByte,1TByte,?..."
bitfld.quad 0x00 14.--15. "TG0,TTBR0_ELx Granule size" "4KByte,64KByte,16KByte,?..."
newline
bitfld.quad 0x00 12.--13. "SH0,Shareability attributes for TTBR_ELx as described in LPAE" "Non-shareable,Reserved,Outer shareable,Inner shareable"
bitfld.quad 0x00 10.--11. "ORGN0,Outer Cacheability attributes for TTBR_ELx as described in LPAE" "Outer Non-cacheable,Outer WB WA cacheable,Outer WT cacheable,Outer WB no WA cacheable"
newline
bitfld.quad 0x00 8.--9. "IRGN0,Inner Cacheability attributes for TTBR_ELx as described in LPAE" "Inner Non-cacheable,Inner WB WA cacheable,Inner WT cacheable,Inner WB no WA cacheable"
bitfld.quad 0x00 0.--5. "T0SZ,Size of virtual address for TTBR_ELx" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
else
group.quad spr:0x34202++0x00
line.quad 0x00 "TCR_EL2,Translation Control Registers"
bitfld.quad 0x00 50. "HWU162,Hardware use of bit[62] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR1_EL1/EL2" "Not possible,Possible"
bitfld.quad 0x00 49. "HWU161,Hardware use of bit[61] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR1_EL1/EL2" "Not possible,Possible"
newline
bitfld.quad 0x00 48. "HWU160,Hardware use of bit[60] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR1_EL1/EL2" "Not possible,Possible"
bitfld.quad 0x00 47. "HWU159,Hardware use of bit[59] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR1_EL1/EL2" "Not possible,Possible"
newline
bitfld.quad 0x00 46. "HWU062,Hardware use of bit[62] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR0_EL1/EL2" "Not possible,Possible"
bitfld.quad 0x00 45. "HWU061,Hardware use of bit[61] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR0_EL1/EL2" "Not possible,Possible"
newline
bitfld.quad 0x00 44. "HWU060,Hardware use of bit[60] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR0_EL1/EL2" "Not possible,Possible"
bitfld.quad 0x00 43. "HWU059,Hardware use of bit[59] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR0_EL1/EL2" "Not possible,Possible"
newline
bitfld.quad 0x00 42. "HPD1,Hierarchical Permission Disable for the TTBR1 region" "No,Yes"
bitfld.quad 0x00 41. "HPD0,Hierarchical Permission Disable for the TTBR0 region" "No,Yes"
newline
bitfld.quad 0x00 40. "HD,Hardware Update of the Dirty Bit Enable - Stage 1" "Disabled,Enabled"
bitfld.quad 0x00 39. "HA,Hardware Update of the Access Bit Enable - Stage 1" "Disabled,Enabled"
newline
bitfld.quad 0x00 38. "TBI1,Top Byte ignored" "Used,Ignored"
bitfld.quad 0x00 37. "TBI0,Top Byte ignored" "Used,Ignored"
newline
bitfld.quad 0x00 36. "AS,ASID Size" "8 bit,16 bit"
bitfld.quad 0x00 32.--34. "IPS,IPASize" "4GByte,64GByte,1TByte,?..."
newline
bitfld.quad 0x00 30.--31. "TG1,TTBR1_EL1 Granule size" "Reserved,16KByte,4KByte,64KByte"
bitfld.quad 0x00 28.--29. "SH1,Shareability attributes for TTBR1 as described in LPAE" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
newline
bitfld.quad 0x00 26.--27. "ORGN1,Outer Cacheability attributes for TTBR1 as described in LPAE" "Outer Non-cacheable,Outer WB WA cacheable,Outer WT cacheable,Outer WB no WA cacheable"
bitfld.quad 0x00 24.--25. "IRGN1,Inner Cacheability attributes for TTBR1 as described in LPAE" "Inner Non-cacheable,Inner WB WA cacheable,Inner WT cacheable,Inner WB no WA cacheable"
newline
bitfld.quad 0x00 23. "EPD1,Translation Table walk disable for TTBR1 as described in LPAE" "No,Yes"
bitfld.quad 0x00 22. "A1,ASID definition from TTBR0 or TTBR1" "TTBR0_EL1,TTBR1_EL1"
newline
bitfld.quad 0x00 16.--21. "T1SZ,Size offset of the memory region for TTBR1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.quad 0x00 14.--15. "TG0,TTBR0_ELx Granule size" "4KByte,64KByte,16KByte,?..."
newline
bitfld.quad 0x00 12.--13. "SH0,Shareability attributes for TTBR0 as described in LPAE" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
bitfld.quad 0x00 10.--11. "ORGN0,Outer Cacheability attributes for TTBR0 as described in LPAE" "Outer Non-cacheable,Outer WB WA cacheable,Outer WT cacheable,Outer WB no WA cacheable"
newline
bitfld.quad 0x00 8.--9. "IRGN0,Inner Cacheability attributes for TTBR0 as described in LPAE" "Inner Non-cacheable,Inner WB WA cacheable,Inner WT cacheable,Inner WB no WA cacheable"
bitfld.quad 0x00 7. "EPD0,Translation Table walk disable for TTBR0 as described in LPAE" "No,Yes"
newline
bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region for TTBR0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
if (CORENAME()=="CORTEXA75")
group.quad spr:0x36202++0x00
line.quad 0x00 "TCR_EL3,Translation Control Registers"
bitfld.quad 0x00 28. "HWU62,Hardware usage of bit[62] of the stage1 translation table block or level 3 entry" "Not possible,Possible"
bitfld.quad 0x00 27. "HWU61,Hardware usage of bit[61] of the stage1 translation table block or level 3 entry" "Not possible,Possible"
newline
bitfld.quad 0x00 26. "HWU60,Hardware usage of bit[60] of the stage1 translation table block or level 3 entry" "Not possible,Possible"
bitfld.quad 0x00 25. "HWU59,Hardware usage of bit[59] of the stage1 translation table block or level 3 entry" "Not possible,Possible"
newline
bitfld.quad 0x00 24. "HPD,Hierarchical Permission Disable" "No,Yes"
bitfld.quad 0x00 22. "HD,Hardware Update of the Dirty Bit Enable - Stage 1" "Disabled,Enabled"
newline
bitfld.quad 0x00 21. "HA,Hardware Update of the Access Bit Enable - Stage 1" "Disabled,Enabled"
bitfld.quad 0x00 20. "TBI,Top Byte ignored" "Used,Ignored"
newline
bitfld.quad 0x00 16.--18. "PS,PASize" "4GByte,64GByte,1TByte,4TByte,16TByte,256TB,4PB,?..."
bitfld.quad 0x00 14.--15. "TG0,TTBR0_ELx Granule size" "4KByte,64KByte,16KByte,?..."
newline
bitfld.quad 0x00 12.--13. "SH0,Shareability attributes for TTBR_ELx as described in LPAE" "Non-shareable,Reserved,Outer shareable,Inner shareable"
bitfld.quad 0x00 10.--11. "ORGN0,Outer Cacheability attributes for TTBR_ELx as described in LPAE" "Outer Non-cacheable,Outer WB WA cacheable,Outer WT cacheable,Outer WB no WA cacheable"
newline
bitfld.quad 0x00 8.--9. "IRGN0,Inner Cacheability attributes for TTBR_ELx as described in LPAE" "Inner Non-cacheable,Inner WB WA cacheable,Inner WT cacheable,Inner WB no WA cacheable"
bitfld.quad 0x00 0.--5. "T0SZ,Size of virtual address for TTBR_ELx" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
elif (CORENAME()=="CORTEXA55")
group.quad spr:0x36202++0x00
line.quad 0x00 "TCR_EL3,Translation Control Registers"
bitfld.quad 0x00 28. "HWU62,Hardware usage of bit[62] of the stage1 translation table block or level 3 entry" "Not possible,Possible"
bitfld.quad 0x00 27. "HWU61,Hardware usage of bit[61] of the stage1 translation table block or level 3 entry" "Not possible,Possible"
newline
bitfld.quad 0x00 26. "HWU60,Hardware usage of bit[60] of the stage1 translation table block or level 3 entry" "Not possible,Possible"
bitfld.quad 0x00 25. "HWU59,Hardware usage of bit[59] of the stage1 translation table block or level 3 entry" "Not possible,Possible"
newline
bitfld.quad 0x00 24. "HPD,Hierarchical Permission Disable" "No,Yes"
bitfld.quad 0x00 22. "HD,Hardware Update of the Dirty Bit Enable - Stage 1" "Disabled,Enabled"
newline
bitfld.quad 0x00 21. "HA,Hardware Update of the Access Bit Enable - Stage 1" "Disabled,Enabled"
bitfld.quad 0x00 20. "TBI,Top Byte ignored" "Used,Ignored"
newline
bitfld.quad 0x00 16.--18. "PS,PASize" "4GByte,64GByte,1TByte,?..."
bitfld.quad 0x00 14.--15. "TG0,TTBR0_ELx Granule size" "4KByte,64KByte,16KByte,?..."
newline
bitfld.quad 0x00 12.--13. "SH0,Shareability attributes for TTBR_ELx as described in LPAE" "Non-shareable,Reserved,Outer shareable,Inner shareable"
bitfld.quad 0x00 10.--11. "ORGN0,Outer Cacheability attributes for TTBR_ELx as described in LPAE" "Outer Non-cacheable,Outer WB WA cacheable,Outer WT cacheable,Outer WB no WA cacheable"
newline
bitfld.quad 0x00 8.--9. "IRGN0,Inner Cacheability attributes for TTBR_ELx as described in LPAE" "Inner Non-cacheable,Inner WB WA cacheable,Inner WT cacheable,Inner WB no WA cacheable"
bitfld.quad 0x00 0.--5. "T0SZ,Size of virtual address for TTBR_ELx" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
if (((per.q(spr:0x34212))&0xC000)==0x0)
group.quad spr:0x34212++0x00
line.quad 0x00 "VTCR_EL2,Virtualization Translation Control Register"
bitfld.quad 0x00 28. "HWU62,Hardware usage of bit[62] of the stage 2 translation table block or level 3 entry" "Not possible,Possible"
bitfld.quad 0x00 27. "HWU61,Hardware usage of bit[61] of the stage 2 translation table block or level 3 entry" "Not possible,Possible"
newline
bitfld.quad 0x00 26. "HWU60,Hardware usage of bit[60] of the stage 2 translation table block or level 3 entry" "Not possible,Possible"
bitfld.quad 0x00 25. "HWU59,Hardware usage of bit[59] of the stage 2 translation table block or level 3 entry" "Not possible,Possible"
newline
bitfld.quad 0x00 22. "HD,Hardware Update of the Dirty Bit Enable - Stage 2" "Disabled,Enabled"
bitfld.quad 0x00 21. "HA,Hardware Update of the Access Bit Enable - Stage 2" "Disabled,Enabled"
newline
bitfld.quad 0x00 19. "VS,VMID Size" "8-bit,16-bit"
bitfld.quad 0x00 16.--18. "PS,PASize" "4GByte,64GByte,1TByte,4TByte,16TByte,256TByte,?..."
newline
bitfld.quad 0x00 14.--15. "TG0,VTTBR0_EL2 Granule size" "4KByte,64KByte,16KByte,?..."
bitfld.quad 0x00 12.--13. "SH0,Shareability attributes for VTTBR_EL2 as described in LPAE" "Non-shareable,Reserved,Outer shareable,Inner shareable"
newline
bitfld.quad 0x00 10.--11. "ORGN0,Outer Cacheability attributes for VTTBR_EL2 as described in LPAE" "Outer Non-cacheable,Outer WB WA cacheable,Outer WT cacheable,Outer WB no WA cacheable"
bitfld.quad 0x00 8.--9. "IRGN0,Inner Cacheability attributes for VTTBR_EL2 as described in LPAE" "Inner Non-cacheable,Inner WB WA cacheable,Inner WT cacheable,Inner WB no WA cacheable"
newline
bitfld.quad 0x00 6.--7. "SL0,Starting level of the VTCR_EL2 addressed region" "Level 2,Level 1,Level 0,?..."
bitfld.quad 0x00 0.--5. "T0SZ,Size of virtual address for VTTBR_EL2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
else
group.quad spr:0x34212++0x00
line.quad 0x00 "VTCR_EL2,Virtualization Translation Control Register"
bitfld.quad 0x00 28. "HWU62,Hardware usage of bit[62] of the stage 2 translation table block or level 3 entry" "Not possible,Possible"
bitfld.quad 0x00 27. "HWU61,Hardware usage of bit[61] of the stage 2 translation table block or level 3 entry" "Not possible,Possible"
newline
bitfld.quad 0x00 26. "HWU60,Hardware usage of bit[60] of the stage 2 translation table block or level 3 entry" "Not possible,Possible"
bitfld.quad 0x00 25. "HWU59,Hardware usage of bit[59] of the stage 2 translation table block or level 3 entry" "Not possible,Possible"
newline
bitfld.quad 0x00 22. "HD,Hardware Update of the Dirty Bit Enable - Stage 2" "Disabled,Enabled"
bitfld.quad 0x00 21. "HA,Hardware Update of the Access Bit Enable - Stage 2" "Disabled,Enabled"
newline
bitfld.quad 0x00 19. "VS,VMID Size" "8-bit,16-bit"
bitfld.quad 0x00 16.--18. "PS,PASize" "4GByte,64GByte,1TByte,4TByte,16TByte,256TByte,?..."
newline
bitfld.quad 0x00 14.--15. "TG0,VTTBR0_EL2 Granule size" "4KByte,64KByte,16KByte,?..."
bitfld.quad 0x00 12.--13. "SH0,Shareability attributes for VTTBR_EL2 as described in LPAE" "Non-shareable,Reserved,Outer shareable,Inner shareable"
newline
bitfld.quad 0x00 10.--11. "ORGN0,Outer Cacheability attributes for VTTBR_EL2 as described in LPAE" "Outer Non-cacheable,Outer WB WA cacheable,Outer WT cacheable,Outer WB no WA cacheable"
bitfld.quad 0x00 8.--9. "IRGN0,Inner Cacheability attributes for VTTBR_EL2 as described in LPAE" "Inner Non-cacheable,Inner WB WA cacheable,Inner WT cacheable,Inner WB no WA cacheable"
newline
bitfld.quad 0x00 6.--7. "SL0,Starting level of the VTCR_EL2 addressed region" "Level 3,Level 2,Level 1,?..."
bitfld.quad 0x00 0.--5. "T0SZ,Size of virtual address for VTTBR_EL2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
if (CORENAME()=="CORTEXA75")
if (((per.q(spr:0x30740))&0xF000000000000001)==0x0000000000000000)
group.quad spr:0x30740++0x00
line.quad 0x00 "PAR_EL1,Physical Address Register"
bitfld.quad 0x00 60.--63. "ATTRH,Device memory or Normal memory plus Outer cacheability [Type/Cacheable/Allocate]" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
newline
bitfld.quad 0x00 56.--59. "ATTRL,Device memory or Normal memory plus Inner cacheability [Type/Cacheable/Allocate]" "Device-nGnRnE memory,---,---,---,Device-nGnRE memory,---,---,---,Device-nGRE memory,---,---,---,Device-GRE memory,---,---,---"
newline
hexmask.quad 0x00 12.--43. 0x10 "PA[47:12],Physical Address"
bitfld.quad 0x00 9. "NS,The NS attribute for a translation table entry read from Secure state" "No,Yes"
newline
bitfld.quad 0x00 7.--8. "SHA,Shareable attribute" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
newline
bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted"
elif ((((per.q(spr:0x30740))&0x01)==0x00)&&(((per.q(spr:0x30740))&0xF000000000000000)==(0x1000000000000000||0x2000000000000000||0x3000000000000000||0x5000000000000000||0x6000000000000000||0x7000000000000000)))
group.quad spr:0x30740++0x00
line.quad 0x00 "PAR_EL1,Physical Address Register"
bitfld.quad 0x00 60.--63. "ATTRH,Device memory or Normal memory plus Outer cacheability [Type/Cacheable/Allocate]" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
newline
newline
hexmask.quad 0x00 12.--43. 0x10 "PA[47:12],Physical Address"
bitfld.quad 0x00 9. "NS,The NS attribute for a translation table entry read from Secure state" "No,Yes"
newline
bitfld.quad 0x00 7.--8. "SHA,Shareable attribute" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
newline
bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted"
elif (((per.q(spr:0x30740))&0x01)==0x00)
group.quad spr:0x30740++0x00
line.quad 0x00 "PAR_EL1,Physical Address Register"
bitfld.quad 0x00 60.--63. "ATTRH,Device memory or Normal memory plus Outer cacheability [Type/Cacheable/Allocate]" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
newline
bitfld.quad 0x00 56.--59. "ATTRL,Device memory or Normal memory plus Inner cacheability [Type/Cacheable/Allocate]" "---,Inner Write-Through Transient W,Inner Write-Through Transient R,Inner Write-Through Transient RW,Inner Non-cacheable,Inner Write-Back Transient R,Inner Write-Back Transient W,Inner Write-Back Transient RW,Inner Write-Through Non-transient,Inner Write-Through Non-transient W,Inner Write-Through Non-transient R,Inner Write-Through Non-transient RW,Inner Write-Back Non-transient,Inner Write-Back Non-transient W,Inner Write-Back Non-transient R,Inner Write-Back Non-transient RW"
newline
hexmask.quad 0x00 12.--43. 0x10 "PA[47:12],Physical Address"
bitfld.quad 0x00 9. "NS,The NS attribute for a translation table entry read from Secure state" "No,Yes"
newline
bitfld.quad 0x00 7.--8. "SHA,Shareable attribute" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
newline
bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted"
else
group.quad spr:0x30740++0x00
line.quad 0x00 "PAR_EL1,Physical Address Register"
bitfld.quad 0x00 9. "S,Indicates the translation stage at which the translation aborted" "Stage 1,Stage 2"
bitfld.quad 0x00 8. "PTW,Translation aborted because of a stage 2 fault during a stage 1 translation table walk" "No,Yes"
newline
bitfld.quad 0x00 1.--6. "FST,Fault Status Field" "Address size fault/zeroth level/TTBR,Address size fault/first level,Address size fault/second level,Address size fault/third level,Translation fault/zeroth level,Translation fault/first level,Translation fault/second level,Translation fault/third level,Reserved,Access flag fault/first level,Access flag fault/second level,Access flag fault/third level,Reserved,Permission fault/first level,Permission fault/second level,Permission fault/third level,Synchronous external abort/not TTBR,Reserved,Reserved,Reserved,Synchronous external abort/TTBR/zeroth level,Synchronous external abort/TTBR/first level,Synchronous external abort/TTBR/second level,Synchronous external abort/TTBR/third level,Synchronous parity/ECC error/not TTBR,Reserved,Reserved,Reserved,Synchronous parity/ECC error/TTBR/zeroth level,Synchronous parity/ECC error/TTBR/first level,Synchronous parity/ECC error/TTBR/second level,Synchronous parity/ECC error/TTBR/third level,Reserved,Alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict abort,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain fault,Page Domain fault,Reserved"
newline
newline
newline
bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted"
endif
elif (CORENAME()=="CORTEXA55")
if (((per.q(spr:0x30740))&0xF000000000000001)==0x0000000000000000)
group.quad spr:0x30740++0x00
line.quad 0x00 "PAR_EL1,Physical Address Register"
bitfld.quad 0x00 60.--63. "ATTRH,Device memory or Normal memory plus Outer cacheability [Type/Cacheable/Allocate]" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
newline
bitfld.quad 0x00 56.--59. "ATTRL,Device memory or Normal memory plus Inner cacheability [Type/Cacheable/Allocate]" "Device-nGnRnE memory,---,---,---,Device-nGnRE memory,---,---,---,Device-nGRE memory,---,---,---,Device-GRE memory,---,---,---"
newline
hexmask.quad.long 0x00 12.--39. 0x10 "PA[39:12],Physical Address"
bitfld.quad 0x00 9. "NS,The NS attribute for a translation table entry read from Secure state" "No,Yes"
newline
bitfld.quad 0x00 7.--8. "SHA,Shareable attribute" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
newline
bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted"
elif ((((per.q(spr:0x30740))&0x01)==0x00)&&(((per.q(spr:0x30740))&0xF000000000000000)==(0x1000000000000000||0x2000000000000000||0x3000000000000000||0x5000000000000000||0x6000000000000000||0x7000000000000000)))
group.quad spr:0x30740++0x00
line.quad 0x00 "PAR_EL1,Physical Address Register"
bitfld.quad 0x00 60.--63. "ATTRH,Device memory or Normal memory plus Outer cacheability [Type/Cacheable/Allocate]" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
newline
newline
hexmask.quad.long 0x00 12.--39. 0x10 "PA[39:12],Physical Address"
bitfld.quad 0x00 9. "NS,The NS attribute for a translation table entry read from Secure state" "No,Yes"
newline
bitfld.quad 0x00 7.--8. "SHA,Shareable attribute" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
newline
bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted"
elif (((per.q(spr:0x30740))&0x01)==0x00)
group.quad spr:0x30740++0x00
line.quad 0x00 "PAR_EL1,Physical Address Register"
bitfld.quad 0x00 60.--63. "ATTRH,Device memory or Normal memory plus Outer cacheability [Type/Cacheable/Allocate]" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
newline
bitfld.quad 0x00 56.--59. "ATTRL,Device memory or Normal memory plus Inner cacheability [Type/Cacheable/Allocate]" "---,Inner Write-Through Transient W,Inner Write-Through Transient R,Inner Write-Through Transient RW,Inner Non-cacheable,Inner Write-Back Transient R,Inner Write-Back Transient W,Inner Write-Back Transient RW,Inner Write-Through Non-transient,Inner Write-Through Non-transient W,Inner Write-Through Non-transient R,Inner Write-Through Non-transient RW,Inner Write-Back Non-transient,Inner Write-Back Non-transient W,Inner Write-Back Non-transient R,Inner Write-Back Non-transient RW"
newline
hexmask.quad.long 0x00 12.--39. 0x10 "PA[39:12],Physical Address"
bitfld.quad 0x00 9. "NS,The NS attribute for a translation table entry read from Secure state" "No,Yes"
newline
bitfld.quad 0x00 7.--8. "SHA,Shareable attribute" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
newline
bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted"
else
group.quad spr:0x30740++0x00
line.quad 0x00 "PAR_EL1,Physical Address Register"
bitfld.quad 0x00 9. "S,Indicates the translation stage at which the translation aborted" "Stage 1,Stage 2"
bitfld.quad 0x00 8. "PTW,Translation aborted because of a stage 2 fault during a stage 1 translation table walk" "No,Yes"
newline
bitfld.quad 0x00 1.--6. "FST,Fault Status Field" "Address size fault/zeroth level/TTBR,Address size fault/first level,Address size fault/second level,Address size fault/third level,Translation fault/zeroth level,Translation fault/first level,Translation fault/second level,Translation fault/third level,Reserved,Access flag fault/first level,Access flag fault/second level,Access flag fault/third level,Reserved,Permission fault/first level,Permission fault/second level,Permission fault/third level,Synchronous external abort/not TTBR,Reserved,Reserved,Reserved,Synchronous external abort/TTBR/zeroth level,Synchronous external abort/TTBR/first level,Synchronous external abort/TTBR/second level,Synchronous external abort/TTBR/third level,Synchronous parity/ECC error/not TTBR,Reserved,Reserved,Reserved,Synchronous parity/ECC error/TTBR/zeroth level,Synchronous parity/ECC error/TTBR/first level,Synchronous parity/ECC error/TTBR/second level,Synchronous parity/ECC error/TTBR/third level,Reserved,Alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict abort,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain fault,Page Domain fault,Reserved"
newline
newline
newline
bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted"
endif
endif
newline
tree.open "Memory Attribute Indirection Registers"
if (CORENAME()=="CORTEXA75")
group.quad spr:0x30A20++0x00
line.quad 0x00 "MAIR_EL1,Memory Attribute Indirection Register (EL1)"
bitfld.quad 0x00 60.--63. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 56.--59. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.quad 0x00 52.--55. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 48.--51. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.quad 0x00 44.--47. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 40.--43. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.quad 0x00 36.--39. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 32.--35. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.quad 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.quad 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.quad 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.quad 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
group.quad spr:0x35A20++0x00
line.quad 0x00 "MAIR_EL12,Memory Attribute Indirection Register (EL12)"
bitfld.quad 0x00 60.--63. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 56.--59. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.quad 0x00 52.--55. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 48.--51. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.quad 0x00 44.--47. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 40.--43. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.quad 0x00 36.--39. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 32.--35. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.quad 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.quad 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.quad 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.quad 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
group.quad spr:0x34A20++0x00
line.quad 0x00 "MAIR_EL2,Memory Attribute Indirection Register (EL2)"
bitfld.quad 0x00 60.--63. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 56.--59. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.quad 0x00 52.--55. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 48.--51. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.quad 0x00 44.--47. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 40.--43. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.quad 0x00 36.--39. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 32.--35. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.quad 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.quad 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.quad 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.quad 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
group.quad spr:0x36A20++0x00
line.quad 0x00 "MAIR_EL3,Memory Attribute Indirection Register (EL3)"
bitfld.quad 0x00 60.--63. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 56.--59. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.quad 0x00 52.--55. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 48.--51. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.quad 0x00 44.--47. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 40.--43. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.quad 0x00 36.--39. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 32.--35. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.quad 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.quad 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.quad 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.quad 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
elif (CORENAME()=="CORTEXA55")
group.quad spr:0x30A20++0x00
line.quad 0x00 "MAIR_EL1,Memory Attribute Indirection Register (EL1)"
bitfld.quad 0x00 60.--63. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 56.--59. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.quad 0x00 52.--55. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 48.--51. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.quad 0x00 44.--47. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 40.--43. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.quad 0x00 36.--39. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 32.--35. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.quad 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.quad 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.quad 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.quad 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
group.quad spr:0x35A20++0x00
line.quad 0x00 "MAIR_EL12,Memory Attribute Indirection Register (EL12)"
bitfld.quad 0x00 60.--63. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 56.--59. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.quad 0x00 52.--55. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 48.--51. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.quad 0x00 44.--47. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 40.--43. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.quad 0x00 36.--39. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 32.--35. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.quad 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.quad 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.quad 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.quad 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
group.quad spr:0x34A20++0x00
line.quad 0x00 "MAIR_EL2,Memory Attribute Indirection Register (EL2)"
bitfld.quad 0x00 60.--63. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 56.--59. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.quad 0x00 52.--55. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 48.--51. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.quad 0x00 44.--47. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 40.--43. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.quad 0x00 36.--39. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 32.--35. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.quad 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.quad 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.quad 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.quad 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
group.quad spr:0x36A20++0x00
line.quad 0x00 "MAIR_EL3,Memory Attribute Indirection Register (EL3)"
bitfld.quad 0x00 60.--63. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 56.--59. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.quad 0x00 52.--55. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 48.--51. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.quad 0x00 44.--47. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 40.--43. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.quad 0x00 36.--39. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 32.--35. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.quad 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.quad 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.quad 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.quad 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
endif
group.quad spr:0x30A30++0x00
line.quad 0x00 "AMAIR_EL1,Auxiliary Memory Attribute Indirection Register"
group.quad spr:0x35A30++0x00
line.quad 0x00 "AMAIR_EL12,Auxiliary Memory Attribute Indirection Register"
group.quad spr:0x34A30++0x00
line.quad 0x00 "AMAIR_EL2,Auxiliary Memory Attribute Indirection Register"
group.quad spr:0x36A30++0x00
line.quad 0x00 "AMAIR_EL3,Auxiliary Memory Attribute Indirection Register"
tree.end
newline
group.quad spr:0x34300++0x00
line.quad 0x00 "DACR32_EL2,Domain Access Control Register"
bitfld.quad 0x00 30.--31. "D15,Domain 15 access permission" "No access,Client,Reserved,Manager"
bitfld.quad 0x00 28.--29. "D14,Domain 14 access permission" "No access,Client,Reserved,Manager"
newline
bitfld.quad 0x00 26.--27. "D13,Domain 13 access permission" "No access,Client,Reserved,Manager"
bitfld.quad 0x00 24.--25. "D12,Domain 12 access permission" "No access,Client,Reserved,Manager"
newline
bitfld.quad 0x00 22.--23. "D11,Domain 11 access permission" "No access,Client,Reserved,Manager"
bitfld.quad 0x00 20.--21. "D10,Domain 10 access permission" "No access,Client,Reserved,Manager"
newline
bitfld.quad 0x00 18.--19. "D9,Domain 9 access permission" "No access,Client,Reserved,Manager"
bitfld.quad 0x00 16.--17. "D8,Domain 8 access permission" "No access,Client,Reserved,Manager"
newline
bitfld.quad 0x00 14.--15. "D7,Domain 7 access permission" "No access,Client,Reserved,Manager"
bitfld.quad 0x00 12.--13. "D6,Domain 6 access permission" "No access,Client,Reserved,Manager"
newline
bitfld.quad 0x00 10.--11. "D5,Domain 5 access permission" "No access,Client,Reserved,Manager"
bitfld.quad 0x00 8.--9. "D4,Domain 4 access permission" "No access,Client,Reserved,Manager"
newline
bitfld.quad 0x00 6.--7. "D3,Domain 3 access permission" "No access,Client,Reserved,Manager"
bitfld.quad 0x00 4.--5. "D2,Domain 2 access permission" "No access,Client,Reserved,Manager"
newline
bitfld.quad 0x00 2.--3. "D1,Domain 1 access permission" "No access,Client,Reserved,Manager"
bitfld.quad 0x00 0.--1. "D0,Domain 0 access permission" "No access,Client,Reserved,Manager"
tree.end
tree "Virtualization Extensions"
group.quad spr:0x34111++0x00
line.quad 0x00 "MDCR_EL2,Monitor Debug Configuration Register"
bitfld.quad 0x00 17. "HPMD,Hypervisor performance monitors disable" "No,Yes"
newline
bitfld.quad 0x00 14. "TPMS,Trap Performance Monitor Sampling" "No trap,Trap"
newline
bitfld.quad 0x00 11. "TDRA,Trap valid EL1 and EL0 access to debug ROM address registers to EL2" "No trap,Trap"
bitfld.quad 0x00 10. "TDOSA,Trap valid accesses to OS-related debug registers to EL2" "No trap,Trap"
bitfld.quad 0x00 9. "TDA,Trap valid Non-secure accesses to Debug registers to EL2" "No trap,Trap"
newline
bitfld.quad 0x00 8. "TDE,Route debug exceptions from Non-secure EL1 and EL0 to EL2" "Disabled,Enabled"
bitfld.quad 0x00 7. "HPME,Hypervisor Performance Monitors Enable" "Disabled,Enabled"
bitfld.quad 0x00 6. "TPM,Trap Non-secure EL0 and EL1 accesses to Performance Monitors registers that are not UNALLOCATED to EL2" "No trap,Trap"
newline
bitfld.quad 0x00 5. "TPMCR,Trap Non-secure EL0 and EL1 accesses to PMCR_EL0 to EL2" "No trap,Trap"
bitfld.quad 0x00 0.--4. "HPMN,Defines the number of Performance Monitors counters accessible from non-secure EL0/EL1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.quad spr:0x36131++0x00
line.quad 0x00 "MDCR_EL3,Monitor Debug Configuration Register"
bitfld.quad 0x00 21. "EPMAD,External debugger to Performance Monitor registers access disable" "No,Yes"
bitfld.quad 0x00 20. "EDAD,External debugger access to breakpoint and watchpoint registers disabled" "No,Yes"
bitfld.quad 0x00 17. "SPME,Secure performance monitors enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 16. "SDD,Secure self-hosted invasive debug disable" "No,Yes"
newline
bitfld.quad 0x00 14.--15. "SPD32,AArch32 secure privileged debug" "Legacy mode,Reserved,Disabled,Enabled"
bitfld.quad 0x00 10. "TDOSA,Trap valid accesses to OS-related debug registers to EL3" "No trap,Trap"
bitfld.quad 0x00 9. "TDA,Trap valid Non-secure accesses to Debug registers to EL3" "No trap,Trap"
newline
bitfld.quad 0x00 6. "TPM,Trap Non-secure EL0/EL1/EL2 accesses to Performance Monitors registers that are not UNALLOCATED or trapped to a lower exception level to EL3" "No trap,Trap"
rgroup.quad spr:0x30012++0x00
line.quad 0x00 "ID_DFR0_EL1,Debug Feature Register"
bitfld.quad 0x00 24.--27. "PMM,Performance Monitor Model Support" "Reserved,Reserved,Reserved,Reserved,Supported/16-bit evtCount,?..."
bitfld.quad 0x00 20.--23. "MDM_MM,Memory-mapped Debug Model for M profile processors Support" "Not supported,?..."
bitfld.quad 0x00 16.--19. "TM_MM,Trace Model (Memory-Mapped) Support" "Reserved,Supported,?..."
newline
bitfld.quad 0x00 12.--15. "CTM_CB,Coprocessor-Based Trace Debug Model Support" "Not supported,?..."
bitfld.quad 0x00 4.--7. "SDM_CB,Secure Debug Model (Coprocessor) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Support v8.2,?..."
bitfld.quad 0x00 0.--3. "CDM_CB,Coprocessor Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Support v8.2,?..."
tree.end
tree "Cache Control and Configuration"
rgroup.quad spr:0x30F00++0x00
line.quad 0x00 "CPUCFR_EL1, CPU Configuration Register (EL1)"
bitfld.quad 0x00 2. "SCU,Indicates whether the SCU is present or not" "Present,?..."
bitfld.quad 0x00 0.--1. "ECC,Indicates whether ECC is present or not" "Not present,Present,?..."
if (CORENAME()=="CORTEXA75")
group.quad spr:0x30F27++0x00
line.quad 0x00 "CPUPWRCTLR_EL1,Power Control Register (EL1)"
bitfld.quad 0x00 7.--9. "WFE_RET_CTRL,CPU WFE retention control. Specifies the number of Architectural Timer ticks required before retention entry" "Disabled,2 AT ticks,8 AT ticks,32 AT ticks,64 AT ticks,128 AT ticks,256 AT ticks,512 AT ticks"
bitfld.quad 0x00 4.--6. "WFI_RET_CTRL,CPU WFI retention control. Specifies the number of Architectural Timer ticks required before retention entry" "Disabled,2 AT ticks,8 AT ticks,32 AT ticks,64 AT ticks,128 AT ticks,256 AT ticks,512 AT ticks"
bitfld.quad 0x00 0. "CORE_PWRDN_EN,Indicates to the power controller if the CPU wants to power down when it enters WFI state" "Not requested,Requested"
elif (CORENAME()=="CORTEXA55")
group.quad spr:0x30F27++0x00
line.quad 0x00 "CPUPWRCTLR_EL1,Power Control Register (EL1)"
bitfld.quad 0x00 10.--12. "SIMD_RET_CTRL,Advanced SIMD and floating-point retention control. Specifies the number of Architectural Timer ticks required before retention entry" "Disabled,2 AT ticks,8 AT ticks,32 AT ticks,64 AT ticks,128 AT ticks,256 AT ticks,512 AT ticks"
bitfld.quad 0x00 7.--9. "WFE_RET_CTRL,CPU WFE retention control. Specifies the number of Architectural Timer ticks required before retention entry" "Disabled,2 AT ticks,8 AT ticks,32 AT ticks,64 AT ticks,128 AT ticks,256 AT ticks,512 AT ticks"
bitfld.quad 0x00 4.--6. "WFI_RET_CTRL,CPU WFI retention control. Specifies the number of Architectural Timer ticks required before retention entry" "Disabled,2 AT ticks,8 AT ticks,32 AT ticks,64 AT ticks,128 AT ticks,256 AT ticks,512 AT ticks"
newline
bitfld.quad 0x00 0. "CORE_PWRDN_EN,Indicates to the power controller if the CPU wants to power down when it enters WFI state" "Not requested,Requested"
endif
rgroup.quad spr:0x33001++0x00
line.quad 0x00 "CTR_EL0,Cache Type Register"
bitfld.quad 0x0 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
bitfld.quad 0x0 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
bitfld.quad 0x0 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
newline
bitfld.quad 0x0 14.--15. "VIPT,Instruction cache policy" "Reserved,Reserved,VIPT,?..."
bitfld.quad 0x0 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
if (((per.q(spr:0x32000))&0xE)==(0x02||0x04))
group.quad spr:0x32000++0x00
line.quad 0x00 "CSSELR_EL1,Cache Size Selection Register"
bitfld.quad 0x00 1.--3. "LEVEL,Cache level of required cache" "Level 1,Level 2,Level 3,?..."
bitfld.quad 0x00 0. "IND,Instruction/Not Data" "Data/Unified,?..."
else
group.quad spr:0x32000++0x00
line.quad 0x00 "CSSELR_EL1,Cache Size Selection Register"
bitfld.quad 0x00 1.--3. "LEVEL,Cache level of required cache" "Level 1,Level 2,Level 3,?..."
bitfld.quad 0x00 0. "IND,Instruction/Not Data" "Data/Unified,Instruction"
endif
rgroup.quad spr:0x31000++0x00
line.quad 0x00 "CCSIDR_EL1,Cache Size and ID register"
bitfld.quad 0x00 31. "WT,Indicates whether the selected cache level supports Write-Through" "Not Supported,?..."
bitfld.quad 0x00 30. "WB,Indicates whether the selected cache level supports Write-Back" "Not Supported,Supported"
bitfld.quad 0x00 29. "RA,Indicates whether the selected cache level supports read-allocation" "Not Supported,Supported"
newline
bitfld.quad 0x00 28. "WA,Indicates whether the selected cache level supports write-allocation" "Not Supported,Supported"
hexmask.quad.word 0x00 13.--27. 1. 1. "SETS,Number of Sets"
hexmask.quad.word 0x00 3.--12. 1. 1. "ASSOC,Associativity"
newline
bitfld.quad 0x00 0.--2. "LSIZE,Line Size" "Reserved,Reserved,64 bytes,?..."
if (CORENAME()=="CORTEXA75")
rgroup.quad spr:0x31001++0x00
line.quad 0x00 "CLIDR_EL1,Cache Level ID register"
bitfld.quad 0x00 30.--32. "ICB,Inner cache boundary" "Reserved,Reserved,L2 highest,L3 highest,?..."
bitfld.quad 0x00 27.--29. "LOUU,Level of Unification Uniprocessor" "Not required,?..."
bitfld.quad 0x00 24.--26. "LOC,Level of Coherency" "Reserved,Reserved,No L3 cache,L3 cache,?..."
newline
bitfld.quad 0x00 21.--23. "LOUIS,Level of Unification Inner Shareable" "No cache,?..."
bitfld.quad 0x00 6.--8. "CTYPE3,Cache type for levels 3" "No cache,Reserved,Reserved,Reserved,Unified,?..."
bitfld.quad 0x00 3.--5. "CTYPE2,Cache type for levels 2" "Reserved,Reserved,Reserved,Reserved,Unified,?..."
newline
bitfld.quad 0x00 0.--2. "CTYPE1,Cache type for levels 1" "Reserved,Reserved,Reserved,Separate,?..."
elif (CORENAME()=="CORTEXA55")
rgroup.quad spr:0x31001++0x00
line.quad 0x00 "CLIDR_EL1,Cache Level ID register"
bitfld.quad 0x00 30.--32. "ICB,Inner cache boundary" "Reserved,L1 highest,L2 highest,L3 highest,?..."
bitfld.quad 0x00 27.--29. "LOUU,Level of Unification Uniprocessor" "Not required,?..."
bitfld.quad 0x00 24.--26. "LOC,Level of Coherency" "Reserved,No cache,L2 or L3 cache,L2 and L3 cache,?..."
newline
bitfld.quad 0x00 21.--23. "LOUIS,Level of Unification Inner Shareable" "Not required,?..."
bitfld.quad 0x00 6.--8. "CTYPE3,Cache type for levels 3" "No cache,Reserved,Reserved,Reserved,L2 and L3 cache,?..."
bitfld.quad 0x00 3.--5. "CTYPE2,Cache type for levels 2" "No cache,Reserved,Reserved,Reserved,Unified,?..."
newline
bitfld.quad 0x00 0.--2. "CTYPE1,Cache type for levels 1" "Reserved,Reserved,Reserved,Separate,?..."
endif
tree "Level 1 memory system"
rgroup.quad spr:0x36F00++0x00
line.quad 0x00 "CDBGDR0_EL3,Data Register 0"
rgroup.quad spr:0x36F01++0x00
line.quad 0x00 "CDBGDR1_EL3,Data Register 1"
rgroup.quad spr:0x36F02++0x00
line.quad 0x00 "CDBGDR2_EL3,Data Register 2"
wgroup.quad spr:0x16F20++0x00
line.quad 0x00 "CDBGDCT_EL3,Data Cache Tag Read Operation Register"
wgroup.quad spr:0x16F21++0x00
line.quad 0x00 "CDBGICT_EL3,Instruction Cache Tag Read Operation Register"
wgroup.quad spr:0x16F22++0x00
line.quad 0x00 "CDBGTT_EL3,TLB Tag Read Operation Register"
wgroup.quad spr:0x16F40++0x00
line.quad 0x00 "CDBGDCD_EL3,Data Cache Data Read Operation Register"
wgroup.quad spr:0x16F41++0x00
line.quad 0x00 "CDBGICD_EL3,Instruction Cache Data Read Operation Register"
wgroup.quad spr:0x16F42++0x00
line.quad 0x00 "CDBGTD_EL3,TLB Data Read Operation Register"
tree.end
tree.end
tree "System Performance Monitor"
group.quad spr:0x339C0++0x00
line.quad 0x00 "PMCR_EL0,Performance Monitors Control Register"
hexmask.quad.byte 0x00 24.--31. 1. "IMP,Implementer code"
hexmask.quad.byte 0x00 16.--23. 1. "IDCODE,Identification code"
bitfld.quad 0x00 11.--15. "N,Number of counters implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 6. "LC,Long cycle counter enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 5. "DP,Disable CCNT when event counting prohibited" "No,Yes"
bitfld.quad 0x00 4. "X,Export of events Enable" "Disabled,Enabled"
bitfld.quad 0x00 3. "D,Clock Divider" "Every cycle,64th cycle"
bitfld.quad 0x00 2. "C,Clock Counter Reset" "No reset,Reset"
newline
bitfld.quad 0x00 1. "P,Performance Counter Reset" "No reset,Reset"
bitfld.quad 0x00 0. "E,All Counters Enable" "Disabled,Enabled"
group.quad spr:0x339C1++0x00
line.quad 0x00 "PMCNTENSET_EL0,Count Enable Set register"
bitfld.quad 0x00 31. "C,Enables the cycle counter register" "Disabled,Enabled"
newline
bitfld.quad 0x00 5. "P5,Event counter PMN 5 enable bit" "Disabled,Enabled"
bitfld.quad 0x00 4. "P4,Event counter PMN 4 enable bit" "Disabled,Enabled"
bitfld.quad 0x00 3. "P3,Event counter PMN 3 enable bit" "Disabled,Enabled"
newline
bitfld.quad 0x00 2. "P2,Event counter PMN 2 enable bit" "Disabled,Enabled"
bitfld.quad 0x00 1. "P1,Event counter PMN 1 enable bit" "Disabled,Enabled"
bitfld.quad 0x00 0. "P0,Event counter PMN 0 enable bit" "Disabled,Enabled"
group.quad spr:0x339C2++0x00
line.quad 0x00 "PMCNTENCLR_EL0,Count Enable Clear register"
bitfld.quad 0x00 31. "C,Disables the cycle counter register" "Disabled,Enabled"
newline
bitfld.quad 0x00 5. "P5,PMN5 overflow" "No overflow,Overflow"
bitfld.quad 0x00 4. "P4,PMN4 overflow" "No overflow,Overflow"
bitfld.quad 0x00 3. "P3,PMN3 overflow" "No overflow,Overflow"
newline
bitfld.quad 0x00 2. "P2,PMN2 overflow" "No overflow,Overflow"
bitfld.quad 0x00 1. "P1,PMN1 overflow" "No overflow,Overflow"
bitfld.quad 0x00 0. "P0,PMN0 overflow" "No overflow,Overflow"
group.quad spr:0x339C3++0x00
line.quad 0x00 "PMOVSCLR_EL0,Overflow Status Flags Clear register"
eventfld.quad 0x00 31. "C,PMCCNTR overflow" "No overflow,Overflow"
newline
eventfld.quad 0x00 5. "P5,PMN5 overflow" "No overflow,Overflow"
eventfld.quad 0x00 4. "P4,PMN4 overflow" "No overflow,Overflow"
eventfld.quad 0x00 3. "P3,PMN3 overflow" "No overflow,Overflow"
newline
eventfld.quad 0x00 2. "P2,PMN2 overflow" "No overflow,Overflow"
eventfld.quad 0x00 1. "P1,PMN1 overflow" "No overflow,Overflow"
eventfld.quad 0x00 0. "P0,PMN0 overflow" "No overflow,Overflow"
wgroup.quad spr:0x339C4++0x00
line.quad 0x00 "PMSWINC_EL0,Software Increment register"
bitfld.quad 0x00 5. "P5,PMN5 software increment" "Disabled,Enabled"
bitfld.quad 0x00 4. "P4,PMN4 software increment" "Disabled,Enabled"
bitfld.quad 0x00 3. "P3,PMN3 software increment" "Disabled,Enabled"
newline
bitfld.quad 0x00 2. "P2,PMN2 software increment" "Disabled,Enabled"
bitfld.quad 0x00 1. "P1,PMN1 software increment" "Disabled,Enabled"
bitfld.quad 0x00 0. "P0,PMN0 software increment" "Disabled,Enabled"
group.quad spr:0x339C5++0x00
line.quad 0x00 "PMSELR_EL0,Event Counter Selection Register"
bitfld.quad 0x00 0.--4. "SEL,Current event counter select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
tree.open "Common Event Identification Registers"
rgroup.quad spr:0x339C6++0x00
line.quad 0x00 "PMCEID0_EL0,Common Event Identification register"
bitfld.quad 0x00 31. "L1D_CACHE_ALLOCATE,Level 1 data cache allocate" "Not implemented,Implemented"
bitfld.quad 0x00 30. "CHAIN,Chain" "Not implemented,Implemented"
bitfld.quad 0x00 29. "BUS_CYCLES,Bus cycle" "Not implemented,Implemented"
newline
bitfld.quad 0x00 28. "TTBR_WRITE_RETIRED,TTBR write retired" "Not implemented,Implemented"
bitfld.quad 0x00 27. "INST_SPEC,Instruction speculatively executed" "Not implemented,Implemented"
bitfld.quad 0x00 26. "MEMORY_ERROR,Local memory error" "Not implemented,Implemented"
newline
bitfld.quad 0x00 25. "BUS_ACCESS,Bus access" "Not implemented,Implemented"
bitfld.quad 0x00 24. "L2D_CACHE_WB,Level 2 data cache write-back" "Not implemented,Implemented"
bitfld.quad 0x00 23. "L2D_CACHE_REFILL,Level 2 data cache refill" "Not implemented,Implemented"
newline
bitfld.quad 0x00 22. "L2D_CACHE,Level 2 data cache access" "Not implemented,Implemented"
bitfld.quad 0x00 21. "L1D_CACHE_WB,Level 1 data cache write-back" "Not implemented,Implemented"
bitfld.quad 0x00 20. "L1I_CACHE,Level 1 instruction cache access" "Not implemented,Implemented"
newline
bitfld.quad 0x00 19. "MEM_ACCESS,Data memory access" "Not implemented,Implemented"
bitfld.quad 0x00 18. "BR_PRED,Predictable branch speculatively executed" "Not implemented,Implemented"
bitfld.quad 0x00 17. "CPU_CYCLES,CPU Cycle" "Not implemented,Implemented"
newline
bitfld.quad 0x00 16. "BR_MIS_PRED,Mispredicted or not predicted branch speculatively executed" "Not implemented,Implemented"
bitfld.quad 0x00 15. "UNALIGNED_LDST_RETIRED,UNALIGNED_LDST_RETIRED" "Not implemented,Implemented"
bitfld.quad 0x00 14. "BR_RETURN_RETIRED,Instruction architecturally executed condition check pass procedure return" "Not implemented,Implemented"
newline
bitfld.quad 0x00 13. "BR_IMMED_RETIRED,Instruction architecturally executed immediate branch" "Not implemented,Implemented"
bitfld.quad 0x00 12. "PC_WRITE_RETIRED,Instruction architecturally executed condition check pass software change of the PC" "Not implemented,Implemented"
bitfld.quad 0x00 11. "CID_WRITE_RETIRED,Instruction architecturally executed condition check pass write to CONTEXTIDR" "Not implemented,Implemented"
newline
bitfld.quad 0x00 10. "EXC_RETURN,Instruction architecturally executed condition check pass exception return" "Not implemented,Implemented"
bitfld.quad 0x00 9. "EXC_TAKEN,Exception taken" "Not implemented,Implemented"
bitfld.quad 0x00 8. "INST_RETIRED,Instruction architecturally executed" "Not implemented,Implemented"
newline
bitfld.quad 0x00 7. "ST_RETIRED,Instruction architecturally executed condition check pass store" "Not implemented,Implemented"
bitfld.quad 0x00 6. "LD_RETIRED,Instruction architecturally executed condition check pass load" "Not implemented,Implemented"
bitfld.quad 0x00 5. "L1D_TLB_REFILL,Level 1 data TLB refill" "Not implemented,Implemented"
newline
bitfld.quad 0x00 4. "L1D_CACHE,Level 1 data cache access" "Not implemented,Implemented"
bitfld.quad 0x00 3. "L1D_CACHE_REFILL,Level 1 data cache refill" "Not implemented,Implemented"
bitfld.quad 0x00 2. "L1I_TLB_REFILL,Level 1 instruction TLB refill" "Not implemented,Implemented"
newline
bitfld.quad 0x00 1. "L1I_CACHE_REFILL,Level 1 instruction cache refill" "Not implemented,Implemented"
bitfld.quad 0x00 0. "SW_INCR,Instruction architecturally executed condition check pass software increment" "Not implemented,Implemented"
if (CORENAME()=="CORTEXA75")
rgroup.quad spr:0x339C7++0x00
line.quad 0x00 "PMCEID1_EL0,Common Event Identification register"
bitfld.quad 0x00 24. "REMOTE_ACCESS,Access to another socket in a multi-socket system" "Not implemented,Implemented"
bitfld.quad 0x00 23. "LL_CACHE_MISS_RD,Last Level cache miss read" "Not implemented,Implemented"
bitfld.quad 0x00 22. "LL_CACHE_RD,Last Level cache access read" "Not implemented,Implemented"
newline
bitfld.quad 0x00 21. "ITLB_WALK,Access to instruction TLB that caused a page table walk" "Not implemented,Implemented"
bitfld.quad 0x00 20. "DTLB_WALK,Access to data TLB that caused a page table walk" "Not implemented,Implemented"
bitfld.quad 0x00 16. "L2I_TLB,Attributable Level 2 instruction TLB access" "Not implemented,Implemented"
newline
bitfld.quad 0x00 15. "L2D_TLB,Attributable Level 2 data or unified TLB access" "Not implemented,Implemented"
bitfld.quad 0x00 13. "L2D_TLB_REFILL,Attributable Level 2 data or unified TLB refill" "Not implemented,Implemented"
bitfld.quad 0x00 11. "L3D_CACHE,Attributable Level 3 data or unified cache access" "Not implemented,Implemented"
newline
bitfld.quad 0x00 10. "L3D_CACHE_REFILL,Attributable Level 3 data or unified cache refill" "Not implemented,Implemented"
bitfld.quad 0x00 9. "L3D_CACHE_ALLOCATE,Attributable Level 3 data or unified cache allocation without refill" "Not implemented,Implemented"
bitfld.quad 0x00 6. "L1I_TLB,Level 1 instruction TLB access" "Not implemented,Implemented"
newline
bitfld.quad 0x00 5. "L1D_TLB,Level 1 data or unified TLB access" "Not implemented,Implemented"
bitfld.quad 0x00 4. "STALL_BACKEND,No operation issued due to backend" "Not implemented,Implemented"
bitfld.quad 0x00 3. "STALL_FRONTEND,No operation issued due to the frontend" "Not implemented,Implemented"
newline
bitfld.quad 0x00 1. "BR_RETIRED,Instruction architecturally executed branch" "Not implemented,Implemented"
bitfld.quad 0x00 0. "L2D_CACHE_ALLOCATE,Level 2 data cache allocate" "Not implemented,Implemented"
elif (CORENAME()=="CORTEXA55")
rgroup.quad spr:0x339C7++0x00
line.quad 0x00 "PMCEID1_EL0,Common Event Identification register"
bitfld.quad 0x00 23. "LL_CACHE_MISS_RD,Last Level cache miss read" "Not implemented,Implemented"
bitfld.quad 0x00 22. "LL_CACHE_RD,Last Level cache access read" "Not implemented,Implemented"
bitfld.quad 0x00 21. "ITLB_WALK,Access to instruction TLB that caused a page table walk" "Not implemented,Implemented"
newline
bitfld.quad 0x00 20. "DTLB_WALK,Access to data TLB that caused a page table walk" "Not implemented,Implemented"
bitfld.quad 0x00 17. "REMOTE_ACCESS,Access to another socket in a multi-socket system" "Not implemented,Implemented"
bitfld.quad 0x00 16. "L2I_TLB,Attributable Level 2 instruction TLB access" "Not implemented,Implemented"
newline
bitfld.quad 0x00 15. "L2D_TLB,Attributable Level 2 data or unified TLB access" "Not implemented,Implemented"
bitfld.quad 0x00 14. "L2I_TLB_REFILL,Attributable Level 2 instruction TLB refill" "Not implemented,Implemented"
bitfld.quad 0x00 13. "L2D_TLB_REFILL,Attributable Level 2 data or unified TLB refill" "Not implemented,Implemented"
newline
bitfld.quad 0x00 12. "L3D_CACHE_WB,Attributable Level 3 data or unified cache write-back" "Not implemented,Implemented"
bitfld.quad 0x00 11. "L3D_CACHE,Attributable Level 3 data or unified cache access" "Not implemented,Implemented"
bitfld.quad 0x00 10. "L3D_CACHE_REFILL,Attributable Level 3 data or unified cache refill" "Not implemented,Implemented"
newline
bitfld.quad 0x00 9. "L3D_CACHE_ALLOCATE,Attributable Level 3 data or unified cache allocation without refill" "Not implemented,Implemented"
bitfld.quad 0x00 8. "L2I_CACHE_REFILL,Attributable Level 2 instruction cache refill" "Not implemented,Implemented"
bitfld.quad 0x00 7. "L2I_CACHE,Attributable Level 2 instruction cache access" "Not implemented,Implemented"
newline
bitfld.quad 0x00 6. "L1I_TLB,Level 1 instruction TLB access" "Not implemented,Implemented"
bitfld.quad 0x00 5. "L1D_TLB,Level 1 data or unified TLB access" "Not implemented,Implemented"
bitfld.quad 0x00 4. "STALL_BACKEND,No operation issued due to backend" "Not implemented,Implemented"
newline
bitfld.quad 0x00 3. "STALL_FRONTEND,No operation issued due to the frontend" "Not implemented,Implemented"
bitfld.quad 0x00 2. "BR_MIS_PRED_RETIRED,Instruction architecturally executed mispredicted branch" "Not implemented,Implemented"
bitfld.quad 0x00 1. "BR_RETIRED,Instruction architecturally executed branch" "Not implemented,Implemented"
newline
bitfld.quad 0x00 0. "L2D_CACHE_ALLOCATE,Level 2 data cache allocate" "Not implemented,Implemented"
endif
tree.end
newline
group.quad spr:0x339D0++0x00
line.quad 0x00 "PMCCNTR_EL0,Performance Monitors Cycle Counter"
group.quad spr:0x339D1++0x00
line.quad 0x00 "PMXEVTYPER_EL0,Performance Monitors Selected Event Type Register"
group.quad spr:0x339D2++0x00
line.quad 0x00 "PMXEVCNTR_EL0,Selected Event Counter Register"
group.quad spr:0x339E0++0x00
line.quad 0x00 "PMUSERENR_EL0,User Enable Register"
bitfld.quad 0x00 3. "ER,Event counter read enable" "Disabled,Enabled"
bitfld.quad 0x00 2. "CR,Cycle counter read enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 1. "SW,Software Increment write enable" "Disabled,Enabled"
bitfld.quad 0x00 0. "EN,EL0 access enable bit" "Disabled,Enabled"
group.quad spr:0x309E1++0x00
line.quad 0x00 "PMINTENSET_EL1,Interrupt Enable Set register"
bitfld.quad 0x00 31. "C,CCNT Overflow Interrupt Request Enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 5. "P5,PMCNT5 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.quad 0x00 4. "P4,PMCNT4 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.quad 0x00 3. "P3,PMCNT3 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 2. "P2,PMCNT2 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.quad 0x00 1. "P1,PMCNT1 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.quad 0x00 0. "P0,PMCNT0 Overflow Interrupt Enable" "Disabled,Enabled"
group.quad spr:0x309E2++0x00
line.quad 0x00 "PMINTENCLR_EL1,Interrupt Enable Clear register"
eventfld.quad 0x00 31. "C,CCNT Overflow Interrupt Request Enable" "Disabled,Enabled"
newline
eventfld.quad 0x00 5. "P5,PMCNT5 Overflow Interrupt Enable" "Disabled,Enabled"
eventfld.quad 0x00 4. "P4,PMCNT4 Overflow Interrupt Enable" "Disabled,Enabled"
eventfld.quad 0x00 3. "P3,PMCNT3 Overflow Interrupt Enable" "Disabled,Enabled"
newline
eventfld.quad 0x00 2. "P2,PMCNT2 Overflow Interrupt Enable" "Disabled,Enabled"
eventfld.quad 0x00 1. "P1,PMCNT1 Overflow Interrupt Enable" "Disabled,Enabled"
eventfld.quad 0x00 0. "P0,PMCNT0 Overflow Interrupt Enable" "Disabled,Enabled"
group.quad spr:0x339E3++0x00
line.quad 0x00 "PMOVSSET_EL0,Overflow Status Flags Set register"
bitfld.quad 0x00 31. "C,PMCCNTR overflow" "No overflow,Overflow"
newline
bitfld.quad 0x00 5. "P5,PMN5 Overflow" "No overflow,Overflow"
bitfld.quad 0x00 4. "P4,PMN4 Overflow" "No overflow,Overflow"
bitfld.quad 0x00 3. "P3,PMN3 Overflow" "No overflow,Overflow"
newline
bitfld.quad 0x00 2. "P2,PMN2 Overflow" "No overflow,Overflow"
bitfld.quad 0x00 1. "P1,PMN1 Overflow" "No overflow,Overflow"
bitfld.quad 0x00 0. "P0,PMN0 Overflow" "No overflow,Overflow"
group.quad spr:(0x33E80+0x0)++0x00
line.quad 0x00 "PMEVCNTR0_EL0,Event Counter Register"
group.quad spr:(0x33E80+0x1)++0x00
line.quad 0x00 "PMEVCNTR1_EL0,Event Counter Register"
group.quad spr:(0x33E80+0x2)++0x00
line.quad 0x00 "PMEVCNTR2_EL0,Event Counter Register"
group.quad spr:(0x33E80+0x3)++0x00
line.quad 0x00 "PMEVCNTR3_EL0,Event Counter Register"
group.quad spr:(0x33E80+0x4)++0x00
line.quad 0x00 "PMEVCNTR4_EL0,Event Counter Register"
group.quad spr:(0x33E80+0x5)++0x00
line.quad 0x00 "PMEVCNTR5_EL0,Event Counter Register"
group.quad spr:(0x33EC0+0x0)++0x00
line.quad 0x00 "PMEVTYPER0_EL0,Event Counter Register"
bitfld.quad 0x00 31. "P,Count events in EL1" "Disabled,Enabled"
bitfld.quad 0x00 30. "U,Count events in EL0" "Disabled,Enabled"
bitfld.quad 0x00 29. "NSK,Count events in non-secure EL1" "Disabled,Enabled"
newline
bitfld.quad 0x00 28. "NSU,Count events in non-secure EL0" "Disabled,Enabled"
bitfld.quad 0x00 27. "NSH,Count events in non-secure EL2" "Disabled,Enabled"
bitfld.quad 0x00 26. "M,Count events in secure EL3" "Disabled,Enabled"
newline
hexmask.quad.word 0x00 0.--15. 1. "EVTCOUNT,Event number"
group.quad spr:(0x33EC0+0x1)++0x00
line.quad 0x00 "PMEVTYPER1_EL0,Event Counter Register"
bitfld.quad 0x00 31. "P,Count events in EL1" "Disabled,Enabled"
bitfld.quad 0x00 30. "U,Count events in EL0" "Disabled,Enabled"
bitfld.quad 0x00 29. "NSK,Count events in non-secure EL1" "Disabled,Enabled"
newline
bitfld.quad 0x00 28. "NSU,Count events in non-secure EL0" "Disabled,Enabled"
bitfld.quad 0x00 27. "NSH,Count events in non-secure EL2" "Disabled,Enabled"
bitfld.quad 0x00 26. "M,Count events in secure EL3" "Disabled,Enabled"
newline
hexmask.quad.word 0x00 0.--15. 1. "EVTCOUNT,Event number"
group.quad spr:(0x33EC0+0x2)++0x00
line.quad 0x00 "PMEVTYPER2_EL0,Event Counter Register"
bitfld.quad 0x00 31. "P,Count events in EL1" "Disabled,Enabled"
bitfld.quad 0x00 30. "U,Count events in EL0" "Disabled,Enabled"
bitfld.quad 0x00 29. "NSK,Count events in non-secure EL1" "Disabled,Enabled"
newline
bitfld.quad 0x00 28. "NSU,Count events in non-secure EL0" "Disabled,Enabled"
bitfld.quad 0x00 27. "NSH,Count events in non-secure EL2" "Disabled,Enabled"
bitfld.quad 0x00 26. "M,Count events in secure EL3" "Disabled,Enabled"
newline
hexmask.quad.word 0x00 0.--15. 1. "EVTCOUNT,Event number"
group.quad spr:(0x33EC0+0x3)++0x00
line.quad 0x00 "PMEVTYPER3_EL0,Event Counter Register"
bitfld.quad 0x00 31. "P,Count events in EL1" "Disabled,Enabled"
bitfld.quad 0x00 30. "U,Count events in EL0" "Disabled,Enabled"
bitfld.quad 0x00 29. "NSK,Count events in non-secure EL1" "Disabled,Enabled"
newline
bitfld.quad 0x00 28. "NSU,Count events in non-secure EL0" "Disabled,Enabled"
bitfld.quad 0x00 27. "NSH,Count events in non-secure EL2" "Disabled,Enabled"
bitfld.quad 0x00 26. "M,Count events in secure EL3" "Disabled,Enabled"
newline
hexmask.quad.word 0x00 0.--15. 1. "EVTCOUNT,Event number"
group.quad spr:(0x33EC0+0x4)++0x00
line.quad 0x00 "PMEVTYPER4_EL0,Event Counter Register"
bitfld.quad 0x00 31. "P,Count events in EL1" "Disabled,Enabled"
bitfld.quad 0x00 30. "U,Count events in EL0" "Disabled,Enabled"
bitfld.quad 0x00 29. "NSK,Count events in non-secure EL1" "Disabled,Enabled"
newline
bitfld.quad 0x00 28. "NSU,Count events in non-secure EL0" "Disabled,Enabled"
bitfld.quad 0x00 27. "NSH,Count events in non-secure EL2" "Disabled,Enabled"
bitfld.quad 0x00 26. "M,Count events in secure EL3" "Disabled,Enabled"
newline
hexmask.quad.word 0x00 0.--15. 1. "EVTCOUNT,Event number"
group.quad spr:(0x33EC0+0x5)++0x00
line.quad 0x00 "PMEVTYPER5_EL0,Event Counter Register"
bitfld.quad 0x00 31. "P,Count events in EL1" "Disabled,Enabled"
bitfld.quad 0x00 30. "U,Count events in EL0" "Disabled,Enabled"
bitfld.quad 0x00 29. "NSK,Count events in non-secure EL1" "Disabled,Enabled"
newline
bitfld.quad 0x00 28. "NSU,Count events in non-secure EL0" "Disabled,Enabled"
bitfld.quad 0x00 27. "NSH,Count events in non-secure EL2" "Disabled,Enabled"
bitfld.quad 0x00 26. "M,Count events in secure EL3" "Disabled,Enabled"
newline
hexmask.quad.word 0x00 0.--15. 1. "EVTCOUNT,Event number"
group.quad spr:0x33EF7++0x00
line.quad 0x00 "PMCCFILTR_EL0,Event Type and Cycle Counter Filter Register"
bitfld.quad 0x00 31. "P,Count events in EL1" "Disabled,Enabled"
bitfld.quad 0x00 30. "U,Count events in EL0" "Disabled,Enabled"
bitfld.quad 0x00 29. "NSK,Count events in non-secure EL1" "Disabled,Enabled"
newline
bitfld.quad 0x00 28. "NSU,Count events in non-secure EL0" "Disabled,Enabled"
bitfld.quad 0x00 27. "NSH,Count events in non-secure EL2" "Disabled,Enabled"
bitfld.quad 0x00 26. "M,Count events in secure EL3" "Disabled,Enabled"
newline
hexmask.quad.word 0x00 0.--15. 1. "EVTCOUNT,Event number"
tree.end
tree "System Timer Registers"
group.quad spr:0x33E00++0x00
line.quad 0x00 "CNTFRQ_EL0,Counter-timer Frequency register"
rgroup.quad spr:0x33E01++0x00
line.quad 0x00 "CNTPCT_EL0,Counter-timer Physical Count register"
rgroup.quad spr:0x33E02++0x00
line.quad 0x00 "CNTVCT_EL0,Counter-timer Virtual Count register"
group.quad spr:0x34E03++0x00
line.quad 0x00 "CNTVOFF_EL2,Counter-timer Virtual Offset register"
if (((per.q(spr:0x34110))&0x408000000)==0x408000000)
group.quad spr:0x30E10++0x00
line.quad 0x00 "CNTKCTL_EL1,Counter-timer Kernel Control register"
bitfld.quad 0x00 4.--7. "EVNTI,Selects which bit of CNTVCT is the trigger for the event stream generated from that counter, when that stream is enabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit defined by EVNTI, generates an event when the event stream is enabled" "0 to 1,1 to 0"
bitfld.quad 0x00 2. "EVNTEN,Enables the generation of an event stream from the corresponding counter" "Disabled,Enabled"
else
group.quad spr:0x30E10++0x00
line.quad 0x00 "CNTKCTL_EL1,Counter-timer Kernel Control register"
bitfld.quad 0x00 9. "EL0PTEN,Controls whether the physical timer registers are accessible from EL0 mode" "Disabled,Enabled"
bitfld.quad 0x00 8. "EL0VTEN,Controls whether the virtual timer registers are accessible from EL0 mode" "Disabled,Enabled"
bitfld.quad 0x00 4.--7. "EVNTI,Selects which bit of CNTVCT is the trigger for the event stream generated from that counter, when that stream is enabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit defined by EVNTI, generates an event when the event stream is enabled" "0 to 1,1 to 0"
newline
bitfld.quad 0x00 2. "EVNTEN,Enables the generation of an event stream from the corresponding counter" "Disabled,Enabled"
bitfld.quad 0x00 1. "EL0VCTEN,Controls whether the virtual counter, CNTVCT, and the frequency register CNTFRQ, are accessible from EL0 mode" "Disabled,Enabled"
bitfld.quad 0x00 0. "EL0PCTEN,Controls whether the physical counter, CNTPCT, and the frequency register CNTFRQ, are accessible from EL0 mode" "Disabled,Enabled"
endif
if (((per.q(spr:0x34110))&0x408000000)==0x408000000)
group.quad spr:0x35E10++0x00
line.quad 0x00 "CNTKCTL_EL12,Counter-timer Kernel Control register"
bitfld.quad 0x00 4.--7. "EVNTI,Selects which bit of CNTVCT is the trigger for the event stream generated from that counter, when that stream is enabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit defined by EVNTI, generates an event when the event stream is enabled" "0 to 1,1 to 0"
bitfld.quad 0x00 2. "EVNTEN,Enables the generation of an event stream from the corresponding counter" "Disabled,Enabled"
else
group.quad spr:0x35E10++0x00
line.quad 0x00 "CNTKCTL_EL12,Counter-timer Kernel Control register"
bitfld.quad 0x00 9. "EL0PTEN,Controls whether the physical timer registers are accessible from EL0 mode" "Disabled,Enabled"
bitfld.quad 0x00 8. "EL0VTEN,Controls whether the virtual timer registers are accessible from EL0 mode" "Disabled,Enabled"
bitfld.quad 0x00 4.--7. "EVNTI,Selects which bit of CNTVCT is the trigger for the event stream generated from that counter, when that stream is enabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit defined by EVNTI, generates an event when the event stream is enabled" "0 to 1,1 to 0"
newline
bitfld.quad 0x00 2. "EVNTEN,Enables the generation of an event stream from the corresponding counter" "Disabled,Enabled"
bitfld.quad 0x00 1. "EL0VCTEN,Controls whether the virtual counter, CNTVCT, and the frequency register CNTFRQ, are accessible from EL0 mode" "Disabled,Enabled"
bitfld.quad 0x00 0. "EL0PCTEN,Controls whether the physical counter, CNTPCT, and the frequency register CNTFRQ, are accessible from EL0 mode" "Disabled,Enabled"
endif
if (((per.q(spr:0x34110))&0x400000000)==0x000000000)
group.quad spr:0x34E10++0x00
line.quad 0x00 "CNTHCTL_EL2,Counter-timer Hypervisor Control register"
bitfld.quad 0x00 4.--7. "EVNTI,Selects which bit of CNTPCT is the trigger for the event stream generated from the physical counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit defined by EVNTI, generates an event when the event stream is enabled" "0 to 1,1 to 0"
bitfld.quad 0x00 2. "EVNTEN,Enables the generation of an event stream from the physical counter" "Disabled,Enabled"
bitfld.quad 0x00 1. "EL1PCEN,Controls whether the physical timer registers are accessible from Non-secure EL1 and EL0 modes" "Not accessible,Accessible"
newline
bitfld.quad 0x00 0. "EL1PCTEN,Controls whether the physical counter, CNTPCT, is accessible from Non-secure EL1 and EL0 modes" "Not accessible,Accessible"
elif (((per.q(spr:0x34110))&0x408000000)==0x400000000)
group.quad spr:0x34E10++0x00
line.quad 0x00 "CNTHCTL_EL2,Counter-timer Hypervisor Control register"
bitfld.quad 0x00 11. "EL1PTEN,Physical timer register accessing instructions are accessible from Non-secure EL1 and EL0" "Not accessible,Accessible"
bitfld.quad 0x00 10. "EL1PCEN,Physical counter is accessible from Non-secure EL1 and EL0" "Not accessible,Accessible"
newline
bitfld.quad 0x00 4.--7. "EVNTI,Selects which bit of CNTPCT is the trigger for the event stream generated from the physical counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit defined by EVNTI, generates an event when the event stream is enabled" "0 to 1,1 to 0"
bitfld.quad 0x00 2. "EVNTEN,Enables the generation of an event stream from the physical counter" "Disabled,Enabled"
else
group.quad spr:0x34E10++0x00
line.quad 0x00 "CNTHCTL_EL2,Counter-timer Hypervisor Control register"
bitfld.quad 0x00 9. "EL0PTEN,Physical timer register accessing instructions are accessible from Non-secure EL0" "Not accessible,Accessible"
bitfld.quad 0x00 8. "EL0VTEN,Virtual timer register accessing instructions are accessible from Non-secure EL0" "Not accessible,Accessible"
newline
bitfld.quad 0x00 4.--7. "EVNTI,Selects which bit of CNTPCT is the trigger for the event stream generated from the physical counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit defined by EVNTI, generates an event when the event stream is enabled" "0 to 1,1 to 0"
bitfld.quad 0x00 2. "EVNTEN,Enables the generation of an event stream from the physical counter" "Disabled,Enabled"
bitfld.quad 0x00 1. "EL0VCTEN,Virtual counter register accessing instructions are accessible from Non-secure EL0" "Not accessible,Accessible"
newline
bitfld.quad 0x00 0. "EL0PCTEN,Physical counter is accessible from Non-secure EL0 modes" "Not accessible,Accessible"
endif
group.quad spr:0x33E20++0x00
line.quad 0x00 "CNTP_TVAL_EL0,Counter-timer Physical Timer TimerValue register"
group.quad spr:0x35E20++0x00
line.quad 0x00 "CNTP_TVAL_EL02,Counter-timer Physical Timer TimerValue register"
group.quad spr:0x33E21++0x00
line.quad 0x00 "CNTP_CTL_EL0,Counter-timer Physical Timer Control register"
rbitfld.quad 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt"
bitfld.quad 0x00 1. "IMASK,Timer interrupt mask" "Not masked,Masked"
bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
group.quad spr:0x35E21++0x00
line.quad 0x00 "CNTP_CTL_EL02,Counter-timer Physical Timer Control register"
rbitfld.quad 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt"
bitfld.quad 0x00 1. "IMASK,Timer interrupt mask" "Not masked,Masked"
bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
group.quad spr:0x33E22++0x00
line.quad 0x00 "CNTP_CVAL_EL0,Counter-timer Physical Timer CompareValue register"
group.quad spr:0x35E22++0x00
line.quad 0x00 "CNTP_CVAL_EL02,Counter-timer Physical Timer CompareValue register"
group.quad spr:0x33E30++0x00
line.quad 0x00 "CNTV_TVAL_EL0,Counter-timer Virtual Timer TimerValue register"
group.quad spr:0x35E30++0x00
line.quad 0x00 "CNTV_TVAL_EL02,Counter-timer Virtual Timer TimerValue register"
group.quad spr:0x33E31++0x00
line.quad 0x00 "CNTV_CTL_EL0,Counter-timer Virtual Timer Control register"
rbitfld.quad 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt"
bitfld.quad 0x00 1. "IMASK,Timer interrupt mask" "Not masked,Masked"
bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
group.quad spr:0x35E31++0x00
line.quad 0x00 "CNTV_CTL_EL02,Counter-timer Virtual Timer Control register"
rbitfld.quad 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt"
bitfld.quad 0x00 1. "IMASK,Timer interrupt mask" "Not masked,Masked"
bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
group.quad spr:0x33E32++0x00
line.quad 0x00 "CNTV_CVAL_EL0,Counter-timer Virtual Timer CompareValue register"
group.quad spr:0x35E32++0x00
line.quad 0x00 "CNTV_CVAL_EL02,Counter-timer Virtual Timer CompareValue register"
group.quad spr:0x34E20++0x00
line.quad 0x00 "CNTHP_TVAL_EL2,Counter-timer Hypervisor Physical Timer TimerValue register"
group.quad spr:0x34E21++0x00
line.quad 0x00 "CNTHP_CTL_EL2,Counter-timer Hypervisor Physical Timer Control register"
rbitfld.quad 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt"
bitfld.quad 0x00 1. "IMASK,Timer interrupt mask" "Not masked,Masked"
bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
group.quad spr:0x34E22++0x00
line.quad 0x00 "CNTHP_CVAL_EL2,Counter-timer Hypervisor Physical Timer CompareValue register"
group.quad spr:0x34E30++0x00
line.quad 0x00 "CNTHV_TVAL_EL2,Counter-timer Hypervisor Virtual Timer Value register"
group.quad spr:0x34E31++0x00
line.quad 0x00 "CNTHV_CTL_EL2,Counter-timer Hypervisor Virtual Timer Control register"
rbitfld.quad 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt"
bitfld.quad 0x00 1. "IMASK,Timer interrupt mask" "Not masked,Masked"
bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
group.quad spr:0x34E32++0x00
line.quad 0x00 "CNTHV_CVAL_EL2,Counter-timer Hypervisor Virtual Timer CompareValue register"
group.quad spr:0x37E20++0x00
line.quad 0x00 "CNTPS_TVAL_EL1,Counter-timer Physical Secure Timer TimerValue register"
group.quad spr:0x37E21++0x00
line.quad 0x00 "CNTPS_CTL_EL1,Counter-timer Physical Secure Timer Control register"
rbitfld.quad 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt"
bitfld.quad 0x00 1. "IMASK,Timer interrupt mask" "Not masked,Masked"
bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
group.quad spr:0x37E22++0x00
line.quad 0x00 "CNTPS_CVAL_EL1,Counter-timer Physical Secure Timer CompareValue register"
tree.end
tree "Generic Interrupt Controller System Registers"
tree "AArch64 Physical GIC CPU Interface System Registers"
tree "Active Priorities Registers"
group.quad spr:0x30C84++0x00
line.quad 0x00 "ICC_AP0R0_EL1,Active Priorities 0 Register 0"
bitfld.quad 0x00 31. "P31,Group 0 interrupt active with priority level 31" "No interrupt,Interrupt"
bitfld.quad 0x00 30. "P30,Group 0 interrupt active with priority level 30" "No interrupt,Interrupt"
bitfld.quad 0x00 29. "P29,Group 0 interrupt active with priority level 29" "No interrupt,Interrupt"
bitfld.quad 0x00 28. "P28,Group 0 interrupt active with priority level 28" "No interrupt,Interrupt"
bitfld.quad 0x00 27. "P27,Group 0 interrupt active with priority level 27" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 26. "P26,Group 0 interrupt active with priority level 26" "No interrupt,Interrupt"
bitfld.quad 0x00 25. "P25,Group 0 interrupt active with priority level 25" "No interrupt,Interrupt"
bitfld.quad 0x00 24. "P24,Group 0 interrupt active with priority level 24" "No interrupt,Interrupt"
bitfld.quad 0x00 23. "P23,Group 0 interrupt active with priority level 23" "No interrupt,Interrupt"
bitfld.quad 0x00 22. "P22,Group 0 interrupt active with priority level 22" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 21. "P21,Group 0 interrupt active with priority level 21" "No interrupt,Interrupt"
bitfld.quad 0x00 20. "P20,Group 0 interrupt active with priority level 20" "No interrupt,Interrupt"
bitfld.quad 0x00 19. "P19,Group 0 interrupt active with priority level 19" "No interrupt,Interrupt"
bitfld.quad 0x00 18. "P18,Group 0 interrupt active with priority level 18" "No interrupt,Interrupt"
bitfld.quad 0x00 17. "P17,Group 0 interrupt active with priority level 17" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 16. "P16,Group 0 interrupt active with priority level 16" "No interrupt,Interrupt"
bitfld.quad 0x00 15. "P15,Group 0 interrupt active with priority level 15" "No interrupt,Interrupt"
bitfld.quad 0x00 14. "P14,Group 0 interrupt active with priority level 14" "No interrupt,Interrupt"
bitfld.quad 0x00 13. "P13,Group 0 interrupt active with priority level 13" "No interrupt,Interrupt"
bitfld.quad 0x00 12. "P12,Group 0 interrupt active with priority level 12" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 11. "P11,Group 0 interrupt active with priority level 11" "No interrupt,Interrupt"
bitfld.quad 0x00 10. "P10,Group 0 interrupt active with priority level 10" "No interrupt,Interrupt"
bitfld.quad 0x00 9. "P9,Group 0 interrupt active with priority level 9" "No interrupt,Interrupt"
bitfld.quad 0x00 8. "P8,Group 0 interrupt active with priority level 8" "No interrupt,Interrupt"
bitfld.quad 0x00 7. "P7,Group 0 interrupt active with priority level 7" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 6. "P6,Group 0 interrupt active with priority level 6" "No interrupt,Interrupt"
bitfld.quad 0x00 5. "P5,Group 0 interrupt active with priority level 5" "No interrupt,Interrupt"
bitfld.quad 0x00 4. "P4,Group 0 interrupt active with priority level 4" "No interrupt,Interrupt"
bitfld.quad 0x00 3. "P3,Group 0 interrupt active with priority level 3" "No interrupt,Interrupt"
bitfld.quad 0x00 2. "P2,Group 0 interrupt active with priority level 2" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 1. "P1,Group 0 interrupt active with priority level 1" "No interrupt,Interrupt"
bitfld.quad 0x00 0. "P0,Group 0 interrupt active with priority level 0" "No interrupt,Interrupt"
group.quad spr:0x30C90++0x00
line.quad 0x00 "ICC_AP1R0_EL1,Active Priorities 1 Register 0"
bitfld.quad 0x00 31. "P31,Group 1 interrupt active with priority level 31" "No interrupt,Interrupt"
bitfld.quad 0x00 30. "P30,Group 1 interrupt active with priority level 30" "No interrupt,Interrupt"
bitfld.quad 0x00 29. "P29,Group 1 interrupt active with priority level 29" "No interrupt,Interrupt"
bitfld.quad 0x00 28. "P28,Group 1 interrupt active with priority level 28" "No interrupt,Interrupt"
bitfld.quad 0x00 27. "P27,Group 1 interrupt active with priority level 27" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 26. "P26,Group 1 interrupt active with priority level 26" "No interrupt,Interrupt"
bitfld.quad 0x00 25. "P25,Group 1 interrupt active with priority level 25" "No interrupt,Interrupt"
bitfld.quad 0x00 24. "P24,Group 1 interrupt active with priority level 24" "No interrupt,Interrupt"
bitfld.quad 0x00 23. "P23,Group 1 interrupt active with priority level 23" "No interrupt,Interrupt"
bitfld.quad 0x00 22. "P22,Group 1 interrupt active with priority level 22" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 21. "P21,Group 1 interrupt active with priority level 21" "No interrupt,Interrupt"
bitfld.quad 0x00 20. "P20,Group 1 interrupt active with priority level 20" "No interrupt,Interrupt"
bitfld.quad 0x00 19. "P19,Group 1 interrupt active with priority level 19" "No interrupt,Interrupt"
bitfld.quad 0x00 18. "P18,Group 1 interrupt active with priority level 18" "No interrupt,Interrupt"
bitfld.quad 0x00 17. "P17,Group 1 interrupt active with priority level 17" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 16. "P16,Group 1 interrupt active with priority level 16" "No interrupt,Interrupt"
bitfld.quad 0x00 15. "P15,Group 1 interrupt active with priority level 15" "No interrupt,Interrupt"
bitfld.quad 0x00 14. "P14,Group 1 interrupt active with priority level 14" "No interrupt,Interrupt"
bitfld.quad 0x00 13. "P13,Group 1 interrupt active with priority level 13" "No interrupt,Interrupt"
bitfld.quad 0x00 12. "P12,Group 1 interrupt active with priority level 12" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 11. "P11,Group 1 interrupt active with priority level 11" "No interrupt,Interrupt"
bitfld.quad 0x00 10. "P10,Group 1 interrupt active with priority level 10" "No interrupt,Interrupt"
bitfld.quad 0x00 9. "P9,Group 1 interrupt active with priority level 9" "No interrupt,Interrupt"
bitfld.quad 0x00 8. "P8,Group 1 interrupt active with priority level 8" "No interrupt,Interrupt"
bitfld.quad 0x00 7. "P7,Group 1 interrupt active with priority level 7" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 6. "P6,Group 1 interrupt active with priority level 6" "No interrupt,Interrupt"
bitfld.quad 0x00 5. "P5,Group 1 interrupt active with priority level 5" "No interrupt,Interrupt"
bitfld.quad 0x00 4. "P4,Group 1 interrupt active with priority level 4" "No interrupt,Interrupt"
bitfld.quad 0x00 3. "P3,Group 1 interrupt active with priority level 3" "No interrupt,Interrupt"
bitfld.quad 0x00 2. "P2,Group 1 interrupt active with priority level 2" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 1. "P1,Group 1 interrupt active with priority level 1" "No interrupt,Interrupt"
bitfld.quad 0x00 0. "P0,Group 1 interrupt active with priority level 0" "No interrupt,Interrupt"
tree.end
newline
if (((per.q(spr:0x30CB6))&0x10000000000)==0x00)
wgroup.quad spr:0x30CB6++0x00
line.quad 0x00 "ICC_ASGI1R_EL1,Interrupt Controller Alias Software Generated Interrupt Group 1 Register"
hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3"
newline
bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self"
newline
hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2"
bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1"
hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,The set of PEs for which SGI interrupts will be generated"
else
wgroup.quad spr:0x30CB6++0x00
line.quad 0x00 "ICC_ASGI1R_EL1,Interrupt Controller Alias Software Generated Interrupt Group 1 Register"
newline
bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self"
newline
bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
endif
group.quad spr:0x30C83++0x00
line.quad 0x00 "ICC_BPR0_EL1,Binary Point Register 0"
bitfld.quad 0x00 0.--2. "BINARYPOINT,Interrupt Priority Field Control And Interrupt Preemption Control" "Reserved,Reserved,[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0],No preemption-[7:0]"
group.quad spr:0x30CC3++0x00
line.quad 0x00 "ICC_BPR1_EL1,Binary Point Register 1"
bitfld.quad 0x00 0.--2. "BINARYPOINT,Interrupt Priority Field Control And Interrupt Preemption Control" "Reserved,Reserved,[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0]"
group.quad spr:0x30CC4++0x00
line.quad 0x00 "ICC_CTLR_EL1,Interrupt Control Registers for EL1"
rbitfld.quad 0x00 19. "EXTRANGE,Extended INTID range" "Reserved,Supported"
rbitfld.quad 0x00 18. "RSS,Range selector support" "0 - 15,0 - 255"
newline
rbitfld.quad 0x00 15. "A3V,Affinity 3 Valid" "Reserved,Valid"
rbitfld.quad 0x00 14. "SEIS,SEI Support" "Not supported,"
bitfld.quad 0x00 11.--13. "IDBITS,Number of physical interrupt identifier bits supported" "16 bits,?..."
rbitfld.quad 0x00 8.--10. "PRIBITS,Number of priority bits implemented" "Reserved,Reserved,Reserved,Reserved,5,?..."
newline
bitfld.quad 0x00 6. "PMHE,Priority Mask Hint Enable" "Disabled,Enabled"
bitfld.quad 0x00 1. "EOIMODE,Indicates whether ICC_EOIR0 and ICC_EOIR1 provide both priority drop and interrupt deactivation functionality" "Both,Priority drop"
bitfld.quad 0x00 0. "CBPR,Common Binary Point Register" "Separate,Common"
group.quad spr:0x36CC4++0x00
line.quad 0x00 "ICC_CTLR_EL3,Interrupt Control Registers for EL3"
rbitfld.quad 0x00 19. "EXTRANGE,Extended INTID range" "Reserved,Supported"
rbitfld.quad 0x00 18. "RSS,Range selector support" "0 - 15,0 - 255"
newline
rbitfld.quad 0x00 17. "NDS,Disable Security not supported" "Reserved,Not supported"
rbitfld.quad 0x00 15. "A3V,Affinity 3 Valid" "Reserved,Valid"
rbitfld.quad 0x00 14. "SEIS,SEI Support" "Not supported,"
newline
bitfld.quad 0x00 11.--13. "IDBITS,Number of physical interrupt identifier bits supported" "16 bits,?..."
rbitfld.quad 0x00 8.--10. "PRIBITS,Number of priority bits implemented" "Reserved,Reserved,Reserved,Reserved,5,?..."
bitfld.quad 0x00 6. "PMHE,Priority Mask Hint Enable" "Disabled,Enabled"
newline
rbitfld.quad 0x00 5. "RM,Routing Modifier" "Normal,"
bitfld.quad 0x00 4. "EOIMODE_EL1NS,EOI mode for interrupts handledat non-secure EL1 and EL2" "0,1"
bitfld.quad 0x00 3. "EOIMODE_EL1S,EOI mode for interrupts handled at secure EL1" "0,1"
newline
bitfld.quad 0x00 2. "EOIMODE_EL3,EOI mode for interrupts handled at EL3" "0,1"
bitfld.quad 0x00 1. "CBPR_EL1NS,Non-secure accesses to GICC_BPR allowed." "Not allowed,Allowed"
bitfld.quad 0x00 0. "CBPR_EL1S,Secure EL1 accesses to ICC_BPR1 allowed" "Not allowed,Allowed"
wgroup.quad spr:0x30CB1++0x00
line.quad 0x00 "ICC_DIR_EL1,Deactivate Interrupt Register"
hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID of the interrupt to be deactivated"
wgroup.quad spr:0x30C81++0x00
line.quad 0x00 "ICC_EOIR0_EL1,End Of Interrupt Register 0"
hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID from the corresponding ICC_IAR0_EL1 access"
wgroup.quad spr:0x30CC1++0x00
line.quad 0x00 "ICC_EOIR1_EL1,End Of Interrupt Register 1"
hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID from the corresponding ICC_IAR1_EL1 access"
rgroup.quad spr:0x30C82++0x00
line.quad 0x00 "ICC_HPPIR0_EL1,Highest Priority Pending Interrupt Register 0"
hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt"
rgroup.quad spr:0x30CC2++0x00
line.quad 0x00 "ICC_HPPIR1_EL1,Highest Priority Pending Interrupt Register 1"
hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt"
newline
hgroup.quad spr:0x30C80++0x00
hide.long 0x00 "ICC_IAR0_EL1,Interrupt Acknowledge Register 0"
in
hgroup.quad spr:0x30CC0++0x00
hide.long 0x00 "ICC_IAR1_EL1,Interrupt Acknowledge Register 1"
in
newline
group.quad spr:0x30CC6++0x00
line.quad 0x00 "ICC_IGRPEN0_EL1,Interrupt Group 0 Enable Register (EL1)"
bitfld.quad 0x00 0. "ENABLE,Enable" "Disabled,Enabled"
group.quad spr:0x30CC7++0x00
line.quad 0x00 "ICC_IGRPEN1_EL1,Interrupt Group 1 Enable Register (EL1)"
bitfld.quad 0x00 0. "ENABLE,Enable" "Disabled,Enabled"
group.quad spr:0x36CC7++0x00
line.quad 0x00 "ICC_IGRPEN1_EL3,Interrupt Group Enable Register 1 (EL3)"
bitfld.quad 0x00 1. "ENABLEGRP1S,Enable Group 1 interrupts for the Secure state" "Disabled,Enabled"
bitfld.quad 0x00 0. "ENABLEGRP1NS,Enable Group 1 interrupts for the Non-secure state" "Disabled,Enabled"
group.quad spr:0x30460++0x00
line.quad 0x00 "ICC_PMR_EL1,Priority Mask Register"
hexmask.quad.byte 0x00 0.--7. 1. "PRIORITY,Priority mask level for the CPU interface"
rgroup.quad spr:0x30CB3++0x00
line.quad 0x00 "ICC_RPR_EL1,Running Priority Register"
hexmask.quad.byte 0x00 0.--7. 1. "PRIORITY,Current running priority on the CPU interface"
if (((per.q(spr:0x30CB7))&0x10000000000)==0x00)
wgroup.quad spr:0x30CB7++0x00
line.quad 0x00 "ICC_SGI0R_EL1,Interrupt Controller Software Generated Interrupt Group 0 Register"
hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3"
newline
bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self"
newline
hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2"
bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1"
hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,The set of PEs for which SGI interrupts will be generated."
else
wgroup.quad spr:0x30CB7++0x00
line.quad 0x00 "ICC_SGI0R_EL1,Interrupt Controller Software Generated Interrupt Group 0 Register"
newline
bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self"
newline
bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
endif
if (((per.q(spr:0x30CB5))&0x10000000000)==0x00)
wgroup.quad spr:0x30CB5++0x00
line.quad 0x00 "ICC_SGI1R_EL1,Interrupt Controller Software Generated Interrupt Group 0 Register"
hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3"
newline
bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self"
newline
hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2"
bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1"
hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,The set of PEs for which SGI interrupts will be generated"
else
wgroup.quad spr:0x30CB5++0x00
line.quad 0x00 "ICC_SGI1R_EL1,Interrupt Controller Software Generated Interrupt Group 0 Register"
newline
bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self"
newline
bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
endif
group.quad spr:0x30CC5++0x00
line.quad 0x00 "ICC_SRE_EL1,System Register Enable Register for EL1"
bitfld.quad 0x00 2. "DIB,Disable IRQ bypass" "No,Yes"
bitfld.quad 0x00 1. "DFB,Disable FIQ bypass" "No,Yes"
rbitfld.quad 0x00 0. "SRE,System Register Enable" "Reserved,Enabled"
group.quad spr:0x34C95++0x00
line.quad 0x00 "ICC_SRE_EL2,System Register Enable Register for EL2"
rbitfld.quad 0x00 3. "ENABLE,Enable lower exception level access to ICC_SRE_EL1" "Reserved,Enabled"
bitfld.quad 0x00 2. "DIB,Disable IRQ bypass" "No,Yes"
bitfld.quad 0x00 1. "DFB,Disable FIQ bypass" "No,Yes"
newline
rbitfld.quad 0x00 0. "SRE,System Register Enable" "Reserved,Enabled"
group.quad spr:0x36CC5++0x00
line.quad 0x00 "ICC_SRE_EL3,System Register Enable Register for EL3"
rbitfld.quad 0x00 3. "ENABLE,Enable lower exception level access to ICC_SRE_EL1 and ICC_SRE_EL2" "Reserved,Enabled"
bitfld.quad 0x00 2. "DIB,Disable IRQ bypass" "No,Yes"
bitfld.quad 0x00 1. "DFB,Disable FIQ bypass" "No,Yes"
newline
rbitfld.quad 0x00 0. "SRE,System Register Enable" "Reserved,Enabled"
tree.end
tree "AArch64 Virtual GIC CPU Interface System Registers"
tree.open "Interrupt Controller Active Priorities Registers"
group.quad spr:0x30C84++0x00
line.quad 0x00 "ICV_AP0R0_EL1,Active Priorities Group 0 Register 0 (EL1)"
bitfld.quad 0x00 31. "P31,Group 0 interrupt active with priority level 31" "No interrupt,Interrupt"
bitfld.quad 0x00 30. "P30,Group 0 interrupt active with priority level 30" "No interrupt,Interrupt"
bitfld.quad 0x00 29. "P29,Group 0 interrupt active with priority level 29" "No interrupt,Interrupt"
bitfld.quad 0x00 28. "P28,Group 0 interrupt active with priority level 28" "No interrupt,Interrupt"
bitfld.quad 0x00 27. "P27,Group 0 interrupt active with priority level 27" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 26. "P26,Group 0 interrupt active with priority level 26" "No interrupt,Interrupt"
bitfld.quad 0x00 25. "P25,Group 0 interrupt active with priority level 25" "No interrupt,Interrupt"
bitfld.quad 0x00 24. "P24,Group 0 interrupt active with priority level 24" "No interrupt,Interrupt"
bitfld.quad 0x00 23. "P23,Group 0 interrupt active with priority level 23" "No interrupt,Interrupt"
bitfld.quad 0x00 22. "P22,Group 0 interrupt active with priority level 22" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 21. "P21,Group 0 interrupt active with priority level 21" "No interrupt,Interrupt"
bitfld.quad 0x00 20. "P20,Group 0 interrupt active with priority level 20" "No interrupt,Interrupt"
bitfld.quad 0x00 19. "P19,Group 0 interrupt active with priority level 19" "No interrupt,Interrupt"
bitfld.quad 0x00 18. "P18,Group 0 interrupt active with priority level 18" "No interrupt,Interrupt"
bitfld.quad 0x00 17. "P17,Group 0 interrupt active with priority level 17" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 16. "P16,Group 0 interrupt active with priority level 16" "No interrupt,Interrupt"
bitfld.quad 0x00 15. "P15,Group 0 interrupt active with priority level 15" "No interrupt,Interrupt"
bitfld.quad 0x00 14. "P14,Group 0 interrupt active with priority level 14" "No interrupt,Interrupt"
bitfld.quad 0x00 13. "P13,Group 0 interrupt active with priority level 13" "No interrupt,Interrupt"
bitfld.quad 0x00 12. "P12,Group 0 interrupt active with priority level 12" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 11. "P11,Group 0 interrupt active with priority level 11" "No interrupt,Interrupt"
bitfld.quad 0x00 10. "P10,Group 0 interrupt active with priority level 10" "No interrupt,Interrupt"
bitfld.quad 0x00 9. "P9,Group 0 interrupt active with priority level 9" "No interrupt,Interrupt"
bitfld.quad 0x00 8. "P8,Group 0 interrupt active with priority level 8" "No interrupt,Interrupt"
bitfld.quad 0x00 7. "P7,Group 0 interrupt active with priority level 7" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 6. "P6,Group 0 interrupt active with priority level 6" "No interrupt,Interrupt"
bitfld.quad 0x00 5. "P5,Group 0 interrupt active with priority level 5" "No interrupt,Interrupt"
bitfld.quad 0x00 4. "P4,Group 0 interrupt active with priority level 4" "No interrupt,Interrupt"
bitfld.quad 0x00 3. "P3,Group 0 interrupt active with priority level 3" "No interrupt,Interrupt"
bitfld.quad 0x00 2. "P2,Group 0 interrupt active with priority level 2" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 1. "P1,Group 0 interrupt active with priority level 1" "No interrupt,Interrupt"
bitfld.quad 0x00 0. "P0,Group 0 interrupt active with priority level 0" "No interrupt,Interrupt"
group.quad spr:0x30C90++0x00
line.quad 0x00 "ICV_AP1R0_EL1,Active Priorities Group 1 Register 0 (EL1)"
bitfld.quad 0x00 31. "P31,Group 1 interrupt active with priority level 31" "No interrupt,Interrupt"
bitfld.quad 0x00 30. "P30,Group 1 interrupt active with priority level 30" "No interrupt,Interrupt"
bitfld.quad 0x00 29. "P29,Group 1 interrupt active with priority level 29" "No interrupt,Interrupt"
bitfld.quad 0x00 28. "P28,Group 1 interrupt active with priority level 28" "No interrupt,Interrupt"
bitfld.quad 0x00 27. "P27,Group 1 interrupt active with priority level 27" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 26. "P26,Group 1 interrupt active with priority level 26" "No interrupt,Interrupt"
bitfld.quad 0x00 25. "P25,Group 1 interrupt active with priority level 25" "No interrupt,Interrupt"
bitfld.quad 0x00 24. "P24,Group 1 interrupt active with priority level 24" "No interrupt,Interrupt"
bitfld.quad 0x00 23. "P23,Group 1 interrupt active with priority level 23" "No interrupt,Interrupt"
bitfld.quad 0x00 22. "P22,Group 1 interrupt active with priority level 22" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 21. "P21,Group 1 interrupt active with priority level 21" "No interrupt,Interrupt"
bitfld.quad 0x00 20. "P20,Group 1 interrupt active with priority level 20" "No interrupt,Interrupt"
bitfld.quad 0x00 19. "P19,Group 1 interrupt active with priority level 19" "No interrupt,Interrupt"
bitfld.quad 0x00 18. "P18,Group 1 interrupt active with priority level 18" "No interrupt,Interrupt"
bitfld.quad 0x00 17. "P17,Group 1 interrupt active with priority level 17" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 16. "P16,Group 1 interrupt active with priority level 16" "No interrupt,Interrupt"
bitfld.quad 0x00 15. "P15,Group 1 interrupt active with priority level 15" "No interrupt,Interrupt"
bitfld.quad 0x00 14. "P14,Group 1 interrupt active with priority level 14" "No interrupt,Interrupt"
bitfld.quad 0x00 13. "P13,Group 1 interrupt active with priority level 13" "No interrupt,Interrupt"
bitfld.quad 0x00 12. "P12,Group 1 interrupt active with priority level 12" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 11. "P11,Group 1 interrupt active with priority level 11" "No interrupt,Interrupt"
bitfld.quad 0x00 10. "P10,Group 1 interrupt active with priority level 10" "No interrupt,Interrupt"
bitfld.quad 0x00 9. "P9,Group 1 interrupt active with priority level 9" "No interrupt,Interrupt"
bitfld.quad 0x00 8. "P8,Group 1 interrupt active with priority level 8" "No interrupt,Interrupt"
bitfld.quad 0x00 7. "P7,Group 1 interrupt active with priority level 7" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 6. "P6,Group 1 interrupt active with priority level 6" "No interrupt,Interrupt"
bitfld.quad 0x00 5. "P5,Group 1 interrupt active with priority level 5" "No interrupt,Interrupt"
bitfld.quad 0x00 4. "P4,Group 1 interrupt active with priority level 4" "No interrupt,Interrupt"
bitfld.quad 0x00 3. "P3,Group 1 interrupt active with priority level 3" "No interrupt,Interrupt"
bitfld.quad 0x00 2. "P2,Group 1 interrupt active with priority level 2" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 1. "P1,Group 1 interrupt active with priority level 1" "No interrupt,Interrupt"
bitfld.quad 0x00 0. "P0,Group 1 interrupt active with priority level 0" "No interrupt,Interrupt"
tree.end
newline
group.quad spr:0x30C83++0x00
line.quad 0x00 "ICV_BPR0_EL1,Binary Point Register 0 (EL1)"
bitfld.quad 0x00 0.--2. "BINARYPOINT,Interrupt Priority Field Control And Interrupt Preemption Control" "Reserved,Reserved,[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0],No preemption-[7:0]"
group.quad spr:0x30CC3++0x00
line.quad 0x00 "ICV_BPR1_EL1,Binary Point Register 1 (EL1)"
bitfld.quad 0x00 0.--2. "BINARYPOINT,Interrupt Priority Field Control And Interrupt Preemption Control" "Reserved,Reserved,[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0]"
group.quad spr:0x30CC4++0x00
line.quad 0x00 "ICV_CTLR_EL1,Control Register (EL1)"
rbitfld.quad 0x00 15. "A3V,Affinity 3 Valid" "Reserved,Valid"
rbitfld.quad 0x00 14. "SEIS,SEI Support" "Not supported,"
rbitfld.quad 0x00 11.--13. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,?..."
newline
rbitfld.quad 0x00 8.--10. "PRIBITS,Number of priority bits implemented" "Reserved,Reserved,Reserved,Reserved,5,?..."
bitfld.quad 0x00 1. "VEOIMODE,Indicates whether ICV_EOIR0 and ICV_EOIR1 provide both priority drop and interrupt deactivation functionality" "Both,Priority drop"
bitfld.quad 0x00 0. "VCBPR,Common Binary Point Register" "Separate,Common"
wgroup.quad spr:0x30CB1++0x00
line.quad 0x00 "ICV_DIR_EL1,Deactivate Interrupt Register"
hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID of the virtual interrupt to be deactivated"
wgroup.quad spr:0x30C81++0x00
line.quad 0x00 "ICV_EOIR0_EL1,End Of Interrupt Register 0"
hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID from the corresponding ICV_IAR0_EL1 access"
wgroup.quad spr:0x30CC1++0x00
line.quad 0x00 "ICV_EOIR1_EL1,End Of Interrupt Register 1"
hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID from the corresponding ICV_IAR1_EL1 access"
rgroup.quad spr:0x30C82++0x00
line.quad 0x00 "ICV_HPPIR0_EL1,Highest Priority Pending Interrupt Register 0"
hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt"
rgroup.quad spr:0x30CC2++0x00
line.quad 0x00 "ICV_HPPIR1_EL1,Highest Priority Pending Interrupt Register 1"
hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt"
rgroup.quad spr:0x30C80++0x00
line.quad 0x00 "ICV_IAR0_EL1,Interrupt Acknowledge Register 0"
rgroup.quad spr:0x30CC0++0x00
line.quad 0x00 "ICV_IAR1_EL1,Interrupt Acknowledge Register 1"
group.quad spr:0x30CC6++0x00
line.quad 0x00 "ICV_IGRPEN0_EL1,Interrupt Group 0 Enable register"
bitfld.quad 0x00 0. "ENABLE,Enables Group 0 interrupts" "Disabled,Enabled"
group.quad spr:0x30CC7++0x00
line.quad 0x00 "ICV_IGRPEN1_EL1,Interrupt Group 1 Enable register"
bitfld.quad 0x00 0. "ENABLE,Enables Group 1 interrupts" "Disabled,Enabled"
group.quad spr:0x30460++0x00
line.quad 0x00 "ICV_PMR_EL1,Priority Mask Register"
hexmask.quad.byte 0x00 0.--7. 1. "PRIORITY,Priority mask level for the CPU interface"
rgroup.quad spr:0x30CB3++0x00
line.quad 0x00 "ICV_RPR_EL1,Running Priority Register"
hexmask.quad.byte 0x00 0.--7. 1. "PRIORITY,Current running priority on the CPU interface"
tree.end
tree "AArch64 Virtual Interface Control System Registers"
tree.open "Hypervisor Active Priorities Registers"
group.quad spr:0x34C80++0x00
line.quad 0x00 "ICH_AP0R0_EL2,Hypervisor Active Priorities Group 0 Register 0"
bitfld.quad 0x00 31. "P31,Group 0 interrupt active with priority level 31" "No interrupt,Interrupt"
bitfld.quad 0x00 30. "P30,Group 0 interrupt active with priority level 30" "No interrupt,Interrupt"
bitfld.quad 0x00 29. "P29,Group 0 interrupt active with priority level 29" "No interrupt,Interrupt"
bitfld.quad 0x00 28. "P28,Group 0 interrupt active with priority level 28" "No interrupt,Interrupt"
bitfld.quad 0x00 27. "P27,Group 0 interrupt active with priority level 27" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 26. "P26,Group 0 interrupt active with priority level 26" "No interrupt,Interrupt"
bitfld.quad 0x00 25. "P25,Group 0 interrupt active with priority level 25" "No interrupt,Interrupt"
bitfld.quad 0x00 24. "P24,Group 0 interrupt active with priority level 24" "No interrupt,Interrupt"
bitfld.quad 0x00 23. "P23,Group 0 interrupt active with priority level 23" "No interrupt,Interrupt"
bitfld.quad 0x00 22. "P22,Group 0 interrupt active with priority level 22" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 21. "P21,Group 0 interrupt active with priority level 21" "No interrupt,Interrupt"
bitfld.quad 0x00 20. "P20,Group 0 interrupt active with priority level 20" "No interrupt,Interrupt"
bitfld.quad 0x00 19. "P19,Group 0 interrupt active with priority level 19" "No interrupt,Interrupt"
bitfld.quad 0x00 18. "P18,Group 0 interrupt active with priority level 18" "No interrupt,Interrupt"
bitfld.quad 0x00 17. "P17,Group 0 interrupt active with priority level 17" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 16. "P16,Group 0 interrupt active with priority level 16" "No interrupt,Interrupt"
bitfld.quad 0x00 15. "P15,Group 0 interrupt active with priority level 15" "No interrupt,Interrupt"
bitfld.quad 0x00 14. "P14,Group 0 interrupt active with priority level 14" "No interrupt,Interrupt"
bitfld.quad 0x00 13. "P13,Group 0 interrupt active with priority level 13" "No interrupt,Interrupt"
bitfld.quad 0x00 12. "P12,Group 0 interrupt active with priority level 12" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 11. "P11,Group 0 interrupt active with priority level 11" "No interrupt,Interrupt"
bitfld.quad 0x00 10. "P10,Group 0 interrupt active with priority level 10" "No interrupt,Interrupt"
bitfld.quad 0x00 9. "P9,Group 0 interrupt active with priority level 9" "No interrupt,Interrupt"
bitfld.quad 0x00 8. "P8,Group 0 interrupt active with priority level 8" "No interrupt,Interrupt"
bitfld.quad 0x00 7. "P7,Group 0 interrupt active with priority level 7" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 6. "P6,Group 0 interrupt active with priority level 6" "No interrupt,Interrupt"
bitfld.quad 0x00 5. "P5,Group 0 interrupt active with priority level 5" "No interrupt,Interrupt"
bitfld.quad 0x00 4. "P4,Group 0 interrupt active with priority level 4" "No interrupt,Interrupt"
bitfld.quad 0x00 3. "P3,Group 0 interrupt active with priority level 3" "No interrupt,Interrupt"
bitfld.quad 0x00 2. "P2,Group 0 interrupt active with priority level 2" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 1. "P1,Group 0 interrupt active with priority level 1" "No interrupt,Interrupt"
bitfld.quad 0x00 0. "P0,Group 0 interrupt active with priority level 0" "No interrupt,Interrupt"
group.quad spr:0x34C90++0x00
line.quad 0x00 "ICH_AP1R0_EL2,Hypervisor Active Priorities Group 1 Register 0"
bitfld.quad 0x00 31. "P31,Group 1 interrupt active with priority level 31" "No interrupt,Interrupt"
bitfld.quad 0x00 30. "P30,Group 1 interrupt active with priority level 30" "No interrupt,Interrupt"
bitfld.quad 0x00 29. "P29,Group 1 interrupt active with priority level 29" "No interrupt,Interrupt"
bitfld.quad 0x00 28. "P28,Group 1 interrupt active with priority level 28" "No interrupt,Interrupt"
bitfld.quad 0x00 27. "P27,Group 1 interrupt active with priority level 27" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 26. "P26,Group 1 interrupt active with priority level 26" "No interrupt,Interrupt"
bitfld.quad 0x00 25. "P25,Group 1 interrupt active with priority level 25" "No interrupt,Interrupt"
bitfld.quad 0x00 24. "P24,Group 1 interrupt active with priority level 24" "No interrupt,Interrupt"
bitfld.quad 0x00 23. "P23,Group 1 interrupt active with priority level 23" "No interrupt,Interrupt"
bitfld.quad 0x00 22. "P22,Group 1 interrupt active with priority level 22" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 21. "P21,Group 1 interrupt active with priority level 21" "No interrupt,Interrupt"
bitfld.quad 0x00 20. "P20,Group 1 interrupt active with priority level 20" "No interrupt,Interrupt"
bitfld.quad 0x00 19. "P19,Group 1 interrupt active with priority level 19" "No interrupt,Interrupt"
bitfld.quad 0x00 18. "P18,Group 1 interrupt active with priority level 18" "No interrupt,Interrupt"
bitfld.quad 0x00 17. "P17,Group 1 interrupt active with priority level 17" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 16. "P16,Group 1 interrupt active with priority level 16" "No interrupt,Interrupt"
bitfld.quad 0x00 15. "P15,Group 1 interrupt active with priority level 15" "No interrupt,Interrupt"
bitfld.quad 0x00 14. "P14,Group 1 interrupt active with priority level 14" "No interrupt,Interrupt"
bitfld.quad 0x00 13. "P13,Group 1 interrupt active with priority level 13" "No interrupt,Interrupt"
bitfld.quad 0x00 12. "P12,Group 1 interrupt active with priority level 12" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 11. "P11,Group 1 interrupt active with priority level 11" "No interrupt,Interrupt"
bitfld.quad 0x00 10. "P10,Group 1 interrupt active with priority level 10" "No interrupt,Interrupt"
bitfld.quad 0x00 9. "P9,Group 1 interrupt active with priority level 9" "No interrupt,Interrupt"
bitfld.quad 0x00 8. "P8,Group 1 interrupt active with priority level 8" "No interrupt,Interrupt"
bitfld.quad 0x00 7. "P7,Group 1 interrupt active with priority level 7" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 6. "P6,Group 1 interrupt active with priority level 6" "No interrupt,Interrupt"
bitfld.quad 0x00 5. "P5,Group 1 interrupt active with priority level 5" "No interrupt,Interrupt"
bitfld.quad 0x00 4. "P4,Group 1 interrupt active with priority level 4" "No interrupt,Interrupt"
bitfld.quad 0x00 3. "P3,Group 1 interrupt active with priority level 3" "No interrupt,Interrupt"
bitfld.quad 0x00 2. "P2,Group 1 interrupt active with priority level 2" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 1. "P1,Group 1 interrupt active with priority level 1" "No interrupt,Interrupt"
bitfld.quad 0x00 0. "P0,Group 1 interrupt active with priority level 0" "No interrupt,Interrupt"
tree.end
newline
rgroup.quad spr:0x34CB3++0x00
line.quad 0x00 "ICH_EISR_EL2,End of Interrupt Status Register"
bitfld.quad 0x00 3. "STATUS3,EOI maintenance interrupt status bit for List register ICH_LR3_EL2" "No interrupt,Interrupt"
bitfld.quad 0x00 2. "STATUS2,EOI maintenance interrupt status bit for List register ICH_LR2_EL2" "No interrupt,Interrupt"
bitfld.quad 0x00 1. "STATUS1,EOI maintenance interrupt status bit for List register ICH_LR1_EL2" "No interrupt,Interrupt"
bitfld.quad 0x00 0. "STATUS0,EOI maintenance interrupt status bit for List register ICH_LR0_EL2" "No interrupt,Interrupt"
rgroup.quad spr:0x34CB5++0x00
line.quad 0x00 "ICH_ELRSR_EL2,Empty List Register Status Register"
bitfld.quad 0x00 3. "STATUS3,Status bit for List register ICH_LR3_EL2" "No interrupt,Interrupt"
bitfld.quad 0x00 2. "STATUS2,Status bit for List register ICH_LR2_EL2" "No interrupt,Interrupt"
bitfld.quad 0x00 1. "STATUS1,Status bit for List register ICH_LR1_EL2" "No interrupt,Interrupt"
bitfld.quad 0x00 0. "STATUS0,Status bit for List register ICH_LR0_EL2" "No interrupt,Interrupt"
group.quad spr:0x34CB0++0x00
line.quad 0x00 "ICH_HCR_EL2,Hypervisor Control Register"
bitfld.quad 0x00 27.--31. "EOICOUNT,Incremented whenever a successful write to a virtual EOIR or DIR register would have resulted in a virtual interrupt deactivation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 14. "TDIR,Trap Non-secure EL1 writes to ICC_DIR_EL1 and ICV_DIR" "No trap,Trap"
bitfld.quad 0x00 13. "TSEI,Trap all locally generated SEIs" "No trap,"
newline
bitfld.quad 0x00 12. "TALL1,Trap all Non-secure EL1 accesses to ICC_* and ICV* System registers for Group 1 interrupts to EL2" "No trap,Trap"
bitfld.quad 0x00 11. "TALL0,Trap all Non-secure EL1 accesses to ICC_* and ICV* System registers for Group 0 interrupts to EL2" "No trap,Trap"
bitfld.quad 0x00 10. "TC,Trap all Non-secure EL1 accesses to System registers that are common to Group 0 and Group 1 to EL2" "No trap,Trap"
newline
bitfld.quad 0x00 7. "VGRP1DIE,VM Group 1 Disabled Interrupt Enable" "Disabled,Enabled"
bitfld.quad 0x00 6. "VGRP1EIE,VM Group 1 Enabled Interrupt Enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 5. "VGRP0DIE,VM Group 0 Disabled Interrupt Enable" "Disabled,Enabled"
bitfld.quad 0x00 4. "VGRP0EIE,VM Group 0 Enabled Interrupt Enable" "Disabled,Enabled"
bitfld.quad 0x00 3. "NPIE,No Pending Interrupt Enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 2. "LRENPIE,List Register Entry Not Present Interrupt Enable" "Disabled,Enabled"
bitfld.quad 0x00 1. "UIE,Underflow Interrupt Enable" "Disabled,Enabled"
bitfld.quad 0x00 0. "EN,Global enable bit for the virtual CPU interface" "Disabled,Enabled"
if (((per.q(spr:0x34CC0))&0x2000000000000000)==0x0)
group.quad spr:0x34CC0++0x00
line.quad 0x00 "ICH_LR0_EL2,List Register 0"
bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending/Active"
bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt" "Software,Hardware"
bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt"
newline
bitfld.quad 0x00 41. "EOI,Maintenance interrupt assertion" "Not asserted,Asserted"
hexmask.quad.long 0x00 0.--31. 1. "VINTID,Virtual INTID of the interrupt"
else
group.quad spr:0x34CC0++0x00
line.quad 0x00 "ICH_LR0_EL2,List Register 0"
bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending/Active"
bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt" "Software,Hardware"
bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt"
newline
hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical interrupt ID for hardware interrupts"
hexmask.quad.long 0x00 0.--31. 1. "VINTID,Virtual INTID of the interrupt"
endif
if (((per.q(spr:0x34CC1))&0x2000000000000000)==0x0)
group.quad spr:0x34CC1++0x00
line.quad 0x00 "ICH_LR1_EL2,List Register 1"
bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending/Active"
bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt" "Software,Hardware"
bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt"
newline
bitfld.quad 0x00 41. "EOI,Maintenance interrupt assertion" "Not asserted,Asserted"
hexmask.quad.long 0x00 0.--31. 1. "VINTID,Virtual INTID of the interrupt"
else
group.quad spr:0x34CC1++0x00
line.quad 0x00 "ICH_LR1_EL2,List Register 1"
bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending/Active"
bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt" "Software,Hardware"
bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt"
newline
hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical interrupt ID for hardware interrupts"
hexmask.quad.long 0x00 0.--31. 1. "VINTID,Virtual INTID of the interrupt"
endif
if (((per.q(spr:0x34CC2))&0x2000000000000000)==0x0)
group.quad spr:0x34CC2++0x00
line.quad 0x00 "ICH_LR2_EL2,List Register 2"
bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending/Active"
bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt" "Software,Hardware"
bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt"
newline
bitfld.quad 0x00 41. "EOI,Maintenance interrupt assertion" "Not asserted,Asserted"
hexmask.quad.long 0x00 0.--31. 1. "VINTID,Virtual INTID of the interrupt"
else
group.quad spr:0x34CC2++0x00
line.quad 0x00 "ICH_LR2_EL2,List Register 2"
bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending/Active"
bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt" "Software,Hardware"
bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt"
newline
hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical interrupt ID for hardware interrupts"
hexmask.quad.long 0x00 0.--31. 1. "VINTID,Virtual INTID of the interrupt"
endif
if (((per.q(spr:0x34CC3))&0x2000000000000000)==0x0)
group.quad spr:0x34CC3++0x00
line.quad 0x00 "ICH_LR3_EL2,List Register 3"
bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending/Active"
bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt" "Software,Hardware"
bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt"
newline
bitfld.quad 0x00 41. "EOI,Maintenance interrupt assertion" "Not asserted,Asserted"
hexmask.quad.long 0x00 0.--31. 1. "VINTID,Virtual INTID of the interrupt"
else
group.quad spr:0x34CC3++0x00
line.quad 0x00 "ICH_LR3_EL2,List Register 3"
bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending/Active"
bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt" "Software,Hardware"
bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt"
newline
hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical interrupt ID for hardware interrupts"
hexmask.quad.long 0x00 0.--31. 1. "VINTID,Virtual INTID of the interrupt"
endif
rgroup.quad spr:0x34CB2++0x00
line.quad 0x00 "ICH_MISR_EL2,Maintenance Interrupt State Register"
bitfld.quad 0x00 7. "VGRP1D,vPE Group 1 Disabled maintenance interrupt assertion" "Not asserted,Asserted"
bitfld.quad 0x00 6. "VGRP1E,vPE Group 1 Enabled maintenance interrupt assertion" "Not asserted,Asserted"
bitfld.quad 0x00 5. "VGRP0D,vPE Group 0 Disabled maintenance interrupt assertion" "Not asserted,Asserted"
bitfld.quad 0x00 4. "VGRP0E,vPE Group 0 Enabled maintenance interrupt assertion" "Not asserted,Asserted"
newline
bitfld.quad 0x00 3. "NP,No Pending maintenance interrupt assertion" "Not asserted,Asserted"
bitfld.quad 0x00 2. "LRENP,List Register Entry Not Present maintenance interrupt assertion" "Not asserted,Asserted"
bitfld.quad 0x00 1. "U,Underflow maintenance interrupt assertion" "Not asserted,Asserted"
bitfld.quad 0x00 0. "EOI,End of Interrupt maintenance interrupt assertion" "Not asserted,Asserted"
group.quad spr:0x34CB7++0x00
line.quad 0x00 "ICH_VMCR_EL2,Virtual Machine Control Register"
hexmask.quad.byte 0x00 24.--31. 1. "VPMR,Virtual Priority Mask"
bitfld.quad 0x00 21.--23. "VBPR0,Interrupt Priority Field Control And Interrupt Preemption Control" "Reserved,Reserved,[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0],No preemption-[7:0]"
bitfld.quad 0x00 18.--20. "VBPR1,Interrupt Priority Field Control And Interrupt Preemption Control" "Reserved,Reserved,[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0]"
bitfld.quad 0x00 9. "VEOIM,Virtual EOI mode. Controls whether a write to an End of Interrupt register also deactivates the virtual interrupt" "Both,Priority drop"
newline
bitfld.quad 0x00 4. "VCBPR,Decides whether both interrupt groups are controlled by ICV_BPR0_EL1" "Separate,Both"
bitfld.quad 0x00 3. "VFIQEN,Virtual FIQ enable" "Reserved,Enabled"
bitfld.quad 0x00 1. "VENG1,Virtual Group 1 interrupt enable" "Disabled,Enabled"
bitfld.quad 0x00 0. "VENG0,Virtual Group 0 interrupt enable" "Disabled,Enabled"
rgroup.quad spr:0x34CB1++0x00
line.quad 0x00 "ICH_VTR_EL2,VGIC Type Register"
bitfld.quad 0x00 29.--31. "PRIBITS,The number of virtual priority bits implemented" "Reserved,Reserved,Reserved,Reserved,5,?..."
bitfld.quad 0x00 26.--28. "PREBITS,The number of virtual preemption bits implemented" "Reserved,Reserved,Reserved,Reserved,5,?..."
bitfld.quad 0x00 23.--25. "IDBITS,The number of virtual interrupt identifier bits supported" "16 bits,?..."
bitfld.quad 0x00 22. "SEIS,SEI Support" "Not supported,"
newline
bitfld.quad 0x00 21. "A3V,Affinity 3 Valid" "Reserved,Valid"
bitfld.quad 0x00 20. "NV4,GICv4 direct injection of virtual interrupts not supported" "Supported,"
bitfld.quad 0x00 19. "TDS,Separate trapping of Non-secure EL1 writes to ICV_DIR_EL1 supported" "Reserved,Supported"
bitfld.quad 0x00 0.--4. "LISTREGS,The number of implemented List registers" "Reserved,Reserved,Reserved,4,?..."
tree.end
tree.end
tree "Debug Registers"
rgroup.quad spr:0x23010++0x00
line.quad 0x00 "MDCCSR_EL0,Debug Comms Channel Status Register"
bitfld.quad 0x00 30. "RXFULL,DBGDTRRX Register full" "Empty,Full"
bitfld.quad 0x00 29. "TXFULL,DBGDTRTX Register full" "Empty,Full"
group.quad spr:0x20020++0x00
line.quad 0x00 "MDCCINT_EL1,Debug Comms Channel Interrupt Enable register"
bitfld.quad 0x00 30. "RX,DCC interrupt enable controls" "Disabled,Enabled"
bitfld.quad 0x00 29. "TX,DCC interrupt enable controls" "Disabled,Enabled"
group.quad spr:0x23040++0x00
line.quad 0x00 "DBGDTR_EL0,Half Duplex Data Transfer Register"
rgroup.quad spr:0x23050++0x00
line.quad 0x00 "DBGDTRRX_EL0,Full Duplex Receive Data Transfer Register"
wgroup.quad spr:0x23050++0x00
line.quad 0x00 "DBGDTRTX_EL0,Full Duplex Transmit Data Transfer Register"
group.quad spr:0x24070++0x00
line.quad 0x00 "DBGVCR32_EL2,Vector Catch Register"
bitfld.quad 0x00 31. "NSF,FIQ vector catch enable in Non-secure state" "Disabled,Enabled"
bitfld.quad 0x00 30. "NSI,IRQ vector catch enable in Non-secure state" "Disabled,Enabled"
bitfld.quad 0x00 28. "NSD,Data Abort vector catch enable in Non-secure state" "Disabled,Enabled"
bitfld.quad 0x00 27. "NSP,Prefetch Abort vector catch enable in Non-secure state" "Disabled,Enabled"
newline
bitfld.quad 0x00 26. "NSS,Supervisor Call (SVC) vector catch enable in Non-secure state" "Disabled,Enabled"
bitfld.quad 0x00 25. "NSU,Undefined Instruction vector catch enable in Non-secure state" "Disabled,Enabled"
bitfld.quad 0x00 7. "SF,FIQ vector catch enable in Secure state" "Disabled,Enabled"
bitfld.quad 0x00 6. "SI,IRQ vector catch enable in Secure state" "Disabled,Enabled"
newline
bitfld.quad 0x00 4. "SD,Data Abort vector catch enable in Secure state" "Disabled,Enabled"
bitfld.quad 0x00 3. "SP,Prefetch Abort vector catch enable in Secure state" "Disabled,Enabled"
bitfld.quad 0x00 2. "SS,Supervisor Call (SVC) vector catch enable in Secure state" "Disabled,Enabled"
bitfld.quad 0x00 1. "SU,Undefined Instruction vector catch enable in Secure state" "Disabled,Enabled"
group.quad spr:0x20002++0x00
line.quad 0x00 "OSDTRRX_EL1,OS Lock Data Transfer Register"
if (((per.q(spr:0x20114)&0x02)==0x00))
group.quad spr:0x20022++0x00
line.quad 0x00 "MDSCR_EL1,Monitor Debug System Control Register"
rbitfld.quad 0x00 30. "RXFULL,Save/restore of EDSCR.RXfull" "Empty,Full"
rbitfld.quad 0x00 29. "TXFULL,Save/restore of EDSCR.TXfull" "Empty,Full"
rbitfld.quad 0x00 27. "RXO,Save/restore of EDSCR.RXO" "Low,High"
rbitfld.quad 0x00 26. "TXU,Save/restore of EDSCR.TXU" "Low,High"
newline
rbitfld.quad 0x00 22.--23. "INTDIS,Save/restore of EDSCR.INTDIS" "0,1,2,3"
rbitfld.quad 0x00 21. "TDA,Save/restore of EDSCR.TDA" "Low,High"
bitfld.quad 0x00 15. "MDE,Monitor debug events" "Disabled,Enabled"
rbitfld.quad 0x00 14. "HDE,Save/restore of EDSCR.HDE" "Low,High"
newline
bitfld.quad 0x00 13. "KDE,Local (kernel) debug enable" "Disabled,Enabled"
bitfld.quad 0x00 12. "TDCC,Traps EL0 accesses to the DCC registers to EL1" "No trap,Trap"
rbitfld.quad 0x00 6. "ERR,Save/restore of EDSCR.ERR" "Low,High"
bitfld.quad 0x00 0. "SS,Software step control" "Disabled,Enabled"
else
group.quad spr:0x20022++0x00
line.quad 0x00 "MDSCR_EL1,Monitor Debug System Control Register"
bitfld.quad 0x00 30. "RXFULL,Save/restore of EDSCR.RXfull" "Empty,Full"
bitfld.quad 0x00 29. "TXFULL,Save/restore of EDSCR.TXfull" "Empty,Full"
bitfld.quad 0x00 27. "RXO,Save/restore of EDSCR.RXO" "Low,High"
bitfld.quad 0x00 26. "TXU,Save/restore of EDSCR.TXU" "Low,High"
newline
bitfld.quad 0x00 22.--23. "INTDIS,Save/restore of EDSCR.INTDIS" "0,1,2,3"
bitfld.quad 0x00 21. "TDA,Save/restore of EDSCR.TDA" "Low,High"
bitfld.quad 0x00 15. "MDE,Monitor debug events" "Disabled,Enabled"
bitfld.quad 0x00 14. "HDE,Save/restore of EDSCR.HDE" "Low,High"
newline
bitfld.quad 0x00 13. "KDE,Local (kernel) debug enable" "Disabled,Enabled"
bitfld.quad 0x00 12. "TDCC,Traps EL0 accesses to the DCC registers to EL1" "No trap,Trap"
bitfld.quad 0x00 6. "ERR,Save/restore of EDSCR.ERR" "Low,High"
bitfld.quad 0x00 0. "SS,Software step control" "Disabled,Enabled"
endif
group.quad spr:0x20032++0x00
line.quad 0x00 "OSDTRTX_EL1,OS Lock Data Transfer Register"
group.quad spr:0x20062++0x00
line.quad 0x00 "OSECCR_EL1,OS Lock Exception Catch Control Register"
bitfld.quad 0x00 7. 15. "NS[3],Coarse-grained Non-secure exception catch/return bit NSE[3] and NSR[3]" "No action/No action,Halt/Halt,Halt/Halt,Halt/No action"
bitfld.quad 0x00 6. 14. "NS[2],Coarse-grained Non-secure exception catch/return bit NSE[2] and NSR[2]" "No action/No action,Halt/Halt,Halt/Halt,Halt/No action"
bitfld.quad 0x00 5. 13. "NS[1],Coarse-grained Non-secure exception catch/return bit NSE[1] and NSR[1]" "No action/No action,Halt/Halt,Halt/Halt,Halt/No action"
bitfld.quad 0x00 4. 12. "NS[0],Coarse-grained Non-secure exception catch/return bit NSE[0] and NSR[0]" "No action/No action,Halt/Halt,Halt/Halt,Halt/No action"
newline
bitfld.quad 0x00 3. 11. "S[3],Coarse-grained Secure exception catch/return bit SE[3] and SR[3]" "No action/No action,Halt/Halt,Halt/Halt,Halt/No action"
bitfld.quad 0x00 2. 10. "S[2],Coarse-grained Secure exception catch/return bit SE[2] and SR[2]" "No action/No action,Halt/Halt,Halt/Halt,Halt/No action"
bitfld.quad 0x00 1. 9. "S[1],Coarse-grained Secure exception catch/return bit SE[1] and SR[1]" "No action/No action,Halt/Halt,Halt/Halt,Halt/No action"
bitfld.quad 0x00 0. 8. "S[0],Coarse-grained Secure exception catch/return bit SE[0] and SR[0]" "No action/No action,Halt/Halt,Halt/Halt,Halt/No action"
rgroup.quad spr:0x20100++0x00
line.quad 0x00 "MDRAR_EL1,Debug ROM Address Register"
wgroup.quad spr:0x20104++0x00
line.quad 0x00 "OSLAR_EL1,OS Lock Access Register"
bitfld.quad 0x00 0. "OSLK,OS lock" "Unlock,Lock"
rgroup.quad spr:0x20114++0x00
line.quad 0x00 "OSLSR_EL1,OS Lock Status Register"
bitfld.quad 0x00 2. "NTT,Not 32-bit access" "Low,High"
bitfld.quad 0x00 1. "OSLK,OS lock status" "Not locked,Locked"
bitfld.quad 0x00 0. 3. "OSLM,OS lock model implemented field" "Reserved,Reserved,Implemented,?..."
group.quad spr:0x20134++0x00
line.quad 0x00 "OSDLR_EL1,OS Double-lock Register"
bitfld.quad 0x00 0. "DLK,OS double-lock control" "Not locked,Locked"
group.quad spr:0x20144++0x00
line.quad 0x00 "DBGPRCR_EL1,Debug Power/Reset Control Register"
bitfld.quad 0x00 0. "CORENPDRQ,Core no powerdown request" "Powered down,Emulated"
group.quad spr:0x20786++0x00
line.quad 0x00 "DBGCLAIMSET_EL1,Claim Tag register Set"
bitfld.quad 0x0 7. "CT7,Claim Tag 7 Set" "Not set,Set"
bitfld.quad 0x0 6. "CT6,Claim Tag 6 Set" "Not set,Set"
bitfld.quad 0x0 5. "CT5,Claim Tag 5 Set" "Not set,Set"
bitfld.quad 0x0 4. "CT4,Claim Tag 4 Set" "Not set,Set"
newline
bitfld.quad 0x0 3. "CT3,Claim Tag 3 Set" "Not set,Set"
bitfld.quad 0x0 2. "CT2,Claim Tag 2 Set" "Not set,Set"
bitfld.quad 0x0 1. "CT1,Claim Tag 1 Set" "Not set,Set"
bitfld.quad 0x0 0. "CT0,Claim Tag 0 Set" "Not set,Set"
group.quad spr:0x20796++0x00
line.quad 0x00 "DBGCLAIMCLR_EL1,Claim Tag register Clear"
bitfld.quad 0x0 7. "CT7,Claim Tag 7 Clear" "Not cleared,Cleared"
bitfld.quad 0x0 6. "CT6,Claim Tag 6 Clear" "Not cleared,Cleared"
bitfld.quad 0x0 5. "CT5,Claim Tag 5 Clear" "Not cleared,Cleared"
bitfld.quad 0x0 4. "CT4,Claim Tag 4 Clear" "Not cleared,Cleared"
newline
bitfld.quad 0x0 3. "CT3,Claim Tag 3 Clear" "Not cleared,Cleared"
bitfld.quad 0x0 2. "CT2,Claim Tag 2 Clear" "Not cleared,Cleared"
bitfld.quad 0x0 1. "CT1,Claim Tag 1 Clear" "Not cleared,Cleared"
bitfld.quad 0x0 0. "CT0,Claim Tag 0 Clear" "Not cleared,Cleared"
rgroup.quad spr:0x207e6++0x00
line.quad 0x00 "DBGAUTHSTATUS_EL1,Authentication Status register"
bitfld.quad 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented"
bitfld.quad 0x00 6. "SNE,Secure non-invasive debug enabled" "Disabled,Enabled"
bitfld.quad 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented"
bitfld.quad 0x00 4. "SE,Secure invasive debug enabled" "Disabled,Enabled"
newline
bitfld.quad 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented"
bitfld.quad 0x00 2. "NSNE,Non-secure non-invasive debug enabled" "Disabled,Enabled"
bitfld.quad 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented"
bitfld.quad 0x00 0. "NSE,Non-secure invasive debug enabled" "Disabled,Enabled"
if (((per.q(spr:0x30400))&0x10)==0x10)
group.quad spr:0x30400++0x00
line.quad 0x00 "SPSR_EL1,Saved Program Status Register"
bitfld.quad 0x00 31. "N,Negative condition flag" "Not negative,Negative"
bitfld.quad 0x00 30. "Z,Zero condition flag" "Not zero,Zero"
bitfld.quad 0x00 29. "C,Carry condition flag" "Not carry,Carry"
bitfld.quad 0x00 28. "V,Overflow condition flag" "No overflow,Overflow"
newline
bitfld.quad 0x00 27. "Q,Cumulative condition flag" "Not occurred,Occurred"
bitfld.quad 0x00 22. "PAN,Privileged Access Never" "No,Yes"
bitfld.quad 0x00 21. "SS,Software step" "0,1"
bitfld.quad 0x00 20. "IL,Illegal Execution state" "0,1"
newline
bitfld.quad 0x00 14.--15. 25.--26. "IT[4:7],IT block state bits for the T32 IT (If-Then) instruction - base condition for the IT block" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 10.--13. "IT[0:3],IT block state bits for the T32 IT (If-Then) instruction - size of the IT block" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 16.--19. "GE,Greater than or Equal flags" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 9. "E,Endianness state bit" "Little,Big"
newline
bitfld.quad 0x00 8. "A,Asynchronous data abort mask bit" "Not masked,Masked"
bitfld.quad 0x00 7. "I,IRQ mask bit" "Not masked,Masked"
bitfld.quad 0x00 6. "F,FIQ mask bit" "Not masked,Masked"
bitfld.quad 0x00 5. "T,T32 Instruction set state" "A32,T32"
newline
bitfld.quad 0x00 4. "M[4],Execution state that the exception was taken from" "AArch64,AArch32"
bitfld.quad 0x00 0.--3. "M[3:0],Current PE mode" "User,FIQ,IRQ,Supervisor,,,,Abort,,,Hyp,Undefined,,,,System"
else
group.quad spr:0x30400++0x00
line.quad 0x00 "SPSR_EL1,Saved Program Status Register"
bitfld.quad 0x00 31. "N,Negative condition flag" "Not negative,Negative"
bitfld.quad 0x00 30. "Z,Zero condition flag" "Not zero,Zero"
bitfld.quad 0x00 29. "C,Carry condition flag" "Not carry,Carry"
bitfld.quad 0x00 28. "V,Overflow condition flag" "No overflow,Overflow"
newline
bitfld.quad 0x00 27. "Q,Cumulative condition flag" "Not occurred,Occurred"
bitfld.quad 0x00 23. "UAO,User Access Override" "Standard routines,New routines"
bitfld.quad 0x00 22. "PAN,Privileged Access Never" "No,Yes"
bitfld.quad 0x00 21. "SS,Software step" "0,1"
newline
bitfld.quad 0x00 20. "IL,Illegal Execution state" "0,1"
bitfld.quad 0x00 14.--15. 25.--26. "IT[4:7],IT block state bits for the T32 IT (If-Then) instruction - base condition for the IT block" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 10.--13. "IT[0:3],IT block state bits for the T32 IT (If-Then) instruction - size of the IT block" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 16.--19. "GE,Greater than or Equal flags" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 9. "E,Endianness state bit" "Little,Big"
bitfld.quad 0x00 8. "A,Asynchronous data abort mask bit" "Not masked,Masked"
bitfld.quad 0x00 7. "I,IRQ mask bit" "Not masked,Masked"
bitfld.quad 0x00 6. "F,FIQ mask bit" "Not masked,Masked"
newline
bitfld.quad 0x00 5. "T,T32 Instruction set state" "A32,T32"
bitfld.quad 0x00 4. "M[4],Execution state that the exception was taken from" "AArch64,AArch32"
bitfld.quad 0x00 0.--3. "M[3:0],Current PE mode" "El0t,,,,EL1t,EL1h,?..."
endif
if (((per.q(spr:0x34400))&0x10)==0x10)
group.quad spr:0x34400++0x00
line.quad 0x00 "SPSR_EL2,Saved Program Status Register"
bitfld.quad 0x00 31. "N,Negative condition flag" "Not negative,Negative"
bitfld.quad 0x00 30. "Z,Zero condition flag" "Not zero,Zero"
bitfld.quad 0x00 29. "C,Carry condition flag" "Not carry,Carry"
bitfld.quad 0x00 28. "V,Overflow condition flag" "No overflow,Overflow"
newline
bitfld.quad 0x00 27. "Q,Cumulative condition flag" "Not occurred,Occurred"
bitfld.quad 0x00 22. "PAN,Privileged Access Never" "No,Yes"
bitfld.quad 0x00 21. "SS,Software step" "0,1"
bitfld.quad 0x00 20. "IL,Illegal Execution state" "0,1"
newline
bitfld.quad 0x00 14.--15. 25.--26. "IT[4:7],IT block state bits for the T32 IT (If-Then) instruction - base condition for the IT block" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 10.--13. "IT[0:3],IT block state bits for the T32 IT (If-Then) instruction - size of the IT block" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 16.--19. "GE,Greater than or Equal flags" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 9. "E,Endianness state bit" "Little,Big"
newline
bitfld.quad 0x00 8. "A,Asynchronous data abort mask bit" "Not masked,Masked"
bitfld.quad 0x00 7. "I,IRQ mask bit" "Not masked,Masked"
bitfld.quad 0x00 6. "F,FIQ mask bit" "Not masked,Masked"
bitfld.quad 0x00 5. "T,T32 Instruction set state" "A32,T32"
newline
bitfld.quad 0x00 4. "M[4],Execution state that the exception was taken from" "AArch64,AArch32"
bitfld.quad 0x00 0.--3. "M[3:0],Current PE mode" "User,FIQ,IRQ,Supervisor,,,,Abort,,,Hyp,Undefined,,,,System"
else
group.quad spr:0x34400++0x00
line.quad 0x00 "SPSR_EL2,Saved Program Status Register"
bitfld.quad 0x00 31. "N,Negative condition flag" "Not negative,Negative"
bitfld.quad 0x00 30. "Z,Zero condition flag" "Not zero,Zero"
bitfld.quad 0x00 29. "C,Carry condition flag" "Not carry,Carry"
bitfld.quad 0x00 28. "V,Overflow condition flag" "No overflow,Overflow"
newline
bitfld.quad 0x00 27. "Q,Cumulative condition flag" "Not occurred,Occurred"
bitfld.quad 0x00 23. "UAO,User Access Override" "Standard routines,New routines"
bitfld.quad 0x00 22. "PAN,Privileged Access Never" "No,Yes"
bitfld.quad 0x00 21. "SS,Software step" "0,1"
newline
bitfld.quad 0x00 20. "IL,Illegal Execution state" "0,1"
bitfld.quad 0x00 14.--15. 25.--26. "IT[4:7],IT block state bits for the T32 IT (If-Then) instruction - base condition for the IT block" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 10.--13. "IT[0:3],IT block state bits for the T32 IT (If-Then) instruction - size of the IT block" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 16.--19. "GE,Greater than or Equal flags" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 9. "E,Endianness state bit" "Little,Big"
bitfld.quad 0x00 8. "A,Asynchronous data abort mask bit" "Not masked,Masked"
bitfld.quad 0x00 7. "I,IRQ mask bit" "Not masked,Masked"
bitfld.quad 0x00 6. "F,FIQ mask bit" "Not masked,Masked"
newline
bitfld.quad 0x00 5. "T,T32 Instruction set state" "A32,T32"
bitfld.quad 0x00 4. "M[4],Execution state that the exception was taken from" "AArch64,AArch32"
bitfld.quad 0x00 0.--3. "M[3:0],Current PE mode" "El0t,,,,EL1t,EL1h,?..."
endif
if (((per.q(spr:0x36400))&0x10)==0x10)
group.quad spr:0x36400++0x00
line.quad 0x00 "SPSR_EL3,Saved Program Status Register"
bitfld.quad 0x00 31. "N,Negative condition flag" "Not negative,Negative"
bitfld.quad 0x00 30. "Z,Zero condition flag" "Not zero,Zero"
bitfld.quad 0x00 29. "C,Carry condition flag" "Not carry,Carry"
bitfld.quad 0x00 28. "V,Overflow condition flag" "No overflow,Overflow"
newline
bitfld.quad 0x00 27. "Q,Cumulative condition flag" "Not occurred,Occurred"
bitfld.quad 0x00 22. "PAN,Privileged Access Never" "No,Yes"
bitfld.quad 0x00 21. "SS,Software step" "0,1"
bitfld.quad 0x00 20. "IL,Illegal Execution state" "0,1"
newline
bitfld.quad 0x00 14.--15. 25.--26. "IT[4:7],IT block state bits for the T32 IT (If-Then) instruction - base condition for the IT block" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 10.--13. "IT[0:3],IT block state bits for the T32 IT (If-Then) instruction - size of the IT block" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 16.--19. "GE,Greater than or Equal flags" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 9. "E,Endianness state bit" "Little,Big"
newline
bitfld.quad 0x00 8. "A,Asynchronous data abort mask bit" "Not masked,Masked"
bitfld.quad 0x00 7. "I,IRQ mask bit" "Not masked,Masked"
bitfld.quad 0x00 6. "F,FIQ mask bit" "Not masked,Masked"
bitfld.quad 0x00 5. "T,T32 Instruction set state" "A32,T32"
newline
bitfld.quad 0x00 4. "M[4],Execution state that the exception was taken from" "AArch64,AArch32"
bitfld.quad 0x00 0.--3. "M[3:0],Current PE mode" "User,FIQ,IRQ,Supervisor,,,,Abort,,,Hyp,Undefined,,,,System"
else
group.quad spr:0x36400++0x00
line.quad 0x00 "SPSR_EL3,Saved Program Status Register"
bitfld.quad 0x00 31. "N,Negative condition flag" "Not negative,Negative"
bitfld.quad 0x00 30. "Z,Zero condition flag" "Not zero,Zero"
bitfld.quad 0x00 29. "C,Carry condition flag" "Not carry,Carry"
bitfld.quad 0x00 28. "V,Overflow condition flag" "No overflow,Overflow"
newline
bitfld.quad 0x00 27. "Q,Cumulative condition flag" "Not occurred,Occurred"
bitfld.quad 0x00 23. "UAO,User Access Override" "Standard routines,New routines"
bitfld.quad 0x00 22. "PAN,Privileged Access Never" "No,Yes"
bitfld.quad 0x00 21. "SS,Software step" "0,1"
newline
bitfld.quad 0x00 20. "IL,Illegal Execution state" "0,1"
bitfld.quad 0x00 14.--15. 25.--26. "IT[4:7],IT block state bits for the T32 IT (If-Then) instruction - base condition for the IT block" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 10.--13. "IT[0:3],IT block state bits for the T32 IT (If-Then) instruction - size of the IT block" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 16.--19. "GE,Greater than or Equal flags" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 9. "E,Endianness state bit" "Little,Big"
bitfld.quad 0x00 8. "A,Asynchronous data abort mask bit" "Not masked,Masked"
bitfld.quad 0x00 7. "I,IRQ mask bit" "Not masked,Masked"
bitfld.quad 0x00 6. "F,FIQ mask bit" "Not masked,Masked"
newline
bitfld.quad 0x00 5. "T,T32 Instruction set state" "A32,T32"
bitfld.quad 0x00 4. "M[4],Execution state that the exception was taken from" "AArch64,AArch32"
bitfld.quad 0x00 0.--3. "M[3:0],Current PE mode" "El0t,,,,EL1t,EL1h,?..."
endif
if (((per.q(spr:0x33450))&0x10)==0x10)
group.quad spr:0x33450++0x00
line.quad 0x00 "DSPSR_EL0,Debug Saved Processor Status Register"
bitfld.quad 0x00 31. "N,Negative condition flag" "Not negative,Negative"
bitfld.quad 0x00 30. "Z,Zero condition flag" "Not zero,Zero"
bitfld.quad 0x00 29. "C,Carry condition flag" "Not carry,Carry"
bitfld.quad 0x00 28. "V,Overflow condition flag" "No overflow,Overflow"
newline
bitfld.quad 0x00 27. "Q,Cumulative condition flag" "Not occurred,Occurred"
bitfld.quad 0x00 22. "PAN,Privileged Access Never" "No,Yes"
bitfld.quad 0x00 21. "SS,Software step" "0,1"
bitfld.quad 0x00 20. "IL,Illegal Execution state" "0,1"
newline
bitfld.quad 0x00 13.--15. "IT[5:7],IT block state bits for the T32 IT (If-Then) instruction - base condition for the IT block" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 25.--26. 10.--12. "IT[0:4],IT block state bits for the T32 IT (If-Then) instruction - size of the IT block" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 16.--19. "GE,Greater than or Equal flags" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 9. "E,Endianness state bit" "Little,Big"
newline
bitfld.quad 0x00 8. "A,Asynchronous data abort mask bit" "Not masked,Masked"
bitfld.quad 0x00 7. "I,IRQ mask bit" "Not masked,Masked"
bitfld.quad 0x00 6. "F,FIQ mask bit" "Not masked,Masked"
bitfld.quad 0x00 5. "T,T32 Instruction set state" "A32,T32"
newline
bitfld.quad 0x00 4. "M[4],Execution state that the exception was taken from" "AArch64,AArch32"
bitfld.quad 0x00 0.--3. "M[3:0],Current PE mode" "User,FIQ,IRQ,Supervisor,,,Monitor,Abort,,,Hyp,Undefined,,,,System"
else
group.quad spr:0x33450++0x00
line.quad 0x00 "DSPSR_EL0,Debug Saved Processor Status Register"
bitfld.quad 0x00 31. "N,Negative condition flag" "Not negative,Negative"
bitfld.quad 0x00 30. "Z,Zero condition flag" "Not zero,Zero"
bitfld.quad 0x00 29. "C,Carry condition flag" "Not carry,Carry"
bitfld.quad 0x00 28. "V,Overflow condition flag" "No overflow,Overflow"
newline
bitfld.quad 0x00 27. "Q,Cumulative condition flag" "Not occurred,Occurred"
bitfld.quad 0x00 23. "UAO,User Access Override" "Standard routines,New routines"
bitfld.quad 0x00 22. "PAN,Privileged Access Never" "No,Yes"
bitfld.quad 0x00 21. "SS,Software step" "0,1"
newline
bitfld.quad 0x00 20. "IL,Illegal Execution state" "0,1"
bitfld.quad 0x00 13.--15. "IT[5:7],IT block state bits for the T32 IT (If-Then) instruction - base condition for the IT block" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 25.--26. 10.--12. "IT[0:4],IT block state bits for the T32 IT (If-Then) instruction - size of the IT block" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 16.--19. "GE,Greater than or Equal flags" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 9. "E,Endianness state bit" "Little,Big"
bitfld.quad 0x00 8. "A,Asynchronous data abort mask bit" "Not masked,Masked"
bitfld.quad 0x00 7. "I,IRQ mask bit" "Not masked,Masked"
bitfld.quad 0x00 6. "F,FIQ mask bit" "Not masked,Masked"
newline
bitfld.quad 0x00 5. "T,T32 Instruction set state" "A32,T32"
bitfld.quad 0x00 4. "M[4],Execution state that the exception was taken from" "AArch64,AArch32"
bitfld.quad 0x00 0.--3. "M[3:0],Current PE mode" "El0t,,,,EL1t,EL1h,,,EL2t,EL2h,,EL3t,EL3h,?..."
endif
tree.end
tree "Activity Monitors Unit"
if (CORENAME()=="CORTEXA75")
group.quad spr:0x33F97++0x00
line.quad 0x00 "CPUAMCNTENCLR_EL0, Activity Monitors Count Enable Clear Register"
bitfld.quad 0x00 4. "P4,AMEVCNTR4 disable bit [read/write]" "Disabled/No effect,Enabled/Disable"
newline
bitfld.quad 0x00 3. "P3,AMEVCNTR3 disable bit [read/write]" "Disabled/No effect,Enabled/Disable"
bitfld.quad 0x00 2. "P2,AMEVCNTR2 disable bit [read/write]" "Disabled/No effect,Enabled/Disable"
bitfld.quad 0x00 1. "P1,AMEVCNTR1 disable bit [read/write]" "Disabled/No effect,Enabled/Disable"
bitfld.quad 0x00 0. "P0,AMEVCNTR0 disable bit [read/write]" "Disabled/No effect,Enabled/Disable"
group.quad spr:0x33F96++0x00
line.quad 0x00 "CPUAMCNTENSET_EL0,Activity Monitors Count Enable Set Register"
bitfld.quad 0x00 4. "P4,AMEVCNTR4 enable bit" "Disabled,Enabled"
newline
bitfld.quad 0x00 3. "P3,AMEVCNTR3 enable bit" "Disabled,Enabled"
bitfld.quad 0x00 2. "P2,AMEVCNTR2 enable bit" "Disabled,Enabled"
bitfld.quad 0x00 1. "P1,AMEVCNTR1 enable bit" "Disabled,Enabled"
bitfld.quad 0x00 0. "P0,AMEVCNTR0 enable bit" "Disabled,Enabled"
group.quad spr:0x33FA6++0x00
line.quad 0x00 "CPUAMCFGR_EL0, Activity Monitors Configuration Register"
bitfld.quad 0x00 8.--13. "SIZE,Size of counters" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
hexmask.quad.byte 0x00 0.--7. 1. "N,Number of activity counters implemented"
group.quad spr:0x33FA7++0x00
line.quad 0x00 "CPUAMUSERENR_EL0, Activity Monitor EL0 Enable access"
bitfld.quad 0x00 0. "EN,Traps EL0 accesses to the activity monitor registers to EL1" "Trapped,Not trapped"
group.quad spr:0x33F90++0x00
line.quad 0x00 "CPUAMEVCNTR0_EL0,Activity Monitor Event Counter Register 0"
group.quad spr:(0x33F90+0x10)++0x00
line.quad 0x00 "CPUAMEVTYPER0_EL0,Activity Monitor Event Type Register 0"
hexmask.quad.word 0x00 0.--9. 1. "EVTCOUNT,EVTCOUNT"
group.quad spr:0x33F91++0x00
line.quad 0x00 "CPUAMEVCNTR1_EL0,Activity Monitor Event Counter Register 1"
group.quad spr:(0x33F91+0x10)++0x00
line.quad 0x00 "CPUAMEVTYPER1_EL0,Activity Monitor Event Type Register 1"
hexmask.quad.word 0x00 0.--9. 1. "EVTCOUNT,EVTCOUNT"
group.quad spr:0x33F92++0x00
line.quad 0x00 "CPUAMEVCNTR2_EL0,Activity Monitor Event Counter Register 2"
group.quad spr:(0x33F92+0x10)++0x00
line.quad 0x00 "CPUAMEVTYPER2_EL0,Activity Monitor Event Type Register 2"
hexmask.quad.word 0x00 0.--9. 1. "EVTCOUNT,EVTCOUNT"
group.quad spr:0x33F93++0x00
line.quad 0x00 "CPUAMEVCNTR3_EL0,Activity Monitor Event Counter Register 3"
group.quad spr:(0x33F93+0x10)++0x00
line.quad 0x00 "CPUAMEVTYPER3_EL0,Activity Monitor Event Type Register 3"
hexmask.quad.word 0x00 0.--9. 1. "EVTCOUNT,EVTCOUNT"
group.quad spr:0x33F94++0x00
line.quad 0x00 "CPUAMEVCNTR4_EL0,Activity Monitor Event Counter Register 4"
group.quad spr:(0x33F94+0x10)++0x00
line.quad 0x00 "CPUAMEVTYPER4_EL0,Activity Monitor Event Type Register 4"
hexmask.quad.word 0x00 0.--9. 1. "EVTCOUNT,EVTCOUNT"
endif
tree.end
tree "Breakpoint Registers"
tree "Breakpoint 0"
if ((((per.q(spr:0x20005+0x0))&0xF00000)<=0x100000)||((((per.q(spr:0x20005+0x0))&0xF00000)>=0x400000)&&(((per.q(spr:0x20005+0x0))&0xF00000)<=0x500000)))
group.quad spr:(0x20004+0x0)++0x00
line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register"
hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[48:2] of the address value for comparison"
elif (((((per.q(spr:0x20005+0x0))&0xF00000)>=0x200000)&&(((per.q(spr:0x20005+0x0))&0xF00000)<=0x300000))||((((per.q(spr:0x20005+0x0))&0xF00000)>=0x600000)&&(((per.q(spr:0x20005+0x0))&0xF00000)<=0x700000))||((((per.q(spr:0x20005+0x0))&0xF00000)>=0xC00000)))
group.quad spr:(0x20004+0x0)++0x00
line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison"
elif ((((per.q(spr:0x20005+0x0))&0xF00000)>=0x800000)&&(((per.q(spr:0x20005+0x0))&0xF00000)<=0x900000))
group.quad spr:(0x20004+0x0)++0x00
line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
elif ((((per.q(spr:0x20005+0x0))&0xF00000)>=0xA00000)&&(((per.q(spr:0x20005+0x0))&0xF00000)<=0xB00000))
group.quad spr:(0x20004+0x0)++0x00
line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison"
else
rgroup.quad spr:(0x20004+0x0)++0x00
line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register"
in
endif
group.quad spr:(0x20005+0x0)++0x00
line.quad 0x00 "DBGBCR0_EL1,Breakpoint Control Register"
bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
newline
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,T32/DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,T32/DBGBVRn+2_EL1,Reserved,Reserved,A64/A32/DBGBVRn_EL1"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
newline
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
tree.end
tree "Breakpoint 1"
if ((((per.q(spr:0x20005+0x10))&0xF00000)<=0x100000)||((((per.q(spr:0x20005+0x10))&0xF00000)>=0x400000)&&(((per.q(spr:0x20005+0x10))&0xF00000)<=0x500000)))
group.quad spr:(0x20004+0x10)++0x00
line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register"
hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[48:2] of the address value for comparison"
elif (((((per.q(spr:0x20005+0x10))&0xF00000)>=0x200000)&&(((per.q(spr:0x20005+0x10))&0xF00000)<=0x300000))||((((per.q(spr:0x20005+0x10))&0xF00000)>=0x600000)&&(((per.q(spr:0x20005+0x10))&0xF00000)<=0x700000))||((((per.q(spr:0x20005+0x10))&0xF00000)>=0xC00000)))
group.quad spr:(0x20004+0x10)++0x00
line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison"
elif ((((per.q(spr:0x20005+0x10))&0xF00000)>=0x800000)&&(((per.q(spr:0x20005+0x10))&0xF00000)<=0x900000))
group.quad spr:(0x20004+0x10)++0x00
line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
elif ((((per.q(spr:0x20005+0x10))&0xF00000)>=0xA00000)&&(((per.q(spr:0x20005+0x10))&0xF00000)<=0xB00000))
group.quad spr:(0x20004+0x10)++0x00
line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison"
else
rgroup.quad spr:(0x20004+0x10)++0x00
line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register"
in
endif
group.quad spr:(0x20005+0x10)++0x00
line.quad 0x00 "DBGBCR1_EL1,Breakpoint Control Register"
bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
newline
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,T32/DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,T32/DBGBVRn+2_EL1,Reserved,Reserved,A64/A32/DBGBVRn_EL1"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
newline
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
tree.end
tree "Breakpoint 2"
if ((((per.q(spr:0x20005+0x20))&0xF00000)<=0x100000)||((((per.q(spr:0x20005+0x20))&0xF00000)>=0x400000)&&(((per.q(spr:0x20005+0x20))&0xF00000)<=0x500000)))
group.quad spr:(0x20004+0x20)++0x00
line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register"
hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[48:2] of the address value for comparison"
elif (((((per.q(spr:0x20005+0x20))&0xF00000)>=0x200000)&&(((per.q(spr:0x20005+0x20))&0xF00000)<=0x300000))||((((per.q(spr:0x20005+0x20))&0xF00000)>=0x600000)&&(((per.q(spr:0x20005+0x20))&0xF00000)<=0x700000))||((((per.q(spr:0x20005+0x20))&0xF00000)>=0xC00000)))
group.quad spr:(0x20004+0x20)++0x00
line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison"
elif ((((per.q(spr:0x20005+0x20))&0xF00000)>=0x800000)&&(((per.q(spr:0x20005+0x20))&0xF00000)<=0x900000))
group.quad spr:(0x20004+0x20)++0x00
line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
elif ((((per.q(spr:0x20005+0x20))&0xF00000)>=0xA00000)&&(((per.q(spr:0x20005+0x20))&0xF00000)<=0xB00000))
group.quad spr:(0x20004+0x20)++0x00
line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison"
else
rgroup.quad spr:(0x20004+0x20)++0x00
line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register"
in
endif
group.quad spr:(0x20005+0x20)++0x00
line.quad 0x00 "DBGBCR2_EL1,Breakpoint Control Register"
bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
newline
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,T32/DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,T32/DBGBVRn+2_EL1,Reserved,Reserved,A64/A32/DBGBVRn_EL1"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
newline
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
tree.end
tree "Breakpoint 3"
if ((((per.q(spr:0x20005+0x30))&0xF00000)<=0x100000)||((((per.q(spr:0x20005+0x30))&0xF00000)>=0x400000)&&(((per.q(spr:0x20005+0x30))&0xF00000)<=0x500000)))
group.quad spr:(0x20004+0x30)++0x00
line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register"
hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[48:2] of the address value for comparison"
elif (((((per.q(spr:0x20005+0x30))&0xF00000)>=0x200000)&&(((per.q(spr:0x20005+0x30))&0xF00000)<=0x300000))||((((per.q(spr:0x20005+0x30))&0xF00000)>=0x600000)&&(((per.q(spr:0x20005+0x30))&0xF00000)<=0x700000))||((((per.q(spr:0x20005+0x30))&0xF00000)>=0xC00000)))
group.quad spr:(0x20004+0x30)++0x00
line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison"
elif ((((per.q(spr:0x20005+0x30))&0xF00000)>=0x800000)&&(((per.q(spr:0x20005+0x30))&0xF00000)<=0x900000))
group.quad spr:(0x20004+0x30)++0x00
line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
elif ((((per.q(spr:0x20005+0x30))&0xF00000)>=0xA00000)&&(((per.q(spr:0x20005+0x30))&0xF00000)<=0xB00000))
group.quad spr:(0x20004+0x30)++0x00
line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison"
else
rgroup.quad spr:(0x20004+0x30)++0x00
line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register"
in
endif
group.quad spr:(0x20005+0x30)++0x00
line.quad 0x00 "DBGBCR3_EL1,Breakpoint Control Register"
bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
newline
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,T32/DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,T32/DBGBVRn+2_EL1,Reserved,Reserved,A64/A32/DBGBVRn_EL1"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
newline
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
tree.end
tree "Breakpoint 4"
if ((((per.q(spr:0x20005+0x40))&0xF00000)<=0x100000)||((((per.q(spr:0x20005+0x40))&0xF00000)>=0x400000)&&(((per.q(spr:0x20005+0x40))&0xF00000)<=0x500000)))
group.quad spr:(0x20004+0x40)++0x00
line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register"
hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[48:2] of the address value for comparison"
elif (((((per.q(spr:0x20005+0x40))&0xF00000)>=0x200000)&&(((per.q(spr:0x20005+0x40))&0xF00000)<=0x300000))||((((per.q(spr:0x20005+0x40))&0xF00000)>=0x600000)&&(((per.q(spr:0x20005+0x40))&0xF00000)<=0x700000))||((((per.q(spr:0x20005+0x40))&0xF00000)>=0xC00000)))
group.quad spr:(0x20004+0x40)++0x00
line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison"
elif ((((per.q(spr:0x20005+0x40))&0xF00000)>=0x800000)&&(((per.q(spr:0x20005+0x40))&0xF00000)<=0x900000))
group.quad spr:(0x20004+0x40)++0x00
line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
elif ((((per.q(spr:0x20005+0x40))&0xF00000)>=0xA00000)&&(((per.q(spr:0x20005+0x40))&0xF00000)<=0xB00000))
group.quad spr:(0x20004+0x40)++0x00
line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison"
else
rgroup.quad spr:(0x20004+0x40)++0x00
line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register"
in
endif
group.quad spr:(0x20005+0x40)++0x00
line.quad 0x00 "DBGBCR4_EL1,Breakpoint Control Register"
bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
newline
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,T32/DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,T32/DBGBVRn+2_EL1,Reserved,Reserved,A64/A32/DBGBVRn_EL1"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
newline
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
tree.end
tree "Breakpoint 5"
if ((((per.q(spr:0x20005+0x50))&0xF00000)<=0x100000)||((((per.q(spr:0x20005+0x50))&0xF00000)>=0x400000)&&(((per.q(spr:0x20005+0x50))&0xF00000)<=0x500000)))
group.quad spr:(0x20004+0x50)++0x00
line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register"
hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[48:2] of the address value for comparison"
elif (((((per.q(spr:0x20005+0x50))&0xF00000)>=0x200000)&&(((per.q(spr:0x20005+0x50))&0xF00000)<=0x300000))||((((per.q(spr:0x20005+0x50))&0xF00000)>=0x600000)&&(((per.q(spr:0x20005+0x50))&0xF00000)<=0x700000))||((((per.q(spr:0x20005+0x50))&0xF00000)>=0xC00000)))
group.quad spr:(0x20004+0x50)++0x00
line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison"
elif ((((per.q(spr:0x20005+0x50))&0xF00000)>=0x800000)&&(((per.q(spr:0x20005+0x50))&0xF00000)<=0x900000))
group.quad spr:(0x20004+0x50)++0x00
line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
elif ((((per.q(spr:0x20005+0x50))&0xF00000)>=0xA00000)&&(((per.q(spr:0x20005+0x50))&0xF00000)<=0xB00000))
group.quad spr:(0x20004+0x50)++0x00
line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison"
else
rgroup.quad spr:(0x20004+0x50)++0x00
line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register"
in
endif
group.quad spr:(0x20005+0x50)++0x00
line.quad 0x00 "DBGBCR5_EL1,Breakpoint Control Register"
bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
newline
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,T32/DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,T32/DBGBVRn+2_EL1,Reserved,Reserved,A64/A32/DBGBVRn_EL1"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
newline
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
tree.end
tree.end
tree "Watchpoint Registers"
tree "Watchpoint 0"
group.quad spr:(0x20006+0x0)++0x00
line.quad 0x00 "DBGWVR0_EL1,Watchpoint Value Register (AArch64)"
hexmask.quad 0x00 2.--48. 0x4 "ADDRESS,Data address"
group.quad spr:(0x20007+0x0)++0x00
line.quad 0x00 "DBGWCR0_EL1,Watchpoint Control Register"
bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
tree.end
tree "Watchpoint 1"
group.quad spr:(0x20006+0x10)++0x00
line.quad 0x00 "DBGWVR1_EL1,Watchpoint Value Register (AArch64)"
hexmask.quad 0x00 2.--48. 0x4 "ADDRESS,Data address"
group.quad spr:(0x20007+0x10)++0x00
line.quad 0x00 "DBGWCR1_EL1,Watchpoint Control Register"
bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
tree.end
tree "Watchpoint 2"
group.quad spr:(0x20006+0x20)++0x00
line.quad 0x00 "DBGWVR2_EL1,Watchpoint Value Register (AArch64)"
hexmask.quad 0x00 2.--48. 0x4 "ADDRESS,Data address"
group.quad spr:(0x20007+0x20)++0x00
line.quad 0x00 "DBGWCR2_EL1,Watchpoint Control Register"
bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
tree.end
tree "Watchpoint 3"
group.quad spr:(0x20006+0x30)++0x00
line.quad 0x00 "DBGWVR3_EL1,Watchpoint Value Register (AArch64)"
hexmask.quad 0x00 2.--48. 0x4 "ADDRESS,Data address"
group.quad spr:(0x20007+0x30)++0x00
line.quad 0x00 "DBGWCR3_EL1,Watchpoint Control Register"
bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
tree.end
tree.end
tree "LORegions Registers"
group.quad spr:0x30A40++0x00
line.quad 0x00 "LORSA_EL1,LORegion Start Address"
hexmask.quad.long 0x00 16.--47. 0x1 "SA,Start physical address bits[47:16]"
bitfld.quad 0x00 0. "VALID,Indicates whether the LORegion Descriptor is enabled" "Not valid,Valid"
group.quad spr:0x30A41++0x00
line.quad 0x00 "LOREA_EL1,LORegion End Address"
hexmask.quad.long 0x00 16.--47. 0x1 "EA,End physical address bits[47:16]"
group.quad spr:0x30A42++0x00
line.quad 0x00 "LORN_EL1,LORegion Number Register"
bitfld.quad 0x00 0.--1. "NUM,Indicates the LORegion number" "0,1,2,3"
group.quad spr:0x30A43++0x00
line.quad 0x00 "LORC_EL1,LORegion Control Register"
bitfld.quad 0x00 2.--3. "DS,Descriptor Select" "0,1,2,3"
bitfld.quad 0x00 0. "EN,Enable" "Disabled,Enabled"
rgroup.quad spr:0x30A47++0x00
line.quad 0x00 "LORID_EL1,Limited Order Region Identification Register"
hexmask.quad.byte 0x00 16.--23. 1. "LD,Number of LOR Descriptors supported by the implementation"
hexmask.quad.byte 0x00 0.--7. 1. "LR,Number of LORegions supported by the implementation"
tree.end
tree "DynamIQ Shared Unit"
tree "Cluster Control Registers"
if (((per.q(spr:0x30F30))&0x2000)==0x00)
rgroup.quad spr:0x30F30++0x00
line.long 0x00 "CLUSTERCFR_EL1,Cluster Configuration Register"
bitfld.long 0x00 24.--27. "NPE,Number of processing elements" "1,2,?..."
bitfld.long 0x00 23. "L3_DATA_RAM_DELAY,L3 data RAM write delay" "Not delayed,Delayed"
newline
bitfld.long 0x00 17. "CRSP3,Core 3 register slice present" "Not present,Present"
bitfld.long 0x00 16. "CRSP2,Core 2 register slice present" "Not present,Present"
newline
bitfld.long 0x00 15. "CRSP1,Core 1 register slice present" "Not present,Present"
bitfld.long 0x00 14. "CRSP0,Core 0 register slice present" "Not present,Present"
bitfld.long 0x00 13. "BUS_INTERFACE_EXT,Bus interface extended" "Not extended,Extended"
newline
bitfld.long 0x00 12. "PPP,Peripheral port present" "Not present,Present"
bitfld.long 0x00 11. "ACP,ACP interface present" "Not present,Present"
bitfld.long 0x00 9.--10. "BUS_INTERFACE,Bus interface configuration" "Single 128-bit ACE,Dual 128-bit ACE,Single 128-bit CHI,Single 256-bit CHI"
newline
bitfld.long 0x00 8. "SCU_L3_ECC,SCU-L3 is configured with ECC" "No ECC,ECC"
bitfld.long 0x00 7. "L3_DATA_RAM_RS,L3 data RAM register slice present" "Not present,Present"
bitfld.long 0x00 6. "L3_DATA_RAM_RL,L3 data RAM read latency" "2 cycles,3 cycles"
newline
bitfld.long 0x00 5. "L3_DATA_RAM_WL,L3 data RAM write latency" "1 cycle,2 cycles"
bitfld.long 0x00 4. "L3_CACHE_PRESENT,L3 cache present" "Not present,Present"
bitfld.long 0x00 0.--2. "NOC,Number of cores present in the cluster" "1,2,3,4,?..."
else
rgroup.quad spr:0x30F30++0x00
line.long 0x00 "CLUSTERCFR_EL1,Cluster Configuration Register"
bitfld.long 0x00 24.--27. "NPE,Number of processing elements" "1,2,?..."
bitfld.long 0x00 23. "L3_DATA_RAM_DELAY,L3 data RAM write delay" "Not delayed,Delayed"
newline
bitfld.long 0x00 17. "CRSP3,Core 3 register slice present" "Not present,Present"
bitfld.long 0x00 16. "CRSP2,Core 2 register slice present" "Not present,Present"
newline
bitfld.long 0x00 15. "CRSP1,Core 1 register slice present" "Not present,Present"
bitfld.long 0x00 14. "CRSP0,Core 0 register slice present" "Not present,Present"
bitfld.long 0x00 13. "BUS_INTERFACE_EXT,Bus interface extended" "Not extended,Extended"
newline
bitfld.long 0x00 12. "PPP,Peripheral port present" "Not present,Present"
bitfld.long 0x00 11. "ACP,ACP interface present" "Not present,Present"
bitfld.long 0x00 9.--10. "BUS_INTERFACE,Bus interface configuration" "Single 128-bit ACE,Dual 128-bit ACE,Single 128-bit CHI,Dual 256-bit CHI"
newline
bitfld.long 0x00 8. "SCU_L3_ECC,SCU-L3 is configured with ECC" "No ECC,ECC"
bitfld.long 0x00 7. "L3_DATA_RAM_RS,L3 data RAM register slice present" "Not present,Present"
bitfld.long 0x00 6. "L3_DATA_RAM_RL,L3 data RAM read latency" "2 cycles,3 cycles"
newline
bitfld.long 0x00 5. "L3_DATA_RAM_WL,L3 data RAM write latency" "1 cycle,2 cycles"
bitfld.long 0x00 4. "L3_CACHE_PRESENT,L3 cache present" "Not present,Present"
bitfld.long 0x00 0.--2. "NOC,Number of cores present in the cluster" "1,2,3,4,?..."
endif
rgroup.quad spr:0x30F31++0x00
line.long 0x00 "CLUSTERIDR_EL1,Cluster Main Revision ID"
hexmask.long.byte 0x00 4.--7. 1. "VARIANT,Indicates the variant of the FCM"
hexmask.long.byte 0x00 0.--3. 1. "REVISION,Indicates the minor revision number of the FCM"
rgroup.quad spr:0x30F32++0x00
line.long 0x00 "CLUSTERREVIDR_EL1,Cluster ECO ID"
group.quad spr:0x30F33++0x00
line.long 0x00 "CLUSTERACTLR_EL1,Cluster Auxiliary Control Register"
if (((per.l(spr:0x30F30))&0x600)==(0x00||0x200))
group.quad spr:0x30F34++0x00
line.long 0x00 "CLUSTERECTLR_EL1,Cluster Extended Control Register"
bitfld.long 0x00 14. "CUEC,Cache UniqueClean eviction control" "Disabled,Enabled"
bitfld.long 0x00 8.--10. "PMD,Prefetch matching delay" "1,2,4,8,16,32,64,128"
bitfld.long 0x00 7. "DICA,Disable interconnect cacheable atomics" "No,Yes"
newline
bitfld.long 0x00 4. "IDPS,Interconnect data poisoning support" "Not supported,Supported"
bitfld.long 0x00 3. "CTEC,Disables send evict transactions on the ACE/CHI master" "No,Yes"
bitfld.long 0x00 2. "CFUCEC,Disables WriteEvict requests on the ACE/CHI master (Powering down part/All L3 cache)" "No,Yes"
newline
bitfld.long 0x00 0. "DNCWL,Disable the limit on the number of non-cacheable writes that are allowed on the ACE interface" "No,Yes"
else
group.quad spr:0x30F34++0x00
line.long 0x00 "CLUSTERECTLR_EL1,Cluster Extended Control Register"
bitfld.long 0x00 14. "CUEC,Cache UniqueClean eviction control" "Disabled,Enabled"
bitfld.long 0x00 8.--10. "PMD,Prefetch matching delay" "1,2,4,8,16,32,64,128"
bitfld.long 0x00 7. "DICA,Disable interconnect cacheable atomics" "No,Yes"
newline
bitfld.long 0x00 4. "IDPS,Interconnect data poisoning support" "Not supported,Supported"
bitfld.long 0x00 3. "CTEC,Disables send evict transactions on the ACE/CHI master" "No,Yes"
bitfld.long 0x00 2. "CFUCEC,Disables WriteEvict requests on the ACE/CHI master (Powering down part/All L3 cache)" "No,Yes"
endif
group.quad spr:0x30F35++0x00
line.long 0x00 "CLUSTERPWRCTLR_EL1,Cluster Power Control Register"
bitfld.long 0x00 4.--7. "CPPR,Cache portion power request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "L3_DATA_RAM_RC,L3 data RAM retention control [Number of Architectural Timer ticks required before retention entry]" "Disabled,2 AT ticks,8 AT ticks,32 AT ticks,64 AT ticks,128 AT ticks,256 AT ticks,512 AT ticks"
group.quad spr:0x30F36++0x00
line.long 0x00 "CLUSTERPWRDN_EL1,Cluster Power Down Register"
bitfld.long 0x00 1. "MRR,Memory retention required" "Not required,Required"
bitfld.long 0x00 0. "CPR,Cluster power required" "Not required,Required"
rgroup.quad spr:0x30F37++0x00
line.long 0x00 "CLUSTERPWRSTAT_EL1,Cluster Power Status Register"
bitfld.long 0x00 4.--7. "CPPS,This bits indicates which cache portions are currently powered up and available" "No ways,Ways 0-3,Reserved,Ways 0-7,Reserved,Reserved,Reserved,Ways 0-11,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Ways 0-15"
bitfld.long 0x00 1. "RWPD,Enabled memory retention when all cores are powered down" "Disabled,Enabled"
bitfld.long 0x00 0. "DCPD,Disabled cluster power down when all cores are powered down" "No,Yes"
group.quad spr:0x30F40++0x00
line.long 0x00 "CLUSTERTHREADSID_EL1,Cluster Thread Scheme ID Register"
bitfld.long 0x00 0.--2. "SCHEME_ID_THREAD,Scheme ID for current thread" "0,1,2,3,4,5,6,7"
group.quad spr:0x30F41++0x00
line.long 0x00 "CLUSTERACPSID_EL1,Cluster ACP Scheme ID Register"
bitfld.long 0x00 0.--2. "SCHEME_ID_ACP,Scheme ID for ACP transactions" "0,1,2,3,4,5,6,7"
group.quad spr:0x30F42++0x00
line.long 0x00 "CLUSTERSTASHSID_EL1,Cluster Stash Scheme ID Register"
bitfld.long 0x00 0.--2. "SCHEME_ID_SR,Scheme ID for stash requests received from the interconnect" "0,1,2,3,4,5,6,7"
group.quad spr:0x30F43++0x00
line.long 0x00 "CLUSTERPARTCR_EL1,Cluster Partition Control Register"
bitfld.long 0x00 31. "W3_ID7,Way group 3 is assigned as private to scheme ID 7" "Not assigned,Assigned"
bitfld.long 0x00 30. "W2_ID7,Way group 2 is assigned as private to scheme ID 7" "Not assigned,Assigned"
bitfld.long 0x00 29. "W1_ID7,Way group 1 is assigned as private to scheme ID 7" "Not assigned,Assigned"
newline
bitfld.long 0x00 28. "W0_ID7,Way group 0 is assigned as private to scheme ID 7" "Not assigned,Assigned"
bitfld.long 0x00 27. "W3_ID6,Way group 3 is assigned as private to scheme ID 6" "Not assigned,Assigned"
bitfld.long 0x00 26. "W2_ID6,Way group 2 is assigned as private to scheme ID 6" "Not assigned,Assigned"
newline
bitfld.long 0x00 25. "W1_ID6,Way group 1 is assigned as private to scheme ID 6" "Not assigned,Assigned"
bitfld.long 0x00 24. "W0_ID6,Way group 0 is assigned as private to scheme ID 6" "Not assigned,Assigned"
bitfld.long 0x00 23. "W3_ID5,Way group 3 is assigned as private to scheme ID 5" "Not assigned,Assigned"
newline
bitfld.long 0x00 22. "W2_ID5,Way group 2 is assigned as private to scheme ID 5" "Not assigned,Assigned"
bitfld.long 0x00 21. "W1_ID5,Way group 1 is assigned as private to scheme ID 5" "Not assigned,Assigned"
bitfld.long 0x00 20. "W0_ID5,Way group 0 is assigned as private to scheme ID 5" "Not assigned,Assigned"
newline
bitfld.long 0x00 19. "W3_ID4,Way group 3 is assigned as private to scheme ID 4" "Not assigned,Assigned"
bitfld.long 0x00 18. "W2_ID4,Way group 2 is assigned as private to scheme ID 4" "Not assigned,Assigned"
bitfld.long 0x00 17. "W1_ID4,Way group 1 is assigned as private to scheme ID 4" "Not assigned,Assigned"
newline
bitfld.long 0x00 16. "W0_ID4,Way group 0 is assigned as private to scheme ID 4" "Not assigned,Assigned"
bitfld.long 0x00 15. "W3_ID3,Way group 3 is assigned as private to scheme ID 3" "Not assigned,Assigned"
bitfld.long 0x00 14. "W2_ID3,Way group 2 is assigned as private to scheme ID 3" "Not assigned,Assigned"
newline
bitfld.long 0x00 13. "W1_ID3,Way group 1 is assigned as private to scheme ID 3" "Not assigned,Assigned"
bitfld.long 0x00 12. "W0_ID3,Way group 0 is assigned as private to scheme ID 3" "Not assigned,Assigned"
bitfld.long 0x00 11. "W3_ID2,Way group 3 is assigned as private to scheme ID 2" "Not assigned,Assigned"
newline
bitfld.long 0x00 10. "W2_ID2,Way group 2 is assigned as private to scheme ID 2" "Not assigned,Assigned"
bitfld.long 0x00 9. "W1_ID2,Way group 1 is assigned as private to scheme ID 2" "Not assigned,Assigned"
bitfld.long 0x00 8. "W0_ID2,Way group 0 is assigned as private to scheme ID 2" "Not assigned,Assigned"
newline
bitfld.long 0x00 7. "W3_ID1,Way group 3 is assigned as private to scheme ID 1" "Not assigned,Assigned"
bitfld.long 0x00 6. "W2_ID1,Way group 2 is assigned as private to scheme ID 1" "Not assigned,Assigned"
bitfld.long 0x00 5. "W1_ID1,Way group 1 is assigned as private to scheme ID 1" "Not assigned,Assigned"
newline
bitfld.long 0x00 4. "W0_ID1,Way group 0 is assigned as private to scheme ID 1" "Not assigned,Assigned"
bitfld.long 0x00 3. "W3_ID0,Way group 3 is assigned as private to scheme ID 0" "Not assigned,Assigned"
bitfld.long 0x00 2. "W2_ID0,Way group 2 is assigned as private to scheme ID 0" "Not assigned,Assigned"
newline
bitfld.long 0x00 1. "W1_ID0,Way group 1 is assigned as private to scheme ID 0" "Not assigned,Assigned"
bitfld.long 0x00 0. "W0_ID0,Way group 0 is assigned as private to scheme ID 0" "Not assigned,Assigned"
group.quad spr:0x30F44++0x00
line.long 0x00 "CLUSTERBUSQOS_EL1,Cluster Bus QoS Control Register"
bitfld.long 0x00 28.--31. "CHI_BUS_QOS_SCHEME_ID7,Value driven on the CHI bus QoS field for scheme ID 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "CHI_BUS_QOS_SCHEME_ID6,Value driven on the CHI bus QoS field for scheme ID 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 20.--23. "CHI_BUS_QOS_SCHEME_ID5,Value driven on the CHI bus QoS field for scheme ID 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 16.--19. "CHI_BUS_QOS_SCHEME_ID4,Value driven on the CHI bus QoS field for scheme ID 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "CHI_BUS_QOS_SCHEME_ID3,Value driven on the CHI bus QoS field for scheme ID 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "CHI_BUS_QOS_SCHEME_ID2,Value driven on the CHI bus QoS field for scheme ID 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "CHI_BUS_QOS_SCHEME_ID1,Value driven on the CHI bus QoS field for scheme ID 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "CHI_BUS_QOS_SCHEME_ID0,Value driven on the CHI bus QoS field for scheme ID 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.quad spr:0x30F45++0x00
line.long 0x00 "CLUSTERL3HIT_EL1,Cluster L3 Hit Counter Register"
group.quad spr:0x30F46++0x00
line.long 0x00 "CLUSTERL3MISS_EL1,Cluster L3 Miss Counter Register"
group.quad spr:0x30F47++0x00
line.long 0x00 "CLUSTERTHREADSIDOVR_EL1,Cluster Thread Scheme ID Override Register"
bitfld.long 0x00 16.--18. "SCHEME_ID_MASK,A bit set in the mask causes the matching bit to be taken from this register rather than from the CLUSTERTHREADSID_EL1 register" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "SCHEME_ID_THREAD,Scheme ID for this thread if masked" "0,1,2,3,4,5,6,7"
tree.end
tree "Error System Registers"
rgroup.quad spr:0x30530++0x00
line.long 0x00 "ERRIDR_EL1,Error ID Register"
hexmask.long.word 0x00 0.--15. 1. "NUM,Number of records that can be accessed through the Error Record system registers"
group.quad spr:0x30531++0x00
line.quad 0x00 "ERRSELR_EL1,Error Record Select Register"
bitfld.quad 0x00 0. "SEL,Selects the record accessed through the ERX registers" "Record 0 - Core,Record 1 - DSU"
if (((per.q(spr:0x30531))&0x01)==0x00)
if (CORENAME()=="CORTEXA75")
rgroup.quad spr:0x30540++0x00
line.quad 0x00 "ERXFR_EL1,Error Record Feature Register"
bitfld.quad 0x00 10.--11. "CFI,Fault handling interrupt for corrected errors" "Reserved,Reserved,Implemented,?..."
bitfld.quad 0x00 6.--7. "FI,Fault handling interrupt" "Reserved,Reserved,Implemented,?..."
bitfld.quad 0x00 4.--5. "UI,Error recovery interrupt for uncorrected errors" "Reserved,Reserved,Implemented,?..."
newline
bitfld.quad 0x00 0.--1. "ED,Error detection and correction" "Reserved,Reserved,Implemented,?..."
group.quad spr:0x30541++0x00
line.quad 0x00 "ERXCTLR_EL1,Selected Error Record Control Register"
bitfld.quad 0x00 8. "CFI,Fault handling interrupt for corrected errors enable" "No interrupt,Interrupt"
bitfld.quad 0x00 3. "FI,Fault handling interrupt enable" "No interrupt,Interrupt"
bitfld.quad 0x00 2. "UI,Uncorrected error recovery interrupt enable" "No interrupt,Interrupt"
group.quad spr:0x30542++0x00
line.long 0x00 "ERXSTATUS_EL1,Selected Error Record Status Register"
bitfld.long 0x00 31. "AV,Address valid" "Not valid,Valid"
bitfld.long 0x00 30. "V,Status register valid" "Not valid,Valid"
bitfld.long 0x00 29. "UE,Uncorrected Error" "No error,>=1 error"
newline
bitfld.long 0x00 28. "ER,Error reported" "No error,Error"
bitfld.long 0x00 27. "OF,Error overflow" "No error,>1 error"
bitfld.long 0x00 26. "MV,Miscellaneous registers valid" "Not valid,Valid"
newline
bitfld.long 0x00 24.--25. "CE,Corrected errors" "No error,Reserved,>=1 error,?..."
bitfld.long 0x00 23. "DE,Deferred errors" "No error,>=1 error"
bitfld.long 0x00 22. "PN,Poison" "No distinction,?..."
newline
bitfld.long 0x00 20.--21. "UET,Uncorrected error type" "Uncontainable,?..."
newline
abitfld.long 0x00 0.--7. "SERR,Primary error code" "0x00=No error,0x02=ECC/internal data buffer,0x06=ECC/Cache data RAM,0x07=ECC/Cache tag/Dirty RAM,0x08=Parity/TLB data,0x09=Parity/TLB tag,0x15=Deferred not supported"
group.quad spr:0x30543++0x00
line.quad 0x00 "ERXADDR_EL1,Selected Error Record Address Register"
bitfld.quad 0x00 63. "NS,Non-secure attribute" "Secure,Non-secure"
bitfld.quad 0x00 62. "SI,Secure incorrect" "Non secure,Secure"
bitfld.quad 0x00 61. "AI,Address incomplete or incorrect" "Correct,Not correct"
hexmask.quad 0x00 0.--43. 0x01 "PADDR,Physical address"
group.quad spr:0x30550++0x00
line.quad 0x00 "ERXMISC0_EL1,Selected Error Record Miscellaneous Register 0"
hexmask.quad.byte 0x00 32.--47. 1. "CECO,Corrected error count other"
bitfld.quad 0x00 28.--31. "WAY,Indicates the way that contained the error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.quad.word 0x00 6.--18. 1. "INDX,Indicates the index that contained the error"
newline
bitfld.quad 0x00 5. "TLBRAM,Indicates which TLB RAM block the error occurs" "RAM 0,RAM 1"
bitfld.quad 0x00 1.--3. "LVL,Indicates the level that contained the error" "level 1,Level 2,?..."
bitfld.quad 0x00 0. "IND,Indicates the type of cache that contained the error" "L1 data/Unified L2/TLB,L1 instruction"
group.quad spr:0x30551++0x00
line.quad 0x00 "ERXMISC1_EL1,Selected Error Record Miscellaneous Register 1"
group.quad spr:0x30F22++0x00
line.long 0x00 "ERXPFGCDN_EL1,Selected Error Pseudo Fault Generation Count Down Register"
group.quad spr:0x30F21++0x00
line.quad 0x00 "ERXPFGCTL_EL1,Selected Error Pseudo Fault Generation Control Register"
bitfld.quad 0x00 31. "CDNEN,Count down enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 30. "R,Restart" "Stop,Reloaded"
bitfld.quad 0x00 6. "CE,Corrected error generation enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 5. "DE,Deferred Error generation enable" "Disabled,Enabled"
bitfld.quad 0x00 1. "UC,Uncontainable error generation enable" "Disabled,Enabled"
rgroup.quad spr:0x30F20++0x00
line.quad 0x00 "ERXPFGF_EL1,Selected Pseudo Fault Generation Feature Register"
bitfld.quad 0x00 31. "PFG,Pseudo fault generation" "Reserved,Supported"
bitfld.quad 0x00 30. "R,Error Generation Counter restart mode support" "Reserved,Supported"
newline
bitfld.quad 0x00 6. "CE,Corrected Error generation" "Reserved,Supported"
bitfld.quad 0x00 5. "DE,Deferred error generation" "Reserved,Supported"
newline
bitfld.quad 0x00 4. "UEO,Latent or restartable error generation" "Not supported,?..."
bitfld.quad 0x00 3. "UER,Signaled or recoverable error generation" "Not supported,?..."
newline
bitfld.quad 0x00 2. "UEU,Unrecoverable error generation" "Not supported,?..."
bitfld.quad 0x00 1. "UC,Uncontainable error generation" "Reserved,Supported"
elif (CORENAME()=="CORTEXA55")
rgroup.quad spr:0x30540++0x00
line.quad 0x00 "ERXFR_EL1,Error Record Feature Register"
bitfld.quad 0x00 18.--19. "CEO,Corrected Error Overwrite" "Count CE,?..."
bitfld.quad 0x00 16.--17. "DUI,Error recovery interrupt for deferred errors" "Not supported,?..."
bitfld.quad 0x00 15. "RP,Repeat counter" "Reserved,Implemented"
newline
bitfld.quad 0x00 12.--14. "CEC,Corrected Error Counter" "Reserved,Reserved,8-bit,?..."
bitfld.quad 0x00 10.--11. "CFI,Fault handling interrupt for corrected errors" "Reserved,Reserved,Implemented,?..."
bitfld.quad 0x00 8.--9. "UE,In-band uncorrected error reporting" "Reserved,Implemented,?..."
newline
bitfld.quad 0x00 6.--7. "FI,Fault handling interrupt" "Reserved,Reserved,Implemented,?..."
bitfld.quad 0x00 4.--5. "UI,Error recovery interrupt for uncorrected errors" "Reserved,Reserved,Implemented,?..."
bitfld.quad 0x00 2.--3. "DE,Defers errors" "Reserved,Enabled,?..."
newline
bitfld.quad 0x00 0.--1. "ED,Error detection and correction" "Reserved,Reserved,Implemented,?..."
group.quad spr:0x30541++0x00
line.quad 0x00 "ERXCTLR_EL1,Selected Error Record Control Register"
bitfld.quad 0x00 8. "CFI,Fault handling interrupt for corrected errors enable" "No interrupt,Interrupt"
bitfld.quad 0x00 3. "FI,Fault handling interrupt enable" "No interrupt,Interrupt"
bitfld.quad 0x00 2. "UI,Uncorrected error recovery interrupt enable" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 0. "ED,Error detection and correction enable" "Disabled,Enabled"
group.quad spr:0x30542++0x00
line.long 0x00 "ERXSTATUS_EL1,Selected Error Record Status Register"
bitfld.long 0x00 31. "AV,Address valid" "Not valid,?..."
bitfld.long 0x00 30. "V,Status register valid" "Not valid,Valid"
bitfld.long 0x00 29. "UE,Uncorrected Error" "No error,>=1 error"
newline
bitfld.long 0x00 28. "ER,Error reported" "No error,Error"
bitfld.long 0x00 27. "OF,Error overflow" "No error,>1 error"
bitfld.long 0x00 26. "MV,Miscellaneous registers valid" "Not valid,Valid"
newline
bitfld.long 0x00 24.--25. "CE,Corrected errors" "No error,Reserved,>=1 error,?..."
bitfld.long 0x00 23. "DE,Deferred errors" "No error,>=1 error"
bitfld.long 0x00 22. "PN,Poison" "No distinction,?..."
newline
bitfld.long 0x00 20.--21. "UET,Uncorrected error type" "Uncontainable,?..."
newline
abitfld.long 0x00 8.--15. "IERR,Implementation defined error code" "0x00=No error/Other RAMs,0x01=Error/L3 snoop RAM"
abitfld.long 0x00 0.--7. "SERR,Primary error code" "0x00=No error,0x02=ECC/internal data buffer,0x06=ECC/Cache data RAM,0x07=ECC/Cache tag/Dirty RAM,0x08=Parity/TLB data,0x09=Parity/TLB tag,0x15=Deferred not supported"
rgroup.quad spr:0x30543++0x00
line.quad 0x00 "ERXADDR_EL1,Selected Error Record Address Register"
group.quad spr:0x30550++0x00
line.quad 0x00 "ERXMISC0_EL1,Selected Error Record Miscellaneous Register 0"
bitfld.quad 0x00 47. "OFO,Sticky overflow bit other" "No overflow,Overflow"
hexmask.quad.byte 0x00 40.--46. 1. "CECO,Corrected error count other"
bitfld.quad 0x00 39. "OFR,Sticky overflow bit repeat" "No overflow,Overflow"
newline
hexmask.quad.byte 0x00 32.--38. 1. "CECR,Repeat error count"
bitfld.quad 0x00 28.--31. "WAY,Indicates the way that contained the error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.quad.word 0x00 6.--18. 1. "INDX,Indicates the index that contained the error"
newline
bitfld.quad 0x00 1.--3. "LVL,Indicates the level that contained the error" "level 1,Level 2,?..."
bitfld.quad 0x00 0. "IND,Indicates the type of cache that contained the error" "L1 data/Unified L2/TLB,L1 instruction"
group.quad spr:0x30551++0x00
line.quad 0x00 "ERXMISC1_EL1,Selected Error Record Miscellaneous Register 1"
group.quad spr:0x30F22++0x00
line.long 0x00 "ERXPFGCDN_EL1,Selected Error Pseudo Fault Generation Count Down Register"
group.quad spr:0x30F21++0x00
line.quad 0x00 "ERXPFGCTL_EL1,Selected Error Pseudo Fault Generation Control Register"
bitfld.quad 0x00 31. "CDNEN,Count down enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 30. "R,Restart" "Stop,Reloaded"
bitfld.quad 0x00 6. "CE,Corrected error generation enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 5. "DE,Deferred Error generation enable" "Disabled,Enabled"
bitfld.quad 0x00 3. "UER,Signaled or recoverable error generation enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 1. "UC,Uncontainable error generation enable" "Disabled,Enabled"
rgroup.quad spr:0x30F20++0x00
line.quad 0x00 "ERXPFGF_EL1,Selected Pseudo Fault Generation Feature Register"
bitfld.quad 0x00 31. "PFG,Pseudo fault generation" "Not supported,Supported"
bitfld.quad 0x00 30. "R,Error Generation Counter restart mode support" "Reserved,Supported"
newline
bitfld.quad 0x00 6. "CE,Corrected Error generation" "Not supported,Supported"
bitfld.quad 0x00 5. "DE,Deferred error generation" "Not supported,Supported"
newline
bitfld.quad 0x00 4. "UEO,Latent or restartable error generation" "Not supported,?..."
bitfld.quad 0x00 3. "UER,Signaled or recoverable error generation" "Not supported,Supported"
newline
bitfld.quad 0x00 2. "UEU,Unrecoverable error generation" "Not supported,?..."
bitfld.quad 0x00 1. "UC,Uncontainable error generation" "Not supported,Supported"
endif
else
rgroup.quad spr:0x30540++0x00
line.quad 0x00 "ERXFR_EL1,Error Record Feature Register"
bitfld.quad 0x00 18.--19. "CEO,Corrected Error Overwrite" "Count CE,?..."
bitfld.quad 0x00 16.--17. "DUI,Error recovery interrupt for deferred errors" "Not supported,?..."
bitfld.quad 0x00 15. "RP,Repeat counter" "Reserved,Implemented"
newline
bitfld.quad 0x00 12.--14. "CEC,Corrected Error Counter" "Reserved,Reserved,8-bit,?..."
bitfld.quad 0x00 10.--11. "CFI,Fault handling interrupt for corrected errors" "Reserved,Reserved,Implemented,?..."
bitfld.quad 0x00 8.--9. "UE,In-band uncorrected error reporting" "Reserved,Implemented,?..."
newline
bitfld.quad 0x00 6.--7. "FI,Fault handling interrupt" "Reserved,Reserved,Implemented,?..."
bitfld.quad 0x00 4.--5. "UI,Error recovery interrupt for uncorrected errors" "Reserved,Enabled,Implemented,?..."
bitfld.quad 0x00 2.--3. "DE,Defers errors" "Reserved,Enabled,?..."
newline
bitfld.quad 0x00 0.--1. "ED,Error detection and correction" "Reserved,Enabled,Implemented,?..."
group.quad spr:0x30541++0x00
line.quad 0x00 "ERXCTLR_EL1,Selected Error Record Control Register"
bitfld.quad 0x00 8. "CFI,Fault handling interrupt for corrected errors enable" "No interrupt,Interrupt"
bitfld.quad 0x00 3. "FI,Fault handling interrupt enable" "No interrupt,Interrupt"
bitfld.quad 0x00 2. "UI,Uncorrected error recovery interrupt enable" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 0. "ED,Error detection and correction enable" "Disabled,Enabled"
group.quad spr:0x30542++0x00
line.long 0x00 "ERXSTATUS_EL1,Selected Error Record Status Register"
bitfld.long 0x00 31. "AV,Address valid" "Not valid,?..."
bitfld.long 0x00 30. "V,Status register valid" "Not valid,Valid"
bitfld.long 0x00 29. "UE,Uncorrected Error" "No error,>=1 error"
newline
bitfld.long 0x00 28. "ER,Error reported" "No error,?..."
bitfld.long 0x00 27. "OF,Error overflow" "No error,>1 error"
bitfld.long 0x00 26. "MV,Miscellaneous registers valid" "Not valid,Valid"
newline
bitfld.long 0x00 24.--25. "CE,Corrected errors" "No error,Reserved,>=1 error,?..."
bitfld.long 0x00 23. "DE,Deferred errors" "No error,>=1 error"
bitfld.long 0x00 22. "PN,Poison" "No distinction,Earlier"
newline
bitfld.long 0x00 20.--21. "UET,Uncorrected error type" "Uncontainable,?..."
newline
bitfld.long 0x00 8.--15. "IERR,Implementation defined error code" "No error/Other RAMs,Reserved,Error/L3 snoop RAM,?..."
bitfld.long 0x00 0.--7. "SERR,Primary error code" "No error,Reserved,ECC/internal data buffer,Reserved,Reserved,Reserved,ECC/Cache data RAM,ECC/Cache tag/Dirty RAM,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Bus error,?..."
rgroup.quad spr:0x30543++0x00
line.quad 0x00 "ERXADDR_EL1,Selected Error Record Address Register"
group.quad spr:0x30550++0x00
line.quad 0x00 "ERXMISC0_EL1,Selected Error Record Miscellaneous Register 0"
bitfld.quad 0x00 47. "OFO,Sticky overflow bit other" "No overflow,Overflow"
hexmask.quad.byte 0x00 40.--46. 1. "CECO,Corrected error count other"
bitfld.quad 0x00 39. "OFR,Sticky overflow bit repeat" "No overflow,Overflow"
newline
hexmask.quad.byte 0x00 32.--38. 1. "CECR,Repeat error count"
bitfld.quad 0x00 28.--31. "WAY,Indicates the way that contained the error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.quad.word 0x00 6.--18. 1. "INDX,Indicates the index that contained the error"
newline
bitfld.quad 0x00 1.--3. "LVL,Indicates the level that contained the error" "Reserved,Reserved,Level 3,?..."
bitfld.quad 0x00 0. "IND,Indicates the type of cache that contained the error" "L3 cache,?..."
group.quad spr:0x30551++0x00
line.quad 0x00 "ERXMISC1_EL1,Selected Error Record Miscellaneous Register 1"
group.quad spr:0x30F22++0x00
line.long 0x00 "ERXPFGCDN_EL1,Selected Error Pseudo Fault Generation Count Down Register"
group.quad spr:0x30F21++0x00
line.quad 0x00 "ERXPFGCTL_EL1,Selected Error Pseudo Fault Generation Control Register"
bitfld.quad 0x00 31. "CDNEN,Count down enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 30. "R,Restart" "Stop,Reloaded"
bitfld.quad 0x00 6. "CE,Corrected error generation" "Not generated,Generated"
newline
bitfld.quad 0x00 5. "DE,Deferred Error generation enable" "Not generated,Generated"
bitfld.quad 0x00 1. "UC,Signaled or recoverable error generation enable" "Not supported,Controllable"
rgroup.quad spr:0x30F20++0x00
line.quad 0x00 "ERXPFGF_EL1,Selected Pseudo Fault Generation Feature Register"
bitfld.quad 0x00 31. "PFG,Pseudo fault generation" "Not supported,Supported"
bitfld.quad 0x00 30. "R,Error Generation Counter restart mode support" "Reserved,Supported"
newline
bitfld.quad 0x00 6. "CE,Corrected Error generation" "Reserved,Supported"
bitfld.quad 0x00 5. "DE,Deferred error generation" "Reserved,Supported"
newline
bitfld.quad 0x00 4. "UEO,Latent or restartable error generation" "Not supported,?..."
bitfld.quad 0x00 3. "UER,Signaled or recoverable error generation" "Not supported,?..."
newline
bitfld.quad 0x00 2. "UEU,Unrecoverable error generation" "Not supported,?..."
bitfld.quad 0x00 1. "UC,Uncontainable error generation" "Reserved,Supported"
endif
tree.end
tree "Cluster PMU Registers"
group.quad spr:0x30F50++0x00
line.long 0x00 "CLUSTERPMCR_EL1,Cluster Performance Monitors Control Register (EL1)"
hexmask.long.byte 0x00 24.--31. 1. "IMP,Implementer code"
hexmask.long.byte 0x00 16.--23. 1. "IDCODE,Identification code"
bitfld.long 0x00 11.--15. "N,Number of counters implemented" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,6,?..."
newline
bitfld.long 0x00 2. "C,Clock Counter Reset" "No reset,Reset"
bitfld.long 0x00 1. "P,Event Counter Reset" "No reset,Reset"
newline
bitfld.long 0x00 0. "E,All Counters Enable" "Disabled,Enabled"
group.quad spr:0x30F51++0x00
line.long 0x00 "CLUSTERPMCNTENSET_EL1,Cluster Count Enable Set Register (EL1)"
bitfld.long 0x00 31. "C,Enables the cycle counter register [Read/Write]" "Disabled/No effect,Enabled/Enable"
newline
bitfld.long 0x00 5. "P5,Event counter PMN 5 enable bit [Read/Write]" "Disabled/No effect,Enabled/Enable"
bitfld.long 0x00 4. "P4,Event counter PMN 4 enable bit [Read/Write]" "Disabled/No effect,Enabled/Enable"
bitfld.long 0x00 3. "P3,Event counter PMN 3 enable bit [Read/Write]" "Disabled/No effect,Enabled/Enable"
newline
bitfld.long 0x00 2. "P2,Event counter PMN 2 enable bit [Read/Write]" "Disabled/No effect,Enabled/Enable"
bitfld.long 0x00 1. "P1,Event counter PMN 1 enable bit [Read/Write]" "Disabled/No effect,Enabled/Enable"
bitfld.long 0x00 0. "P0,Event counter PMN 0 enable bit [Read/Write]" "Disabled/No effect,Enabled/Enable"
group.quad spr:0x30F52++0x00
line.long 0x00 "CLUSTERPMCNTENCLR_EL1,Cluster Count Enable Clear Register (EL1)"
bitfld.long 0x00 31. "C,Disables the cycle counter register [Read/Write]" "Disabled/No effect,Enabled/Disable"
newline
bitfld.long 0x00 5. "P5,Event counter PMN 5 disable bit [Read/Write]" "Disabled/No effect,Enabled/Disable"
bitfld.long 0x00 4. "P4,Event counter PMN 4 disable bit [Read/Write]" "Disabled/No effect,Enabled/Disable"
bitfld.long 0x00 3. "P3,Event counter PMN 3 disable bit [Read/Write]" "Disabled/No effect,Enabled/Disable"
newline
bitfld.long 0x00 2. "P2,Event counter PMN 2 disable bit [Read/Write]" "Disabled/No effect,Enabled/Disable"
bitfld.long 0x00 1. "P1,Event counter PMN 1 disable bit [Read/Write]" "Disabled/No effect,Enabled/Disable"
bitfld.long 0x00 0. "P0,Event counter PMN 0 disable bit [Read/Write]" "Disabled/No effect,Enabled/Disable"
group.quad spr:0x30F53++0x00
line.long 0x00 "CLUSTERPMOVSSET_EL1,Cluster Overflow Flag Status Set (EL1)"
bitfld.long 0x00 31. "C,PMCCNTR overflow bit [Read/Write]" "No overflow/No effect,Overflow/Set"
newline
bitfld.long 0x00 5. "P5,PMN5 Overflow set bit [Read/Write]" "No overflow/No effect,Overflow/Set"
bitfld.long 0x00 4. "P4,PMN4 Overflow set bit [Read/Write]" "No overflow/No effect,Overflow/Set"
bitfld.long 0x00 3. "P3,PMN3 Overflow set bit [Read/Write]" "No overflow/No effect,Overflow/Set"
newline
bitfld.long 0x00 2. "P2,PMN2 Overflow set bit [Read/Write]" "No overflow/No effect,Overflow/Set"
bitfld.long 0x00 1. "P1,PMN1 Overflow set bit [Read/Write]" "No overflow/No effect,Overflow/Set"
bitfld.long 0x00 0. "P0,PMN0 Overflow set bit [Read/Write]" "No overflow/No effect,Overflow/Set"
group.quad spr:0x30F54++0x00
line.long 0x00 "CLUSTERPMOVSCLR_EL1,Cluster Overflow Flag Status Clear (EL1)"
eventfld.long 0x00 31. "C,PMCCNTR overflow bit [Read/Write]" "No overflow/No effect,Overflow/Clear"
newline
eventfld.long 0x00 5. "P5,PMN5 overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear"
eventfld.long 0x00 4. "P4,PMN4 Overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear"
eventfld.long 0x00 3. "P3,PMN3 Overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear"
newline
eventfld.long 0x00 2. "P2,PMN2 Overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear"
eventfld.long 0x00 1. "P1,PMN1 Overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear"
eventfld.long 0x00 0. "P0,PMN0 Overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear"
group.quad spr:0x30F55++0x00
line.long 0x00 "CLUSTERPMSELR_EL1,Cluster Event Counter Selection Register (EL1)"
bitfld.long 0x00 0.--4. "SEL,Current event counter select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.quad spr:0x30F56++0x00
line.long 0x00 "CLUSTERPMINTENSET_EL1,Cluster Interrupt Enable Set Register (EL1)"
bitfld.long 0x00 31. "C,PMCCNTR Overflow Interrupt Request Enable [Read/Write]" "Disabled/No effect,Enabled/Enable"
newline
bitfld.long 0x00 5. "P5,PMCNT5 Overflow Interrupt Request Enable [Read/Write]" "Disabled/No effect,Enabled/Enable"
bitfld.long 0x00 4. "P4,PMCNT4 Overflow Interrupt Request Enable [Read/Write]" "Disabled/No effect,Enabled/Enable"
bitfld.long 0x00 3. "P3,PMCNT3 Overflow Interrupt Request Enable [Read/Write]" "Disabled/No effect,Enabled/Enable"
newline
bitfld.long 0x00 2. "P2,PMCNT2 Overflow Interrupt Request Enable [Read/Write]" "Disabled/No effect,Enabled/Enable"
bitfld.long 0x00 1. "P1,PMCNT1 Overflow Interrupt Request Enable [Read/Write]" "Disabled/No effect,Enabled/Enable"
bitfld.long 0x00 0. "P0,PMCNT0 Overflow Interrupt Request Enable [Read/Write]" "Disabled/No effect,Enabled/Enable"
group.quad spr:0x30F57++0x00
line.long 0x00 "CLUSTERPMINTENCLR_EL1,Cluster Interrupt Enable Clear Register (EL1)"
eventfld.long 0x00 31. "C,PMCCNTR Overflow Interrupt Request Disable [Read/Write]" "Disabled/No effect,Enabled/Disable"
newline
eventfld.long 0x00 5. "P5,PMCNT5 Overflow Interrupt Disable [Read/Write]" "Disabled/No effect,Enabled/Disable"
eventfld.long 0x00 4. "P4,PMCNT4 Overflow Interrupt Disable [Read/Write]" "Disabled/No effect,Enabled/Disable"
eventfld.long 0x00 3. "P3,PMCNT3 Overflow Interrupt Disable [Read/Write]" "Disabled/No effect,Enabled/Disable"
newline
eventfld.long 0x00 2. "P2,PMCNT2 Overflow Interrupt Disable [Read/Write]" "Disabled/No effect,Enabled/Disable"
eventfld.long 0x00 1. "P1,PMCNT1 Overflow Interrupt Disable [Read/Write]" "Disabled/No effect,Enabled/Disable"
eventfld.long 0x00 0. "P0,PMCNT0 Overflow Interrupt Disable [Read/Write]" "Disabled/No effect,Enabled/Disable"
if (((per.l(spr:0x30F55))&0x1F)<=0x05)
if (((per.q(spr:0x30F61))&0x80000000)==0x00)
group.quad spr:0x30F61++0x00
line.long 0x00 "CLUSTERPMXEVTYPER_EL1,Cluster Selected Event Type and Filter Register (EL1)"
bitfld.long 0x00 31. "S,Count events in EL1 disable" "No,Yes"
bitfld.long 0x00 29. "NS,Count events in non-secure EL2 disable" "No,Yes"
newline
hexmask.long.word 0x00 0.--15. 1. "EVTCOUNT,Event number"
else
group.quad spr:0x30F61++0x00
line.long 0x00 "CLUSTERPMXEVTYPER_EL1,Cluster Selected Event Type and Filter Register (EL1)"
bitfld.long 0x00 31. "S,Count events in EL1 disable" "No,Yes"
bitfld.long 0x00 29. "NS,Count events in non-secure EL2 disable" "Yes,No"
newline
hexmask.long.word 0x00 0.--15. 1. "EVTCOUNT,Event number"
endif
else
rgroup.quad spr:0x30F61++0x00
line.long 0x00 "CLUSTERPMXEVTYPER_EL1,Cluster Selected Event Type and Filter Register (EL1)"
endif
group.quad spr:0x30F62++0x00
line.long 0x00 "CLUSTERPMXEVCNTR_EL1,Cluster Selected Event Counter Register (EL1)"
tree.open "Common Event Identification Registers"
rgroup.quad spr:0x30F64++0x00
line.long 0x00 "CLUSTERPMCEID0_EL1,Cluster Common Event Identification ID0 Register (EL1)"
bitfld.long 0x00 30. "CHAIN,Chain" "Reserved,Implemented"
bitfld.long 0x00 29. "BUS_CYCLES,Bus cycle" "Reserved,Implemented"
bitfld.long 0x00 26. "MEMORY_ERROR,Local memory error" "Reserved,Implemented"
newline
bitfld.long 0x00 25. "BUS_ACCESS,Bus access" "Reserved,Implemented"
bitfld.long 0x00 17. "CPU_CYCLES,CPU Cycle" "Reserved,Implemented"
rgroup.quad spr:0x30F65++0x00
line.long 0x00 "CLUSTERPMCEID1_EL1,Cluster Common Event Identification ID1 Register (EL1)"
bitfld.long 0x00 12. "L3D_CACHE_WB,Attributable Level 3 data or unified cache write-back" "Reserved,Implemented"
bitfld.long 0x00 11. "L3D_CACHE,Attributable Level 3 data or unified cache access" "Reserved,Implemented"
bitfld.long 0x00 10. "L3D_CACHE_REFILL,Attributable Level 3 data or unified cache refill" "Reserved,Implemented"
newline
bitfld.long 0x00 9. "L3D_CACHE_ALLOCATE,Attributable Level 3 data or unified cache allocation without refill" "Reserved,Implemented"
tree.end
newline
group.quad spr:0x30F66++0x00
line.long 0x00 "CLUSTERPMCLAIMSET_EL1,Cluster Performance Monitor Claim Tag Set Register (EL1)"
bitfld.long 0x00 3. "S[3],Set bit 3 [Read/Write]" "Not implemented/No effect,Implemented/Set"
bitfld.long 0x00 2. "S[2],Set bit 2 [Read/Write]" "Not implemented/No effect,Implemented/Set"
bitfld.long 0x00 1. "S[1],Set bit 1 [Read/Write]" "Not implemented/No effect,Implemented/Set"
bitfld.long 0x00 0. "S[0],Set bit 0 [Read/Write]" "Not implemented/No effect,Implemented/Set"
group.quad spr:0x30F67++0x00
line.long 0x00 "CLUSTERPMCLAIMCLR_EL1,Cluster Performance Monitor Claim Tag Clear Register (EL1)"
bitfld.long 0x00 3. "C[3],Clear bit 3 [Read/Write]" "Not implemented/No effect,Implemented/Set"
bitfld.long 0x00 2. "C[2],Clear bit 2 [Read/Write]" "Not implemented/No effect,Implemented/Set"
bitfld.long 0x00 1. "C[1],Clear bit 1 [Read/Write]" "Not implemented/No effect,Implemented/Set"
bitfld.long 0x00 0. "C[0],Clear bit 0 [Read/Write]" "Not implemented/No effect,Implemented/Set"
tree.end
tree.end
tree.end
tree.open "AArch32"
tree "ID Registers"
rgroup.long c15:0x0010++0x00
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
bitfld.long 0x00 28.--31. "RAS,RAS extension version" "Reserved,Version 1,?..."
newline
bitfld.long 0x00 12.--15. "STATE3,Thumb Execution Environment (Thumb-EE) Support" "Not supported,?..."
bitfld.long 0x00 8.--11. "STATE2,Support for Jazelle extension" "Reserved,Trivial,?..."
bitfld.long 0x00 4.--7. "STATE1,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,After Thumb-2,?..."
newline
bitfld.long 0x00 0.--3. "STATE0,ARM Instruction Set Support" "Reserved,Supported,?..."
rgroup.long c15:0x0110++0x00
line.long 0x00 "ID_PFR1,Processor Feature Register 1"
bitfld.long 0x00 28.--31. "GIC_CPU,GIC CPU Support" "Disabled,Enabled,?..."
newline
bitfld.long 0x00 16.--19. "GT,Generic Timer Support" "Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "VE,Virtualization Extensions Support" "Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "MPM,Microcontroller Programmer's Model Support" "Not supported,?..."
newline
bitfld.long 0x00 4.--7. "SE,Security Extensions Architecture v1 Support" "Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "PM,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..."
rgroup.long c15:0x0310++0x00
line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
rgroup.long c15:0x0410++0x00
line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
bitfld.long 0x00 28.--31. "IS,Indicates innermost shareability domain implemented" "Reserved,HW coherency,?..."
bitfld.long 0x00 24.--27. "FCSE,Fast Context Switch Memory Mappings Support" "Not supported,?..."
bitfld.long 0x00 20.--23. "AR,Auxiliary Register Support" "Reserved,Reserved,Control/Fault Status,?..."
newline
bitfld.long 0x00 16.--19. "TCM,TCM and Associated DMA Support" "Not supported,?..."
bitfld.long 0x00 12.--15. "SL,Shareability levels" "Reserved,Implemented 2 levels,?..."
bitfld.long 0x00 8.--11. "OSS,Outer Shareable Support" "Reserved,HW coherency,?..."
newline
bitfld.long 0x00 4.--7. "PMSA,Physical Memory System Architecture (PMSA) Support" "Not supported,?..."
bitfld.long 0x00 0.--3. "VMSA,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,VMSAv7/PXN/L-DESC,?..."
rgroup.long c15:0x0510++0x00
line.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
bitfld.long 0x00 28.--31. "BTB,Branch Predictor" "Reserved,Reserved,Reserved,Reserved,No flushing,?..."
bitfld.long 0x00 24.--27. "L1TCO,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 20.--23. "L1UCMO,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..."
newline
bitfld.long 0x00 16.--19. "L1HCMO,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Not supported,?..."
newline
bitfld.long 0x00 12.--15. "L1UCLMOSW,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 8.--11. "L1HCLMOSW,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Not supported,?..."
newline
bitfld.long 0x00 4.--7. "L1UCLMOMVA,L1 Cache Line Maintenance Operations by VA/Unified Architecture Support" "Not supported,?..."
newline
bitfld.long 0x00 0.--3. "L1HCLMOMVA,L1 Cache Line Maintenance Operations by VA/Harvard Architecture" "Not supported,?..."
rgroup.long c15:0x0610++0x00
line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
bitfld.long 0x00 28.--31. "HAF,Hardware Access Flag Support" "Not supported,?..."
bitfld.long 0x00 24.--27. "WFI,Wait for Interrupt Stalling Support" "Reserved,Supported,?..."
bitfld.long 0x00 20.--23. "MBF,Memory Barrier Operations Support" "Reserved,Reserved,DSB/ISB/DMB,?..."
newline
bitfld.long 0x00 16.--19. "UTLBMO,TLB Maintenance Operations/Unified Architecture Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,S2 operations,?..."
newline
bitfld.long 0x00 12.--15. "HTLBMO,TLB Maintenance Operations/Harvard Architecture Support" "Not supported,?..."
bitfld.long 0x00 8.--11. "HL1CMRO,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..."
bitfld.long 0x00 4.--7. "HL1BPCRO,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
newline
bitfld.long 0x00 0.--3. "HL1FPCRO,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
rgroup.long c15:0x0710++0x00
line.long 0x00 "ID_MMFR3,Memory Model Feature Register 3"
bitfld.long 0x00 28.--31. "SS,Supersection support" "Supported,?..."
bitfld.long 0x00 24.--27. "CMEMSZ,Cache memory size" "Reserved,Reserved,1TByte,?..."
bitfld.long 0x00 20.--23. "CW,Coherent walk" "Reserved,Not required,?..."
newline
bitfld.long 0x00 16.--19. "PAN,Privileged Access Never Support" "Reserved,Reserved,Extended,?..."
bitfld.long 0x00 12.--15. "MB,Maintenance broadcast Support" "Reserved,Reserved,Shareability/Defined behavior,?..."
bitfld.long 0x00 8.--11. "BPM,Invalidate Branch predictor Support" "Reserved,Reserved,Invalidate All/VA,?..."
newline
bitfld.long 0x00 4.--7. "CMSW,Cache maintenance by set/way" "Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "CMMVA,Cache maintenance by MVA" "Reserved,Supported,?..."
rgroup.long c15:0x0620++0x00
line.long 0x00 "ID_MMFR4,Memory Model Feature Register 4"
bitfld.long 0x00 20.--23. "LSM,LSMAOE and NTLSMD bits support" "Not supported,?..."
bitfld.long 0x00 16.--19. "HD,Hierarchical Permission Disables Support" "Reserved,Reserved,Extended,?..."
bitfld.long 0x00 12.--15. "CNP,Common not Private support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 8.--11. "XNX,EL0/EL1 execute control distinction at stage2 bit support" "Reserved,Supported,?..."
bitfld.long 0x00 4.--7. "AC2,Indicates the extension of the HACTLR Register using HACTLR2" "Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "SPECSEI,Describes whether the PE can generate SError interrupt exceptions" "Not possible,?..."
rgroup.long c15:0x0020++0x00
line.long 0x00 "ID_ISAR0,ID_ISAR0"
bitfld.long 0x00 24.--27. "DIVI,Divide Instructions Support" "Reserved,Reserved,T32/A32,?..."
bitfld.long 0x00 20.--23. "DEBI,Debug Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 16.--19. "CI,Coprocessor Instructions Support" "Not supported,?..."
newline
bitfld.long 0x00 12.--15. "CBI,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "BI,Bitfield Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 4.--7. "BCI,Bit Counting Instructions Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 0.--3. "SI,Swap Instructions Support" "Not supported,?..."
rgroup.long c15:0x0120++0x00
line.long 0x00 "ID_ISAR1,ID_ISAR1"
bitfld.long 0x00 28.--31. "JI,Jazelle Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 24.--27. "INTI,Interwork Instructions Support" "Reserved,Reserved,Reserved,A32-BX like,?..."
bitfld.long 0x00 20.--23. "IMMI,Immediate Instructions Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 16.--19. "ITEI,If Then Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "EXTI,Extend Instructions Support" "Reserved,Reserved,Full support,?..."
bitfld.long 0x00 8.--11. "EARI,Exception A and R Instructions Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 4.--7. "EXIN,Exception in ARM Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "ENDI,Endian Instructions Support" "Reserved,Supported,?..."
rgroup.long c15:0x0220++0x00
line.long 0x00 "ID_ISAR2,ID_ISAR2"
bitfld.long 0x00 28.--31. "RI,Reversal Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 24.--27. "PSRI,PSR Instructions Support" "Not supported,Supported,?..."
bitfld.long 0x00 20.--23. "UMI,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,UMAAL,?..."
newline
bitfld.long 0x00 16.--19. "SMI,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
newline
bitfld.long 0x00 12.--15. "MI,Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "II,Multi-Access Interruptible Instructions Support" "Not supported,?..."
newline
bitfld.long 0x00 4.--7. "MHI,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Reserved,PLD/PLI/PLDW,?..."
bitfld.long 0x00 0.--3. "LSI,Load and Store Instructions Support" "Reserved,Reserved,Supported,?..."
rgroup.long c15:0x0320++0x00
line.long 0x00 "ID_ISAR3,ID_ISAR3"
bitfld.long 0x00 28.--31. "T32EE,Thumb-EE Extensions Support" "Not supported,?..."
bitfld.long 0x00 24.--27. "NOPI,True NOP Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 20.--23. "TCI,Thumb Copy Instructions Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 16.--19. "TBI,Table Branch Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "SPI,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "SVCI,SVC Instructions Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 4.--7. "SIMDI,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "SI,Saturate Instructions Support" "Reserved,Supported,?..."
rgroup.long c15:0x0420++0x00
line.long 0x00 "ID_ISAR4,ID_ISAR4"
bitfld.long 0x00 28.--31. "SWP_FRAC,Memory System Locking Support" "Not supported,?..."
bitfld.long 0x00 24.--27. "PSR_M_I,PSR_M Instructions Support" "Not supported,?..."
bitfld.long 0x00 20.--23. "SPRI,Synchronization Primitive instructions" "Supported,?..."
newline
bitfld.long 0x00 16.--19. "BI,Barrier Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "SMCI,SMC Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "WBI,Write-Back Instructions Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 4.--7. "WSI,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "UI,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..."
rgroup.long c15:0x0520++0x00
line.long 0x00 "ID_ISAR5,Instruction Set Attribute Register 5"
bitfld.long 0x00 24.--27. "RDM,Rounding Double Multiply Add/Subtract instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 16.--19. "CRC32,Indicates whether CRC32 instructions are implemented in AArch32 state" "Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "SHA2,Indicates whether SHA2 instructions are implemented in AArch32 state" "Not supported,Supported,?..."
newline
bitfld.long 0x00 8.--11. "SHA1,Indicates whether SHA1 instructions are implemented in AArch32 state" "Not supported,Supported,?..."
bitfld.long 0x00 4.--7. "AES,Indicates whether AES instructions are implemented in AArch32 state" "Not supported,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "SEVL,Indicates whether SEVL instruction is implemented in AArch32" "Reserved,Supported,?..."
rgroup.long c15:0x0720++0x00
line.long 0x00 "ID_ISAR6,Instruction Set Attribute Register 6"
bitfld.long 0x00 4.--7. "DP,Indicates UDOT and SDOT instructions in AArch32 state" "Reserved,Implemented,?..."
rgroup.long c15:0x0210++0x00
line.long 0x00 "ID_DFR0,Debug Feature Register"
bitfld.long 0x00 24.--27. "PMM,Performance Monitor Model Support" "Reserved,Reserved,Reserved,Reserved,Supported/16bit evtCount,?..."
bitfld.long 0x00 20.--23. "MDM_MM,Memory-mapped Debug Model for M profile processors Support" "Not supported,?..."
bitfld.long 0x00 16.--19. "TM_MM,Trace Model (Memory-Mapped) Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 12.--15. "CTM_CB,Coprocessor-Based Trace Debug Model Support" "Not supported,?..."
bitfld.long 0x00 4.--7. "SDM_CB,Secure Debug Model (Coprocessor) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Support v8.2,?..."
newline
bitfld.long 0x00 0.--3. "CDM_CB,Coprocessor Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Support v8.2,?..."
rgroup.long c15:0x0000++0x00
line.long 0x00 "MIDR,Main ID Register"
hexmask.long.byte 0x0 24.--31. 1. "IMPL,Implementer code"
bitfld.long 0x00 20.--23. "VAR,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "ARCH, Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,CPUID scheme"
newline
hexmask.long.word 0x00 4.--15. 1. "PART,Primary Part Number"
bitfld.long 0x00 0.--3. "REV,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long c15:0x0200++0x00
line.long 0x00 "TCMTR,TCM Type Register"
rgroup.long c15:0x0300++0x00
line.long 0x00 "TLBTR,TLB Type Register"
bitfld.long 0x00 0. "NU,Not Unified TLB" "Unified TLB,Separate Instruction and Data TLBs"
rgroup.long c15:0x0500++0x00
line.long 0x00 "MPIDR,Multiprocessor Affinity Register"
bitfld.long 0x00 30. "U,Processor is part of a multiprocessor or uniprocessor system" "Multiprocessor,?..."
bitfld.long 0x00 24. "MT,Lowest level of affinity consist of logical processors" "Not implemented,Implemented"
newline
hexmask.long.byte 0x00 16.--23. 1. "AFF2,Affinity level 2. Identifies different clusters within the system"
bitfld.long 0x00 8.--15. "AFF1,Affinity level 1. Identifies individual cores within the local FCM cluster" "CORE0,CORE1,CORE2,CORE3,CORE4,CORE5,CORE6,CORE7,?..."
hexmask.long.byte 0x00 0.--7. 1. "AFF0,Affinity level 0. Identifies individual threads within a multi-threaded core"
rgroup.long c15:0x0600++0x00
line.long 0x00 "REVIDR,Revision ID Register"
rgroup.long c15:0x1700++0x00
line.long 0x00 "AIDR,Auxiliary ID Register"
tree.end
tree "System Control and Configuration"
group.long c15:0x0001++0x00
line.long 0x0 "SCTLR,Control Register"
bitfld.long 0x00 30. "TE,T32 exception enable" "A32,T32"
bitfld.long 0x00 29. "AFE,Access Flag Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 28. "TRE,TEX remap enable" "Disabled,Enabled"
bitfld.long 0x00 25. "EE,Exception endianness" "Little,Big"
newline
bitfld.long 0x00 23. "SPAN,Set Privileged Access Never" "Disabled,Enabled"
bitfld.long 0x00 20. "UWXN,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced"
newline
bitfld.long 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
bitfld.long 0x00 18. "NTWE,Not trap WFE" "No,Yes"
newline
bitfld.long 0x00 16. "NTWI,Not trap WFI" "No,Yes"
bitfld.long 0x00 13. "V,Base Location of Exception Registers" "VBAR value,0xFFFF0000"
newline
bitfld.long 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled"
bitfld.long 0x00 8. "SED,SETEND Disable" "No,Yes"
newline
bitfld.long 0x00 5. "CP15BEN,C15 Barrier Enable" "Disabled,Enabled"
bitfld.long 0x00 4. "LSMAOE,Load/Store Multiple Atomicity and Ordering Enable" "Reserved,Enabled"
newline
bitfld.long 0x00 3. "NTLSMD,No Trap Load/Store Multiple to Device-nGRE/Device-nGnRE/Device-nGnRnE memory" "Reserved,No Trap"
bitfld.long 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
newline
bitfld.long 0x00 1. "A,Strict Alignment" "Disabled,Enabled"
bitfld.long 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled"
rgroup.quad c15:0x100F0++0x01
line.quad 0x00 "CPUACTLR,CPU Auxiliary Control Register"
if corename()=="CORTEXA75"
rgroup.quad c15:0x10F11++0x01
line.quad 0x00 "CPUACTLR2,CPU Auxiliary Control Register 2"
endif
if corename()=="CORTEXA75"
group.quad c15:0x140F0++0x01
line.quad 0x00 "CPUECTLR,CPU Extended Control Register"
bitfld.quad 0x00 22.--23. "L4_STREAM,Threshold for direct stream to L4 cache on store" "512KB,1024KB,2048KB,Disabled"
bitfld.quad 0x00 20.--21. "L3_STREAM,Threshold for direct stream to L3 cache on store" "64KB,256KB,512KB,Disabled"
newline
bitfld.quad 0x00 18.--19. "L2_STREAM,Threshold for direct stream to L2 cache on store" "16KB,64KB,128KB,Disabled"
bitfld.quad 0x00 10. "L3PF,Enable L3 prefetch requests sent by the stride prefetcher" "Disabled,Enabled"
newline
bitfld.quad 0x00 9. "L2PF,Enable L2 prefetch requests sent by the stride prefetcher" "Disabled,Enabled"
bitfld.quad 0x00 8. "L1PF,Enable L1 prefetch requests sent by the stride prefetcher" "Disabled,Enabled"
newline
bitfld.quad 0x00 7. "RPF,Enable L2 region prefetch requests" "Disabled,Enabled"
bitfld.quad 0x00 6. "MMUPF,Enable MMU prefetch requests" "Disabled,Enabled"
newline
bitfld.quad 0x00 5. "RPF_AGGRO,L2 region prefetcher aggressivity" "Longer,Shorter"
bitfld.quad 0x00 1. "RNSD_EXCL,Enables signaling of cacheable Exclusive loads on the internal interface between the core and the DSU" "Not use,Use"
newline
bitfld.quad 0x00 0. "EXTLLC,Type of last-level cache that is present in the system" "Internal,External"
elif corename()=="CORTEXA55"
group.quad c15:0x140F0++0x01
line.quad 0x00 "CPUECTLR,CPU Extended Control Register"
bitfld.quad 0x00 38.--39. "ATOM,Force most cacheable atomic instructions to be executed far in the L3 cache or beyond and near in the L1 cache" "Near - hit/unique | Far - miss/shared,Near,Far,Near - load | Far - store"
bitfld.quad 0x00 37. "L2FLUSH,L2 cache flush" "Enabled,Disabled"
newline
bitfld.quad 0x00 29.--30. "L3WSCTL,Write streaming no-L3-allocate threshold" "128th line,1024th line,4096th line,Disabled"
bitfld.quad 0x00 27.--28. "L2WSCTL,Write streaming no-L2-allocate threshold" "16th line,128th line,512th line,Disabled"
newline
bitfld.quad 0x00 25.--26. "L1WSCTL,Write streaming no-L1-allocate threshold" "4th line,64th line,128th line,Disabled"
bitfld.quad 0x00 13.--15. "L1PCTL,L1 Data prefetch control. Maximum number of outstanding data prefetches allowed in the L1 memory system" "Prefetch disabled,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 10.--12. "L3PCTL,L3 Data prefetch control. Maximum number of outstanding data prefetches allowed that can be sent to the L3 memory system" "16 lines,32 lines,Reserved,Reserved,Disabled,2 lines,4 lines,8 lines"
bitfld.quad 0x00 0. "EXTLLC,Type of last-level cache that is present in the system" "Internal,External"
endif
rgroup.long c15:0x608F++0x00
line.long 0x00 "CPUPSELR,CPU Private Selection Register"
rgroup.quad c15:0x618F++0x01
line.quad 0x00 "CPUPCR,CPU Private Control Register"
rgroup.quad c15:0x638F++0x01
line.quad 0x00 "CPUPMR,CPU Private Mask Register"
rgroup.quad c15:0x628F++0x01
line.quad 0x00 "CPUPOR,CPU Private Operation Register"
group.long c15:0x0101++0x00
line.long 0x00 "ACTLR,Auxiliary Control Register"
bitfld.long 0x00 12. "CLUSTERPMUEN,Performance Management Registers access control" "Not accessible,Accessible"
bitfld.long 0x00 11. "SMEN,Scheme Management Registers access control" "Not accessible,Accessible"
newline
bitfld.long 0x00 10. "TSIDEN,Thread Scheme ID Register enable" "Not accessible,Accessible"
bitfld.long 0x00 7. "PWREN,Power Control Registers access control" "Not accessible,Accessible"
newline
bitfld.long 0x00 5. "ERXPFGEN,Error Record Registers access control" "Not accessible,Accessible"
bitfld.long 0x00 1. "ECTLREN, Extended Control Registers access control" "Not accessible,Accessible"
newline
bitfld.long 0x00 0. "ACTLREN,Auxiliary Control Registers access control" "Not accessible,Accessible"
rgroup.long c15:0x0301++0x00
line.long 0x00 "ACTLR2,Auxiliary Control Register 2"
group.long c15:0x0201++0x00
line.long 0x00 "CPACR,Coprocessor Access Control Register 1"
bitfld.long 0x00 31. "ASEDIS,Disable Advanced SIMD Extension functionality" "No,Yes"
bitfld.long 0x00 22.--23. "CP11,Coprocessor access control" "Denied,Privileged,Reserved,Full"
newline
bitfld.long 0x00 20.--21. "CP10,Coprocessor access control" "Denied,Privileged,Reserved,Full"
group.long c15:0x0011++0x00
line.long 0x00 "SCR,Secure Configuration Register"
bitfld.long 0x00 13. "TWE,Traps WFE instructions to Monitor mode" "No trap,Trap"
bitfld.long 0x00 12. "TWI,Traps WFI instructions to Monitor mode" "No trap,Trap"
newline
bitfld.long 0x00 9. "SIF,Secure Instruction Fetch" "Permitted,Not permitted"
bitfld.long 0x00 8. "HCE,Hypervisor Call instruction enable" "No,Yes"
newline
bitfld.long 0x00 7. "SCD,Secure Monitor Call disable" "No,Yes"
bitfld.long 0x00 6. "NET,Disables early termination" "Enabled,Disabled"
newline
bitfld.long 0x00 5. "AW,Controls whether the Non-secure world can modify the A-bit in the CPSR" "Not allowed,Allowed"
bitfld.long 0x00 4. "FW,Controls whether the Non-secure world can modify the F-bit in the CPSR" "Not allowed,Allowed"
newline
bitfld.long 0x00 3. "EA,External Abort exceptions handled in Abort mode or Monitor mode" "Abort,Monitor"
bitfld.long 0x00 2. "FIQ,FIQ exceptions handled in Abort mode or Monitor mode" "FIQ,Monitor"
newline
bitfld.long 0x00 1. "IRQ,IRQ exceptions handled in Abort mode or Monitor mode" "IRQ,Monitor"
bitfld.long 0x00 0. "NS,Secure mode " "Secure,Non-secure"
group.long c15:0x0111++0x00
line.long 0x00 "SDER,Secure Debug Enable Register"
bitfld.long 0x00 1. "SUNIDEN,Secure User Non-Invasive Debug Enable" "Disabled,Enabled"
bitfld.long 0x00 0. "SUIDEN,Secure User Invasive Debug Enable" "Disabled,Enabled"
group.long c15:0x0131++0x00
line.long 0x00 "SDCR,Secure Debug Control Register"
bitfld.long 0x00 21. "EPMAD,External debugger access to Performance Monitors Registers disabled" "No,Yes"
bitfld.long 0x00 20. "EDAD,External debugger access to breakpoint and watchpoint Registers disabled" "No,Yes"
newline
bitfld.long 0x00 17. "SPME,Secure performance monitors enable" "Disabled,Enabled"
bitfld.long 0x00 14.--15. "SPD,AArch32 secure privileged debug" "Legacy,Reserved,Disabled,Enabled"
group.long c15:0x0211++0x00
line.long 0x00 "NSACR,Non-Secure Access Control Register"
bitfld.long 0x00 15. "NSASEDIS,Disable Non-secure Advanced SIMD Extension functionality" "No,Yes"
bitfld.long 0x00 11. "CP11,Coprocessor 11 in the Non-secure World Access Permission" "Denied,Permitted"
newline
bitfld.long 0x00 10. "CP10,Coprocessor 10 in the Non-secure World Access Permission" "Denied,Permitted"
group.long c15:0x000C++0x00
line.long 0x00 "VBAR,Vector Base Address Register"
hexmask.long 0x00 5.--31. 0x20 "VBA,Vector Base Address"
group.long c15:0x010C++0x00
line.long 0x00 "MVBAR,Monitor Vector Base Address Register"
hexmask.long 0x00 5.--31. 0x20 "MVBADDR,Monitor Vector Base Address"
rgroup.long c15:0x001C++0x00
line.long 0x00 "ISR,Interrupt Status Register"
bitfld.long 0x00 8. "A,Asynchronous external abort pending bit" "Not pending,Pending"
bitfld.long 0x00 7. "I,IRQ pending bit" "Not pending,Pending"
newline
bitfld.long 0x00 6. "F,FIQ pending bit" "Not pending,Pending"
group.long c15:0x020C++0x00
line.long 0x00 "RMR,Reset Management Register"
bitfld.long 0x00 1. "RR,Reset Request" "Not requested,Requested"
bitfld.long 0x00 0. "AA64,Determines which execution state the processor boots into after a warm reset" "AArch32,AArch64"
if corename()=="CORTEXA75"
rgroup.long c15:0x010C++0x00
line.long 0x00 "RVBAR,Reset Vector Base Address Register"
hexmask.long 0x00 2.--31. 0x4 "RA,Reset Address"
endif
rgroup.long c15:0x0015++0x00
line.long 0x00 "ADFSR,Auxiliary Data Fault Status Register"
rgroup.long c15:0x0115++0x00
line.long 0x00 "AIFSR,Auxiliary Instruction Fault Status Register"
if corename()=="CORTEXA75"
if (((per.l(c15:0x0202))&0x80000000)==0x00000000)
group.long c15:0x0005++0x00
line.long 0x00 "DFSR,Data Fault Status Register"
bitfld.long 0x00 16. "FNV,FAR not Valid" "Valid,Not valid"
bitfld.long 0x00 14.--15. "AET,Asynchronous Error Type" "Uncorrected/Unrecoverable,?..."
newline
bitfld.long 0x00 13. "CM,Cache maintenance fault" "No fault,Fault"
bitfld.long 0x00 11. "WNR,Access Caused an Abort Type" "Read,Write"
newline
bitfld.long 0x00 9. "LPAE,Descriptor translation table format" "Short,Long"
bitfld.long 0x00 4.--7. "DOMAIN,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15"
newline
bitfld.long 0x00 0.--3. 10. "FS,Generated Exception Type" "Reserved,Alignment,Debug,Access flag/L1,Instruction,Translation/L1,Access flag/L2,Translation/L1,Sync. external,Domain/L1,Reserved,Domain/L2,Sync. external/on TTW/L1,Permission/L1,Sync. external/on TTW/L2,Permission/L2,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupp exclusive access,SError,Reserved,SError/ECC on memory access,Sync. parity/ECC on memory access,Reserved,Reserved,Sync. parity/ECC on TTW/L1,Reserved,Sync. parity/ECC on TTW/L2,?..."
group.long c15:0x0105++0x00
line.long 0x00 "IFSR,Instruction Fault Status Register"
bitfld.long 0x00 16. "FNV,FAR not Valid" "Valid,Not valid"
bitfld.long 0x00 12. "EXT,External Abort Qualifier" "0,1"
newline
bitfld.long 0x00 9. "LPAE,Descriptor translation table format" "Short,Long"
bitfld.long 0x00 0.--3. 10. "FS,Fault status bits" "Reserved,Alignment,Debug,Access flag/L1,Reserved,Translation/L1,Access flag/L2,Translation/L2,Sync. external,Domain/L1,Reserved,Domain/L2,Sync. external/on TTW/L1,Permission/L1,Sync. external/on TTW/L2,Permission/L2,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Reserved,Reserved,Reserved,Reserved,Sync. parity/ECC on memory access,Reserved,Reserved,Sync. parity/ECC on TTW/L1,Reserved,Sync. parity/ECC on TTW/L2,?..."
else
group.long c15:0x0005++0x00
line.long 0x00 "DFSR,Data Fault Status Register"
bitfld.long 0x00 16. "FNV,FAR not Valid" "Valid,Not valid"
bitfld.long 0x00 14.--15. "AET,Asynchronous Error Type" "Uncorrected/Unrecoverable,?..."
newline
bitfld.long 0x00 13. "CM,Cache maintenance fault" "No fault,Fault"
bitfld.long 0x00 11. "WNR,Access Caused an Abort Type" "Read,Write"
newline
bitfld.long 0x00 9. "LPAE,Descriptor translation table format" "Short,Long"
bitfld.long 0x00 0.--5. "STATUS,Fault status bits" "Address size/TTBR0/TTBR1,Address size/L1,Address size/L2,Address size/L3,Reserved,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external,Async. SError,Reserved,Reserved,Reserved,Sync. external/on TTW/L1,Sync. external/on TTW/L2,Sync. external/on TTW/L3,Sync. parity/ECC on memory access,Reserved,Reserved,Reserved,Reserved,Sync. parity/ECC on TTW/L1,Sync. parity error/ECC on TTW/L2,Sync. parity error/ECC on TTW/L3,Reserved,Alignment,Debug,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupp exclusive access,?..."
group.long c15:0x0105++0x00
line.long 0x00 "IFSR,Instruction Fault Status Register"
bitfld.long 0x00 16. "FNV,FAR not Valid" "Valid,Not valid"
bitfld.long 0x00 12. "EXT,External Abort Qualifier" "0,1"
newline
bitfld.long 0x00 9. "LPAE,Descriptor translation table format" "Short,Long"
bitfld.long 0x00 0.--5. "STATUS,Fault status bits" "Address size/TTBR0/TTBR1,Address size/L1,Address size/L2,Address size/L3,Reserved,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external,Reserved,Reserved,Reserved,Reserved,Sync. external/on TTW/L1,Sync. external/on TTW/L2,Sync. external/on TTW/L3,Sync. parity/ECC on memory access,Reserved,Reserved,Reserved,Reserved,Sync. parity/ECC on TTW/L1,Sync. parity/ECC on TTW/L2,Sync. parity/ECC on TTW/L3,Reserved,Alignment,Debug,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..."
endif
elif corename()=="CORTEXA55"
if (((per.l(c15:0x0202))&0x80000000)==0x00000000)
group.long c15:0x0005++0x00
line.long 0x00 "DFSR,Data Fault Status Register"
bitfld.long 0x00 16. "FNV,FAR not Valid" "Valid,Not valid"
bitfld.long 0x00 14.--15. "AET,Asynchronous Error Type" ",Uncorrected/Unrecoverable,?..."
newline
bitfld.long 0x00 13. "CM,Cache maintenance fault" "No fault,Fault"
bitfld.long 0x00 11. "WNR,Access Caused an Abort Type" "Read,Write"
newline
bitfld.long 0x00 9. "LPAE,Descriptor translation table format" "Short,Long"
bitfld.long 0x00 4.--7. "DOMAIN,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15"
newline
bitfld.long 0x00 0.--3. 10. "FS,Fault status bits" "Reserved,Alignment,Debug,Access flag/L1,Reserved,Translation/L1,Access flag/L2,Translation/L2,Sync. external,Domain/L1,Reserved,Domain/L2,Sync. external/on TTW/L1,Permission/L1,Sync. external/on TTW/L2,Permission/L2,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Reserved,Reserved,Reserved,Reserved,Sync. parity/ECC on memory access,Reserved,Reserved,Sync. parity/ECC on TTW/L1,Reserved,Sync. parity/ECC on TTW/L2,?..."
group.long c15:0x0105++0x00
line.long 0x00 "IFSR,Instruction Fault Status Register"
bitfld.long 0x00 16. "FNV,FAR not Valid" "Valid,Not valid"
bitfld.long 0x00 12. "EXT,External Abort Qualifier" "0,1"
newline
bitfld.long 0x00 9. "LPAE,Descriptor translation table format" "Short,Long"
bitfld.long 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Reserved,Debug event,Access flag/section,Reserved,Translation/section,Access flag/page,Translation/page,Sync. external/non-translation,Domain/section,Reserved,Domain/page,Sync. external/on TTW/L1,Permission/section,Sync. external/on TTW/L2,Permission/page,TLB conflict,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/L1,Reserved,Sync. parity/on TTW/L2,?..."
else
group.long c15:0x0005++0x00
line.long 0x00 "DFSR,Data Fault Status Register"
bitfld.long 0x00 16. "FNV,FAR not Valid" "Valid,Not valid"
bitfld.long 0x00 14.--15. "AET,Asynchronous Error Type" ",Uncorrected/Unrecoverable,?..."
newline
bitfld.long 0x00 13. "CM,Cache maintenance fault" "No fault,Fault"
bitfld.long 0x00 11. "WNR,Access Caused an Abort Type" "Read,Write"
newline
bitfld.long 0x00 9. "LPAE,Descriptor translation table format" "Short,Long"
bitfld.long 0x00 0.--5. "STATUS,Fault status bits" "Address size/TTBR0/TTBR1,Address size/L1,Address size/L2,Address size/L3,Reserved,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external,Async. SError,Reserved,Reserved,Reserved,Sync. external/on TTW/L1,Sync. external/on TTW/L2,Sync. external/on TTW/L3,Sync. parity/ECC on memory access,Reserved,Reserved,Reserved,Reserved,Sync. parity/ECC on TTW/L1,Sync. parity error/ECC on TTW/L2,Sync. parity error/ECC on TTW/L3,Reserved,Alignment,Debug,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupp exclusive access,?..."
group.long c15:0x0105++0x00
line.long 0x00 "IFSR,Instruction Fault Status Register"
bitfld.long 0x00 16. "FNV,FAR not Valid" "Valid,Not valid"
bitfld.long 0x00 12. "EXT,External Abort Qualifier" "0,1"
newline
bitfld.long 0x00 9. "LPAE,Descriptor translation table format" "Short,Long"
bitfld.long 0x00 0.--5. "STATUS,Fault status bits" "Address size/TTBR0/TTBR1,Address size/L1,Address size/L2,Address size/L3,Reserved,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external,Reserved,Reserved,Reserved,Reserved,Sync. external/on TTW/L1,Sync. external/on TTW/L2,Sync. external/on TTW/L3,Sync. parity/ECC on memory access,Reserved,Reserved,Reserved,Reserved,Sync. parity/ECC on TTW/L1,Sync. parity/ECC on TTW/L2,Sync. parity/ECC on TTW/L3,Reserved,Alignment,Debug,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..."
endif
endif
group.long c15:0x0006++0x00
line.long 0x00 "DFAR,Data Fault Address Register"
group.long c15:0x0206++0x00
line.long 0x00 "IFAR,Instruction Fault Address Register"
rgroup.long c15:0x000D++0x00
line.long 0x00 "FCSEIDR,FCSE PID Register"
group.long c15:0x020D++0x00
line.long 0x00 "TPIDRURW,PL0 Read/Write Software Thread ID Register"
group.long c15:0x030D++0x00
line.long 0x00 "TPIDRURO,PL0 Read-Only Software Thread ID Register"
group.long c15:0x040D++0x00
line.long 0x00 "TPIDRPRW,PL1 Software Thread ID Register"
if corename()=="CORTEXA75"
if (((per.l(c15:0x0202))&0x80000000)==0x00000000)
group.long c15:0x011C++0x00
line.long 0x00 "DISR,Deferred Interrupt Status Register"
bitfld.long 0x00 31. "A,Asynchronous SError interrupt deferred" "No,Yes"
bitfld.long 0x00 14.--15. "AET,Asynchronous Error Type" "UC/Uncontainable,?..."
newline
bitfld.long 0x00 9. "LPAE,Format" "Short-descriptor,Long-descriptor"
bitfld.long 0x00 0.--3. 10. "FS,Fault Status Code" "Reserved,Alignment,Debug,Access/L1,Instruction,Translation/L1,Access/L2,Translation/L2,Non-translation/sync. external,Domain/L1,Reserved,Domain/L2,L1/external,Permission/L1,L2/external,Permission/L2,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupp exclusive access,SError interrupt,Reserved,SError interrupt parity/ECC on memory access,Sync. parity/ECC on memory access,Reserved,Reserved,Sync. parity/ECC on TTW/L1,Reserved,Sync. parity/ECC on TTW/L2,?..."
else
group.long c15:0x011C++0x00
line.long 0x00 "DISR,Deferred Interrupt Status Register"
bitfld.long 0x00 31. "A,Asynchronous SError interrupt deferred" "No,Yes"
bitfld.long 0x00 14.--15. "AET,Asynchronous Error Type" "UC/Uncontainable,?..."
newline
bitfld.long 0x00 9. "LPAE,Format" "Short-descriptor,Long-descriptor"
bitfld.long 0x00 0.--5. "STATUS,Fault Status Code" "Address size/TTBR0/TTBR1,Address size/L1,Address size/L2,Address size/L3,Reserved,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external,SError interrupt,Reserved,Reserved,Reserved,Sync. external/on TTW/L1,Sync. external/on TTW/L2,Sync. external/on TTW/L3,Sync. parity/on memory access,SError interrupt/a parity or ECC/on memory access,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/L1,Sync. parity/on memory access/on TTW/L2,Sync. parity/on memory access/on TTW/L3,Reserved,Alignment,Debug event,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Lockdown,Unsupp exclusive access,?..."
endif
elif corename()=="CORTEXA55"
if (((per.l(c15:0x0202))&0x80000000)==0x00000000)
group.long c15:0x011C++0x00
line.long 0x00 "DISR,Deferred Interrupt Status Register"
bitfld.long 0x00 31. "A,Asynchronous SError interrupt deferred" "No,Yes"
bitfld.long 0x00 14.--15. "AET,Asynchronous Error Type" "Reserved,UEU/Unrecoverable,?..."
newline
bitfld.long 0x00 9. "LPAE,Format" "Short-descriptor,Long-descriptor"
bitfld.long 0x00 0.--3. 10. "FS,Fault Status Code" "Reserved,Alignment,Debug,Access/L1,Instruction,Translation/L1,Access/L2,Translation/L2,Non-translation/sync. external,Domain/L1,Reserved,Domain/L2,L1/external,Permission/L1,L2/external,Permission/L2,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupp exclusive access,SError interrupt,Reserved,SError interrupt parity/ECC on memory access,Sync. parity/ECC on memory access,Reserved,Reserved,Sync. parity/ECC on TTW/L1,Reserved,Sync. parity/ECC on TTW/L2,?..."
else
group.long c15:0x011C++0x00
line.long 0x00 "DISR,Deferred Interrupt Status Register"
bitfld.long 0x00 31. "A,Asynchronous SError interrupt deferred" "No,Yes"
bitfld.long 0x00 14.--15. "AET,Asynchronous Error Type" "Reserved,UEU/Unrecoverable,?..."
newline
bitfld.long 0x00 9. "LPAE,Format" "Short-descriptor,Long-descriptor"
bitfld.long 0x00 0.--5. "STATUS,Fault Status Code" "Address size/TTBR0/TTBR1,Address size/L1,Address size/L2,Address size/L3,Reserved,Translation/L1,Translation fault/L2,Translation fault/L3,Reserved,Access flag fault/L1,Access flag fault/L2,Access flag fault/L3,Reserved,Permission fault/L1,Permission fault/L2,Permission fault/L3,Sync. external,SError interrupt,Reserved,Reserved,Reserved,Sync. external/on TTW/L1,Sync. external/on TTW/L2,Sync. external/on TTW/L3,Sync. parity/on memory access,SError interrupt/parity or ECC/on memory access,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/L1,Sync. parity/on memory access/on TTW/L2,Sync. parity/on memory access/on TTW/L3,Reserved,Alignment,Debug event,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Lockdown,Unsupp exclusive access,?..."
endif
endif
if corename()=="CORTEXA75"
if (((per.l(c15:0x0202))&0x80000000)==0x00000000)
group.long c15:0x411C++0x00
line.long 0x00 "VDISR,Virtual Deferred Interrupt Status Register"
bitfld.long 0x00 31. "A,Asynchronous SError interrupt deferred" "No,Yes"
bitfld.long 0x00 14.--15. "AET,Asynchronous Error Type" "UC/Uncontainable,?..."
newline
bitfld.long 0x00 9. "LPAE,Format" "Short-descriptor,Long-descriptor"
bitfld.long 0x00 0.--3. 10. "FS,Fault Status Code" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Async SError interrupt,?..."
else
group.long c15:0x411C++0x00
line.long 0x00 "VDISR,Virtual Deferred Interrupt Status Register"
bitfld.long 0x00 31. "A,Asynchronous SError interrupt deferred" "No,Yes"
bitfld.long 0x00 14.--15. "AET,Asynchronous Error Type" "UC/Uncontainable,?..."
newline
bitfld.long 0x00 9. "LPAE,Format" "Short-descriptor,Long-descriptor"
bitfld.long 0x00 0.--5. "STATUS,Fault Status Code" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Async SError interrupt,?..."
endif
elif corename()=="CORTEXA55"
if (((per.l(c15:0x0202))&0x80000000)==0x00000000)
group.long c15:0x411C++0x00
line.long 0x00 "VDISR,Virtual Deferred Interrupt Status Register"
bitfld.long 0x00 31. "A,Asynchronous SError interrupt deferred" "No,Yes"
bitfld.long 0x00 14.--15. "AET,Asynchronous Error Type" "Reserved,UEU/Unrecoverable,?..."
newline
bitfld.long 0x00 9. "LPAE,Format" "Short-descriptor,?..."
bitfld.long 0x00 0.--3. 10. "FS,Fault Status Code" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Async SError interrupt,?..."
else
group.long c15:0x411C++0x00
line.long 0x00 "VDISR,Virtual Deferred Interrupt Status Register"
bitfld.long 0x00 31. "A,Asynchronous SError interrupt deferred" "No,Yes"
bitfld.long 0x00 14.--15. "AET,Asynchronous Error Type" "Reserved,UEU/Unrecoverable,?..."
newline
bitfld.long 0x00 9. "LPAE,Format" ",Long-descriptor"
bitfld.long 0x00 0.--5. "STATUS,Fault Status Code" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Async SError interrupt,?..."
endif
endif
group.long c15:0x4325++0x00
line.long 0x00 "VDFSR,Virtual SError Exception Syndrome Register"
bitfld.long 0x00 14.--15. "AET,Asynchronous Error Type" "Reserved,UEU/Unrecoverable,?..."
tree "System Instructions"
wgroup.long c15:0x0068++0x00
line.long 0x00 "DTLBIALL,DTLBIALL"
wgroup.long c15:0x0268++0x00
line.long 0x00 "DTLBIASID,DTLBIASID"
wgroup.long c15:0x0168++0x00
line.long 0x00 "DTLBIMVA,DTLBIMVA"
wgroup.long c15:0x0058++0x00
line.long 0x00 "ITLBIALL,ITLBIALL"
wgroup.long c15:0x0258++0x00
line.long 0x00 "ITLBIASID,ITLBIASID"
wgroup.long c15:0x0158++0x00
line.long 0x00 "ITLBIMVA,ITLBIMVA"
wgroup.long c15:0x05A7++0x00
line.long 0x00 "CP15DMB,CP15DMB"
wgroup.long c15:0x04A7++0x00
line.long 0x00 "CP15DSB,CP15DSB"
wgroup.long c15:0x0457++0x00
line.long 0x00 "CP15ISB,CP15ISB"
wgroup.long c15:0x0657++0x00
line.long 0x00 "BPIALL,BPIALL"
wgroup.long c15:0x0617++0x00
line.long 0x00 "BPIALLIS,BPIALLIS"
wgroup.long c15:0x0757++0x00
line.long 0x00 "BPIMVA,BPIMVA"
wgroup.long c15:0x0017++0x00
line.long 0x00 "ICIALLUIS,ICIALLUIS"
wgroup.long c15:0x0057++0x00
line.long 0x00 "ICIALLU,ICIALLU"
wgroup.long c15:0x0157++0x00
line.long 0x00 "ICIMVAU,ICIMVAU"
wgroup.long c15:0x3147++0x00
line.long 0x00 "DCZVA,DCZVA"
wgroup.long c15:0x0167++0x00
line.long 0x00 "DCIMVAC,DCIMVAC"
wgroup.long c15:0x0267++0x00
line.long 0x00 "DCISW,DCISW"
wgroup.long c15:0x01A7++0x00
line.long 0x00 "DCCMVAC,DCCMVAC"
wgroup.long c15:0x02A7++0x00
line.long 0x00 "DCCSW,DCCSW"
wgroup.long c15:0x01B7++0x00
line.long 0x00 "DCCMVAU,DCCMVAU"
wgroup.long c15:0x01E7++0x00
line.long 0x00 "DCCIMVAC,DCCIMVAC"
wgroup.long c15:0x02E7++0x00
line.long 0x00 "DCCISW,DCCISW"
wgroup.long c15:0x0087++0x00
line.long 0x00 "ATS1CPR,ATS1CPR"
wgroup.long c15:0x0097++0x00
line.long 0x00 "ATS1CPRP,ATS1CPRP"
wgroup.long c15:0x0187++0x00
line.long 0x00 "ATS1CPW,ATS1CPW"
wgroup.long c15:0x0197++0x00
line.long 0x00 "ATS1CPWP,ATS1CPWP"
wgroup.long c15:0x0287++0x00
line.long 0x00 "ATS1CUR,ATS1CUR"
wgroup.long c15:0x0387++0x00
line.long 0x00 "ATS1CUW,ATS1CUW"
wgroup.long c15:0x0487++0x00
line.long 0x00 "ATS12NSOPR,ATS12NSOPR"
wgroup.long c15:0x0587++0x00
line.long 0x00 "ATS12NSOPW,ATS12NSOPW"
wgroup.long c15:0x0687++0x00
line.long 0x00 "ATS12NSOUR,ATS12NSOUR"
wgroup.long c15:0x0787++0x00
line.long 0x00 "ATS12NSOUW,ATS12NSOUW"
wgroup.long c15:0x4087++0x00
line.long 0x00 "ATS1HR,ATS1HR"
wgroup.long c15:0x4187++0x00
line.long 0x00 "ATS1HW,ATS1HW"
; Commented Registers are not described in ARMv8 reference manual (DDI0407A)
; wgroup.long c15:0x6087++0x00
; line.long 0x00 "ATS1E3R,ATS1E3R"
; wgroup.long c15:0x6187++0x00
; line.long 0x00 "ATS1E3W,ATS1E3W"
wgroup.long c15:0x0078++0x00
line.long 0x00 "TLBIALL,TLBIALL"
wgroup.long c15:0x0178++0x00
line.long 0x00 "TLBIMVA,TLBIMVA"
wgroup.long c15:0x4178++0x00
line.long 0x00 "TLBIMVAH,Invalidate Hypervisor unified TLB entry by MVA"
wgroup.long c15:0x0278++0x00
line.long 0x00 "TLBIASID,TLBIASID"
wgroup.long c15:0x0378++0x00
line.long 0x00 "TLBIMVAA,TLBIMVAA"
wgroup.long c15:0x0578++0x00
line.long 0x00 "TLBIMVAL,TLBIMVAL"
wgroup.long c15:0x0778++0x00
line.long 0x00 "TLBIMVAAL,TLBIMVAAL"
wgroup.long c15:0x0038++0x00
line.long 0x00 "TLBIALLIS,TLBIALLIS"
wgroup.long c15:0x0138++0x00
line.long 0x00 "TLBIMVAIS,TLBIMVAIS"
wgroup.long c15:0x0238++0x00
line.long 0x00 "TLBIASIDIS,TLBIASIDIS"
wgroup.long c15:0x0338++0x00
line.long 0x00 "TLBIMVAAIS,TLBIMVAAIS"
wgroup.long c15:0x0538++0x00
line.long 0x00 "TLBIMVALIS,TLBIMVALIS"
wgroup.long c15:0x0738++0x00
line.long 0x00 "TLBIMVAALI,TLBIMVAALI"
wgroup.long c15:0x4108++0x00
line.long 0x00 "TLBIIPAS2IS,TLBIIPAS2IS"
wgroup.long c15:0x4508++0x00
line.long 0x00 "TLBIIPAS2LIS,TLBIIPAS2LIS"
wgroup.long c15:0x4148++0x00
line.long 0x00 "TLBIIPAS2,TLBIIPAS2"
wgroup.long c15:0x4548++0x00
line.long 0x00 "TLBIIPAS2L,TLBIIPAS2L"
wgroup.long c15:0x4178++0x00
line.long 0x00 "TLBIIPAS2L,TLBIIPAS2L"
wgroup.long c15:0x4578++0x00
line.long 0x00 "TLBIMVALH,TLBIMVALH"
; wgroup.long c15:0x4678++0x00
; line.long 0x00 "TLBIVMALLS12E1,TLBIVMALLS12E1"
wgroup.long c15:0x4138++0x00
line.long 0x00 "TLBIMVAHIS,TLBIMVAHIS"
wgroup.long c15:0x4538++0x00
line.long 0x00 "TLBIMVALHIS,TLBIMVALHIS"
; wgroup.long c15:0x4638++0x00
; line.long 0x00 "TLBIVMALLS12E1IS,TLBIVMALLS12E1IS"
; wgroup.long c15:0x6178++0x00
; line.long 0x00 "TLBIVAE3,TLBIVAE3"
; wgroup.long c15:0x6578++0x00
; line.long 0x00 "TLBIVALE3,TLBIVALE3"
; wgroup.long c15:0x6138++0x00
; line.long 0x00 "TLBIVAE3IS,TLBIVAE3IS"
; wgroup.long c15:0x6538++0x00
; line.long 0x00 "TLBIVALE3IS,TLBIVALE3IS"
wgroup.long c15:0x4078++0x00
line.long 0x00 "TLBIALLH,TLBIALLH"
wgroup.long c15:0x4038++0x00
line.long 0x00 "TLBIALLHIS,TLBIALLHIS"
wgroup.long c15:0x4478++0x00
line.long 0x00 "TLBIALLNSNH,TLBIALLNSNH"
wgroup.long c15:0x4438++0x00
line.long 0x00 "TLBIALLNSNHIS,TLBIALLNSNHIS"
; wgroup.long c15:0x6078++0x00
; line.long 0x00 "TLBIALLE3,TLBIALLE3"
; wgroup.long c15:0x6038++0x00
; line.long 0x00 "TLBIALLE3IS,TLBIALLE3IS"
tree.end
tree.end
tree "Memory Management Unit"
group.long c15:0x0001++0x0
line.long 0x0 "SCTLR,Control Register"
bitfld.long 0x00 30. "TE,T32 exception enable" "A32,T32"
bitfld.long 0x00 29. "AFE,Access Flag Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 28. "TRE,TEX remap enable" "Disabled,Enabled"
bitfld.long 0x00 25. "EE,Exception endianness" "Little,Big"
newline
bitfld.long 0x00 23. "SPAN,Set Privileged Access Never" "Disabled,Enabled"
bitfld.long 0x00 20. "UWXN,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced"
newline
bitfld.long 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
bitfld.long 0x00 18. "NTWE,Not trap WFE" "No,Yes"
newline
bitfld.long 0x00 16. "NTWI,Not trap WFI" "No,Yes"
bitfld.long 0x00 13. "V,Base Location of Exception Registers" "VBAR value,0xFFFF0000"
newline
bitfld.long 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled"
bitfld.long 0x00 8. "SED,SETEND Disable" "No,Yes"
newline
bitfld.long 0x00 5. "CP15BEN,C15 Barrier Enable" "Disabled,Enabled"
rbitfld.long 0x00 4. "LSMAOE,Load/Store Multiple Atomicity and Ordering Enable" "Reserved,Enabled"
newline
rbitfld.long 0x00 3. "NTLSMD,No Trap Load/Store Multiple to Device-nGRE/Device-nGnRE/Device-nGnRnE memory" "Reserved,No Trap"
bitfld.long 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
newline
bitfld.long 0x00 1. "A,Strict Alignment" "Disabled,Enabled"
bitfld.long 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled"
group.long c15:0x4001++0x0
line.long 0x00 "HSCTLR,Hypervisor System Control Register"
bitfld.long 0x00 30. "TE,Thumb exception enable" "A32,T32"
bitfld.long 0x00 25. "EE,Exception endianness" "Little,Big"
newline
bitfld.long 0x00 19. "WXN,Write permission implies XN" "Not forced,Forced"
bitfld.long 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 8. "SED,SETEND Disable" "No,Yes"
bitfld.long 0x00 7. "ITD,IT instruction functionality Disabled" "No,?..."
newline
bitfld.long 0x00 5. "CP15BEN,C15 Barrier Enable" "Disabled,Enabled"
rbitfld.long 0x00 4. "LSMAOE,Load/Store Multiple Atomicity and Ordering Enable" "Reserved,Enabled"
newline
rbitfld.long 0x00 3. "NTLSMD,No Trap Load/Store Multiple to Device-nGRE/Device-nGnRE/Device-nGnRnE memory" "Trapped,No Trapped"
bitfld.long 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
newline
bitfld.long 0x00 1. "A,Strict Alignment" "Disabled,Enabled"
bitfld.long 0x00 0. "M,Enable address translation" "Disabled,Enabled"
if (((per.l(c15:0x0202))&0x80000000)==0x00000000)
group.long c15:0x0002++0x00
line.long 0x00 "TTBR0,Translation Table Base Registers"
hexmask.long 0x00 7.--31. 0x80 "TTB0,Translation table base address"
bitfld.long 0x00 6. 0. "IRGN,Inner region bits" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.long 0x00 5. "NOS,Not Outer Shareable bit" "Outer,Inner"
bitfld.long 0x00 3.--4. "RGN,RGN" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.long 0x00 1. "S,Shareable bit" "Non-shareable,Shareable"
group.long c15:0x0102++0x00
line.long 0x00 "TTBR1,Translation Table Base Registers"
hexmask.long 0x00 7.--31. 0x80 "TTB1,Translation table base address"
bitfld.long 0x00 6. 0. "IRGN,Inner region bits" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.long 0x00 5. "NOS,Not Outer Shareable bit" "Outer,Inner"
bitfld.long 0x00 3.--4. "RGN,RGN" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.long 0x00 1. "S,Shareable" "Non-shareable,Shareable"
group.long c15:0x0202++0x00
line.long 0x00 "TTBCR,Translation Table Base Control Register"
bitfld.long 0x00 31. "EAE,Extended Address Enable" "32-bit,40-bit"
bitfld.long 0x00 5. "PD1,Translation table walk disable for translations using TTBR1" "No,Yes"
newline
bitfld.long 0x00 4. "PD0,Translation table walk disable for translations using TTBR0" "No,Yes"
bitfld.long 0x00 0.--2. "N,Width of the base address held in TTBR0" "0,1,2,3,4,5,6,7"
else
group.quad c15:0x10020++0x01
line.quad 0x00 "TTBR0,Translation Table Base Registers"
hexmask.quad.byte 0x00 48.--55. 1. "ASID,ASID for the translation table base address"
hexmask.quad 0x00 1.--47. 1. "BADDR,Translation table base address"
newline
bitfld.quad 0x00 0. "CNP,Common not Private" "Not supported,Supported"
group.quad c15:0x11020++0x01
line.quad 0x00 "TTBR1,Translation Table Base Registers"
hexmask.quad.byte 0x00 48.--55. 1. "ASID,ASID for the translation table base address"
hexmask.quad 0x00 1.--47. 1. "BADDR,Translation table base address"
newline
bitfld.quad 0x00 0. "CNP,Common not Private" "Not supported,Supported"
group.long c15:0x0202++0x00
line.long 0x00 "TTBCR,Translation Table Base Control Register"
bitfld.long 0x00 31. "EAE,Extended Address Enable" "32-bit,40-bit"
bitfld.long 0x00 28.--29. "SH1,Shareability attributes for the memory associated with the translation table walks using TTBR1" "Non-Shareable,Reserved,Outer Shareable,Inner Shareable"
newline
bitfld.long 0x00 26.--27. "ORGN1,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
bitfld.long 0x00 24.--25. "IRGN1,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.long 0x00 23. "EPD1,Translation Walk Disable for TTBR1" "No,Yes"
bitfld.long 0x00 22. "A1,Selects whether TTBR0 or TTBR1 defines the ASID" "TTBR0,TTBR1"
newline
bitfld.long 0x00 16.--18. "T1SZ,The Size offset of the TTBR1 addressed region" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-Shareable,Reserved,Outer Shareable,Inner Shareable"
newline
bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.long 0x00 7. "EPD0,Translation Walk Disable for TTBR0 region" "No,Yes"
bitfld.long 0x00 6. "T2E,TTBCR2 Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 0.--2. "T0SZ,The Size offset of the TTBR0/HTTBR addressed region" "0,1,2,3,4,5,6,7"
endif
if corename()=="CORTEXA55"
group.long c15:0x0302++0x00
line.long 0x00 "TTBCR2,Translation Table Base Control Register 2"
bitfld.long 0x00 18. "HWU162,Hardware usage of bit[62] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR1" "Not possible,Possible"
bitfld.long 0x00 17. "HWU161,Hardware usage of bit[61] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR1" "Not possible,Possible"
newline
bitfld.long 0x00 16. "HWU160,Hardware usage of bit[60] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR1" "Not possible,Possible"
bitfld.long 0x00 15. "HWU159,Hardware usage of bit[59] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR1" "Not possible,Possible"
newline
bitfld.long 0x00 14. "HWU062,Hardware usage of bit[62] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR0" "Not possible,Possible"
bitfld.long 0x00 13. "HWU061,Hardware usage of bit[61] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR0" "Not possible,Possible"
newline
bitfld.long 0x00 12. "HWU060,Hardware usage of bit[60] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR0" "Not possible,Possible"
bitfld.long 0x00 11. "HWU059,Hardware usage of bit[59] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR0" "Not possible,Possible"
newline
bitfld.long 0x00 10. "HPD1,Hierarchical Permission Disable for the TTBR1 region" "No,Yes"
bitfld.long 0x00 9. "HPD0,Hierarchical Permission Disable for the TTBR0 region" "No,Yes"
group.long c15:0x007F++0x00
line.long 0x00 "ATTBCR,Auxiliary Translation Table Base Control Register"
bitfld.long 0x00 13. "HWVAL160,Indicates the value of PBHA[1] on page table walks memory access targeting the base address defined by TTB1 if HWEN160 is set" "0,1"
bitfld.long 0x00 12. "HWVAL159,Indicates the value of PBHA[0] on page table walks memory access targeting the base address defined by TTB1 if HWEN159 is set" "0,1"
newline
bitfld.long 0x00 9. "HWVAL060,Indicates the value of PBHA[1] on page table walks memory access targeting the base address defined by TTB0 if HWEN060 is set" "0,1"
bitfld.long 0x00 8. "HWVAL059,Indicates the value of PBHA[1] on page table walks memory access targeting the base address defined by TTB0 if HWEN059 is set" "0,1"
newline
bitfld.long 0x00 5. "HWEN160,Enables PBHA[1] page table walks memory access targeting the base address defined by TTB1" "Disabled,Enabled"
bitfld.long 0x00 4. "HWEN159,Enables PBHA[0] page table walks memory access targeting the base address defined by TTB1" "Disabled,Enabled"
newline
bitfld.long 0x00 1. "HWEN060,Enables PBHA[1] page table walks memory access targeting the base address defined by TTB0" "Disabled,Enabled"
bitfld.long 0x00 0. "HWEN059,Enables PBHA[0] page table walks memory access targeting the base address defined by TTB0" "Disabled,Enabled"
endif
group.quad c15:0x14020++0x01
line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register"
hexmask.quad 0x00 1.--47. 0x02 "BADDR,Translation table base address"
bitfld.quad 0x00 0. "CNP,Common not Private" "Not supported,Supported"
group.long c15:0x4202++0x00
line.long 0x00 "HTCR,Hypervisor Translation Control Register"
bitfld.long 0x00 28. "HWU062,Hardware usage of bit[62] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR0" "Not possible,Possible"
bitfld.long 0x00 27. "HWU061,Hardware usage of bit[61] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR0" "Not possible,Possible"
newline
bitfld.long 0x00 26. "HWU060,Hardware usage of bit[60] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR0" "Not possible,Possible"
bitfld.long 0x00 25. "HWU059,Hardware usage of bit[59] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR0" "Not possible,Possible"
newline
bitfld.long 0x00 24. "HPD,Hierarchical Permission Disables" "No,Yes"
bitfld.long 0x00 12.--13. "SH0,Shareability attribute" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
newline
bitfld.long 0x00 10.--11. "ORGN0,Outer cacheability attribute, Normal memory" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
bitfld.long 0x00 8.--9. "IRGN0,Inner cacheability attribute, Normal memory" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.long 0x00 0.--2. "T0SZ,The size offset of the memory region addressed by HTTBR" "0,1,2,3,4,5,6,7"
group.long c15:0x0003++0x00
line.long 0x00 "DACR,Domain Access Control Register"
bitfld.long 0x0 30.--31. "D15,Domain Access 15" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 28.--29. "D14,Domain Access 14" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x0 26.--27. "D13,Domain Access 13" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 24.--25. "D12,Domain Access 12" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x0 22.--23. "D11,Domain Access 11" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 20.--21. "D10,Domain Access 10" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x0 18.--19. "D9,Domain Access 9" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 16.--17. "D8,Domain Access 8" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x0 14.--15. "D7,Domain Access 7" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 12.--13. "D6,Domain Access 6" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x0 10.--11. "D5,Domain Access 5" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 8.--9. "D4,Domain Access 4" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x0 6.--7. "D3,Domain Access 3" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 4.--5. "D2,Domain Access 2" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x0 2.--3. "D1,Domain Access 1" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 0.--1. "D0,Domain Access 0" "Denied,Client,Reserved,Manager"
if corename()=="CORTEXA75"
if ((((per.l(c15:0x0202))&0x80000000)==0x00000000)&&(((per.l(c15:0x0047))&0x1)==0x0))
group.long c15:0x0047++0x00
line.long 0x00 "PAR,Physical Address Register"
hexmask.long.tbyte 0x00 12.--31. 0x10 "PA,Physical Address"
bitfld.long 0x00 11. "LPAE,Descriptor translation table format" "Short,Long"
newline
bitfld.long 0x00 10. "NOS,Not Outer Shareable attribute for the region" "Outer,?..."
bitfld.long 0x00 9. "NS,Non-secure" "No,Yes"
newline
bitfld.long 0x00 7. "SH,Shareability attribute for the region" "No,Yes"
newline
bitfld.long 0x00 4.--6. "INNER,Inner memory attributes for the region" "Non-cacheable,Device-nGnRnE,Reserved,Device-nGnRE,Reserved,Write-Back/Write-Allocate,Write-Through,Write-Back/No Write-Allocate"
newline
bitfld.long 0x00 2.--3. "OUTER,Outer memory attributes for the region" "Non-cacheable,Write-Back/Write-Allocate,Write-Through/No Write-Allocate,Write-Back/No Write-Allocate"
newline
bitfld.long 0x00 1. "SS,Used to indicate if the result is a Supersection" "No,Yes"
newline
bitfld.long 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted"
elif ((((per.l(c15:0x0202))&0x80000000)==0x00000000)&&(((per.l(c15:0x0047))&0x1)==0x1))
group.long c15:0x0047++0x00
line.long 0x00 "PAR,Physical Address Register"
bitfld.long 0x00 11. "LPAE,Descriptor translation table format" "Short,?..."
newline
newline
newline
bitfld.long 0x00 6. "FS[5],Fault status bit [5] - External abort type" "Internal,External"
newline
newline
bitfld.long 0x00 1.--5. "FS[4:0],Fault status bit [4:0] - Abort source" "Reserved,Alignment,Debug,Access flag/L1,Instruction,Translation/L1,Access flag/L2,Translation/L2,Sync. external,Domain/L1,Reserved,Domain/L2,Sync. external/on TTW/L1,Permission/L1,Sync. external/on TTW/L2,Permission/L2,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupp. exclusive access,SError,Reserved,Reserved,Sync. parity/ECC on memory access,Reserved,Reserved,Sync. parity/ECC on TTW/L1,Reserved,Sync. parity/ECC on TTW/L2,?..."
newline
bitfld.long 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted"
elif ((((per.l(c15:0x0202))&0x80000000)==0x80000000)&&(((per.l(c15:0x10070))&0x1)==0x0))
group.quad c15:0x10070++0x01
line.quad 0x00 "PAR,Physical Address Register"
hexmask.quad.byte 0x00 56.--63. 1. "ATTR,Memory attributes for the returned PA"
hexmask.quad.long 0x00 12.--39. 0x10 "PA,Physical Address"
newline
bitfld.quad 0x00 11. "LPAE,Descriptor translation table format" ",Long"
newline
bitfld.quad 0x00 9. "NS,Non-secure" "No,Yes"
bitfld.quad 0x00 7.--8. "SH,Shareability attribute" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
newline
newline
newline
newline
bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted"
else
group.quad c15:0x10070++0x01
line.quad 0x00 "PAR,Physical Address Register"
newline
bitfld.quad 0x00 11. "LPAE,Descriptor translation table format" ",Long"
newline
bitfld.quad 0x00 9. "FSTAGE,Indicates the translation stage at which the translation aborted" "Stage 1,Stage 2"
bitfld.quad 0x00 8. "S2WLK,Translation aborted because of a stage 2 fault during a stage 1 translation table walk" "No,Yes"
newline
newline
newline
bitfld.quad 0x00 1.--6. "FST,Fault Status Field" "Address size/TTBR,Address size/L1,Address size/L2,Address size/L3,Reserved,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external,Reserved,Reserved,Reserved,Reserved,Sync. external/on TTW/L1,Sync. external/on TTW/L2,Sync. external/on TTW/L3,Sync. parity/ECC on memory access,Sync. parity/ECC on memory access,Reserved,Reserved,Reserved,Sync. parity/ECC on TTW/L1,Sync. parity/ECC on TTW/L2,Sync. parity/ECC/on TTW/L3,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..."
newline
bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted"
endif
elif corename()=="CORTEXA55"
if ((((per.l(c15:0x0202))&0x80000000)==0x00000000)&&(((per.l(c15:0x0047))&0x1)==0x0))
group.long c15:0x0047++0x00
line.long 0x00 "PAR,Physical Address Register"
hexmask.long.tbyte 0x00 12.--31. 0x10 "PA,Physical Address"
newline
bitfld.long 0x00 11. "LPAE,Descriptor translation table format" "Short,?..."
bitfld.long 0x00 10. "NOS,Not Outer Shareable attribute for the region" "Outer,Inner"
newline
bitfld.long 0x00 9. "NS,Non-secure" "No,Yes"
bitfld.long 0x00 7. "SH,Shareability attribute for the region" "No,Yes"
newline
bitfld.long 0x00 4.--6. "INNER,Inner memory attributes for the region" "Non-cacheable,Device-nGnRnE,Reserved,Device-nGnRE,Reserved,Write-Back/Write-Allocate,Write-Through,Write-Back/No Write-Allocate"
newline
bitfld.long 0x00 2.--3. "OUTER,Outer memory attributes for the region" "Non-cacheable,Write-Back/Write-Allocate,Write-Through/No Write-Allocate,Write-Back/No Write-Allocate"
newline
bitfld.long 0x00 1. "SS,Used to indicate if the result is a Supersection" "No,Yes"
newline
bitfld.long 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,?..."
elif ((((per.l(c15:0x0202))&0x80000000)==0x00000000)&&(((per.l(c15:0x0047))&0x1)==0x1))
group.long c15:0x0047++0x00
line.long 0x00 "PAR,Physical Address Register"
newline
bitfld.long 0x00 11. "LPAE,Descriptor translation table format" "Short,?..."
newline
bitfld.long 0x00 6. "FS[5],Fault status bit [5] - External abort type" "Internal,External"
newline
newline
newline
bitfld.long 0x00 1.--5. "FS[4:0],Fault status bit [4:0] - Abort source" "Reserved,Alignment,Debug,Access flag/L1,Instruction,Translation/L1,Access flag/L2,Translation/L2,Sync. external,Domain/L1,Reserved,Domain/L2,Sync. external/on TTW/L1,Permission/L1,Sync. external/on TTW/L2,Permission/L2,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupp. exclusive access,SError,Reserved,Reserved,Sync. parity/ECC on memory access,Reserved,Reserved,Sync. parity/ECC on TTW/L1,Reserved,Sync. parity/ECC on TTW/L2,?..."
newline
bitfld.long 0x00 0. "F,Indicates whether the conversion completed successfully" ",Aborted"
elif ((((per.l(c15:0x0202))&0x80000000)==0x80000000)&&(((per.l(c15:0x10070))&0x1)==0x0))
group.quad c15:0x10070++0x01
line.quad 0x00 "PAR,Physical Address Register"
hexmask.quad.byte 0x00 56.--63. 1. "ATTR,Memory attributes for the returned PA"
hexmask.quad.long 0x00 12.--39. 0x10 "PA,Physical Address"
newline
bitfld.quad 0x00 11. "LPAE,Descriptor translation table format" ",Long"
newline
bitfld.quad 0x00 9. "NS,Non-secure" "No,Yes"
bitfld.quad 0x00 7.--8. "SH,Shareability attribute" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
newline
newline
newline
newline
bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,?..."
else
group.quad c15:0x10070++0x01
line.quad 0x00 "PAR,Physical Address Register"
newline
bitfld.quad 0x00 11. "LPAE,Descriptor translation table format" ",Long"
newline
bitfld.quad 0x00 9. "FSTAGE,Indicates the translation stage at which the translation aborted" "Stage 1,Stage 2"
bitfld.quad 0x00 8. "S2WLK,Translation aborted because of a stage 2 fault during a stage 1 translation table walk" "No,Yes"
newline
newline
newline
bitfld.quad 0x00 1.--6. "FST,Fault Status Field" "Address size/TTBR,Address size/L1,Address size/L2,Address size/L3,Reserved,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external,Reserved,Reserved,Reserved,Reserved,Sync. external/on TTW/L1,Sync. external/on TTW/L2,Sync. external/on TTW/L3,Sync. parity/ECC on memory access,Sync. parity/ECC on memory access,Reserved,Reserved,Reserved,Sync. parity/ECC on TTW/L1,Sync. parity/ECC on TTW/L2,Sync. parity/ECC/on TTW/L3,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..."
newline
bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" ",Aborted"
endif
endif
tree.open "Memory Attribute Indirection Registers"
rgroup.long c15:0x003A++0x00
line.long 0x00 "AMAIR0,Auxiliary Memory Attribute Indirection Register 0"
rgroup.long c15:0x013A++0x00
line.long 0x00 "AMAIR1,Auxiliary Memory Attribute Indirection Register 1"
if corename()=="CORTEXA75"
if (((per.l(c15:0x0202))&0x80000000)==0x80000000)
group.long c15:0x402A++0x00
line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0"
bitfld.long 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3L,Attribute 3 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2L,Attribute 2 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1L,Attribute 1 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0L,Attribute 0 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
group.long c15:0x412A++0x00
line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1"
bitfld.long 0x00 28.--31. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR7L,Attribute 7 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 20.--23. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR6L,Attribute 6 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 12.--15. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR5L,Attribute 5 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 4.--7. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR4L,Attribute 4 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
else
rgroup.long c15:0x402A++0x00
line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0"
rgroup.long c15:0x412A++0x00
line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1"
endif
elif corename()=="CORTEXA55"
if (((per.l(c15:0x0202))&0x80000000)==0x80000000)
group.long c15:0x402A++0x00
line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0"
bitfld.long 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3L,Attribute 3 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2L,Attribute 2 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1L,Attribute 1 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0L,Attribute 0 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
group.long c15:0x412A++0x00
line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1"
bitfld.long 0x00 28.--31. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR7L,Attribute 7 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 20.--23. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR6L,Attribute 6 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 12.--15. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR5L,Attribute 5 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 4.--7. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR4L,Attribute 4 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
else
rgroup.long c15:0x402A++0x00
line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0"
rgroup.long c15:0x412A++0x00
line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1"
endif
endif
rgroup.long c15:0x403A++0x00
line.long 0x00 "HAMAIR0,Hypervisor Auxiliary Memory Attribute Indirection Register 0"
rgroup.long c15:0x413A++0x00
line.long 0x00 "HAMAIR1,Hypervisor Auxiliary Memory Attribute Indirection Register 1"
if corename()=="CORTEXA75"
if (((per.l(c15:0x0202))&0x80000000)==0x80000000)
group.long c15:0x002A++0x00
line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0"
bitfld.long 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3L,Attribute 3 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2L,Attribute 2 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1L,Attribute 1 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0L,Attribute 0 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
group.long c15:0x012A++0x00
line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1"
bitfld.long 0x00 28.--31. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR7L,Attribute 7 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 20.--23. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR6L,Attribute 6 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 12.--15. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR5L,Attribute 5 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 4.--7. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR4L,Attribute 4 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
group.long c15:0x010D++0x00
line.long 0x00 "CONTEXTIDR,Context ID Register"
else
group.long c15:0x002A++0x0
line.long 0x00 "PRRR,Primary Region Remap Register"
bitfld.long 0x00 31. "NOS7,Outer Shareable property mapping for memory attributes" "Outer,Inner"
bitfld.long 0x00 30. "NOS6,Outer Shareable property mapping for memory attributes" "Outer,Inner"
newline
bitfld.long 0x00 29. "NOS5,Outer Shareable property mapping for memory attributes" "Outer,Inner"
bitfld.long 0x00 28. "NOS4,Outer Shareable property mapping for memory attributes" "Outer,Inner"
newline
bitfld.long 0x00 27. "NOS3,Outer Shareable property mapping for memory attributes" "Outer,Inner"
bitfld.long 0x00 26. "NOS2,Outer Shareable property mapping for memory attributes" "Outer,Inner"
newline
bitfld.long 0x00 25. "NOS1,Outer Shareable property mapping for memory attributes" "Outer,Inner"
bitfld.long 0x00 24. "NOS0,Outer Shareable property mapping for memory attributes" "Outer,Inner"
newline
bitfld.long 0x00 19. "NS1,Mapping of S = 1 attribute for Normal memory" "Not shareable,Shareable"
bitfld.long 0x00 18. "NS0,Mapping of S = 0 attribute for Normal memory" "Not shareable,Shareable"
newline
bitfld.long 0x00 17. "DS1,Mapping of S = 1 attribute for Device memory" "Not shareable,Shareable"
bitfld.long 0x00 16. "DS0,Mapping of S = 0 attribute for Device memory" "Not shareable,Shareable"
newline
bitfld.long 0x00 14.--15. "TR7,{TEX[0] C B} = b111 Remap" "Device (nGnRnE),Device (not nGnRnE),Normal,?..."
bitfld.long 0x00 12.--13. "TR6,{TEX[0] C B} = b110 Remap" "Device (nGnRnE),Device (not nGnRnE),Normal,?..."
newline
bitfld.long 0x00 10.--11. "TR5,{TEX[0] C B} = b101 Remap" "Device (nGnRnE),Device (not nGnRnE),Normal,?..."
bitfld.long 0x00 8.--9. "TR4,{TEX[0] C B} = b100 Remap" "Device (nGnRnE),Device (not nGnRnE),Normal,?..."
newline
bitfld.long 0x00 6.--7. "TR3,{TEX[0] C B} = b011 Remap" "Device (nGnRnE),Device (not nGnRnE),Normal,?..."
bitfld.long 0x00 4.--5. "TR2,{TEX[0] C B} = b010 Remap" "Device (nGnRnE),Device (not nGnRnE),Normal,?..."
newline
bitfld.long 0x00 2.--3. "TR1,{TEX[0] C B} = b001 Remap" "Device (nGnRnE),Device (not nGnRnE),Normal,?..."
bitfld.long 0x00 0.--1. "TR0,{TEX[0] C B} = b000 Remap" "Device (nGnRnE),Device (not nGnRnE),Normal,?..."
group.long c15:0x012A++0x0
line.long 0x00 "NMRR,Normal Memory Remap Register"
bitfld.long 0x00 30.--31. "OR7,Outer Attribute for {TEX[0] C B} = b111 Remap" "Non-cacheable,Write-Back Allocate,Write-Through,Write-Back no Allocate"
bitfld.long 0x00 28.--29. "OR6,Outer Attribute for {TEX[0] C B} = b110 Remap" "Non-cacheable,Write-Back Allocate,Write-Through,Write-Back no Allocate"
newline
bitfld.long 0x00 26.--27. "OR5,Outer Attribute for {TEX[0] C B} = b101 Remap" "Non-cacheable,Write-Back Allocate,Write-Through,Write-Back no Allocate"
bitfld.long 0x00 24.--25. "OR4,Outer Attribute for {TEX[0] C B} = b100 Remap" "Non-cacheable,Write-Back Allocate,Write-Through,Write-Back no Allocate"
newline
bitfld.long 0x00 22.--23. "OR3,Outer Attribute for {TEX[0] C B} = b011 Remap" "Non-cacheable,Write-Back Allocate,Write-Through,Write-Back no Allocate"
bitfld.long 0x00 20.--21. "OR2,Outer Attribute for {TEX[0] C B} = b010 Remap" "Non-cacheable,Write-Back Allocate,Write-Through,Write-Back no Allocate"
newline
bitfld.long 0x00 18.--19. "OR1,Outer Attribute for {TEX[0] C B} = b001 Remap" "Non-cacheable,Write-Back Allocate,Write-Through,Write-Back no Allocate"
bitfld.long 0x00 16.--17. "OR0,Outer Attribute for {TEX[0] C B} = b000 Remap" "Non-cacheable,Write-Back Allocate,Write-Through,Write-Back no Allocate"
newline
bitfld.long 0x00 14.--15. "IR7,Inner attribute for {TEX[0] C B} = b111 Remap" "Non-cacheable,Write-Back Allocate,Write-Through,Write-Back no Allocate"
bitfld.long 0x00 12.--13. "IR6,Inner attribute for {TEX[0] C B} = b110 Remap" "Non-cacheable,Write-Back Allocate,Write-Through,Write-Back no Allocate"
newline
bitfld.long 0x00 10.--11. "IR5,Inner attribute for {TEX[0] C B} = b101 Remap" "Non-cacheable,Write-Back Allocate,Write-Through,Write-Back no Allocate"
bitfld.long 0x00 8.--9. "IR4,Inner attribute for {TEX[0] C B} = b100 Remap" "Non-cacheable,Write-Back Allocate,Write-Through,Write-Back no Allocate"
newline
bitfld.long 0x00 6.--7. "IR3,Inner attribute for {TEX[0] C B} = b011 Remap" "Non-cacheable,Write-Back Allocate,Write-Through,Write-Back no Allocate"
bitfld.long 0x00 4.--5. "IR2,Inner attribute for {TEX[0] C B} = b010 Remap" "Non-cacheable,Write-Back Allocate,Write-Through,Write-Back no Allocate"
newline
bitfld.long 0x00 2.--3. "IR1,Inner attribute for {TEX[0] C B} = b001 Remap" "Non-cacheable,Write-Back Allocate,Write-Through,Write-Back no Allocate"
bitfld.long 0x00 0.--1. "IR0,Inner attribute for {TEX[0] C B} = b000 Remap" "Non-cacheable,Write-Back Allocate,Write-Through,Write-Back no Allocate"
group.long c15:0x010D++0x00
line.long 0x00 "CONTEXTIDR,Context ID Register"
hexmask.long.tbyte 0x00 8.--31. 1. "PROCID,Process Identifier"
hexmask.long.byte 0x00 0.--7. 1. "ASID,Address Space Identifier"
endif
elif corename()=="CORTEXA55"
if (((per.l(c15:0x0202))&0x80000000)==0x80000000)
group.long c15:0x002A++0x00
line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0"
bitfld.long 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3L,Attribute 3 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2L,Attribute 2 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1L,Attribute 1 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0L,Attribute 0 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
group.long c15:0x012A++0x00
line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1"
bitfld.long 0x00 28.--31. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR7L,Attribute 7 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 20.--23. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR6L,Attribute 6 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 12.--15. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR5L,Attribute 5 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 4.--7. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR4L,Attribute 4 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
group.long c15:0x010D++0x00
line.long 0x00 "CONTEXTIDR,Context ID Register"
else
group.long c15:0x002A++0x0
line.long 0x00 "PRRR,Primary Region Remap Register"
bitfld.long 0x00 31. "NOS7,Outer Shareable property mapping for memory attributes" "Outer,Inner"
bitfld.long 0x00 30. "NOS6,Outer Shareable property mapping for memory attributes" "Outer,Inner"
newline
bitfld.long 0x00 29. "NOS5,Outer Shareable property mapping for memory attributes" "Outer,Inner"
bitfld.long 0x00 28. "NOS4,Outer Shareable property mapping for memory attributes" "Outer,Inner"
newline
bitfld.long 0x00 27. "NOS3,Outer Shareable property mapping for memory attributes" "Outer,Inner"
bitfld.long 0x00 26. "NOS2,Outer Shareable property mapping for memory attributes" "Outer,Inner"
newline
bitfld.long 0x00 25. "NOS1,Outer Shareable property mapping for memory attributes" "Outer,Inner"
bitfld.long 0x00 24. "NOS0,Outer Shareable property mapping for memory attributes" "Outer,Inner"
newline
bitfld.long 0x00 19. "NS1,Mapping of S = 1 attribute for Normal memory" "Not shareable,Shareable"
bitfld.long 0x00 18. "NS0,Mapping of S = 0 attribute for Normal memory" "Not shareable,Shareable"
newline
bitfld.long 0x00 17. "DS1,Mapping of S = 1 attribute for Device memory" "Not shareable,Shareable"
bitfld.long 0x00 16. "DS0,Mapping of S = 0 attribute for Device memory" "Not shareable,Shareable"
newline
bitfld.long 0x00 14.--15. "TR7,{TEX[0] C B} = b111 Remap" "Device (nGnRnE),Device (not nGnRnE),Normal,?..."
bitfld.long 0x00 12.--13. "TR6,{TEX[0] C B} = b110 Remap" "Device (nGnRnE),Device (not nGnRnE),Normal,?..."
newline
bitfld.long 0x00 10.--11. "TR5,{TEX[0] C B} = b101 Remap" "Device (nGnRnE),Device (not nGnRnE),Normal,?..."
bitfld.long 0x00 8.--9. "TR4,{TEX[0] C B} = b100 Remap" "Device (nGnRnE),Device (not nGnRnE),Normal,?..."
newline
bitfld.long 0x00 6.--7. "TR3,{TEX[0] C B} = b011 Remap" "Device (nGnRnE),Device (not nGnRnE),Normal,?..."
bitfld.long 0x00 4.--5. "TR2,{TEX[0] C B} = b010 Remap" "Device (nGnRnE),Device (not nGnRnE),Normal,?..."
newline
bitfld.long 0x00 2.--3. "TR1,{TEX[0] C B} = b001 Remap" "Device (nGnRnE),Device (not nGnRnE),Normal,?..."
bitfld.long 0x00 0.--1. "TR0,{TEX[0] C B} = b000 Remap" "Device (nGnRnE),Device (not nGnRnE),Normal,?..."
group.long c15:0x012A++0x0
line.long 0x00 "NMRR,Normal Memory Remap Register"
bitfld.long 0x00 30.--31. "OR7,Outer Attribute for {TEX[0] C B} = b111 Remap" "Non-cacheable,Write-Back Allocate,Write-Through,Write-Back no Allocate"
bitfld.long 0x00 28.--29. "OR6,Outer Attribute for {TEX[0] C B} = b110 Remap" "Non-cacheable,Write-Back Allocate,Write-Through,Write-Back no Allocate"
newline
bitfld.long 0x00 26.--27. "OR5,Outer Attribute for {TEX[0] C B} = b101 Remap" "Non-cacheable,Write-Back Allocate,Write-Through,Write-Back no Allocate"
bitfld.long 0x00 24.--25. "OR4,Outer Attribute for {TEX[0] C B} = b100 Remap" "Non-cacheable,Write-Back Allocate,Write-Through,Write-Back no Allocate"
newline
bitfld.long 0x00 22.--23. "OR3,Outer Attribute for {TEX[0] C B} = b011 Remap" "Non-cacheable,Write-Back Allocate,Write-Through,Write-Back no Allocate"
bitfld.long 0x00 20.--21. "OR2,Outer Attribute for {TEX[0] C B} = b010 Remap" "Non-cacheable,Write-Back Allocate,Write-Through,Write-Back no Allocate"
newline
bitfld.long 0x00 18.--19. "OR1,Outer Attribute for {TEX[0] C B} = b001 Remap" "Non-cacheable,Write-Back Allocate,Write-Through,Write-Back no Allocate"
bitfld.long 0x00 16.--17. "OR0,Outer Attribute for {TEX[0] C B} = b000 Remap" "Non-cacheable,Write-Back Allocate,Write-Through,Write-Back no Allocate"
newline
bitfld.long 0x00 14.--15. "IR7,Inner attribute for {TEX[0] C B} = b111 Remap" "Non-cacheable,Write-Back Allocate,Write-Through,Write-Back no Allocate"
bitfld.long 0x00 12.--13. "IR6,Inner attribute for {TEX[0] C B} = b110 Remap" "Non-cacheable,Write-Back Allocate,Write-Through,Write-Back no Allocate"
newline
bitfld.long 0x00 10.--11. "IR5,Inner attribute for {TEX[0] C B} = b101 Remap" "Non-cacheable,Write-Back Allocate,Write-Through,Write-Back no Allocate"
bitfld.long 0x00 8.--9. "IR4,Inner attribute for {TEX[0] C B} = b100 Remap" "Non-cacheable,Write-Back Allocate,Write-Through,Write-Back no Allocate"
newline
bitfld.long 0x00 6.--7. "IR3,Inner attribute for {TEX[0] C B} = b011 Remap" "Non-cacheable,Write-Back Allocate,Write-Through,Write-Back no Allocate"
bitfld.long 0x00 4.--5. "IR2,Inner attribute for {TEX[0] C B} = b010 Remap" "Non-cacheable,Write-Back Allocate,Write-Through,Write-Back no Allocate"
newline
bitfld.long 0x00 2.--3. "IR1,Inner attribute for {TEX[0] C B} = b001 Remap" "Non-cacheable,Write-Back Allocate,Write-Through,Write-Back no Allocate"
bitfld.long 0x00 0.--1. "IR0,Inner attribute for {TEX[0] C B} = b000 Remap" "Non-cacheable,Write-Back Allocate,Write-Through,Write-Back no Allocate"
group.long c15:0x010D++0x00
line.long 0x00 "CONTEXTIDR,Context ID Register"
hexmask.long.tbyte 0x00 8.--31. 1. "PROCID,Process Identifier"
hexmask.long.byte 0x00 0.--7. 1. "ASID,Address Space Identifier"
endif
endif
tree.end
tree.end
tree "Virtualization Extensions"
group.long c15:0x4000++0x00
line.long 0x00 "VPIDR,Virtualization Processor ID Register"
hexmask.long.byte 0x0 24.--31. 0x1 "IMPL,Implementer code"
bitfld.long 0x00 20.--23. "VAR,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 16.--19. "ARCH, Architecture" "0,ARMv4,ARMv4T,ARMv5,ARMv5T,ARMv5TE,ARMv5TEJ,ARMv6,8,9,10,11,12,13,14,CPUID scheme"
hexmask.long.word 0x00 4.--15. 1. "PART,Primary Part Number"
newline
bitfld.long 0x00 0.--3. "REV,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long c15:0x4500++0x00
line.long 0x00 "VMPIDR,Virtualization Multiprocessor ID Registers"
bitfld.long 0x00 31. "M,Multiprocessing Extensions Register format" "Reserved,Supported"
bitfld.long 0x00 30. "U,Processor is part of a multiprocessor or uniprocessor system" "Multiprocessor,Uniprocessor"
newline
bitfld.long 0x00 24. "MT,Lowest level of affinity consist of logical processors" "Not implemented,Implemented"
hexmask.long.byte 0x00 16.--23. 1. "AFF2,Affinity level 2. Identifies different clusters within the system"
newline
bitfld.long 0x00 8.--15. "AFF1,Affinity level 1. Identifies individual cores within the local FCM cluster" "CORE0,CORE1,CORE2,CORE3,CORE4,CORE5,CORE6,CORE7,?..."
hexmask.long.byte 0x00 0.--7. 1. "AFF0,Affinity level 0. Identifies individual threads within a multi-threaded core"
group.long c15:0x420D++0x00
line.long 0x00 "HTPIDR,Hypervisor Software Thread ID Register"
group.long c15:0x4001++0x0
line.long 0x00 "HSCTLR,Hypervisor System Control Register"
bitfld.long 0x00 30. "TE,Thumb exception enable" "A32,T32"
bitfld.long 0x00 25. "EE,Exception endianness" "Little,Big"
newline
bitfld.long 0x00 19. "WXN,Write permission implies XN" "Not forced,Forced"
bitfld.long 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 8. "SED,SETEND Disable" "No,Yes"
bitfld.long 0x00 7. "ITD,IT instruction functionality Disabled" "No,?..."
newline
bitfld.long 0x00 5. "CP15BEN,C15 Barrier Enable" "Disabled,Enabled"
bitfld.long 0x00 4. "LSMAOE,Load/Store Multiple Atomicity and Ordering Enable" "Reserved,Enabled"
newline
bitfld.long 0x00 3. "NTLSMD,No Trap Load/Store Multiple to Device-nGRE/Device-nGnRE/Device-nGnRnE memory" "Reserved,No Trap"
bitfld.long 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
newline
bitfld.long 0x00 1. "A,Strict Alignment" "Disabled,Enabled"
bitfld.long 0x00 0. "M,Enable address translation" "Disabled,Enabled"
group.long c15:0x4101++0x00
line.long 0x00 "HACTLR,Hypervisor Auxiliary Control Register"
bitfld.long 0x00 12. "CLUSTERPMUEN,Performance Management Registers write access control" "Not accessible,Accessible"
bitfld.long 0x00 11. "SMEN,Scheme Management Registers write access control" "Not accessible,Accessible"
newline
bitfld.long 0x00 10. "TSIDEN,Thread Scheme ID Register enable" "Not accessible,Accessible"
bitfld.long 0x00 7. "PWREN,Power Control Registers access control" "Not accessible,Accessible"
newline
bitfld.long 0x00 5. "ERXPFGEN,Error Record Registers write access control" "Not accessible,Accessible"
bitfld.long 0x00 1. "ECTLREN,Extended Control Registers write access control" "Not accessible,Accessible"
newline
bitfld.long 0x00 0. "ACTLREN,Auxiliary Control Registers write access control" "Not accessible,Accessible"
rgroup.long c15:0x4301++0x00
line.long 0x00 "HACTLR2,Hypervisor Auxiliary Control Register 2"
rgroup.long c15:0x4711++0x00
line.long 0x00 "HACR,Hypervisor Auxiliary Configuration Register"
group.long c15:0x4011++0x00
line.long 0x00 "HCR,Hypervisor Configuration Register"
bitfld.long 0x00 30. "TRVM,Trap Read of Virtual Memory controls" "No trap,Trap"
bitfld.long 0x00 27. "TGE,Trap General Exceptions from Non-secure EL0" "No trap,Trap"
newline
bitfld.long 0x00 26. "TVM,Trap Virtual Memory controls" "No trap,Trap"
bitfld.long 0x00 25. "TTLB,Trap TLB maintenance instructions" "No trap,Trap"
newline
bitfld.long 0x00 24. "TPU,Trap Cache maintenance instructions to Point of Unification" "No trap,Trap"
bitfld.long 0x00 23. "TPC,Trap Data/Unified Cache maintenance instructions to Point of Coherency" "No trap,Trap"
newline
bitfld.long 0x00 22. "TSW,Trap Data/Unified Cache maintenance instructions by Set/Way" "No trap,Trap"
bitfld.long 0x00 21. "TAC,Trap Auxiliary Control Register" "No trap,Trap"
newline
bitfld.long 0x00 20. "TIDCP,Trap Implementation Dependent functionality" "No trap,Trap"
bitfld.long 0x00 19. "TSC,Trap SMC" "No trap,Trap"
newline
bitfld.long 0x00 18. "TID3,Trap ID Group 3" "No trap,Trap"
bitfld.long 0x00 17. "TID2,Trap ID Group 2" "No trap,Trap"
newline
bitfld.long 0x00 16. "TID1,Trap ID Group 1" "No trap,Trap"
bitfld.long 0x00 15. "TID0,Trap ID Group 0" "No trap,Trap"
newline
bitfld.long 0x00 14. "TWE,Trap WFE" "No trap,Trap"
bitfld.long 0x00 13. "TWI,Trap WFI" "No trap,Trap"
newline
bitfld.long 0x00 12. "DC,Default Cacheable" "Disabled,Enabled"
bitfld.long 0x00 10.--11. "BSU,Barrier Shareability upgrade" "No effect,Inner Shareable,Outer Shareable,Full System"
newline
bitfld.long 0x00 9. "FB,Force broadcast" "Not forced,Forced"
bitfld.long 0x00 8. "VA,Virtual Asynchronous Abort exception" "Not pending,Pending"
newline
bitfld.long 0x00 7. "VI,Virtual IRQ Interrupt" "Not pending,Pending"
bitfld.long 0x00 6. "VF,Virtual FIQ Interrupt" "Not pending,Pending"
newline
bitfld.long 0x00 5. "AMO,Asynchronous Abort Mask Override" "Disabled,Enabled"
bitfld.long 0x00 4. "IMO,Physical IRQ Routing" "Disabled,Enabled"
newline
bitfld.long 0x00 3. "FMO,Physical FIQ Routing" "Disabled,Enabled"
bitfld.long 0x00 2. "PTW,Protected Table Walk" "Disabled,Enabled"
newline
bitfld.long 0x00 1. "SWIO,Set/Way Invalidation Override" "Disabled,Enabled"
bitfld.long 0x00 0. "VM,Second stage of Translation enable" "Disabled,Enabled"
group.long c15:0x4411++0x00
line.long 0x00 "HCR2,Hypervisor Configuration Register"
bitfld.long 0x00 5. "TEA,   Route synchronous external aborts to EL2" "Not routed,Routed"
bitfld.long 0x00 4. "TERR,   Trap Error record accesses" "No trap,Trap"
newline
bitfld.long 0x00 1. "ID,Stage 2 Instruction cache disable" "No,Yes"
bitfld.long 0x00 0. "CD,Stage 2 Data cache disable" "No,Yes"
group.long c15:0x3054++0x00
line.long 0x00 "DSPSR,Debug Saved Program Status Register"
bitfld.long 0x00 31. "N,Negative condition flag" "Not negative,Negative"
bitfld.long 0x00 30. "Z,Zero condition flag" "Not zero,Zero"
newline
bitfld.long 0x00 29. "C,Carry condition flag" "Not carry,Carry"
bitfld.long 0x00 28. "V,Overflow condition flag" "No overflow,Overflow"
newline
bitfld.long 0x00 27. "Q,Cumulative condition flag" "Not occurred,Occurred"
bitfld.long 0x00 22. "PAN,Privileged Access Never" "No,Yes"
newline
bitfld.long 0x00 21. "SS,Software step" "0,1"
bitfld.long 0x00 20. "IL,Illegal Execution state" "0,1"
newline
bitfld.long 0x00 16.--19. "GE,Greater than or Equal flags" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 13.--15. "IT[5:7],IT block state bits for the T32 IT (If-Then) instruction - base condition for the IT block" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 25.--26. 10.--12. "IT[0:4],IT block state bits for the T32 IT (If-Then) instruction - size of the IT block" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 9. "E,Endianness state bit" "Little,Big"
newline
bitfld.long 0x00 8. "A,Asynchronous data abort mask bit" "Not masked,Masked"
bitfld.long 0x00 7. "I,IRQ mask bit" "Not masked,Masked"
newline
bitfld.long 0x00 6. "F,FIQ mask bit" "Not masked,Masked"
bitfld.long 0x00 5. "T,T32 Instruction set state" "A32,T32"
newline
bitfld.long 0x00 4. "M[4],Execution state that the exception was taken from" ",AArch32"
bitfld.long 0x00 0.--3. "M[3:0],Current PE mode" "User,FIQ,IRQ,Supervisor,,,Monitor,Abort,,,Hyp,Undefined,,,,System"
group.long c15:0x4111++0x00
line.long 0x00 "HDCR,Hypervisor Debug Control Register"
bitfld.long 0x00 17. "HPMD,Guest Performance Monitors Disable" "Allowed,Prohibited"
bitfld.long 0x00 11. "TDRA,Trap Debug ROM Access" "No trap,Trap"
newline
bitfld.long 0x00 10. "TDOSA,Trap Debug OS-related Register Access" "No trap,Trap"
bitfld.long 0x00 9. "TDA,Trap Debug Access" "No trap,Trap"
newline
bitfld.long 0x00 8. "TDE,Trap Debug Exceptions" "No trap,Trap"
bitfld.long 0x00 7. "HPME,Hypervisor Performance Monitors Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 6. "TPM,Trap Performance Monitors accesses" "No trap,Trap"
bitfld.long 0x00 5. "TPMCR,Trap Performance Monitor Control Register accesses" "No trap,Trap"
newline
bitfld.long 0x00 0.--4. "HPMN,Defines the number of Performance Monitors counters" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long c15:0x4211++0x00
line.long 0x00 "HCPTR,Hypervisor Coprocessor Trap Register"
bitfld.long 0x0 31. "TCPAC,Trap Coprocessor Access Control" "No trap,Trap"
bitfld.long 0x0 20. "TTA,Traps Non-secure System Register accesses to all implemented trace Registers to Hypervisor mode" "No trap,Trap"
newline
bitfld.long 0x0 15. "TASE,Trap Advanced SIMD extensions" "No trap,Trap"
bitfld.long 0x0 11. "TCP11,Trap coprocessor 11" "No trap,Trap"
newline
bitfld.long 0x0 10. "TCP10,Trap coprocessor 10" "No trap,Trap"
group.long c15:0x4311++0x00
line.long 0x00 "HSTR,Hypervisor System Trap Register"
bitfld.long 0x00 15. "T15,Trap to Hypervisor mode Non-secure priv 15" "No trap,Trap"
bitfld.long 0x00 13. "T13,Trap to Hypervisor mode Non-secure priv 13" "No trap,Trap"
newline
bitfld.long 0x00 12. "T12,Trap to Hypervisor mode Non-secure priv 12" "No trap,Trap"
bitfld.long 0x00 11. "T11,Trap to Hypervisor mode Non-secure priv 11" "No trap,Trap"
newline
bitfld.long 0x00 10. "T10,Trap to Hypervisor mode Non-secure priv 10" "No trap,Trap"
bitfld.long 0x00 9. "T9,Trap to Hypervisor mode Non-secure priv 9" "No trap,Trap"
newline
bitfld.long 0x00 8. "T8,Trap to Hypervisor mode Non-secure priv 8" "No trap,Trap"
bitfld.long 0x00 7. "T7,Trap to Hypervisor mode Non-secure priv 7" "No trap,Trap"
newline
bitfld.long 0x00 6. "T6,Trap to Hypervisor mode Non-secure priv 6" "No trap,Trap"
bitfld.long 0x00 5. "T5,Trap to Hypervisor mode Non-secure priv 5" "No trap,Trap"
newline
bitfld.long 0x00 3. "T3,Trap to Hypervisor mode Non-secure priv 3" "No trap,Trap"
bitfld.long 0x00 2. "T2,Trap to Hypervisor mode Non-secure priv 2" "No trap,Trap"
newline
bitfld.long 0x00 1. "T1,Trap to Hypervisor mode Non-secure priv 1" "No trap,Trap"
bitfld.long 0x00 0. "T0,Trap to Hypervisor mode Non-secure priv 0" "No trap,Trap"
group.quad c15:0x14020++0x01
line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register"
hexmask.quad 0x00 1.--47. 0x02 "BADDR,Translation table base address"
bitfld.quad 0x00 0. "CNP,Common not Private" "Not supported,Supported"
group.long c15:0x4202++0x00
line.long 0x00 "HTCR,Hypervisor Translation Control Register"
bitfld.long 0x00 28. "HWU62,Hardware usage of bit[62] of the stage2 translation table block or level 3 entry" "Not possible,Possible"
bitfld.long 0x00 27. "HWU61,Hardware usage of bit[61] of the stage2 translation table block or level 3 entry" "Not possible,Possible"
newline
bitfld.long 0x00 26. "HWU60,Hardware usage of bit[60] of the stage2 translation table block or level 3 entry" "Not possible,Possible"
bitfld.long 0x00 25. "HWU59,Hardware usage of bit[59] of the stage2 translation table block or level 3 entry" "Not possible,Possible"
newline
bitfld.long 0x00 24. "HPD,Hierarchical Permission Disables" "No,Yes"
bitfld.long 0x00 12.--13. "SH0,Shareability attribute" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
newline
bitfld.long 0x00 10.--11. "ORGN0,Outer cacheability attribute, Normal memory" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
bitfld.long 0x00 8.--9. "IRGN0,  ,Inner cacheability attribute, Normal memory" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.long 0x00 0.--2. "T0SZ,The size offset of the memory region addressed by HTTBR" "0,1,2,3,4,5,6,7"
if corename()=="CORTEXA75"
group.quad c15:0x16020++0x01
line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register"
hexmask.quad.word 0x00 48.--63. 1. "VMID,VMID for the translation table"
hexmask.quad 0x00 4.--47. 0x10 "BADDR,Translation table base address"
newline
bitfld.quad 0x00 0. "CNP,Common not Private" "Not supported,Supported"
elif corename()=="CORTEXA55"
group.long c15:0x407F++0x00
line.long 0x00 "AHTCR,Auxiliary Hypervisor Translation Control Register"
bitfld.long 0x00 9. "HWVAL60,Indicates the value of PBHA[1] page table walks memory access if HWEN60 is set" "0,1"
bitfld.long 0x00 8. "HWVAL59,Indicates the value of PBHA[1] page table walks memory access if HWEN59 is set" "0,1"
newline
bitfld.long 0x00 1. "HWEN60,Enables PBHA[1] page table walks memory access" "Disabled,Enabled"
bitfld.long 0x00 0. "HWEN59,Enables PBHA[0] page table walks memory access" "Disabled,Enabled"
group.quad c15:0x16020++0x01
line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register"
hexmask.quad.word 0x00 48.--63. 1. "ASID,ASID for the translation table base address"
hexmask.quad 0x00 2.--47. 0x04 "BADDR,Translation table base address"
newline
bitfld.quad 0x00 0. "CNP,Common not Private" "Not supported,?..."
endif
if corename()=="CORTEXA75"
group.long c15:0x4212++0x00
line.long 0x00 "VTCR,Virtualization Translation Control Register"
bitfld.long 0x00 28. "HWU62,Hardware usage of bit[62] of the stage2 translation table block or level 3 entry" "Not possible,Possible"
bitfld.long 0x00 27. "HWU61,Hardware usage of bit[61] of the stage2 translation table block or level 3 entry" "Not possible,Possible"
newline
bitfld.long 0x00 26. "HWU60,Hardware usage of bit[60] of the stage2 translation table block or level 3 entry" "Not possible,Possible"
bitfld.long 0x00 25. "HWU59,Hardware usage of bit[59] of the stage2 translation table block or level 3 entry" "Not possible,Possible"
newline
bitfld.long 0x00 12.--13. "SH0,Shareability attribute" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
bitfld.long 0x00 10.--11. "ORGN0,Outer cacheability attribute, Normal memory" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.long 0x00 8.--9. "IRGN0,Inner cacheability attribute, Normal memory" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
bitfld.long 0x00 6.--7. "SL0,Starting level for translation table walks using VTTBR" "L2,L1,?..."
newline
bitfld.long 0x00 4. "S,Sign extension bit" "0,1"
bitfld.long 0x00 0.--3. "T0SZ,Size offset of the memory region addressed by TTBR0" "0,1,2,3,4,5,6,7,-8,-7,-6,-5,-4,-3,-2,-1"
elif corename()=="CORTEXA55"
group.long c15:0x4212++0x00
line.long 0x00 "VTCR,Virtualization Translation Control Register"
bitfld.long 0x00 12.--13. "SH0,Shareability attribute" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
bitfld.long 0x00 10.--11. "ORGN0,Outer cacheability attribute, Normal memory" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.long 0x00 8.--9. "IRGN0,Inner cacheability attribute, Normal memory" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
bitfld.long 0x00 6.--7. "SL0,Starting level for translation table walks using VTTBR" "L2,L1,?..."
newline
bitfld.long 0x00 4. "S,Sign extension bit" "0,1"
bitfld.long 0x00 0.--3. "T0SZ,Size offset of the memory region addressed by TTBR0" "0,1,2,3,4,5,6,7,-8,-7,-6,-5,-4,-3,-2,-1"
group.long c15:0x417F++0x00
line.long 0x00 "AVTCR,Auxiliary Virtualized Translation Control Register"
bitfld.long 0x00 9. "HWVAL60,Indicates the value of PBHA[1] page table walks memory access if HWEN60 is set" "0,1"
bitfld.long 0x00 8. "HWVAL59,Indicates the value of PBHA[1] page table walks memory access if HWEN59 is set" "0,1"
newline
bitfld.long 0x00 1. "HWEN60,Enables PBHA[1] page table walks memory access" "Disabled,Enabled"
bitfld.long 0x00 0. "HWEN59,Enables PBHA[0] page table walks memory access" "Disabled,Enabled"
endif
rgroup.long c15:0x4015++0x00
line.long 0x00 "HADFSR,Hypervisor Auxiliary Data Fault Status Syndrome Register"
rgroup.long c15:0x4115++0x00
line.long 0x00 "HAIFSR,Hypervisor Auxiliary Instruction Fault Status Register"
group.long c15:0x4006++0x00
line.long 0x00 "HDFAR,Hypervisor Data Fault Address Register"
group.long c15:0x3154++0x00
line.long 0x00 "DLR,Debug Link Register"
if (((per.l(c15:0x4025))&0xFC000000)==0x0)
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hypervisor Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped Coprocessor Usage,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..."
elif (((per.l(c15:0x4025))&0xFC000000)==0x4000000)
if (((per.l(c15:0x4025))&0x1000000)==0x1000000)
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hypervisor Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped Coprocessor Usage,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..."
bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Invalid,Valid"
bitfld.long 0x00 20.--23. "COND,The condition code for the trapped instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0. "TI,Trapped instruction" "WFI,WFE"
else
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hypervisor Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped Coprocessor Usage,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..."
bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Invalid,Valid"
bitfld.long 0x00 0. "TI,Trapped instruction" "WFI,WFE"
endif
elif (((per.l(c15:0x4025))&0xFC000000)==(0xC000000||0x20000000||0x14000000))
if (((per.l(c15:0x4025))&0x1000000)==0x1000000)
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hypervisor Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped Coprocessor Usage,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..."
bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Invalid,Valid"
bitfld.long 0x00 20.--23. "COND,The condition code for the trapped instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 17.--19. "OPC2,The Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 14.--16. "OPC1,The Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 10.--13. "CRN,The CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 5.--8. "RT,The Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 1.--4. "CRM,The CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "DIRECTION,Indicates the direction of the trapped instruction" "MCR,MRC/VMRS"
else
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hypervisor Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped Coprocessor Usage,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..."
bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Invalid,Valid"
bitfld.long 0x00 17.--19. "OPC2,The Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 14.--16. "OPC1,The Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10.--13. "CRN,The CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 5.--8. "RT,The Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1.--4. "CRM,The CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0. "DIRECTION,Indicates the direction of the trapped instruction" "MCR,MRC/VMRS"
endif
elif (((per.l(c15:0x4025))&0xFC000000)==(0x10000000||0x30000000))
if (((per.l(c15:0x4025))&0x1000000)==0x1000000)
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hypervisor Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped Coprocessor Usage,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..."
bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Invalid,Valid"
bitfld.long 0x00 20.--23. "COND,The condition code for the trapped instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 16.--19. "OPC1,The Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 10.--13. "RT2,The Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 5.--8. "RT,The Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1.--4. "CRM,The CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0. "DIRECTION,Indicates the direction of the trapped instruction" "MCRR,MRRC"
else
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hypervisor Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped Coprocessor Usage,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..."
bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Invalid,Valid"
bitfld.long 0x00 16.--19. "OPC1,The Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 10.--13. "RT2,The Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 5.--8. "RT,The Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 1.--4. "CRM,The CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "DIRECTION,Indicates the direction of the trapped instruction" "MCRR,MRRC"
endif
elif (((per.l(c15:0x4025))&0xFC000000)==0x18000000)
if (((per.l(c15:0x4025))&0x1000000)==0x1000000)
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hypervisor Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped Coprocessor Usage,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..."
bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Invalid,Valid"
bitfld.long 0x00 20.--23. "COND,The condition code for the trapped instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction"
bitfld.long 0x00 5.--8. "RN,The Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
bitfld.long 0x00 1.--3. "AM,Addressing mode" "Imm unindexed,Imm post-indexed,Imm offset,Imm pre-indexed,Literal unindexed (A32),Reserved,Literal offset (A32),?..."
newline
bitfld.long 0x00 0. "DIRECTION,Indicates the direction of the trapped instruction" "STC,LDC"
else
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hypervisor Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped Coprocessor Usage,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..."
bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Invalid,Valid"
hexmask.long.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction"
newline
bitfld.long 0x00 5.--8. "RN,The Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
newline
bitfld.long 0x00 1.--3. "AM,Addressing mode" "Imm unindexed,Imm post-indexed,Imm offset,Imm pre-indexed,Literal unindexed (A32),Reserved,Literal offset (A32),?..."
bitfld.long 0x00 0. "DIRECTION,Indicates the direction of the trapped instruction" "STC,LDC"
endif
elif (((per.l(c15:0x4025))&0xFC000000)==0x1C000000)
if (((per.l(c15:0x4025))&0x1000000)==0x1000000)
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hypervisor Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped Coprocessor Usage,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..."
bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Invalid,Valid"
bitfld.long 0x00 20.--23. "COND,The condition code for the trapped instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 5. "TA,Indicates trapped use of Advanced SIMD functionality" "Not occurred,Occurred"
bitfld.long 0x00 0.--3. "COPROC,The number of the coprocessor accessed by the trapped operation" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CP10,?..."
else
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hypervisor Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped Coprocessor Usage,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..."
bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Invalid,Valid"
bitfld.long 0x00 5. "TA,Indicates trapped use of Advanced SIMD functionality" "Not occurred,Occurred"
newline
bitfld.long 0x00 0.--3. "COPROC,The number of the coprocessor accessed by the trapped operation" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CP10,?..."
endif
elif (((per.l(c15:0x4025))&0xFC000000)==(0x44000000||0x48000000))
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hypervisor Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped Coprocessor Usage,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..."
bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit"
newline
hexmask.long.word 0x00 0.--15. 1. "IMM16,The value of the immediate field from the HVC or SVC instruction"
elif ((((per.l(c15:0x4025))&0xFC000000)==(0x80000000||0x84000000))&&(((per.l(c15:0x4025))&0x3F)==0x10))
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hypervisor Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped Coprocessor Usage,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..."
bitfld.long 0x00 10. "FNV,FAR not Valid" "HIFAR valid,HIFAR invalid"
newline
bitfld.long 0x00 9. "EA,External abort type" "Internal,External"
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an access for a stage 1 translation table walk" "Not occurred,Occurred"
newline
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code. SEA - Synchronous External Abort / SPE - Synchronous parity or ECC" "Address/TTBR,Address/Lvl1,Address/Lvl2,Address/Lvl3,Reserved,Translation/Lvl1,Translation/Lvl2,Translation/Lvl3,Reserved,Access flag/Lvl1,Access flag/Lvl2,Access flag/Lvl3,Reserved,Permission/Lvl1,Permission/Lvl2,Permission/Lvl3,SEA/Not ECC/Not on TTBW,Reserved,Reserved,Reserved,Reserved,SEA/Not ECC/On TTBW lvl1,SEA/Not ECC/On TTBW lvl2,SEA/Not ECC/On TTBW lvl3,SPE on mem access/Not on TTBW,Reserved,Reserved,Reserved,Reserved,SPE on mem access/On TTBW lvl1,SPE on mem access/On TTBW lvl2,SPE on mem access/On TTBW lvl3,Reserved,Reserved,Debug (only from Hypervisor mode),Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict abort,?..."
elif ((((per.l(c15:0x4025))&0xFC000000)==(0x80000000||0x84000000))&&(((per.l(c15:0x4025))&0x3F)!=0x10))
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hypervisor Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped Coprocessor Usage,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..."
bitfld.long 0x00 9. "EA,External abort type" "Internal,External"
newline
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an access for a stage 1 translation table walk" "Not occurred,Occurred"
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code. SEA - Synchronous External Abort / SPE - Synchronous parity or ECC" "Address/TTBR,Address/Lvl1,Address/Lvl2,Address/Lvl3,Reserved,Translation/Lvl1,Translation/Lvl2,Translation/Lvl3,Reserved,Access flag/Lvl1,Access flag/Lvl2,Access flag/Lvl3,Reserved,Permission/Lvl1,Permission/Lvl2,Permission/Lvl3,SEA/Not ECC/Not on TTBW,Reserved,Reserved,Reserved,Reserved,SEA/Not ECC/On TTBW lvl1,SEA/Not ECC/On TTBW lvl2,SEA/Not ECC/On TTBW lvl3,SPE on mem access/Not on TTBW,Reserved,Reserved,Reserved,Reserved,SPE on mem access/On TTBW lvl1,SPE on mem access/On TTBW lvl2,SPE on mem access/On TTBW lvl3,Reserved,Reserved,Debug (only from Hypervisor mode),Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict abort,?..."
elif (((per.l(c15:0x4025))&0xFC000000)==(0x88000000||0x38000000))
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hypervisor Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped Coprocessor Usage,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..."
elif (((per.l(c15:0x4025))&0xFD000000)==(0x91000000||0x95000000))
if (((per.l(c15:0x4025))&0x3F)==(0x11))
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hypervisor Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped Coprocessor Usage,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..."
bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Invalid,Valid"
bitfld.long 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword"
newline
bitfld.long 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required"
bitfld.long 0x00 16.--19. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14. "AR,Acquire/Release semantics present" "Absent,Present"
bitfld.long 0x00 10.--11. "AET,Asynchronous Error Type" "UC,UEU,UEO/CE,UER"
newline
bitfld.long 0x00 9. "EA,External abort type" "Internal,External"
bitfld.long 0x00 8. "CM,Cache maintenance" "Not generated,Generated"
newline
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an access for a stage 1 translation table walk" "Not occurred,Occurred"
bitfld.long 0x00 6. "WNR,Write not Read as abort cause" "Read,Write"
newline
bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code. SEA - Synchronous External Abort / SPE - Synchronous parity or ECC" "Address/TTBR,Address/Lvl1,Address/Lvl2,Address/Lvl3,Reserved,Translation/Lvl1,Translation/Lvl2,Translation/Lvl3,Reserved,Access flag/Lvl1,Access flag/Lvl2,Access flag/Lvl3,Reserved,Permission/Lvl1,Permission/Lvl2,Permission/Lvl3,SEA/Not ECC/Not on TTBW,SError int,Reserved,Reserved,Reserved,SEA/Not ECC/On TTBW lvl1,SEA/Not ECC/On TTBW lvl2,SEA/Not ECC/On TTBW lvl3,SPE on mem access/Not on TTBW,SError int from parity/ECC err on mem access,Reserved,Reserved,Reserved,SPE on mem access/On TTBW lvl1,SPE on mem access/On TTBW lvl2,SPE on mem access/On TTBW lvl3,Reserved,Alignment fault,Debug (only from Hypervisor mode),Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict abort,Reserved,Reserved,Reserved,Lockdown fault,Unsupp Exclusive acc fault,?..."
else
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hypervisor Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped Coprocessor Usage,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..."
bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Invalid,Valid"
bitfld.long 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword"
newline
bitfld.long 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required"
bitfld.long 0x00 16.--19. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14. "AR,Acquire/Release semantics present" "Absent,Present"
bitfld.long 0x00 10. "FNV,FAR not Valid" "Valid,Invalid"
newline
bitfld.long 0x00 9. "EA,External abort type" "Internal,External"
bitfld.long 0x00 8. "CM,Cache maintenance" "Not generated,Generated"
newline
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an access for a stage 1 translation table walk" "Not occurred,Occurred"
bitfld.long 0x00 6. "WNR,Write not Read as abort cause" "Read,Write"
newline
bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code. SEA - Synchronous External Abort / SPE - Synchronous parity or ECC" "Address/TTBR,Address/Lvl1,Address/Lvl2,Address/Lvl3,Reserved,Translation/Lvl1,Translation/Lvl2,Translation/Lvl3,Reserved,Access flag/Lvl1,Access flag/Lvl2,Access flag/Lvl3,Reserved,Permission/Lvl1,Permission/Lvl2,Permission/Lvl3,SEA/Not ECC/Not on TTBW,SError int,Reserved,Reserved,Reserved,SEA/Not ECC/On TTBW lvl1,SEA/Not ECC/On TTBW lvl2,SEA/Not ECC/On TTBW lvl3,SPE on mem access/Not on TTBW,SError int from parity/ECC err on mem access,Reserved,Reserved,Reserved,SPE on mem access/On TTBW lvl1,SPE on mem access/On TTBW lvl2,SPE on mem access/On TTBW lvl3,Reserved,Alignment fault,Debug (only from Hypervisor mode),Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict abort,Reserved,Reserved,Reserved,Lockdown fault,Unsupp Exclusive acc fault,?..."
endif
elif (((per.l(c15:0x4025))&0xFD000000)==(0x90000000||0x94000000))
if (((per.l(c15:0x4025))&0x3F)==(0x11))
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hypervisor Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped Coprocessor Usage,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..."
bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Invalid,Valid"
bitfld.long 0x00 10.--11. "AET,Asynchronous Error Type" "UC,UEU,UEO/CE,UER"
newline
bitfld.long 0x00 9. "EA,External abort type" "Internal,External"
bitfld.long 0x00 8. "CM,Cache maintenance" "Not generated,Generated"
newline
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an access for a stage 1 translation table walk" "Not occurred,Occurred"
bitfld.long 0x00 6. "WNR,Write not Read as abort cause" "Read,Write"
newline
bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code. SEA - Synchronous External Abort / SPE - Synchronous parity or ECC" "Address/TTBR,Address/Lvl1,Address/Lvl2,Address/Lvl3,Reserved,Translation/Lvl1,Translation/Lvl2,Translation/Lvl3,Reserved,Access flag/Lvl1,Access flag/Lvl2,Access flag/Lvl3,Reserved,Permission/Lvl1,Permission/Lvl2,Permission/Lvl3,SEA/Not ECC/Not on TTBW,SError int,Reserved,Reserved,Reserved,SEA/Not ECC/On TTBW lvl1,SEA/Not ECC/On TTBW lvl2,SEA/Not ECC/On TTBW lvl3,SPE on mem access/Not on TTBW,SError int from parity/ECC err on mem access,Reserved,Reserved,Reserved,SPE on mem access/On TTBW lvl1,SPE on mem access/On TTBW lvl2,SPE on mem access/On TTBW lvl3,Reserved,Alignment fault,Debug (only from Hypervisor mode),Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict abort,Reserved,Reserved,Reserved,Lockdown fault,Unsupp Exclusive acc fault,?..."
else
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hypervisor Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped Coprocessor Usage,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..."
bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Invalid,Valid"
bitfld.long 0x00 10. "FNV,FAR not Valid" "Valid,Invalid"
newline
bitfld.long 0x00 9. "EA,External abort type" "Internal,External"
bitfld.long 0x00 8. "CM,Cache maintenance" "Not generated,Generated"
newline
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an access for a stage 1 translation table walk" "Not occurred,Occurred"
bitfld.long 0x00 6. "WNR,Write not Read as abort cause" "Read,Write"
newline
bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code. SEA - Synchronous External Abort / SPE - Synchronous parity or ECC" "Address/TTBR,Address/Lvl1,Address/Lvl2,Address/Lvl3,Reserved,Translation/Lvl1,Translation/Lvl2,Translation/Lvl3,Reserved,Access flag/Lvl1,Access flag/Lvl2,Access flag/Lvl3,Reserved,Permission/Lvl1,Permission/Lvl2,Permission/Lvl3,SEA/Not ECC/Not on TTBW,SError int,Reserved,Reserved,Reserved,SEA/Not ECC/On TTBW lvl1,SEA/Not ECC/On TTBW lvl2,SEA/Not ECC/On TTBW lvl3,SPE on mem access/Not on TTBW,SError int from parity/ECC err on mem access,Reserved,Reserved,Reserved,SPE on mem access/On TTBW lvl1,SPE on mem access/On TTBW lvl2,SPE on mem access/On TTBW lvl3,Reserved,Alignment fault,Debug (only from Hypervisor mode),Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict abort,Reserved,Reserved,Reserved,Lockdown fault,Unsupp Exclusive acc fault,?..."
endif
elif (((per.l(c15:0x4025))&0xFC080000)==(0x4C080000))
if (((per.l(c15:0x4025))&0x1000000)==(0x1000000))
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hypervisor Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped Coprocessor Usage,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..."
bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Invalid,Valid"
bitfld.long 0x00 20.--23. "COND,The condition code for the trapped instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 19. "CCKNOWNPASS,Trapped instruction" "Unconditional,Conditional"
else
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hypervisor Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped Coprocessor Usage,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..."
bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Invalid,Valid"
bitfld.long 0x00 19. "CCKNOWNPASS,Trapped instruction" "Unconditional,Conditional"
endif
elif (((per.l(c15:0x4025))&0xFC080000)==(0x4C000000))
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hypervisor Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped Coprocessor Usage,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..."
bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit"
newline
bitfld.long 0x00 19. "CCKNOWNPASS,Trapped instruction" "Unconditional,Conditional"
else
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hypervisor Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped Coprocessor Usage,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..."
bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit"
newline
hexmask.long 0x00 0.--24. 1. "ISS,Instruction specific syndrome"
endif
rgroup.long c15:0x4115++0x00
line.long 0x00 "HAIFSR,Hypervisor Auxiliary Instruction Fault Status Register"
group.long c15:0x4206++0x00
line.long 0x00 "HIFAR,Hypervisor Instruction Fault Address Register"
group.long c15:0x4406++0x00
line.long 0x00 "HPFAR,Hypervisor IPA Fault Address Register"
hexmask.long 0x00 4.--31. 0x10 "FIPA[39:12],Bits [39:12] of the faulting intermediate physical address"
tree.open "Hypervisor Memory Attribute Indirection Registers"
if corename()=="CORTEXA75"
if (((per.l(c15:0x0202))&0x80000000)==0x80000000)
group.long c15:0x402A++0x00
line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0"
bitfld.long 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3L,Attribute 3 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2L,Attribute 2 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1L,Attribute 1 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0L,Attribute 0 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
group.long c15:0x412A++0x00
line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1"
bitfld.long 0x00 28.--31. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR7L,Attribute 7 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 20.--23. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR6L,Attribute 6 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 12.--15. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR5L,Attribute 5 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 4.--7. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR4L,Attribute 4 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
else
rgroup.long c15:0x402A++0x00
line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0"
rgroup.long c15:0x412A++0x00
line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1"
endif
elif corename()=="CORTEXA55"
if (((per.l(c15:0x0202))&0x80000000)==0x80000000)
group.long c15:0x402A++0x00
line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0"
bitfld.long 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3L,Attribute 3 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2L,Attribute 2 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1L,Attribute 1 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0L,Attribute 0 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
group.long c15:0x412A++0x00
line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1"
bitfld.long 0x00 28.--31. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR7L,Attribute 7 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 20.--23. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR6L,Attribute 6 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 12.--15. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR5L,Attribute 5 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 4.--7. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR4L,Attribute 4 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
else
rgroup.long c15:0x402A++0x00
line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0"
rgroup.long c15:0x412A++0x00
line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1"
endif
endif
rgroup.long c15:0x403A++0x00
line.long 0x00 "HAMAIR0,Hypervisor Auxiliary Memory Attribute Indirection Register 0"
rgroup.long c15:0x413A++0x00
line.long 0x00 "HAMAIR1,Hypervisor Auxiliary Memory Attribute Indirection Register 1"
tree.end
newline
group.long c15:0x400C++0x00
line.long 0x00 "HVBAR,Hypervisor Vector Base Address Register"
hexmask.long 0x00 5.--31. 0x20 "VBA,Vector Base Address"
tree.end
tree "Cache Control and Configuration"
rgroup.long c15:0x000F++0x00
line.long 0x00 "CPUCFR,CPU Configuration Register"
bitfld.long 0x00 2. "SCU,Indicates whether the SCU is present or not" "Present,?..."
bitfld.long 0x00 0.--1. "ECC,Indicates whether ECC is present or not" "Not present,Present,?..."
group.long c15:0x072F++0x00
line.long 0x00 "CPUPWRCTLR,Power Control Register"
bitfld.long 0x00 10.--12. "SIMD_RET_CTRL,Advanced SIMD and floating-point retention control. Specifies the number of Architectural Timer ticks required before retention entry" "Disabled,2 AT ticks,8 AT ticks,32 AT ticks,64 AT ticks,128 AT ticks,256 AT ticks,512 AT ticks"
bitfld.long 0x00 7.--9. "WFE_RET_CTRL,CPU WFE retention control. Specifies the number of Architectural Timer ticks required before retention entry" "Disabled,2 AT ticks,8 AT ticks,32 AT ticks,64 AT ticks,128 AT ticks,256 AT ticks,512 AT ticks"
bitfld.long 0x00 4.--6. "WFI_RET_CTRL,CPU WFI retention control. Specifies the number of Architectural Timer ticks required before retention entry" "Disabled,2 AT ticks,8 AT ticks,32 AT ticks,64 AT ticks,128 AT ticks,256 AT ticks,512 AT ticks"
newline
bitfld.long 0x00 0. "CORE_PWRDN_EN,Indicates to the power controller if the CPU wants to power down when it enters WFI state" "Not requested,Requested"
rgroup.long c15:0x0100++0x00
line.long 0x00 "CTR,Cache Type Register"
bitfld.long 0x00 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
bitfld.long 0x00 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
bitfld.long 0x00 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
newline
bitfld.long 0x00 14.--15. "L1IP,Instruction cache policy" "Reserved,Reserved,VIPT,?..."
bitfld.long 0x00 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
if (((per.l(c15:0x2000))&0x0E)==0x00)
group.long c15:0x2000++0x00
line.long 0x00 "CSSELR,Cache Size Selection Register"
bitfld.long 0x00 1.--3. "LEVEL,Cache level of required cache" "Level 1,Level 2,Level 3,?..."
bitfld.long 0x00 0. "IND,Instruction/Not Data" "Data,Instruction"
else
group.long c15:0x2000++0x00
line.long 0x00 "CSSELR,Cache Size Selection Register"
bitfld.long 0x00 1.--3. "LEVEL,Cache level of required cache" "Level 1,Level 2,Level 3,?..."
bitfld.long 0x00 0. "IND,Instruction/Not Data" "Unified,?..."
endif
rgroup.long c15:0x1000++0x00
line.long 0x00 "CCSIDR,Cache size ID Register"
bitfld.long 0x00 31. "WT,Indicates whether the selected cache level supports Write-Through" "Not Supported,?..."
bitfld.long 0x00 30. "WB,Indicates whether the selected cache level supports Write-Back" "Not Supported,Supported"
bitfld.long 0x00 29. "RA,Indicates whether the selected cache level supports read-allocation" "Not Supported,Supported"
newline
bitfld.long 0x00 28. "WA,Indicates whether the selected cache level supports write-allocation" "Not Supported,Supported"
hexmask.long.word 0x00 13.--27. 1. 1. "SETS,Number of Sets"
hexmask.long.word 0x00 3.--12. 1. 1. "ASSOC,Associativity"
newline
bitfld.long 0x00 0.--2. "LSIZE,Line Size" "Reserved,Reserved,64 bytes,?..."
if corename()=="CORTEXA75"
rgroup.long c15:0x1100++0x00
line.long 0x00 "CLIDR,Cache Level ID Register"
bitfld.long 0x00 30.--31. "ICB,Inner cache boundary" "Reserved,Reserved,L2 highest,L3 highest"
bitfld.long 0x00 27.--29. "LOUU,Level of Unification Uniprocessor" "Not required,?..."
bitfld.long 0x00 24.--26. "LOC,Level of Coherency" "Reserved,Reserved,No L3 cache,L3 cache,?..."
newline
bitfld.long 0x00 21.--23. "LOUIS,Level of Unification Inner Shareable" "Not required,?..."
bitfld.long 0x00 6.--8. "CTYPE3,Cache type for levels 3" "No cache,Reserved,Reserved,Reserved,L3 cache,?..."
bitfld.long 0x00 3.--5. "CTYPE2,Cache type for levels 2" "Reserved,Reserved,Reserved,Reserved,Unified,?..."
newline
bitfld.long 0x00 0.--2. "CTYPE1,Cache type for levels 1" "Reserved,Reserved,Reserved,Separate I/D,?..."
elif corename()=="CORTEXA55"
rgroup.long c15:0x1100++0x00
line.long 0x00 "CLIDR,Cache Level ID Register"
bitfld.long 0x00 30.--31. "ICB,Inner cache boundary" "Reserved,Reserved,L2 highest,L3 highest"
bitfld.long 0x00 27.--29. "LOUU,Level of Unification Uniprocessor" "Not required,?..."
bitfld.long 0x00 24.--26. "LOC,Level of Coherency" "Reserved,No cache,L2 or L3 cache,L2 and L3 cache,?..."
newline
bitfld.long 0x00 21.--23. "LOUIS,Level of Unification Inner Shareable" "Not required,?..."
bitfld.long 0x00 6.--8. "CTYPE3,Cache type for levels 3" "L2 or L3 cache,Reserved,Reserved,Reserved,L2 and L3 cache,?..."
bitfld.long 0x00 3.--5. "CTYPE2,Cache type for levels 2" "No cache,Reserved,Reserved,Reserved,Unified,?..."
newline
bitfld.long 0x00 0.--2. "CTYPE1,Cache type for levels 1" "Reserved,Reserved,Reserved,Separate I/D,?..."
endif
tree "Level 1 memory system"
rgroup.long c15:0x600F++0x00
line.long 0x00 "CDBGDR0,Data Register 0"
rgroup.long c15:0x610F++0x00
line.long 0x00 "CDBGDR1,Data Register 1"
rgroup.long c15:0x620F++0x00
line.long 0x00 "CDBGDR2,Data Register 2"
wgroup.long c15:0x602F++0x00
line.long 0x00 "CDBGDCT,Data Cache Tag Read Operation Register"
wgroup.long c15:0x612F++0x00
line.long 0x00 "CDBGICT,Instruction Cache Tag Read Operation Register"
wgroup.long c15:0x622F++0x00
line.long 0x00 "CDBGTT,TLB Tag Read Operation Register"
wgroup.long c15:0x604F++0x00
line.long 0x00 "CDBGDCD,Data Cache Data Read Operation Register"
wgroup.long c15:0x614F++0x00
line.long 0x00 "CDBGICD,Instruction Cache Data Read Operation Register"
wgroup.long c15:0x624F++0x00
line.long 0x00 "CDBGTD,TLB Data Read Operation Register"
tree.end
tree.end
tree "System Performance Monitor"
group.long c15:0x00C9++0x00
line.long 0x00 "PMCR,Performance Monitors Control Register"
hexmask.long.byte 0x00 24.--31. 1. "IMP,Implementer code"
hexmask.long.byte 0x00 16.--23. 1. "IDCODE,Identification code"
bitfld.long 0x00 11.--15. "N,Number of counters implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 6. "LC,Long cycle counter enable" "Disabled,Enabled"
newline
bitfld.long 0x00 5. "DP,Disable CCNT when prohibited" "No,Yes"
bitfld.long 0x00 4. "X,Export Enable" "Disabled,Enabled"
bitfld.long 0x00 3. "D,Clock Divider" "Every cycle,64th cycle"
bitfld.long 0x00 2. "C,Clock Counter Reset" "No reset,Reset"
newline
bitfld.long 0x00 1. "P,Performance Counter Reset" "No reset,Reset"
bitfld.long 0x00 0. "E,All Counters Enable" "Disabled,Enabled"
group.long c15:0x01C9++0x00
line.long 0x00 "PMCNTENSET,Performance Monitors Count Enable Set Register"
bitfld.long 0x00 31. "C,PMCCNTR Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 5. "P5,Event counter PMN 5 enable bit" "Disabled,Enabled"
bitfld.long 0x00 4. "P4,Event counter PMN 4 enable bit" "Disabled,Enabled"
newline
bitfld.long 0x00 3. "P3,Event counter PMN 3 enable bit" "Disabled,Enabled"
bitfld.long 0x00 2. "P2,Event counter PMN 2 enable bit" "Disabled,Enabled"
bitfld.long 0x00 1. "P1,Event counter PMN 1 enable bit" "Disabled,Enabled"
newline
bitfld.long 0x00 0. "P0,Event counter PMN 0 enable bit" "Disabled,Enabled"
group.long c15:0x02C9++0x00
line.long 0x00 "PMCNTENCLR,Performance Monitors Count Enable Clear Register"
bitfld.long 0x00 31. "C,PMCCNTR Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 5. "P5,Event counter PMN 5 enable bit" "Disabled,Enabled"
bitfld.long 0x00 4. "P4,Event counter PMN 4 enable bit" "Disabled,Enabled"
newline
bitfld.long 0x00 3. "P3,Event counter PMN 3 enable bit" "Disabled,Enabled"
bitfld.long 0x00 2. "P2,Event counter PMN 2 enable bit" "Disabled,Enabled"
bitfld.long 0x00 1. "P1,Event counter PMN 1 enable bit" "Disabled,Enabled"
newline
bitfld.long 0x00 0. "P0,Event counter PMN 0 enable bit" "Disabled,Enabled"
group.long c15:0x03C9++0x00
line.long 0x00 "PMOVSR,Performance Monitors Overflow Status Flags Register"
eventfld.long 0x00 31. "C,PMCCNTR overflow" "No overflow,Overflow"
eventfld.long 0x00 5. "P5,PMN5 overflow" "No overflow,Overflow"
eventfld.long 0x00 4. "P4,PMN4 overflow" "No overflow,Overflow"
newline
eventfld.long 0x00 3. "P3,PMN3 overflow" "No overflow,Overflow"
eventfld.long 0x00 2. "P2,PMN2 overflow" "No overflow,Overflow"
eventfld.long 0x00 1. "P1,PMN1 overflow" "No overflow,Overflow"
newline
eventfld.long 0x00 0. "P0,PMN0 overflow" "No overflow,Overflow"
wgroup.long c15:0x04C9++0x00
line.long 0x00 "PMSWINC,Performance Monitors Software Increment Register"
bitfld.long 0x00 5. "P5,PMN5 software increment" "Disabled,Enabled"
bitfld.long 0x00 4. "P4,PMN4 software increment" "Disabled,Enabled"
bitfld.long 0x00 3. "P3,PMN3 software increment" "Disabled,Enabled"
newline
bitfld.long 0x00 2. "P2,PMN2 software increment" "Disabled,Enabled"
bitfld.long 0x00 1. "P1,PMN1 software increment" "Disabled,Enabled"
bitfld.long 0x00 0. "P0,PMN0 software increment" "Disabled,Enabled"
group.long c15:0x05C9++0x00
line.long 0x00 "PMSELR,Performance Monitors Event Counter Selection Register"
bitfld.long 0x00 0.--4. "SEL,Current event counter select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.open "Common Event Identification Registers"
rgroup.long c15:0x06C9++0x00
line.long 0x00 "PMCEID0,Performance Monitors Common Event Identification Register 0"
bitfld.long 0x00 31. "L1D_CACHE_ALLOCATE,Level 1 data cache allocate" "Not implemented,Implemented"
bitfld.long 0x00 30. "CHAIN,Chain" "Not implemented,Implemented"
bitfld.long 0x00 29. "BUS_CYCLES,Bus cycle" "Not implemented,Implemented"
newline
bitfld.long 0x00 28. "TTBR_WRITE_RETIRED,TTBR write retired" "Not implemented,Implemented"
bitfld.long 0x00 27. "INST_SPEC,Instruction speculatively executed" "Not implemented,Implemented"
bitfld.long 0x00 26. "MEMORY_ERROR,Local memory error" "Not implemented,Implemented"
newline
bitfld.long 0x00 25. "BUS_ACCESS,Bus access" "Not implemented,Implemented"
bitfld.long 0x00 24. "L2D_CACHE_WB,Level 2 data cache write-back" "Not implemented,Implemented"
bitfld.long 0x00 23. "L2D_CACHE_REFILL,Level 2 data cache refill" "Not implemented,Implemented"
newline
bitfld.long 0x00 22. "L2D_CACHE,Level 2 data cache access" "Not implemented,Implemented"
bitfld.long 0x00 21. "L1D_CACHE_WB,Level 1 data cache write-back" "Not implemented,Implemented"
bitfld.long 0x00 20. "L1I_CACHE,Level 1 instruction cache access" "Not implemented,Implemented"
newline
bitfld.long 0x00 19. "MEM_ACCESS,Data memory access" "Not implemented,Implemented"
bitfld.long 0x00 18. "BR_PRED,Predictable branch speculatively executed" "Not implemented,Implemented"
bitfld.long 0x00 17. "CPU_CYCLES,CPU Cycle" "Not implemented,Implemented"
newline
bitfld.long 0x00 16. "BR_MIS_PRED,Mispredicted or not predicted branch speculatively executed" "Not implemented,Implemented"
bitfld.long 0x00 15. "UNALIGNED_LDST_RETIRED,UNALIGNED_LDST_RETIRED" "Not implemented,Implemented"
bitfld.long 0x00 14. "BR_RETURN_RETIRED,Instruction architecturally executed condition check pass procedure return" "Not implemented,Implemented"
newline
bitfld.long 0x00 13. "BR_IMMED_RETIRED,Instruction architecturally executed immediate branch" "Not implemented,Implemented"
bitfld.long 0x00 12. "PC_WRITE_RETIRED,Instruction architecturally executed condition check pass software change of the PC" "Not implemented,Implemented"
bitfld.long 0x00 11. "CID_WRITE_RETIRED,Instruction architecturally executed condition check pass write to CONTEXTIDR" "Not implemented,Implemented"
newline
bitfld.long 0x00 10. "EXC_RETURN,Instruction architecturally executed condition check pass exception return" "Not implemented,Implemented"
bitfld.long 0x00 9. "EXC_TAKEN,Exception taken" "Not implemented,Implemented"
bitfld.long 0x00 8. "INST_RETIRED,Instruction architecturally executed" "Not implemented,Implemented"
newline
bitfld.long 0x00 7. "ST_RETIRED,Instruction architecturally executed condition check pass store" "Not implemented,Implemented"
bitfld.long 0x00 6. "LD_RETIRED,Instruction architecturally executed condition check pass load" "Not implemented,Implemented"
bitfld.long 0x00 5. "L1D_TLB_REFILL,Level 1 data TLB refill" "Not implemented,Implemented"
newline
bitfld.long 0x00 4. "L1D_CACHE,Level 1 data cache access" "Not implemented,Implemented"
bitfld.long 0x00 3. "L1D_CACHE_REFILL,Level 1 data cache refill" "Not implemented,Implemented"
bitfld.long 0x00 2. "L1I_TLB_REFILL,Level 1 instruction TLB refill" "Not implemented,Implemented"
newline
bitfld.long 0x00 1. "L1I_CACHE_REFILL,Level 1 instruction cache refill" "Not implemented,Implemented"
bitfld.long 0x00 0. "SW_INCR,Instruction architecturally executed condition check pass software increment" "Not implemented,Implemented"
if corename()=="CORTEXA75"
rgroup.long c15:0x07C9++0x00
line.long 0x00 "PMCEID1,Performance Monitors Common Event Identification Register 1"
bitfld.long 0x00 24. "REMOTE_ACCESS,Access to another socket in a multi-socket system" "Not implemented,Implemented"
bitfld.long 0x00 23. "LL_CACHE_MISS_RD,Last Level cache miss read" "Not implemented,Implemented"
bitfld.long 0x00 22. "LL_CACHE_RD,Last Level cache access read" "Not implemented,Implemented"
newline
bitfld.long 0x00 21. "ITLB_WALK,Access to instruction TLB that caused a page table walk" "Not implemented,Implemented"
bitfld.long 0x00 20. "DTLB_WALK,Access to data TLB that caused a page table walk" "Not implemented,Implemented"
bitfld.long 0x00 16. "L2I_TLB,Attributable Level 2 instruction TLB access" "Not implemented,Implemented"
newline
bitfld.long 0x00 15. "L2D_TLB,Attributable Level 2 data or unified TLB access" "Not implemented,Implemented"
bitfld.long 0x00 13. "L2D_TLB_REFILL,Attributable Level 2 data or unified TLB refill" "Not implemented,Implemented"
bitfld.long 0x00 11. "L3D_CACHE,Attributable Level 3 data or unified cache access" "Not implemented,Implemented"
newline
bitfld.long 0x00 10. "L3D_CACHE_REFILL,Attributable Level 3 data or unified cache refill" "Not implemented,Implemented"
bitfld.long 0x00 9. "L3D_CACHE_ALLOCATE,Attributable Level 3 data or unified cache allocation without refill" "Not implemented,Implemented"
bitfld.long 0x00 6. "L1I_TLB,Level 1 instruction TLB access" "Not implemented,Implemented"
newline
bitfld.long 0x00 5. "L1D_TLB,Level 1 data or unified TLB access" "Not implemented,Implemented"
bitfld.long 0x00 4. "STALL_BACKEND,No operation issued due to backend" "Not implemented,Implemented"
bitfld.long 0x00 3. "STALL_FRONTEND,No operation issued due to the frontend" "Not implemented,Implemented"
newline
bitfld.long 0x00 1. "BR_RETIRED,Instruction architecturally executed branch" "Not implemented,Implemented"
bitfld.long 0x00 0. "L2D_CACHE_ALLOCATE,Level 2 data cache allocate" "Not implemented,Implemented"
elif corename()=="CORTEXA55"
rgroup.long c15:0x07C9++0x00
line.long 0x00 "PMCEID1,Performance Monitors Common Event Identification Register 1"
bitfld.long 0x00 24. "REMOTE_ACCESS,Access to another socket in a multi-socket system" "Not implemented,Implemented"
bitfld.long 0x00 23. "LL_CACHE_MISS_RD,Last Level cache miss read" "Not implemented,Implemented"
bitfld.long 0x00 22. "LL_CACHE_RD,Last Level cache access read" "Not implemented,Implemented"
newline
bitfld.long 0x00 21. "ITLB_WALK,Access to instruction TLB that caused a page table walk" "Not implemented,Implemented"
bitfld.long 0x00 20. "DTLB_WALK,Access to data TLB that caused a page table walk" "Not implemented,Implemented"
bitfld.long 0x00 16. "L2I_TLB,Attributable Level 2 instruction TLB access" "Not implemented,Implemented"
newline
bitfld.long 0x00 15. "L2D_TLB,Attributable Level 2 data or unified TLB access" "Not implemented,Implemented"
bitfld.long 0x00 14. "L2I_TLB_REFILL,Attributable Level 2 instruction TLB refill" "Not implemented,Implemented"
bitfld.long 0x00 13. "L2D_TLB_REFILL,Attributable Level 2 data or unified TLB refill" "Not implemented,Implemented"
newline
bitfld.long 0x00 12. "L3D_CACHE_WB,Attributable Level 3 data or unified cache write-back" "Not implemented,Implemented"
bitfld.long 0x00 11. "L3D_CACHE,Attributable Level 3 data or unified cache access" "Not implemented,Implemented"
bitfld.long 0x00 10. "L3D_CACHE_REFILL,Attributable Level 3 data or unified cache refill" "Not implemented,Implemented"
newline
bitfld.long 0x00 9. "L3D_CACHE_ALLOCATE,Attributable Level 3 data or unified cache allocation without refill" "Not implemented,Implemented"
bitfld.long 0x00 8. "L2I_CACHE_REFILL,Attributable Level 2 instruction cache refill" "Not implemented,Implemented"
bitfld.long 0x00 7. "L2I_CACHE,Attributable Level 2 instruction cache access" "Not implemented,Implemented"
newline
bitfld.long 0x00 6. "L1I_TLB,Level 1 instruction TLB access" "Not implemented,Implemented"
bitfld.long 0x00 5. "L1D_TLB,Level 1 data or unified TLB access" "Not implemented,Implemented"
bitfld.long 0x00 4. "STALL_BACKEND,No operation issued due to backend" "Not implemented,Implemented"
newline
bitfld.long 0x00 3. "STALL_FRONTEND,No operation issued due to the frontend" "Not implemented,Implemented"
bitfld.long 0x00 2. "BR_MIS_PRED_RETIRED,Instruction architecturally executed mispredicted branch" "Not implemented,Implemented"
bitfld.long 0x00 1. "BR_RETIRED,Instruction architecturally executed branch" "Not implemented,Implemented"
newline
bitfld.long 0x00 0. "L2D_CACHE_ALLOCATE,Level 2 data cache allocate" "Not implemented,Implemented"
endif
rgroup.long c15:0x04E9++0x00
line.long 0x00 "PMCEID2,Performance Monitors Common Event Identification Register 2"
rgroup.long c15:0x05E9++0x00
line.long 0x00 "PMCEID3,Performance Monitors Common Event Identification Register 3"
tree.end
newline
group.long c15:0x00D9++0x00
line.long 0x00 "PMCCNTR[31:0],Performance Monitors Cycle Counter (32bit access)"
group.quad c15:0x13090++0x01
line.quad 0x00 "PMCCNTR[63:0],Performance Monitors Cycle Counter (64bit access)"
if (((per.l(c15:0X05C9))&0x1F)==0x1F)
group.long c15:0x01D9++0x00
line.long 0x00 "PMXEVTYPER,Performance Monitors Selected Event Type and Filter Register - PMCCFILTR"
bitfld.long 0x00 31. "P,Privileged modes filtering" "Disabled,Enabled"
bitfld.long 0x00 30. "U,User modes filtering" "Disabled,Enabled"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering" "Disabled,Enabled"
newline
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering" "Disabled,Enabled"
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering" "Disabled,Enabled"
elif (((per.l(c15:0X00E9))&0x1)==0x1)
group.long c15:0x01D9++0x00
line.long 0x00 "PMXEVTYPER,Performance Monitors Selected Event Type and Filter Register - PMEVTYPER"
bitfld.long 0x00 31. "P,Privileged modes filtering" "Disabled,Enabled"
bitfld.long 0x00 30. "U,User modes filtering" "Disabled,Enabled"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering" "Disabled,Enabled"
newline
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering" "Disabled,Enabled"
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering" "Disabled,Enabled"
bitfld.long 0x00 26. "M,Secure EL3 filtering" "Disabled,Enabled"
newline
hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event number"
else
rgroup.long c15:0x01D9++0x00
line.long 0x00 "PMXEVTYPER,Performance Monitors Selected Event Type and Filter Register"
endif
group.long c15:0x02D9++0x00
line.long 0x00 "PMXEVCNTR,Performance Monitors Selected Event Counter Register"
group.long c15:0x00E9++0x00
line.long 0x00 "PMUSERENR,Performance Monitors User Enable Register"
bitfld.long 0x00 3. "ER,Event counter read enable" "Disabled,Enabled"
bitfld.long 0x00 2. "CR,Cycle counter read enable" "Disabled,Enabled"
newline
bitfld.long 0x00 1. "SW,Software Increment write enable" "Disabled,Enabled"
bitfld.long 0x00 0. "EN,User enable" "Disabled,Enabled"
group.long c15:0x01E9++0x00
line.long 0x00 "PMINTENSET,Performance Monitors Interrupt Enable Set Register"
bitfld.long 0x00 31. "C,PMCCNTR Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 5. "P5,PMCNT5 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 4. "P4,PMCNT4 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 3. "P3,PMCNT3 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 2. "P2,PMCNT2 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 1. "P1,PMCNT1 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 0. "P0,PMCNT0 Overflow Interrupt Enable" "Disabled,Enabled"
group.long c15:0x02E9++0x00
line.long 0x00 "PMINTENCLR,Performance Monitors Interrupt Enable Clear Register"
bitfld.long 0x00 31. "C,PMCCNTR Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 5. "P5,PMCNT5 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 4. "P4,PMCNT4 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 3. "P3,PMCNT3 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 2. "P2,PMCNT2 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 1. "P1,PMCNT1 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 0. "P0,PMCNT0 Overflow Interrupt Enable" "Disabled,Enabled"
group.long c15:0x03E9++0x00
line.long 0x00 "PMOVSSET,Performance Monitors Overflow Flag Status Set Register"
bitfld.long 0x00 31. "C,PMCCNTR overflow" "No overflow,Overflow"
bitfld.long 0x00 5. "P5,PMEVCNTR5 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 4. "P4,PMEVCNTR4 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 3. "P3,PMEVCNTR3 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 2. "P2,PMEVCNTR2 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 1. "P1,PMEVCNTR1 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 0. "P0,PMEVCNTR0 Overflow Interrupt Enable" "Disabled,Enabled"
group.long c15:0x8E++0x00
line.long 0x00 "PMEVCNTR0,Performance Monitors Event Count Register 0"
group.long c15:(0x8E+0x0040)++0x00
line.long 0x00 "PMEVTYPER0,Performance Monitors Event Type Register 0"
group.long c15:0x18E++0x00
line.long 0x00 "PMEVCNTR1,Performance Monitors Event Count Register 1"
group.long c15:(0x18E+0x0040)++0x00
line.long 0x00 "PMEVTYPER1,Performance Monitors Event Type Register 1"
group.long c15:0x28E++0x00
line.long 0x00 "PMEVCNTR2,Performance Monitors Event Count Register 2"
group.long c15:(0x28E+0x0040)++0x00
line.long 0x00 "PMEVTYPER2,Performance Monitors Event Type Register 2"
group.long c15:0x38E++0x00
line.long 0x00 "PMEVCNTR3,Performance Monitors Event Count Register 3"
group.long c15:(0x38E+0x0040)++0x00
line.long 0x00 "PMEVTYPER3,Performance Monitors Event Type Register 3"
group.long c15:0x48E++0x00
line.long 0x00 "PMEVCNTR4,Performance Monitors Event Count Register 4"
group.long c15:(0x48E+0x0040)++0x00
line.long 0x00 "PMEVTYPER4,Performance Monitors Event Type Register 4"
group.long c15:0x58E++0x00
line.long 0x00 "PMEVCNTR5,Performance Monitors Event Count Register 5"
group.long c15:(0x58E+0x0040)++0x00
line.long 0x00 "PMEVTYPER5,Performance Monitors Event Type Register 5"
group.long c15:0x07FE++0x00
line.long 0x00 "PMCCFILTR,Performance Monitors Cycle Count Filter Register"
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Disabled,Enabled"
bitfld.long 0x00 30. "U,EL0 filtering bit" "Disabled,Enabled"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Disabled,Enabled"
newline
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
tree.end
tree "System Timer Registers"
group.long c15:0x000E++0x00
line.long 0x00 "CNTFRQ,Counter Frequency Register"
group.quad c15:0x100E0++0x01
line.quad 0x00 "CNTPCT,Counter Physical Count Register"
rgroup.quad c15:0x110E0++0x01
line.quad 0x00 "CNTVCT,Counter Virtual Count Register"
group.quad c15:0x140E0++0x01
line.quad 0x00 "CNTVOFF,Counter Virtual Offset Register"
group.long c15:0x001E++0x00
line.long 0x00 "CNTKCTL,Timer PL1 Control Register"
bitfld.long 0x00 9. "EL0PTEN,Controls whether the physical timer Registers are accessible from EL0 mode" "Disabled,Enabled"
bitfld.long 0x00 8. "EL0VTEN,Controls whether the virtual timer Registers are accessible from EL0 mode" "Disabled,Enabled"
bitfld.long 0x00 4.--7. "EVNTI,Selects which bit of CNTVCT is the trigger for the event stream generated from the virtual counter, when that stream is enabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit" "0 to 1,1 to 0"
newline
bitfld.long 0x00 2. "EVNTEN,Enables the generation of an event stream from the virtual counter" "Disabled,Enabled"
bitfld.long 0x00 1. "EL0VCTEN,Controls whether the virtual counter, CNTVCT, and the frequency Register CNTFRQ, are accessible from EL0 mode" "Disabled,Enabled"
bitfld.long 0x00 0. "EL0PCTEN,Controls whether the physical counter, CNTPCT, and the frequency Register CNTFRQ, are accessible from EL0 mode" "Disabled,Enabled"
group.long c15:0x401E++0x00
line.long 0x00 "CNTHCTL,Counter Non-secure PL2 Control Register"
bitfld.long 0x00 4.--7. "EVNTI,Selects which bit of CNTPCT is the trigger for the event stream generated from the physical counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 3. "EVNTDIR,Controls which transition of the CNTPCT trigger bit, defined by EVNTI" "0 to 1,1 to 0"
bitfld.long 0x00 2. "EVNTEN,Enables the generation of an event stream from the physical counter" "Disabled,Enabled"
bitfld.long 0x00 1. "EL1PCEN,Controls whether the Non-secure copies of the physical timer Registers are accessible from Non-secure EL1 and EL0 modes" "Not accessible,Accessible"
newline
bitfld.long 0x00 0. "EL1PCTEN,Controls whether the physical counter, CNTPCT, is accessible from Non-secure EL1 and EL0 modes" "Not accessible,Accessible"
group.long c15:0x002E++0x00
line.long 0x00 "CNTP_TVAL,Counter EL1 Physical Compare Value Register"
group.long c15:0x012E++0x00
line.long 0x00 "CNTP_CTL,Counter EL1 Physical Timer Control Register"
rbitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt"
bitfld.long 0x00 1. "IMASK,Timer interrupt mask" "Not masked,Masked"
bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
group.quad c15:0x120E0++0x01
line.quad 0x00 "CNTP_CVAL,Counter EL1 Physical Compare Value Register"
group.long c15:0x003E++0x00
line.long 0x00 "CNTV_TVAL,Counter EL1 Virtual Timer Value Register"
group.long c15:0x013E++0x00
line.long 0x00 "CNTV_CTL,Counter EL1 Virtual Timer Control Register"
rbitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt"
bitfld.long 0x00 1. "IMASK,Timer interrupt mask" "Not masked,Masked"
bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
group.quad c15:0x130E0++0x01
line.quad 0x00 "CNTV_CVAL,Counter EL1 Virtual Compare Value Register"
group.long c15:0x402E++0x00
line.long 0x00 "CNTHP_TVAL,Counter Non-secure EL2 Physical Timer Value Register"
group.long c15:0x412E++0x00
line.long 0x00 "CNTHP_CTL,Counter Non-secure EL2 Physical Timer Control Register"
rbitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt"
bitfld.long 0x00 1. "IMASK,Timer interrupt mask" "Not masked,Masked"
bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
group.quad c15:0x160E0++0x01
line.quad 0x00 "CNTHP_CVAL,Counter Non-secure EL2 Physical Compare Value Register"
tree.end
tree "Generic Interrupt Controller System Registers"
tree "AArch32 Physical GIC CPU Interface System Registers"
tree.open "Interrupt Controller Active Priorities Registers"
group.long c15:0x048C++0x00
line.long 0x00 "ICC_AP0R0,Active Priorities Group 0 Register 0"
bitfld.long 0x00 31. "P31,Group 0 interrupt active with priority level 31" "No interrupt,Interrupt"
bitfld.long 0x00 30. "P30,Group 0 interrupt active with priority level 30" "No interrupt,Interrupt"
bitfld.long 0x00 29. "P29,Group 0 interrupt active with priority level 29" "No interrupt,Interrupt"
newline
bitfld.long 0x00 28. "P28,Group 0 interrupt active with priority level 28" "No interrupt,Interrupt"
bitfld.long 0x00 27. "P27,Group 0 interrupt active with priority level 27" "No interrupt,Interrupt"
bitfld.long 0x00 26. "P26,Group 0 interrupt active with priority level 26" "No interrupt,Interrupt"
newline
bitfld.long 0x00 25. "P25,Group 0 interrupt active with priority level 25" "No interrupt,Interrupt"
bitfld.long 0x00 24. "P24,Group 0 interrupt active with priority level 24" "No interrupt,Interrupt"
bitfld.long 0x00 23. "P23,Group 0 interrupt active with priority level 23" "No interrupt,Interrupt"
newline
bitfld.long 0x00 22. "P22,Group 0 interrupt active with priority level 22" "No interrupt,Interrupt"
bitfld.long 0x00 21. "P21,Group 0 interrupt active with priority level 21" "No interrupt,Interrupt"
bitfld.long 0x00 20. "P20,Group 0 interrupt active with priority level 20" "No interrupt,Interrupt"
newline
bitfld.long 0x00 19. "P19,Group 0 interrupt active with priority level 19" "No interrupt,Interrupt"
bitfld.long 0x00 18. "P18,Group 0 interrupt active with priority level 18" "No interrupt,Interrupt"
bitfld.long 0x00 17. "P17,Group 0 interrupt active with priority level 17" "No interrupt,Interrupt"
newline
bitfld.long 0x00 16. "P16,Group 0 interrupt active with priority level 16" "No interrupt,Interrupt"
bitfld.long 0x00 15. "P15,Group 0 interrupt active with priority level 15" "No interrupt,Interrupt"
bitfld.long 0x00 14. "P14,Group 0 interrupt active with priority level 14" "No interrupt,Interrupt"
newline
bitfld.long 0x00 13. "P13,Group 0 interrupt active with priority level 13" "No interrupt,Interrupt"
bitfld.long 0x00 12. "P12,Group 0 interrupt active with priority level 12" "No interrupt,Interrupt"
bitfld.long 0x00 11. "P11,Group 0 interrupt active with priority level 11" "No interrupt,Interrupt"
newline
bitfld.long 0x00 10. "P10,Group 0 interrupt active with priority level 10" "No interrupt,Interrupt"
bitfld.long 0x00 9. "P9,Group 0 interrupt active with priority level 9" "No interrupt,Interrupt"
bitfld.long 0x00 8. "P8,Group 0 interrupt active with priority level 8" "No interrupt,Interrupt"
newline
bitfld.long 0x00 7. "P7,Group 0 interrupt active with priority level 7" "No interrupt,Interrupt"
bitfld.long 0x00 6. "P6,Group 0 interrupt active with priority level 6" "No interrupt,Interrupt"
bitfld.long 0x00 5. "P5,Group 0 interrupt active with priority level 5" "No interrupt,Interrupt"
newline
bitfld.long 0x00 4. "P4,Group 0 interrupt active with priority level 4" "No interrupt,Interrupt"
bitfld.long 0x00 3. "P3,Group 0 interrupt active with priority level 3" "No interrupt,Interrupt"
bitfld.long 0x00 2. "P2,Group 0 interrupt active with priority level 2" "No interrupt,Interrupt"
newline
bitfld.long 0x00 1. "P1,Group 0 interrupt active with priority level 1" "No interrupt,Interrupt"
bitfld.long 0x00 0. "P0,Group 0 interrupt active with priority level 0" "No interrupt,Interrupt"
group.long c15:0x009C++0x00
line.long 0x00 "ICC_AP1R0,Active Priorities Group 1 Register 0"
bitfld.long 0x00 31. "P31,Group 1 interrupt active with priority level 31" "No interrupt,Interrupt"
bitfld.long 0x00 30. "P30,Group 1 interrupt active with priority level 30" "No interrupt,Interrupt"
bitfld.long 0x00 29. "P29,Group 1 interrupt active with priority level 29" "No interrupt,Interrupt"
newline
bitfld.long 0x00 28. "P28,Group 1 interrupt active with priority level 28" "No interrupt,Interrupt"
bitfld.long 0x00 27. "P27,Group 1 interrupt active with priority level 27" "No interrupt,Interrupt"
bitfld.long 0x00 26. "P26,Group 1 interrupt active with priority level 26" "No interrupt,Interrupt"
newline
bitfld.long 0x00 25. "P25,Group 1 interrupt active with priority level 25" "No interrupt,Interrupt"
bitfld.long 0x00 24. "P24,Group 1 interrupt active with priority level 24" "No interrupt,Interrupt"
bitfld.long 0x00 23. "P23,Group 1 interrupt active with priority level 23" "No interrupt,Interrupt"
newline
bitfld.long 0x00 22. "P22,Group 1 interrupt active with priority level 22" "No interrupt,Interrupt"
bitfld.long 0x00 21. "P21,Group 1 interrupt active with priority level 21" "No interrupt,Interrupt"
bitfld.long 0x00 20. "P20,Group 1 interrupt active with priority level 20" "No interrupt,Interrupt"
newline
bitfld.long 0x00 19. "P19,Group 1 interrupt active with priority level 19" "No interrupt,Interrupt"
bitfld.long 0x00 18. "P18,Group 1 interrupt active with priority level 18" "No interrupt,Interrupt"
bitfld.long 0x00 17. "P17,Group 1 interrupt active with priority level 17" "No interrupt,Interrupt"
newline
bitfld.long 0x00 16. "P16,Group 1 interrupt active with priority level 16" "No interrupt,Interrupt"
bitfld.long 0x00 15. "P15,Group 1 interrupt active with priority level 15" "No interrupt,Interrupt"
bitfld.long 0x00 14. "P14,Group 1 interrupt active with priority level 14" "No interrupt,Interrupt"
newline
bitfld.long 0x00 13. "P13,Group 1 interrupt active with priority level 13" "No interrupt,Interrupt"
bitfld.long 0x00 12. "P12,Group 1 interrupt active with priority level 12" "No interrupt,Interrupt"
bitfld.long 0x00 11. "P11,Group 1 interrupt active with priority level 11" "No interrupt,Interrupt"
newline
bitfld.long 0x00 10. "P10,Group 1 interrupt active with priority level 10" "No interrupt,Interrupt"
bitfld.long 0x00 9. "P9,Group 1 interrupt active with priority level 9" "No interrupt,Interrupt"
bitfld.long 0x00 8. "P8,Group 1 interrupt active with priority level 8" "No interrupt,Interrupt"
newline
bitfld.long 0x00 7. "P7,Group 1 interrupt active with priority level 7" "No interrupt,Interrupt"
bitfld.long 0x00 6. "P6,Group 1 interrupt active with priority level 6" "No interrupt,Interrupt"
bitfld.long 0x00 5. "P5,Group 1 interrupt active with priority level 5" "No interrupt,Interrupt"
newline
bitfld.long 0x00 4. "P4,Group 1 interrupt active with priority level 4" "No interrupt,Interrupt"
bitfld.long 0x00 3. "P3,Group 1 interrupt active with priority level 3" "No interrupt,Interrupt"
bitfld.long 0x00 2. "P2,Group 1 interrupt active with priority level 2" "No interrupt,Interrupt"
newline
bitfld.long 0x00 1. "P1,Group 1 interrupt active with priority level 1" "No interrupt,Interrupt"
bitfld.long 0x00 0. "P0,Group 1 interrupt active with priority level 0" "No interrupt,Interrupt"
tree.end
newline
if (((per.l(c15:0x110C0))&0x10000000000)==0x00)
wgroup.quad c15:0x110C0++0x01
line.quad 0x00 "ICC_ASGI1R,Interrupt Controller Alias Software Generated Interrupt Group 1 Register"
hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3"
newline
bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self"
newline
hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2"
bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1"
hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,The set of PEs for which SGI interrupts will be generated"
else
wgroup.quad c15:0x110C0++0x01
line.quad 0x00 "ICC_ASGI1R,Interrupt Controller Alias Software Generated Interrupt Group 1 Register"
newline
bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self"
newline
bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
endif
group.long c15:0x038C++0x00
line.long 0x00 "ICC_BPR0,Binary Point Register 0"
bitfld.long 0x00 0.--2. "BINARYPOINT,Interrupt Priority Field Control And Interrupt Preemption Control" "[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0],No preemption-[7:0]"
group.long c15:0x03CC++0x00
line.long 0x00 "ICC_BPR1,Binary Point Register 1"
bitfld.long 0x00 0.--2. "BINARYPOINT,Interrupt Priority Field Control And Interrupt Preemption Control" ",[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0]"
group.long c15:0x04CC++0x00
line.long 0x00 "ICC_CTLR,Interrupt Control Registers for EL1"
rbitfld.long 0x00 19. "EXTRANGE,Extended INTID range" "Not supported,Supported"
rbitfld.long 0x00 18. "RSS,Range selector support" "0 - 15,0 - 255"
newline
rbitfld.long 0x00 15. "A3V,Affinity 3 Valid" "Reserved,Supported"
rbitfld.long 0x00 14. "SEIS,SEI Support" "Not supported,?..."
rbitfld.long 0x00 11.--13. "IDBITS,Number of physical interrupt identifier bits supported" "16 bits,?..."
newline
rbitfld.long 0x00 8.--10. "PRIBITS,Number of priority bits implemented" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6. "PMHE,Priority Mask Hint Enable" "Disabled,Enabled"
bitfld.long 0x00 1. "EOIMODE,Controls whether a write to an End of Interrupt Register also deactivates the interrupt" "Enabled,Disabled"
newline
bitfld.long 0x00 0. "CBPR,Common Binary Point Register. Controls whether the same Register is used for interrupt pre-emption of both Group 0 and Group 1 interrupt" "Separate Registers,Same Register"
group.long c15:0x64CC++0x00
line.long 0x00 "ICC_MCTLR,Interrupt Control Registers for EL3"
rbitfld.long 0x00 19. "EXTRANGE,Extended INTID range" "Not supported,Supported"
rbitfld.long 0x00 18. "RSS,Range selector support" "0 - 15,0 - 255"
newline
rbitfld.long 0x00 17. "NDS,Disable Security not supported" "Supported,Not supported"
rbitfld.long 0x00 15. "A3V,Affinity 3 Valid" "Reserved,Supported"
rbitfld.long 0x00 14. "SEIS,Indicates whether the CPU interface supports generation of SEIs" "Not supported,?..."
newline
rbitfld.long 0x00 11.--13. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,?..."
rbitfld.long 0x00 8.--10. "PRIBITS,The number of priority bits implemented minus one" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6. "PMHE,Priority Mask Hint Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 4. "EOIMODE_EL1NS,Controls whether a write to an End of Interrupt Register also deactivates the interrupt(Non-secure EL1 and EL2)" "Enabled,Disabled"
bitfld.long 0x00 3. "EOIMODE_EL1S,Controls whether a write to an End of Interrupt Register also deactivates the interrupt(Secure EL1)" "Enabled,Disabled"
bitfld.long 0x00 2. "EOIMODE_EL3,Controls whether a write to an End of Interrupt Register also deactivates the interrupt(EL3)" "Enabled,Disabled"
newline
bitfld.long 0x00 1. "CBPR_EL1NS,Controls whether the same Register is used for interrupt preemption of both Group 0 and Group 1 Non-secure interrupts at EL1" "Separate Registers,Same Register"
bitfld.long 0x00 0. "CBPR_EL1S,Controls whether the same Register is used for interrupt preemption of both Group 0 and Group 1 Secure interrupts in Secure non-Monitor modes" "Separate Registers,Same Register"
wgroup.long c15:0x01BC++0x00
line.long 0x00 "ICC_DIR,Deactivate Interrupt Register"
hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID of the interrupt to be deactivated"
wgroup.long c15:0x018C++0x00
line.long 0x00 "ICC_EOIR0,End Of Interrupt Register 0"
hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID from the corresponding ICC_IAR0 access"
wgroup.long c15:0x01CC++0x00
line.long 0x00 "ICC_EOIR1,End Of Interrupt Register 1"
hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID from the corresponding ICC_IAR1 access."
rgroup.long c15:0x028C++0x00
line.long 0x00 "ICC_HPPIR0,Highest Priority Pending Interrupt Register 0"
hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt"
rgroup.long c15:0x02CC++0x00
line.long 0x00 "ICC_HPPIR1,Highest Priority Pending Interrupt Register 1"
hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt"
rgroup.long c15:0x008C++0x00
line.long 0x00 "ICC_IAR0,Interrupt Acknowledge Register 0"
rgroup.long c15:0x00CC++0x00
line.long 0x00 "ICC_IAR1,Interrupt Acknowledge Register 1"
group.long c15:0x06CC++0x00
line.long 0x00 "ICC_IGRPEN0,Interrupt Group Enable Register 0"
bitfld.long 0x00 0. "ENABLE,Enables Group 0 interrupts" "Disabled,Enabled"
group.long c15:0x07CC++0x00
line.long 0x00 "ICC_IGRPEN1,Interrupt Group Enable Register 1"
bitfld.long 0x00 0. "ENABLE,Enables Group 0 interrupts" "Disabled,Enabled"
group.long c15:0x0064++0x00
line.long 0x00 "ICC_PMR,Priority Mask Register"
hexmask.long.byte 0x00 0.--7. 1. "PRIORITY,Priority mask level for the CPU interface"
rgroup.long c15:0x03BC++0x00
line.long 0x00 "ICC_RPR,Running Priority Register"
hexmask.long.byte 0x00 0.--7. 1. "PRIORITY,Current running priority on the CPU interface"
if (((per.q(c15:0x120C0))&0x10000000000)==0x00)
group.quad c15:0x120C0++0x01
line.quad 0x00 "ICC_SGI0R,Interrupt Controller Software Generated Interrupt Group 0 Register"
hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3"
newline
bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self"
hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2"
newline
bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1"
hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,The set of PEs for which SGI interrupts will be generated."
else
group.quad c15:0x120C0++0x01
line.quad 0x00 "ICC_SGI0R,Interrupt Controller Software Generated Interrupt Group 0 Register"
bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self"
bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
endif
group.long c15:0x05CC++0x00
line.long 0x00 "ICC_SRE,System Register Enable Register for EL1"
bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "No,Yes"
bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "No,Yes"
rbitfld.long 0x00 0. "SRE,System Register Enable" "Reserved,Enabled"
group.long c15:0x459C++0x00
line.long 0x00 "ICC_HSRE,System Register Enable Register for EL2"
rbitfld.long 0x00 3. "ENABLE,Enable lower exception level access to ICC_SRE_EL1" "Reserved,Enabled"
bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "No,Yes"
bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "No,Yes"
newline
rbitfld.long 0x00 0. "SRE,System Register Enable" "Reserved,Enabled"
group.long c15:0x65CC++0x00
line.long 0x00 "ICC_MSRE,System Register Enable Register for EL3"
rbitfld.long 0x00 3. "ENABLE,Enable lower exception level access to ICC_SRE_EL1 and ICC_SRE_EL2" "Reserved,Enabled"
bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "No,Yes"
bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "No,Yes"
newline
rbitfld.long 0x00 0. "SRE,System Register Enable" "Reserved,Enabled"
group.long c15:0x67CC++0x00
line.long 0x00 "ICC_MGRPEN1,Monitor Group1 Interrupt Group Enable"
bitfld.long 0x00 1. "ENABLEGRP1S,Enables Group 1 interrupts for the Secure state" "Disabled,Enabled"
bitfld.long 0x00 0. "ENABLEGRP1NS,Enables Group 1 interrupts for the Non-secure state" "Disabled,Enabled"
tree.end
tree "AArch32 Virtual GIC CPU Interface System Registers"
tree.open "Interrupt Controller Active Priorities Registers"
group.long c15:0x048C++0x00
line.long 0x00 "ICV_AP0R0,Active Priorities Group 0 Register 0"
bitfld.long 0x00 31. "P31,Group 0 interrupt active with priority level 31" "No interrupt,Interrupt"
bitfld.long 0x00 30. "P30,Group 0 interrupt active with priority level 30" "No interrupt,Interrupt"
bitfld.long 0x00 29. "P29,Group 0 interrupt active with priority level 29" "No interrupt,Interrupt"
newline
bitfld.long 0x00 28. "P28,Group 0 interrupt active with priority level 28" "No interrupt,Interrupt"
bitfld.long 0x00 27. "P27,Group 0 interrupt active with priority level 27" "No interrupt,Interrupt"
bitfld.long 0x00 26. "P26,Group 0 interrupt active with priority level 26" "No interrupt,Interrupt"
newline
bitfld.long 0x00 25. "P25,Group 0 interrupt active with priority level 25" "No interrupt,Interrupt"
bitfld.long 0x00 24. "P24,Group 0 interrupt active with priority level 24" "No interrupt,Interrupt"
bitfld.long 0x00 23. "P23,Group 0 interrupt active with priority level 23" "No interrupt,Interrupt"
newline
bitfld.long 0x00 22. "P22,Group 0 interrupt active with priority level 22" "No interrupt,Interrupt"
bitfld.long 0x00 21. "P21,Group 0 interrupt active with priority level 21" "No interrupt,Interrupt"
bitfld.long 0x00 20. "P20,Group 0 interrupt active with priority level 20" "No interrupt,Interrupt"
newline
bitfld.long 0x00 19. "P19,Group 0 interrupt active with priority level 19" "No interrupt,Interrupt"
bitfld.long 0x00 18. "P18,Group 0 interrupt active with priority level 18" "No interrupt,Interrupt"
bitfld.long 0x00 17. "P17,Group 0 interrupt active with priority level 17" "No interrupt,Interrupt"
newline
bitfld.long 0x00 16. "P16,Group 0 interrupt active with priority level 16" "No interrupt,Interrupt"
bitfld.long 0x00 15. "P15,Group 0 interrupt active with priority level 15" "No interrupt,Interrupt"
bitfld.long 0x00 14. "P14,Group 0 interrupt active with priority level 14" "No interrupt,Interrupt"
newline
bitfld.long 0x00 13. "P13,Group 0 interrupt active with priority level 13" "No interrupt,Interrupt"
bitfld.long 0x00 12. "P12,Group 0 interrupt active with priority level 12" "No interrupt,Interrupt"
bitfld.long 0x00 11. "P11,Group 0 interrupt active with priority level 11" "No interrupt,Interrupt"
newline
bitfld.long 0x00 10. "P10,Group 0 interrupt active with priority level 10" "No interrupt,Interrupt"
bitfld.long 0x00 9. "P9,Group 0 interrupt active with priority level 9" "No interrupt,Interrupt"
bitfld.long 0x00 8. "P8,Group 0 interrupt active with priority level 8" "No interrupt,Interrupt"
newline
bitfld.long 0x00 7. "P7,Group 0 interrupt active with priority level 7" "No interrupt,Interrupt"
bitfld.long 0x00 6. "P6,Group 0 interrupt active with priority level 6" "No interrupt,Interrupt"
bitfld.long 0x00 5. "P5,Group 0 interrupt active with priority level 5" "No interrupt,Interrupt"
newline
bitfld.long 0x00 4. "P4,Group 0 interrupt active with priority level 4" "No interrupt,Interrupt"
bitfld.long 0x00 3. "P3,Group 0 interrupt active with priority level 3" "No interrupt,Interrupt"
bitfld.long 0x00 2. "P2,Group 0 interrupt active with priority level 2" "No interrupt,Interrupt"
newline
bitfld.long 0x00 1. "P1,Group 0 interrupt active with priority level 1" "No interrupt,Interrupt"
bitfld.long 0x00 0. "P0,Group 0 interrupt active with priority level 0" "No interrupt,Interrupt"
group.long c15:0x009C++0x00
line.long 0x00 "ICV_AP1R0,Active Priorities Group 1 Register 0"
bitfld.long 0x00 31. "P31,Group 1 interrupt active with priority level 31" "No interrupt,Interrupt"
bitfld.long 0x00 30. "P30,Group 1 interrupt active with priority level 30" "No interrupt,Interrupt"
bitfld.long 0x00 29. "P29,Group 1 interrupt active with priority level 29" "No interrupt,Interrupt"
newline
bitfld.long 0x00 28. "P28,Group 1 interrupt active with priority level 28" "No interrupt,Interrupt"
bitfld.long 0x00 27. "P27,Group 1 interrupt active with priority level 27" "No interrupt,Interrupt"
bitfld.long 0x00 26. "P26,Group 1 interrupt active with priority level 26" "No interrupt,Interrupt"
newline
bitfld.long 0x00 25. "P25,Group 1 interrupt active with priority level 25" "No interrupt,Interrupt"
bitfld.long 0x00 24. "P24,Group 1 interrupt active with priority level 24" "No interrupt,Interrupt"
bitfld.long 0x00 23. "P23,Group 1 interrupt active with priority level 23" "No interrupt,Interrupt"
newline
bitfld.long 0x00 22. "P22,Group 1 interrupt active with priority level 22" "No interrupt,Interrupt"
bitfld.long 0x00 21. "P21,Group 1 interrupt active with priority level 21" "No interrupt,Interrupt"
bitfld.long 0x00 20. "P20,Group 1 interrupt active with priority level 20" "No interrupt,Interrupt"
newline
bitfld.long 0x00 19. "P19,Group 1 interrupt active with priority level 19" "No interrupt,Interrupt"
bitfld.long 0x00 18. "P18,Group 1 interrupt active with priority level 18" "No interrupt,Interrupt"
bitfld.long 0x00 17. "P17,Group 1 interrupt active with priority level 17" "No interrupt,Interrupt"
newline
bitfld.long 0x00 16. "P16,Group 1 interrupt active with priority level 16" "No interrupt,Interrupt"
bitfld.long 0x00 15. "P15,Group 1 interrupt active with priority level 15" "No interrupt,Interrupt"
bitfld.long 0x00 14. "P14,Group 1 interrupt active with priority level 14" "No interrupt,Interrupt"
newline
bitfld.long 0x00 13. "P13,Group 1 interrupt active with priority level 13" "No interrupt,Interrupt"
bitfld.long 0x00 12. "P12,Group 1 interrupt active with priority level 12" "No interrupt,Interrupt"
bitfld.long 0x00 11. "P11,Group 1 interrupt active with priority level 11" "No interrupt,Interrupt"
newline
bitfld.long 0x00 10. "P10,Group 1 interrupt active with priority level 10" "No interrupt,Interrupt"
bitfld.long 0x00 9. "P9,Group 1 interrupt active with priority level 9" "No interrupt,Interrupt"
bitfld.long 0x00 8. "P8,Group 1 interrupt active with priority level 8" "No interrupt,Interrupt"
newline
bitfld.long 0x00 7. "P7,Group 1 interrupt active with priority level 7" "No interrupt,Interrupt"
bitfld.long 0x00 6. "P6,Group 1 interrupt active with priority level 6" "No interrupt,Interrupt"
bitfld.long 0x00 5. "P5,Group 1 interrupt active with priority level 5" "No interrupt,Interrupt"
newline
bitfld.long 0x00 4. "P4,Group 1 interrupt active with priority level 4" "No interrupt,Interrupt"
bitfld.long 0x00 3. "P3,Group 1 interrupt active with priority level 3" "No interrupt,Interrupt"
bitfld.long 0x00 2. "P2,Group 1 interrupt active with priority level 2" "No interrupt,Interrupt"
newline
bitfld.long 0x00 1. "P1,Group 1 interrupt active with priority level 1" "No interrupt,Interrupt"
bitfld.long 0x00 0. "P0,Group 1 interrupt active with priority level 0" "No interrupt,Interrupt"
tree.end
newline
group.long c15:0x038C++0x00
line.long 0x00 "ICV_BPR0,Binary Point Register 0"
bitfld.long 0x00 0.--2. "BINARYPOINT,Interrupt Priority Field Control And Interrupt Preemption Control" "[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0],No preemption-[7:0]"
group.long c15:0x03CC++0x00
line.long 0x00 "ICV_BPR1,Binary Point Register 1"
bitfld.long 0x00 0.--2. "BINARYPOINT,Interrupt Priority Field Control And Interrupt Preemption Control" ",[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0]"
group.long c15:0x4CC++0x00
line.long 0x00 "ICV_CTLR,Control Register"
rbitfld.long 0x00 19. "EXTRANGE,Extended INTID range" "Not supported,Supported"
rbitfld.long 0x00 18. "RSS,Range selector support" "0 - 15,0 - 255"
newline
bitfld.long 0x00 15. "A3V,Affinity 3 Valid" "Reserved,Supported"
bitfld.long 0x00 14. "SEIS,Indicates whether the CPU interface supports local generation of SEIs" "Not supported,?..."
bitfld.long 0x00 11.--13. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,?..."
newline
bitfld.long 0x00 8.--10. "PRIBITS,The number of priority bits implemented minus one" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 1. "VEOIMODE,Controls whether a write to an End of Interrupt Register also deactivates the interrupt" "Disabled,Enabled"
newline
bitfld.long 0x00 0. "VCBPR,Controls whether the same Register is used for interrupt preemption of both virtual Group 0 and virtual Group 1 interrupts" "Separate Registers,Same Register"
wgroup.long c15:0x01BC++0x00
line.long 0x00 "ICV_DIR,Deactivate Interrupt Register"
hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID of the interrupt to be deactivated"
wgroup.long c15:0x018C++0x00
line.long 0x00 "ICV_EOIR0,End Of Interrupt Register 0"
hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID from the corresponding ICC_IAR0 access"
wgroup.long c15:0x01CC++0x00
line.long 0x00 "ICV_EOIR1,End Of Interrupt Register 1"
hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID from the corresponding ICC_IAR1 access"
rgroup.long c15:0x028C++0x00
line.long 0x00 "ICV_HPPIR0,Highest Priority Pending Interrupt Register 0"
hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt"
rgroup.long c15:0x02CC++0x00
line.long 0x00 "ICV_HPPIR1,Highest Priority Pending Interrupt Register 1"
hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt"
rgroup.long c15:0x008C++0x00
line.long 0x00 "ICV_IAR0,Interrupt Acknowledge Register 0"
rgroup.long c15:0x00CC++0x00
line.long 0x00 "ICV_IAR1,Interrupt Acknowledge Register 1"
group.long c15:0x06CC++0x00
line.long 0x00 "ICV_IGRPEN0,Interrupt Group 0 Enable Register"
bitfld.long 0x00 0. "ENABLE,Enables Group 0 interrupts" "Disabled,Enabled"
group.long c15:0x07CC++0x00
line.long 0x00 "ICV_IGRPEN1,Interrupt Group 1 Enable Register"
bitfld.long 0x00 0. "ENABLE,Enables Group 1 interrupts" "Disabled,Enabled"
newline
group.long c15:0x064CC++0x00
line.long 0x00 "ICV_MCTLR,Monitor Control Register"
rbitfld.long 0x00 19. "EXTRANGE,Extended INTID range" "Not supported,Supported"
rbitfld.long 0x00 18. "RSS,Range selector support" "0 - 15,0 - 255"
newline
rbitfld.long 0x00 17. "NDS,Disable Security not supported" "Supported,Not supported"
rbitfld.long 0x00 15. "A3V,Affinity 3 Valid" "Reserved,Supported"
rbitfld.long 0x00 14. "SEIS,Indicates whether the CPU interface supports generation of SEIs" "Not supported,?..."
newline
rbitfld.long 0x00 11.--13. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,?..."
rbitfld.long 0x00 8.--10. "PRIBITS,The number of priority bits implemented minus one" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6. "PMHE,Priority Mask Hint Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 4. "EOIMODE_EL1NS,Controls whether a write to an End of Interrupt Register also deactivates the interrupt (Non-secure EL1 and EL2)" "Priority drop/Deactivation,Priority drop"
bitfld.long 0x00 3. "EOIMODE_EL1S,Controls whether a write to an End of Interrupt Register also deactivates the interrupt (Secure EL1)" "Enabled,Disabled"
bitfld.long 0x00 2. "EOIMODE_EL3,Controls whether a write to an End of Interrupt Register also deactivates the interrupt (EL3)" "Enabled,Disabled"
newline
bitfld.long 0x00 1. "CBPR_EL1NS,Controls whether the same Register is used for interrupt preemption of both Group 0 and Group 1 Non-secure interrupts at EL1" "Separate Registers,Same Register"
bitfld.long 0x00 0. "CBPR_EL1S,Controls whether the same Register is used for interrupt preemption of both Group 0 and Group 1 Secure interrupts in Secure non-Monitor modes" "Separate Registers,Same Register"
group.long c15:0x67CC++0x00
line.long 0x00 "ICV_MGRPEN1,Monitor Interrupt Group 1 Enable Register"
bitfld.long 0x00 1. "ENABLEGRP1S,Enables Group 1 interrupts for the Secure state" "Disabled,Enabled"
bitfld.long 0x00 0. "ENABLEGRP1NS,Enables Group 1 interrupts for the Non-secure state" "Disabled,Enabled"
group.long c15:0x0064++0x00
line.long 0x00 "ICV_PMR,Interrupt Priority Mask Register"
hexmask.long.byte 0x00 0.--7. 1. "PRIORITY,The priority mask level for the CPU interface"
rgroup.long c15:0x03BC++0x00
line.long 0x00 "ICV_RPR,Running Priority Register"
hexmask.long.byte 0x00 0.--7. 1. "PRIORITY,The current running priority on the CPU interface"
tree.end
tree "AArch32 Virtual Interface Control System Registers"
tree.open "Hypervisor Active Priorities Registers"
group.long c15:0x408C++0x00
line.long 0x00 "ICH_AP0R0,Hypervisor Active Priorities Group 0 Register 0"
bitfld.long 0x00 31. "P31,Group 0 interrupt active with priority level 31" "No interrupt,Interrupt"
bitfld.long 0x00 30. "P30,Group 0 interrupt active with priority level 30" "No interrupt,Interrupt"
bitfld.long 0x00 29. "P29,Group 0 interrupt active with priority level 29" "No interrupt,Interrupt"
newline
bitfld.long 0x00 28. "P28,Group 0 interrupt active with priority level 28" "No interrupt,Interrupt"
bitfld.long 0x00 27. "P27,Group 0 interrupt active with priority level 27" "No interrupt,Interrupt"
bitfld.long 0x00 26. "P26,Group 0 interrupt active with priority level 26" "No interrupt,Interrupt"
newline
bitfld.long 0x00 25. "P25,Group 0 interrupt active with priority level 25" "No interrupt,Interrupt"
bitfld.long 0x00 24. "P24,Group 0 interrupt active with priority level 24" "No interrupt,Interrupt"
bitfld.long 0x00 23. "P23,Group 0 interrupt active with priority level 23" "No interrupt,Interrupt"
newline
bitfld.long 0x00 22. "P22,Group 0 interrupt active with priority level 22" "No interrupt,Interrupt"
bitfld.long 0x00 21. "P21,Group 0 interrupt active with priority level 21" "No interrupt,Interrupt"
bitfld.long 0x00 20. "P20,Group 0 interrupt active with priority level 20" "No interrupt,Interrupt"
newline
bitfld.long 0x00 19. "P19,Group 0 interrupt active with priority level 19" "No interrupt,Interrupt"
bitfld.long 0x00 18. "P18,Group 0 interrupt active with priority level 18" "No interrupt,Interrupt"
bitfld.long 0x00 17. "P17,Group 0 interrupt active with priority level 17" "No interrupt,Interrupt"
newline
bitfld.long 0x00 16. "P16,Group 0 interrupt active with priority level 16" "No interrupt,Interrupt"
bitfld.long 0x00 15. "P15,Group 0 interrupt active with priority level 15" "No interrupt,Interrupt"
bitfld.long 0x00 14. "P14,Group 0 interrupt active with priority level 14" "No interrupt,Interrupt"
newline
bitfld.long 0x00 13. "P13,Group 0 interrupt active with priority level 13" "No interrupt,Interrupt"
bitfld.long 0x00 12. "P12,Group 0 interrupt active with priority level 12" "No interrupt,Interrupt"
bitfld.long 0x00 11. "P11,Group 0 interrupt active with priority level 11" "No interrupt,Interrupt"
newline
bitfld.long 0x00 10. "P10,Group 0 interrupt active with priority level 10" "No interrupt,Interrupt"
bitfld.long 0x00 9. "P9,Group 0 interrupt active with priority level 9" "No interrupt,Interrupt"
bitfld.long 0x00 8. "P8,Group 0 interrupt active with priority level 8" "No interrupt,Interrupt"
newline
bitfld.long 0x00 7. "P7,Group 0 interrupt active with priority level 7" "No interrupt,Interrupt"
bitfld.long 0x00 6. "P6,Group 0 interrupt active with priority level 6" "No interrupt,Interrupt"
bitfld.long 0x00 5. "P5,Group 0 interrupt active with priority level 5" "No interrupt,Interrupt"
newline
bitfld.long 0x00 4. "P4,Group 0 interrupt active with priority level 4" "No interrupt,Interrupt"
bitfld.long 0x00 3. "P3,Group 0 interrupt active with priority level 3" "No interrupt,Interrupt"
bitfld.long 0x00 2. "P2,Group 0 interrupt active with priority level 2" "No interrupt,Interrupt"
newline
bitfld.long 0x00 1. "P1,Group 0 interrupt active with priority level 1" "No interrupt,Interrupt"
bitfld.long 0x00 0. "P0,Group 0 interrupt active with priority level 0" "No interrupt,Interrupt"
group.long c15:0x409C++0x00
line.long 0x00 "ICH_AP1R0,Hypervisor Active Priorities Group 1 Register 0"
bitfld.long 0x00 31. "P31,Group 1 interrupt active with priority level 31" "No interrupt,Interrupt"
bitfld.long 0x00 30. "P30,Group 1 interrupt active with priority level 30" "No interrupt,Interrupt"
bitfld.long 0x00 29. "P29,Group 1 interrupt active with priority level 29" "No interrupt,Interrupt"
newline
bitfld.long 0x00 28. "P28,Group 1 interrupt active with priority level 28" "No interrupt,Interrupt"
bitfld.long 0x00 27. "P27,Group 1 interrupt active with priority level 27" "No interrupt,Interrupt"
bitfld.long 0x00 26. "P26,Group 1 interrupt active with priority level 26" "No interrupt,Interrupt"
newline
bitfld.long 0x00 25. "P25,Group 1 interrupt active with priority level 25" "No interrupt,Interrupt"
bitfld.long 0x00 24. "P24,Group 1 interrupt active with priority level 24" "No interrupt,Interrupt"
bitfld.long 0x00 23. "P23,Group 1 interrupt active with priority level 23" "No interrupt,Interrupt"
newline
bitfld.long 0x00 22. "P22,Group 1 interrupt active with priority level 22" "No interrupt,Interrupt"
bitfld.long 0x00 21. "P21,Group 1 interrupt active with priority level 21" "No interrupt,Interrupt"
bitfld.long 0x00 20. "P20,Group 1 interrupt active with priority level 20" "No interrupt,Interrupt"
newline
bitfld.long 0x00 19. "P19,Group 1 interrupt active with priority level 19" "No interrupt,Interrupt"
bitfld.long 0x00 18. "P18,Group 1 interrupt active with priority level 18" "No interrupt,Interrupt"
bitfld.long 0x00 17. "P17,Group 1 interrupt active with priority level 17" "No interrupt,Interrupt"
newline
bitfld.long 0x00 16. "P16,Group 1 interrupt active with priority level 16" "No interrupt,Interrupt"
bitfld.long 0x00 15. "P15,Group 1 interrupt active with priority level 15" "No interrupt,Interrupt"
bitfld.long 0x00 14. "P14,Group 1 interrupt active with priority level 14" "No interrupt,Interrupt"
newline
bitfld.long 0x00 13. "P13,Group 1 interrupt active with priority level 13" "No interrupt,Interrupt"
bitfld.long 0x00 12. "P12,Group 1 interrupt active with priority level 12" "No interrupt,Interrupt"
bitfld.long 0x00 11. "P11,Group 1 interrupt active with priority level 11" "No interrupt,Interrupt"
newline
bitfld.long 0x00 10. "P10,Group 1 interrupt active with priority level 10" "No interrupt,Interrupt"
bitfld.long 0x00 9. "P9,Group 1 interrupt active with priority level 9" "No interrupt,Interrupt"
bitfld.long 0x00 8. "P8,Group 1 interrupt active with priority level 8" "No interrupt,Interrupt"
newline
bitfld.long 0x00 7. "P7,Group 1 interrupt active with priority level 7" "No interrupt,Interrupt"
bitfld.long 0x00 6. "P6,Group 1 interrupt active with priority level 6" "No interrupt,Interrupt"
bitfld.long 0x00 5. "P5,Group 1 interrupt active with priority level 5" "No interrupt,Interrupt"
newline
bitfld.long 0x00 4. "P4,Group 1 interrupt active with priority level 4" "No interrupt,Interrupt"
bitfld.long 0x00 3. "P3,Group 1 interrupt active with priority level 3" "No interrupt,Interrupt"
bitfld.long 0x00 2. "P2,Group 1 interrupt active with priority level 2" "No interrupt,Interrupt"
newline
bitfld.long 0x00 1. "P1,Group 1 interrupt active with priority level 1" "No interrupt,Interrupt"
bitfld.long 0x00 0. "P0,Group 1 interrupt active with priority level 0" "No interrupt,Interrupt"
tree.end
newline
rgroup.long c15:0x438C++0x00
line.long 0x00 "ICH_EISR,End of Interrupt Status Register"
bitfld.long 0x00 3. "STATUS3,EOI maintenance interrupt status bit for List Register 3" "No interrupt,Interrupt"
bitfld.long 0x00 2. "STATUS2,EOI maintenance interrupt status bit for List Register 2" "No interrupt,Interrupt"
bitfld.long 0x00 1. "STATUS1,EOI maintenance interrupt status bit for List Register 1" "No interrupt,Interrupt"
newline
bitfld.long 0x00 0. "STATUS0,EOI maintenance interrupt status bit for List Register 0" "No interrupt,Interrupt"
rgroup.long c15:0x458C++0x00
line.long 0x00 "ICH_ELRSR,Empty List Register Status Register"
bitfld.long 0x00 3. "STATUS3,Status bit for List Register 3" "Interrupt,No interrupt"
bitfld.long 0x00 2. "STATUS2,Status bit for List Register 2" "Interrupt,No interrupt"
bitfld.long 0x00 1. "STATUS1,Status bit for List Register 1" "Interrupt,No interrupt"
newline
bitfld.long 0x00 0. "STATUS0,Status bit for List Register 0" "Interrupt,No interrupt"
group.long c15:0x40BC++0x00
line.long 0x00 "ICH_HCR,Hypervisor Control Register"
bitfld.long 0x00 27.--31. "EOICOUNT,This field is incremented whenever a successful write to a virtual EOIR or DIR Register would have resulted in a virtual interrupt deactivation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 14. "TDIR,Trap Non-secure EL1 writes to ICC_DIR and ICV_DIR" "No trap,Trap"
bitfld.long 0x00 13. "TSEI,Trap all locally generated SEIs" "No trap,Trap"
newline
bitfld.long 0x00 12. "TALL1,Trap all Non-secure EL1 accesses to ICC_* and ICV_* System Registers for Group 1 interrupts to EL2" "No trap,Trap"
bitfld.long 0x00 11. "TALL0,Trap all Non-secure EL1 accesses to ICC_* and ICV_* System Registers for Group 0 interrupts to EL2" "No trap,Trap"
bitfld.long 0x00 10. "TC,Trap all Non-secure EL1 accesses to System Registers that are common to Group 0 and Group 1 to EL2" "No trap,Trap"
newline
bitfld.long 0x00 7. "VGRP1DIE,VM Group 1 Disabled Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 6. "VGRP1EIE,VM Group 1 Enabled Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 5. "VGRP0DIE,VM Group 0 Disabled Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 4. "VGRP0EIE,VM Group 0 Enabled Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 3. "NPIE,No Pending Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 2. "LRENPIE,List Register Entry Not Present Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 1. "UIE,Underflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 0. "EN,Global enable bit for the virtual CPU interface" "Disabled,Enabled"
group.long c15:(0x40CC+0x0)++0x00
line.long 0x00 "ICH_LR0,List Register 0"
hexmask.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
group.long c15:(0x40CC+0x100)++0x00
line.long 0x00 "ICH_LR1,List Register 1"
hexmask.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
group.long c15:(0x40CC+0x200)++0x00
line.long 0x00 "ICH_LR2,List Register 2"
hexmask.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
group.long c15:(0x40CC+0x300)++0x00
line.long 0x00 "ICH_LR3,List Register 3"
hexmask.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
group.long c15:(0x40EC+0x0)++0x00
line.long 0x00 "ICH_LRC0,List Register Extension 0"
bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt." "Triggered by Software,Hardware interrupt"
bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 1,Group 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt"
hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts"
group.long c15:(0x40EC+0x100)++0x00
line.long 0x00 "ICH_LRC1,List Register Extension 1"
bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt." "Triggered by Software,Hardware interrupt"
bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 1,Group 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt"
hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts"
group.long c15:(0x40EC+0x200)++0x00
line.long 0x00 "ICH_LRC2,List Register Extension 2"
bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt." "Triggered by Software,Hardware interrupt"
bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 1,Group 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt"
hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts"
group.long c15:(0x40EC+0x300)++0x00
line.long 0x00 "ICH_LRC3,List Register Extension 3"
bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt." "Triggered by Software,Hardware interrupt"
bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 1,Group 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt"
hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts"
rgroup.long c15:0x42BC++0x00
line.long 0x00 "ICH_MISR,Maintenance Interrupt State Register"
bitfld.long 0x00 7. "VGRP1D,VPE Group 1 Disabled" "Not asserted,Asserted"
bitfld.long 0x00 6. "VGRP1E,VPE Group 1 Enabled" "Not asserted,Asserted"
bitfld.long 0x00 5. "VGRP0D,VPE Group 0 Disabled" "Not asserted,Asserted"
newline
bitfld.long 0x00 4. "VGRP0E,VPE Group 0 Enabled" "Not asserted,Asserted"
bitfld.long 0x00 3. "NP,No Pending" "Not asserted,Asserted"
bitfld.long 0x00 2. "LRENP,List Register Entry Not Present" "Not asserted,Asserted"
newline
bitfld.long 0x00 1. "U,Underflow" "Not asserted,Asserted"
bitfld.long 0x00 0. "EOI,End Of Interrupt" "Not asserted,Asserted"
group.long c15:0x47BC++0x00
line.long 0x00 "ICH_VMCR,Virtual Machine Control Register"
hexmask.long.byte 0x00 24.--31. 1. "VPMR,The priority mask level for the virtual CPU interface"
bitfld.long 0x00 21.--23. "VBPR0,Virtual Binary Point Register Group 0" "[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0],No preemption-[7:0]"
bitfld.long 0x00 18.--20. "VBPR1,Virtual Binary Point Register, Group 1" ",[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0]"
newline
bitfld.long 0x00 9. "VEOIM,Controls whether a write to an End of Interrupt Register also deactivates the virtual interrupt" "Disabled,Enabled"
bitfld.long 0x00 4. "VCBPR,Virtual Common Binary Point Register" "Separate Registers,Same Register"
bitfld.long 0x00 3. "VFIQEN,Virtual FIQ enable" "Reserved,Virtual FIQs"
newline
bitfld.long 0x00 1. "VENG1,Virtual Group 1 interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 0. "VENG0,Virtual Group 0 interrupt enable" "Disabled,Enabled"
group.long c15:0x449C++0x00
line.long 0x00 "ICH_VSEIR,Virtual System Error Interrupt Register"
rgroup.long c15:0x41BC++0x00
line.long 0x00 "ICH_VTR,VGIC Type Register"
bitfld.long 0x00 29.--31. "PRIBITS,The number of priority bits implemented minus one" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 26.--28. "PREBITS,The number of virtual preemption bits implemented, minus one" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 23.--25. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,?..."
newline
bitfld.long 0x00 22. "SEIS,Indicates whether the CPU interface supports local generation of SEIs" "Not supported,?..."
bitfld.long 0x00 21. "A3V,Affinity 3 Valid" "Reserved,Supported"
bitfld.long 0x00 20. "NV4,GICv4 direct injection of virtual interrupts not supported" "Supported,?..."
newline
bitfld.long 0x00 19. "TDS,Separate trapping of Non-secure EL1 writes to ICV_DIR_EL1 supported" "Reserved,Supported"
bitfld.long 0x00 0.--4. "LISTREGS,The number of implemented List Registers minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.end
tree.end
tree "Debug Registers"
tree "Coresight Management Registers"
if corename()=="CORTEXA75"
rgroup.long c14:0x0000++0x0
line.long 0x0 "DBGDIDR,Debug ID Register"
bitfld.long 0x0 28.--31. "WRP,Number of Watchpoint Register Pairs" "Reserved,Reserved,Reserved,4,?..."
bitfld.long 0x0 24.--27. "BRP,Number of Breakpoint Register Pairs" "Reserved,Reserved,Reserved,Reserved,Reserved,6,?..."
bitfld.long 0x0 20.--23. "CTX_CMP,Number of BRPs with Context ID Comparison Capability" "Reserved,2,?..."
newline
bitfld.long 0x00 16.--19. "VERSION,Debug architecture version" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,v8.2,?..."
bitfld.long 0x0 14. "NSUHD,Secure User halting debug-mode" "Reserved,Not supported"
bitfld.long 0x0 12. "SE,Security Extensions implemented" "Reserved,Implemented"
elif corename()=="CORTEXA55"
rgroup.long c14:0x0000++0x0
line.long 0x0 "DBGDIDR,Debug ID Register"
bitfld.long 0x0 28.--31. "WRP,Number of Watchpoint Register Pairs" "Reserved,Reserved,Reserved,4,?..."
bitfld.long 0x0 24.--27. "BRP,Number of Breakpoint Register Pairs" "Reserved,Reserved,Reserved,Reserved,Reserved,6,?..."
bitfld.long 0x0 20.--23. "CTX_CMP,Number of BRPs with Context ID Comparison Capability" "Reserved,2,?..."
newline
bitfld.long 0x00 16.--19. "VERSION,Debug architecture version" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,v8.2,?..."
bitfld.long 0x0 14. "NSUHD,Secure User halting debug-mode" "Reserved,Not supported"
bitfld.long 0x0 12. "SE,Security Extensions implemented" "Reserved,Implemented"
endif
rgroup.long c14:0x0060++0x0
line.long 0x00 "DBGWFAR,Watchpoint Fault Address Register"
group.long c14:0x0070++0x0
line.long 0x00 "DBGVCR,Debug Vector Catch register"
bitfld.long 0x00 31. "FIQVCE_NS,FIQ vector catch in Non-secure state" "Disabled,Enabled"
bitfld.long 0x00 30. "IRQVCE_NS,IRG vector catch in Non-secure state" "Disabled,Enabled"
bitfld.long 0x00 28. "DAVCE_NS,Data Abort vector catch in Non-secure state" "Disabled,Enabled"
newline
bitfld.long 0x00 27. "PAVCE_NS,Prefetch Abort vector catch in Non-secure state" "Disabled,Enabled"
bitfld.long 0x00 26. "SVCVCE_NS,SVC vector catch in Non-secure state" "Disabled,Enabled"
bitfld.long 0x00 25. "UIVCE_NS,Undefined instruction vector catch in Non-secure state" "Disabled,Enabled"
newline
bitfld.long 0x00 23. "FIQ,HVBAR: FIQ" "Disabled,Enabled"
bitfld.long 0x00 22. "IRQ,HVBAR: IRQ" "Disabled,Enabled"
bitfld.long 0x00 21. "HEE,HVBAR: Hyp Entry Exception" "Disabled,Enabled"
newline
bitfld.long 0x00 20. "DA,HVBAR: Data Abort" "Disabled,Enabled"
bitfld.long 0x00 19. "PA,HVBAR: Prefetch Abort" "Disabled,Enabled"
bitfld.long 0x00 18. "HVC,HVBAR: HVC" "Disabled,Enabled"
newline
bitfld.long 0x00 17. "UI,HVBAR: Undefined Instruction" "Disabled,Enabled"
bitfld.long 0x00 15. "FIQVCE_SM,FIQ vector catch enable, in Secure state on Monitor mode vector" "Disabled,Enabled"
bitfld.long 0x00 14. "IRQVCE_SM,IRQ vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled"
newline
bitfld.long 0x00 12. "DAVCE_SM,Data Abort vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled"
bitfld.long 0x00 11. "PAVCE_SM,Prefetch Abort vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled"
bitfld.long 0x00 10. "SMCVCE_S,SMC vector catch enable in Secure state" "Disabled,Enabled"
newline
bitfld.long 0x00 7. "FIQVCE_S,FIQ vector catch in Secure state" "Disabled,Enabled"
bitfld.long 0x00 6. "IRQVCE_S,IRG vector catch in Secure state" "Disabled,Enabled"
bitfld.long 0x00 4. "DAVCE_S,Data Abort vector catch in Secure state" "Disabled,Enabled"
newline
bitfld.long 0x00 3. "PAVCE_S,Prefetch Abort vector catch in Secure state" "Disabled,Enabled"
bitfld.long 0x00 2. "SVCVCE_S,SVC vector catch in Secure state" "Disabled,Enabled"
bitfld.long 0x00 1. "UIVCE_S,Undefined instruction vector catch in Secure state" "Disabled,Enabled"
newline
bitfld.long 0x00 0. "RVCE,Reset vector catch enable" "Disabled,Enabled"
group.long c14:0x0200++0x0
line.long 0x00 "DBGDTRRXEXT,Debug Receive Register (External View)"
rgroup.long c14:0x0050++0x0
line.long 0x00 "DBGDTRRXINT,Debug Receive Register (Internal View)"
group.long c14:0x0020++0x00
line.long 0x00 "DBGDCCINT,Debug Comms Channel Interrupt Enable register"
bitfld.long 0x00 30. "RX,DCC interrupt enable controls" "Disabled,Enabled"
bitfld.long 0x00 29. "TX,DCC interrupt enable controls" "Disabled,Enabled"
; For DBGDSCRint, bits 28 - 19, 14 - 13, 11 - 6, 1 - 0 are RES0.
; DBGDSCRint is read only.
rgroup.long c14:0x0010++0x0
line.long 0x00 "DBGDSCRINT,Debug Status and Control Register (Internal View)"
bitfld.long 0x00 30. "RXFULL,DBGDTRRX Register full" "Empty,Full"
bitfld.long 0x00 29. "TXFULL,DBGDTRTX Register full" "Empty,Full"
bitfld.long 0x00 18. "NS,Non-secure status bit" "Secure,Non-secure"
newline
bitfld.long 0x00 17. "SPNIDDIS,Secure Privileged Non-Invasive Debug Disable" "No,Yes"
bitfld.long 0x00 16. "SPIDDIS,Secure Privileged Invasive Debug Disable" "No,Yes"
bitfld.long 0x00 15. "MDBGEN,Monitor debug-mode enable" "Disabled,Enabled"
newline
bitfld.long 0x00 12. "UDCCDIS,User mode access to Communications Channel disable" "No,Yes"
bitfld.long 0x00 2.--5. "MOE,Method of debug entry field" "Reserved,Breakpoint,Reserved,Software Breakpoint (BKPT),Reserved,Vector Catch,Reserved,Reserved,Reserved,Reserved,Watchpoint,?..."
; For DBGDSCRext, bits 25 - 24, 20, 13, 11 - 7, 1 - 0 are RES0.
; DBGDSCRext is read/write only.
group.long c14:0x0220++0x0
line.long 0x00 "DBGDSCREXT,Debug Status and Control Register (External View)"
bitfld.long 0x00 30. "RXFULL,DBGDTRRX Register full" "Empty,Full"
bitfld.long 0x00 29. "TXFULL,DBGDTRTX Register full" "Empty,Full"
bitfld.long 0x00 27. "RXO,DBGDTRRX overflow" "No overflow,Overflow"
newline
bitfld.long 0x00 26. "TXU,DBGDTRTX underflow" "No underflow,Underflow"
bitfld.long 0x00 22.--23. "INTDIS,Interrupt disable" "Don't disable interrupts,Disable interrupts targeting non-sec EL1,Disable interrupts targeting EL1 & EL2,Disable all interrupts"
bitfld.long 0x00 21. "TDA,Trap debug register access" "No trap,Trap"
newline
bitfld.long 0x00 19. "SC2,Sample CONTEXTIDR_EL2" "VTTBR_EL2.VMID,CONTEXTIDR_EL2"
bitfld.long 0x00 18. "NS,Non-secure status bit" "Secure,Non-secure"
bitfld.long 0x00 17. "SPNIDDIS,Secure Privileged Non-Invasive Debug Disable" "No,Yes"
newline
bitfld.long 0x00 16. "SPIDDIS,Secure Privileged Invasive Debug Disable" "No,Yes"
bitfld.long 0x00 15. "MDBGEN,Monitor debug-mode enable" "Disabled,Enabled"
bitfld.long 0x00 14. "HDE,Halting debug-mode" "Disabled,Enabled"
newline
bitfld.long 0x00 12. "UDCCDIS,User mode access to Communications Channel disable" "No,Yes"
bitfld.long 0x00 7. "ADABORT,Asynchronous data abort" "Not aborted,Aborted"
bitfld.long 0x00 6. "ERR,Cumulative error flag" "Not error,Error"
newline
bitfld.long 0x00 2.--5. "MOE,Method of debug entry field" "Reserved,Breakpoint,Reserved,Software Breakpoint (BKPT),Reserved,Vector Catch,Reserved,Reserved,Reserved,Reserved,Watchpoint,?..."
group.long c14:0x0230++0x0
line.long 0x00 "DBGDTRTXEXT,Debug Transmit Register (External View)"
wgroup.long c14:0x0050++0x0
line.long 0x00 "DBGDTRTXINT,Debug Transmit Register (Internal View)"
if (((per.l(c14:0x0411))&0x2)==0x2)
group.long c14:0x0260++0x0
line.long 0x0 "DBGOSECCR,Debug OS Lock Exception Catch Control Register"
else
rgroup.long c14:0x0260++0x0
line.long 0x0 "DBGOSECCR,Debug OS Lock Exception Catch Control Register"
endif
rgroup.long c14:0x0707++0x0
line.long 0x0 "DBGDEVID2,Debug Device ID Register 2"
rgroup.long c14:0x0717++0x0
line.long 0x0 "DBGDEVID1,Debug Device ID Register 1"
rgroup.long c14:0x0727++0x0
line.long 0x0 "DBGDEVID,Debug Device ID Register 0"
bitfld.long 0x0 28.--31. "CIDMASK,Level of support for the Context ID matching breakpoint masking capability" "Not implemented,?..."
bitfld.long 0x0 24.--27. "AR,Debug External Auxiliary Control Register support status" "Not supported,?..."
bitfld.long 0x0 20.--23. "DL,Support for Debug OS Double Lock Register" "Reserved,Supported,?..."
newline
bitfld.long 0x0 16.--19. "VE,Specifies implementation of Virtualization Extension" "Reserved,Implemented,?..."
bitfld.long 0x0 12.--15. "VC,Form of the vector catch event implemented" "Implemented,?..."
bitfld.long 0x0 8.--11. "BPAM,Level of support for Immediate Virtual Address matching breakpoint masking capability" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Not implemented"
newline
bitfld.long 0x0 4.--7. "WPAM,Level of support for the DVA matching watchpoint masking capability" "Reserved,Implemented,?..."
tree.end
newline
rgroup.quad c14:0x10010++0x1
line.quad 0x0 "DBGDRAR,Debug ROM Address Register"
rgroup.quad c14:0x10020++0x1
line.quad 0x0 "DBGDSAR,Debug Self Address Offset Register"
wgroup.long c14:0x0401++0x00
line.long 0x00 "DBGOSLAR,Operating System Lock Access Register"
rgroup.long c14:0x0411++0x00
line.long 0x00 "DBGOSLSR,Operating System Lock Status Register"
bitfld.long 0x00 2. "NTT,32-Bit Access" "Not required,Required"
bitfld.long 0x00 1. "OSLK,Status of the OS Lock" "Not locked,Locked"
bitfld.long 0x00 0. 3. "OSLM,OS Lock Model implemented Bit" "Reserved,Reserved,Implemented,?..."
group.long c14:0x0431++0x00
line.long 0x00 "DBGOSDLR,OS Double-lock Register"
bitfld.long 0x00 0. "DLK,OS double-lock control" "Not locked,Locked"
group.long c14:0x0441++0x00
line.long 0x00 "DBGPRCR,Device Power-Down and Reset Control Register"
bitfld.long 0x00 0. "CORENPDRQ,Core No Power down Request" "Powered down,Emulated"
group.long c14:0x0687++0x00
line.long 0x00 "DBGCLAIMSET,Claim Tag register Set"
bitfld.long 0x0 7. "CT7,Claim Tag 7 Set" "Not set,Set"
bitfld.long 0x0 6. "CT6,Claim Tag 6 Set" "Not set,Set"
bitfld.long 0x0 5. "CT5,Claim Tag 5 Set" "Not set,Set"
newline
bitfld.long 0x0 4. "CT4,Claim Tag 4 Set" "Not set,Set"
bitfld.long 0x0 3. "CT3,Claim Tag 3 Set" "Not set,Set"
bitfld.long 0x0 2. "CT2,Claim Tag 2 Set" "Not set,Set"
newline
bitfld.long 0x0 1. "CT1,Claim Tag 1 Set" "Not set,Set"
bitfld.long 0x0 0. "CT0,Claim Tag 0 Set" "Not set,Set"
group.long c14:0x0697++0x00
line.long 0x00 "DBGCLAIMCLR,Claim Tag register Clear"
bitfld.long 0x0 7. "CT7,Claim Tag 7 Clear" "Not cleared,Cleared"
bitfld.long 0x0 6. "CT6,Claim Tag 6 Clear" "Not cleared,Cleared"
bitfld.long 0x0 5. "CT5,Claim Tag 5 Clear" "Not cleared,Cleared"
newline
bitfld.long 0x0 4. "CT4,Claim Tag 4 Clear" "Not cleared,Cleared"
bitfld.long 0x0 3. "CT3,Claim Tag 3 Clear" "Not cleared,Cleared"
bitfld.long 0x0 2. "CT2,Claim Tag 2 Clear" "Not cleared,Cleared"
newline
bitfld.long 0x0 1. "CT1,Claim Tag 1 Clear" "Not cleared,Cleared"
bitfld.long 0x0 0. "CT0,Claim Tag 0 Clear" "Not cleared,Cleared"
rgroup.long c14:0x06E7++0x00
line.long 0x00 "DBGAUTHSTATUS,Authentication Status register"
bitfld.long 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented"
bitfld.long 0x00 6. "SNE,Secure non-invasive debug enabled" "Disabled,Enabled"
bitfld.long 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented"
newline
bitfld.long 0x00 4. "SE,Secure invasive debug enabled" "Disabled,Enabled"
bitfld.long 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented"
bitfld.long 0x00 2. "NSNE,Non-secure non-invasive debug enabled" "Disabled,Enabled"
newline
bitfld.long 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented"
bitfld.long 0x00 0. "NSE,Non-secure invasive debug enabled" "Disabled,Enabled"
rgroup.long c14:0x7000++0x00 "Jazelle Registers"
line.long 0x0 "JIDR,Jazelle ID Register"
rgroup.long c14:0x7001++0x00
line.long 0x0 "JOSCR,Jazelle OS Control Register"
rgroup.long c14:0x7002++0x00
line.long 0x0 "JMCR,Jazelle Main Configuration Register"
tree.end
tree "Breakpoint Registers"
tree "Breakpoint 0"
group.long c14:(0x0400+0x0)++0x00
line.long 0x00 "DBGBVR0,Breakpoint Value Register"
group.long c14:(0x0500+0x0)++0x00
line.long 0x00 "DBGBCR0,Breakpoint Control Register"
bitfld.long 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
newline
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
bitfld.long 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,T32/DBGBVRn,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,T32/DBGBVRn+2,Reserved,Reserved,A64/A32/DBGBVRn"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
newline
bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
tree.end
tree "Breakpoint 1"
group.long c14:(0x0400+0x10)++0x00
line.long 0x00 "DBGBVR1,Breakpoint Value Register"
group.long c14:(0x0500+0x10)++0x00
line.long 0x00 "DBGBCR1,Breakpoint Control Register"
bitfld.long 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
newline
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
bitfld.long 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,T32/DBGBVRn,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,T32/DBGBVRn+2,Reserved,Reserved,A64/A32/DBGBVRn"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
newline
bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
tree.end
tree "Breakpoint 2"
group.long c14:(0x0400+0x20)++0x00
line.long 0x00 "DBGBVR2,Breakpoint Value Register"
group.long c14:(0x0500+0x20)++0x00
line.long 0x00 "DBGBCR2,Breakpoint Control Register"
bitfld.long 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
newline
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
bitfld.long 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,T32/DBGBVRn,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,T32/DBGBVRn+2,Reserved,Reserved,A64/A32/DBGBVRn"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
newline
bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
tree.end
tree "Breakpoint 3"
group.long c14:(0x0400+0x30)++0x00
line.long 0x00 "DBGBVR3,Breakpoint Value Register"
group.long c14:(0x0500+0x30)++0x00
line.long 0x00 "DBGBCR3,Breakpoint Control Register"
bitfld.long 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
newline
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
bitfld.long 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,T32/DBGBVRn,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,T32/DBGBVRn+2,Reserved,Reserved,A64/A32/DBGBVRn"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
newline
bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
tree.end
tree "Breakpoint 4"
group.long c14:(0x0400+0x40)++0x00
line.long 0x00 "DBGBVR4,Breakpoint Value Register"
group.long c14:(0x0101+0x40)++0x00
line.long 0x00 "DBGBXVR4,Breakpoint Extended Value Register"
group.long c14:(0x0500+0x40)++0x00
line.long 0x00 "DBGBCR4,Breakpoint Control Register"
bitfld.long 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
newline
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
bitfld.long 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,T32/DBGBVRn,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,T32/DBGBVRn+2,Reserved,Reserved,A64/A32/DBGBVRn"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
newline
bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
tree.end
tree "Breakpoint 5"
group.long c14:(0x0400+0x50)++0x00
line.long 0x00 "DBGBVR5,Breakpoint Value Register"
group.long c14:(0x0101+0x50)++0x00
line.long 0x00 "DBGBXVR5,Breakpoint Extended Value Register"
group.long c14:(0x0500+0x50)++0x00
line.long 0x00 "DBGBCR5,Breakpoint Control Register"
bitfld.long 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
newline
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
bitfld.long 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,T32/DBGBVRn,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,T32/DBGBVRn+2,Reserved,Reserved,A64/A32/DBGBVRn"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
newline
bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
tree.end
tree.end
tree "Watchpoint Registers"
tree "Watchpoint 0"
group.long c14:(0x0600+0x0)++0x00
line.long 0x00 "DBGWVR0,Watchpoint Value Register"
hexmask.long 0x00 2.--31. 0x4 "ADDRESS,Data address"
group.long c14:(0x0700+0x0)++0x00
line.long 0x00 "DBGWCR0,Watchpoint Control Register"
bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.long.byte 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.long 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled"
tree.end
tree "Watchpoint 1"
group.long c14:(0x0600+0x10)++0x00
line.long 0x00 "DBGWVR1,Watchpoint Value Register"
hexmask.long 0x00 2.--31. 0x4 "ADDRESS,Data address"
group.long c14:(0x0700+0x10)++0x00
line.long 0x00 "DBGWCR1,Watchpoint Control Register"
bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.long.byte 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.long 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled"
tree.end
tree "Watchpoint 2"
group.long c14:(0x0600+0x20)++0x00
line.long 0x00 "DBGWVR2,Watchpoint Value Register"
hexmask.long 0x00 2.--31. 0x4 "ADDRESS,Data address"
group.long c14:(0x0700+0x20)++0x00
line.long 0x00 "DBGWCR2,Watchpoint Control Register"
bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.long.byte 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.long 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled"
tree.end
tree "Watchpoint 3"
group.long c14:(0x0600+0x30)++0x00
line.long 0x00 "DBGWVR3,Watchpoint Value Register"
hexmask.long 0x00 2.--31. 0x4 "ADDRESS,Data address"
group.long c14:(0x0700+0x30)++0x00
line.long 0x00 "DBGWCR3,Watchpoint Control Register"
bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.long.byte 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.long 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled"
tree.end
tree.end
tree "DynamIQ Shared Unit"
tree "Cluster Control Registers"
if (((per.l(c15:0x003F))&0x2000)==0x00)
rgroup.long c15:0x003F++0x00
line.long 0x00 "CLUSTERCFR,Cluster Configuration Register"
bitfld.long 0x00 24.--27. "NPE,Number of processing elements" "1,2,?..."
newline
bitfld.long 0x00 17. "CRSP3,Core 3 Register slice present" "Not present,Present"
bitfld.long 0x00 16. "CRSP2,Core 2 Register slice present" "Not present,Present"
bitfld.long 0x00 15. "CRSP1,Core 1 Register slice present" "Not present,Present"
newline
bitfld.long 0x00 14. "CRSP0,Core 0 Register slice present" "Not present,Present"
bitfld.long 0x00 13. "BUS_INTERFACE_EXT,Bus interface extended" "Not extended,Extended"
bitfld.long 0x00 12. "PPP,Peripheral port present" "Not present,Present"
newline
bitfld.long 0x00 11. "ACP,ACP interface present" "Not present,Present"
bitfld.long 0x00 9.--10. "BUS_INTERFACE,Bus interface configuration" "Single 128-bit ACE,Dual 128-bit ACE,Single 128-bit CHI,Single 256-bit CHI"
bitfld.long 0x00 8. "SCU_L3_ECC,SCU-L3 is configured with ECC" "No ECC,ECC"
newline
bitfld.long 0x00 7. "L3_DATA_RAM_RS,L3 data RAM Register slice present" "Not present,Present"
bitfld.long 0x00 6. "L3_DATA_RAM_RL,L3 data RAM read latency" "2 cycles,3 cycles"
bitfld.long 0x00 5. "L3_DATA_RAM_WL,L3 data RAM write latency" "1 cycle,2 cycles"
newline
bitfld.long 0x00 4. "L3_CACHE_PRESENT,L3 cache present" "Not present,Present"
bitfld.long 0x00 0.--2. "NOC,Number of cores present in the cluster" "1,2,3,4,?..."
else
rgroup.long c15:0x003F++0x00
line.long 0x00 "CLUSTERCFR,Cluster Configuration Register"
bitfld.long 0x00 24.--27. "NPE,Number of processing elements" "1,2,?..."
newline
bitfld.long 0x00 17. "CRSP3,Core 3 Register slice present" "Not present,Present"
bitfld.long 0x00 16. "CRSP2,Core 2 Register slice present" "Not present,Present"
bitfld.long 0x00 15. "CRSP1,Core 1 Register slice present" "Not present,Present"
newline
bitfld.long 0x00 14. "CRSP0,Core 0 Register slice present" "Not present,Present"
bitfld.long 0x00 13. "BUS_INTERFACE_EXT,Bus interface extended" "Not extended,Extended"
bitfld.long 0x00 12. "PPP,Peripheral port present" "Not present,Present"
newline
bitfld.long 0x00 11. "ACP,ACP interface present" "Not present,Present"
bitfld.long 0x00 9.--10. "BUS_INTERFACE,Bus interface configuration" "Single 128-bit ACE,Dual 128-bit ACE,Single 128-bit CHI,Dual 256-bit CHI"
bitfld.long 0x00 8. "SCU_L3_ECC,SCU-L3 is configured with ECC" "No ECC,ECC"
newline
bitfld.long 0x00 7. "L3_DATA_RAM_RS,L3 data RAM Register slice present" "Not present,Present"
bitfld.long 0x00 6. "L3_DATA_RAM_RL,L3 data RAM read latency" "2 cycles,3 cycles"
bitfld.long 0x00 5. "L3_DATA_RAM_WL,L3 data RAM write latency" "1 cycle,2 cycles"
newline
bitfld.long 0x00 4. "L3_CACHE_PRESENT,L3 cache present" "Not present,Present"
bitfld.long 0x00 0.--2. "NOC,Number of cores present in the cluster" "1,2,3,4,?..."
endif
rgroup.long c15:0x013F++0x00
line.long 0x00 "CLUSTERIDR,Cluster Main Revision ID"
hexmask.long.byte 0x00 4.--7. 1. "VARIANT,Indicates the variant of the DSU"
hexmask.long.byte 0x00 0.--3. 1. "REVISION,Indicates the minor revision number of the DSU"
rgroup.long c15:0x023F++0x00
line.long 0x00 "CLUSTERREVIDR,Cluster ECO ID"
rgroup.long c15:0x033F++0x00
line.long 0x00 "CLUSTERACTLR,Cluster Auxiliary Control Register"
if (((per.l(c15:0x003F))&0x600)==(0x00||0x200))
group.long c15:0x043F++0x00
line.long 0x00 "CLUSTERECTLR,Cluster Extended Control Register"
bitfld.long 0x00 14. "CUEC,Cache UniqueClean eviction control" "Disabled,Enabled"
bitfld.long 0x00 8.--10. "PMD,Prefetch matching delay" "1,2,4,8,16,32,64,128"
bitfld.long 0x00 7. "DICA,Disable interconnect cacheable atomics" "No,Yes"
newline
bitfld.long 0x00 4. "IDPS,Interconnect data poisoning support" "Not supported,Supported"
bitfld.long 0x00 3. "CTEC,Clean/evict to external control disable" "No,Yes"
bitfld.long 0x00 2. "CFUCEC,Cache flush UniqueClean eviction control" "No,Yes"
newline
bitfld.long 0x00 0. "DNCWL,Disable non-cacheable write limit" "No,Yes"
else
group.long c15:0x043F++0x00
line.long 0x00 "CLUSTERECTLR,Cluster Extended Control Register"
bitfld.long 0x00 14. "CUEC,Cache UniqueClean eviction control" "Disabled,Enabled"
bitfld.long 0x00 8.--10. "PMD,Prefetch matching delay" "1,2,4,8,16,32,64,128"
bitfld.long 0x00 7. "DICA,Disable interconnect cacheable atomics" "No,Yes"
newline
bitfld.long 0x00 4. "IDPS,Interconnect data poisoning support" "Not supported,Supported"
bitfld.long 0x00 3. "CTEC,Clean/evict to external control disable" "No,Yes"
bitfld.long 0x00 2. "CFUCEC,Cache flush UniqueClean eviction control" "No,Yes"
endif
group.long c15:0x053F++0x00
line.long 0x00 "CLUSTERPWRCTLR,Cluster Power Control Register"
bitfld.long 0x00 4.--7. "CPPR,Cache portion power request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "FUNC_RET_CTRL,Duration of inactivity before the DSU uses CLUSTERPACTIVE" "Disabled,2 AT ticks,8 AT ticks,32 AT ticks,64 AT ticks,128 AT ticks,256 AT ticks,512 AT ticks"
group.long c15:0x063F++0x00
line.long 0x00 "CLUSTERPWRDN,Cluster Power Down Register"
bitfld.long 0x00 1. "MRR,Memory retention required" "Not required,Required"
bitfld.long 0x00 0. "CPR,Cluster power required" "Not required,Required"
rgroup.long c15:0x073F++0x00
line.long 0x00 "CLUSTERPWRSTAT,Cluster Power Status Register"
bitfld.long 0x00 4.--7. "CPPS,This bits indicates which cache portions are currently powered up and available" "No ways,Ways 0-3,Reserved,Ways 0-7,Reserved,Reserved,Reserved,Ways 0-11,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Ways 0-15"
bitfld.long 0x00 1. "RWPD,Enabled memory retention when all cores are powered down" "Disabled,Enabled"
bitfld.long 0x00 0. "DCPD,Disabled cluster power down when all cores are powered down" "No,Yes"
group.long c15:0x004F++0x00
line.long 0x00 "CLUSTERTHREADSID,Cluster Thread Scheme ID Register"
bitfld.long 0x00 0.--2. "SCHEME_ID_THREAD,Scheme ID for current thread" "0,1,2,3,4,5,6,7"
group.long c15:0x014F++0x00
line.long 0x00 "CLUSTERACPSID,Cluster ACP Scheme ID Register"
bitfld.long 0x00 0.--2. "SCHEME_ID_ACP,Scheme ID for ACP transactions" "0,1,2,3,4,5,6,7"
group.long c15:0x024F++0x00
line.long 0x00 "CLUSTERSTASHSID,Cluster Stash Scheme ID Register"
bitfld.long 0x00 0.--2. "SCHEME_ID_SR,Scheme ID for stash requests received from the interconnect" "0,1,2,3,4,5,6,7"
group.long c15:0x034F++0x00
line.long 0x00 "CLUSTERPARTCR,Cluster Partition Control Register"
bitfld.long 0x00 31. "W3_ID7,Way group 3 is assigned as private to scheme ID 7" "Not assigned,Assigned"
bitfld.long 0x00 30. "W2_ID7,Way group 2 is assigned as private to scheme ID 7" "Not assigned,Assigned"
bitfld.long 0x00 29. "W1_ID7,Way group 1 is assigned as private to scheme ID 7" "Not assigned,Assigned"
newline
bitfld.long 0x00 28. "W0_ID7,Way group 0 is assigned as private to scheme ID 7" "Not assigned,Assigned"
bitfld.long 0x00 27. "W3_ID6,Way group 3 is assigned as private to scheme ID 6" "Not assigned,Assigned"
bitfld.long 0x00 26. "W2_ID6,Way group 2 is assigned as private to scheme ID 6" "Not assigned,Assigned"
newline
bitfld.long 0x00 25. "W1_ID6,Way group 1 is assigned as private to scheme ID 6" "Not assigned,Assigned"
bitfld.long 0x00 24. "W0_ID6,Way group 0 is assigned as private to scheme ID 6" "Not assigned,Assigned"
bitfld.long 0x00 23. "W3_ID5,Way group 3 is assigned as private to scheme ID 5" "Not assigned,Assigned"
newline
bitfld.long 0x00 22. "W2_ID5,Way group 2 is assigned as private to scheme ID 5" "Not assigned,Assigned"
bitfld.long 0x00 21. "W1_ID5,Way group 1 is assigned as private to scheme ID 5" "Not assigned,Assigned"
bitfld.long 0x00 20. "W0_ID5,Way group 0 is assigned as private to scheme ID 5" "Not assigned,Assigned"
newline
bitfld.long 0x00 19. "W3_ID4,Way group 3 is assigned as private to scheme ID 4" "Not assigned,Assigned"
bitfld.long 0x00 18. "W2_ID4,Way group 2 is assigned as private to scheme ID 4" "Not assigned,Assigned"
bitfld.long 0x00 17. "W1_ID4,Way group 1 is assigned as private to scheme ID 4" "Not assigned,Assigned"
newline
bitfld.long 0x00 16. "W0_ID4,Way group 0 is assigned as private to scheme ID 4" "Not assigned,Assigned"
bitfld.long 0x00 15. "W3_ID3,Way group 3 is assigned as private to scheme ID 3" "Not assigned,Assigned"
bitfld.long 0x00 14. "W2_ID3,Way group 2 is assigned as private to scheme ID 3" "Not assigned,Assigned"
newline
bitfld.long 0x00 13. "W1_ID3,Way group 1 is assigned as private to scheme ID 3" "Not assigned,Assigned"
bitfld.long 0x00 12. "W0_ID3,Way group 0 is assigned as private to scheme ID 3" "Not assigned,Assigned"
bitfld.long 0x00 11. "W3_ID2,Way group 3 is assigned as private to scheme ID 2" "Not assigned,Assigned"
newline
bitfld.long 0x00 10. "W2_ID2,Way group 2 is assigned as private to scheme ID 2" "Not assigned,Assigned"
bitfld.long 0x00 9. "W1_ID2,Way group 1 is assigned as private to scheme ID 2" "Not assigned,Assigned"
bitfld.long 0x00 8. "W0_ID2,Way group 0 is assigned as private to scheme ID 2" "Not assigned,Assigned"
newline
bitfld.long 0x00 7. "W3_ID1,Way group 3 is assigned as private to scheme ID 1" "Not assigned,Assigned"
bitfld.long 0x00 6. "W2_ID1,Way group 2 is assigned as private to scheme ID 1" "Not assigned,Assigned"
bitfld.long 0x00 5. "W1_ID1,Way group 1 is assigned as private to scheme ID 1" "Not assigned,Assigned"
newline
bitfld.long 0x00 4. "W0_ID1,Way group 0 is assigned as private to scheme ID 1" "Not assigned,Assigned"
bitfld.long 0x00 3. "W3_ID0,Way group 3 is assigned as private to scheme ID 0" "Not assigned,Assigned"
bitfld.long 0x00 2. "W2_ID0,Way group 2 is assigned as private to scheme ID 0" "Not assigned,Assigned"
newline
bitfld.long 0x00 1. "W1_ID0,Way group 1 is assigned as private to scheme ID 0" "Not assigned,Assigned"
bitfld.long 0x00 0. "W0_ID0,Way group 0 is assigned as private to scheme ID 0" "Not assigned,Assigned"
newline
group.long c15:0x044F++0x00
line.long 0x00 "CLUSTERBUSQOS,Cluster Bus QoS Control Register"
bitfld.long 0x00 28.--31. "CHI_BUS_QOS_SCHEME_ID7,Value driven on the CHI bus QoS field for scheme ID 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "CHI_BUS_QOS_SCHEME_ID6,Value driven on the CHI bus QoS field for scheme ID 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 20.--23. "CHI_BUS_QOS_SCHEME_ID5,Value driven on the CHI bus QoS field for scheme ID 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 16.--19. "CHI_BUS_QOS_SCHEME_ID4,Value driven on the CHI bus QoS field for scheme ID 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "CHI_BUS_QOS_SCHEME_ID3,Value driven on the CHI bus QoS field for scheme ID 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "CHI_BUS_QOS_SCHEME_ID2,Value driven on the CHI bus QoS field for scheme ID 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "CHI_BUS_QOS_SCHEME_ID1,Value driven on the CHI bus QoS field for scheme ID 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "CHI_BUS_QOS_SCHEME_ID0,Value driven on the CHI bus QoS field for scheme ID 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long c15:0x054F++0x00
line.long 0x00 "CLUSTERL3HIT,Cluster L3 Hit Counter Register"
group.long c15:0x064F++0x00
line.long 0x00 "CLUSTERL3MISS,Cluster L3 Miss Counter Register"
group.long c15:0x074F++0x00
line.long 0x00 "CLUSTERTHREADSIDOVR,Cluster Thread Scheme ID Override Register"
bitfld.long 0x00 16.--18. "SCHEME_ID_MASK,A bit set in the mask causes the matching bit to be taken from this Register rather than from the CLUSTERTHREADSID_EL1 Register" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "SCHEME_ID_THREAD,Scheme ID for this thread if masked" "0,1,2,3,4,5,6,7"
tree.end
tree "Error System Registers"
rgroup.long c15:0x0035++0x00
line.long 0x00 "ERRIDR,Error Record ID Register"
hexmask.long.word 0x00 0.--15. 1. "NUM,Number of records that can be accessed through the Error Record system Registers"
group.long c15:0x0135++0x00
line.long 0x00 "ERRSELR,Error Record Select Register"
bitfld.long 0x00 0. "SEL,Selects the record accessed through the Error Record system Registers" "Record 0 - Core,Record 1 - DSU"
if (((per.l(c15:0x0135))&0x01)==0x00)
if CORENAME()=="CORTEXA55"
rgroup.long c15:0x0345++0x00
line.long 0x00 "ERXADDR,Selected Error Record Address Register"
rgroup.long c15:0x0745++0x00
line.long 0x00 "ERXADDR2,Selected Error Record Address Register 2"
group.long c15:0x0145++0x00
line.long 0x00 "ERXCTLR,Selected Error Record Control Register"
bitfld.long 0x00 8. "CFI,Fault handling interrupt for corrected errors enable" "Disabled,Enabled"
bitfld.long 0x00 3. "FI,Fault handling interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 2. "UI,Uncorrected error recovery interrupt enable" "Disabled,Enabled"
newline
bitfld.long 0x00 0. "ED,Enable error detection" "Disabled,Enabled"
rgroup.long c15:0x0545++0x00
line.long 0x00 "ERXCTLR2,Selected Error Record Control Register 2"
rgroup.long c15:0x0045++0x00
line.long 0x00 "ERXFR,Selected Error Record Feature Register"
bitfld.long 0x00 18.--19. "CEO,Previous error syndrome is kept on a second corrected error" "Yes,?..."
bitfld.long 0x00 16.--17. "DUI,Error recovery interrupt for deferred errors" "Not supported,?..."
bitfld.long 0x00 15. "RP,Indicates whether a repeat counter is implemented" "Reserved,1st and 2nd counter implemented"
newline
bitfld.long 0x00 12.--14. "CEC,Defines whether the node implements a standard CE counter mechanism in ERR<n>MISC0" "Reserved,Reserved,8bit error counter,?..."
bitfld.long 0x00 10.--11. "CFI,Fault handling interrupt for corrected errors" "Reserved,Reserved,Controllable,?..."
bitfld.long 0x00 8.--9. "UE,Uncorrected error reporting" "Reserved,Supported,?..."
newline
bitfld.long 0x00 6.--7. "FI,Fault handling interrupt" "Reserved,Reserved,Controllable,?..."
bitfld.long 0x00 4.--5. "UI,Uncorrected error recovery interrupt" "Reserved,Reserved,Controllable,?..."
bitfld.long 0x00 2.--3. "DE,Deferred errors" "Reserved,Reserved,Controllable,?..."
newline
bitfld.long 0x00 0.--1. "ED,Error detection and correction" "Reserved,Reserved,Controllable,?..."
rgroup.long c15:0x0445++0x00
line.long 0x00 "ERXFR2,Selected Error Record Feature Register 2"
group.long c15:0x0055++0x00
line.long 0x00 "ERXMISC0,Selected Error Miscellaneous Register 0"
bitfld.long 0x00 28.--31. "WAY,Indicates the way that contained the error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 6.--18. 1. "INDX,Indicates the index that contained the error"
newline
bitfld.long 0x00 1.--3. "L,Indicates the level that contained the error" "Level 1,Level 2,?..."
bitfld.long 0x00 0. "IND,Indicates the type of cache that contained the error" "Data cache(L1)/Unified cache(L2)/TLB,Instruction cache(L1)"
group.long c15:0x0155++0x00
line.long 0x00 "ERXMISC1,Selected Error Miscellaneous Register 1"
bitfld.long 0x00 15. "OFO,Other Error Count Overflow" "No overflow,Overflow"
hexmask.long.byte 0x00 8.--14. 1. "CECO,Other Error Count"
bitfld.long 0x00 7. "OFR,Repeat Error Count Overflow" "No overflow,Overflow"
newline
hexmask.long.byte 0x00 0.--6. 1. "CECR,Repeat Error Count"
rgroup.long c15:0x0455++0x00
line.long 0x00 "ERXMISC2,Selected Error Miscellaneous Register 2"
rgroup.long c15:0x0555++0x00
line.long 0x00 "ERXMISC3,Selected Error Miscellaneous Register 3"
group.long c15:0x0245++0x00
line.long 0x00 "ERXSTATUS,Selected Error Record Primary Status Register"
bitfld.long 0x00 31. "AV,Address Valid" "Not valid,?..."
bitfld.long 0x00 30. "V,Status Register valid" "Not valid,Valid"
bitfld.long 0x00 29. "UE,Uncorrected Error" "No error,>=1 error"
newline
bitfld.long 0x00 28. "ER,Error Reported" "No error,Error"
bitfld.long 0x00 27. "OF,Error overflow" "No error,>1 error"
bitfld.long 0x00 26. "MV,Miscellaneous Registers Valid" "Not valid,Valid"
newline
bitfld.long 0x00 24.--25. "CE,Corrected Errors" "No error,Reserved,>=1 error,?..."
bitfld.long 0x00 23. "DE,Deferred Errors" "No error,>=1 error"
bitfld.long 0x00 22. "PN,Poison" "No distinction,?..."
newline
bitfld.long 0x00 20.--21. "UET,Uncorrected Error Type" "Uncontainable,?..."
abitfld.long 0x00 8.--15. "IERR,Implementation defined error code" "0x00=No error/Error not on dirty RAM,0x01=Error on L1 dirty RAM"
abitfld.long 0x00 0.--7. "SERR,Primary error code" "0x00=No error,0x02=ECC/Internal data buffer,0x06=ECC/Cache data RAM,0x07=ECC/Cache tag/Dirty RAM,0x08=Parity error/TLB data RAM,0x09=Parity error/TLB tag RAM,0x15=Deferred error from slave,?..."
group.long c15:0x022F++0x00
line.long 0x00 "ERXPFGCDN,Selected Error Pseudo Fault Generation Count Down Register"
group.long c15:0x012F++0x00
line.long 0x00 "ERXPFGCTL,Selected Error Pseudo Fault Generation Control Register"
bitfld.long 0x00 31. "CDNEN,Count down enable" "Disabled,Enabled"
bitfld.long 0x00 30. "R,Restartable bit. Controls whether Error Generation Counter restarts from the ERR0PFGCDNR value or stops after reaching 0" "Counter stops,Counter restarts"
bitfld.long 0x00 6. "CE,Corrected Error generation enable" "Disabled,Enabled"
newline
bitfld.long 0x00 5. "DE,Deferred Error generation enable" "Disabled,Enabled"
bitfld.long 0x00 3. "UER,Signaled or Recoverable Error generation enable" "Disabled,Enabled"
newline
bitfld.long 0x00 1. "UC,Uncontainable error generation enable" "Disabled,Enabled"
rgroup.long c15:0x002F++0x00
line.long 0x00 "ERXPFGF,Selected Pseudo Fault Generation Feature Register"
bitfld.long 0x00 31. "PFG,Pseudo Fault Generation" "Not supported,Supported"
bitfld.long 0x00 30. "R,Restartable bit" "Not supported,Controllable"
bitfld.long 0x00 6. "CE,Corrected Error generation" "Not supported,Controllable"
newline
bitfld.long 0x00 5. "DE,Deferred Error generation" "Not supported,Controllable"
bitfld.long 0x00 4. "UEO,Latent or Restartable Error generation" "Not supported,?..."
bitfld.long 0x00 3. "UER,Signaled or Recoverable Error generation" "Not supported,Controllable"
newline
bitfld.long 0x00 2. "UEU,Unrecoverable Error generation" "Not supported,?..."
bitfld.long 0x00 1. "UC,Uncontainable Error generation" "Not supported,Controllable"
elif CORENAME()=="CORTEXA75"
group.long c15:0x0345++0x00
line.long 0x00 "ERXADDR,Selected Error Record Address Register"
bitfld.long 0x00 31. "NS,Non-secure attribute" "Secure,Non-secure"
bitfld.long 0x00 30. "SI,Secure incorrect" "Correct,Incorrect"
bitfld.long 0x00 29. "AI,Address incomplete or incorrect" "Correct,Not correct"
newline
hexmask.long.word 0x00 0.--31. 0x01 "PADDR[43:32],Physical address bits [43:32]"
group.long c15:0x0745++0x00
line.long 0x00 "ERXADDR2,Selected Error Record Address Register 2"
hexmask.long 0x00 0.--31. 0x01 "PADDR[31:0],Physical address"
group.long c15:0x0145++0x00
line.long 0x00 "ERXCTLR,Selected Error Record Control Register"
bitfld.long 0x00 8. "CFI,Fault handling interrupt for corrected errors enable" "Disabled,Enabled"
bitfld.long 0x00 3. "FI,Fault handling interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 2. "UI,Uncorrected error recovery interrupt enable" "Disabled,Enabled"
newline
bitfld.long 0x00 0. "ED,Enable error detection" "Disabled,Enabled"
rgroup.long c15:0x0545++0x00
line.long 0x00 "ERXCTLR2,Selected Error Record Control Register 2"
rgroup.long c15:0x0045++0x00
line.long 0x00 "ERXFR,Selected Error Record Feature Register"
bitfld.long 0x00 18.--19. "CEO,Previous error syndrome is kept on a second corrected error" "Yes,?..."
bitfld.long 0x00 16.--17. "DUI,Error recovery interrupt for deferred errors" "Not supported,?..."
bitfld.long 0x00 15. "RP,Indicates whether a repeat counter is implemented" "Reserved,1st and 2nd counter implemented"
newline
bitfld.long 0x00 12.--14. "CEC,Defines whether the node implements a standard CE counter mechanism in ERR<n>MISC0" "Reserved,Reserved,8bit error counter,?..."
bitfld.long 0x00 10.--11. "CFI,Fault handling interrupt for corrected errors" "Reserved,Reserved,Controllable,?..."
bitfld.long 0x00 8.--9. "UE,Uncorrected error reporting" "Reserved,Supported,?..."
newline
bitfld.long 0x00 6.--7. "FI,Fault handling interrupt" "Reserved,Reserved,Controllable,?..."
bitfld.long 0x00 4.--5. "UI,Uncorrected error recovery interrupt" "Reserved,Reserved,Controllable,?..."
newline
bitfld.long 0x00 0.--1. "ED,Error detection and correction" "Reserved,Reserved,Controllable,?..."
rgroup.long c15:0x0445++0x00
line.long 0x00 "ERXFR2,Selected Error Record Feature Register 2"
group.long c15:0x0055++0x00
line.long 0x00 "ERXMISC0,Selected Error Miscellaneous Register 0"
bitfld.long 0x00 28.--31. "WAY,Indicates the way that contained the error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 6.--18. 1. "INDX,Indicates the index that contained the error"
bitfld.long 0x00 5. "TLBRAM,Indicates in which TLB RAM block the error occurs" "RAM0,RAM1"
newline
bitfld.long 0x00 1.--3. "L,Indicates the level that contained the error" "Level 1,Level 2,?..."
bitfld.long 0x00 0. "IND,Indicates the type of cache that contained the error" "Data cache(L1)/Unified cache(L2)/TLB,Instruction cache(L1)"
group.long c15:0x0155++0x00
line.long 0x00 "ERXMISC1,Selected Error Miscellaneous Register 1"
hexmask.long.word 0x00 0.--15. 1. "CEC,Corrected Error Count"
rgroup.long c15:0x0455++0x00
line.long 0x00 "ERXMISC2,Selected Error Miscellaneous Register 2"
rgroup.long c15:0x0555++0x00
line.long 0x00 "ERXMISC3,Selected Error Miscellaneous Register 3"
group.long c15:0x0245++0x00
line.long 0x00 "ERXSTATUS,Selected Error Record Primary Status Register"
bitfld.long 0x00 31. "AV,Address Valid" "Not valid,Valid"
bitfld.long 0x00 30. "V,Status Register valid" "Not valid,Valid"
bitfld.long 0x00 29. "UE,Uncorrected Error" "No error,>=1 error"
newline
bitfld.long 0x00 28. "ER,Error Reported" "No error,Error"
bitfld.long 0x00 27. "OF,Error overflow" "No error,>1 error"
bitfld.long 0x00 26. "MV,Miscellaneous Registers Valid" "Not valid,Valid"
newline
bitfld.long 0x00 24.--25. "CE,Corrected Errors" "No error,Reserved,>=1 error,?..."
bitfld.long 0x00 23. "DE,Deferred Errors" "No error,>=1 error"
bitfld.long 0x00 22. "PN,Poison" "No distinction,?..."
newline
bitfld.long 0x00 20.--21. "UET,Uncorrected Error Type" "Uncontainable,?..."
abitfld.long 0x00 0.--7. "SERR,Primary error code" "0x00=No error,0x02=ECC/Internal data buffer,0x06=ECC/Cache data RAM,0x07=ECC/Cache tag/Dirty RAM,0x08=Parity error/TLB data RAM,0x09=Parity error/TLB tag RAM,0x15=Deferred error from slave,?..."
group.long c15:0x022F++0x00
line.long 0x00 "ERXPFGCDN,Selected Error Pseudo Fault Generation Count Down Register"
group.long c15:0x012F++0x00
line.long 0x00 "ERXPFGCTL,Selected Error Pseudo Fault Generation Control Register"
bitfld.long 0x00 31. "CDNEN,Count down enable" "Disabled,Enabled"
bitfld.long 0x00 30. "R,Restartable bit. Controls whether Error Generation Counter restarts from the ERR0PFGCDNR value or stops after reaching 0" "Counter stops,Counter restarts"
bitfld.long 0x00 6. "CE,Corrected Error generation enable" "Disabled,Enabled"
newline
bitfld.long 0x00 5. "DE,Deferred Error generation enable" "Disabled,Enabled"
bitfld.long 0x00 3. "UER,Signaled or Recoverable Error generation enable" "Disabled,Enabled"
newline
bitfld.long 0x00 1. "UC,Uncontainable error generation enable" "Disabled,Enabled"
rgroup.long c15:0x002F++0x00
line.long 0x00 "ERXPFGF,Selected Pseudo Fault Generation Feature Register"
bitfld.long 0x00 31. "PFG,Pseudo Fault Generation" "Reserved,Supported"
bitfld.long 0x00 30. "R,Restartable bit" "Reserved,Controllable"
bitfld.long 0x00 6. "CE,Corrected Error generation" "Reserved,Controllable"
newline
bitfld.long 0x00 5. "DE,Deferred Error generation" "Reserved,Controllable"
bitfld.long 0x00 4. "UEO,Latent or Restartable Error generation" "Not supported,?..."
bitfld.long 0x00 3. "UER,Signaled or Recoverable Error generation" "Not supported,?..."
newline
bitfld.long 0x00 2. "UEU,Unrecoverable Error generation" "Not supported,?..."
bitfld.long 0x00 1. "UC,Uncontainable Error generation" "Reserved,Controllable"
endif
else
rgroup.long c15:0x0345++0x00
line.long 0x00 "ERXADDR,Selected Error Record Address Register"
rgroup.long c15:0x0745++0x00
line.long 0x00 "ERXADDR2,Selected Error Record Address Register 2"
group.long c15:0x0145++0x00
line.long 0x00 "ERXCTLR,Selected Error Record Control Register"
bitfld.long 0x00 8. "CFI,Fault handling interrupt for corrected errors enable" "Disabled,Enabled"
bitfld.long 0x00 3. "FI,Fault handling interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 2. "UI,Uncorrected error recovery interrupt enable" "Disabled,Enabled"
newline
bitfld.long 0x00 0. "ED,Error reporting and logging enable" "Disabled,Enabled"
rgroup.long c15:0x0545++0x00
line.long 0x00 "ERXCTLR2,Selected Error Record Control Register 2"
rgroup.long c15:0x0045++0x00
line.long 0x00 "ERXFR,Selected Error Record Feature Register"
bitfld.long 0x00 18.--19. "CEO,Previous error syndrome is kept on a second corrected error" "Yes,?..."
bitfld.long 0x00 16.--17. "DUI,Error recovery interrupt for deferred errors" "Not supported,?..."
bitfld.long 0x00 15. "RP,Indicates whether a repeat counter is implemented" "Reserved,1st and 2nd counter implemented"
newline
bitfld.long 0x00 12.--14. "CEC,Defines whether the node implements a standard CE counter mechanism in ERR<n>MISC0" "Reserved,Reserved,8bit error counter,?..."
bitfld.long 0x00 10.--11. "CFI,Fault handling interrupt for corrected errors" "Reserved,Reserved,Controllable,?..."
bitfld.long 0x00 8.--9. "UE,Uncorrected error reporting" "Reserved,Supported,?..."
newline
bitfld.long 0x00 6.--7. "FI,Fault handling interrupt" "Reserved,Reserved,Controllable,?..."
bitfld.long 0x00 4.--5. "UI,Uncorrected error recovery interrupt" ",Reserved,Controllable,?..."
bitfld.long 0x00 2.--3. "DE,Deferred errors" "Reserved,Always enabled,?..."
newline
bitfld.long 0x00 0.--1. "ED,Error detection and correction" "Reserved,Reserved,Controllable,?..."
rgroup.long c15:0x0445++0x00
line.long 0x00 "ERXFR2,Selected Error Record Feature Register 2"
group.long c15:0x0055++0x00
line.long 0x00 "ERXMISC0,Selected Error Miscellaneous Register 0"
bitfld.long 0x00 28.--31. "WAY,Indicates the way that contained the error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 6.--18. 1. "INDX,Indicates the index that contained the error"
newline
bitfld.long 0x00 1.--3. "L,Indicates the level that contained the error" "Reserved,Reserved,Level 3,?..."
bitfld.long 0x00 0. "IND,Indicates the type of cache that contained the error" "L3 cache,"
group.long c15:0x0155++0x00
line.long 0x00 "ERXMISC1,Selected Error Miscellaneous Register 1"
bitfld.long 0x00 15. "OFO,Other Error Count Overflow" "No overflow,Overflow"
hexmask.long.byte 0x00 8.--14. 1. "CECO,Other Error Count"
bitfld.long 0x00 7. "OFR,Repeat Error Count Overflow" "No overflow,Overflow"
newline
hexmask.long.byte 0x00 0.--6. 1. "CECR,Repeat Error Count"
rgroup.long c15:0x0455++0x00
line.long 0x00 "ERXMISC2,Selected Error Miscellaneous Register 2"
rgroup.long c15:0x0555++0x00
line.long 0x00 "ERXMISC3,Selected Error Miscellaneous Register 3"
group.long c15:0x0245++0x00
line.long 0x00 "ERXSTATUS,Selected Error Record Primary Status Register"
bitfld.long 0x00 31. "AV,Address Valid" "Not valid,?..."
bitfld.long 0x00 30. "V,Status Register valid" "Not valid,Valid"
bitfld.long 0x00 29. "UE,Uncorrected Error" "No error,>=1 error"
newline
bitfld.long 0x00 28. "ER,Error Reported" "No error,?..."
bitfld.long 0x00 27. "OF,Error overflow" "No error,>1 error"
bitfld.long 0x00 26. "MV,Miscellaneous Registers Valid" "Not valid,Valid"
newline
bitfld.long 0x00 24.--25. "CE,Corrected Errors" "No error,Reserved,>=1 error,?..."
bitfld.long 0x00 23. "DE,Deferred Errors" "No error,>=1 error"
bitfld.long 0x00 22. "PN,Poison" "No distinction,Uncorrected error"
newline
bitfld.long 0x00 20.--21. "UET,Uncorrected Error Type" "Uncontainable,?..."
abitfld.long 0x00 8.--15. "IERR,Implementation defined error code" "0x00=No error/Error on other RAMs,0x02=Error on a L3 snoop filter RAM"
abitfld.long 0x00 0.--7. "SERR,Primary error code" "0x00=No error,0x02=ECC/Internal data buffer,0x06=ECC/Cache data RAM,0x07=ECC/Cache tag/Dirty RAM,0x12=Bus error"
group.long c15:0x022F++0x00
line.long 0x00 "ERXPFGCDN,Selected Error Pseudo Fault Generation Count Down Register"
group.long c15:0x012F++0x00
line.long 0x00 "ERXPFGCTL,Selected Error Pseudo Fault Generation Control Register"
bitfld.long 0x00 31. "CDNEN,Count down enable" "Disabled,Enabled"
bitfld.long 0x00 30. "R,Restartable bit. Controls whether Error Generation Counter restarts from the ERR0PFGCDNR value or stops after reaching 0" "Counter stops,Counter restarts"
bitfld.long 0x00 6. "CE,Corrected Error generation enable" "Disabled,Enabled"
newline
bitfld.long 0x00 5. "DE,Deferred Error generation enable" "Disabled,Enabled"
bitfld.long 0x00 1. "UC,Uncontainable error generation enable" "Disabled,Enabled"
rgroup.long c15:0x002F++0x00
line.long 0x00 "ERXPFGF,Selected Pseudo Fault Generation Feature Register"
bitfld.long 0x00 31. "PFG,Pseudo Fault Generation" "Not supported,Supported"
bitfld.long 0x00 30. "R,Restartable bit" "Not supported,Controllable"
bitfld.long 0x00 6. "CE,Corrected Error generation" "Not supported,Controllable"
newline
bitfld.long 0x00 5. "DE,Deferred Error generation" "Not supported,Controllable"
bitfld.long 0x00 4. "UEO,Latent or Restartable Error generation" "Not supported,Controllable"
bitfld.long 0x00 3. "UER,Signaled or Recoverable Error generation" "Not supported,Controllable"
newline
bitfld.long 0x00 2. "UEU,Unrecoverable Error generation" "Not supported,Controllable"
bitfld.long 0x00 1. "UC,Uncontainable Error generation" "Not supported,Controllable"
endif
tree.end
tree "Cluster PMU Registers"
group.long c15:0x005F++0x00
line.long 0x00 "CLUSTERPMCR,Cluster Performance Monitors Control Register"
hexmask.long.byte 0x00 24.--31. 1. "IMP,Implementer code"
hexmask.long.byte 0x00 16.--23. 1. "IDCODE,Identification code"
bitfld.long 0x00 11.--15. "N,Number of counters implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 4. "X,Export of events Enable" "Disabled,"
bitfld.long 0x00 2. "C,Clock Counter Reset" "No reset,Reset"
bitfld.long 0x00 1. "P,Event Counter Reset" "No reset,Reset"
newline
bitfld.long 0x00 0. "E,All Counters Enable" "Disabled,Enabled"
newline
group.long c15:0x015F++0x00
line.long 0x00 "CLUSTERPMCNTENSET,Cluster Count Enable Set Register"
bitfld.long 0x00 31. "C,Enables the cycle counter Register [Read/Write]" "Disabled/No effect,Enabled/Enable"
newline
bitfld.long 0x00 5. "P5,Event counter PMN 5 enable bit [Read/Write]" "Disabled/No effect,Enabled/Enable"
bitfld.long 0x00 4. "P4,Event counter PMN 4 enable bit [Read/Write]" "Disabled/No effect,Enabled/Enable"
bitfld.long 0x00 3. "P3,Event counter PMN 3 enable bit [Read/Write]" "Disabled/No effect,Enabled/Enable"
newline
bitfld.long 0x00 2. "P2,Event counter PMN 2 enable bit [Read/Write]" "Disabled/No effect,Enabled/Enable"
bitfld.long 0x00 1. "P1,Event counter PMN 1 enable bit [Read/Write]" "Disabled/No effect,Enabled/Enable"
bitfld.long 0x00 0. "P0,Event counter PMN 0 enable bit [Read/Write]" "Disabled/No effect,Enabled/Enable"
group.long c15:0x025F++0x00
line.long 0x00 "CLUSTERPMCNTENCLR,Cluster Count Enable Clear Register"
bitfld.long 0x00 31. "C,Disables the cycle counter Register [Read/Write]" "Disabled/No effect,Enabled/Disable"
newline
bitfld.long 0x00 5. "P5,Event counter PMN 5 disable bit [Read/Write]" "Disabled/No effect,Enabled/Disable"
bitfld.long 0x00 4. "P4,Event counter PMN 4 disable bit [Read/Write]" "Disabled/No effect,Enabled/Disable"
bitfld.long 0x00 3. "P3,Event counter PMN 3 disable bit [Read/Write]" "Disabled/No effect,Enabled/Disable"
newline
bitfld.long 0x00 2. "P2,Event counter PMN 2 disable bit [Read/Write]" "Disabled/No effect,Enabled/Disable"
bitfld.long 0x00 1. "P1,Event counter PMN 1 disable bit [Read/Write]" "Disabled/No effect,Enabled/Disable"
bitfld.long 0x00 0. "P0,Event counter PMN 0 disable bit [Read/Write]" "Disabled/No effect,Enabled/Disable"
group.long c15:0x035F++0x00
line.long 0x00 "CLUSTERPMOVSSET,Cluster Overflow Flag Status Set"
bitfld.long 0x00 31. "C,PMCCNTR overflow bit [Read/Write]" "No overflow/No effect,Overflow/Set"
newline
bitfld.long 0x00 5. "P5,PMN5 Overflow set bit [Read/Write]" "No overflow/No effect,Overflow/Set"
bitfld.long 0x00 4. "P4,PMN4 Overflow set bit [Read/Write]" "No overflow/No effect,Overflow/Set"
bitfld.long 0x00 3. "P3,PMN3 Overflow set bit [Read/Write]" "No overflow/No effect,Overflow/Set"
newline
bitfld.long 0x00 2. "P2,PMN2 Overflow set bit [Read/Write]" "No overflow/No effect,Overflow/Set"
bitfld.long 0x00 1. "P1,PMN1 Overflow set bit [Read/Write]" "No overflow/No effect,Overflow/Set"
bitfld.long 0x00 0. "P0,PMN0 Overflow set bit [Read/Write]" "No overflow/No effect,Overflow/Set"
group.long c15:0x045F++0x00
line.long 0x00 "CLUSTERPMOVSCLR,Cluster Overflow Flag Status Clear"
eventfld.long 0x00 31. "C,PMCCNTR overflow bit [Read/Write]" "No overflow/No effect,Overflow/Clear"
newline
eventfld.long 0x00 5. "P5,PMN5 overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear"
eventfld.long 0x00 4. "P4,PMN4 Overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear"
eventfld.long 0x00 3. "P3,PMN3 Overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear"
newline
eventfld.long 0x00 2. "P2,PMN2 Overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear"
eventfld.long 0x00 1. "P1,PMN1 Overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear"
eventfld.long 0x00 0. "P0,PMN0 Overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear"
group.long c15:0x055F++0x00
line.long 0x00 "CLUSTERPMSELR,Cluster Event Counter Selection Register"
bitfld.long 0x00 0.--4. "SEL,Current event counter select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long c15:0x065F++0x00
line.long 0x00 "CLUSTERPMINTENSET,Cluster Interrupt Enable Set Register"
bitfld.long 0x00 31. "C,PMCCNTR Overflow Interrupt Request Enable [Read/Write]" "Disabled/No effect,Enabled/Enable"
newline
bitfld.long 0x00 5. "P5,PMCNT5 Overflow Interrupt Request Enable [Read/Write]" "Disabled/No effect,Enabled/Enable"
bitfld.long 0x00 4. "P4,PMCNT4 Overflow Interrupt Request Enable [Read/Write]" "Disabled/No effect,Enabled/Enable"
bitfld.long 0x00 3. "P3,PMCNT3 Overflow Interrupt Request Enable [Read/Write]" "Disabled/No effect,Enabled/Enable"
newline
bitfld.long 0x00 2. "P2,PMCNT2 Overflow Interrupt Request Enable [Read/Write]" "Disabled/No effect,Enabled/Enable"
bitfld.long 0x00 1. "P1,PMCNT1 Overflow Interrupt Request Enable [Read/Write]" "Disabled/No effect,Enabled/Enable"
bitfld.long 0x00 0. "P0,PMCNT0 Overflow Interrupt Request Enable [Read/Write]" "Disabled/No effect,Enabled/Enable"
group.long c15:0x075F++0x00
line.long 0x00 "CLUSTERPMINTENCLR,Cluster Interrupt Enable Clear Register"
eventfld.long 0x00 31. "C,PMCCNTR Overflow Interrupt Request Disable [Read/Write]" "Disabled/No effect,Enabled/Disable"
newline
eventfld.long 0x00 5. "P5,PMCNT5 Overflow Interrupt Disable [Read/Write]" "Disabled/No effect,Enabled/Disable"
eventfld.long 0x00 4. "P4,PMCNT4 Overflow Interrupt Disable [Read/Write]" "Disabled/No effect,Enabled/Disable"
eventfld.long 0x00 3. "P3,PMCNT3 Overflow Interrupt Disable [Read/Write]" "Disabled/No effect,Enabled/Disable"
newline
eventfld.long 0x00 2. "P2,PMCNT2 Overflow Interrupt Disable [Read/Write]" "Disabled/No effect,Enabled/Disable"
eventfld.long 0x00 1. "P1,PMCNT1 Overflow Interrupt Disable [Read/Write]" "Disabled/No effect,Enabled/Disable"
eventfld.long 0x00 0. "P0,PMCNT0 Overflow Interrupt Disable [Read/Write]" "Disabled/No effect,Enabled/Disable"
group.quad c15:0x006F++0x01
line.quad 0x00 "CLUSTERPMCCNTR,Cluster Performance Monitors Cycle Counter"
if (((per.l(c15:0x016F))&0x80000000)==0x80000000)
group.long c15:0x016F++0x00
line.long 0x00 "CLUSTERPMXEVTYPER,Cluster Selected Event Type and Filter Register"
bitfld.long 0x00 31. "S,Secure events filtering bit. Controls counting of events that are generated by Secure transactions" "Count Secure events,Not count Secure events"
bitfld.long 0x00 29. "NS,Non-secure events filtering bit. Controls counting of events that are generated by Non-secure transactions" "Not count Non-secure events,Count Non-secure events"
hexmask.long.word 0x00 0.--15. 1. "EVTCOUNT,Event number"
else
group.long c15:0x016F++0x00
line.long 0x00 "CLUSTERPMXEVTYPER,Cluster Selected Event Type and Filter Register"
bitfld.long 0x00 31. "S,Secure events filtering bit. Controls counting of events that are generated by Secure transactions" "Count Secure events,Not count Secure events"
bitfld.long 0x00 29. "NS,Non-secure events filtering bit. Controls counting of events that are generated by Non-secure transactions" "Count Non-secure events,Not count Non-secure events"
hexmask.long.word 0x00 0.--15. 1. "EVTCOUNT,Event number"
endif
group.long c15:0x026F++0x00
line.long 0x00 "CLUSTERPMXEVCNTR,Cluster Selected Event Counter Register"
group.long c15:0x036F++0x00
line.long 0x00 "CLUSTERPMMDCR,Cluster Monitor Debug Configuration Register"
bitfld.long 0x00 0. "SPME,Secure Performance Monitors Enable" "Disabled,Enabled"
tree.open "Common Event Identification Registers"
rgroup.long c15:0x046F++0x00
line.long 0x00 "CLUSTERPMCEID0,Cluster Common Event Identification ID0 Register"
bitfld.long 0x00 30. "CHAIN,Chain" "Reserved,Implemented"
bitfld.long 0x00 29. "BUS_CYCLES,Bus cycle" "Reserved,Implemented"
bitfld.long 0x00 26. "MEMORY_ERROR,Local memory error" "Reserved,Implemented"
newline
bitfld.long 0x00 25. "BUS_ACCESS,Bus access" "Reserved,Implemented"
bitfld.long 0x00 17. "CPU_CYCLES,CPU Cycle" "Reserved,Implemented"
rgroup.long c15:0x056F++0x00
line.long 0x00 "CLUSTERPMCEID1,Cluster Common Event Identification ID1 Register"
bitfld.long 0x00 12. "L3D_CACHE_WB,Attributable Level 3 data or unified cache write-back" "Reserved,Implemented"
bitfld.long 0x00 11. "L3D_CACHE,Attributable Level 3 data or unified cache access" "Reserved,Implemented"
bitfld.long 0x00 10. "L3D_CACHE_REFILL,Attributable Level 3 data or unified cache refill" "Reserved,Implemented"
newline
bitfld.long 0x00 9. "L3D_CACHE_ALLOCATE,Attributable Level 3 data or unified cache allocation without refill" "Reserved,Implemented"
tree.end
newline
group.long c15:0x066F++0x00
line.long 0x00 "CLUSTERPMCLAIMSET,Cluster Performance Monitor Claim Tag Set Register"
bitfld.long 0x00 3. "S[3],Set bit 3" "Low,High"
bitfld.long 0x00 2. "S[2],Set bit 2" "Low,High"
bitfld.long 0x00 1. "S[1],Set bit 1" "Low,High"
newline
bitfld.long 0x00 0. "S[0],Set bit 0" "Low,High"
group.long c15:0x076F++0x00
line.long 0x00 "CLUSTERPMCLAIMCLR,Cluster Performance Monitor Claim Tag Clear Register"
bitfld.long 0x00 3. "C[3],Clear bit 3" "Low,High"
bitfld.long 0x00 2. "C[2],Clear bit 2" "Low,High"
bitfld.long 0x00 1. "C[1],Clear bit 1" "Low,High"
newline
bitfld.long 0x00 0. "C[0],Clear bit 0" "Low,High"
tree.end
tree.end
tree.end
AUTOINDENT.OFF
AUTOINDENT.POP
tree "Interrupt Controller"
width 17.
base ad:(per.long(spr:0x31F30)&0xFFFC0000)
tree "Distributor Interface"
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x400)==0x400)
if PER.ADDRESS.isSECUREEX(ad:(per.long(spr:0x31F30)&0xFFFC0000))
group.long 0x0000++0x03
line.long 0x00 "GICD_CTLR,Distributor Control Register (Secure access)"
bitfld.long 0x00 1. " ENABLEGRP1    ,Global Interrupt Enable Group 1" "Disabled,Enabled"
bitfld.long 0x00 0. "         ENABLEGRP0    ,Global Interrupt Enable Group 1" "Disabled,Enabled"
else
group.long 0x0000++0x03
line.long 0x00 "GICD_CTLR,Distributor Control Register (Non-secure access)"
bitfld.long 0x00 0. " ENABLE        ,Global enable for forwarding pending interrupts from the Distributor to the CPU interfaces" "Disabled,Enabled"
endif
else
group.long 0x0000++0x03
line.long 0x00 "GICD_CTLR,Distributor Control Register"
bitfld.long 0x00 0. " ENABLE        ,Global enable for forwarding pending interrupts from the Distributor to the CPU interfaces" "Disabled,Enabled"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x400)==0x400)
rgroup.long 0x0004++0x03
line.long 0x00 "GICD_TYPER,Interrupt Controller Type Register"
bitfld.long 0x00 11.--15. " LSPI          ,Locable Shared Peripheral Interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 10. "               SECURITYEXTN  ,Indicate whether interrupt controller implements the security extensions" "Not implemented,Implemented"
textline "                          "
bitfld.long 0x00 5.--7. " CPUNUMBER     ,Indicates the number of implemented CPU interfaces" "1,2,3,4,?..."
bitfld.long 0x00 0.--4. "                ITLN          ,Indicates the number of interrupts that the interrupt controller supports" "Up to 32,Up to 64,Up to 96,Up to 128,Up to 160,Up to 192,Up to 224,Up to 256,Up to 288,Up to 320,Up to 352,Up to 384,Up to 416,Up to 448,Up to 480,Up to 512,Up to 544,Up to 576,Up to 608,Up to 640,Up to 672,Up to 704,Up to 736,Up to 768,Up to 800,Up to 832,Up to 864,Up to 896,Up to 928,Up to 960,Up to 992,Up to 1020"
else
rgroup.long 0x0004++0x03
line.long 0x00 "GICD_TYPER,Interrupt Controller Type Register"
bitfld.long 0x00 10. " SECURITYEXTN  ,Indicates whether interrupt controller implements the security extensions" "Not implemented,Implemented"
textline "                          "
bitfld.long 0x00 5.--7. " CPUNUMBER     ,Indicates the number of implemented CPU interfaces" "1,2,3,4,?..."
bitfld.long 0x00 0.--4. "                ITLN          ,Indicates the number of interrupts that the interrupt controller supports" "Up to 32,Up to 64,Up to 96,Up to 128,Up to 160,Up to 192,Up to 224,Up to 256,Up to 288,Up to 320,Up to 352,Up to 384,Up to 416,Up to 448,Up to 480,Up to 512,Up to 544,Up to 576,Up to 608,Up to 640,Up to 672,Up to 704,Up to 736,Up to 768,Up to 800,Up to 832,Up to 864,Up to 896,Up to 928,Up to 960,Up to 992,Up to 1020"
endif
rgroup.long 0x0008++0x03
line.long 0x00 "GICD_IIDR,Distributor Implementer Identification Register"
bitfld.long 0x00 24.--31. " PRODID        ,Indicates the product ID" "PL390,PL390,GIC400,GIC400,?..."
bitfld.long 0x00 16.--19. "           VAR           ,Major revison number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                          "
bitfld.long 0x00 12.--15. " REV           ,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "               IMP           ,Implementer"
sif CPU.FEATURE(hypervisor)||CPU.FEATURE(secure)
width 17.
tree "Group/Security Registers"
if PER.ADDRESS.isSECUREEX(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x0080)
group.long 0x0080++0x03
line.long 0x0 "GICD_IGROUPR0,Interrupt Group Register 0 (Secure Access)"
bitfld.long 0x00 31. " GSB31   ,Group Status Bit 31" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 30. "  GSB30   ,Group Status Bit 30" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 29. "  GSB29   ,Group Status Bit 29" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 28. " GSB28   ,Group Status Bit 28" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 27. "  GSB27   ,Group Status Bit 27" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 26. "  GSB26   ,Group Status Bit 26" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 25. " GSB25   ,Group Status Bit 25" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 24. "  GSB24   ,Group Status Bit 24" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 23. "  GSB23   ,Group Status Bit 23" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 22. " GSB22   ,Group Status Bit 22" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 21. "  GSB21   ,Group Status Bit 21" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 20. "  GSB20   ,Group Status Bit 20" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 19. " GSB19   ,Group Status Bit 19" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 18. "  GSB18   ,Group Status Bit 18" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 17. "  GSB17   ,Group Status Bit 17" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 16. " GSB16   ,Group Status Bit 16" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 15. "  GSB15   ,Group Status Bit 15" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 14. "  GSB14   ,Group Status Bit 14" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 13. " GSB13   ,Group Status Bit 13" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 12. "  GSB12   ,Group Status Bit 12" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 11. "  GSB11   ,Group Status Bit 11" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 10. " GSB10   ,Group Status Bit 10" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 9. "  GSB9    ,Group Status Bit 9" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 8. "  GSB8    ,Group Status Bit 8" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 7. " GSB7    ,Group Status Bit 7" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 6. "  GSB6    ,Group Status Bit 6" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 5. "  GSB5    ,Group Status Bit 5" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 4. " GSB4    ,Group Status Bit 4" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 3. "  GSB3    ,Group Status Bit 3" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 2. "  GSB2    ,Group Status Bit 2" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 1. " GSB1    ,Group Status Bit 1" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 0. "  GSB0    ,Group Status Bit 0" "Group 0 (Secure),Group 1 (Non-secure)"
else
group.long 0x0080++0x03
line.long 0x0 "GICD_IGROUPR0,Interrupt Group Register 0 (Non-secure access)"
bitfld.long 0x00 31. " GSB31   ,Group Status Bit 31" "Group 0,Group 1"
bitfld.long 0x00 30. "  GSB30   ,Group Status Bit 30" "Group 0,Group 1"
bitfld.long 0x00 29. "  GSB29   ,Group Status Bit 29" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB28   ,Group Status Bit 28" "Group 0,Group 1"
bitfld.long 0x00 27. "  GSB27   ,Group Status Bit 27" "Group 0,Group 1"
bitfld.long 0x00 26. "  GSB26   ,Group Status Bit 26" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB25   ,Group Status Bit 25" "Group 0,Group 1"
bitfld.long 0x00 24. "  GSB24   ,Group Status Bit 24" "Group 0,Group 1"
bitfld.long 0x00 23. "  GSB23   ,Group Status Bit 23" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB22   ,Group Status Bit 22" "Group 0,Group 1"
bitfld.long 0x00 21. "  GSB21   ,Group Status Bit 21" "Group 0,Group 1"
bitfld.long 0x00 20. "  GSB20   ,Group Status Bit 20" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB19   ,Group Status Bit 19" "Group 0,Group 1"
bitfld.long 0x00 18. "  GSB18   ,Group Status Bit 18" "Group 0,Group 1"
bitfld.long 0x00 17. "  GSB17   ,Group Status Bit 17" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB16   ,Group Status Bit 16" "Group 0,Group 1"
bitfld.long 0x00 15. "  GSB15   ,Group Status Bit 15" "Group 0,Group 1"
bitfld.long 0x00 14. "  GSB14   ,Group Status Bit 14" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB13   ,Group Status Bit 13" "Group 0,Group 1"
bitfld.long 0x00 12. "  GSB12   ,Group Status Bit 12" "Group 0,Group 1"
bitfld.long 0x00 11. "  GSB11   ,Group Status Bit 11" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB10   ,Group Status Bit 10" "Group 0,Group 1"
bitfld.long 0x00 9. "  GSB9    ,Group Status Bit 9" "Group 0,Group 1"
bitfld.long 0x00 8. "  GSB8    ,Group Status Bit 8" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB7    ,Group Status Bit 7" "Group 0,Group 1"
bitfld.long 0x00 6. "  GSB6    ,Group Status Bit 6" "Group 0,Group 1"
bitfld.long 0x00 5. "  GSB5    ,Group Status Bit 5" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB4    ,Group Status Bit 4" "Group 0,Group 1"
bitfld.long 0x00 3. "  GSB3    ,Group Status Bit 3" "Group 0,Group 1"
bitfld.long 0x00 2. "  GSB2    ,Group Status Bit 2" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB1    ,Group Status Bit 1" "Group 0,Group 1"
bitfld.long 0x00 0. "  GSB0    ,Group Status Bit 0" "Group 0,Group 1"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x01)&&(PER.ADDRESS.isSECUREEX(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x0084))
group.long 0x0084++0x03
line.long 0x0 "GICD_IGROUPR1,Interrupt Group Register 1 (Secure Access)"
bitfld.long 0x00 31. " GSB63   ,Group Status Bit 63" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 30. "  GSB62   ,Group Status Bit 62" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 29. "  GSB61   ,Group Status Bit 61" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 28. " GSB60   ,Group Status Bit 60" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 27. "  GSB59   ,Group Status Bit 59" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 26. "  GSB58   ,Group Status Bit 58" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 25. " GSB57   ,Group Status Bit 57" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 24. "  GSB56   ,Group Status Bit 56" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 23. "  GSB55   ,Group Status Bit 55" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 22. " GSB54   ,Group Status Bit 54" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 21. "  GSB53   ,Group Status Bit 53" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 20. "  GSB52   ,Group Status Bit 52" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 19. " GSB51   ,Group Status Bit 51" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 18. "  GSB50   ,Group Status Bit 50" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 17. "  GSB49   ,Group Status Bit 49" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 16. " GSB48   ,Group Status Bit 48" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 15. "  GSB47   ,Group Status Bit 47" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 14. "  GSB46   ,Group Status Bit 46" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 13. " GSB45   ,Group Status Bit 45" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 12. "  GSB44   ,Group Status Bit 44" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 11. "  GSB43   ,Group Status Bit 43" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 10. " GSB42   ,Group Status Bit 42" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 9. "  GSB41   ,Group Status Bit 41" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 8. "  GSB40   ,Group Status Bit 40" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 7. " GSB39   ,Group Status Bit 39" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 6. "  GSB38   ,Group Status Bit 38" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 5. "  GSB37   ,Group Status Bit 37" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 4. " GSB36   ,Group Status Bit 36" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 3. "  GSB35   ,Group Status Bit 35" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 2. "  GSB34   ,Group Status Bit 34" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 1. " GSB33   ,Group Status Bit 33" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 0. "  GSB32   ,Group Status Bit 32" "Group 0 (Secure),Group 1 (Non-secure)"
elif (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x01)
group.long 0x0084++0x03
line.long 0x0 "GICD_IGROUPR1,Interrupt Group Register 1 (Non-secure access)"
bitfld.long 0x00 31. " GSB63   ,Group Status Bit 63" "Group 0,Group 1"
bitfld.long 0x00 30. "  GSB62   ,Group Status Bit 62" "Group 0,Group 1"
bitfld.long 0x00 29. "  GSB61   ,Group Status Bit 61" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB60   ,Group Status Bit 60" "Group 0,Group 1"
bitfld.long 0x00 27. "  GSB59   ,Group Status Bit 59" "Group 0,Group 1"
bitfld.long 0x00 26. "  GSB58   ,Group Status Bit 58" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB57   ,Group Status Bit 57" "Group 0,Group 1"
bitfld.long 0x00 24. "  GSB56   ,Group Status Bit 56" "Group 0,Group 1"
bitfld.long 0x00 23. "  GSB55   ,Group Status Bit 55" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB54   ,Group Status Bit 54" "Group 0,Group 1"
bitfld.long 0x00 21. "  GSB53   ,Group Status Bit 53" "Group 0,Group 1"
bitfld.long 0x00 20. "  GSB52   ,Group Status Bit 52" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB51   ,Group Status Bit 51" "Group 0,Group 1"
bitfld.long 0x00 18. "  GSB50   ,Group Status Bit 50" "Group 0,Group 1"
bitfld.long 0x00 17. "  GSB49   ,Group Status Bit 49" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB48   ,Group Status Bit 48" "Group 0,Group 1"
bitfld.long 0x00 15. "  GSB47   ,Group Status Bit 47" "Group 0,Group 1"
bitfld.long 0x00 14. "  GSB46   ,Group Status Bit 46" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB45   ,Group Status Bit 45" "Group 0,Group 1"
bitfld.long 0x00 12. "  GSB44   ,Group Status Bit 44" "Group 0,Group 1"
bitfld.long 0x00 11. "  GSB43   ,Group Status Bit 43" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB42   ,Group Status Bit 42" "Group 0,Group 1"
bitfld.long 0x00 9. "  GSB41   ,Group Status Bit 41" "Group 0,Group 1"
bitfld.long 0x00 8. "  GSB40   ,Group Status Bit 40" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB39   ,Group Status Bit 39" "Group 0,Group 1"
bitfld.long 0x00 6. "  GSB38   ,Group Status Bit 38" "Group 0,Group 1"
bitfld.long 0x00 5. "  GSB37   ,Group Status Bit 37" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB36   ,Group Status Bit 36" "Group 0,Group 1"
bitfld.long 0x00 3. "  GSB35   ,Group Status Bit 35" "Group 0,Group 1"
bitfld.long 0x00 2. "  GSB34   ,Group Status Bit 34" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB33   ,Group Status Bit 33" "Group 0,Group 1"
bitfld.long 0x00 0. "  GSB32   ,Group Status Bit 32" "Group 0,Group 1"
else
rgroup.long 0x0084++0x03
line.long 0x0 "GICD_IGROUPR1,Interrupt Group Register 1"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x02)&&(PER.ADDRESS.isSECUREEX(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x0088))
group.long 0x0088++0x03
line.long 0x0 "GICD_IGROUPR2,Interrupt Group Register 2 (Secure access)"
bitfld.long 0x00 31. " GSB95   ,Group Status Bit 95" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 30. "  GSB94   ,Group Status Bit 94" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 29. "  GSB93   ,Group Status Bit 93" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 28. " GSB92   ,Group Status Bit 92" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 27. "  GSB91   ,Group Status Bit 91" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 26. "  GSB90   ,Group Status Bit 90" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 25. " GSB89   ,Group Status Bit 89" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 24. "  GSB88   ,Group Status Bit 88" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 23. "  GSB87   ,Group Status Bit 87" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 22. " GSB86   ,Group Status Bit 86" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 21. "  GSB85   ,Group Status Bit 85" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 20. "  GSB84   ,Group Status Bit 84" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 19. " GSB83   ,Group Status Bit 83" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 18. "  GSB82   ,Group Status Bit 82" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 17. "  GSB81   ,Group Status Bit 81" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 16. " GSB80   ,Group Status Bit 80" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 15. "  GSB79   ,Group Status Bit 79" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 14. "  GSB78   ,Group Status Bit 78" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 13. " GSB77   ,Group Status Bit 77" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 12. "  GSB76   ,Group Status Bit 76" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 11. "  GSB75   ,Group Status Bit 75" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 10. " GSB74   ,Group Status Bit 74" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 9. "  GSB73   ,Group Status Bit 73" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 8. "  GSB72   ,Group Status Bit 72" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 7. " GSB71   ,Group Status Bit 71" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 6. "  GSB70   ,Group Status Bit 70" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 5. "  GSB69   ,Group Status Bit 69" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 4. " GSB68   ,Group Status Bit 68" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 3. "  GSB67   ,Group Status Bit 67" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 2. "  GSB66   ,Group Status Bit 66" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 1. " GSB65   ,Group Status Bit 65" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 0. "  GSB64   ,Group Status Bit 64" "Group 0 (Secure),Group 1 (Non-secure)"
elif (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x02)
group.long 0x0088++0x03
line.long 0x0 "GICD_IGROUPR2,Interrupt Group Register 2 (Non-secure access)"
bitfld.long 0x00 31. " GSB95   ,Group Status Bit 95" "Group 0,Group 1"
bitfld.long 0x00 30. "  GSB94   ,Group Status Bit 94" "Group 0,Group 1"
bitfld.long 0x00 29. "  GSB93   ,Group Status Bit 93" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB92   ,Group Status Bit 92" "Group 0,Group 1"
bitfld.long 0x00 27. "  GSB91   ,Group Status Bit 91" "Group 0,Group 1"
bitfld.long 0x00 26. "  GSB90   ,Group Status Bit 90" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB89   ,Group Status Bit 89" "Group 0,Group 1"
bitfld.long 0x00 24. "  GSB88   ,Group Status Bit 88" "Group 0,Group 1"
bitfld.long 0x00 23. "  GSB87   ,Group Status Bit 87" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB86   ,Group Status Bit 86" "Group 0,Group 1"
bitfld.long 0x00 21. "  GSB85   ,Group Status Bit 85" "Group 0,Group 1"
bitfld.long 0x00 20. "  GSB84   ,Group Status Bit 84" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB83   ,Group Status Bit 83" "Group 0,Group 1"
bitfld.long 0x00 18. "  GSB82   ,Group Status Bit 82" "Group 0,Group 1"
bitfld.long 0x00 17. "  GSB81   ,Group Status Bit 81" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB80   ,Group Status Bit 80" "Group 0,Group 1"
bitfld.long 0x00 15. "  GSB79   ,Group Status Bit 79" "Group 0,Group 1"
bitfld.long 0x00 14. "  GSB78   ,Group Status Bit 78" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB77   ,Group Status Bit 77" "Group 0,Group 1"
bitfld.long 0x00 12. "  GSB76   ,Group Status Bit 76" "Group 0,Group 1"
bitfld.long 0x00 11. "  GSB75   ,Group Status Bit 75" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB74   ,Group Status Bit 74" "Group 0,Group 1"
bitfld.long 0x00 9. "  GSB73   ,Group Status Bit 73" "Group 0,Group 1"
bitfld.long 0x00 8. "  GSB72   ,Group Status Bit 72" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB71   ,Group Status Bit 71" "Group 0,Group 1"
bitfld.long 0x00 6. "  GSB70   ,Group Status Bit 70" "Group 0,Group 1"
bitfld.long 0x00 5. "  GSB69   ,Group Status Bit 69" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB68   ,Group Status Bit 68" "Group 0,Group 1"
bitfld.long 0x00 3. "  GSB67   ,Group Status Bit 67" "Group 0,Group 1"
bitfld.long 0x00 2. "  GSB66   ,Group Status Bit 66" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB65   ,Group Status Bit 65" "Group 0,Group 1"
bitfld.long 0x00 0. "  GSB64   ,Group Status Bit 64" "Group 0,Group 1"
else
rgroup.long 0x0088++0x03
line.long 0x0 "GICD_IGROUPR2,Interrupt Group Register 2"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x03)&&(PER.ADDRESS.isSECUREEX(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x008C))
group.long 0x008C++0x03
line.long 0x0 "GICD_IGROUPR3,Interrupt Group Register 3 (Secure access)"
bitfld.long 0x00 31. " GSB127  ,Group Status Bit 127" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 30. "  GSB126  ,Group Status Bit 126" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 29. "  GSB125  ,Group Status Bit 125" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 28. " GSB124  ,Group Status Bit 124" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 27. "  GSB123  ,Group Status Bit 123" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 26. "  GSB122  ,Group Status Bit 122" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 25. " GSB121  ,Group Status Bit 121" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 24. "  GSB120  ,Group Status Bit 120" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 23. "  GSB119  ,Group Status Bit 119" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 22. " GSB118  ,Group Status Bit 118" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 21. "  GSB117  ,Group Status Bit 117" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 20. "  GSB116  ,Group Status Bit 116" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 19. " GSB115  ,Group Status Bit 115" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 18. "  GSB114  ,Group Status Bit 114" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 17. "  GSB113  ,Group Status Bit 113" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 16. " GSB112  ,Group Status Bit 112" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 15. "  GSB111  ,Group Status Bit 111" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 14. "  GSB110  ,Group Status Bit 110" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 13. " GSB109  ,Group Status Bit 109" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 12. "  GSB108  ,Group Status Bit 108" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 11. "  GSB107  ,Group Status Bit 107" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 10. " GSB106  ,Group Status Bit 106" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 9. "  GSB105  ,Group Status Bit 105" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 8. "  GSB104  ,Group Status Bit 104" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 7. " GSB103  ,Group Status Bit 103" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 6. "  GSB102  ,Group Status Bit 102" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 5. "  GSB101  ,Group Status Bit 101" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 4. " GSB100  ,Group Status Bit 100" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 3. "  GSB99   ,Group Status Bit 99" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 2. "  GSB98   ,Group Status Bit 98" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 1. " GSB97   ,Group Status Bit 97" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 0. "  GSB96   ,Group Status Bit 96" "Group 0 (Secure),Group 1 (Non-secure)"
elif (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x03)
group.long 0x008C++0x03
line.long 0x0 "GICD_IGROUPR3,Interrupt Group Register 3 (Non-secure access)"
bitfld.long 0x00 31. " GSB127  ,Group Status Bit 127" "Group 0,Group 1"
bitfld.long 0x00 30. "  GSB126  ,Group Status Bit 126" "Group 0,Group 1"
bitfld.long 0x00 29. "  GSB125  ,Group Status Bit 125" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB124  ,Group Status Bit 124" "Group 0,Group 1"
bitfld.long 0x00 27. "  GSB123  ,Group Status Bit 123" "Group 0,Group 1"
bitfld.long 0x00 26. "  GSB122  ,Group Status Bit 122" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB121  ,Group Status Bit 121" "Group 0,Group 1"
bitfld.long 0x00 24. "  GSB120  ,Group Status Bit 120" "Group 0,Group 1"
bitfld.long 0x00 23. "  GSB119  ,Group Status Bit 119" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB118  ,Group Status Bit 118" "Group 0,Group 1"
bitfld.long 0x00 21. "  GSB117  ,Group Status Bit 117" "Group 0,Group 1"
bitfld.long 0x00 20. "  GSB116  ,Group Status Bit 116" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB115  ,Group Status Bit 115" "Group 0,Group 1"
bitfld.long 0x00 18. "  GSB114  ,Group Status Bit 114" "Group 0,Group 1"
bitfld.long 0x00 17. "  GSB113  ,Group Status Bit 113" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB112  ,Group Status Bit 112" "Group 0,Group 1"
bitfld.long 0x00 15. "  GSB111  ,Group Status Bit 111" "Group 0,Group 1"
bitfld.long 0x00 14. "  GSB110  ,Group Status Bit 110" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB109  ,Group Status Bit 109" "Group 0,Group 1"
bitfld.long 0x00 12. "  GSB108  ,Group Status Bit 108" "Group 0,Group 1"
bitfld.long 0x00 11. "  GSB107  ,Group Status Bit 107" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB106  ,Group Status Bit 106" "Group 0,Group 1"
bitfld.long 0x00 9. "  GSB105  ,Group Status Bit 105" "Group 0,Group 1"
bitfld.long 0x00 8. "  GSB104  ,Group Status Bit 104" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB103  ,Group Status Bit 103" "Group 0,Group 1"
bitfld.long 0x00 6. "  GSB102  ,Group Status Bit 102" "Group 0,Group 1"
bitfld.long 0x00 5. "  GSB101  ,Group Status Bit 101" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB100  ,Group Status Bit 100" "Group 0,Group 1"
bitfld.long 0x00 3. "  GSB99   ,Group Status Bit 99" "Group 0,Group 1"
bitfld.long 0x00 2. "  GSB98   ,Group Status Bit 98" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB97   ,Group Status Bit 97" "Group 0,Group 1"
bitfld.long 0x00 0. "  GSB96   ,Group Status Bit 96" "Group 0,Group 1"
else
rgroup.long 0x008C++0x03
line.long 0x0 "GICD_IGROUPR3,Interrupt Group Register 3"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x04)&&(PER.ADDRESS.isSECUREEX(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x0090))
group.long 0x0090++0x03
line.long 0x0 "GICD_IGROUPR4,Interrupt Group Register 4 (Secure access)"
bitfld.long 0x00 31. " GSB159  ,Group Status Bit 159" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 30. "  GSB158  ,Group Status Bit 158" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 29. "  GSB157  ,Group Status Bit 157" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 28. " GSB156  ,Group Status Bit 156" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 27. "  GSB155  ,Group Status Bit 155" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 26. "  GSB154  ,Group Status Bit 154" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 25. " GSB153  ,Group Status Bit 153" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 24. "  GSB152  ,Group Status Bit 152" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 23. "  GSB151  ,Group Status Bit 151" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 22. " GSB150  ,Group Status Bit 150" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 21. "  GSB149  ,Group Status Bit 149" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 20. "  GSB148  ,Group Status Bit 148" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 19. " GSB147  ,Group Status Bit 147" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 18. "  GSB146  ,Group Status Bit 146" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 17. "  GSB145  ,Group Status Bit 145" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 16. " GSB144  ,Group Status Bit 144" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 15. "  GSB143  ,Group Status Bit 143" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 14. "  GSB142  ,Group Status Bit 142" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 13. " GSB141  ,Group Status Bit 141" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 12. "  GSB140  ,Group Status Bit 140" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 11. "  GSB139  ,Group Status Bit 139" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 10. " GSB138  ,Group Status Bit 138" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 9. "  GSB137  ,Group Status Bit 137" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 8. "  GSB136  ,Group Status Bit 136" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 7. " GSB135  ,Group Status Bit 135" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 6. "  GSB134  ,Group Status Bit 134" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 5. "  GSB133  ,Group Status Bit 133" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 4. " GSB132  ,Group Status Bit 132" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 3. "  GSB131  ,Group Status Bit 131" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 2. "  GSB130  ,Group Status Bit 130" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 1. " GSB129  ,Group Status Bit 129" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 0. "  GSB128  ,Group Status Bit 128" "Group 0 (Secure),Group 1 (Non-secure)"
elif (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x04)
group.long 0x0090++0x03
line.long 0x0 "GICD_IGROUPR4,Interrupt Group Register 4 (Non-secure access)"
bitfld.long 0x00 31. " GSB159  ,Group Status Bit 159" "Group 0,Group 1"
bitfld.long 0x00 30. "  GSB158  ,Group Status Bit 158" "Group 0,Group 1"
bitfld.long 0x00 29. "  GSB157  ,Group Status Bit 157" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB156  ,Group Status Bit 156" "Group 0,Group 1"
bitfld.long 0x00 27. "  GSB155  ,Group Status Bit 155" "Group 0,Group 1"
bitfld.long 0x00 26. "  GSB154  ,Group Status Bit 154" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB153  ,Group Status Bit 153" "Group 0,Group 1"
bitfld.long 0x00 24. "  GSB152  ,Group Status Bit 152" "Group 0,Group 1"
bitfld.long 0x00 23. "  GSB151  ,Group Status Bit 151" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB150  ,Group Status Bit 150" "Group 0,Group 1"
bitfld.long 0x00 21. "  GSB149  ,Group Status Bit 149" "Group 0,Group 1"
bitfld.long 0x00 20. "  GSB148  ,Group Status Bit 148" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB147  ,Group Status Bit 147" "Group 0,Group 1"
bitfld.long 0x00 18. "  GSB146  ,Group Status Bit 146" "Group 0,Group 1"
bitfld.long 0x00 17. "  GSB145  ,Group Status Bit 145" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB144  ,Group Status Bit 144" "Group 0,Group 1"
bitfld.long 0x00 15. "  GSB143  ,Group Status Bit 143" "Group 0,Group 1"
bitfld.long 0x00 14. "  GSB142  ,Group Status Bit 142" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB141  ,Group Status Bit 141" "Group 0,Group 1"
bitfld.long 0x00 12. "  GSB140  ,Group Status Bit 140" "Group 0,Group 1"
bitfld.long 0x00 11. "  GSB139  ,Group Status Bit 139" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB138  ,Group Status Bit 138" "Group 0,Group 1"
bitfld.long 0x00 9. "  GSB137  ,Group Status Bit 137" "Group 0,Group 1"
bitfld.long 0x00 8. "  GSB136  ,Group Status Bit 136" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB135  ,Group Status Bit 135" "Group 0,Group 1"
bitfld.long 0x00 6. "  GSB134  ,Group Status Bit 134" "Group 0,Group 1"
bitfld.long 0x00 5. "  GSB133  ,Group Status Bit 133" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB132  ,Group Status Bit 132" "Group 0,Group 1"
bitfld.long 0x00 3. "  GSB131  ,Group Status Bit 131" "Group 0,Group 1"
bitfld.long 0x00 2. "  GSB130  ,Group Status Bit 130" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB129  ,Group Status Bit 129" "Group 0,Group 1"
bitfld.long 0x00 0. "  GSB128  ,Group Status Bit 128" "Group 0,Group 1"
else
rgroup.long 0x0090++0x03
line.long 0x0 "GICD_IGROUPR4,Interrupt Group Register 4"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x05)&&(PER.ADDRESS.isSECUREEX(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x0094))
group.long 0x0094++0x03
line.long 0x0 "GICD_IGROUPR5,Interrupt Group Register 5 (Secure access)"
bitfld.long 0x00 31. " GSB191  ,Group Status Bit 191" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 30. "  GSB190  ,Group Status Bit 190" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 29. "  GSB189  ,Group Status Bit 189" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 28. " GSB188  ,Group Status Bit 188" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 27. "  GSB187  ,Group Status Bit 187" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 26. "  GSB186  ,Group Status Bit 186" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 25. " GSB185  ,Group Status Bit 185" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 24. "  GSB184  ,Group Status Bit 184" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 23. "  GSB183  ,Group Status Bit 183" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 22. " GSB182  ,Group Status Bit 182" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 21. "  GSB181  ,Group Status Bit 181" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 20. "  GSB180  ,Group Status Bit 180" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 19. " GSB179  ,Group Status Bit 179" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 18. "  GSB178  ,Group Status Bit 178" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 17. "  GSB177  ,Group Status Bit 177" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 16. " GSB176  ,Group Status Bit 176" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 15. "  GSB175  ,Group Status Bit 175" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 14. "  GSB174  ,Group Status Bit 174" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 13. " GSB173  ,Group Status Bit 173" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 12. "  GSB172  ,Group Status Bit 172" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 11. "  GSB171  ,Group Status Bit 171" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 10. " GSB170  ,Group Status Bit 170" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 9. "  GSB169  ,Group Status Bit 169" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 8. "  GSB168  ,Group Status Bit 168" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 7. " GSB167  ,Group Status Bit 167" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 6. "  GSB166  ,Group Status Bit 166" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 5. "  GSB165  ,Group Status Bit 165" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 4. " GSB164  ,Group Status Bit 164" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 3. "  GSB163  ,Group Status Bit 163" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 2. "  GSB162  ,Group Status Bit 162" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 1. " GSB161  ,Group Status Bit 161" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 0. "  GSB160  ,Group Status Bit 160" "Group 0 (Secure),Group 1 (Non-secure)"
elif (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x05)
group.long 0x0094++0x03
line.long 0x0 "GICD_IGROUPR5,Interrupt Group Register 5 (Non-secure access)"
bitfld.long 0x00 31. " GSB191  ,Group Status Bit 191" "Group 0,Group 1"
bitfld.long 0x00 30. "  GSB190  ,Group Status Bit 190" "Group 0,Group 1"
bitfld.long 0x00 29. "  GSB189  ,Group Status Bit 189" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB188  ,Group Status Bit 188" "Group 0,Group 1"
bitfld.long 0x00 27. "  GSB187  ,Group Status Bit 187" "Group 0,Group 1"
bitfld.long 0x00 26. "  GSB186  ,Group Status Bit 186" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB185  ,Group Status Bit 185" "Group 0,Group 1"
bitfld.long 0x00 24. "  GSB184  ,Group Status Bit 184" "Group 0,Group 1"
bitfld.long 0x00 23. "  GSB183  ,Group Status Bit 183" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB182  ,Group Status Bit 182" "Group 0,Group 1"
bitfld.long 0x00 21. "  GSB181  ,Group Status Bit 181" "Group 0,Group 1"
bitfld.long 0x00 20. "  GSB180  ,Group Status Bit 180" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB179  ,Group Status Bit 179" "Group 0,Group 1"
bitfld.long 0x00 18. "  GSB178  ,Group Status Bit 178" "Group 0,Group 1"
bitfld.long 0x00 17. "  GSB177  ,Group Status Bit 177" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB176  ,Group Status Bit 176" "Group 0,Group 1"
bitfld.long 0x00 15. "  GSB175  ,Group Status Bit 175" "Group 0,Group 1"
bitfld.long 0x00 14. "  GSB174  ,Group Status Bit 174" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB173  ,Group Status Bit 173" "Group 0,Group 1"
bitfld.long 0x00 12. "  GSB172  ,Group Status Bit 172" "Group 0,Group 1"
bitfld.long 0x00 11. "  GSB171  ,Group Status Bit 171" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB170  ,Group Status Bit 170" "Group 0,Group 1"
bitfld.long 0x00 9. "  GSB169  ,Group Status Bit 169" "Group 0,Group 1"
bitfld.long 0x00 8. "  GSB168  ,Group Status Bit 168" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB167  ,Group Status Bit 167" "Group 0,Group 1"
bitfld.long 0x00 6. "  GSB166  ,Group Status Bit 166" "Group 0,Group 1"
bitfld.long 0x00 5. "  GSB165  ,Group Status Bit 165" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB164  ,Group Status Bit 164" "Group 0,Group 1"
bitfld.long 0x00 3. "  GSB163  ,Group Status Bit 163" "Group 0,Group 1"
bitfld.long 0x00 2. "  GSB162  ,Group Status Bit 162" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB161  ,Group Status Bit 161" "Group 0,Group 1"
bitfld.long 0x00 0. "  GSB160  ,Group Status Bit 160" "Group 0,Group 1"
else
rgroup.long 0x0094++0x03
line.long 0x0 "GICD_IGROUPR5,Interrupt Group Register 5"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x06)&&(PER.ADDRESS.isSECUREEX(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x0098))
group.long 0x0098++0x03
line.long 0x0 "GICD_IGROUPR6,Interrupt Group Register 6 (Secure access)"
bitfld.long 0x00 31. " GSB223  ,Group Status Bit 223" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 30. "  GSB222  ,Group Status Bit 222" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 29. "  GSB221  ,Group Status Bit 221" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 28. " GSB220  ,Group Status Bit 220" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 27. "  GSB219  ,Group Status Bit 219" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 26. "  GSB218  ,Group Status Bit 218" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 25. " GSB217  ,Group Status Bit 217" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 24. "  GSB216  ,Group Status Bit 216" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 23. "  GSB215  ,Group Status Bit 215" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 22. " GSB214  ,Group Status Bit 214" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 21. "  GSB213  ,Group Status Bit 213" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 20. "  GSB212  ,Group Status Bit 212" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 19. " GSB211  ,Group Status Bit 211" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 18. "  GSB210  ,Group Status Bit 210" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 17. "  GSB209  ,Group Status Bit 209" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 16. " GSB208  ,Group Status Bit 208" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 15. "  GSB207  ,Group Status Bit 207" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 14. "  GSB206  ,Group Status Bit 206" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 13. " GSB205  ,Group Status Bit 205" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 12. "  GSB204  ,Group Status Bit 204" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 11. "  GSB203  ,Group Status Bit 203" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 10. " GSB202  ,Group Status Bit 202" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 9. "  GSB201  ,Group Status Bit 201" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 8. "  GSB200  ,Group Status Bit 200" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 7. " GSB199  ,Group Status Bit 199" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 6. "  GSB198  ,Group Status Bit 198" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 5. "  GSB197  ,Group Status Bit 197" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 4. " GSB196  ,Group Status Bit 196" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 3. "  GSB195  ,Group Status Bit 195" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 2. "  GSB194  ,Group Status Bit 194" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 1. " GSB193  ,Group Status Bit 193" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 0. "  GSB192  ,Group Status Bit 192" "Group 0 (Secure),Group 1 (Non-secure)"
elif (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x06)
group.long 0x0098++0x03
line.long 0x0 "GICD_IGROUPR6,Interrupt Group Register 6 (Non-secure access)"
bitfld.long 0x00 31. " GSB223  ,Group Status Bit 223" "Group 0,Group 1"
bitfld.long 0x00 30. "  GSB222  ,Group Status Bit 222" "Group 0,Group 1"
bitfld.long 0x00 29. "  GSB221  ,Group Status Bit 221" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB220  ,Group Status Bit 220" "Group 0,Group 1"
bitfld.long 0x00 27. "  GSB219  ,Group Status Bit 219" "Group 0,Group 1"
bitfld.long 0x00 26. "  GSB218  ,Group Status Bit 218" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB217  ,Group Status Bit 217" "Group 0,Group 1"
bitfld.long 0x00 24. "  GSB216  ,Group Status Bit 216" "Group 0,Group 1"
bitfld.long 0x00 23. "  GSB215  ,Group Status Bit 215" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB214  ,Group Status Bit 214" "Group 0,Group 1"
bitfld.long 0x00 21. "  GSB213  ,Group Status Bit 213" "Group 0,Group 1"
bitfld.long 0x00 20. "  GSB212  ,Group Status Bit 212" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB211  ,Group Status Bit 211" "Group 0,Group 1"
bitfld.long 0x00 18. "  GSB210  ,Group Status Bit 210" "Group 0,Group 1"
bitfld.long 0x00 17. "  GSB209  ,Group Status Bit 209" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB208  ,Group Status Bit 208" "Group 0,Group 1"
bitfld.long 0x00 15. "  GSB207  ,Group Status Bit 207" "Group 0,Group 1"
bitfld.long 0x00 14. "  GSB206  ,Group Status Bit 206" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB205  ,Group Status Bit 205" "Group 0,Group 1"
bitfld.long 0x00 12. "  GSB204  ,Group Status Bit 204" "Group 0,Group 1"
bitfld.long 0x00 11. "  GSB203  ,Group Status Bit 203" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB202  ,Group Status Bit 202" "Group 0,Group 1"
bitfld.long 0x00 9. "  GSB201  ,Group Status Bit 201" "Group 0,Group 1"
bitfld.long 0x00 8. "  GSB200  ,Group Status Bit 200" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB199  ,Group Status Bit 199" "Group 0,Group 1"
bitfld.long 0x00 6. "  GSB198  ,Group Status Bit 198" "Group 0,Group 1"
bitfld.long 0x00 5. "  GSB197  ,Group Status Bit 197" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB196  ,Group Status Bit 196" "Group 0,Group 1"
bitfld.long 0x00 3. "  GSB195  ,Group Status Bit 195" "Group 0,Group 1"
bitfld.long 0x00 2. "  GSB194  ,Group Status Bit 194" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB193  ,Group Status Bit 193" "Group 0,Group 1"
bitfld.long 0x00 0. "  GSB192  ,Group Status Bit 192" "Group 0,Group 1"
else
rgroup.long 0x0098++0x03
line.long 0x0 "GICD_IGROUPR6,Interrupt Group Register 6"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x07)&&(PER.ADDRESS.isSECUREEX(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x009C))
group.long 0x009C++0x03
line.long 0x0 "GICD_IGROUPR7,Interrupt Group Register 7 (Secure access)"
bitfld.long 0x00 31. " GSB255  ,Group Status Bit 255" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 30. "  GSB254  ,Group Status Bit 254" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 29. "  GSB253  ,Group Status Bit 253" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 28. " GSB252  ,Group Status Bit 252" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 27. "  GSB251  ,Group Status Bit 251" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 26. "  GSB250  ,Group Status Bit 250" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 25. " GSB249  ,Group Status Bit 249" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 24. "  GSB248  ,Group Status Bit 248" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 23. "  GSB247  ,Group Status Bit 247" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 22. " GSB246  ,Group Status Bit 246" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 21. "  GSB245  ,Group Status Bit 245" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 20. "  GSB244  ,Group Status Bit 244" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 19. " GSB243  ,Group Status Bit 243" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 18. "  GSB242  ,Group Status Bit 242" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 17. "  GSB241  ,Group Status Bit 241" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 16. " GSB240  ,Group Status Bit 240" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 15. "  GSB239  ,Group Status Bit 239" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 14. "  GSB238  ,Group Status Bit 238" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 13. " GSB237  ,Group Status Bit 237" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 12. "  GSB236  ,Group Status Bit 236" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 11. "  GSB235  ,Group Status Bit 235" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 10. " GSB234  ,Group Status Bit 234" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 9. "  GSB233  ,Group Status Bit 233" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 8. "  GSB232  ,Group Status Bit 232" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 7. " GSB231  ,Group Status Bit 231" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 6. "  GSB230  ,Group Status Bit 230" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 5. "  GSB229  ,Group Status Bit 229" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 4. " GSB228  ,Group Status Bit 228" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 3. "  GSB227  ,Group Status Bit 227" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 2. "  GSB226  ,Group Status Bit 226" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 1. " GSB225  ,Group Status Bit 225" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 0. "  GSB224  ,Group Status Bit 224" "Group 0 (Secure),Group 1 (Non-secure)"
elif (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x07)
group.long 0x009C++0x03
line.long 0x0 "GICD_IGROUPR7,Interrupt Group Register 7 (Non-secure access)"
bitfld.long 0x00 31. " GSB255  ,Group Status Bit 255" "Group 0,Group 1"
bitfld.long 0x00 30. "  GSB254  ,Group Status Bit 254" "Group 0,Group 1"
bitfld.long 0x00 29. "  GSB253  ,Group Status Bit 253" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB252  ,Group Status Bit 252" "Group 0,Group 1"
bitfld.long 0x00 27. "  GSB251  ,Group Status Bit 251" "Group 0,Group 1"
bitfld.long 0x00 26. "  GSB250  ,Group Status Bit 250" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB249  ,Group Status Bit 249" "Group 0,Group 1"
bitfld.long 0x00 24. "  GSB248  ,Group Status Bit 248" "Group 0,Group 1"
bitfld.long 0x00 23. "  GSB247  ,Group Status Bit 247" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB246  ,Group Status Bit 246" "Group 0,Group 1"
bitfld.long 0x00 21. "  GSB245  ,Group Status Bit 245" "Group 0,Group 1"
bitfld.long 0x00 20. "  GSB244  ,Group Status Bit 244" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB243  ,Group Status Bit 243" "Group 0,Group 1"
bitfld.long 0x00 18. "  GSB242  ,Group Status Bit 242" "Group 0,Group 1"
bitfld.long 0x00 17. "  GSB241  ,Group Status Bit 241" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB240  ,Group Status Bit 240" "Group 0,Group 1"
bitfld.long 0x00 15. "  GSB239  ,Group Status Bit 239" "Group 0,Group 1"
bitfld.long 0x00 14. "  GSB238  ,Group Status Bit 238" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB237  ,Group Status Bit 237" "Group 0,Group 1"
bitfld.long 0x00 12. "  GSB236  ,Group Status Bit 236" "Group 0,Group 1"
bitfld.long 0x00 11. "  GSB235  ,Group Status Bit 235" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB234  ,Group Status Bit 234" "Group 0,Group 1"
bitfld.long 0x00 9. "  GSB233  ,Group Status Bit 233" "Group 0,Group 1"
bitfld.long 0x00 8. "  GSB232  ,Group Status Bit 232" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB231  ,Group Status Bit 231" "Group 0,Group 1"
bitfld.long 0x00 6. "  GSB230  ,Group Status Bit 230" "Group 0,Group 1"
bitfld.long 0x00 5. "  GSB229  ,Group Status Bit 229" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB228  ,Group Status Bit 228" "Group 0,Group 1"
bitfld.long 0x00 3. "  GSB227  ,Group Status Bit 227" "Group 0,Group 1"
bitfld.long 0x00 2. "  GSB226  ,Group Status Bit 226" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB225  ,Group Status Bit 225" "Group 0,Group 1"
bitfld.long 0x00 0. "  GSB224  ,Group Status Bit 224" "Group 0,Group 1"
else
rgroup.long 0x009C++0x03
line.long 0x0 "GICD_IGROUPR7,Interrupt Group Register 7"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x08)&&(PER.ADDRESS.isSECUREEX(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x00A0))
group.long 0x00A0++0x03
line.long 0x0 "GICD_IGROUPR8,Interrupt Group Register 8 (Secure access)"
bitfld.long 0x00 31. " GSB287  ,Group Status Bit 287" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 30. "  GSB286  ,Group Status Bit 286" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 29. "  GSB285  ,Group Status Bit 285" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 28. " GSB284  ,Group Status Bit 284" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 27. "  GSB283  ,Group Status Bit 283" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 26. "  GSB282  ,Group Status Bit 282" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 25. " GSB281  ,Group Status Bit 281" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 24. "  GSB280  ,Group Status Bit 280" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 23. "  GSB279  ,Group Status Bit 279" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 22. " GSB278  ,Group Status Bit 278" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 21. "  GSB277  ,Group Status Bit 277" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 20. "  GSB276  ,Group Status Bit 276" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 19. " GSB275  ,Group Status Bit 275" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 18. "  GSB274  ,Group Status Bit 274" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 17. "  GSB273  ,Group Status Bit 273" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 16. " GSB272  ,Group Status Bit 272" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 15. "  GSB271  ,Group Status Bit 271" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 14. "  GSB270  ,Group Status Bit 270" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 13. " GSB269  ,Group Status Bit 269" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 12. "  GSB268  ,Group Status Bit 268" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 11. "  GSB267  ,Group Status Bit 267" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 10. " GSB266  ,Group Status Bit 266" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 9. "  GSB265  ,Group Status Bit 265" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 8. "  GSB264  ,Group Status Bit 264" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 7. " GSB263  ,Group Status Bit 263" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 6. "  GSB262  ,Group Status Bit 262" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 5. "  GSB261  ,Group Status Bit 261" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 4. " GSB260  ,Group Status Bit 260" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 3. "  GSB259  ,Group Status Bit 259" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 2. "  GSB258  ,Group Status Bit 258" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 1. " GSB257  ,Group Status Bit 257" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 0. "  GSB256  ,Group Status Bit 256" "Group 0 (Secure),Group 1 (Non-secure)"
elif (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x08)
group.long 0x00A0++0x03
line.long 0x0 "GICD_IGROUPR8,Interrupt Group Register 8 (Non-secure access)"
bitfld.long 0x00 31. " GSB287  ,Group Status Bit 287" "Group 0,Group 1"
bitfld.long 0x00 30. "  GSB286  ,Group Status Bit 286" "Group 0,Group 1"
bitfld.long 0x00 29. "  GSB285  ,Group Status Bit 285" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB284  ,Group Status Bit 284" "Group 0,Group 1"
bitfld.long 0x00 27. "  GSB283  ,Group Status Bit 283" "Group 0,Group 1"
bitfld.long 0x00 26. "  GSB282  ,Group Status Bit 282" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB281  ,Group Status Bit 281" "Group 0,Group 1"
bitfld.long 0x00 24. "  GSB280  ,Group Status Bit 280" "Group 0,Group 1"
bitfld.long 0x00 23. "  GSB279  ,Group Status Bit 279" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB278  ,Group Status Bit 278" "Group 0,Group 1"
bitfld.long 0x00 21. "  GSB277  ,Group Status Bit 277" "Group 0,Group 1"
bitfld.long 0x00 20. "  GSB276  ,Group Status Bit 276" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB275  ,Group Status Bit 275" "Group 0,Group 1"
bitfld.long 0x00 18. "  GSB274  ,Group Status Bit 274" "Group 0,Group 1"
bitfld.long 0x00 17. "  GSB273  ,Group Status Bit 273" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB272  ,Group Status Bit 272" "Group 0,Group 1"
bitfld.long 0x00 15. "  GSB271  ,Group Status Bit 271" "Group 0,Group 1"
bitfld.long 0x00 14. "  GSB270  ,Group Status Bit 270" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB269  ,Group Status Bit 269" "Group 0,Group 1"
bitfld.long 0x00 12. "  GSB268  ,Group Status Bit 268" "Group 0,Group 1"
bitfld.long 0x00 11. "  GSB267  ,Group Status Bit 267" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB266  ,Group Status Bit 266" "Group 0,Group 1"
bitfld.long 0x00 9. "  GSB265  ,Group Status Bit 265" "Group 0,Group 1"
bitfld.long 0x00 8. "  GSB264  ,Group Status Bit 264" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB263  ,Group Status Bit 263" "Group 0,Group 1"
bitfld.long 0x00 6. "  GSB262  ,Group Status Bit 262" "Group 0,Group 1"
bitfld.long 0x00 5. "  GSB261  ,Group Status Bit 261" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB260  ,Group Status Bit 260" "Group 0,Group 1"
bitfld.long 0x00 3. "  GSB259  ,Group Status Bit 259" "Group 0,Group 1"
bitfld.long 0x00 2. "  GSB258  ,Group Status Bit 258" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB257  ,Group Status Bit 257" "Group 0,Group 1"
bitfld.long 0x00 0. "  GSB256  ,Group Status Bit 256" "Group 0,Group 1"
else
rgroup.long 0x00A0++0x03
line.long 0x0 "GICD_IGROUPR8,Interrupt Group Register 8"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x09)&&(PER.ADDRESS.isSECUREEX(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x00A4))
group.long 0x00A4++0x03
line.long 0x0 "GICD_IGROUPR9,Interrupt Group Register 9 (Secure access)"
bitfld.long 0x00 31. " GSB319  ,Group Status Bit 319" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 30. "  GSB318  ,Group Status Bit 318" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 29. "  GSB317  ,Group Status Bit 317" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 28. " GSB316  ,Group Status Bit 316" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 27. "  GSB315  ,Group Status Bit 315" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 26. "  GSB314  ,Group Status Bit 314" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 25. " GSB313  ,Group Status Bit 313" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 24. "  GSB312  ,Group Status Bit 312" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 23. "  GSB311  ,Group Status Bit 311" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 22. " GSB310  ,Group Status Bit 310" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 21. "  GSB309  ,Group Status Bit 309" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 20. "  GSB308  ,Group Status Bit 308" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 19. " GSB307  ,Group Status Bit 307" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 18. "  GSB306  ,Group Status Bit 306" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 17. "  GSB305  ,Group Status Bit 305" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 16. " GSB304  ,Group Status Bit 304" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 15. "  GSB303  ,Group Status Bit 303" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 14. "  GSB302  ,Group Status Bit 302" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 13. " GSB301  ,Group Status Bit 301" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 12. "  GSB300  ,Group Status Bit 300" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 11. "  GSB299  ,Group Status Bit 299" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 10. " GSB298  ,Group Status Bit 298" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 9. "  GSB297  ,Group Status Bit 297" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 8. "  GSB296  ,Group Status Bit 296" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 7. " GSB295  ,Group Status Bit 295" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 6. "  GSB294  ,Group Status Bit 294" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 5. "  GSB293  ,Group Status Bit 293" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 4. " GSB292  ,Group Status Bit 292" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 3. "  GSB291  ,Group Status Bit 291" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 2. "  GSB290  ,Group Status Bit 290" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 1. " GSB289  ,Group Status Bit 289" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 0. "  GSB288  ,Group Status Bit 288" "Group 0 (Secure),Group 1 (Non-secure)"
elif (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x09)
group.long 0x00A4++0x03
line.long 0x0 "GICD_IGROUPR9,Interrupt Group Register 9 (Non-secure access)"
bitfld.long 0x00 31. " GSB319  ,Group Status Bit 319" "Group 0,Group 1"
bitfld.long 0x00 30. "  GSB318  ,Group Status Bit 318" "Group 0,Group 1"
bitfld.long 0x00 29. "  GSB317  ,Group Status Bit 317" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB316  ,Group Status Bit 316" "Group 0,Group 1"
bitfld.long 0x00 27. "  GSB315  ,Group Status Bit 315" "Group 0,Group 1"
bitfld.long 0x00 26. "  GSB314  ,Group Status Bit 314" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB313  ,Group Status Bit 313" "Group 0,Group 1"
bitfld.long 0x00 24. "  GSB312  ,Group Status Bit 312" "Group 0,Group 1"
bitfld.long 0x00 23. "  GSB311  ,Group Status Bit 311" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB310  ,Group Status Bit 310" "Group 0,Group 1"
bitfld.long 0x00 21. "  GSB309  ,Group Status Bit 309" "Group 0,Group 1"
bitfld.long 0x00 20. "  GSB308  ,Group Status Bit 308" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB307  ,Group Status Bit 307" "Group 0,Group 1"
bitfld.long 0x00 18. "  GSB306  ,Group Status Bit 306" "Group 0,Group 1"
bitfld.long 0x00 17. "  GSB305  ,Group Status Bit 305" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB304  ,Group Status Bit 304" "Group 0,Group 1"
bitfld.long 0x00 15. "  GSB303  ,Group Status Bit 303" "Group 0,Group 1"
bitfld.long 0x00 14. "  GSB302  ,Group Status Bit 302" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB301  ,Group Status Bit 301" "Group 0,Group 1"
bitfld.long 0x00 12. "  GSB300  ,Group Status Bit 300" "Group 0,Group 1"
bitfld.long 0x00 11. "  GSB299  ,Group Status Bit 299" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB298  ,Group Status Bit 298" "Group 0,Group 1"
bitfld.long 0x00 9. "  GSB297  ,Group Status Bit 297" "Group 0,Group 1"
bitfld.long 0x00 8. "  GSB296  ,Group Status Bit 296" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB295  ,Group Status Bit 295" "Group 0,Group 1"
bitfld.long 0x00 6. "  GSB294  ,Group Status Bit 294" "Group 0,Group 1"
bitfld.long 0x00 5. "  GSB293  ,Group Status Bit 293" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB292  ,Group Status Bit 292" "Group 0,Group 1"
bitfld.long 0x00 3. "  GSB291  ,Group Status Bit 291" "Group 0,Group 1"
bitfld.long 0x00 2. "  GSB290  ,Group Status Bit 290" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB289  ,Group Status Bit 289" "Group 0,Group 1"
bitfld.long 0x00 0. "  GSB288  ,Group Status Bit 288" "Group 0,Group 1"
else
rgroup.long 0x00A4++0x03
line.long 0x0 "GICD_IGROUPR9,Interrupt Group Register 9"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0A)&&(PER.ADDRESS.isSECUREEX(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x00A8))
group.long 0x00A8++0x03
line.long 0x0 "GICD_IGROUPR10,Interrupt Group Register 10 (Secure access)"
bitfld.long 0x00 31. " GSB351  ,Group Status Bit 351" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 30. "  GSB350  ,Group Status Bit 350" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 29. "  GSB349  ,Group Status Bit 349" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 28. " GSB348  ,Group Status Bit 348" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 27. "  GSB347  ,Group Status Bit 347" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 26. "  GSB346  ,Group Status Bit 346" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 25. " GSB345  ,Group Status Bit 345" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 24. "  GSB344  ,Group Status Bit 344" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 23. "  GSB343  ,Group Status Bit 343" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 22. " GSB342  ,Group Status Bit 342" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 21. "  GSB341  ,Group Status Bit 341" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 20. "  GSB340  ,Group Status Bit 340" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 19. " GSB339  ,Group Status Bit 339" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 18. "  GSB338  ,Group Status Bit 338" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 17. "  GSB337  ,Group Status Bit 337" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 16. " GSB336  ,Group Status Bit 336" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 15. "  GSB335  ,Group Status Bit 335" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 14. "  GSB334  ,Group Status Bit 334" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 13. " GSB333  ,Group Status Bit 333" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 12. "  GSB332  ,Group Status Bit 332" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 11. "  GSB331  ,Group Status Bit 331" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 10. " GSB330  ,Group Status Bit 330" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 9. "  GSB329  ,Group Status Bit 329" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 8. "  GSB328  ,Group Status Bit 328" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 7. " GSB327  ,Group Status Bit 327" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 6. "  GSB326  ,Group Status Bit 326" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 5. "  GSB325  ,Group Status Bit 325" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 4. " GSB324  ,Group Status Bit 324" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 3. "  GSB323  ,Group Status Bit 323" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 2. "  GSB322  ,Group Status Bit 322" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 1. " GSB321  ,Group Status Bit 321" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 0. "  GSB320  ,Group Status Bit 320" "Group 0 (Secure),Group 1 (Non-secure)"
elif (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0A)
group.long 0x00A8++0x03
line.long 0x0 "GICD_IGROUPR10,Interrupt Group Register 10 (Non-secure access)"
bitfld.long 0x00 31. " GSB351  ,Group Status Bit 351" "Group 0,Group 1"
bitfld.long 0x00 30. "  GSB350  ,Group Status Bit 350" "Group 0,Group 1"
bitfld.long 0x00 29. "  GSB349  ,Group Status Bit 349" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB348  ,Group Status Bit 348" "Group 0,Group 1"
bitfld.long 0x00 27. "  GSB347  ,Group Status Bit 347" "Group 0,Group 1"
bitfld.long 0x00 26. "  GSB346  ,Group Status Bit 346" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB345  ,Group Status Bit 345" "Group 0,Group 1"
bitfld.long 0x00 24. "  GSB344  ,Group Status Bit 344" "Group 0,Group 1"
bitfld.long 0x00 23. "  GSB343  ,Group Status Bit 343" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB342  ,Group Status Bit 342" "Group 0,Group 1"
bitfld.long 0x00 21. "  GSB341  ,Group Status Bit 341" "Group 0,Group 1"
bitfld.long 0x00 20. "  GSB340  ,Group Status Bit 340" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB339  ,Group Status Bit 339" "Group 0,Group 1"
bitfld.long 0x00 18. "  GSB338  ,Group Status Bit 338" "Group 0,Group 1"
bitfld.long 0x00 17. "  GSB337  ,Group Status Bit 337" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB336  ,Group Status Bit 336" "Group 0,Group 1"
bitfld.long 0x00 15. "  GSB335  ,Group Status Bit 335" "Group 0,Group 1"
bitfld.long 0x00 14. "  GSB334  ,Group Status Bit 334" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB333  ,Group Status Bit 333" "Group 0,Group 1"
bitfld.long 0x00 12. "  GSB332  ,Group Status Bit 332" "Group 0,Group 1"
bitfld.long 0x00 11. "  GSB331  ,Group Status Bit 331" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB330  ,Group Status Bit 330" "Group 0,Group 1"
bitfld.long 0x00 9. "  GSB329  ,Group Status Bit 329" "Group 0,Group 1"
bitfld.long 0x00 8. "  GSB328  ,Group Status Bit 328" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB327  ,Group Status Bit 327" "Group 0,Group 1"
bitfld.long 0x00 6. "  GSB326  ,Group Status Bit 326" "Group 0,Group 1"
bitfld.long 0x00 5. "  GSB325  ,Group Status Bit 325" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB324  ,Group Status Bit 324" "Group 0,Group 1"
bitfld.long 0x00 3. "  GSB323  ,Group Status Bit 323" "Group 0,Group 1"
bitfld.long 0x00 2. "  GSB322  ,Group Status Bit 322" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB321  ,Group Status Bit 321" "Group 0,Group 1"
bitfld.long 0x00 0. "  GSB320  ,Group Status Bit 320" "Group 0,Group 1"
else
rgroup.long 0x00A8++0x03
line.long 0x0 "GICD_IGROUPR10,Interrupt Group Register 10"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0B)&&(PER.ADDRESS.isSECUREEX(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x00AC))
group.long 0x00AC++0x03
line.long 0x0 "GICD_IGROUPR11,Interrupt Group Register 11 (Secure access)"
bitfld.long 0x00 31. " GSB383  ,Group Status Bit 383" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 30. "  GSB382  ,Group Status Bit 382" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 29. "  GSB381  ,Group Status Bit 381" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 28. " GSB380  ,Group Status Bit 380" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 27. "  GSB379  ,Group Status Bit 379" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 26. "  GSB378  ,Group Status Bit 378" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 25. " GSB377  ,Group Status Bit 377" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 24. "  GSB376  ,Group Status Bit 376" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 23. "  GSB375  ,Group Status Bit 375" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 22. " GSB374  ,Group Status Bit 374" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 21. "  GSB373  ,Group Status Bit 373" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 20. "  GSB372  ,Group Status Bit 372" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 19. " GSB371  ,Group Status Bit 371" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 18. "  GSB370  ,Group Status Bit 370" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 17. "  GSB369  ,Group Status Bit 369" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 16. " GSB368  ,Group Status Bit 368" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 15. "  GSB367  ,Group Status Bit 367" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 14. "  GSB366  ,Group Status Bit 366" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 13. " GSB365  ,Group Status Bit 365" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 12. "  GSB364  ,Group Status Bit 364" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 11. "  GSB363  ,Group Status Bit 363" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 10. " GSB362  ,Group Status Bit 362" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 9. "  GSB361  ,Group Status Bit 361" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 8. "  GSB360  ,Group Status Bit 360" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 7. " GSB359  ,Group Status Bit 359" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 6. "  GSB358  ,Group Status Bit 358" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 5. "  GSB357  ,Group Status Bit 357" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 4. " GSB356  ,Group Status Bit 356" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 3. "  GSB355  ,Group Status Bit 355" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 2. "  GSB354  ,Group Status Bit 354" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 1. " GSB353  ,Group Status Bit 353" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 0. "  GSB352  ,Group Status Bit 352" "Group 0 (Secure),Group 1 (Non-secure)"
elif (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0B)
group.long 0x00AC++0x03
line.long 0x0 "GICD_IGROUPR11,Interrupt Group Register 11 (Non-secure access)"
bitfld.long 0x00 31. " GSB383  ,Group Status Bit 383" "Group 0,Group 1"
bitfld.long 0x00 30. "  GSB382  ,Group Status Bit 382" "Group 0,Group 1"
bitfld.long 0x00 29. "  GSB381  ,Group Status Bit 381" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB380  ,Group Status Bit 380" "Group 0,Group 1"
bitfld.long 0x00 27. "  GSB379  ,Group Status Bit 379" "Group 0,Group 1"
bitfld.long 0x00 26. "  GSB378  ,Group Status Bit 378" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB377  ,Group Status Bit 377" "Group 0,Group 1"
bitfld.long 0x00 24. "  GSB376  ,Group Status Bit 376" "Group 0,Group 1"
bitfld.long 0x00 23. "  GSB375  ,Group Status Bit 375" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB374  ,Group Status Bit 374" "Group 0,Group 1"
bitfld.long 0x00 21. "  GSB373  ,Group Status Bit 373" "Group 0,Group 1"
bitfld.long 0x00 20. "  GSB372  ,Group Status Bit 372" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB371  ,Group Status Bit 371" "Group 0,Group 1"
bitfld.long 0x00 18. "  GSB370  ,Group Status Bit 370" "Group 0,Group 1"
bitfld.long 0x00 17. "  GSB369  ,Group Status Bit 369" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB368  ,Group Status Bit 368" "Group 0,Group 1"
bitfld.long 0x00 15. "  GSB367  ,Group Status Bit 367" "Group 0,Group 1"
bitfld.long 0x00 14. "  GSB366  ,Group Status Bit 366" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB365  ,Group Status Bit 365" "Group 0,Group 1"
bitfld.long 0x00 12. "  GSB364  ,Group Status Bit 364" "Group 0,Group 1"
bitfld.long 0x00 11. "  GSB363  ,Group Status Bit 363" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB362  ,Group Status Bit 362" "Group 0,Group 1"
bitfld.long 0x00 9. "  GSB361  ,Group Status Bit 361" "Group 0,Group 1"
bitfld.long 0x00 8. "  GSB360  ,Group Status Bit 360" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB359  ,Group Status Bit 359" "Group 0,Group 1"
bitfld.long 0x00 6. "  GSB358  ,Group Status Bit 358" "Group 0,Group 1"
bitfld.long 0x00 5. "  GSB357  ,Group Status Bit 357" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB356  ,Group Status Bit 356" "Group 0,Group 1"
bitfld.long 0x00 3. "  GSB355  ,Group Status Bit 355" "Group 0,Group 1"
bitfld.long 0x00 2. "  GSB354  ,Group Status Bit 354" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB353  ,Group Status Bit 353" "Group 0,Group 1"
bitfld.long 0x00 0. "  GSB352  ,Group Status Bit 352" "Group 0,Group 1"
else
rgroup.long 0x00AC++0x03
line.long 0x0 "GICD_IGROUPR11,Interrupt Group Register 11"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0C)&&(PER.ADDRESS.isSECUREEX(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x00B0))
group.long 0x00B0++0x03
line.long 0x0 "GICD_IGROUPR12,Interrupt Group Register 12 (Secure access)"
bitfld.long 0x00 31. " GSB415  ,Group Status Bit 415" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 30. "  GSB414  ,Group Status Bit 414" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 29. "  GSB413  ,Group Status Bit 413" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 28. " GSB412  ,Group Status Bit 412" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 27. "  GSB411  ,Group Status Bit 411" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 26. "  GSB410  ,Group Status Bit 410" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 25. " GSB409  ,Group Status Bit 409" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 24. "  GSB408  ,Group Status Bit 408" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 23. "  GSB407  ,Group Status Bit 407" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 22. " GSB406  ,Group Status Bit 406" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 21. "  GSB405  ,Group Status Bit 405" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 20. "  GSB404  ,Group Status Bit 404" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 19. " GSB403  ,Group Status Bit 403" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 18. "  GSB402  ,Group Status Bit 402" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 17. "  GSB401  ,Group Status Bit 401" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 16. " GSB400  ,Group Status Bit 400" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 15. "  GSB399  ,Group Status Bit 399" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 14. "  GSB398  ,Group Status Bit 398" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 13. " GSB397  ,Group Status Bit 397" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 12. "  GSB396  ,Group Status Bit 396" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 11. "  GSB395  ,Group Status Bit 395" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 10. " GSB394  ,Group Status Bit 394" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 9. "  GSB393  ,Group Status Bit 393" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 8. "  GSB392  ,Group Status Bit 392" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 7. " GSB391  ,Group Status Bit 391" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 6. "  GSB390  ,Group Status Bit 390" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 5. "  GSB389  ,Group Status Bit 389" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 4. " GSB388  ,Group Status Bit 388" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 3. "  GSB387  ,Group Status Bit 387" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 2. "  GSB386  ,Group Status Bit 386" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 1. " GSB385  ,Group Status Bit 385" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 0. "  GSB384  ,Group Status Bit 384" "Group 0 (Secure),Group 1 (Non-secure)"
elif (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0C)
group.long 0x00B0++0x03
line.long 0x0 "GICD_IGROUPR12,Interrupt Group Register 12 (Non-secure access)"
bitfld.long 0x00 31. " GSB415  ,Group Status Bit 415" "Group 0,Group 1"
bitfld.long 0x00 30. "  GSB414  ,Group Status Bit 414" "Group 0,Group 1"
bitfld.long 0x00 29. "  GSB413  ,Group Status Bit 413" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB412  ,Group Status Bit 412" "Group 0,Group 1"
bitfld.long 0x00 27. "  GSB411  ,Group Status Bit 411" "Group 0,Group 1"
bitfld.long 0x00 26. "  GSB410  ,Group Status Bit 410" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB409  ,Group Status Bit 409" "Group 0,Group 1"
bitfld.long 0x00 24. "  GSB408  ,Group Status Bit 408" "Group 0,Group 1"
bitfld.long 0x00 23. "  GSB407  ,Group Status Bit 407" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB406  ,Group Status Bit 406" "Group 0,Group 1"
bitfld.long 0x00 21. "  GSB405  ,Group Status Bit 405" "Group 0,Group 1"
bitfld.long 0x00 20. "  GSB404  ,Group Status Bit 404" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB403  ,Group Status Bit 403" "Group 0,Group 1"
bitfld.long 0x00 18. "  GSB402  ,Group Status Bit 402" "Group 0,Group 1"
bitfld.long 0x00 17. "  GSB401  ,Group Status Bit 401" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB400  ,Group Status Bit 400" "Group 0,Group 1"
bitfld.long 0x00 15. "  GSB399  ,Group Status Bit 399" "Group 0,Group 1"
bitfld.long 0x00 14. "  GSB398  ,Group Status Bit 398" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB397  ,Group Status Bit 397" "Group 0,Group 1"
bitfld.long 0x00 12. "  GSB396  ,Group Status Bit 396" "Group 0,Group 1"
bitfld.long 0x00 11. "  GSB395  ,Group Status Bit 395" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB394  ,Group Status Bit 394" "Group 0,Group 1"
bitfld.long 0x00 9. "  GSB393  ,Group Status Bit 393" "Group 0,Group 1"
bitfld.long 0x00 8. "  GSB392  ,Group Status Bit 392" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB391  ,Group Status Bit 391" "Group 0,Group 1"
bitfld.long 0x00 6. "  GSB390  ,Group Status Bit 390" "Group 0,Group 1"
bitfld.long 0x00 5. "  GSB389  ,Group Status Bit 389" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB388  ,Group Status Bit 388" "Group 0,Group 1"
bitfld.long 0x00 3. "  GSB387  ,Group Status Bit 387" "Group 0,Group 1"
bitfld.long 0x00 2. "  GSB386  ,Group Status Bit 386" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB385  ,Group Status Bit 385" "Group 0,Group 1"
bitfld.long 0x00 0. "  GSB384  ,Group Status Bit 384" "Group 0,Group 1"
else
rgroup.long 0x00B0++0x03
line.long 0x0 "GICD_IGROUPR12,Interrupt Group Register 12"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0D)&&(PER.ADDRESS.isSECUREEX(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x00B4))
group.long 0x00B4++0x03
line.long 0x0 "GICD_IGROUPR13,Interrupt Group Register 13 (Secure access)"
bitfld.long 0x00 31. " GSB447  ,Group Status Bit 447" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 30. "  GSB446  ,Group Status Bit 446" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 29. "  GSB445  ,Group Status Bit 445" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 28. " GSB444  ,Group Status Bit 444" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 27. "  GSB443  ,Group Status Bit 443" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 26. "  GSB442  ,Group Status Bit 442" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 25. " GSB441  ,Group Status Bit 441" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 24. "  GSB440  ,Group Status Bit 440" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 23. "  GSB439  ,Group Status Bit 439" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 22. " GSB438  ,Group Status Bit 438" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 21. "  GSB437  ,Group Status Bit 437" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 20. "  GSB436  ,Group Status Bit 436" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 19. " GSB435  ,Group Status Bit 435" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 18. "  GSB434  ,Group Status Bit 434" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 17. "  GSB433  ,Group Status Bit 433" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 16. " GSB432  ,Group Status Bit 432" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 15. "  GSB431  ,Group Status Bit 431" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 14. "  GSB430  ,Group Status Bit 430" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 13. " GSB429  ,Group Status Bit 429" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 12. "  GSB428  ,Group Status Bit 428" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 11. "  GSB427  ,Group Status Bit 427" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 10. " GSB426  ,Group Status Bit 426" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 9. "  GSB425  ,Group Status Bit 425" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 8. "  GSB424  ,Group Status Bit 424" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 7. " GSB423  ,Group Status Bit 423" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 6. "  GSB422  ,Group Status Bit 422" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 5. "  GSB421  ,Group Status Bit 421" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 4. " GSB420  ,Group Status Bit 420" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 3. "  GSB419  ,Group Status Bit 419" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 2. "  GSB418  ,Group Status Bit 418" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 1. " GSB417  ,Group Status Bit 417" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 0. "  GSB416  ,Group Status Bit 416" "Group 0 (Secure),Group 1 (Non-secure)"
elif (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0D)
group.long 0x00B4++0x03
line.long 0x0 "GICD_IGROUPR13,Interrupt Group Register 13 (Non-secure access)"
bitfld.long 0x00 31. " GSB447  ,Group Status Bit 447" "Group 0,Group 1"
bitfld.long 0x00 30. "  GSB446  ,Group Status Bit 446" "Group 0,Group 1"
bitfld.long 0x00 29. "  GSB445  ,Group Status Bit 445" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB444  ,Group Status Bit 444" "Group 0,Group 1"
bitfld.long 0x00 27. "  GSB443  ,Group Status Bit 443" "Group 0,Group 1"
bitfld.long 0x00 26. "  GSB442  ,Group Status Bit 442" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB441  ,Group Status Bit 441" "Group 0,Group 1"
bitfld.long 0x00 24. "  GSB440  ,Group Status Bit 440" "Group 0,Group 1"
bitfld.long 0x00 23. "  GSB439  ,Group Status Bit 439" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB438  ,Group Status Bit 438" "Group 0,Group 1"
bitfld.long 0x00 21. "  GSB437  ,Group Status Bit 437" "Group 0,Group 1"
bitfld.long 0x00 20. "  GSB436  ,Group Status Bit 436" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB435  ,Group Status Bit 435" "Group 0,Group 1"
bitfld.long 0x00 18. "  GSB434  ,Group Status Bit 434" "Group 0,Group 1"
bitfld.long 0x00 17. "  GSB433  ,Group Status Bit 433" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB432  ,Group Status Bit 432" "Group 0,Group 1"
bitfld.long 0x00 15. "  GSB431  ,Group Status Bit 431" "Group 0,Group 1"
bitfld.long 0x00 14. "  GSB430  ,Group Status Bit 430" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB429  ,Group Status Bit 429" "Group 0,Group 1"
bitfld.long 0x00 12. "  GSB428  ,Group Status Bit 428" "Group 0,Group 1"
bitfld.long 0x00 11. "  GSB427  ,Group Status Bit 427" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB426  ,Group Status Bit 426" "Group 0,Group 1"
bitfld.long 0x00 9. "  GSB425  ,Group Status Bit 425" "Group 0,Group 1"
bitfld.long 0x00 8. "  GSB424  ,Group Status Bit 424" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB423  ,Group Status Bit 423" "Group 0,Group 1"
bitfld.long 0x00 6. "  GSB422  ,Group Status Bit 422" "Group 0,Group 1"
bitfld.long 0x00 5. "  GSB421  ,Group Status Bit 421" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB420  ,Group Status Bit 420" "Group 0,Group 1"
bitfld.long 0x00 3. "  GSB419  ,Group Status Bit 419" "Group 0,Group 1"
bitfld.long 0x00 2. "  GSB418  ,Group Status Bit 418" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB417  ,Group Status Bit 417" "Group 0,Group 1"
bitfld.long 0x00 0. "  GSB416  ,Group Status Bit 416" "Group 0,Group 1"
else
rgroup.long 0x00B4++0x03
line.long 0x0 "GICD_IGROUPR13,Interrupt Group Register 13"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0E)&&(PER.ADDRESS.isSECUREEX(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x00B8))
group.long 0x00B8++0x03
line.long 0x0 "GICD_IGROUPR14,Interrupt Group Register 14 (Secure access)"
bitfld.long 0x00 31. " GSB479  ,Group Status Bit 479" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 30. "  GSB478  ,Group Status Bit 478" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 29. "  GSB477  ,Group Status Bit 477" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 28. " GSB476  ,Group Status Bit 476" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 27. "  GSB475  ,Group Status Bit 475" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 26. "  GSB474  ,Group Status Bit 474" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 25. " GSB473  ,Group Status Bit 473" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 24. "  GSB472  ,Group Status Bit 472" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 23. "  GSB471  ,Group Status Bit 471" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 22. " GSB470  ,Group Status Bit 470" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 21. "  GSB469  ,Group Status Bit 469" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 20. "  GSB468  ,Group Status Bit 468" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 19. " GSB467  ,Group Status Bit 467" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 18. "  GSB466  ,Group Status Bit 466" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 17. "  GSB465  ,Group Status Bit 465" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 16. " GSB464  ,Group Status Bit 464" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 15. "  GSB463  ,Group Status Bit 463" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 14. "  GSB462  ,Group Status Bit 462" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 13. " GSB461  ,Group Status Bit 461" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 12. "  GSB460  ,Group Status Bit 460" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 11. "  GSB459  ,Group Status Bit 459" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 10. " GSB458  ,Group Status Bit 458" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 9. "  GSB457  ,Group Status Bit 457" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 8. "  GSB456  ,Group Status Bit 456" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 7. " GSB455  ,Group Status Bit 455" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 6. "  GSB454  ,Group Status Bit 454" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 5. "  GSB453  ,Group Status Bit 453" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 4. " GSB452  ,Group Status Bit 452" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 3. "  GSB451  ,Group Status Bit 451" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 2. "  GSB450  ,Group Status Bit 450" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 1. " GSB449  ,Group Status Bit 449" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 0. "  GSB448  ,Group Status Bit 448" "Group 0 (Secure),Group 1 (Non-secure)"
elif (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0E)
group.long 0x00B8++0x03
line.long 0x0 "GICD_IGROUPR14,Interrupt Group Register 14 (Non-secure access)"
bitfld.long 0x00 31. " GSB479  ,Group Status Bit 479" "Group 0,Group 1"
bitfld.long 0x00 30. "  GSB478  ,Group Status Bit 478" "Group 0,Group 1"
bitfld.long 0x00 29. "  GSB477  ,Group Status Bit 477" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB476  ,Group Status Bit 476" "Group 0,Group 1"
bitfld.long 0x00 27. "  GSB475  ,Group Status Bit 475" "Group 0,Group 1"
bitfld.long 0x00 26. "  GSB474  ,Group Status Bit 474" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB473  ,Group Status Bit 473" "Group 0,Group 1"
bitfld.long 0x00 24. "  GSB472  ,Group Status Bit 472" "Group 0,Group 1"
bitfld.long 0x00 23. "  GSB471  ,Group Status Bit 471" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB470  ,Group Status Bit 470" "Group 0,Group 1"
bitfld.long 0x00 21. "  GSB469  ,Group Status Bit 469" "Group 0,Group 1"
bitfld.long 0x00 20. "  GSB468  ,Group Status Bit 468" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB467  ,Group Status Bit 467" "Group 0,Group 1"
bitfld.long 0x00 18. "  GSB466  ,Group Status Bit 466" "Group 0,Group 1"
bitfld.long 0x00 17. "  GSB465  ,Group Status Bit 465" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB464  ,Group Status Bit 464" "Group 0,Group 1"
bitfld.long 0x00 15. "  GSB463  ,Group Status Bit 463" "Group 0,Group 1"
bitfld.long 0x00 14. "  GSB462  ,Group Status Bit 462" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB461  ,Group Status Bit 461" "Group 0,Group 1"
bitfld.long 0x00 12. "  GSB460  ,Group Status Bit 460" "Group 0,Group 1"
bitfld.long 0x00 11. "  GSB459  ,Group Status Bit 459" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB458  ,Group Status Bit 458" "Group 0,Group 1"
bitfld.long 0x00 9. "  GSB457  ,Group Status Bit 457" "Group 0,Group 1"
bitfld.long 0x00 8. "  GSB456  ,Group Status Bit 456" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB455  ,Group Status Bit 455" "Group 0,Group 1"
bitfld.long 0x00 6. "  GSB454  ,Group Status Bit 454" "Group 0,Group 1"
bitfld.long 0x00 5. "  GSB453  ,Group Status Bit 453" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB452  ,Group Status Bit 452" "Group 0,Group 1"
bitfld.long 0x00 3. "  GSB451  ,Group Status Bit 451" "Group 0,Group 1"
bitfld.long 0x00 2. "  GSB450  ,Group Status Bit 450" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB449  ,Group Status Bit 449" "Group 0,Group 1"
bitfld.long 0x00 0. "  GSB448  ,Group Status Bit 448" "Group 0,Group 1"
else
rgroup.long 0x00B8++0x03
line.long 0x0 "GICD_IGROUPR14,Interrupt Group Register 14"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0F)&&(PER.ADDRESS.isSECUREEX(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x00BC))
group.long 0x00BC++0x03
line.long 0x0 "GICD_IGROUPR15,Interrupt Group Register 15 (Secure access)"
bitfld.long 0x00 31. " GSB511  ,Group Status Bit 511" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 30. "  GSB510  ,Group Status Bit 510" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 29. "  GSB509  ,Group Status Bit 509" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 28. " GSB508  ,Group Status Bit 508" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 27. "  GSB507  ,Group Status Bit 507" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 26. "  GSB506  ,Group Status Bit 506" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 25. " GSB505  ,Group Status Bit 505" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 24. "  GSB504  ,Group Status Bit 504" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 23. "  GSB503  ,Group Status Bit 503" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 22. " GSB502  ,Group Status Bit 502" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 21. "  GSB501  ,Group Status Bit 501" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 20. "  GSB500  ,Group Status Bit 500" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 19. " GSB499  ,Group Status Bit 499" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 18. "  GSB498  ,Group Status Bit 498" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 17. "  GSB497  ,Group Status Bit 497" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 16. " GSB496  ,Group Status Bit 496" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 15. "  GSB495  ,Group Status Bit 495" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 14. "  GSB494  ,Group Status Bit 494" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 13. " GSB493  ,Group Status Bit 493" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 12. "  GSB492  ,Group Status Bit 492" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 11. "  GSB491  ,Group Status Bit 491" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 10. " GSB490  ,Group Status Bit 490" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 9. "  GSB489  ,Group Status Bit 489" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 8. "  GSB488  ,Group Status Bit 488" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 7. " GSB487  ,Group Status Bit 487" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 6. "  GSB486  ,Group Status Bit 486" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 5. "  GSB485  ,Group Status Bit 485" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 4. " GSB484  ,Group Status Bit 484" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 3. "  GSB483  ,Group Status Bit 483" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 2. "  GSB482  ,Group Status Bit 482" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 1. " GSB481  ,Group Status Bit 481" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 0. "  GSB480  ,Group Status Bit 480" "Group 0 (Secure),Group 1 (Non-secure)"
elif (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0F)
group.long 0x00BC++0x03
line.long 0x0 "GICD_IGROUPR15,Interrupt Group Register 15 (Non-secure access)"
bitfld.long 0x00 31. " GSB511  ,Group Status Bit 511" "Group 0,Group 1"
bitfld.long 0x00 30. "  GSB510  ,Group Status Bit 510" "Group 0,Group 1"
bitfld.long 0x00 29. "  GSB509  ,Group Status Bit 509" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB508  ,Group Status Bit 508" "Group 0,Group 1"
bitfld.long 0x00 27. "  GSB507  ,Group Status Bit 507" "Group 0,Group 1"
bitfld.long 0x00 26. "  GSB506  ,Group Status Bit 506" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB505  ,Group Status Bit 505" "Group 0,Group 1"
bitfld.long 0x00 24. "  GSB504  ,Group Status Bit 504" "Group 0,Group 1"
bitfld.long 0x00 23. "  GSB503  ,Group Status Bit 503" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB502  ,Group Status Bit 502" "Group 0,Group 1"
bitfld.long 0x00 21. "  GSB501  ,Group Status Bit 501" "Group 0,Group 1"
bitfld.long 0x00 20. "  GSB500  ,Group Status Bit 500" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB499  ,Group Status Bit 499" "Group 0,Group 1"
bitfld.long 0x00 18. "  GSB498  ,Group Status Bit 498" "Group 0,Group 1"
bitfld.long 0x00 17. "  GSB497  ,Group Status Bit 497" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB496  ,Group Status Bit 496" "Group 0,Group 1"
bitfld.long 0x00 15. "  GSB495  ,Group Status Bit 495" "Group 0,Group 1"
bitfld.long 0x00 14. "  GSB494  ,Group Status Bit 494" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB493  ,Group Status Bit 493" "Group 0,Group 1"
bitfld.long 0x00 12. "  GSB492  ,Group Status Bit 492" "Group 0,Group 1"
bitfld.long 0x00 11. "  GSB491  ,Group Status Bit 491" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB490  ,Group Status Bit 490" "Group 0,Group 1"
bitfld.long 0x00 9. "  GSB489  ,Group Status Bit 489" "Group 0,Group 1"
bitfld.long 0x00 8. "  GSB488  ,Group Status Bit 488" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB487  ,Group Status Bit 487" "Group 0,Group 1"
bitfld.long 0x00 6. "  GSB486  ,Group Status Bit 486" "Group 0,Group 1"
bitfld.long 0x00 5. "  GSB485  ,Group Status Bit 485" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB484  ,Group Status Bit 484" "Group 0,Group 1"
bitfld.long 0x00 3. "  GSB483  ,Group Status Bit 483" "Group 0,Group 1"
bitfld.long 0x00 2. "  GSB482  ,Group Status Bit 482" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB481  ,Group Status Bit 481" "Group 0,Group 1"
bitfld.long 0x00 0. "  GSB480  ,Group Status Bit 480" "Group 0,Group 1"
else
rgroup.long 0x00BC++0x03
line.long 0x0 "GICD_IGROUPR15,Interrupt Group Register 15"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x10)&&(PER.ADDRESS.isSECUREEX(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x00C0))
group.long 0x00C0++0x03
line.long 0x0 "GICD_IGROUPR16,Interrupt Group Register 16 (Secure access)"
bitfld.long 0x00 31. " GSB543  ,Group Status Bit 543" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 30. "  GSB542  ,Group Status Bit 542" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 29. "  GSB541  ,Group Status Bit 541" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 28. " GSB540  ,Group Status Bit 540" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 27. "  GSB539  ,Group Status Bit 539" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 26. "  GSB538  ,Group Status Bit 538" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 25. " GSB537  ,Group Status Bit 537" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 24. "  GSB536  ,Group Status Bit 536" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 23. "  GSB535  ,Group Status Bit 535" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 22. " GSB534  ,Group Status Bit 534" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 21. "  GSB533  ,Group Status Bit 533" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 20. "  GSB532  ,Group Status Bit 532" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 19. " GSB531  ,Group Status Bit 531" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 18. "  GSB530  ,Group Status Bit 530" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 17. "  GSB529  ,Group Status Bit 529" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 16. " GSB528  ,Group Status Bit 528" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 15. "  GSB527  ,Group Status Bit 527" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 14. "  GSB526  ,Group Status Bit 526" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 13. " GSB525  ,Group Status Bit 525" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 12. "  GSB524  ,Group Status Bit 524" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 11. "  GSB523  ,Group Status Bit 523" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 10. " GSB522  ,Group Status Bit 522" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 9. "  GSB521  ,Group Status Bit 521" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 8. "  GSB520  ,Group Status Bit 520" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 7. " GSB519  ,Group Status Bit 519" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 6. "  GSB518  ,Group Status Bit 518" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 5. "  GSB517  ,Group Status Bit 517" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 4. " GSB516  ,Group Status Bit 516" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 3. "  GSB515  ,Group Status Bit 515" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 2. "  GSB514  ,Group Status Bit 514" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 1. " GSB513  ,Group Status Bit 513" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 0. "  GSB512  ,Group Status Bit 512" "Group 0 (Secure),Group 1 (Non-secure)"
elif (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x10)
group.long 0x00C0++0x03
line.long 0x0 "GICD_IGROUPR16,Interrupt Group Register 16 (Non-secure access)"
bitfld.long 0x00 31. " GSB543  ,Group Status Bit 543" "Group 0,Group 1"
bitfld.long 0x00 30. "  GSB542  ,Group Status Bit 542" "Group 0,Group 1"
bitfld.long 0x00 29. "  GSB541  ,Group Status Bit 541" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB540  ,Group Status Bit 540" "Group 0,Group 1"
bitfld.long 0x00 27. "  GSB539  ,Group Status Bit 539" "Group 0,Group 1"
bitfld.long 0x00 26. "  GSB538  ,Group Status Bit 538" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB537  ,Group Status Bit 537" "Group 0,Group 1"
bitfld.long 0x00 24. "  GSB536  ,Group Status Bit 536" "Group 0,Group 1"
bitfld.long 0x00 23. "  GSB535  ,Group Status Bit 535" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB534  ,Group Status Bit 534" "Group 0,Group 1"
bitfld.long 0x00 21. "  GSB533  ,Group Status Bit 533" "Group 0,Group 1"
bitfld.long 0x00 20. "  GSB532  ,Group Status Bit 532" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB531  ,Group Status Bit 531" "Group 0,Group 1"
bitfld.long 0x00 18. "  GSB530  ,Group Status Bit 530" "Group 0,Group 1"
bitfld.long 0x00 17. "  GSB529  ,Group Status Bit 529" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB528  ,Group Status Bit 528" "Group 0,Group 1"
bitfld.long 0x00 15. "  GSB527  ,Group Status Bit 527" "Group 0,Group 1"
bitfld.long 0x00 14. "  GSB526  ,Group Status Bit 526" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB525  ,Group Status Bit 525" "Group 0,Group 1"
bitfld.long 0x00 12. "  GSB524  ,Group Status Bit 524" "Group 0,Group 1"
bitfld.long 0x00 11. "  GSB523  ,Group Status Bit 523" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB522  ,Group Status Bit 522" "Group 0,Group 1"
bitfld.long 0x00 9. "  GSB521  ,Group Status Bit 521" "Group 0,Group 1"
bitfld.long 0x00 8. "  GSB520  ,Group Status Bit 520" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB519  ,Group Status Bit 519" "Group 0,Group 1"
bitfld.long 0x00 6. "  GSB518  ,Group Status Bit 518" "Group 0,Group 1"
bitfld.long 0x00 5. "  GSB517  ,Group Status Bit 517" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB516  ,Group Status Bit 516" "Group 0,Group 1"
bitfld.long 0x00 3. "  GSB515  ,Group Status Bit 515" "Group 0,Group 1"
bitfld.long 0x00 2. "  GSB514  ,Group Status Bit 514" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB513  ,Group Status Bit 513" "Group 0,Group 1"
bitfld.long 0x00 0. "  GSB512  ,Group Status Bit 512" "Group 0,Group 1"
else
rgroup.long 0x00C0++0x03
line.long 0x0 "GICD_IGROUPR16,Interrupt Group Register 16"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x11)&&(PER.ADDRESS.isSECUREEX(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x00C4))
group.long 0x00C4++0x03
line.long 0x0 "GICD_IGROUPR17,Interrupt Group Register 17 (Secure access)"
bitfld.long 0x00 31. " GSB575  ,Group Status Bit 575" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 30. "  GSB574  ,Group Status Bit 574" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 29. "  GSB573  ,Group Status Bit 573" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 28. " GSB572  ,Group Status Bit 572" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 27. "  GSB571  ,Group Status Bit 571" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 26. "  GSB570  ,Group Status Bit 570" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 25. " GSB569  ,Group Status Bit 569" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 24. "  GSB568  ,Group Status Bit 568" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 23. "  GSB567  ,Group Status Bit 567" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 22. " GSB566  ,Group Status Bit 566" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 21. "  GSB565  ,Group Status Bit 565" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 20. "  GSB564  ,Group Status Bit 564" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 19. " GSB563  ,Group Status Bit 563" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 18. "  GSB562  ,Group Status Bit 562" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 17. "  GSB561  ,Group Status Bit 561" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 16. " GSB560  ,Group Status Bit 560" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 15. "  GSB559  ,Group Status Bit 559" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 14. "  GSB558  ,Group Status Bit 558" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 13. " GSB557  ,Group Status Bit 557" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 12. "  GSB556  ,Group Status Bit 556" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 11. "  GSB555  ,Group Status Bit 555" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 10. " GSB554  ,Group Status Bit 554" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 9. "  GSB553  ,Group Status Bit 553" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 8. "  GSB552  ,Group Status Bit 552" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 7. " GSB551  ,Group Status Bit 551" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 6. "  GSB550  ,Group Status Bit 550" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 5. "  GSB549  ,Group Status Bit 549" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 4. " GSB548  ,Group Status Bit 548" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 3. "  GSB547  ,Group Status Bit 547" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 2. "  GSB546  ,Group Status Bit 546" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 1. " GSB545  ,Group Status Bit 545" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 0. "  GSB544  ,Group Status Bit 544" "Group 0 (Secure),Group 1 (Non-secure)"
elif (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x11)
group.long 0x00C4++0x03
line.long 0x0 "GICD_IGROUPR17,Interrupt Group Register 17 (Non-secure access)"
bitfld.long 0x00 31. " GSB575  ,Group Status Bit 575" "Group 0,Group 1"
bitfld.long 0x00 30. "  GSB574  ,Group Status Bit 574" "Group 0,Group 1"
bitfld.long 0x00 29. "  GSB573  ,Group Status Bit 573" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB572  ,Group Status Bit 572" "Group 0,Group 1"
bitfld.long 0x00 27. "  GSB571  ,Group Status Bit 571" "Group 0,Group 1"
bitfld.long 0x00 26. "  GSB570  ,Group Status Bit 570" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB569  ,Group Status Bit 569" "Group 0,Group 1"
bitfld.long 0x00 24. "  GSB568  ,Group Status Bit 568" "Group 0,Group 1"
bitfld.long 0x00 23. "  GSB567  ,Group Status Bit 567" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB566  ,Group Status Bit 566" "Group 0,Group 1"
bitfld.long 0x00 21. "  GSB565  ,Group Status Bit 565" "Group 0,Group 1"
bitfld.long 0x00 20. "  GSB564  ,Group Status Bit 564" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB563  ,Group Status Bit 563" "Group 0,Group 1"
bitfld.long 0x00 18. "  GSB562  ,Group Status Bit 562" "Group 0,Group 1"
bitfld.long 0x00 17. "  GSB561  ,Group Status Bit 561" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB560  ,Group Status Bit 560" "Group 0,Group 1"
bitfld.long 0x00 15. "  GSB559  ,Group Status Bit 559" "Group 0,Group 1"
bitfld.long 0x00 14. "  GSB558  ,Group Status Bit 558" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB557  ,Group Status Bit 557" "Group 0,Group 1"
bitfld.long 0x00 12. "  GSB556  ,Group Status Bit 556" "Group 0,Group 1"
bitfld.long 0x00 11. "  GSB555  ,Group Status Bit 555" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB554  ,Group Status Bit 554" "Group 0,Group 1"
bitfld.long 0x00 9. "  GSB553  ,Group Status Bit 553" "Group 0,Group 1"
bitfld.long 0x00 8. "  GSB552  ,Group Status Bit 552" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB551  ,Group Status Bit 551" "Group 0,Group 1"
bitfld.long 0x00 6. "  GSB550  ,Group Status Bit 550" "Group 0,Group 1"
bitfld.long 0x00 5. "  GSB549  ,Group Status Bit 549" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB548  ,Group Status Bit 548" "Group 0,Group 1"
bitfld.long 0x00 3. "  GSB547  ,Group Status Bit 547" "Group 0,Group 1"
bitfld.long 0x00 2. "  GSB546  ,Group Status Bit 546" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB545  ,Group Status Bit 545" "Group 0,Group 1"
bitfld.long 0x00 0. "  GSB544  ,Group Status Bit 544" "Group 0,Group 1"
else
rgroup.long 0x00C4++0x03
line.long 0x0 "GICD_IGROUPR17,Interrupt Group Register 17"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x12)&&(PER.ADDRESS.isSECUREEX(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x00C8))
group.long 0x00C8++0x03
line.long 0x0 "GICD_IGROUPR18,Interrupt Group Register 18 (Secure access)"
bitfld.long 0x00 31. " GSB607  ,Group Status Bit 607" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 30. "  GSB606  ,Group Status Bit 606" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 29. "  GSB605  ,Group Status Bit 605" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 28. " GSB604  ,Group Status Bit 604" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 27. "  GSB603  ,Group Status Bit 603" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 26. "  GSB602  ,Group Status Bit 602" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 25. " GSB601  ,Group Status Bit 601" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 24. "  GSB600  ,Group Status Bit 600" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 23. "  GSB599  ,Group Status Bit 599" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 22. " GSB598  ,Group Status Bit 598" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 21. "  GSB597  ,Group Status Bit 597" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 20. "  GSB596  ,Group Status Bit 596" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 19. " GSB595  ,Group Status Bit 595" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 18. "  GSB594  ,Group Status Bit 594" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 17. "  GSB593  ,Group Status Bit 593" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 16. " GSB592  ,Group Status Bit 592" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 15. "  GSB591  ,Group Status Bit 591" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 14. "  GSB590  ,Group Status Bit 590" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 13. " GSB589  ,Group Status Bit 589" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 12. "  GSB588  ,Group Status Bit 588" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 11. "  GSB587  ,Group Status Bit 587" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 10. " GSB586  ,Group Status Bit 586" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 9. "  GSB585  ,Group Status Bit 585" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 8. "  GSB584  ,Group Status Bit 584" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 7. " GSB583  ,Group Status Bit 583" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 6. "  GSB582  ,Group Status Bit 582" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 5. "  GSB581  ,Group Status Bit 581" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 4. " GSB580  ,Group Status Bit 580" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 3. "  GSB579  ,Group Status Bit 579" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 2. "  GSB578  ,Group Status Bit 578" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 1. " GSB577  ,Group Status Bit 577" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 0. "  GSB576  ,Group Status Bit 576" "Group 0 (Secure),Group 1 (Non-secure)"
elif (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x12)
group.long 0x00C8++0x03
line.long 0x0 "GICD_IGROUPR18,Interrupt Group Register 18 (Non-secure access)"
bitfld.long 0x00 31. " GSB607  ,Group Status Bit 607" "Group 0,Group 1"
bitfld.long 0x00 30. "  GSB606  ,Group Status Bit 606" "Group 0,Group 1"
bitfld.long 0x00 29. "  GSB605  ,Group Status Bit 605" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB604  ,Group Status Bit 604" "Group 0,Group 1"
bitfld.long 0x00 27. "  GSB603  ,Group Status Bit 603" "Group 0,Group 1"
bitfld.long 0x00 26. "  GSB602  ,Group Status Bit 602" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB601  ,Group Status Bit 601" "Group 0,Group 1"
bitfld.long 0x00 24. "  GSB600  ,Group Status Bit 600" "Group 0,Group 1"
bitfld.long 0x00 23. "  GSB599  ,Group Status Bit 599" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB598  ,Group Status Bit 598" "Group 0,Group 1"
bitfld.long 0x00 21. "  GSB597  ,Group Status Bit 597" "Group 0,Group 1"
bitfld.long 0x00 20. "  GSB596  ,Group Status Bit 596" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB595  ,Group Status Bit 595" "Group 0,Group 1"
bitfld.long 0x00 18. "  GSB594  ,Group Status Bit 594" "Group 0,Group 1"
bitfld.long 0x00 17. "  GSB593  ,Group Status Bit 593" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB592  ,Group Status Bit 592" "Group 0,Group 1"
bitfld.long 0x00 15. "  GSB591  ,Group Status Bit 591" "Group 0,Group 1"
bitfld.long 0x00 14. "  GSB590  ,Group Status Bit 590" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB589  ,Group Status Bit 589" "Group 0,Group 1"
bitfld.long 0x00 12. "  GSB588  ,Group Status Bit 588" "Group 0,Group 1"
bitfld.long 0x00 11. "  GSB587  ,Group Status Bit 587" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB586  ,Group Status Bit 586" "Group 0,Group 1"
bitfld.long 0x00 9. "  GSB585  ,Group Status Bit 585" "Group 0,Group 1"
bitfld.long 0x00 8. "  GSB584  ,Group Status Bit 584" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB583  ,Group Status Bit 583" "Group 0,Group 1"
bitfld.long 0x00 6. "  GSB582  ,Group Status Bit 582" "Group 0,Group 1"
bitfld.long 0x00 5. "  GSB581  ,Group Status Bit 581" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB580  ,Group Status Bit 580" "Group 0,Group 1"
bitfld.long 0x00 3. "  GSB579  ,Group Status Bit 579" "Group 0,Group 1"
bitfld.long 0x00 2. "  GSB578  ,Group Status Bit 578" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB577  ,Group Status Bit 577" "Group 0,Group 1"
bitfld.long 0x00 0. "  GSB576  ,Group Status Bit 576" "Group 0,Group 1"
else
rgroup.long 0x00C8++0x03
line.long 0x0 "GICD_IGROUPR18,Interrupt Group Register 18"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x13)&&(PER.ADDRESS.isSECUREEX(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x00CC))
group.long 0x00CC++0x03
line.long 0x0 "GICD_IGROUPR19,Interrupt Group Register 19 (Secure access)"
bitfld.long 0x00 31. " GSB639  ,Group Status Bit 639" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 30. "  GSB638  ,Group Status Bit 638" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 29. "  GSB637  ,Group Status Bit 637" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 28. " GSB636  ,Group Status Bit 636" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 27. "  GSB635  ,Group Status Bit 635" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 26. "  GSB634  ,Group Status Bit 634" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 25. " GSB633  ,Group Status Bit 633" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 24. "  GSB632  ,Group Status Bit 632" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 23. "  GSB631  ,Group Status Bit 631" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 22. " GSB630  ,Group Status Bit 630" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 21. "  GSB629  ,Group Status Bit 629" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 20. "  GSB628  ,Group Status Bit 628" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 19. " GSB627  ,Group Status Bit 627" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 18. "  GSB626  ,Group Status Bit 626" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 17. "  GSB625  ,Group Status Bit 625" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 16. " GSB624  ,Group Status Bit 624" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 15. "  GSB623  ,Group Status Bit 623" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 14. "  GSB622  ,Group Status Bit 622" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 13. " GSB621  ,Group Status Bit 621" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 12. "  GSB620  ,Group Status Bit 620" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 11. "  GSB619  ,Group Status Bit 619" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 10. " GSB618  ,Group Status Bit 618" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 9. "  GSB617  ,Group Status Bit 617" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 8. "  GSB616  ,Group Status Bit 616" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 7. " GSB615  ,Group Status Bit 615" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 6. "  GSB614  ,Group Status Bit 614" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 5. "  GSB613  ,Group Status Bit 613" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 4. " GSB612  ,Group Status Bit 612" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 3. "  GSB611  ,Group Status Bit 611" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 2. "  GSB610  ,Group Status Bit 610" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 1. " GSB609  ,Group Status Bit 609" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 0. "  GSB608  ,Group Status Bit 608" "Group 0 (Secure),Group 1 (Non-secure)"
elif (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x13)
group.long 0x00CC++0x03
line.long 0x0 "GICD_IGROUPR19,Interrupt Group Register 19 (Non-secure access)"
bitfld.long 0x00 31. " GSB639  ,Group Status Bit 639" "Group 0,Group 1"
bitfld.long 0x00 30. "  GSB638  ,Group Status Bit 638" "Group 0,Group 1"
bitfld.long 0x00 29. "  GSB637  ,Group Status Bit 637" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB636  ,Group Status Bit 636" "Group 0,Group 1"
bitfld.long 0x00 27. "  GSB635  ,Group Status Bit 635" "Group 0,Group 1"
bitfld.long 0x00 26. "  GSB634  ,Group Status Bit 634" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB633  ,Group Status Bit 633" "Group 0,Group 1"
bitfld.long 0x00 24. "  GSB632  ,Group Status Bit 632" "Group 0,Group 1"
bitfld.long 0x00 23. "  GSB631  ,Group Status Bit 631" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB630  ,Group Status Bit 630" "Group 0,Group 1"
bitfld.long 0x00 21. "  GSB629  ,Group Status Bit 629" "Group 0,Group 1"
bitfld.long 0x00 20. "  GSB628  ,Group Status Bit 628" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB627  ,Group Status Bit 627" "Group 0,Group 1"
bitfld.long 0x00 18. "  GSB626  ,Group Status Bit 626" "Group 0,Group 1"
bitfld.long 0x00 17. "  GSB625  ,Group Status Bit 625" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB624  ,Group Status Bit 624" "Group 0,Group 1"
bitfld.long 0x00 15. "  GSB623  ,Group Status Bit 623" "Group 0,Group 1"
bitfld.long 0x00 14. "  GSB622  ,Group Status Bit 622" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB621  ,Group Status Bit 621" "Group 0,Group 1"
bitfld.long 0x00 12. "  GSB620  ,Group Status Bit 620" "Group 0,Group 1"
bitfld.long 0x00 11. "  GSB619  ,Group Status Bit 619" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB618  ,Group Status Bit 618" "Group 0,Group 1"
bitfld.long 0x00 9. "  GSB617  ,Group Status Bit 617" "Group 0,Group 1"
bitfld.long 0x00 8. "  GSB616  ,Group Status Bit 616" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB615  ,Group Status Bit 615" "Group 0,Group 1"
bitfld.long 0x00 6. "  GSB614  ,Group Status Bit 614" "Group 0,Group 1"
bitfld.long 0x00 5. "  GSB613  ,Group Status Bit 613" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB612  ,Group Status Bit 612" "Group 0,Group 1"
bitfld.long 0x00 3. "  GSB611  ,Group Status Bit 611" "Group 0,Group 1"
bitfld.long 0x00 2. "  GSB610  ,Group Status Bit 610" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB609  ,Group Status Bit 609" "Group 0,Group 1"
bitfld.long 0x00 0. "  GSB608  ,Group Status Bit 608" "Group 0,Group 1"
else
rgroup.long 0x00CC++0x03
line.long 0x0 "GICD_IGROUPR19,Interrupt Group Register 19"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x14)&&(PER.ADDRESS.isSECUREEX(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x00D0))
group.long 0x00D0++0x03
line.long 0x0 "GICD_IGROUPR20,Interrupt Group Register 20 (Secure access)"
bitfld.long 0x00 31. " GSB671  ,Group Status Bit 671" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 30. "  GSB670  ,Group Status Bit 670" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 29. "  GSB669  ,Group Status Bit 669" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 28. " GSB668  ,Group Status Bit 668" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 27. "  GSB667  ,Group Status Bit 667" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 26. "  GSB666  ,Group Status Bit 666" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 25. " GSB665  ,Group Status Bit 665" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 24. "  GSB664  ,Group Status Bit 664" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 23. "  GSB663  ,Group Status Bit 663" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 22. " GSB662  ,Group Status Bit 662" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 21. "  GSB661  ,Group Status Bit 661" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 20. "  GSB660  ,Group Status Bit 660" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 19. " GSB659  ,Group Status Bit 659" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 18. "  GSB658  ,Group Status Bit 658" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 17. "  GSB657  ,Group Status Bit 657" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 16. " GSB656  ,Group Status Bit 656" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 15. "  GSB655  ,Group Status Bit 655" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 14. "  GSB654  ,Group Status Bit 654" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 13. " GSB653  ,Group Status Bit 653" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 12. "  GSB652  ,Group Status Bit 652" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 11. "  GSB651  ,Group Status Bit 651" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 10. " GSB650  ,Group Status Bit 650" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 9. "  GSB649  ,Group Status Bit 649" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 8. "  GSB648  ,Group Status Bit 648" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 7. " GSB647  ,Group Status Bit 647" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 6. "  GSB646  ,Group Status Bit 646" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 5. "  GSB645  ,Group Status Bit 645" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 4. " GSB644  ,Group Status Bit 644" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 3. "  GSB643  ,Group Status Bit 643" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 2. "  GSB642  ,Group Status Bit 642" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 1. " GSB641  ,Group Status Bit 641" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 0. "  GSB640  ,Group Status Bit 640" "Group 0 (Secure),Group 1 (Non-secure)"
elif (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x14)
group.long 0x00D0++0x03
line.long 0x0 "GICD_IGROUPR20,Interrupt Group Register 20 (Non-secure access)"
bitfld.long 0x00 31. " GSB671  ,Group Status Bit 671" "Group 0,Group 1"
bitfld.long 0x00 30. "  GSB670  ,Group Status Bit 670" "Group 0,Group 1"
bitfld.long 0x00 29. "  GSB669  ,Group Status Bit 669" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB668  ,Group Status Bit 668" "Group 0,Group 1"
bitfld.long 0x00 27. "  GSB667  ,Group Status Bit 667" "Group 0,Group 1"
bitfld.long 0x00 26. "  GSB666  ,Group Status Bit 666" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB665  ,Group Status Bit 665" "Group 0,Group 1"
bitfld.long 0x00 24. "  GSB664  ,Group Status Bit 664" "Group 0,Group 1"
bitfld.long 0x00 23. "  GSB663  ,Group Status Bit 663" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB662  ,Group Status Bit 662" "Group 0,Group 1"
bitfld.long 0x00 21. "  GSB661  ,Group Status Bit 661" "Group 0,Group 1"
bitfld.long 0x00 20. "  GSB660  ,Group Status Bit 660" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB659  ,Group Status Bit 659" "Group 0,Group 1"
bitfld.long 0x00 18. "  GSB658  ,Group Status Bit 658" "Group 0,Group 1"
bitfld.long 0x00 17. "  GSB657  ,Group Status Bit 657" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB656  ,Group Status Bit 656" "Group 0,Group 1"
bitfld.long 0x00 15. "  GSB655  ,Group Status Bit 655" "Group 0,Group 1"
bitfld.long 0x00 14. "  GSB654  ,Group Status Bit 654" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB653  ,Group Status Bit 653" "Group 0,Group 1"
bitfld.long 0x00 12. "  GSB652  ,Group Status Bit 652" "Group 0,Group 1"
bitfld.long 0x00 11. "  GSB651  ,Group Status Bit 651" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB650  ,Group Status Bit 650" "Group 0,Group 1"
bitfld.long 0x00 9. "  GSB649  ,Group Status Bit 649" "Group 0,Group 1"
bitfld.long 0x00 8. "  GSB648  ,Group Status Bit 648" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB647  ,Group Status Bit 647" "Group 0,Group 1"
bitfld.long 0x00 6. "  GSB646  ,Group Status Bit 646" "Group 0,Group 1"
bitfld.long 0x00 5. "  GSB645  ,Group Status Bit 645" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB644  ,Group Status Bit 644" "Group 0,Group 1"
bitfld.long 0x00 3. "  GSB643  ,Group Status Bit 643" "Group 0,Group 1"
bitfld.long 0x00 2. "  GSB642  ,Group Status Bit 642" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB641  ,Group Status Bit 641" "Group 0,Group 1"
bitfld.long 0x00 0. "  GSB640  ,Group Status Bit 640" "Group 0,Group 1"
else
rgroup.long 0x00D0++0x03
line.long 0x0 "GICD_IGROUPR20,Interrupt Group Register 20"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x15)&&(PER.ADDRESS.isSECUREEX(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x00D4))
group.long 0x00D4++0x03
line.long 0x0 "GICD_IGROUPR21,Interrupt Group Register 21 (Secure access)"
bitfld.long 0x00 31. " GSB703  ,Group Status Bit 703" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 30. "  GSB702  ,Group Status Bit 702" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 29. "  GSB701  ,Group Status Bit 701" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 28. " GSB700  ,Group Status Bit 700" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 27. "  GSB699  ,Group Status Bit 699" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 26. "  GSB698  ,Group Status Bit 698" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 25. " GSB697  ,Group Status Bit 697" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 24. "  GSB696  ,Group Status Bit 696" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 23. "  GSB695  ,Group Status Bit 695" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 22. " GSB694  ,Group Status Bit 694" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 21. "  GSB693  ,Group Status Bit 693" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 20. "  GSB692  ,Group Status Bit 692" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 19. " GSB691  ,Group Status Bit 691" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 18. "  GSB690  ,Group Status Bit 690" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 17. "  GSB689  ,Group Status Bit 689" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 16. " GSB688  ,Group Status Bit 688" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 15. "  GSB687  ,Group Status Bit 687" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 14. "  GSB686  ,Group Status Bit 686" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 13. " GSB685  ,Group Status Bit 685" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 12. "  GSB684  ,Group Status Bit 684" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 11. "  GSB683  ,Group Status Bit 683" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 10. " GSB682  ,Group Status Bit 682" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 9. "  GSB681  ,Group Status Bit 681" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 8. "  GSB680  ,Group Status Bit 680" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 7. " GSB679  ,Group Status Bit 679" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 6. "  GSB678  ,Group Status Bit 678" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 5. "  GSB677  ,Group Status Bit 677" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 4. " GSB676  ,Group Status Bit 676" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 3. "  GSB675  ,Group Status Bit 675" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 2. "  GSB674  ,Group Status Bit 674" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 1. " GSB673  ,Group Status Bit 673" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 0. "  GSB672  ,Group Status Bit 672" "Group 0 (Secure),Group 1 (Non-secure)"
elif (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x15)
group.long 0x00D4++0x03
line.long 0x0 "GICD_IGROUPR21,Interrupt Group Register 21 (Non-secure access)"
bitfld.long 0x00 31. " GSB703  ,Group Status Bit 703" "Group 0,Group 1"
bitfld.long 0x00 30. "  GSB702  ,Group Status Bit 702" "Group 0,Group 1"
bitfld.long 0x00 29. "  GSB701  ,Group Status Bit 701" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB700  ,Group Status Bit 700" "Group 0,Group 1"
bitfld.long 0x00 27. "  GSB699  ,Group Status Bit 699" "Group 0,Group 1"
bitfld.long 0x00 26. "  GSB698  ,Group Status Bit 698" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB697  ,Group Status Bit 697" "Group 0,Group 1"
bitfld.long 0x00 24. "  GSB696  ,Group Status Bit 696" "Group 0,Group 1"
bitfld.long 0x00 23. "  GSB695  ,Group Status Bit 695" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB694  ,Group Status Bit 694" "Group 0,Group 1"
bitfld.long 0x00 21. "  GSB693  ,Group Status Bit 693" "Group 0,Group 1"
bitfld.long 0x00 20. "  GSB692  ,Group Status Bit 692" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB691  ,Group Status Bit 691" "Group 0,Group 1"
bitfld.long 0x00 18. "  GSB690  ,Group Status Bit 690" "Group 0,Group 1"
bitfld.long 0x00 17. "  GSB689  ,Group Status Bit 689" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB688  ,Group Status Bit 688" "Group 0,Group 1"
bitfld.long 0x00 15. "  GSB687  ,Group Status Bit 687" "Group 0,Group 1"
bitfld.long 0x00 14. "  GSB686  ,Group Status Bit 686" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB685  ,Group Status Bit 685" "Group 0,Group 1"
bitfld.long 0x00 12. "  GSB684  ,Group Status Bit 684" "Group 0,Group 1"
bitfld.long 0x00 11. "  GSB683  ,Group Status Bit 683" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB682  ,Group Status Bit 682" "Group 0,Group 1"
bitfld.long 0x00 9. "  GSB681  ,Group Status Bit 681" "Group 0,Group 1"
bitfld.long 0x00 8. "  GSB680  ,Group Status Bit 680" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB679  ,Group Status Bit 679" "Group 0,Group 1"
bitfld.long 0x00 6. "  GSB678  ,Group Status Bit 678" "Group 0,Group 1"
bitfld.long 0x00 5. "  GSB677  ,Group Status Bit 677" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB676  ,Group Status Bit 676" "Group 0,Group 1"
bitfld.long 0x00 3. "  GSB675  ,Group Status Bit 675" "Group 0,Group 1"
bitfld.long 0x00 2. "  GSB674  ,Group Status Bit 674" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB673  ,Group Status Bit 673" "Group 0,Group 1"
bitfld.long 0x00 0. "  GSB672  ,Group Status Bit 672" "Group 0,Group 1"
else
rgroup.long 0x00D4++0x03
line.long 0x0 "GICD_IGROUPR21,Interrupt Group Register 21"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x16)&&(PER.ADDRESS.isSECUREEX(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x00D8))
group.long 0x00D8++0x03
line.long 0x0 "GICD_IGROUPR22,Interrupt Group Register 22 (Secure access)"
bitfld.long 0x00 31. " GSB735  ,Group Status Bit 735" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 30. "  GSB734  ,Group Status Bit 734" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 29. "  GSB733  ,Group Status Bit 733" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 28. " GSB732  ,Group Status Bit 732" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 27. "  GSB731  ,Group Status Bit 731" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 26. "  GSB730  ,Group Status Bit 730" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 25. " GSB729  ,Group Status Bit 729" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 24. "  GSB728  ,Group Status Bit 728" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 23. "  GSB727  ,Group Status Bit 727" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 22. " GSB726  ,Group Status Bit 726" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 21. "  GSB725  ,Group Status Bit 725" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 20. "  GSB724  ,Group Status Bit 724" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 19. " GSB723  ,Group Status Bit 723" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 18. "  GSB722  ,Group Status Bit 722" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 17. "  GSB721  ,Group Status Bit 721" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 16. " GSB720  ,Group Status Bit 720" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 15. "  GSB719  ,Group Status Bit 719" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 14. "  GSB718  ,Group Status Bit 718" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 13. " GSB717  ,Group Status Bit 717" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 12. "  GSB716  ,Group Status Bit 716" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 11. "  GSB715  ,Group Status Bit 715" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 10. " GSB714  ,Group Status Bit 714" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 9. "  GSB713  ,Group Status Bit 713" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 8. "  GSB712  ,Group Status Bit 712" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 7. " GSB711  ,Group Status Bit 711" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 6. "  GSB710  ,Group Status Bit 710" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 5. "  GSB709  ,Group Status Bit 709" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 4. " GSB708  ,Group Status Bit 708" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 3. "  GSB707  ,Group Status Bit 707" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 2. "  GSB706  ,Group Status Bit 706" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 1. " GSB705  ,Group Status Bit 705" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 0. "  GSB704  ,Group Status Bit 704" "Group 0 (Secure),Group 1 (Non-secure)"
elif (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x16)
group.long 0x00D8++0x03
line.long 0x0 "GICD_IGROUPR22,Interrupt Group Register 22 (Non-secure access)"
bitfld.long 0x00 31. " GSB735  ,Group Status Bit 735" "Group 0,Group 1"
bitfld.long 0x00 30. "  GSB734  ,Group Status Bit 734" "Group 0,Group 1"
bitfld.long 0x00 29. "  GSB733  ,Group Status Bit 733" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB732  ,Group Status Bit 732" "Group 0,Group 1"
bitfld.long 0x00 27. "  GSB731  ,Group Status Bit 731" "Group 0,Group 1"
bitfld.long 0x00 26. "  GSB730  ,Group Status Bit 730" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB729  ,Group Status Bit 729" "Group 0,Group 1"
bitfld.long 0x00 24. "  GSB728  ,Group Status Bit 728" "Group 0,Group 1"
bitfld.long 0x00 23. "  GSB727  ,Group Status Bit 727" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB726  ,Group Status Bit 726" "Group 0,Group 1"
bitfld.long 0x00 21. "  GSB725  ,Group Status Bit 725" "Group 0,Group 1"
bitfld.long 0x00 20. "  GSB724  ,Group Status Bit 724" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB723  ,Group Status Bit 723" "Group 0,Group 1"
bitfld.long 0x00 18. "  GSB722  ,Group Status Bit 722" "Group 0,Group 1"
bitfld.long 0x00 17. "  GSB721  ,Group Status Bit 721" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB720  ,Group Status Bit 720" "Group 0,Group 1"
bitfld.long 0x00 15. "  GSB719  ,Group Status Bit 719" "Group 0,Group 1"
bitfld.long 0x00 14. "  GSB718  ,Group Status Bit 718" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB717  ,Group Status Bit 717" "Group 0,Group 1"
bitfld.long 0x00 12. "  GSB716  ,Group Status Bit 716" "Group 0,Group 1"
bitfld.long 0x00 11. "  GSB715  ,Group Status Bit 715" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB714  ,Group Status Bit 714" "Group 0,Group 1"
bitfld.long 0x00 9. "  GSB713  ,Group Status Bit 713" "Group 0,Group 1"
bitfld.long 0x00 8. "  GSB712  ,Group Status Bit 712" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB711  ,Group Status Bit 711" "Group 0,Group 1"
bitfld.long 0x00 6. "  GSB710  ,Group Status Bit 710" "Group 0,Group 1"
bitfld.long 0x00 5. "  GSB709  ,Group Status Bit 709" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB708  ,Group Status Bit 708" "Group 0,Group 1"
bitfld.long 0x00 3. "  GSB707  ,Group Status Bit 707" "Group 0,Group 1"
bitfld.long 0x00 2. "  GSB706  ,Group Status Bit 706" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB705  ,Group Status Bit 705" "Group 0,Group 1"
bitfld.long 0x00 0. "  GSB704  ,Group Status Bit 704" "Group 0,Group 1"
else
rgroup.long 0x00D8++0x03
line.long 0x0 "GICD_IGROUPR22,Interrupt Group Register 22"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x17)&&(PER.ADDRESS.isSECUREEX(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x00DC))
group.long 0x00DC++0x03
line.long 0x0 "GICD_IGROUPR23,Interrupt Group Register 23 (Secure access)"
bitfld.long 0x00 31. " GSB767  ,Group Status Bit 767" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 30. "  GSB766  ,Group Status Bit 766" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 29. "  GSB765  ,Group Status Bit 765" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 28. " GSB764  ,Group Status Bit 764" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 27. "  GSB763  ,Group Status Bit 763" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 26. "  GSB762  ,Group Status Bit 762" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 25. " GSB761  ,Group Status Bit 761" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 24. "  GSB760  ,Group Status Bit 760" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 23. "  GSB759  ,Group Status Bit 759" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 22. " GSB758  ,Group Status Bit 758" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 21. "  GSB757  ,Group Status Bit 757" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 20. "  GSB756  ,Group Status Bit 756" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 19. " GSB755  ,Group Status Bit 755" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 18. "  GSB754  ,Group Status Bit 754" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 17. "  GSB753  ,Group Status Bit 753" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 16. " GSB752  ,Group Status Bit 752" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 15. "  GSB751  ,Group Status Bit 751" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 14. "  GSB750  ,Group Status Bit 750" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 13. " GSB749  ,Group Status Bit 749" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 12. "  GSB748  ,Group Status Bit 748" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 11. "  GSB747  ,Group Status Bit 747" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 10. " GSB746  ,Group Status Bit 746" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 9. "  GSB745  ,Group Status Bit 745" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 8. "  GSB744  ,Group Status Bit 744" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 7. " GSB743  ,Group Status Bit 743" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 6. "  GSB742  ,Group Status Bit 742" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 5. "  GSB741  ,Group Status Bit 741" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 4. " GSB740  ,Group Status Bit 740" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 3. "  GSB739  ,Group Status Bit 739" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 2. "  GSB738  ,Group Status Bit 738" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 1. " GSB737  ,Group Status Bit 737" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 0. "  GSB736  ,Group Status Bit 736" "Group 0 (Secure),Group 1 (Non-secure)"
elif (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x17)
group.long 0x00DC++0x03
line.long 0x0 "GICD_IGROUPR23,Interrupt Group Register 23 (Non-secure access)"
bitfld.long 0x00 31. " GSB767  ,Group Status Bit 767" "Group 0,Group 1"
bitfld.long 0x00 30. "  GSB766  ,Group Status Bit 766" "Group 0,Group 1"
bitfld.long 0x00 29. "  GSB765  ,Group Status Bit 765" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB764  ,Group Status Bit 764" "Group 0,Group 1"
bitfld.long 0x00 27. "  GSB763  ,Group Status Bit 763" "Group 0,Group 1"
bitfld.long 0x00 26. "  GSB762  ,Group Status Bit 762" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB761  ,Group Status Bit 761" "Group 0,Group 1"
bitfld.long 0x00 24. "  GSB760  ,Group Status Bit 760" "Group 0,Group 1"
bitfld.long 0x00 23. "  GSB759  ,Group Status Bit 759" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB758  ,Group Status Bit 758" "Group 0,Group 1"
bitfld.long 0x00 21. "  GSB757  ,Group Status Bit 757" "Group 0,Group 1"
bitfld.long 0x00 20. "  GSB756  ,Group Status Bit 756" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB755  ,Group Status Bit 755" "Group 0,Group 1"
bitfld.long 0x00 18. "  GSB754  ,Group Status Bit 754" "Group 0,Group 1"
bitfld.long 0x00 17. "  GSB753  ,Group Status Bit 753" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB752  ,Group Status Bit 752" "Group 0,Group 1"
bitfld.long 0x00 15. "  GSB751  ,Group Status Bit 751" "Group 0,Group 1"
bitfld.long 0x00 14. "  GSB750  ,Group Status Bit 750" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB749  ,Group Status Bit 749" "Group 0,Group 1"
bitfld.long 0x00 12. "  GSB748  ,Group Status Bit 748" "Group 0,Group 1"
bitfld.long 0x00 11. "  GSB747  ,Group Status Bit 747" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB746  ,Group Status Bit 746" "Group 0,Group 1"
bitfld.long 0x00 9. "  GSB745  ,Group Status Bit 745" "Group 0,Group 1"
bitfld.long 0x00 8. "  GSB744  ,Group Status Bit 744" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB743  ,Group Status Bit 743" "Group 0,Group 1"
bitfld.long 0x00 6. "  GSB742  ,Group Status Bit 742" "Group 0,Group 1"
bitfld.long 0x00 5. "  GSB741  ,Group Status Bit 741" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB740  ,Group Status Bit 740" "Group 0,Group 1"
bitfld.long 0x00 3. "  GSB739  ,Group Status Bit 739" "Group 0,Group 1"
bitfld.long 0x00 2. "  GSB738  ,Group Status Bit 738" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB737  ,Group Status Bit 737" "Group 0,Group 1"
bitfld.long 0x00 0. "  GSB736  ,Group Status Bit 736" "Group 0,Group 1"
else
rgroup.long 0x00DC++0x03
line.long 0x0 "GICD_IGROUPR23,Interrupt Group Register 23"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x18)&&(PER.ADDRESS.isSECUREEX(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x00E0))
group.long 0x00E0++0x03
line.long 0x0 "GICD_IGROUPR24,Interrupt Group Register 24 (Secure access)"
bitfld.long 0x00 31. " GSB799  ,Group Status Bit 799" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 30. "  GSB798  ,Group Status Bit 798" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 29. "  GSB797  ,Group Status Bit 797" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 28. " GSB796  ,Group Status Bit 796" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 27. "  GSB795  ,Group Status Bit 795" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 26. "  GSB794  ,Group Status Bit 794" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 25. " GSB793  ,Group Status Bit 793" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 24. "  GSB792  ,Group Status Bit 792" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 23. "  GSB791  ,Group Status Bit 791" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 22. " GSB790  ,Group Status Bit 790" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 21. "  GSB789  ,Group Status Bit 789" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 20. "  GSB788  ,Group Status Bit 788" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 19. " GSB787  ,Group Status Bit 787" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 18. "  GSB786  ,Group Status Bit 786" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 17. "  GSB785  ,Group Status Bit 785" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 16. " GSB784  ,Group Status Bit 784" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 15. "  GSB783  ,Group Status Bit 783" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 14. "  GSB782  ,Group Status Bit 782" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 13. " GSB781  ,Group Status Bit 781" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 12. "  GSB780  ,Group Status Bit 780" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 11. "  GSB779  ,Group Status Bit 779" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 10. " GSB778  ,Group Status Bit 778" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 9. "  GSB777  ,Group Status Bit 777" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 8. "  GSB776  ,Group Status Bit 776" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 7. " GSB775  ,Group Status Bit 775" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 6. "  GSB774  ,Group Status Bit 774" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 5. "  GSB773  ,Group Status Bit 773" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 4. " GSB772  ,Group Status Bit 772" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 3. "  GSB771  ,Group Status Bit 771" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 2. "  GSB770  ,Group Status Bit 770" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 1. " GSB769  ,Group Status Bit 769" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 0. "  GSB768  ,Group Status Bit 768" "Group 0 (Secure),Group 1 (Non-secure)"
elif (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x18)
group.long 0x00E0++0x03
line.long 0x0 "GICD_IGROUPR24,Interrupt Group Register 24 (Non-secure access)"
bitfld.long 0x00 31. " GSB799  ,Group Status Bit 799" "Group 0,Group 1"
bitfld.long 0x00 30. "  GSB798  ,Group Status Bit 798" "Group 0,Group 1"
bitfld.long 0x00 29. "  GSB797  ,Group Status Bit 797" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB796  ,Group Status Bit 796" "Group 0,Group 1"
bitfld.long 0x00 27. "  GSB795  ,Group Status Bit 795" "Group 0,Group 1"
bitfld.long 0x00 26. "  GSB794  ,Group Status Bit 794" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB793  ,Group Status Bit 793" "Group 0,Group 1"
bitfld.long 0x00 24. "  GSB792  ,Group Status Bit 792" "Group 0,Group 1"
bitfld.long 0x00 23. "  GSB791  ,Group Status Bit 791" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB790  ,Group Status Bit 790" "Group 0,Group 1"
bitfld.long 0x00 21. "  GSB789  ,Group Status Bit 789" "Group 0,Group 1"
bitfld.long 0x00 20. "  GSB788  ,Group Status Bit 788" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB787  ,Group Status Bit 787" "Group 0,Group 1"
bitfld.long 0x00 18. "  GSB786  ,Group Status Bit 786" "Group 0,Group 1"
bitfld.long 0x00 17. "  GSB785  ,Group Status Bit 785" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB784  ,Group Status Bit 784" "Group 0,Group 1"
bitfld.long 0x00 15. "  GSB783  ,Group Status Bit 783" "Group 0,Group 1"
bitfld.long 0x00 14. "  GSB782  ,Group Status Bit 782" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB781  ,Group Status Bit 781" "Group 0,Group 1"
bitfld.long 0x00 12. "  GSB780  ,Group Status Bit 780" "Group 0,Group 1"
bitfld.long 0x00 11. "  GSB779  ,Group Status Bit 779" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB778  ,Group Status Bit 778" "Group 0,Group 1"
bitfld.long 0x00 9. "  GSB777  ,Group Status Bit 777" "Group 0,Group 1"
bitfld.long 0x00 8. "  GSB776  ,Group Status Bit 776" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB775  ,Group Status Bit 775" "Group 0,Group 1"
bitfld.long 0x00 6. "  GSB774  ,Group Status Bit 774" "Group 0,Group 1"
bitfld.long 0x00 5. "  GSB773  ,Group Status Bit 773" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB772  ,Group Status Bit 772" "Group 0,Group 1"
bitfld.long 0x00 3. "  GSB771  ,Group Status Bit 771" "Group 0,Group 1"
bitfld.long 0x00 2. "  GSB770  ,Group Status Bit 770" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB769  ,Group Status Bit 769" "Group 0,Group 1"
bitfld.long 0x00 0. "  GSB768  ,Group Status Bit 768" "Group 0,Group 1"
else
rgroup.long 0x0E0++0x03
line.long 0x0 "GICD_IGROUPR24,Interrupt Group Register 24"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x19)&&(PER.ADDRESS.isSECUREEX(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x00E4))
group.long 0x00E4++0x03
line.long 0x0 "GICD_IGROUPR25,Interrupt Group Register 25 (Secure access)"
bitfld.long 0x00 31. " GSB831  ,Group Status Bit 831" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 30. "  GSB830  ,Group Status Bit 830" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 29. "  GSB829  ,Group Status Bit 829" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 28. " GSB828  ,Group Status Bit 828" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 27. "  GSB827  ,Group Status Bit 827" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 26. "  GSB826  ,Group Status Bit 826" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 25. " GSB825  ,Group Status Bit 825" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 24. "  GSB824  ,Group Status Bit 824" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 23. "  GSB823  ,Group Status Bit 823" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 22. " GSB822  ,Group Status Bit 822" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 21. "  GSB821  ,Group Status Bit 821" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 20. "  GSB820  ,Group Status Bit 820" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 19. " GSB819  ,Group Status Bit 819" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 18. "  GSB818  ,Group Status Bit 818" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 17. "  GSB817  ,Group Status Bit 817" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 16. " GSB816  ,Group Status Bit 816" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 15. "  GSB815  ,Group Status Bit 815" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 14. "  GSB814  ,Group Status Bit 814" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 13. " GSB813  ,Group Status Bit 813" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 12. "  GSB812  ,Group Status Bit 812" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 11. "  GSB811  ,Group Status Bit 811" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 10. " GSB810  ,Group Status Bit 810" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 9. "  GSB809  ,Group Status Bit 809" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 8. "  GSB808  ,Group Status Bit 808" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 7. " GSB807  ,Group Status Bit 807" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 6. "  GSB806  ,Group Status Bit 806" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 5. "  GSB805  ,Group Status Bit 805" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 4. " GSB804  ,Group Status Bit 804" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 3. "  GSB803  ,Group Status Bit 803" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 2. "  GSB802  ,Group Status Bit 802" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 1. " GSB801  ,Group Status Bit 801" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 0. "  GSB800  ,Group Status Bit 800" "Group 0 (Secure),Group 1 (Non-secure)"
elif (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x19)
group.long 0x00E4++0x03
line.long 0x0 "GICD_IGROUPR25,Interrupt Group Register 25 (Non-secure access)"
bitfld.long 0x00 31. " GSB831  ,Group Status Bit 831" "Group 0,Group 1"
bitfld.long 0x00 30. "  GSB830  ,Group Status Bit 830" "Group 0,Group 1"
bitfld.long 0x00 29. "  GSB829  ,Group Status Bit 829" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB828  ,Group Status Bit 828" "Group 0,Group 1"
bitfld.long 0x00 27. "  GSB827  ,Group Status Bit 827" "Group 0,Group 1"
bitfld.long 0x00 26. "  GSB826  ,Group Status Bit 826" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB825  ,Group Status Bit 825" "Group 0,Group 1"
bitfld.long 0x00 24. "  GSB824  ,Group Status Bit 824" "Group 0,Group 1"
bitfld.long 0x00 23. "  GSB823  ,Group Status Bit 823" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB822  ,Group Status Bit 822" "Group 0,Group 1"
bitfld.long 0x00 21. "  GSB821  ,Group Status Bit 821" "Group 0,Group 1"
bitfld.long 0x00 20. "  GSB820  ,Group Status Bit 820" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB819  ,Group Status Bit 819" "Group 0,Group 1"
bitfld.long 0x00 18. "  GSB818  ,Group Status Bit 818" "Group 0,Group 1"
bitfld.long 0x00 17. "  GSB817  ,Group Status Bit 817" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB816  ,Group Status Bit 816" "Group 0,Group 1"
bitfld.long 0x00 15. "  GSB815  ,Group Status Bit 815" "Group 0,Group 1"
bitfld.long 0x00 14. "  GSB814  ,Group Status Bit 814" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB813  ,Group Status Bit 813" "Group 0,Group 1"
bitfld.long 0x00 12. "  GSB812  ,Group Status Bit 812" "Group 0,Group 1"
bitfld.long 0x00 11. "  GSB811  ,Group Status Bit 811" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB810  ,Group Status Bit 810" "Group 0,Group 1"
bitfld.long 0x00 9. "  GSB809  ,Group Status Bit 809" "Group 0,Group 1"
bitfld.long 0x00 8. "  GSB808  ,Group Status Bit 808" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB807  ,Group Status Bit 807" "Group 0,Group 1"
bitfld.long 0x00 6. "  GSB806  ,Group Status Bit 806" "Group 0,Group 1"
bitfld.long 0x00 5. "  GSB805  ,Group Status Bit 805" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB804  ,Group Status Bit 804" "Group 0,Group 1"
bitfld.long 0x00 3. "  GSB803  ,Group Status Bit 803" "Group 0,Group 1"
bitfld.long 0x00 2. "  GSB802  ,Group Status Bit 802" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB801  ,Group Status Bit 801" "Group 0,Group 1"
bitfld.long 0x00 0. "  GSB800  ,Group Status Bit 800" "Group 0,Group 1"
else
rgroup.long 0x00E4++0x03
line.long 0x0 "GICD_IGROUPR25,Interrupt Group Register 25"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1A)&&(PER.ADDRESS.isSECUREEX(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x00E8))
group.long 0x00E8++0x03
line.long 0x0 "GICD_IGROUPR26,Interrupt Group Register 26 (Secure access)"
bitfld.long 0x00 31. " GSB863  ,Group Status Bit 863" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 30. "  GSB862  ,Group Status Bit 862" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 29. "  GSB861  ,Group Status Bit 861" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 28. " GSB860  ,Group Status Bit 860" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 27. "  GSB859  ,Group Status Bit 859" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 26. "  GSB858  ,Group Status Bit 858" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 25. " GSB857  ,Group Status Bit 857" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 24. "  GSB856  ,Group Status Bit 856" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 23. "  GSB855  ,Group Status Bit 855" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 22. " GSB854  ,Group Status Bit 854" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 21. "  GSB853  ,Group Status Bit 853" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 20. "  GSB852  ,Group Status Bit 852" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 19. " GSB851  ,Group Status Bit 851" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 18. "  GSB850  ,Group Status Bit 850" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 17. "  GSB849  ,Group Status Bit 849" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 16. " GSB848  ,Group Status Bit 848" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 15. "  GSB847  ,Group Status Bit 847" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 14. "  GSB846  ,Group Status Bit 846" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 13. " GSB845  ,Group Status Bit 845" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 12. "  GSB844  ,Group Status Bit 844" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 11. "  GSB843  ,Group Status Bit 843" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 10. " GSB842  ,Group Status Bit 842" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 9. "  GSB841  ,Group Status Bit 841" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 8. "  GSB840  ,Group Status Bit 840" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 7. " GSB839  ,Group Status Bit 839" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 6. "  GSB838  ,Group Status Bit 838" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 5. "  GSB837  ,Group Status Bit 837" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 4. " GSB836  ,Group Status Bit 836" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 3. "  GSB835  ,Group Status Bit 835" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 2. "  GSB834  ,Group Status Bit 834" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 1. " GSB833  ,Group Status Bit 833" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 0. "  GSB832  ,Group Status Bit 832" "Group 0 (Secure),Group 1 (Non-secure)"
elif (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1A)
group.long 0x00E8++0x03
line.long 0x0 "GICD_IGROUPR26,Interrupt Group Register 26 (Non-secure access)"
bitfld.long 0x00 31. " GSB863  ,Group Status Bit 863" "Group 0,Group 1"
bitfld.long 0x00 30. "  GSB862  ,Group Status Bit 862" "Group 0,Group 1"
bitfld.long 0x00 29. "  GSB861  ,Group Status Bit 861" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB860  ,Group Status Bit 860" "Group 0,Group 1"
bitfld.long 0x00 27. "  GSB859  ,Group Status Bit 859" "Group 0,Group 1"
bitfld.long 0x00 26. "  GSB858  ,Group Status Bit 858" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB857  ,Group Status Bit 857" "Group 0,Group 1"
bitfld.long 0x00 24. "  GSB856  ,Group Status Bit 856" "Group 0,Group 1"
bitfld.long 0x00 23. "  GSB855  ,Group Status Bit 855" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB854  ,Group Status Bit 854" "Group 0,Group 1"
bitfld.long 0x00 21. "  GSB853  ,Group Status Bit 853" "Group 0,Group 1"
bitfld.long 0x00 20. "  GSB852  ,Group Status Bit 852" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB851  ,Group Status Bit 851" "Group 0,Group 1"
bitfld.long 0x00 18. "  GSB850  ,Group Status Bit 850" "Group 0,Group 1"
bitfld.long 0x00 17. "  GSB849  ,Group Status Bit 849" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB848  ,Group Status Bit 848" "Group 0,Group 1"
bitfld.long 0x00 15. "  GSB847  ,Group Status Bit 847" "Group 0,Group 1"
bitfld.long 0x00 14. "  GSB846  ,Group Status Bit 846" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB845  ,Group Status Bit 845" "Group 0,Group 1"
bitfld.long 0x00 12. "  GSB844  ,Group Status Bit 844" "Group 0,Group 1"
bitfld.long 0x00 11. "  GSB843  ,Group Status Bit 843" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB842  ,Group Status Bit 842" "Group 0,Group 1"
bitfld.long 0x00 9. "  GSB841  ,Group Status Bit 841" "Group 0,Group 1"
bitfld.long 0x00 8. "  GSB840  ,Group Status Bit 840" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB839  ,Group Status Bit 839" "Group 0,Group 1"
bitfld.long 0x00 6. "  GSB838  ,Group Status Bit 838" "Group 0,Group 1"
bitfld.long 0x00 5. "  GSB837  ,Group Status Bit 837" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB836  ,Group Status Bit 836" "Group 0,Group 1"
bitfld.long 0x00 3. "  GSB835  ,Group Status Bit 835" "Group 0,Group 1"
bitfld.long 0x00 2. "  GSB834  ,Group Status Bit 834" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB833  ,Group Status Bit 833" "Group 0,Group 1"
bitfld.long 0x00 0. "  GSB832  ,Group Status Bit 832" "Group 0,Group 1"
else
rgroup.long 0x00E8++0x03
line.long 0x0 "GICD_IGROUPR26,Interrupt Group Register 26"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1B)&&(PER.ADDRESS.isSECUREEX(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x00EC))
group.long 0x00EC++0x03
line.long 0x0 "GICD_IGROUPR27,Interrupt Group Register 27 (Secure access)"
bitfld.long 0x00 31. " GSB895  ,Group Status Bit 895" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 30. "  GSB894  ,Group Status Bit 894" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 29. "  GSB893  ,Group Status Bit 893" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 28. " GSB892  ,Group Status Bit 892" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 27. "  GSB891  ,Group Status Bit 891" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 26. "  GSB890  ,Group Status Bit 890" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 25. " GSB889  ,Group Status Bit 889" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 24. "  GSB888  ,Group Status Bit 888" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 23. "  GSB887  ,Group Status Bit 887" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 22. " GSB886  ,Group Status Bit 886" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 21. "  GSB885  ,Group Status Bit 885" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 20. "  GSB884  ,Group Status Bit 884" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 19. " GSB883  ,Group Status Bit 883" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 18. "  GSB882  ,Group Status Bit 882" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 17. "  GSB881  ,Group Status Bit 881" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 16. " GSB880  ,Group Status Bit 880" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 15. "  GSB879  ,Group Status Bit 879" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 14. "  GSB878  ,Group Status Bit 878" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 13. " GSB877  ,Group Status Bit 877" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 12. "  GSB876  ,Group Status Bit 876" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 11. "  GSB875  ,Group Status Bit 875" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 10. " GSB874  ,Group Status Bit 874" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 9. "  GSB873  ,Group Status Bit 873" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 8. "  GSB872  ,Group Status Bit 872" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 7. " GSB871  ,Group Status Bit 871" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 6. "  GSB870  ,Group Status Bit 870" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 5. "  GSB869  ,Group Status Bit 869" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 4. " GSB868  ,Group Status Bit 868" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 3. "  GSB867  ,Group Status Bit 867" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 2. "  GSB866  ,Group Status Bit 866" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 1. " GSB865  ,Group Status Bit 865" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 0. "  GSB864  ,Group Status Bit 864" "Group 0 (Secure),Group 1 (Non-secure)"
elif (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1B)
group.long 0x00EC++0x03
line.long 0x0 "GICD_IGROUPR27,Interrupt Group Register 27 (Non-Secure access)"
bitfld.long 0x00 31. " GSB895  ,Group Status Bit 895" "Group 0,Group 1"
bitfld.long 0x00 30. "  GSB894  ,Group Status Bit 894" "Group 0,Group 1"
bitfld.long 0x00 29. "  GSB893  ,Group Status Bit 893" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB892  ,Group Status Bit 892" "Group 0,Group 1"
bitfld.long 0x00 27. "  GSB891  ,Group Status Bit 891" "Group 0,Group 1"
bitfld.long 0x00 26. "  GSB890  ,Group Status Bit 890" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB889  ,Group Status Bit 889" "Group 0,Group 1"
bitfld.long 0x00 24. "  GSB888  ,Group Status Bit 888" "Group 0,Group 1"
bitfld.long 0x00 23. "  GSB887  ,Group Status Bit 887" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB886  ,Group Status Bit 886" "Group 0,Group 1"
bitfld.long 0x00 21. "  GSB885  ,Group Status Bit 885" "Group 0,Group 1"
bitfld.long 0x00 20. "  GSB884  ,Group Status Bit 884" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB883  ,Group Status Bit 883" "Group 0,Group 1"
bitfld.long 0x00 18. "  GSB882  ,Group Status Bit 882" "Group 0,Group 1"
bitfld.long 0x00 17. "  GSB881  ,Group Status Bit 881" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB880  ,Group Status Bit 880" "Group 0,Group 1"
bitfld.long 0x00 15. "  GSB879  ,Group Status Bit 879" "Group 0,Group 1"
bitfld.long 0x00 14. "  GSB878  ,Group Status Bit 878" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB877  ,Group Status Bit 877" "Group 0,Group 1"
bitfld.long 0x00 12. "  GSB876  ,Group Status Bit 876" "Group 0,Group 1"
bitfld.long 0x00 11. "  GSB875  ,Group Status Bit 875" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB874  ,Group Status Bit 874" "Group 0,Group 1"
bitfld.long 0x00 9. "  GSB873  ,Group Status Bit 873" "Group 0,Group 1"
bitfld.long 0x00 8. "  GSB872  ,Group Status Bit 872" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB871  ,Group Status Bit 871" "Group 0,Group 1"
bitfld.long 0x00 6. "  GSB870  ,Group Status Bit 870" "Group 0,Group 1"
bitfld.long 0x00 5. "  GSB869  ,Group Status Bit 869" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB868  ,Group Status Bit 868" "Group 0,Group 1"
bitfld.long 0x00 3. "  GSB867  ,Group Status Bit 867" "Group 0,Group 1"
bitfld.long 0x00 2. "  GSB866  ,Group Status Bit 866" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB865  ,Group Status Bit 865" "Group 0,Group 1"
bitfld.long 0x00 0. "  GSB864  ,Group Status Bit 864" "Group 0,Group 1"
else
rgroup.long 0x00EC++0x03
line.long 0x0 "GICD_IGROUPR27,Interrupt Group Register 27"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1C)&&(PER.ADDRESS.isSECUREEX(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x00F0))
group.long 0x00F0++0x03
line.long 0x0 "GICD_IGROUPR28,Interrupt Group Register 28 (Secure access)"
bitfld.long 0x00 31. " GSB927  ,Group Status Bit 927" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 30. "  GSB926  ,Group Status Bit 926" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 29. "  GSB925  ,Group Status Bit 925" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 28. " GSB924  ,Group Status Bit 924" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 27. "  GSB923  ,Group Status Bit 923" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 26. "  GSB922  ,Group Status Bit 922" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 25. " GSB921  ,Group Status Bit 921" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 24. "  GSB920  ,Group Status Bit 920" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 23. "  GSB919  ,Group Status Bit 919" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 22. " GSB918  ,Group Status Bit 918" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 21. "  GSB917  ,Group Status Bit 917" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 20. "  GSB916  ,Group Status Bit 916" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 19. " GSB915  ,Group Status Bit 915" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 18. "  GSB914  ,Group Status Bit 914" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 17. "  GSB913  ,Group Status Bit 913" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 16. " GSB912  ,Group Status Bit 912" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 15. "  GSB911  ,Group Status Bit 911" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 14. "  GSB910  ,Group Status Bit 910" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 13. " GSB909  ,Group Status Bit 909" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 12. "  GSB908  ,Group Status Bit 908" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 11. "  GSB907  ,Group Status Bit 907" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 10. " GSB906  ,Group Status Bit 906" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 9. "  GSB905  ,Group Status Bit 905" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 8. "  GSB904  ,Group Status Bit 904" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 7. " GSB903  ,Group Status Bit 903" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 6. "  GSB902  ,Group Status Bit 902" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 5. "  GSB901  ,Group Status Bit 901" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 4. " GSB900  ,Group Status Bit 900" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 3. "  GSB899  ,Group Status Bit 899" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 2. "  GSB898  ,Group Status Bit 898" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 1. " GSB897  ,Group Status Bit 897" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 0. "  GSB896  ,Group Status Bit 896" "Group 0 (Secure),Group 1 (Non-secure)"
elif (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1C)
group.long 0x00F0++0x03
line.long 0x0 "GICD_IGROUPR28,Interrupt Group Register 28 (Non-secure access)"
bitfld.long 0x00 31. " GSB927  ,Group Status Bit 927" "Group 0,Group 1"
bitfld.long 0x00 30. "  GSB926  ,Group Status Bit 926" "Group 0,Group 1"
bitfld.long 0x00 29. "  GSB925  ,Group Status Bit 925" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB924  ,Group Status Bit 924" "Group 0,Group 1"
bitfld.long 0x00 27. "  GSB923  ,Group Status Bit 923" "Group 0,Group 1"
bitfld.long 0x00 26. "  GSB922  ,Group Status Bit 922" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB921  ,Group Status Bit 921" "Group 0,Group 1"
bitfld.long 0x00 24. "  GSB920  ,Group Status Bit 920" "Group 0,Group 1"
bitfld.long 0x00 23. "  GSB919  ,Group Status Bit 919" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB918  ,Group Status Bit 918" "Group 0,Group 1"
bitfld.long 0x00 21. "  GSB917  ,Group Status Bit 917" "Group 0,Group 1"
bitfld.long 0x00 20. "  GSB916  ,Group Status Bit 916" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB915  ,Group Status Bit 915" "Group 0,Group 1"
bitfld.long 0x00 18. "  GSB914  ,Group Status Bit 914" "Group 0,Group 1"
bitfld.long 0x00 17. "  GSB913  ,Group Status Bit 913" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB912  ,Group Status Bit 912" "Group 0,Group 1"
bitfld.long 0x00 15. "  GSB911  ,Group Status Bit 911" "Group 0,Group 1"
bitfld.long 0x00 14. "  GSB910  ,Group Status Bit 910" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB909  ,Group Status Bit 909" "Group 0,Group 1"
bitfld.long 0x00 12. "  GSB908  ,Group Status Bit 908" "Group 0,Group 1"
bitfld.long 0x00 11. "  GSB907  ,Group Status Bit 907" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB906  ,Group Status Bit 906" "Group 0,Group 1"
bitfld.long 0x00 9. "  GSB905  ,Group Status Bit 905" "Group 0,Group 1"
bitfld.long 0x00 8. "  GSB904  ,Group Status Bit 904" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB903  ,Group Status Bit 903" "Group 0,Group 1"
bitfld.long 0x00 6. "  GSB902  ,Group Status Bit 902" "Group 0,Group 1"
bitfld.long 0x00 5. "  GSB901  ,Group Status Bit 901" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB900  ,Group Status Bit 900" "Group 0,Group 1"
bitfld.long 0x00 3. "  GSB899  ,Group Status Bit 899" "Group 0,Group 1"
bitfld.long 0x00 2. "  GSB898  ,Group Status Bit 898" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB897  ,Group Status Bit 897" "Group 0,Group 1"
bitfld.long 0x00 0. "  GSB896  ,Group Status Bit 896" "Group 0,Group 1"
else
rgroup.long 0x0F0++0x03
line.long 0x0 "GICD_IGROUPR28,Interrupt Group Register 28"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1D)&&(PER.ADDRESS.isSECUREEX(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x00F4))
group.long 0x00F4++0x03
line.long 0x0 "GICD_IGROUPR29,Interrupt Group Register 29 (Secure access)"
bitfld.long 0x00 31. " GSB959  ,Group Status Bit 959" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 30. "  GSB958  ,Group Status Bit 958" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 29. "  GSB957  ,Group Status Bit 957" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 28. " GSB956  ,Group Status Bit 956" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 27. "  GSB955  ,Group Status Bit 955" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 26. "  GSB954  ,Group Status Bit 954" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 25. " GSB953  ,Group Status Bit 953" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 24. "  GSB952  ,Group Status Bit 952" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 23. "  GSB951  ,Group Status Bit 951" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 22. " GSB950  ,Group Status Bit 950" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 21. "  GSB949  ,Group Status Bit 949" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 20. "  GSB948  ,Group Status Bit 948" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 19. " GSB947  ,Group Status Bit 947" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 18. "  GSB946  ,Group Status Bit 946" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 17. "  GSB945  ,Group Status Bit 945" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 16. " GSB944  ,Group Status Bit 944" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 15. "  GSB943  ,Group Status Bit 943" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 14. "  GSB942  ,Group Status Bit 942" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 13. " GSB941  ,Group Status Bit 941" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 12. "  GSB940  ,Group Status Bit 940" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 11. "  GSB939  ,Group Status Bit 939" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 10. " GSB938  ,Group Status Bit 938" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 9. "  GSB937  ,Group Status Bit 937" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 8. "  GSB936  ,Group Status Bit 936" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 7. " GSB935  ,Group Status Bit 935" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 6. "  GSB934  ,Group Status Bit 934" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 5. "  GSB933  ,Group Status Bit 933" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 4. " GSB932  ,Group Status Bit 932" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 3. "  GSB931  ,Group Status Bit 931" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 2. "  GSB930  ,Group Status Bit 930" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 1. " GSB929  ,Group Status Bit 929" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 0. "  GSB928  ,Group Status Bit 928" "Group 0 (Secure),Group 1 (Non-secure)"
elif (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1D)
group.long 0x00F4++0x03
line.long 0x0 "GICD_IGROUPR29,Interrupt Group Register 29 (Non-secure access)"
bitfld.long 0x00 31. " GSB959  ,Group Status Bit 959" "Group 0,Group 1"
bitfld.long 0x00 30. "  GSB958  ,Group Status Bit 958" "Group 0,Group 1"
bitfld.long 0x00 29. "  GSB957  ,Group Status Bit 957" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB956  ,Group Status Bit 956" "Group 0,Group 1"
bitfld.long 0x00 27. "  GSB955  ,Group Status Bit 955" "Group 0,Group 1"
bitfld.long 0x00 26. "  GSB954  ,Group Status Bit 954" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB953  ,Group Status Bit 953" "Group 0,Group 1"
bitfld.long 0x00 24. "  GSB952  ,Group Status Bit 952" "Group 0,Group 1"
bitfld.long 0x00 23. "  GSB951  ,Group Status Bit 951" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB950  ,Group Status Bit 950" "Group 0,Group 1"
bitfld.long 0x00 21. "  GSB949  ,Group Status Bit 949" "Group 0,Group 1"
bitfld.long 0x00 20. "  GSB948  ,Group Status Bit 948" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB947  ,Group Status Bit 947" "Group 0,Group 1"
bitfld.long 0x00 18. "  GSB946  ,Group Status Bit 946" "Group 0,Group 1"
bitfld.long 0x00 17. "  GSB945  ,Group Status Bit 945" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB944  ,Group Status Bit 944" "Group 0,Group 1"
bitfld.long 0x00 15. "  GSB943  ,Group Status Bit 943" "Group 0,Group 1"
bitfld.long 0x00 14. "  GSB942  ,Group Status Bit 942" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB941  ,Group Status Bit 941" "Group 0,Group 1"
bitfld.long 0x00 12. "  GSB940  ,Group Status Bit 940" "Group 0,Group 1"
bitfld.long 0x00 11. "  GSB939  ,Group Status Bit 939" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB938  ,Group Status Bit 938" "Group 0,Group 1"
bitfld.long 0x00 9. "  GSB937  ,Group Status Bit 937" "Group 0,Group 1"
bitfld.long 0x00 8. "  GSB936  ,Group Status Bit 936" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB935  ,Group Status Bit 935" "Group 0,Group 1"
bitfld.long 0x00 6. "  GSB934  ,Group Status Bit 934" "Group 0,Group 1"
bitfld.long 0x00 5. "  GSB933  ,Group Status Bit 933" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB932  ,Group Status Bit 932" "Group 0,Group 1"
bitfld.long 0x00 3. "  GSB931  ,Group Status Bit 931" "Group 0,Group 1"
bitfld.long 0x00 2. "  GSB930  ,Group Status Bit 930" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB929  ,Group Status Bit 929" "Group 0,Group 1"
bitfld.long 0x00 0. "  GSB928  ,Group Status Bit 928" "Group 0,Group 1"
else
rgroup.long 0x00F4++0x03
line.long 0x0 "GICD_IGROUPR29,Interrupt Group Register 29"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1E)&&(PER.ADDRESS.isSECUREEX(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x00F8))
group.long 0x00F8++0x03
line.long 0x0 "GICD_IGROUPR30,Interrupt Group Register 30 (Secure access)"
bitfld.long 0x00 31. " GSB991  ,Group Status Bit 991" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 30. "  GSB990  ,Group Status Bit 990" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 29. "  GSB989  ,Group Status Bit 989" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 28. " GSB988  ,Group Status Bit 988" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 27. "  GSB987  ,Group Status Bit 987" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 26. "  GSB986  ,Group Status Bit 986" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 25. " GSB985  ,Group Status Bit 985" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 24. "  GSB984  ,Group Status Bit 984" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 23. "  GSB983  ,Group Status Bit 983" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 22. " GSB982  ,Group Status Bit 982" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 21. "  GSB981  ,Group Status Bit 981" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 20. "  GSB980  ,Group Status Bit 980" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 19. " GSB979  ,Group Status Bit 979" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 18. "  GSB978  ,Group Status Bit 978" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 17. "  GSB977  ,Group Status Bit 977" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 16. " GSB976  ,Group Status Bit 976" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 15. "  GSB975  ,Group Status Bit 975" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 14. "  GSB974  ,Group Status Bit 974" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 13. " GSB973  ,Group Status Bit 973" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 12. "  GSB972  ,Group Status Bit 972" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 11. "  GSB971  ,Group Status Bit 971" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 10. " GSB970  ,Group Status Bit 970" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 9. "  GSB969  ,Group Status Bit 969" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 8. "  GSB968  ,Group Status Bit 968" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 7. " GSB967  ,Group Status Bit 967" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 6. "  GSB966  ,Group Status Bit 966" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 5. "  GSB965  ,Group Status Bit 965" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 4. " GSB964  ,Group Status Bit 964" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 3. "  GSB963  ,Group Status Bit 963" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 2. "  GSB962  ,Group Status Bit 962" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 1. " GSB961  ,Group Status Bit 961" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 0. "  GSB960  ,Group Status Bit 960" "Group 0 (Secure),Group 1 (Non-secure)"
elif (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1E)
group.long 0x00F8++0x03
line.long 0x0 "GICD_IGROUPR30,Interrupt Group Register 30 (Non-secure access)"
bitfld.long 0x00 31. " GSB991  ,Group Status Bit 991" "Group 0,Group 1"
bitfld.long 0x00 30. "  GSB990  ,Group Status Bit 990" "Group 0,Group 1"
bitfld.long 0x00 29. "  GSB989  ,Group Status Bit 989" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB988  ,Group Status Bit 988" "Group 0,Group 1"
bitfld.long 0x00 27. "  GSB987  ,Group Status Bit 987" "Group 0,Group 1"
bitfld.long 0x00 26. "  GSB986  ,Group Status Bit 986" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB985  ,Group Status Bit 985" "Group 0,Group 1"
bitfld.long 0x00 24. "  GSB984  ,Group Status Bit 984" "Group 0,Group 1"
bitfld.long 0x00 23. "  GSB983  ,Group Status Bit 983" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB982  ,Group Status Bit 982" "Group 0,Group 1"
bitfld.long 0x00 21. "  GSB981  ,Group Status Bit 981" "Group 0,Group 1"
bitfld.long 0x00 20. "  GSB980  ,Group Status Bit 980" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB979  ,Group Status Bit 979" "Group 0,Group 1"
bitfld.long 0x00 18. "  GSB978  ,Group Status Bit 978" "Group 0,Group 1"
bitfld.long 0x00 17. "  GSB977  ,Group Status Bit 977" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB976  ,Group Status Bit 976" "Group 0,Group 1"
bitfld.long 0x00 15. "  GSB975  ,Group Status Bit 975" "Group 0,Group 1"
bitfld.long 0x00 14. "  GSB974  ,Group Status Bit 974" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB973  ,Group Status Bit 973" "Group 0,Group 1"
bitfld.long 0x00 12. "  GSB972  ,Group Status Bit 972" "Group 0,Group 1"
bitfld.long 0x00 11. "  GSB971  ,Group Status Bit 971" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB970  ,Group Status Bit 970" "Group 0,Group 1"
bitfld.long 0x00 9. "  GSB969  ,Group Status Bit 969" "Group 0,Group 1"
bitfld.long 0x00 8. "  GSB968  ,Group Status Bit 968" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB967  ,Group Status Bit 967" "Group 0,Group 1"
bitfld.long 0x00 6. "  GSB966  ,Group Status Bit 966" "Group 0,Group 1"
bitfld.long 0x00 5. "  GSB965  ,Group Status Bit 965" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB964  ,Group Status Bit 964" "Group 0,Group 1"
bitfld.long 0x00 3. "  GSB963  ,Group Status Bit 963" "Group 0,Group 1"
bitfld.long 0x00 2. "  GSB962  ,Group Status Bit 962" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB961  ,Group Status Bit 961" "Group 0,Group 1"
bitfld.long 0x00 0. "  GSB960  ,Group Status Bit 960" "Group 0,Group 1"
else
rgroup.long 0x00F8++0x03
line.long 0x0 "GICD_IGROUPR30,Interrupt Group Register 30"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)==0x1F)&&(PER.ADDRESS.isSECUREEX(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x00FC))
group.long 0x00FC++0x03
line.long 0x0 "GICD_IGROUPR31,Interrupt Group Register 31 (Secure access)"
bitfld.long 0x00 27. " GSB1019 ,Group Status Bit 1019" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 26. "  GSB1018 ,Group Status Bit 1018" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 25. " GSB1017 ,Group Status Bit 1017" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 24. "  GSB1016 ,Group Status Bit 1016" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 23. "  GSB1015 ,Group Status Bit 1015" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 22. " GSB1014 ,Group Status Bit 1014" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 21. "  GSB1013 ,Group Status Bit 1013" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 20. "  GSB1012 ,Group Status Bit 1012" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 19. " GSB1011 ,Group Status Bit 1011" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 18. "  GSB1010 ,Group Status Bit 1010" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 17. "  GSB1009 ,Group Status Bit 1009" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 16. " GSB1008 ,Group Status Bit 1008" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 15. "  GSB1007 ,Group Status Bit 1007" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 14. "  GSB1006 ,Group Status Bit 1006" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 13. " GSB1005 ,Group Status Bit 1005" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 12. "  GSB1004 ,Group Status Bit 1004" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 11. "  GSB1003 ,Group Status Bit 1003" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 10. " GSB1002 ,Group Status Bit 1002" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 9. "  GSB1001 ,Group Status Bit 1001" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 8. "  GSB1000 ,Group Status Bit 1000" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 7. " GSB999  ,Group Status Bit 999" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 6. "  GSB998  ,Group Status Bit 998" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 5. "  GSB997  ,Group Status Bit 997" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 4. " GSB996  ,Group Status Bit 996" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 3. "  GSB995  ,Group Status Bit 995" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 2. "  GSB994  ,Group Status Bit 994" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 1. " GSB993  ,Group Status Bit 993" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 0. "  GSB992  ,Group Status Bit 992" "Group 0 (Secure),Group 1 (Non-secure)"
elif (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)==0x1F)
group.long 0x00FC++0x03
line.long 0x0 "GICD_IGROUPR31,Interrupt Group Register 31 (Non-secure access)"
bitfld.long 0x00 27. " GSB1019 ,Group Status Bit 1019" "Group 0,Group 1"
bitfld.long 0x00 26. "  GSB1018 ,Group Status Bit 1018" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB1017 ,Group Status Bit 1017" "Group 0,Group 1"
bitfld.long 0x00 24. "  GSB1016 ,Group Status Bit 1016" "Group 0,Group 1"
bitfld.long 0x00 23. "  GSB1015 ,Group Status Bit 1015" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB1014 ,Group Status Bit 1014" "Group 0,Group 1"
bitfld.long 0x00 21. "  GSB1013 ,Group Status Bit 1013" "Group 0,Group 1"
bitfld.long 0x00 20. "  GSB1012 ,Group Status Bit 1012" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB1011 ,Group Status Bit 1011" "Group 0,Group 1"
bitfld.long 0x00 18. "  GSB1010 ,Group Status Bit 1010" "Group 0,Group 1"
bitfld.long 0x00 17. "  GSB1009 ,Group Status Bit 1009" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB1008 ,Group Status Bit 1008" "Group 0,Group 1"
bitfld.long 0x00 15. "  GSB1007 ,Group Status Bit 1007" "Group 0,Group 1"
bitfld.long 0x00 14. "  GSB1006 ,Group Status Bit 1006" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB1005 ,Group Status Bit 1005" "Group 0,Group 1"
bitfld.long 0x00 12. "  GSB1004 ,Group Status Bit 1004" "Group 0,Group 1"
bitfld.long 0x00 11. "  GSB1003 ,Group Status Bit 1003" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB1002 ,Group Status Bit 1002" "Group 0,Group 1"
bitfld.long 0x00 9. "  GSB1001 ,Group Status Bit 1001" "Group 0,Group 1"
bitfld.long 0x00 8. "  GSB1000 ,Group Status Bit 1000" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB999  ,Group Status Bit 999" "Group 0,Group 1"
bitfld.long 0x00 6. "  GSB998  ,Group Status Bit 998" "Group 0,Group 1"
bitfld.long 0x00 5. "  GSB997  ,Group Status Bit 997" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB996  ,Group Status Bit 996" "Group 0,Group 1"
bitfld.long 0x00 3. "  GSB995  ,Group Status Bit 995" "Group 0,Group 1"
bitfld.long 0x00 2. "  GSB994  ,Group Status Bit 994" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB993  ,Group Status Bit 993" "Group 0,Group 1"
bitfld.long 0x00 0. "  GSB992  ,Group Status Bit 992" "Group 0,Group 1"
else
rgroup.long 0x00FC++0x03
line.long 0x0 "GICD_IGROUPR31,Interrupt Group Register 31"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
endif
tree.end
endif
width 24.
tree "Set/Clear Enable Registers"
group.long 0x0100++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER0,Interrupt Set/Clear Enable Register 0"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB31   ,Set/Clear Enable Bit 31" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB30   ,Set/Clear Enable Bit 30" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB29   ,Set/Clear Enable Bit 29" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB28   ,Set/Clear Enable Bit 28" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB27   ,Set/Clear Enable Bit 27" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB26   ,Set/Clear Enable Bit 26" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB25   ,Set/Clear Enable Bit 25" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB24   ,Set/Clear Enable Bit 24" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB23   ,Set/Clear Enable Bit 23" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB22   ,Set/Clear Enable Bit 22" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB21   ,Set/Clear Enable Bit 21" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB20   ,Set/Clear Enable Bit 20" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB19   ,Set/Clear Enable Bit 19" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB18   ,Set/Clear Enable Bit 18" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB17   ,Set/Clear Enable Bit 17" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB16   ,Set/Clear Enable Bit 16" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB15   ,Set/Clear Enable Bit 15" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB14   ,Set/Clear Enable Bit 14" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB13   ,Set/Clear Enable Bit 13" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB12   ,Set/Clear Enable Bit 12" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB11   ,Set/Clear Enable Bit 11" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB10   ,Set/Clear Enable Bit 10" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB9    ,Set/Clear Enable Bit 9" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB8    ,Set/Clear Enable Bit 8" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB7    ,Set/Clear Enable Bit 7" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB6    ,Set/Clear Enable Bit 6" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB5    ,Set/Clear Enable Bit 5" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB4    ,Set/Clear Enable Bit 4" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB3    ,Set/Clear Enable Bit 3" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB2    ,Set/Clear Enable Bit 2" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB1    ,Set/Clear Enable Bit 1" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB0    ,Set/Clear Enable Bit 0" "Disabled,Enabled"
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x01)
group.long 0x0104++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER1,Interrupt Set/Clear Enable Register 1"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB63   ,Set/Clear Enable Bit 63" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB62   ,Set/Clear Enable Bit 62" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB61   ,Set/Clear Enable Bit 61" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB60   ,Set/Clear Enable Bit 60" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB59   ,Set/Clear Enable Bit 59" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB58   ,Set/Clear Enable Bit 58" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB57   ,Set/Clear Enable Bit 57" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB56   ,Set/Clear Enable Bit 56" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB55   ,Set/Clear Enable Bit 55" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB54   ,Set/Clear Enable Bit 54" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB53   ,Set/Clear Enable Bit 53" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB52   ,Set/Clear Enable Bit 52" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB51   ,Set/Clear Enable Bit 51" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB50   ,Set/Clear Enable Bit 50" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB49   ,Set/Clear Enable Bit 49" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB48   ,Set/Clear Enable Bit 48" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB47   ,Set/Clear Enable Bit 47" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB46   ,Set/Clear Enable Bit 46" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB45   ,Set/Clear Enable Bit 45" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB44   ,Set/Clear Enable Bit 44" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB43   ,Set/Clear Enable Bit 43" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB42   ,Set/Clear Enable Bit 42" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB41   ,Set/Clear Enable Bit 41" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB40   ,Set/Clear Enable Bit 40" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB39   ,Set/Clear Enable Bit 39" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB38   ,Set/Clear Enable Bit 38" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB37   ,Set/Clear Enable Bit 37" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB36   ,Set/Clear Enable Bit 36" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB35   ,Set/Clear Enable Bit 35" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB34   ,Set/Clear Enable Bit 34" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB33   ,Set/Clear Enable Bit 33" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB32   ,Set/Clear Enable Bit 32" "Disabled,Enabled"
else
rgroup.long 0x0104++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER1,Interrupt Set/Clear Enable Register 1"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x02)
group.long 0x0108++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER2,Interrupt Set/Clear Enable Register 2"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB95   ,Set/Clear Enable Bit 95" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB94   ,Set/Clear Enable Bit 94" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB93   ,Set/Clear Enable Bit 93" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB92   ,Set/Clear Enable Bit 92" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB91   ,Set/Clear Enable Bit 91" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB90   ,Set/Clear Enable Bit 90" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB89   ,Set/Clear Enable Bit 89" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB88   ,Set/Clear Enable Bit 88" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB87   ,Set/Clear Enable Bit 87" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB86   ,Set/Clear Enable Bit 86" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB85   ,Set/Clear Enable Bit 85" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB84   ,Set/Clear Enable Bit 84" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB83   ,Set/Clear Enable Bit 83" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB82   ,Set/Clear Enable Bit 82" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB81   ,Set/Clear Enable Bit 81" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB80   ,Set/Clear Enable Bit 80" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB79   ,Set/Clear Enable Bit 79" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB78   ,Set/Clear Enable Bit 78" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB77   ,Set/Clear Enable Bit 77" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB76   ,Set/Clear Enable Bit 76" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB75   ,Set/Clear Enable Bit 75" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB74   ,Set/Clear Enable Bit 74" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB73   ,Set/Clear Enable Bit 73" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB72   ,Set/Clear Enable Bit 72" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB71   ,Set/Clear Enable Bit 71" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB70   ,Set/Clear Enable Bit 70" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB69   ,Set/Clear Enable Bit 69" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB68   ,Set/Clear Enable Bit 68" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB67   ,Set/Clear Enable Bit 67" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB66   ,Set/Clear Enable Bit 66" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB65   ,Set/Clear Enable Bit 65" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB64   ,Set/Clear Enable Bit 64" "Disabled,Enabled"
else
rgroup.long 0x0108++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER2,Interrupt Set/Clear Enable Register 2"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x03)
group.long 0x010C++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER3,Interrupt Set/Clear Enable Register 3"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB127  ,Set/Clear Enable Bit 127" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB126  ,Set/Clear Enable Bit 126" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB125  ,Set/Clear Enable Bit 125" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB124  ,Set/Clear Enable Bit 124" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB123  ,Set/Clear Enable Bit 123" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB122  ,Set/Clear Enable Bit 122" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB121  ,Set/Clear Enable Bit 121" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB120  ,Set/Clear Enable Bit 120" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB119  ,Set/Clear Enable Bit 119" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB118  ,Set/Clear Enable Bit 118" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB117  ,Set/Clear Enable Bit 117" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB116  ,Set/Clear Enable Bit 116" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB115  ,Set/Clear Enable Bit 115" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB114  ,Set/Clear Enable Bit 114" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB113  ,Set/Clear Enable Bit 113" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB112  ,Set/Clear Enable Bit 112" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB111  ,Set/Clear Enable Bit 111" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB110  ,Set/Clear Enable Bit 110" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB109  ,Set/Clear Enable Bit 109" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB108  ,Set/Clear Enable Bit 108" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB107  ,Set/Clear Enable Bit 107" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB106  ,Set/Clear Enable Bit 106" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB105  ,Set/Clear Enable Bit 105" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB104  ,Set/Clear Enable Bit 104" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB103  ,Set/Clear Enable Bit 103" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB102  ,Set/Clear Enable Bit 102" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB101  ,Set/Clear Enable Bit 101" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB100  ,Set/Clear Enable Bit 100" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB99   ,Set/Clear Enable Bit 99" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB98   ,Set/Clear Enable Bit 98" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB97   ,Set/Clear Enable Bit 97" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB96   ,Set/Clear Enable Bit 96" "Disabled,Enabled"
else
rgroup.long 0x010C++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER3,Interrupt Set/Clear Enable Register 3"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x04)
group.long 0x0110++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER4,Interrupt Set/Clear Enable Register 4"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB159  ,Set/Clear Enable Bit 159" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB158  ,Set/Clear Enable Bit 158" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB157  ,Set/Clear Enable Bit 157" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB156  ,Set/Clear Enable Bit 156" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB155  ,Set/Clear Enable Bit 155" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB154  ,Set/Clear Enable Bit 154" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB153  ,Set/Clear Enable Bit 153" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB152  ,Set/Clear Enable Bit 152" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB151  ,Set/Clear Enable Bit 151" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB150  ,Set/Clear Enable Bit 150" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB149  ,Set/Clear Enable Bit 149" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB148  ,Set/Clear Enable Bit 148" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB147  ,Set/Clear Enable Bit 147" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB146  ,Set/Clear Enable Bit 146" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB145  ,Set/Clear Enable Bit 145" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB144  ,Set/Clear Enable Bit 144" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB143  ,Set/Clear Enable Bit 143" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB142  ,Set/Clear Enable Bit 142" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB141  ,Set/Clear Enable Bit 141" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB140  ,Set/Clear Enable Bit 140" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB139  ,Set/Clear Enable Bit 139" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB138  ,Set/Clear Enable Bit 138" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB137  ,Set/Clear Enable Bit 137" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB136  ,Set/Clear Enable Bit 136" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB135  ,Set/Clear Enable Bit 135" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB134  ,Set/Clear Enable Bit 134" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB133  ,Set/Clear Enable Bit 133" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB132  ,Set/Clear Enable Bit 132" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB131  ,Set/Clear Enable Bit 131" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB130  ,Set/Clear Enable Bit 130" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB129  ,Set/Clear Enable Bit 129" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB128  ,Set/Clear Enable Bit 128" "Disabled,Enabled"
else
rgroup.long 0x0110++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER4,Interrupt Set/Clear Enable Register 4"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x05)
group.long 0x0114++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER5,Interrupt Set/Clear Enable Register 5"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB191  ,Set/Clear Enable Bit 191" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB190  ,Set/Clear Enable Bit 190" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB189  ,Set/Clear Enable Bit 189" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB188  ,Set/Clear Enable Bit 188" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB187  ,Set/Clear Enable Bit 187" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB186  ,Set/Clear Enable Bit 186" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB185  ,Set/Clear Enable Bit 185" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB184  ,Set/Clear Enable Bit 184" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB183  ,Set/Clear Enable Bit 183" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB182  ,Set/Clear Enable Bit 182" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB181  ,Set/Clear Enable Bit 181" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB180  ,Set/Clear Enable Bit 180" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB179  ,Set/Clear Enable Bit 179" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB178  ,Set/Clear Enable Bit 178" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB177  ,Set/Clear Enable Bit 177" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB176  ,Set/Clear Enable Bit 176" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB175  ,Set/Clear Enable Bit 175" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB174  ,Set/Clear Enable Bit 174" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB173  ,Set/Clear Enable Bit 173" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB172  ,Set/Clear Enable Bit 172" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB171  ,Set/Clear Enable Bit 171" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB170  ,Set/Clear Enable Bit 170" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB169  ,Set/Clear Enable Bit 169" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB168  ,Set/Clear Enable Bit 168" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB167  ,Set/Clear Enable Bit 167" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB166  ,Set/Clear Enable Bit 166" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB165  ,Set/Clear Enable Bit 165" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB164  ,Set/Clear Enable Bit 164" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB163  ,Set/Clear Enable Bit 163" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB162  ,Set/Clear Enable Bit 162" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB161  ,Set/Clear Enable Bit 161" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB160  ,Set/Clear Enable Bit 160" "Disabled,Enabled"
else
rgroup.long 0x0114++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER5,Interrupt Set/Clear Enable Register 5"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x06)
group.long 0x0118++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER6,Interrupt Set/Clear Enable Register 6"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB223  ,Set/Clear Enable Bit 223" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB222  ,Set/Clear Enable Bit 222" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB221  ,Set/Clear Enable Bit 221" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB220  ,Set/Clear Enable Bit 220" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB219  ,Set/Clear Enable Bit 219" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB218  ,Set/Clear Enable Bit 218" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB217  ,Set/Clear Enable Bit 217" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB216  ,Set/Clear Enable Bit 216" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB215  ,Set/Clear Enable Bit 215" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB214  ,Set/Clear Enable Bit 214" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB213  ,Set/Clear Enable Bit 213" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB212  ,Set/Clear Enable Bit 212" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB211  ,Set/Clear Enable Bit 211" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB210  ,Set/Clear Enable Bit 210" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB209  ,Set/Clear Enable Bit 209" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB208  ,Set/Clear Enable Bit 208" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB207  ,Set/Clear Enable Bit 207" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB206  ,Set/Clear Enable Bit 206" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB205  ,Set/Clear Enable Bit 205" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB204  ,Set/Clear Enable Bit 204" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB203  ,Set/Clear Enable Bit 203" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB202  ,Set/Clear Enable Bit 202" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB201  ,Set/Clear Enable Bit 201" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB200  ,Set/Clear Enable Bit 200" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB199  ,Set/Clear Enable Bit 199" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB198  ,Set/Clear Enable Bit 198" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB197  ,Set/Clear Enable Bit 197" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB196  ,Set/Clear Enable Bit 196" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB195  ,Set/Clear Enable Bit 195" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB194  ,Set/Clear Enable Bit 194" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB193  ,Set/Clear Enable Bit 193" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB192  ,Set/Clear Enable Bit 192" "Disabled,Enabled"
else
rgroup.long 0x0118++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER6,Interrupt Set/Clear Enable Register 6"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x07)
group.long 0x011C++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER7,Interrupt Set/Clear Enable Register 7"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB255  ,Set/Clear Enable Bit 255" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB254  ,Set/Clear Enable Bit 254" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB253  ,Set/Clear Enable Bit 253" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB252  ,Set/Clear Enable Bit 252" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB251  ,Set/Clear Enable Bit 251" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB250  ,Set/Clear Enable Bit 250" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB249  ,Set/Clear Enable Bit 249" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB248  ,Set/Clear Enable Bit 248" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB247  ,Set/Clear Enable Bit 247" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB246  ,Set/Clear Enable Bit 246" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB245  ,Set/Clear Enable Bit 245" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB244  ,Set/Clear Enable Bit 244" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB243  ,Set/Clear Enable Bit 243" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB242  ,Set/Clear Enable Bit 242" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB241  ,Set/Clear Enable Bit 241" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB240  ,Set/Clear Enable Bit 240" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB239  ,Set/Clear Enable Bit 239" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB238  ,Set/Clear Enable Bit 238" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB237  ,Set/Clear Enable Bit 237" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB236  ,Set/Clear Enable Bit 236" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB235  ,Set/Clear Enable Bit 235" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB234  ,Set/Clear Enable Bit 234" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB233  ,Set/Clear Enable Bit 233" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB232  ,Set/Clear Enable Bit 232" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB231  ,Set/Clear Enable Bit 231" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB230  ,Set/Clear Enable Bit 230" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB229  ,Set/Clear Enable Bit 229" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB228  ,Set/Clear Enable Bit 228" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB227  ,Set/Clear Enable Bit 227" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB226  ,Set/Clear Enable Bit 226" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB225  ,Set/Clear Enable Bit 225" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB224  ,Set/Clear Enable Bit 224" "Disabled,Enabled"
else
rgroup.long 0x011C++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER7,Interrupt Set/Clear Enable Register 7"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x08)
group.long 0x0120++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER8,Interrupt Set/Clear Enable Register 8"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB287  ,Set/Clear Enable Bit 287" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB286  ,Set/Clear Enable Bit 286" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB285  ,Set/Clear Enable Bit 285" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB284  ,Set/Clear Enable Bit 284" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB283  ,Set/Clear Enable Bit 283" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB282  ,Set/Clear Enable Bit 282" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB281  ,Set/Clear Enable Bit 281" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB280  ,Set/Clear Enable Bit 280" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB279  ,Set/Clear Enable Bit 279" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB278  ,Set/Clear Enable Bit 278" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB277  ,Set/Clear Enable Bit 277" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB276  ,Set/Clear Enable Bit 276" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB275  ,Set/Clear Enable Bit 275" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB274  ,Set/Clear Enable Bit 274" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB273  ,Set/Clear Enable Bit 273" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB272  ,Set/Clear Enable Bit 272" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB271  ,Set/Clear Enable Bit 271" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB270  ,Set/Clear Enable Bit 270" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB269  ,Set/Clear Enable Bit 269" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB268  ,Set/Clear Enable Bit 268" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB267  ,Set/Clear Enable Bit 267" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB266  ,Set/Clear Enable Bit 266" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB265  ,Set/Clear Enable Bit 265" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB264  ,Set/Clear Enable Bit 264" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB263  ,Set/Clear Enable Bit 263" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB262  ,Set/Clear Enable Bit 262" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB261  ,Set/Clear Enable Bit 261" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB260  ,Set/Clear Enable Bit 260" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB259  ,Set/Clear Enable Bit 259" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB258  ,Set/Clear Enable Bit 258" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB257  ,Set/Clear Enable Bit 257" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB256  ,Set/Clear Enable Bit 256" "Disabled,Enabled"
else
rgroup.long 0x0120++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER8,Interrupt Set/Clear Enable Register 8"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x09)
group.long 0x0124++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER9,Interrupt Set/Clear Enable Register 9"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB319  ,Set/Clear Enable Bit 319" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB318  ,Set/Clear Enable Bit 318" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB317  ,Set/Clear Enable Bit 317" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB316  ,Set/Clear Enable Bit 316" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB315  ,Set/Clear Enable Bit 315" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB314  ,Set/Clear Enable Bit 314" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB313  ,Set/Clear Enable Bit 313" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB312  ,Set/Clear Enable Bit 312" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB311  ,Set/Clear Enable Bit 311" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB310  ,Set/Clear Enable Bit 310" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB309  ,Set/Clear Enable Bit 309" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB308  ,Set/Clear Enable Bit 308" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB307  ,Set/Clear Enable Bit 307" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB306  ,Set/Clear Enable Bit 306" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB305  ,Set/Clear Enable Bit 305" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB304  ,Set/Clear Enable Bit 304" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB303  ,Set/Clear Enable Bit 303" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB302  ,Set/Clear Enable Bit 302" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB301  ,Set/Clear Enable Bit 301" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB300  ,Set/Clear Enable Bit 300" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB299  ,Set/Clear Enable Bit 299" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB298  ,Set/Clear Enable Bit 298" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB297  ,Set/Clear Enable Bit 297" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB296  ,Set/Clear Enable Bit 296" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB295  ,Set/Clear Enable Bit 295" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB294  ,Set/Clear Enable Bit 294" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB293  ,Set/Clear Enable Bit 293" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB292  ,Set/Clear Enable Bit 292" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB291  ,Set/Clear Enable Bit 291" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB290  ,Set/Clear Enable Bit 290" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB289  ,Set/Clear Enable Bit 289" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB288  ,Set/Clear Enable Bit 288" "Disabled,Enabled"
else
rgroup.long 0x0124++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER9,Interrupt Set/Clear Enable Register 9"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0A)
group.long 0x0128++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER10,Interrupt Set/Clear Enable Register 10"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB351  ,Set/Clear Enable Bit 351" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB350  ,Set/Clear Enable Bit 350" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB349  ,Set/Clear Enable Bit 349" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB348  ,Set/Clear Enable Bit 348" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB347  ,Set/Clear Enable Bit 347" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB346  ,Set/Clear Enable Bit 346" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB345  ,Set/Clear Enable Bit 345" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB344  ,Set/Clear Enable Bit 344" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB343  ,Set/Clear Enable Bit 343" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB342  ,Set/Clear Enable Bit 342" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB341  ,Set/Clear Enable Bit 341" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB340  ,Set/Clear Enable Bit 340" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB339  ,Set/Clear Enable Bit 339" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB338  ,Set/Clear Enable Bit 338" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB337  ,Set/Clear Enable Bit 337" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB336  ,Set/Clear Enable Bit 336" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB335  ,Set/Clear Enable Bit 335" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB334  ,Set/Clear Enable Bit 334" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB333  ,Set/Clear Enable Bit 333" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB332  ,Set/Clear Enable Bit 332" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB331  ,Set/Clear Enable Bit 331" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB330  ,Set/Clear Enable Bit 330" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB329  ,Set/Clear Enable Bit 329" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB328  ,Set/Clear Enable Bit 328" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB327  ,Set/Clear Enable Bit 327" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB326  ,Set/Clear Enable Bit 326" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB325  ,Set/Clear Enable Bit 325" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB324  ,Set/Clear Enable Bit 324" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB323  ,Set/Clear Enable Bit 323" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB322  ,Set/Clear Enable Bit 322" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB321  ,Set/Clear Enable Bit 321" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB320  ,Set/Clear Enable Bit 320" "Disabled,Enabled"
else
rgroup.long 0x0128++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER10,Interrupt Set/Clear Enable Register 10"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0B)
group.long 0x012C++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER11,Interrupt Set/Clear Enable Register 11"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB383  ,Set/Clear Enable Bit 383" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB382  ,Set/Clear Enable Bit 382" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB381  ,Set/Clear Enable Bit 381" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB380  ,Set/Clear Enable Bit 380" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB379  ,Set/Clear Enable Bit 379" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB378  ,Set/Clear Enable Bit 378" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB377  ,Set/Clear Enable Bit 377" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB376  ,Set/Clear Enable Bit 376" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB375  ,Set/Clear Enable Bit 375" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB374  ,Set/Clear Enable Bit 374" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB373  ,Set/Clear Enable Bit 373" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB372  ,Set/Clear Enable Bit 372" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB371  ,Set/Clear Enable Bit 371" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB370  ,Set/Clear Enable Bit 370" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB369  ,Set/Clear Enable Bit 369" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB368  ,Set/Clear Enable Bit 368" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB367  ,Set/Clear Enable Bit 367" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB366  ,Set/Clear Enable Bit 366" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB365  ,Set/Clear Enable Bit 365" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB364  ,Set/Clear Enable Bit 364" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB363  ,Set/Clear Enable Bit 363" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB362  ,Set/Clear Enable Bit 362" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB361  ,Set/Clear Enable Bit 361" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB360  ,Set/Clear Enable Bit 360" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB359  ,Set/Clear Enable Bit 359" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB358  ,Set/Clear Enable Bit 358" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB357  ,Set/Clear Enable Bit 357" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB356  ,Set/Clear Enable Bit 356" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB355  ,Set/Clear Enable Bit 355" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB354  ,Set/Clear Enable Bit 354" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB353  ,Set/Clear Enable Bit 353" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB352  ,Set/Clear Enable Bit 352" "Disabled,Enabled"
else
rgroup.long 0x012C++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER11,Interrupt Set/Clear Enable Register 11"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0C)
group.long 0x0130++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER12,Interrupt Set/Clear Enable Register 12"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB415  ,Set/Clear Enable Bit 415" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB414  ,Set/Clear Enable Bit 414" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB413  ,Set/Clear Enable Bit 413" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB412  ,Set/Clear Enable Bit 412" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB411  ,Set/Clear Enable Bit 411" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB410  ,Set/Clear Enable Bit 410" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB409  ,Set/Clear Enable Bit 409" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB408  ,Set/Clear Enable Bit 408" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB407  ,Set/Clear Enable Bit 407" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB406  ,Set/Clear Enable Bit 406" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB405  ,Set/Clear Enable Bit 405" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB404  ,Set/Clear Enable Bit 404" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB403  ,Set/Clear Enable Bit 403" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB402  ,Set/Clear Enable Bit 402" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB401  ,Set/Clear Enable Bit 401" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB400  ,Set/Clear Enable Bit 400" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB399  ,Set/Clear Enable Bit 399" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB398  ,Set/Clear Enable Bit 398" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB397  ,Set/Clear Enable Bit 397" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB396  ,Set/Clear Enable Bit 396" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB395  ,Set/Clear Enable Bit 395" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB394  ,Set/Clear Enable Bit 394" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB393  ,Set/Clear Enable Bit 393" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB392  ,Set/Clear Enable Bit 392" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB391  ,Set/Clear Enable Bit 391" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB390  ,Set/Clear Enable Bit 390" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB389  ,Set/Clear Enable Bit 389" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB388  ,Set/Clear Enable Bit 388" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB387  ,Set/Clear Enable Bit 387" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB386  ,Set/Clear Enable Bit 386" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB385  ,Set/Clear Enable Bit 385" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB384  ,Set/Clear Enable Bit 384" "Disabled,Enabled"
else
rgroup.long 0x0130++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER12,Interrupt Set/Clear Enable Register 12"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0D)
group.long 0x0134++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER13,Interrupt Set/Clear Enable Register 13"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB447  ,Set/Clear Enable Bit 447" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB446  ,Set/Clear Enable Bit 446" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB445  ,Set/Clear Enable Bit 445" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB444  ,Set/Clear Enable Bit 444" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB443  ,Set/Clear Enable Bit 443" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB442  ,Set/Clear Enable Bit 442" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB441  ,Set/Clear Enable Bit 441" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB440  ,Set/Clear Enable Bit 440" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB439  ,Set/Clear Enable Bit 439" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB438  ,Set/Clear Enable Bit 438" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB437  ,Set/Clear Enable Bit 437" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB436  ,Set/Clear Enable Bit 436" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB435  ,Set/Clear Enable Bit 435" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB434  ,Set/Clear Enable Bit 434" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB433  ,Set/Clear Enable Bit 433" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB432  ,Set/Clear Enable Bit 432" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB431  ,Set/Clear Enable Bit 431" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB430  ,Set/Clear Enable Bit 430" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB429  ,Set/Clear Enable Bit 429" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB428  ,Set/Clear Enable Bit 428" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB427  ,Set/Clear Enable Bit 427" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB426  ,Set/Clear Enable Bit 426" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB425  ,Set/Clear Enable Bit 425" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB424  ,Set/Clear Enable Bit 424" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB423  ,Set/Clear Enable Bit 423" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB422  ,Set/Clear Enable Bit 422" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB421  ,Set/Clear Enable Bit 421" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB420  ,Set/Clear Enable Bit 420" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB419  ,Set/Clear Enable Bit 419" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB418  ,Set/Clear Enable Bit 418" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB417  ,Set/Clear Enable Bit 417" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB416  ,Set/Clear Enable Bit 416" "Disabled,Enabled"
else
rgroup.long 0x0134++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER13,Interrupt Set/Clear Enable Register 13"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0E)
group.long 0x0138++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER14,Interrupt Set/Clear Enable Register 14"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB479  ,Set/Clear Enable Bit 479" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB478  ,Set/Clear Enable Bit 478" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB477  ,Set/Clear Enable Bit 477" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB476  ,Set/Clear Enable Bit 476" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB475  ,Set/Clear Enable Bit 475" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB474  ,Set/Clear Enable Bit 474" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB473  ,Set/Clear Enable Bit 473" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB472  ,Set/Clear Enable Bit 472" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB471  ,Set/Clear Enable Bit 471" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB470  ,Set/Clear Enable Bit 470" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB469  ,Set/Clear Enable Bit 469" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB468  ,Set/Clear Enable Bit 468" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB467  ,Set/Clear Enable Bit 467" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB466  ,Set/Clear Enable Bit 466" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB465  ,Set/Clear Enable Bit 465" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB464  ,Set/Clear Enable Bit 464" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB463  ,Set/Clear Enable Bit 463" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB462  ,Set/Clear Enable Bit 462" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB461  ,Set/Clear Enable Bit 461" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB460  ,Set/Clear Enable Bit 460" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB459  ,Set/Clear Enable Bit 459" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB458  ,Set/Clear Enable Bit 458" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB457  ,Set/Clear Enable Bit 457" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB456  ,Set/Clear Enable Bit 456" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB455  ,Set/Clear Enable Bit 455" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB454  ,Set/Clear Enable Bit 454" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB453  ,Set/Clear Enable Bit 453" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB452  ,Set/Clear Enable Bit 452" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB451  ,Set/Clear Enable Bit 451" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB450  ,Set/Clear Enable Bit 450" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB449  ,Set/Clear Enable Bit 449" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB448  ,Set/Clear Enable Bit 448" "Disabled,Enabled"
else
rgroup.long 0x0138++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER14,Interrupt Set/Clear Enable Register 14"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0F)
group.long 0x013C++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER15,Interrupt Set/Clear Enable Register 15"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB511  ,Set/Clear Enable Bit 511" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB510  ,Set/Clear Enable Bit 510" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB509  ,Set/Clear Enable Bit 509" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB508  ,Set/Clear Enable Bit 508" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB507  ,Set/Clear Enable Bit 507" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB506  ,Set/Clear Enable Bit 506" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB505  ,Set/Clear Enable Bit 505" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB504  ,Set/Clear Enable Bit 504" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB503  ,Set/Clear Enable Bit 503" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB502  ,Set/Clear Enable Bit 502" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB501  ,Set/Clear Enable Bit 501" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB500  ,Set/Clear Enable Bit 500" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB499  ,Set/Clear Enable Bit 499" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB498  ,Set/Clear Enable Bit 498" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB497  ,Set/Clear Enable Bit 497" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB496  ,Set/Clear Enable Bit 496" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB495  ,Set/Clear Enable Bit 495" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB494  ,Set/Clear Enable Bit 494" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB493  ,Set/Clear Enable Bit 493" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB492  ,Set/Clear Enable Bit 492" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB491  ,Set/Clear Enable Bit 491" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB490  ,Set/Clear Enable Bit 490" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB489  ,Set/Clear Enable Bit 489" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB488  ,Set/Clear Enable Bit 488" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB487  ,Set/Clear Enable Bit 487" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB486  ,Set/Clear Enable Bit 486" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB485  ,Set/Clear Enable Bit 485" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB484  ,Set/Clear Enable Bit 484" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB483  ,Set/Clear Enable Bit 483" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB482  ,Set/Clear Enable Bit 482" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB481  ,Set/Clear Enable Bit 481" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB480  ,Set/Clear Enable Bit 480" "Disabled,Enabled"
else
rgroup.long 0x013C++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER15,Interrupt Set/Clear Enable Register 15"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x10)
group.long 0x0140++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER16,Interrupt Set/Clear Enable Register 16"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB543  ,Set/Clear Enable Bit 543" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB542  ,Set/Clear Enable Bit 542" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB541  ,Set/Clear Enable Bit 541" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB540  ,Set/Clear Enable Bit 540" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB539  ,Set/Clear Enable Bit 539" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB538  ,Set/Clear Enable Bit 538" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB537  ,Set/Clear Enable Bit 537" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB536  ,Set/Clear Enable Bit 536" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB535  ,Set/Clear Enable Bit 535" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB534  ,Set/Clear Enable Bit 534" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB533  ,Set/Clear Enable Bit 533" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB532  ,Set/Clear Enable Bit 532" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB531  ,Set/Clear Enable Bit 531" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB530  ,Set/Clear Enable Bit 530" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB529  ,Set/Clear Enable Bit 529" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB528  ,Set/Clear Enable Bit 528" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB527  ,Set/Clear Enable Bit 527" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB526  ,Set/Clear Enable Bit 526" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB525  ,Set/Clear Enable Bit 525" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB524  ,Set/Clear Enable Bit 524" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB523  ,Set/Clear Enable Bit 523" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB522  ,Set/Clear Enable Bit 522" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB521  ,Set/Clear Enable Bit 521" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB520  ,Set/Clear Enable Bit 520" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB519  ,Set/Clear Enable Bit 519" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB518  ,Set/Clear Enable Bit 518" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB517  ,Set/Clear Enable Bit 517" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB516  ,Set/Clear Enable Bit 516" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB515  ,Set/Clear Enable Bit 515" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB514  ,Set/Clear Enable Bit 514" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB513  ,Set/Clear Enable Bit 513" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB512  ,Set/Clear Enable Bit 512" "Disabled,Enabled"
else
rgroup.long 0x0140++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER16,Interrupt Set/Clear Enable Register 16"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x11)
group.long 0x0144++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER17,Interrupt Set/Clear Enable Register 17"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB575  ,Set/Clear Enable Bit 575" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB574  ,Set/Clear Enable Bit 574" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB573  ,Set/Clear Enable Bit 573" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB572  ,Set/Clear Enable Bit 572" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB571  ,Set/Clear Enable Bit 571" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB570  ,Set/Clear Enable Bit 570" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB569  ,Set/Clear Enable Bit 569" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB568  ,Set/Clear Enable Bit 568" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB567  ,Set/Clear Enable Bit 567" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB566  ,Set/Clear Enable Bit 566" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB565  ,Set/Clear Enable Bit 565" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB564  ,Set/Clear Enable Bit 564" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB563  ,Set/Clear Enable Bit 563" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB562  ,Set/Clear Enable Bit 562" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB561  ,Set/Clear Enable Bit 561" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB560  ,Set/Clear Enable Bit 560" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB559  ,Set/Clear Enable Bit 559" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB558  ,Set/Clear Enable Bit 558" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB557  ,Set/Clear Enable Bit 557" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB556  ,Set/Clear Enable Bit 556" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB555  ,Set/Clear Enable Bit 555" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB554  ,Set/Clear Enable Bit 554" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB553  ,Set/Clear Enable Bit 553" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB552  ,Set/Clear Enable Bit 552" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB551  ,Set/Clear Enable Bit 551" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB550  ,Set/Clear Enable Bit 550" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB549  ,Set/Clear Enable Bit 549" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB548  ,Set/Clear Enable Bit 548" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB547  ,Set/Clear Enable Bit 547" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB546  ,Set/Clear Enable Bit 546" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB545  ,Set/Clear Enable Bit 545" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB544  ,Set/Clear Enable Bit 544" "Disabled,Enabled"
else
rgroup.long 0x0144++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER17,Interrupt Set/Clear Enable Register 17"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x12)
group.long 0x0148++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER18,Interrupt Set/Clear Enable Register 18"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB607  ,Set/Clear Enable Bit 607" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB606  ,Set/Clear Enable Bit 606" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB605  ,Set/Clear Enable Bit 605" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB604  ,Set/Clear Enable Bit 604" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB603  ,Set/Clear Enable Bit 603" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB602  ,Set/Clear Enable Bit 602" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB601  ,Set/Clear Enable Bit 601" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB600  ,Set/Clear Enable Bit 600" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB599  ,Set/Clear Enable Bit 599" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB598  ,Set/Clear Enable Bit 598" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB597  ,Set/Clear Enable Bit 597" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB596  ,Set/Clear Enable Bit 596" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB595  ,Set/Clear Enable Bit 595" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB594  ,Set/Clear Enable Bit 594" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB593  ,Set/Clear Enable Bit 593" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB592  ,Set/Clear Enable Bit 592" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB591  ,Set/Clear Enable Bit 591" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB590  ,Set/Clear Enable Bit 590" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB589  ,Set/Clear Enable Bit 589" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB588  ,Set/Clear Enable Bit 588" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB587  ,Set/Clear Enable Bit 587" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB586  ,Set/Clear Enable Bit 586" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB585  ,Set/Clear Enable Bit 585" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB584  ,Set/Clear Enable Bit 584" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB583  ,Set/Clear Enable Bit 583" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB582  ,Set/Clear Enable Bit 582" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB581  ,Set/Clear Enable Bit 581" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB580  ,Set/Clear Enable Bit 580" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB579  ,Set/Clear Enable Bit 579" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB578  ,Set/Clear Enable Bit 578" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB577  ,Set/Clear Enable Bit 577" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB576  ,Set/Clear Enable Bit 576" "Disabled,Enabled"
else
rgroup.long 0x0148++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER18,Interrupt Set/Clear Enable Register 18"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x13)
group.long 0x014C++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER19,Interrupt Set/Clear Enable Register 19"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB639  ,Set/Clear Enable Bit 639" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB638  ,Set/Clear Enable Bit 638" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB637  ,Set/Clear Enable Bit 637" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB636  ,Set/Clear Enable Bit 636" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB635  ,Set/Clear Enable Bit 635" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB634  ,Set/Clear Enable Bit 634" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB633  ,Set/Clear Enable Bit 633" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB632  ,Set/Clear Enable Bit 632" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB631  ,Set/Clear Enable Bit 631" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB630  ,Set/Clear Enable Bit 630" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB629  ,Set/Clear Enable Bit 629" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB628  ,Set/Clear Enable Bit 628" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB627  ,Set/Clear Enable Bit 627" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB626  ,Set/Clear Enable Bit 626" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB625  ,Set/Clear Enable Bit 625" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB624  ,Set/Clear Enable Bit 624" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB623  ,Set/Clear Enable Bit 623" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB622  ,Set/Clear Enable Bit 622" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB621  ,Set/Clear Enable Bit 621" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB620  ,Set/Clear Enable Bit 620" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB619  ,Set/Clear Enable Bit 619" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB618  ,Set/Clear Enable Bit 618" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB617  ,Set/Clear Enable Bit 617" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB616  ,Set/Clear Enable Bit 616" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB615  ,Set/Clear Enable Bit 615" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB614  ,Set/Clear Enable Bit 614" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB613  ,Set/Clear Enable Bit 613" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB612  ,Set/Clear Enable Bit 612" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB611  ,Set/Clear Enable Bit 611" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB610  ,Set/Clear Enable Bit 610" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB609  ,Set/Clear Enable Bit 609" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB608  ,Set/Clear Enable Bit 608" "Disabled,Enabled"
else
rgroup.long 0x014C++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER19,Interrupt Set/Clear Enable Register 19"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x14)
group.long 0x0150++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER20,Interrupt Set/Clear Enable Register 20"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB671  ,Set/Clear Enable Bit 671" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB670  ,Set/Clear Enable Bit 670" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB669  ,Set/Clear Enable Bit 669" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB668  ,Set/Clear Enable Bit 668" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB667  ,Set/Clear Enable Bit 667" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB666  ,Set/Clear Enable Bit 666" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB665  ,Set/Clear Enable Bit 665" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB664  ,Set/Clear Enable Bit 664" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB663  ,Set/Clear Enable Bit 663" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB662  ,Set/Clear Enable Bit 662" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB661  ,Set/Clear Enable Bit 661" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB660  ,Set/Clear Enable Bit 660" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB659  ,Set/Clear Enable Bit 659" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB658  ,Set/Clear Enable Bit 658" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB657  ,Set/Clear Enable Bit 657" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB656  ,Set/Clear Enable Bit 656" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB655  ,Set/Clear Enable Bit 655" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB654  ,Set/Clear Enable Bit 654" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB653  ,Set/Clear Enable Bit 653" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB652  ,Set/Clear Enable Bit 652" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB651  ,Set/Clear Enable Bit 651" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB650  ,Set/Clear Enable Bit 650" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB649  ,Set/Clear Enable Bit 649" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB648  ,Set/Clear Enable Bit 648" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB647  ,Set/Clear Enable Bit 647" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB646  ,Set/Clear Enable Bit 646" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB645  ,Set/Clear Enable Bit 645" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB644  ,Set/Clear Enable Bit 644" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB643  ,Set/Clear Enable Bit 643" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB642  ,Set/Clear Enable Bit 642" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB641  ,Set/Clear Enable Bit 641" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB640  ,Set/Clear Enable Bit 640" "Disabled,Enabled"
else
rgroup.long 0x0150++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER20,Interrupt Set/Clear Enable Register 20"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x15)
group.long 0x0154++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER21,Interrupt Set/Clear Enable Register 21"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB703  ,Set/Clear Enable Bit 703" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB702  ,Set/Clear Enable Bit 702" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB701  ,Set/Clear Enable Bit 701" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB700  ,Set/Clear Enable Bit 700" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB699  ,Set/Clear Enable Bit 699" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB698  ,Set/Clear Enable Bit 698" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB697  ,Set/Clear Enable Bit 697" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB696  ,Set/Clear Enable Bit 696" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB695  ,Set/Clear Enable Bit 695" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB694  ,Set/Clear Enable Bit 694" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB693  ,Set/Clear Enable Bit 693" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB692  ,Set/Clear Enable Bit 692" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB691  ,Set/Clear Enable Bit 691" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB690  ,Set/Clear Enable Bit 690" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB689  ,Set/Clear Enable Bit 689" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB688  ,Set/Clear Enable Bit 688" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB687  ,Set/Clear Enable Bit 687" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB686  ,Set/Clear Enable Bit 686" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB685  ,Set/Clear Enable Bit 685" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB684  ,Set/Clear Enable Bit 684" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB683  ,Set/Clear Enable Bit 683" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB682  ,Set/Clear Enable Bit 682" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB681  ,Set/Clear Enable Bit 681" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB680  ,Set/Clear Enable Bit 680" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB679  ,Set/Clear Enable Bit 679" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB678  ,Set/Clear Enable Bit 678" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB677  ,Set/Clear Enable Bit 677" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB676  ,Set/Clear Enable Bit 676" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB675  ,Set/Clear Enable Bit 675" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB674  ,Set/Clear Enable Bit 674" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB673  ,Set/Clear Enable Bit 673" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB672  ,Set/Clear Enable Bit 672" "Disabled,Enabled"
else
rgroup.long 0x0154++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER21,Interrupt Set/Clear Enable Register 21"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x16)
group.long 0x0158++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER22,Interrupt Set/Clear Enable Register 22"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB735  ,Set/Clear Enable Bit 735" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB734  ,Set/Clear Enable Bit 734" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB733  ,Set/Clear Enable Bit 733" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB732  ,Set/Clear Enable Bit 732" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB731  ,Set/Clear Enable Bit 731" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB730  ,Set/Clear Enable Bit 730" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB729  ,Set/Clear Enable Bit 729" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB728  ,Set/Clear Enable Bit 728" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB727  ,Set/Clear Enable Bit 727" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB726  ,Set/Clear Enable Bit 726" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB725  ,Set/Clear Enable Bit 725" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB724  ,Set/Clear Enable Bit 724" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB723  ,Set/Clear Enable Bit 723" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB722  ,Set/Clear Enable Bit 722" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB721  ,Set/Clear Enable Bit 721" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB720  ,Set/Clear Enable Bit 720" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB719  ,Set/Clear Enable Bit 719" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB718  ,Set/Clear Enable Bit 718" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB717  ,Set/Clear Enable Bit 717" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB716  ,Set/Clear Enable Bit 716" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB715  ,Set/Clear Enable Bit 715" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB714  ,Set/Clear Enable Bit 714" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB713  ,Set/Clear Enable Bit 713" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB712  ,Set/Clear Enable Bit 712" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB711  ,Set/Clear Enable Bit 711" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB710  ,Set/Clear Enable Bit 710" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB709  ,Set/Clear Enable Bit 709" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB708  ,Set/Clear Enable Bit 708" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB707  ,Set/Clear Enable Bit 707" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB706  ,Set/Clear Enable Bit 706" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB705  ,Set/Clear Enable Bit 705" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB704  ,Set/Clear Enable Bit 704" "Disabled,Enabled"
else
rgroup.long 0x0158++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER22,Interrupt Set/Clear Enable Register 22"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x17)
group.long 0x015C++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER23,Interrupt Set/Clear Enable Register 23"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB767  ,Set/Clear Enable Bit 767" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB766  ,Set/Clear Enable Bit 766" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB765  ,Set/Clear Enable Bit 765" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB764  ,Set/Clear Enable Bit 764" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB763  ,Set/Clear Enable Bit 763" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB762  ,Set/Clear Enable Bit 762" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB761  ,Set/Clear Enable Bit 761" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB760  ,Set/Clear Enable Bit 760" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB759  ,Set/Clear Enable Bit 759" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB758  ,Set/Clear Enable Bit 758" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB757  ,Set/Clear Enable Bit 757" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB756  ,Set/Clear Enable Bit 756" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB755  ,Set/Clear Enable Bit 755" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB754  ,Set/Clear Enable Bit 754" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB753  ,Set/Clear Enable Bit 753" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB752  ,Set/Clear Enable Bit 752" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB751  ,Set/Clear Enable Bit 751" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB750  ,Set/Clear Enable Bit 750" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB749  ,Set/Clear Enable Bit 749" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB748  ,Set/Clear Enable Bit 748" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB747  ,Set/Clear Enable Bit 747" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB746  ,Set/Clear Enable Bit 746" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB745  ,Set/Clear Enable Bit 745" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB744  ,Set/Clear Enable Bit 744" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB743  ,Set/Clear Enable Bit 743" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB742  ,Set/Clear Enable Bit 742" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB741  ,Set/Clear Enable Bit 741" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB740  ,Set/Clear Enable Bit 740" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB739  ,Set/Clear Enable Bit 739" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB738  ,Set/Clear Enable Bit 738" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB737  ,Set/Clear Enable Bit 737" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB736  ,Set/Clear Enable Bit 736" "Disabled,Enabled"
else
rgroup.long 0x015C++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER23,Interrupt Set/Clear Enable Register 23"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x18)
group.long 0x0160++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER24,Interrupt Set/Clear Enable Register 24"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB799  ,Set/Clear Enable Bit 799" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB798  ,Set/Clear Enable Bit 798" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB797  ,Set/Clear Enable Bit 797" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB796  ,Set/Clear Enable Bit 796" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB795  ,Set/Clear Enable Bit 795" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB794  ,Set/Clear Enable Bit 794" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB793  ,Set/Clear Enable Bit 793" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB792  ,Set/Clear Enable Bit 792" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB791  ,Set/Clear Enable Bit 791" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB790  ,Set/Clear Enable Bit 790" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB789  ,Set/Clear Enable Bit 789" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB788  ,Set/Clear Enable Bit 788" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB787  ,Set/Clear Enable Bit 787" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB786  ,Set/Clear Enable Bit 786" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB785  ,Set/Clear Enable Bit 785" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB784  ,Set/Clear Enable Bit 784" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB783  ,Set/Clear Enable Bit 783" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB782  ,Set/Clear Enable Bit 782" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB781  ,Set/Clear Enable Bit 781" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB780  ,Set/Clear Enable Bit 780" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB779  ,Set/Clear Enable Bit 779" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB778  ,Set/Clear Enable Bit 778" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB777  ,Set/Clear Enable Bit 777" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB776  ,Set/Clear Enable Bit 776" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB775  ,Set/Clear Enable Bit 775" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB774  ,Set/Clear Enable Bit 774" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB773  ,Set/Clear Enable Bit 773" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB772  ,Set/Clear Enable Bit 772" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB771  ,Set/Clear Enable Bit 771" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB770  ,Set/Clear Enable Bit 770" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB769  ,Set/Clear Enable Bit 769" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB768  ,Set/Clear Enable Bit 768" "Disabled,Enabled"
else
rgroup.long 0x0160++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER24,Interrupt Set/Clear Enable Register 24"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x19)
group.long 0x0164++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER25,Interrupt Set/Clear Enable Register 25"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB831  ,Set/Clear Enable Bit 831" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB830  ,Set/Clear Enable Bit 830" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB829  ,Set/Clear Enable Bit 829" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB828  ,Set/Clear Enable Bit 828" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB827  ,Set/Clear Enable Bit 827" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB826  ,Set/Clear Enable Bit 826" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB825  ,Set/Clear Enable Bit 825" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB824  ,Set/Clear Enable Bit 824" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB823  ,Set/Clear Enable Bit 823" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB822  ,Set/Clear Enable Bit 822" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB821  ,Set/Clear Enable Bit 821" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB820  ,Set/Clear Enable Bit 820" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB819  ,Set/Clear Enable Bit 819" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB818  ,Set/Clear Enable Bit 818" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB817  ,Set/Clear Enable Bit 817" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB816  ,Set/Clear Enable Bit 816" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB815  ,Set/Clear Enable Bit 815" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB814  ,Set/Clear Enable Bit 814" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB813  ,Set/Clear Enable Bit 813" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB812  ,Set/Clear Enable Bit 812" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB811  ,Set/Clear Enable Bit 811" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB810  ,Set/Clear Enable Bit 810" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB809  ,Set/Clear Enable Bit 809" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB808  ,Set/Clear Enable Bit 808" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB807  ,Set/Clear Enable Bit 807" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB806  ,Set/Clear Enable Bit 806" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB805  ,Set/Clear Enable Bit 805" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB804  ,Set/Clear Enable Bit 804" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB803  ,Set/Clear Enable Bit 803" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB802  ,Set/Clear Enable Bit 802" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB801  ,Set/Clear Enable Bit 801" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB800  ,Set/Clear Enable Bit 800" "Disabled,Enabled"
else
rgroup.long 0x0164++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER25,Interrupt Set/Clear Enable Register 25"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1A)
group.long 0x0168++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER26,Interrupt Set/Clear Enable Register 26"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB863  ,Set/Clear Enable Bit 863" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB862  ,Set/Clear Enable Bit 862" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB861  ,Set/Clear Enable Bit 861" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB860  ,Set/Clear Enable Bit 860" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB859  ,Set/Clear Enable Bit 859" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB858  ,Set/Clear Enable Bit 858" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB857  ,Set/Clear Enable Bit 857" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB856  ,Set/Clear Enable Bit 856" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB855  ,Set/Clear Enable Bit 855" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB854  ,Set/Clear Enable Bit 854" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB853  ,Set/Clear Enable Bit 853" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB852  ,Set/Clear Enable Bit 852" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB851  ,Set/Clear Enable Bit 851" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB850  ,Set/Clear Enable Bit 850" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB849  ,Set/Clear Enable Bit 849" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB848  ,Set/Clear Enable Bit 848" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB847  ,Set/Clear Enable Bit 847" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB846  ,Set/Clear Enable Bit 846" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB845  ,Set/Clear Enable Bit 845" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB844  ,Set/Clear Enable Bit 844" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB843  ,Set/Clear Enable Bit 843" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB842  ,Set/Clear Enable Bit 842" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB841  ,Set/Clear Enable Bit 841" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB840  ,Set/Clear Enable Bit 840" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB839  ,Set/Clear Enable Bit 839" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB838  ,Set/Clear Enable Bit 838" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB837  ,Set/Clear Enable Bit 837" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB836  ,Set/Clear Enable Bit 836" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB835  ,Set/Clear Enable Bit 835" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB834  ,Set/Clear Enable Bit 834" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB833  ,Set/Clear Enable Bit 833" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB832  ,Set/Clear Enable Bit 832" "Disabled,Enabled"
else
rgroup.long 0x0168++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER26,Interrupt Set/Clear Enable Register 26"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1B)
group.long 0x016C++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER27,Interrupt Set/Clear Enable Register 27"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB895  ,Set/Clear Enable Bit 895" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB894  ,Set/Clear Enable Bit 894" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB893  ,Set/Clear Enable Bit 893" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB892  ,Set/Clear Enable Bit 892" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB891  ,Set/Clear Enable Bit 891" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB890  ,Set/Clear Enable Bit 890" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB889  ,Set/Clear Enable Bit 889" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB888  ,Set/Clear Enable Bit 888" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB887  ,Set/Clear Enable Bit 887" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB886  ,Set/Clear Enable Bit 886" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB885  ,Set/Clear Enable Bit 885" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB884  ,Set/Clear Enable Bit 884" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB883  ,Set/Clear Enable Bit 883" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB882  ,Set/Clear Enable Bit 882" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB881  ,Set/Clear Enable Bit 881" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB880  ,Set/Clear Enable Bit 880" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB879  ,Set/Clear Enable Bit 879" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB878  ,Set/Clear Enable Bit 878" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB877  ,Set/Clear Enable Bit 877" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB876  ,Set/Clear Enable Bit 876" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB875  ,Set/Clear Enable Bit 875" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB874  ,Set/Clear Enable Bit 874" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB873  ,Set/Clear Enable Bit 873" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB872  ,Set/Clear Enable Bit 872" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB871  ,Set/Clear Enable Bit 871" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB870  ,Set/Clear Enable Bit 870" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB869  ,Set/Clear Enable Bit 869" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB868  ,Set/Clear Enable Bit 868" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB867  ,Set/Clear Enable Bit 867" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB866  ,Set/Clear Enable Bit 866" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB865  ,Set/Clear Enable Bit 865" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB864  ,Set/Clear Enable Bit 864" "Disabled,Enabled"
else
rgroup.long 0x016C++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER27,Interrupt Set/Clear Enable Register 27"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1C)
group.long 0x0170++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER28,Interrupt Set/Clear Enable Register 28"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB927  ,Set/Clear Enable Bit 927" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB926  ,Set/Clear Enable Bit 926" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB925  ,Set/Clear Enable Bit 925" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB924  ,Set/Clear Enable Bit 924" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB923  ,Set/Clear Enable Bit 923" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB922  ,Set/Clear Enable Bit 922" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB921  ,Set/Clear Enable Bit 921" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB920  ,Set/Clear Enable Bit 920" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB919  ,Set/Clear Enable Bit 919" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB918  ,Set/Clear Enable Bit 918" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB917  ,Set/Clear Enable Bit 917" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB916  ,Set/Clear Enable Bit 916" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB915  ,Set/Clear Enable Bit 915" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB914  ,Set/Clear Enable Bit 914" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB913  ,Set/Clear Enable Bit 913" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB912  ,Set/Clear Enable Bit 912" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB911  ,Set/Clear Enable Bit 911" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB910  ,Set/Clear Enable Bit 910" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB909  ,Set/Clear Enable Bit 909" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB908  ,Set/Clear Enable Bit 908" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB907  ,Set/Clear Enable Bit 907" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB906  ,Set/Clear Enable Bit 906" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB905  ,Set/Clear Enable Bit 905" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB904  ,Set/Clear Enable Bit 904" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB903  ,Set/Clear Enable Bit 903" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB902  ,Set/Clear Enable Bit 902" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB901  ,Set/Clear Enable Bit 901" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB900  ,Set/Clear Enable Bit 900" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB899  ,Set/Clear Enable Bit 899" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB898  ,Set/Clear Enable Bit 898" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB897  ,Set/Clear Enable Bit 897" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB896  ,Set/Clear Enable Bit 896" "Disabled,Enabled"
else
rgroup.long 0x0170++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER28,Interrupt Set/Clear Enable Register 28"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1D)
group.long 0x0174++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER29,Interrupt Set/Clear Enable Register 29"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB959  ,Set/Clear Enable Bit 959" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB958  ,Set/Clear Enable Bit 958" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB957  ,Set/Clear Enable Bit 957" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB956  ,Set/Clear Enable Bit 956" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB955  ,Set/Clear Enable Bit 955" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB954  ,Set/Clear Enable Bit 954" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB953  ,Set/Clear Enable Bit 953" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB952  ,Set/Clear Enable Bit 952" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB951  ,Set/Clear Enable Bit 951" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB950  ,Set/Clear Enable Bit 950" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB949  ,Set/Clear Enable Bit 949" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB948  ,Set/Clear Enable Bit 948" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB947  ,Set/Clear Enable Bit 947" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB946  ,Set/Clear Enable Bit 946" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB945  ,Set/Clear Enable Bit 945" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB944  ,Set/Clear Enable Bit 944" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB943  ,Set/Clear Enable Bit 943" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB942  ,Set/Clear Enable Bit 942" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB941  ,Set/Clear Enable Bit 941" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB940  ,Set/Clear Enable Bit 940" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB939  ,Set/Clear Enable Bit 939" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB938  ,Set/Clear Enable Bit 938" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB937  ,Set/Clear Enable Bit 937" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB936  ,Set/Clear Enable Bit 936" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB935  ,Set/Clear Enable Bit 935" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB934  ,Set/Clear Enable Bit 934" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB933  ,Set/Clear Enable Bit 933" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB932  ,Set/Clear Enable Bit 932" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB931  ,Set/Clear Enable Bit 931" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB930  ,Set/Clear Enable Bit 930" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB929  ,Set/Clear Enable Bit 929" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB928  ,Set/Clear Enable Bit 928" "Disabled,Enabled"
else
rgroup.long 0x0174++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER29,Interrupt Set/Clear Enable Register 29"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1E)
group.long 0x0178++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER30,Interrupt Set/Clear Enable Register 30"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB991  ,Set/Clear Enable Bit 991" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB990  ,Set/Clear Enable Bit 990" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB989  ,Set/Clear Enable Bit 989" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB988  ,Set/Clear Enable Bit 988" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB987  ,Set/Clear Enable Bit 987" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB986  ,Set/Clear Enable Bit 986" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB985  ,Set/Clear Enable Bit 985" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB984  ,Set/Clear Enable Bit 984" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB983  ,Set/Clear Enable Bit 983" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB982  ,Set/Clear Enable Bit 982" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB981  ,Set/Clear Enable Bit 981" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB980  ,Set/Clear Enable Bit 980" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB979  ,Set/Clear Enable Bit 979" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB978  ,Set/Clear Enable Bit 978" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB977  ,Set/Clear Enable Bit 977" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB976  ,Set/Clear Enable Bit 976" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB975  ,Set/Clear Enable Bit 975" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB974  ,Set/Clear Enable Bit 974" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB973  ,Set/Clear Enable Bit 973" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB972  ,Set/Clear Enable Bit 972" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB971  ,Set/Clear Enable Bit 971" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB970  ,Set/Clear Enable Bit 970" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB969  ,Set/Clear Enable Bit 969" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB968  ,Set/Clear Enable Bit 968" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB967  ,Set/Clear Enable Bit 967" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB966  ,Set/Clear Enable Bit 966" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB965  ,Set/Clear Enable Bit 965" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB964  ,Set/Clear Enable Bit 964" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB963  ,Set/Clear Enable Bit 963" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB962  ,Set/Clear Enable Bit 962" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB961  ,Set/Clear Enable Bit 961" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB960  ,Set/Clear Enable Bit 960" "Disabled,Enabled"
else
rgroup.long 0x0178++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER30,Interrupt Set/Clear Enable Register 30"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)==0x1F)
group.long 0x017C++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER31,Interrupt Set/Clear Enable Register 31"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB1019 ,Set/Clear Enable Bit 1019" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB1018 ,Set/Clear Enable Bit 1018" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB1017 ,Set/Clear Enable Bit 1017" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB1016 ,Set/Clear Enable Bit 1016" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB1015 ,Set/Clear Enable Bit 1015" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB1014 ,Set/Clear Enable Bit 1014" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB1013 ,Set/Clear Enable Bit 1013" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB1012 ,Set/Clear Enable Bit 1012" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB1011 ,Set/Clear Enable Bit 1011" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB1010 ,Set/Clear Enable Bit 1010" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB1009 ,Set/Clear Enable Bit 1009" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB1008 ,Set/Clear Enable Bit 1008" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB1007 ,Set/Clear Enable Bit 1007" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB1006 ,Set/Clear Enable Bit 1006" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB1005 ,Set/Clear Enable Bit 1005" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB1004 ,Set/Clear Enable Bit 1004" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB1003 ,Set/Clear Enable Bit 1003" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB1002 ,Set/Clear Enable Bit 1002" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB1001 ,Set/Clear Enable Bit 1001" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB1000 ,Set/Clear Enable Bit 1000" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB999  ,Set/Clear Enable Bit 999" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB998  ,Set/Clear Enable Bit 998" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB997  ,Set/Clear Enable Bit 997" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB996  ,Set/Clear Enable Bit 996" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB995  ,Set/Clear Enable Bit 995" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB994  ,Set/Clear Enable Bit 994" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB993  ,Set/Clear Enable Bit 993" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB992  ,Set/Clear Enable Bit 992" "Disabled,Enabled"
else
rgroup.long 0x017C++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER31,Interrupt Set/Clear Enable Register 31"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
tree.end
width 22.
tree "Set/Clear Pending Registers"
group.long 0x0200++0x03
line.long 0x0 "GICD_SET/CLR_PENDR0,Interrupt Set/Clear Pending Register 0"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND31   ,Set/Clear Pending Bit 31" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND30   ,Set/Clear Pending Bit 30" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND29   ,Set/Clear Pending Bit 29" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND28   ,Set/Clear Pending Bit 28" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND27   ,Set/Clear Pending Bit 27" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND26   ,Set/Clear Pending Bit 26" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND25   ,Set/Clear Pending Bit 25" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND24   ,Set/Clear Pending Bit 24" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND23   ,Set/Clear Pending Bit 23" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND22   ,Set/Clear Pending Bit 22" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND21   ,Set/Clear Pending Bit 21" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND20   ,Set/Clear Pending Bit 20" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND19   ,Set/Clear Pending Bit 19" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND18   ,Set/Clear Pending Bit 18" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND17   ,Set/Clear Pending Bit 17" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND16   ,Set/Clear Pending Bit 16" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND15   ,Set/Clear Pending Bit 15" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND14   ,Set/Clear Pending Bit 14" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND13   ,Set/Clear Pending Bit 13" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND12   ,Set/Clear Pending Bit 12" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND11   ,Set/Clear Pending Bit 11" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND10   ,Set/Clear Pending Bit 10" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND9    ,Set/Clear Pending Bit 9" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND8    ,Set/Clear Pending Bit 8" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND7    ,Set/Clear Pending Bit 7" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND6    ,Set/Clear Pending Bit 6" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND5    ,Set/Clear Pending Bit 5" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND4    ,Set/Clear Pending Bit 4" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND3    ,Set/Clear Pending Bit 3" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND2    ,Set/Clear Pending Bit 2" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND1    ,Set/Clear Pending Bit 1" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND0    ,Set/Clear Pending Bit 0" "Not pending,Pending"
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x01)
group.long 0x0204++0x03
line.long 0x0 "GICD_SET/CLR_PENDR1,Interrupt Set/Clear Pending Register 1"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND63   ,Set/Clear Pending Bit 63" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND62   ,Set/Clear Pending Bit 62" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND61   ,Set/Clear Pending Bit 61" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND60   ,Set/Clear Pending Bit 60" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND59   ,Set/Clear Pending Bit 59" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND58   ,Set/Clear Pending Bit 58" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND57   ,Set/Clear Pending Bit 57" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND56   ,Set/Clear Pending Bit 56" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND55   ,Set/Clear Pending Bit 55" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND54   ,Set/Clear Pending Bit 54" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND53   ,Set/Clear Pending Bit 53" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND52   ,Set/Clear Pending Bit 52" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND51   ,Set/Clear Pending Bit 51" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND50   ,Set/Clear Pending Bit 50" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND49   ,Set/Clear Pending Bit 49" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND48   ,Set/Clear Pending Bit 48" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND47   ,Set/Clear Pending Bit 47" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND46   ,Set/Clear Pending Bit 46" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND45   ,Set/Clear Pending Bit 45" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND44   ,Set/Clear Pending Bit 44" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND43   ,Set/Clear Pending Bit 43" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND42   ,Set/Clear Pending Bit 42" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND41   ,Set/Clear Pending Bit 41" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND40   ,Set/Clear Pending Bit 40" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND39   ,Set/Clear Pending Bit 39" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND38   ,Set/Clear Pending Bit 38" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND37   ,Set/Clear Pending Bit 37" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND36   ,Set/Clear Pending Bit 36" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND35   ,Set/Clear Pending Bit 35" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND34   ,Set/Clear Pending Bit 34" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND33   ,Set/Clear Pending Bit 33" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND32   ,Set/Clear Pending Bit 32" "Not pending,Pending"
else
rgroup.long 0x0204++0x03
line.long 0x0 "GICD_SET/CLR_PENDR1,Interrupt Set/Clear Pending Register 1"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x02)
group.long 0x0208++0x03
line.long 0x0 "GICD_SET/CLR_PENDR2,Interrupt Set/Clear Pending Register 2"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND95   ,Set/Clear Pending Bit 95" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND94   ,Set/Clear Pending Bit 94" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND93   ,Set/Clear Pending Bit 93" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND92   ,Set/Clear Pending Bit 92" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND91   ,Set/Clear Pending Bit 91" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND90   ,Set/Clear Pending Bit 90" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND89   ,Set/Clear Pending Bit 89" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND88   ,Set/Clear Pending Bit 88" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND87   ,Set/Clear Pending Bit 87" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND86   ,Set/Clear Pending Bit 86" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND85   ,Set/Clear Pending Bit 85" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND84   ,Set/Clear Pending Bit 84" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND83   ,Set/Clear Pending Bit 83" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND82   ,Set/Clear Pending Bit 82" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND81   ,Set/Clear Pending Bit 81" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND80   ,Set/Clear Pending Bit 80" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND79   ,Set/Clear Pending Bit 79" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND78   ,Set/Clear Pending Bit 78" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND77   ,Set/Clear Pending Bit 77" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND76   ,Set/Clear Pending Bit 76" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND75   ,Set/Clear Pending Bit 75" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND74   ,Set/Clear Pending Bit 74" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND73   ,Set/Clear Pending Bit 73" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND72   ,Set/Clear Pending Bit 72" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND71   ,Set/Clear Pending Bit 71" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND70   ,Set/Clear Pending Bit 70" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND69   ,Set/Clear Pending Bit 69" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND68   ,Set/Clear Pending Bit 68" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND67   ,Set/Clear Pending Bit 67" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND66   ,Set/Clear Pending Bit 66" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND65   ,Set/Clear Pending Bit 65" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND64   ,Set/Clear Pending Bit 64" "Not pending,Pending"
else
rgroup.long 0x0208++0x03
line.long 0x0 "GICD_SET/CLR_PENDR2,Interrupt Set/Clear Pending Register 2"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x03)
group.long 0x020C++0x03
line.long 0x0 "GICD_SET/CLR_PENDR3,Interrupt Set/Clear Pending Register 3"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND127  ,Set/Clear Pending Bit 127" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND126  ,Set/Clear Pending Bit 126" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND125  ,Set/Clear Pending Bit 125" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND124  ,Set/Clear Pending Bit 124" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND123  ,Set/Clear Pending Bit 123" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND122  ,Set/Clear Pending Bit 122" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND121  ,Set/Clear Pending Bit 121" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND120  ,Set/Clear Pending Bit 120" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND119  ,Set/Clear Pending Bit 119" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND118  ,Set/Clear Pending Bit 118" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND117  ,Set/Clear Pending Bit 117" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND116  ,Set/Clear Pending Bit 116" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND115  ,Set/Clear Pending Bit 115" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND114  ,Set/Clear Pending Bit 114" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND113  ,Set/Clear Pending Bit 113" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND112  ,Set/Clear Pending Bit 112" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND111  ,Set/Clear Pending Bit 111" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND110  ,Set/Clear Pending Bit 110" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND109  ,Set/Clear Pending Bit 109" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND108  ,Set/Clear Pending Bit 108" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND107  ,Set/Clear Pending Bit 107" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND106  ,Set/Clear Pending Bit 106" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND105  ,Set/Clear Pending Bit 105" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND104  ,Set/Clear Pending Bit 104" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND103  ,Set/Clear Pending Bit 103" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND102  ,Set/Clear Pending Bit 102" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND101  ,Set/Clear Pending Bit 101" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND100  ,Set/Clear Pending Bit 100" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND99   ,Set/Clear Pending Bit 99" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND98   ,Set/Clear Pending Bit 98" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND97   ,Set/Clear Pending Bit 97" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND96   ,Set/Clear Pending Bit 96" "Not pending,Pending"
else
rgroup.long 0x020C++0x03
line.long 0x0 "GICD_SET/CLR_PENDR3,Interrupt Set/Clear Pending Register 3"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x04)
group.long 0x0210++0x03
line.long 0x0 "GICD_SET/CLR_PENDR4,Interrupt Set/Clear Pending Register 4"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND159  ,Set/Clear Pending Bit 159" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND158  ,Set/Clear Pending Bit 158" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND157  ,Set/Clear Pending Bit 157" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND156  ,Set/Clear Pending Bit 156" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND155  ,Set/Clear Pending Bit 155" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND154  ,Set/Clear Pending Bit 154" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND153  ,Set/Clear Pending Bit 153" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND152  ,Set/Clear Pending Bit 152" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND151  ,Set/Clear Pending Bit 151" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND150  ,Set/Clear Pending Bit 150" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND149  ,Set/Clear Pending Bit 149" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND148  ,Set/Clear Pending Bit 148" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND147  ,Set/Clear Pending Bit 147" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND146  ,Set/Clear Pending Bit 146" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND145  ,Set/Clear Pending Bit 145" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND144  ,Set/Clear Pending Bit 144" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND143  ,Set/Clear Pending Bit 143" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND142  ,Set/Clear Pending Bit 142" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND141  ,Set/Clear Pending Bit 141" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND140  ,Set/Clear Pending Bit 140" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND139  ,Set/Clear Pending Bit 139" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND138  ,Set/Clear Pending Bit 138" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND137  ,Set/Clear Pending Bit 137" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND136  ,Set/Clear Pending Bit 136" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND135  ,Set/Clear Pending Bit 135" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND134  ,Set/Clear Pending Bit 134" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND133  ,Set/Clear Pending Bit 133" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND132  ,Set/Clear Pending Bit 132" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND131  ,Set/Clear Pending Bit 131" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND130  ,Set/Clear Pending Bit 130" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND129  ,Set/Clear Pending Bit 129" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND128  ,Set/Clear Pending Bit 128" "Not pending,Pending"
else
rgroup.long 0x0210++0x03
line.long 0x0 "GICD_SET/CLR_PENDR4,Interrupt Set/Clear Pending Register 4"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x05)
group.long 0x0214++0x03
line.long 0x0 "GICD_SET/CLR_PENDR5,Interrupt Set/Clear Pending Register 5"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND191  ,Set/Clear Pending Bit 191" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND190  ,Set/Clear Pending Bit 190" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND189  ,Set/Clear Pending Bit 189" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND188  ,Set/Clear Pending Bit 188" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND187  ,Set/Clear Pending Bit 187" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND186  ,Set/Clear Pending Bit 186" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND185  ,Set/Clear Pending Bit 185" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND184  ,Set/Clear Pending Bit 184" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND183  ,Set/Clear Pending Bit 183" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND182  ,Set/Clear Pending Bit 182" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND181  ,Set/Clear Pending Bit 181" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND180  ,Set/Clear Pending Bit 180" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND179  ,Set/Clear Pending Bit 179" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND178  ,Set/Clear Pending Bit 178" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND177  ,Set/Clear Pending Bit 177" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND176  ,Set/Clear Pending Bit 176" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND175  ,Set/Clear Pending Bit 175" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND174  ,Set/Clear Pending Bit 174" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND173  ,Set/Clear Pending Bit 173" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND172  ,Set/Clear Pending Bit 172" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND171  ,Set/Clear Pending Bit 171" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND170  ,Set/Clear Pending Bit 170" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND169  ,Set/Clear Pending Bit 169" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND168  ,Set/Clear Pending Bit 168" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND167  ,Set/Clear Pending Bit 167" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND166  ,Set/Clear Pending Bit 166" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND165  ,Set/Clear Pending Bit 165" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND164  ,Set/Clear Pending Bit 164" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND163  ,Set/Clear Pending Bit 163" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND162  ,Set/Clear Pending Bit 162" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND161  ,Set/Clear Pending Bit 161" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND160  ,Set/Clear Pending Bit 160" "Not pending,Pending"
else
rgroup.long 0x0214++0x03
line.long 0x0 "GICD_SET/CLR_PENDR5,Interrupt Set/Clear Pending Register 5"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x06)
group.long 0x0218++0x03
line.long 0x0 "GICD_SET/CLR_PENDR6,Interrupt Set/Clear Pending Register 6"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND223  ,Set/Clear Pending Bit 223" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND222  ,Set/Clear Pending Bit 222" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND221  ,Set/Clear Pending Bit 221" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND220  ,Set/Clear Pending Bit 220" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND219  ,Set/Clear Pending Bit 219" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND218  ,Set/Clear Pending Bit 218" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND217  ,Set/Clear Pending Bit 217" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND216  ,Set/Clear Pending Bit 216" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND215  ,Set/Clear Pending Bit 215" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND214  ,Set/Clear Pending Bit 214" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND213  ,Set/Clear Pending Bit 213" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND212  ,Set/Clear Pending Bit 212" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND211  ,Set/Clear Pending Bit 211" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND210  ,Set/Clear Pending Bit 210" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND209  ,Set/Clear Pending Bit 209" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND208  ,Set/Clear Pending Bit 208" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND207  ,Set/Clear Pending Bit 207" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND206  ,Set/Clear Pending Bit 206" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND205  ,Set/Clear Pending Bit 205" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND204  ,Set/Clear Pending Bit 204" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND203  ,Set/Clear Pending Bit 203" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND202  ,Set/Clear Pending Bit 202" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND201  ,Set/Clear Pending Bit 201" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND200  ,Set/Clear Pending Bit 200" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND199  ,Set/Clear Pending Bit 199" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND198  ,Set/Clear Pending Bit 198" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND197  ,Set/Clear Pending Bit 197" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND196  ,Set/Clear Pending Bit 196" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND195  ,Set/Clear Pending Bit 195" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND194  ,Set/Clear Pending Bit 194" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND193  ,Set/Clear Pending Bit 193" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND192  ,Set/Clear Pending Bit 192" "Not pending,Pending"
else
rgroup.long 0x0218++0x03
line.long 0x0 "GICD_SET/CLR_PENDR6,Interrupt Set/Clear Pending Register 6"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x07)
group.long 0x021C++0x03
line.long 0x0 "GICD_SET/CLR_PENDR7,Interrupt Set/Clear Pending Register 7"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND255  ,Set/Clear Pending Bit 255" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND254  ,Set/Clear Pending Bit 254" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND253  ,Set/Clear Pending Bit 253" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND252  ,Set/Clear Pending Bit 252" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND251  ,Set/Clear Pending Bit 251" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND250  ,Set/Clear Pending Bit 250" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND249  ,Set/Clear Pending Bit 249" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND248  ,Set/Clear Pending Bit 248" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND247  ,Set/Clear Pending Bit 247" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND246  ,Set/Clear Pending Bit 246" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND245  ,Set/Clear Pending Bit 245" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND244  ,Set/Clear Pending Bit 244" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND243  ,Set/Clear Pending Bit 243" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND242  ,Set/Clear Pending Bit 242" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND241  ,Set/Clear Pending Bit 241" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND240  ,Set/Clear Pending Bit 240" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND239  ,Set/Clear Pending Bit 239" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND238  ,Set/Clear Pending Bit 238" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND237  ,Set/Clear Pending Bit 237" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND236  ,Set/Clear Pending Bit 236" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND235  ,Set/Clear Pending Bit 235" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND234  ,Set/Clear Pending Bit 234" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND233  ,Set/Clear Pending Bit 233" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND232  ,Set/Clear Pending Bit 232" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND231  ,Set/Clear Pending Bit 231" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND230  ,Set/Clear Pending Bit 230" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND229  ,Set/Clear Pending Bit 229" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND228  ,Set/Clear Pending Bit 228" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND227  ,Set/Clear Pending Bit 227" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND226  ,Set/Clear Pending Bit 226" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND225  ,Set/Clear Pending Bit 225" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND224  ,Set/Clear Pending Bit 224" "Not pending,Pending"
else
rgroup.long 0x021C++0x03
line.long 0x0 "GICD_SET/CLR_PENDR7,Interrupt Set/Clear Pending Register 7"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x08)
group.long 0x0220++0x03
line.long 0x0 "GICD_SET/CLR_PENDR8,Interrupt Set/Clear Pending Register 8"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND287  ,Set/Clear Pending Bit 287" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND286  ,Set/Clear Pending Bit 286" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND285  ,Set/Clear Pending Bit 285" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND284  ,Set/Clear Pending Bit 284" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND283  ,Set/Clear Pending Bit 283" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND282  ,Set/Clear Pending Bit 282" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND281  ,Set/Clear Pending Bit 281" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND280  ,Set/Clear Pending Bit 280" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND279  ,Set/Clear Pending Bit 279" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND278  ,Set/Clear Pending Bit 278" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND277  ,Set/Clear Pending Bit 277" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND276  ,Set/Clear Pending Bit 276" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND275  ,Set/Clear Pending Bit 275" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND274  ,Set/Clear Pending Bit 274" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND273  ,Set/Clear Pending Bit 273" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND272  ,Set/Clear Pending Bit 272" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND271  ,Set/Clear Pending Bit 271" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND270  ,Set/Clear Pending Bit 270" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND269  ,Set/Clear Pending Bit 269" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND268  ,Set/Clear Pending Bit 268" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND267  ,Set/Clear Pending Bit 267" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND266  ,Set/Clear Pending Bit 266" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND265  ,Set/Clear Pending Bit 265" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND264  ,Set/Clear Pending Bit 264" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND263  ,Set/Clear Pending Bit 263" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND262  ,Set/Clear Pending Bit 262" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND261  ,Set/Clear Pending Bit 261" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND260  ,Set/Clear Pending Bit 260" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND259  ,Set/Clear Pending Bit 259" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND258  ,Set/Clear Pending Bit 258" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND257  ,Set/Clear Pending Bit 257" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND256  ,Set/Clear Pending Bit 256" "Not pending,Pending"
else
rgroup.long 0x0220++0x03
line.long 0x0 "GICD_SET/CLR_PENDR8,Interrupt Set/Clear Pending Register 8"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x09)
group.long 0x0224++0x03
line.long 0x0 "GICD_SET/CLR_PENDR9,Interrupt Set/Clear Pending Register 9"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND319  ,Set/Clear Pending Bit 319" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND318  ,Set/Clear Pending Bit 318" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND317  ,Set/Clear Pending Bit 317" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND316  ,Set/Clear Pending Bit 316" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND315  ,Set/Clear Pending Bit 315" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND314  ,Set/Clear Pending Bit 314" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND313  ,Set/Clear Pending Bit 313" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND312  ,Set/Clear Pending Bit 312" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND311  ,Set/Clear Pending Bit 311" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND310  ,Set/Clear Pending Bit 310" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND309  ,Set/Clear Pending Bit 309" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND308  ,Set/Clear Pending Bit 308" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND307  ,Set/Clear Pending Bit 307" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND306  ,Set/Clear Pending Bit 306" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND305  ,Set/Clear Pending Bit 305" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND304  ,Set/Clear Pending Bit 304" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND303  ,Set/Clear Pending Bit 303" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND302  ,Set/Clear Pending Bit 302" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND301  ,Set/Clear Pending Bit 301" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND300  ,Set/Clear Pending Bit 300" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND299  ,Set/Clear Pending Bit 299" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND298  ,Set/Clear Pending Bit 298" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND297  ,Set/Clear Pending Bit 297" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND296  ,Set/Clear Pending Bit 296" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND295  ,Set/Clear Pending Bit 295" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND294  ,Set/Clear Pending Bit 294" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND293  ,Set/Clear Pending Bit 293" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND292  ,Set/Clear Pending Bit 292" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND291  ,Set/Clear Pending Bit 291" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND290  ,Set/Clear Pending Bit 290" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND289  ,Set/Clear Pending Bit 289" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND288  ,Set/Clear Pending Bit 288" "Not pending,Pending"
else
rgroup.long 0x0224++0x03
line.long 0x0 "GICD_SET/CLR_PENDR9,Interrupt Set/Clear Pending Register 9"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0A)
group.long 0x0228++0x03
line.long 0x0 "GICD_SET/CLR_PENDR10,Interrupt Set/Clear Pending Register 10"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND351  ,Set/Clear Pending Bit 351" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND350  ,Set/Clear Pending Bit 350" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND349  ,Set/Clear Pending Bit 349" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND348  ,Set/Clear Pending Bit 348" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND347  ,Set/Clear Pending Bit 347" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND346  ,Set/Clear Pending Bit 346" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND345  ,Set/Clear Pending Bit 345" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND344  ,Set/Clear Pending Bit 344" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND343  ,Set/Clear Pending Bit 343" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND342  ,Set/Clear Pending Bit 342" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND341  ,Set/Clear Pending Bit 341" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND340  ,Set/Clear Pending Bit 340" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND339  ,Set/Clear Pending Bit 339" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND338  ,Set/Clear Pending Bit 338" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND337  ,Set/Clear Pending Bit 337" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND336  ,Set/Clear Pending Bit 336" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND335  ,Set/Clear Pending Bit 335" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND334  ,Set/Clear Pending Bit 334" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND333  ,Set/Clear Pending Bit 333" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND332  ,Set/Clear Pending Bit 332" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND331  ,Set/Clear Pending Bit 331" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND330  ,Set/Clear Pending Bit 330" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND329  ,Set/Clear Pending Bit 329" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND328  ,Set/Clear Pending Bit 328" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND327  ,Set/Clear Pending Bit 327" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND326  ,Set/Clear Pending Bit 326" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND325  ,Set/Clear Pending Bit 325" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND324  ,Set/Clear Pending Bit 324" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND323  ,Set/Clear Pending Bit 323" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND322  ,Set/Clear Pending Bit 322" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND321  ,Set/Clear Pending Bit 321" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND320  ,Set/Clear Pending Bit 320" "Not pending,Pending"
else
rgroup.long 0x0228++0x03
line.long 0x0 "GICD_SET/CLR_PENDR10,Interrupt Set/Clear Pending Register 10"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0B)
group.long 0x022C++0x03
line.long 0x0 "GICD_SET/CLR_PENDR11,Interrupt Set/Clear Pending Register 11"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND383  ,Set/Clear Pending Bit 383" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND382  ,Set/Clear Pending Bit 382" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND381  ,Set/Clear Pending Bit 381" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND380  ,Set/Clear Pending Bit 380" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND379  ,Set/Clear Pending Bit 379" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND378  ,Set/Clear Pending Bit 378" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND377  ,Set/Clear Pending Bit 377" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND376  ,Set/Clear Pending Bit 376" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND375  ,Set/Clear Pending Bit 375" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND374  ,Set/Clear Pending Bit 374" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND373  ,Set/Clear Pending Bit 373" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND372  ,Set/Clear Pending Bit 372" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND371  ,Set/Clear Pending Bit 371" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND370  ,Set/Clear Pending Bit 370" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND369  ,Set/Clear Pending Bit 369" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND368  ,Set/Clear Pending Bit 368" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND367  ,Set/Clear Pending Bit 367" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND366  ,Set/Clear Pending Bit 366" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND365  ,Set/Clear Pending Bit 365" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND364  ,Set/Clear Pending Bit 364" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND363  ,Set/Clear Pending Bit 363" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND362  ,Set/Clear Pending Bit 362" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND361  ,Set/Clear Pending Bit 361" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND360  ,Set/Clear Pending Bit 360" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND359  ,Set/Clear Pending Bit 359" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND358  ,Set/Clear Pending Bit 358" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND357  ,Set/Clear Pending Bit 357" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND356  ,Set/Clear Pending Bit 356" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND355  ,Set/Clear Pending Bit 355" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND354  ,Set/Clear Pending Bit 354" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND353  ,Set/Clear Pending Bit 353" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND352  ,Set/Clear Pending Bit 352" "Not pending,Pending"
else
rgroup.long 0x022C++0x03
line.long 0x0 "GICD_SET/CLR_PENDR11,Interrupt Set/Clear Pending Register 11"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0C)
group.long 0x0230++0x03
line.long 0x0 "GICD_SET/CLR_PENDR12,Interrupt Set/Clear Pending Register 12"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND415  ,Set/Clear Pending Bit 415" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND414  ,Set/Clear Pending Bit 414" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND413  ,Set/Clear Pending Bit 413" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND412  ,Set/Clear Pending Bit 412" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND411  ,Set/Clear Pending Bit 411" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND410  ,Set/Clear Pending Bit 410" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND409  ,Set/Clear Pending Bit 409" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND408  ,Set/Clear Pending Bit 408" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND407  ,Set/Clear Pending Bit 407" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND406  ,Set/Clear Pending Bit 406" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND405  ,Set/Clear Pending Bit 405" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND404  ,Set/Clear Pending Bit 404" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND403  ,Set/Clear Pending Bit 403" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND402  ,Set/Clear Pending Bit 402" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND401  ,Set/Clear Pending Bit 401" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND400  ,Set/Clear Pending Bit 400" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND399  ,Set/Clear Pending Bit 399" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND398  ,Set/Clear Pending Bit 398" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND397  ,Set/Clear Pending Bit 397" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND396  ,Set/Clear Pending Bit 396" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND395  ,Set/Clear Pending Bit 395" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND394  ,Set/Clear Pending Bit 394" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND393  ,Set/Clear Pending Bit 393" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND392  ,Set/Clear Pending Bit 392" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND391  ,Set/Clear Pending Bit 391" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND390  ,Set/Clear Pending Bit 390" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND389  ,Set/Clear Pending Bit 389" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND388  ,Set/Clear Pending Bit 388" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND387  ,Set/Clear Pending Bit 387" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND386  ,Set/Clear Pending Bit 386" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND385  ,Set/Clear Pending Bit 385" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND384  ,Set/Clear Pending Bit 384" "Not pending,Pending"
else
rgroup.long 0x0230++0x03
line.long 0x0 "GICD_SET/CLR_PENDR12,Interrupt Set/Clear Pending Register 12"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0D)
group.long 0x0234++0x03
line.long 0x0 "GICD_SET/CLR_PENDR13,Interrupt Set/Clear Pending Register 13"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND447  ,Set/Clear Pending Bit 447" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND446  ,Set/Clear Pending Bit 446" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND445  ,Set/Clear Pending Bit 445" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND444  ,Set/Clear Pending Bit 444" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND443  ,Set/Clear Pending Bit 443" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND442  ,Set/Clear Pending Bit 442" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND441  ,Set/Clear Pending Bit 441" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND440  ,Set/Clear Pending Bit 440" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND439  ,Set/Clear Pending Bit 439" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND438  ,Set/Clear Pending Bit 438" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND437  ,Set/Clear Pending Bit 437" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND436  ,Set/Clear Pending Bit 436" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND435  ,Set/Clear Pending Bit 435" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND434  ,Set/Clear Pending Bit 434" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND433  ,Set/Clear Pending Bit 433" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND432  ,Set/Clear Pending Bit 432" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND431  ,Set/Clear Pending Bit 431" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND430  ,Set/Clear Pending Bit 430" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND429  ,Set/Clear Pending Bit 429" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND428  ,Set/Clear Pending Bit 428" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND427  ,Set/Clear Pending Bit 427" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND426  ,Set/Clear Pending Bit 426" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND425  ,Set/Clear Pending Bit 425" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND424  ,Set/Clear Pending Bit 424" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND423  ,Set/Clear Pending Bit 423" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND422  ,Set/Clear Pending Bit 422" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND421  ,Set/Clear Pending Bit 421" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND420  ,Set/Clear Pending Bit 420" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND419  ,Set/Clear Pending Bit 419" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND418  ,Set/Clear Pending Bit 418" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND417  ,Set/Clear Pending Bit 417" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND416  ,Set/Clear Pending Bit 416" "Not pending,Pending"
else
rgroup.long 0x0234++0x03
line.long 0x0 "GICD_SET/CLR_PENDR13,Interrupt Set/Clear Pending Register 13"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0E)
group.long 0x0238++0x03
line.long 0x0 "GICD_SET/CLR_PENDR14,Interrupt Set/Clear Pending Register 14"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND479  ,Set/Clear Pending Bit 479" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND478  ,Set/Clear Pending Bit 478" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND477  ,Set/Clear Pending Bit 477" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND476  ,Set/Clear Pending Bit 476" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND475  ,Set/Clear Pending Bit 475" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND474  ,Set/Clear Pending Bit 474" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND473  ,Set/Clear Pending Bit 473" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND472  ,Set/Clear Pending Bit 472" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND471  ,Set/Clear Pending Bit 471" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND470  ,Set/Clear Pending Bit 470" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND469  ,Set/Clear Pending Bit 469" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND468  ,Set/Clear Pending Bit 468" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND467  ,Set/Clear Pending Bit 467" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND466  ,Set/Clear Pending Bit 466" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND465  ,Set/Clear Pending Bit 465" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND464  ,Set/Clear Pending Bit 464" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND463  ,Set/Clear Pending Bit 463" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND462  ,Set/Clear Pending Bit 462" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND461  ,Set/Clear Pending Bit 461" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND460  ,Set/Clear Pending Bit 460" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND459  ,Set/Clear Pending Bit 459" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND458  ,Set/Clear Pending Bit 458" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND457  ,Set/Clear Pending Bit 457" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND456  ,Set/Clear Pending Bit 456" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND455  ,Set/Clear Pending Bit 455" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND454  ,Set/Clear Pending Bit 454" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND453  ,Set/Clear Pending Bit 453" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND452  ,Set/Clear Pending Bit 452" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND451  ,Set/Clear Pending Bit 451" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND450  ,Set/Clear Pending Bit 450" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND449  ,Set/Clear Pending Bit 449" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND448  ,Set/Clear Pending Bit 448" "Not pending,Pending"
else
rgroup.long 0x0238++0x03
line.long 0x0 "GICD_SET/CLR_PENDR14,Interrupt Set/Clear Pending Register 14"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0F)
group.long 0x023C++0x03
line.long 0x0 "GICD_SET/CLR_PENDR15,Interrupt Set/Clear Pending Register 15"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND511  ,Set/Clear Pending Bit 511" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND510  ,Set/Clear Pending Bit 510" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND509  ,Set/Clear Pending Bit 509" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND508  ,Set/Clear Pending Bit 508" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND507  ,Set/Clear Pending Bit 507" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND506  ,Set/Clear Pending Bit 506" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND505  ,Set/Clear Pending Bit 505" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND504  ,Set/Clear Pending Bit 504" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND503  ,Set/Clear Pending Bit 503" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND502  ,Set/Clear Pending Bit 502" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND501  ,Set/Clear Pending Bit 501" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND500  ,Set/Clear Pending Bit 500" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND499  ,Set/Clear Pending Bit 499" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND498  ,Set/Clear Pending Bit 498" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND497  ,Set/Clear Pending Bit 497" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND496  ,Set/Clear Pending Bit 496" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND495  ,Set/Clear Pending Bit 495" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND494  ,Set/Clear Pending Bit 494" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND493  ,Set/Clear Pending Bit 493" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND492  ,Set/Clear Pending Bit 492" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND491  ,Set/Clear Pending Bit 491" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND490  ,Set/Clear Pending Bit 490" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND489  ,Set/Clear Pending Bit 489" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND488  ,Set/Clear Pending Bit 488" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND487  ,Set/Clear Pending Bit 487" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND486  ,Set/Clear Pending Bit 486" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND485  ,Set/Clear Pending Bit 485" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND484  ,Set/Clear Pending Bit 484" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND483  ,Set/Clear Pending Bit 483" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND482  ,Set/Clear Pending Bit 482" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND481  ,Set/Clear Pending Bit 481" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND480  ,Set/Clear Pending Bit 480" "Not pending,Pending"
else
rgroup.long 0x023C++0x03
line.long 0x0 "GICD_SET/CLR_PENDR15,Interrupt Set/Clear Pending Register 15"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x10)
group.long 0x0240++0x03
line.long 0x0 "GICD_SET/CLR_PENDR16,Interrupt Set/Clear Pending Register 16"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND543  ,Set/Clear Pending Bit 543" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND542  ,Set/Clear Pending Bit 542" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND541  ,Set/Clear Pending Bit 541" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND540  ,Set/Clear Pending Bit 540" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND539  ,Set/Clear Pending Bit 539" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND538  ,Set/Clear Pending Bit 538" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND537  ,Set/Clear Pending Bit 537" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND536  ,Set/Clear Pending Bit 536" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND535  ,Set/Clear Pending Bit 535" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND534  ,Set/Clear Pending Bit 534" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND533  ,Set/Clear Pending Bit 533" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND532  ,Set/Clear Pending Bit 532" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND531  ,Set/Clear Pending Bit 531" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND530  ,Set/Clear Pending Bit 530" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND529  ,Set/Clear Pending Bit 529" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND528  ,Set/Clear Pending Bit 528" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND527  ,Set/Clear Pending Bit 527" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND526  ,Set/Clear Pending Bit 526" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND525  ,Set/Clear Pending Bit 525" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND524  ,Set/Clear Pending Bit 524" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND523  ,Set/Clear Pending Bit 523" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND522  ,Set/Clear Pending Bit 522" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND521  ,Set/Clear Pending Bit 521" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND520  ,Set/Clear Pending Bit 520" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND519  ,Set/Clear Pending Bit 519" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND518  ,Set/Clear Pending Bit 518" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND517  ,Set/Clear Pending Bit 517" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND516  ,Set/Clear Pending Bit 516" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND515  ,Set/Clear Pending Bit 515" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND514  ,Set/Clear Pending Bit 514" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND513  ,Set/Clear Pending Bit 513" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND512  ,Set/Clear Pending Bit 512" "Not pending,Pending"
else
rgroup.long 0x0240++0x03
line.long 0x0 "GICD_SET/CLR_PENDR16,Interrupt Set/Clear Pending Register 16"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x11)
group.long 0x0244++0x03
line.long 0x0 "GICD_SET/CLR_PENDR17,Interrupt Set/Clear Pending Register 17"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND575  ,Set/Clear Pending Bit 575" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND574  ,Set/Clear Pending Bit 574" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND573  ,Set/Clear Pending Bit 573" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND572  ,Set/Clear Pending Bit 572" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND571  ,Set/Clear Pending Bit 571" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND570  ,Set/Clear Pending Bit 570" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND569  ,Set/Clear Pending Bit 569" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND568  ,Set/Clear Pending Bit 568" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND567  ,Set/Clear Pending Bit 567" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND566  ,Set/Clear Pending Bit 566" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND565  ,Set/Clear Pending Bit 565" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND564  ,Set/Clear Pending Bit 564" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND563  ,Set/Clear Pending Bit 563" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND562  ,Set/Clear Pending Bit 562" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND561  ,Set/Clear Pending Bit 561" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND560  ,Set/Clear Pending Bit 560" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND559  ,Set/Clear Pending Bit 559" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND558  ,Set/Clear Pending Bit 558" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND557  ,Set/Clear Pending Bit 557" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND556  ,Set/Clear Pending Bit 556" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND555  ,Set/Clear Pending Bit 555" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND554  ,Set/Clear Pending Bit 554" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND553  ,Set/Clear Pending Bit 553" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND552  ,Set/Clear Pending Bit 552" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND551  ,Set/Clear Pending Bit 551" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND550  ,Set/Clear Pending Bit 550" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND549  ,Set/Clear Pending Bit 549" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND548  ,Set/Clear Pending Bit 548" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND547  ,Set/Clear Pending Bit 547" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND546  ,Set/Clear Pending Bit 546" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND545  ,Set/Clear Pending Bit 545" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND544  ,Set/Clear Pending Bit 544" "Not pending,Pending"
else
rgroup.long 0x0244++0x03
line.long 0x0 "GICD_SET/CLR_PENDR17,Interrupt Set/Clear Pending Register 17"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x12)
group.long 0x0248++0x03
line.long 0x0 "GICD_SET/CLR_PENDR18,Interrupt Set/Clear Pending Register 18"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND607  ,Set/Clear Pending Bit 607" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND606  ,Set/Clear Pending Bit 606" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND605  ,Set/Clear Pending Bit 605" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND604  ,Set/Clear Pending Bit 604" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND603  ,Set/Clear Pending Bit 603" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND602  ,Set/Clear Pending Bit 602" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND601  ,Set/Clear Pending Bit 601" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND600  ,Set/Clear Pending Bit 600" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND599  ,Set/Clear Pending Bit 599" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND598  ,Set/Clear Pending Bit 598" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND597  ,Set/Clear Pending Bit 597" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND596  ,Set/Clear Pending Bit 596" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND595  ,Set/Clear Pending Bit 595" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND594  ,Set/Clear Pending Bit 594" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND593  ,Set/Clear Pending Bit 593" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND592  ,Set/Clear Pending Bit 592" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND591  ,Set/Clear Pending Bit 591" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND590  ,Set/Clear Pending Bit 590" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND589  ,Set/Clear Pending Bit 589" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND588  ,Set/Clear Pending Bit 588" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND587  ,Set/Clear Pending Bit 587" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND586  ,Set/Clear Pending Bit 586" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND585  ,Set/Clear Pending Bit 585" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND584  ,Set/Clear Pending Bit 584" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND583  ,Set/Clear Pending Bit 583" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND582  ,Set/Clear Pending Bit 582" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND581  ,Set/Clear Pending Bit 581" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND580  ,Set/Clear Pending Bit 580" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND579  ,Set/Clear Pending Bit 579" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND578  ,Set/Clear Pending Bit 578" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND577  ,Set/Clear Pending Bit 577" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND576  ,Set/Clear Pending Bit 576" "Not pending,Pending"
else
rgroup.long 0x0248++0x03
line.long 0x0 "GICD_SET/CLR_PENDR18,Interrupt Set/Clear Pending Register 18"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x13)
group.long 0x024C++0x03
line.long 0x0 "GICD_SET/CLR_PENDR19,Interrupt Set/Clear Pending Register 19"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND639  ,Set/Clear Pending Bit 639" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND638  ,Set/Clear Pending Bit 638" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND637  ,Set/Clear Pending Bit 637" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND636  ,Set/Clear Pending Bit 636" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND635  ,Set/Clear Pending Bit 635" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND634  ,Set/Clear Pending Bit 634" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND633  ,Set/Clear Pending Bit 633" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND632  ,Set/Clear Pending Bit 632" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND631  ,Set/Clear Pending Bit 631" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND630  ,Set/Clear Pending Bit 630" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND629  ,Set/Clear Pending Bit 629" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND628  ,Set/Clear Pending Bit 628" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND627  ,Set/Clear Pending Bit 627" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND626  ,Set/Clear Pending Bit 626" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND625  ,Set/Clear Pending Bit 625" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND624  ,Set/Clear Pending Bit 624" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND623  ,Set/Clear Pending Bit 623" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND622  ,Set/Clear Pending Bit 622" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND621  ,Set/Clear Pending Bit 621" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND620  ,Set/Clear Pending Bit 620" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND619  ,Set/Clear Pending Bit 619" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND618  ,Set/Clear Pending Bit 618" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND617  ,Set/Clear Pending Bit 617" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND616  ,Set/Clear Pending Bit 616" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND615  ,Set/Clear Pending Bit 615" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND614  ,Set/Clear Pending Bit 614" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND613  ,Set/Clear Pending Bit 613" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND612  ,Set/Clear Pending Bit 612" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND611  ,Set/Clear Pending Bit 611" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND610  ,Set/Clear Pending Bit 610" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND609  ,Set/Clear Pending Bit 609" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND608  ,Set/Clear Pending Bit 608" "Not pending,Pending"
else
rgroup.long 0x024C++0x03
line.long 0x0 "GICD_SET/CLR_PENDR19,Interrupt Set/Clear Pending Register 19"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x14)
group.long 0x0250++0x03
line.long 0x0 "GICD_SET/CLR_PENDR20,Interrupt Set/Clear Pending Register 20"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND671  ,Set/Clear Pending Bit 671" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND670  ,Set/Clear Pending Bit 670" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND669  ,Set/Clear Pending Bit 669" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND668  ,Set/Clear Pending Bit 668" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND667  ,Set/Clear Pending Bit 667" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND666  ,Set/Clear Pending Bit 666" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND665  ,Set/Clear Pending Bit 665" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND664  ,Set/Clear Pending Bit 664" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND663  ,Set/Clear Pending Bit 663" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND662  ,Set/Clear Pending Bit 662" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND661  ,Set/Clear Pending Bit 661" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND660  ,Set/Clear Pending Bit 660" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND659  ,Set/Clear Pending Bit 659" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND658  ,Set/Clear Pending Bit 658" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND657  ,Set/Clear Pending Bit 657" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND656  ,Set/Clear Pending Bit 656" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND655  ,Set/Clear Pending Bit 655" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND654  ,Set/Clear Pending Bit 654" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND653  ,Set/Clear Pending Bit 653" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND652  ,Set/Clear Pending Bit 652" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND651  ,Set/Clear Pending Bit 651" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND650  ,Set/Clear Pending Bit 650" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND649  ,Set/Clear Pending Bit 649" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND648  ,Set/Clear Pending Bit 648" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND647  ,Set/Clear Pending Bit 647" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND646  ,Set/Clear Pending Bit 646" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND645  ,Set/Clear Pending Bit 645" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND644  ,Set/Clear Pending Bit 644" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND643  ,Set/Clear Pending Bit 643" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND642  ,Set/Clear Pending Bit 642" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND641  ,Set/Clear Pending Bit 641" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND640  ,Set/Clear Pending Bit 640" "Not pending,Pending"
else
rgroup.long 0x0250++0x03
line.long 0x0 "GICD_SET/CLR_PENDR20,Interrupt Set/Clear Pending Register 20"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x15)
group.long 0x0254++0x03
line.long 0x0 "GICD_SET/CLR_PENDR21,Interrupt Set/Clear Pending Register 21"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND703  ,Set/Clear Pending Bit 703" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND702  ,Set/Clear Pending Bit 702" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND701  ,Set/Clear Pending Bit 701" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND700  ,Set/Clear Pending Bit 700" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND699  ,Set/Clear Pending Bit 699" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND698  ,Set/Clear Pending Bit 698" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND697  ,Set/Clear Pending Bit 697" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND696  ,Set/Clear Pending Bit 696" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND695  ,Set/Clear Pending Bit 695" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND694  ,Set/Clear Pending Bit 694" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND693  ,Set/Clear Pending Bit 693" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND692  ,Set/Clear Pending Bit 692" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND691  ,Set/Clear Pending Bit 691" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND690  ,Set/Clear Pending Bit 690" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND689  ,Set/Clear Pending Bit 689" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND688  ,Set/Clear Pending Bit 688" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND687  ,Set/Clear Pending Bit 687" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND686  ,Set/Clear Pending Bit 686" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND685  ,Set/Clear Pending Bit 685" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND684  ,Set/Clear Pending Bit 684" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND683  ,Set/Clear Pending Bit 683" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND682  ,Set/Clear Pending Bit 682" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND681  ,Set/Clear Pending Bit 681" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND680  ,Set/Clear Pending Bit 680" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND679  ,Set/Clear Pending Bit 679" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND678  ,Set/Clear Pending Bit 678" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND677  ,Set/Clear Pending Bit 677" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND676  ,Set/Clear Pending Bit 676" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND675  ,Set/Clear Pending Bit 675" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND674  ,Set/Clear Pending Bit 674" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND673  ,Set/Clear Pending Bit 673" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND672  ,Set/Clear Pending Bit 672" "Not pending,Pending"
else
rgroup.long 0x0254++0x03
line.long 0x0 "GICD_SET/CLR_PENDR21,Interrupt Set/Clear Pending Register 21"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x16)
group.long 0x0258++0x03
line.long 0x0 "GICD_SET/CLR_PENDR22,Interrupt Set/Clear Pending Register 22"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND735  ,Set/Clear Pending Bit 735" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND734  ,Set/Clear Pending Bit 734" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND733  ,Set/Clear Pending Bit 733" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND732  ,Set/Clear Pending Bit 732" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND731  ,Set/Clear Pending Bit 731" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND730  ,Set/Clear Pending Bit 730" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND729  ,Set/Clear Pending Bit 729" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND728  ,Set/Clear Pending Bit 728" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND727  ,Set/Clear Pending Bit 727" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND726  ,Set/Clear Pending Bit 726" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND725  ,Set/Clear Pending Bit 725" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND724  ,Set/Clear Pending Bit 724" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND723  ,Set/Clear Pending Bit 723" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND722  ,Set/Clear Pending Bit 722" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND721  ,Set/Clear Pending Bit 721" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND720  ,Set/Clear Pending Bit 720" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND719  ,Set/Clear Pending Bit 719" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND718  ,Set/Clear Pending Bit 718" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND717  ,Set/Clear Pending Bit 717" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND716  ,Set/Clear Pending Bit 716" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND715  ,Set/Clear Pending Bit 715" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND714  ,Set/Clear Pending Bit 714" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND713  ,Set/Clear Pending Bit 713" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND712  ,Set/Clear Pending Bit 712" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND711  ,Set/Clear Pending Bit 711" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND710  ,Set/Clear Pending Bit 710" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND709  ,Set/Clear Pending Bit 709" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND708  ,Set/Clear Pending Bit 708" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND707  ,Set/Clear Pending Bit 707" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND706  ,Set/Clear Pending Bit 706" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND705  ,Set/Clear Pending Bit 705" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND704  ,Set/Clear Pending Bit 704" "Not pending,Pending"
else
rgroup.long 0x0258++0x03
line.long 0x0 "GICD_SET/CLR_PENDR22,Interrupt Set/Clear Pending Register 22"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x17)
group.long 0x025C++0x03
line.long 0x0 "GICD_SET/CLR_PENDR23,Interrupt Set/Clear Pending Register 23"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND767  ,Set/Clear Pending Bit 767" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND766  ,Set/Clear Pending Bit 766" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND765  ,Set/Clear Pending Bit 765" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND764  ,Set/Clear Pending Bit 764" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND763  ,Set/Clear Pending Bit 763" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND762  ,Set/Clear Pending Bit 762" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND761  ,Set/Clear Pending Bit 761" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND760  ,Set/Clear Pending Bit 760" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND759  ,Set/Clear Pending Bit 759" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND758  ,Set/Clear Pending Bit 758" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND757  ,Set/Clear Pending Bit 757" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND756  ,Set/Clear Pending Bit 756" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND755  ,Set/Clear Pending Bit 755" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND754  ,Set/Clear Pending Bit 754" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND753  ,Set/Clear Pending Bit 753" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND752  ,Set/Clear Pending Bit 752" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND751  ,Set/Clear Pending Bit 751" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND750  ,Set/Clear Pending Bit 750" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND749  ,Set/Clear Pending Bit 749" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND748  ,Set/Clear Pending Bit 748" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND747  ,Set/Clear Pending Bit 747" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND746  ,Set/Clear Pending Bit 746" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND745  ,Set/Clear Pending Bit 745" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND744  ,Set/Clear Pending Bit 744" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND743  ,Set/Clear Pending Bit 743" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND742  ,Set/Clear Pending Bit 742" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND741  ,Set/Clear Pending Bit 741" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND740  ,Set/Clear Pending Bit 740" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND739  ,Set/Clear Pending Bit 739" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND738  ,Set/Clear Pending Bit 738" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND737  ,Set/Clear Pending Bit 737" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND736  ,Set/Clear Pending Bit 736" "Not pending,Pending"
else
rgroup.long 0x025C++0x03
line.long 0x0 "GICD_SET/CLR_PENDR23,Interrupt Set/Clear Pending Register 23"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x18)
group.long 0x0260++0x03
line.long 0x0 "GICD_SET/CLR_PENDR24,Interrupt Set/Clear Pending Register 24"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND799  ,Set/Clear Pending Bit 799" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND798  ,Set/Clear Pending Bit 798" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND797  ,Set/Clear Pending Bit 797" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND796  ,Set/Clear Pending Bit 796" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND795  ,Set/Clear Pending Bit 795" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND794  ,Set/Clear Pending Bit 794" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND793  ,Set/Clear Pending Bit 793" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND792  ,Set/Clear Pending Bit 792" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND791  ,Set/Clear Pending Bit 791" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND790  ,Set/Clear Pending Bit 790" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND789  ,Set/Clear Pending Bit 789" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND788  ,Set/Clear Pending Bit 788" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND787  ,Set/Clear Pending Bit 787" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND786  ,Set/Clear Pending Bit 786" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND785  ,Set/Clear Pending Bit 785" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND784  ,Set/Clear Pending Bit 784" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND783  ,Set/Clear Pending Bit 783" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND782  ,Set/Clear Pending Bit 782" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND781  ,Set/Clear Pending Bit 781" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND780  ,Set/Clear Pending Bit 780" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND779  ,Set/Clear Pending Bit 779" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND778  ,Set/Clear Pending Bit 778" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND777  ,Set/Clear Pending Bit 777" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND776  ,Set/Clear Pending Bit 776" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND775  ,Set/Clear Pending Bit 775" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND774  ,Set/Clear Pending Bit 774" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND773  ,Set/Clear Pending Bit 773" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND772  ,Set/Clear Pending Bit 772" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND771  ,Set/Clear Pending Bit 771" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND770  ,Set/Clear Pending Bit 770" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND769  ,Set/Clear Pending Bit 769" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND768  ,Set/Clear Pending Bit 768" "Not pending,Pending"
else
rgroup.long 0x0260++0x03
line.long 0x0 "GICD_SET/CLR_PENDR24,Interrupt Set/Clear Pending Register 24"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x19)
group.long 0x0264++0x03
line.long 0x0 "GICD_SET/CLR_PENDR25,Interrupt Set/Clear Pending Register 25"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND831  ,Set/Clear Pending Bit 831" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND830  ,Set/Clear Pending Bit 830" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND829  ,Set/Clear Pending Bit 829" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND828  ,Set/Clear Pending Bit 828" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND827  ,Set/Clear Pending Bit 827" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND826  ,Set/Clear Pending Bit 826" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND825  ,Set/Clear Pending Bit 825" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND824  ,Set/Clear Pending Bit 824" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND823  ,Set/Clear Pending Bit 823" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND822  ,Set/Clear Pending Bit 822" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND821  ,Set/Clear Pending Bit 821" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND820  ,Set/Clear Pending Bit 820" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND819  ,Set/Clear Pending Bit 819" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND818  ,Set/Clear Pending Bit 818" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND817  ,Set/Clear Pending Bit 817" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND816  ,Set/Clear Pending Bit 816" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND815  ,Set/Clear Pending Bit 815" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND814  ,Set/Clear Pending Bit 814" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND813  ,Set/Clear Pending Bit 813" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND812  ,Set/Clear Pending Bit 812" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND811  ,Set/Clear Pending Bit 811" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND810  ,Set/Clear Pending Bit 810" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND809  ,Set/Clear Pending Bit 809" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND808  ,Set/Clear Pending Bit 808" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND807  ,Set/Clear Pending Bit 807" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND806  ,Set/Clear Pending Bit 806" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND805  ,Set/Clear Pending Bit 805" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND804  ,Set/Clear Pending Bit 804" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND803  ,Set/Clear Pending Bit 803" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND802  ,Set/Clear Pending Bit 802" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND801  ,Set/Clear Pending Bit 801" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND800  ,Set/Clear Pending Bit 800" "Not pending,Pending"
else
rgroup.long 0x0264++0x03
line.long 0x0 "GICD_SET/CLR_PENDR25,Interrupt Set/Clear Pending Register 25"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1A)
group.long 0x0268++0x03
line.long 0x0 "GICD_SET/CLR_PENDR26,Interrupt Set/Clear Pending Register 26"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND863  ,Set/Clear Pending Bit 863" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND862  ,Set/Clear Pending Bit 862" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND861  ,Set/Clear Pending Bit 861" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND860  ,Set/Clear Pending Bit 860" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND859  ,Set/Clear Pending Bit 859" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND858  ,Set/Clear Pending Bit 858" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND857  ,Set/Clear Pending Bit 857" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND856  ,Set/Clear Pending Bit 856" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND855  ,Set/Clear Pending Bit 855" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND854  ,Set/Clear Pending Bit 854" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND853  ,Set/Clear Pending Bit 853" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND852  ,Set/Clear Pending Bit 852" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND851  ,Set/Clear Pending Bit 851" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND850  ,Set/Clear Pending Bit 850" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND849  ,Set/Clear Pending Bit 849" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND848  ,Set/Clear Pending Bit 848" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND847  ,Set/Clear Pending Bit 847" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND846  ,Set/Clear Pending Bit 846" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND845  ,Set/Clear Pending Bit 845" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND844  ,Set/Clear Pending Bit 844" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND843  ,Set/Clear Pending Bit 843" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND842  ,Set/Clear Pending Bit 842" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND841  ,Set/Clear Pending Bit 841" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND840  ,Set/Clear Pending Bit 840" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND839  ,Set/Clear Pending Bit 839" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND838  ,Set/Clear Pending Bit 838" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND837  ,Set/Clear Pending Bit 837" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND836  ,Set/Clear Pending Bit 836" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND835  ,Set/Clear Pending Bit 835" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND834  ,Set/Clear Pending Bit 834" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND833  ,Set/Clear Pending Bit 833" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND832  ,Set/Clear Pending Bit 832" "Not pending,Pending"
else
rgroup.long 0x0268++0x03
line.long 0x0 "GICD_SET/CLR_PENDR26,Interrupt Set/Clear Pending Register 26"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1B)
group.long 0x026C++0x03
line.long 0x0 "GICD_SET/CLR_PENDR27,Interrupt Set/Clear Pending Register 27"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND895  ,Set/Clear Pending Bit 895" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND894  ,Set/Clear Pending Bit 894" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND893  ,Set/Clear Pending Bit 893" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND892  ,Set/Clear Pending Bit 892" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND891  ,Set/Clear Pending Bit 891" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND890  ,Set/Clear Pending Bit 890" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND889  ,Set/Clear Pending Bit 889" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND888  ,Set/Clear Pending Bit 888" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND887  ,Set/Clear Pending Bit 887" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND886  ,Set/Clear Pending Bit 886" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND885  ,Set/Clear Pending Bit 885" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND884  ,Set/Clear Pending Bit 884" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND883  ,Set/Clear Pending Bit 883" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND882  ,Set/Clear Pending Bit 882" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND881  ,Set/Clear Pending Bit 881" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND880  ,Set/Clear Pending Bit 880" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND879  ,Set/Clear Pending Bit 879" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND878  ,Set/Clear Pending Bit 878" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND877  ,Set/Clear Pending Bit 877" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND876  ,Set/Clear Pending Bit 876" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND875  ,Set/Clear Pending Bit 875" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND874  ,Set/Clear Pending Bit 874" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND873  ,Set/Clear Pending Bit 873" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND872  ,Set/Clear Pending Bit 872" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND871  ,Set/Clear Pending Bit 871" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND870  ,Set/Clear Pending Bit 870" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND869  ,Set/Clear Pending Bit 869" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND868  ,Set/Clear Pending Bit 868" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND867  ,Set/Clear Pending Bit 867" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND866  ,Set/Clear Pending Bit 866" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND865  ,Set/Clear Pending Bit 865" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND864  ,Set/Clear Pending Bit 864" "Not pending,Pending"
else
rgroup.long 0x026C++0x03
line.long 0x0 "GICD_SET/CLR_PENDR27,Interrupt Set/Clear Pending Register 27"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1C)
group.long 0x0270++0x03
line.long 0x0 "GICD_SET/CLR_PENDR28,Interrupt Set/Clear Pending Register 28"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND927  ,Set/Clear Pending Bit 927" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND926  ,Set/Clear Pending Bit 926" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND925  ,Set/Clear Pending Bit 925" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND924  ,Set/Clear Pending Bit 924" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND923  ,Set/Clear Pending Bit 923" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND922  ,Set/Clear Pending Bit 922" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND921  ,Set/Clear Pending Bit 921" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND920  ,Set/Clear Pending Bit 920" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND919  ,Set/Clear Pending Bit 919" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND918  ,Set/Clear Pending Bit 918" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND917  ,Set/Clear Pending Bit 917" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND916  ,Set/Clear Pending Bit 916" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND915  ,Set/Clear Pending Bit 915" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND914  ,Set/Clear Pending Bit 914" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND913  ,Set/Clear Pending Bit 913" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND912  ,Set/Clear Pending Bit 912" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND911  ,Set/Clear Pending Bit 911" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND910  ,Set/Clear Pending Bit 910" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND909  ,Set/Clear Pending Bit 909" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND908  ,Set/Clear Pending Bit 908" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND907  ,Set/Clear Pending Bit 907" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND906  ,Set/Clear Pending Bit 906" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND905  ,Set/Clear Pending Bit 905" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND904  ,Set/Clear Pending Bit 904" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND903  ,Set/Clear Pending Bit 903" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND902  ,Set/Clear Pending Bit 902" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND901  ,Set/Clear Pending Bit 901" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND900  ,Set/Clear Pending Bit 900" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND899  ,Set/Clear Pending Bit 899" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND898  ,Set/Clear Pending Bit 898" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND897  ,Set/Clear Pending Bit 897" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND896  ,Set/Clear Pending Bit 896" "Not pending,Pending"
else
rgroup.long 0x0270++0x03
line.long 0x0 "GICD_SET/CLR_PENDR28,Interrupt Set/Clear Pending Register 28"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1D)
group.long 0x0274++0x03
line.long 0x0 "GICD_SET/CLR_PENDR29,Interrupt Set/Clear Pending Register 29"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND959  ,Set/Clear Pending Bit 959" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND958  ,Set/Clear Pending Bit 958" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND957  ,Set/Clear Pending Bit 957" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND956  ,Set/Clear Pending Bit 956" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND955  ,Set/Clear Pending Bit 955" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND954  ,Set/Clear Pending Bit 954" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND953  ,Set/Clear Pending Bit 953" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND952  ,Set/Clear Pending Bit 952" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND951  ,Set/Clear Pending Bit 951" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND950  ,Set/Clear Pending Bit 950" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND949  ,Set/Clear Pending Bit 949" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND948  ,Set/Clear Pending Bit 948" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND947  ,Set/Clear Pending Bit 947" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND946  ,Set/Clear Pending Bit 946" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND945  ,Set/Clear Pending Bit 945" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND944  ,Set/Clear Pending Bit 944" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND943  ,Set/Clear Pending Bit 943" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND942  ,Set/Clear Pending Bit 942" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND941  ,Set/Clear Pending Bit 941" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND940  ,Set/Clear Pending Bit 940" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND939  ,Set/Clear Pending Bit 939" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND938  ,Set/Clear Pending Bit 938" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND937  ,Set/Clear Pending Bit 937" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND936  ,Set/Clear Pending Bit 936" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND935  ,Set/Clear Pending Bit 935" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND934  ,Set/Clear Pending Bit 934" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND933  ,Set/Clear Pending Bit 933" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND932  ,Set/Clear Pending Bit 932" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND931  ,Set/Clear Pending Bit 931" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND930  ,Set/Clear Pending Bit 930" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND929  ,Set/Clear Pending Bit 929" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND928  ,Set/Clear Pending Bit 928" "Not pending,Pending"
else
rgroup.long 0x0274++0x03
line.long 0x0 "GICD_SET/CLR_PENDR29,Interrupt Set/Clear Pending Register 29"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1E)
group.long 0x0278++0x03
line.long 0x0 "GICD_SET/CLR_PENDR30,Interrupt Set/Clear Pending Register 30"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND991  ,Set/Clear Pending Bit 991" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND990  ,Set/Clear Pending Bit 990" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND989  ,Set/Clear Pending Bit 989" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND988  ,Set/Clear Pending Bit 988" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND987  ,Set/Clear Pending Bit 987" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND986  ,Set/Clear Pending Bit 986" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND985  ,Set/Clear Pending Bit 985" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND984  ,Set/Clear Pending Bit 984" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND983  ,Set/Clear Pending Bit 983" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND982  ,Set/Clear Pending Bit 982" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND981  ,Set/Clear Pending Bit 981" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND980  ,Set/Clear Pending Bit 980" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND979  ,Set/Clear Pending Bit 979" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND978  ,Set/Clear Pending Bit 978" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND977  ,Set/Clear Pending Bit 977" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND976  ,Set/Clear Pending Bit 976" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND975  ,Set/Clear Pending Bit 975" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND974  ,Set/Clear Pending Bit 974" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND973  ,Set/Clear Pending Bit 973" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND972  ,Set/Clear Pending Bit 972" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND971  ,Set/Clear Pending Bit 971" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND970  ,Set/Clear Pending Bit 970" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND969  ,Set/Clear Pending Bit 969" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND968  ,Set/Clear Pending Bit 968" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND967  ,Set/Clear Pending Bit 967" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND966  ,Set/Clear Pending Bit 966" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND965  ,Set/Clear Pending Bit 965" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND964  ,Set/Clear Pending Bit 964" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND963  ,Set/Clear Pending Bit 963" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND962  ,Set/Clear Pending Bit 962" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND961  ,Set/Clear Pending Bit 961" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND960  ,Set/Clear Pending Bit 960" "Not pending,Pending"
else
rgroup.long 0x0278++0x03
line.long 0x0 "GICD_SET/CLR_PENDR30,Interrupt Set/Clear Pending Register 30"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)==0x1F)
group.long 0x027C++0x03
line.long 0x0 "GICD_SET/CLR_PENDR31,Interrupt Set/Clear Pending Register 31"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND1019 ,Set/Clear Pending Bit 1019" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND1018 ,Set/Clear Pending Bit 1018" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND1017 ,Set/Clear Pending Bit 1017" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND1016 ,Set/Clear Pending Bit 1016" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND1015 ,Set/Clear Pending Bit 1015" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND1014 ,Set/Clear Pending Bit 1014" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND1013 ,Set/Clear Pending Bit 1013" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND1012 ,Set/Clear Pending Bit 1012" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND1011 ,Set/Clear Pending Bit 1011" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND1010 ,Set/Clear Pending Bit 1010" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND1009 ,Set/Clear Pending Bit 1009" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND1008 ,Set/Clear Pending Bit 1008" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND1007 ,Set/Clear Pending Bit 1007" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND1006 ,Set/Clear Pending Bit 1006" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND1005 ,Set/Clear Pending Bit 1005" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND1004 ,Set/Clear Pending Bit 1004" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND1003 ,Set/Clear Pending Bit 1003" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND1002 ,Set/Clear Pending Bit 1002" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND1001 ,Set/Clear Pending Bit 1001" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND1000 ,Set/Clear Pending Bit 1000" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND999  ,Set/Clear Pending Bit 999" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND998  ,Set/Clear Pending Bit 998" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND997  ,Set/Clear Pending Bit 997" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND996  ,Set/Clear Pending Bit 996" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND995  ,Set/Clear Pending Bit 995" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND994  ,Set/Clear Pending Bit 994" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND993  ,Set/Clear Pending Bit 993" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND992  ,Set/Clear Pending Bit 992" "Not pending,Pending"
else
rgroup.long 0x027C++0x03
line.long 0x0 "GICD_SET/CLR_PENDR31,Interrupt Set/Clear Pending Register 31"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
tree.end
width 24.
tree "Set/Clear Active Registers"
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x08))&0xFF000000)==(0x0000000||0x1000000))
rgroup.long 0x0300++0x03
line.long 0x0 "GICD_ICDABR0,Active Status Register 0"
bitfld.long 0x00 31. " ASB31   ,Active Status Bit 31" "Not active,Active"
bitfld.long 0x00 30. "  ASB30   ,Active Status Bit 30" "Not active,Active"
bitfld.long 0x00 29. "  ASB29   ,Active Status Bit 29" "Not active,Active"
textline "                                 "
bitfld.long 0x00 28. " ASB28   ,Active Status Bit 28" "Not active,Active"
bitfld.long 0x00 27. "  ASB27   ,Active Status Bit 27" "Not active,Active"
bitfld.long 0x00 26. "  ASB26   ,Active Status Bit 26" "Not active,Active"
textline "                                 "
bitfld.long 0x00 25. " ASB25   ,Active Status Bit 25" "Not active,Active"
bitfld.long 0x00 24. "  ASB24   ,Active Status Bit 24" "Not active,Active"
bitfld.long 0x00 23. "  ASB23   ,Active Status Bit 23" "Not active,Active"
textline "                                 "
bitfld.long 0x00 22. " ASB22   ,Active Status Bit 22" "Not active,Active"
bitfld.long 0x00 21. "  ASB21   ,Active Status Bit 21" "Not active,Active"
bitfld.long 0x00 20. "  ASB20   ,Active Status Bit 20" "Not active,Active"
textline "                                 "
bitfld.long 0x00 19. " ASB19   ,Active Status Bit 19" "Not active,Active"
bitfld.long 0x00 18. "  ASB18   ,Active Status Bit 18" "Not active,Active"
bitfld.long 0x00 17. "  ASB17   ,Active Status Bit 17" "Not active,Active"
textline "                                 "
bitfld.long 0x00 16. " ASB16   ,Active Status Bit 16" "Not active,Active"
bitfld.long 0x00 15. "  ASB15   ,Active Status Bit 15" "Not active,Active"
bitfld.long 0x00 14. "  ASB14   ,Active Status Bit 14" "Not active,Active"
textline "                                 "
bitfld.long 0x00 13. " ASB13   ,Active Status Bit 13" "Not active,Active"
bitfld.long 0x00 12. "  ASB12   ,Active Status Bit 12" "Not active,Active"
bitfld.long 0x00 11. "  ASB11   ,Active Status Bit 11" "Not active,Active"
textline "                                 "
bitfld.long 0x00 10. " ASB10   ,Active Status Bit 10" "Not active,Active"
bitfld.long 0x00 9. "  ASB9    ,Active Status Bit 9" "Not active,Active"
bitfld.long 0x00 8. "  ASB8    ,Active Status Bit 8" "Not active,Active"
textline "                                 "
bitfld.long 0x00 7. " ASB7    ,Active Status Bit 7" "Not active,Active"
bitfld.long 0x00 6. "  ASB6    ,Active Status Bit 6" "Not active,Active"
bitfld.long 0x00 5. "  ASB5    ,Active Status Bit 5" "Not active,Active"
textline "                                 "
bitfld.long 0x00 4. " ASB4    ,Active Status Bit 4" "Not active,Active"
bitfld.long 0x00 3. "  ASB3    ,Active Status Bit 3" "Not active,Active"
bitfld.long 0x00 2. "  ASB2    ,Active Status Bit 2" "Not active,Active"
textline "                                 "
bitfld.long 0x00 1. " ASB1    ,Active Status Bit 1" "Not active,Active"
bitfld.long 0x00 0. "  ASB0    ,Active Status Bit 0" "Not active,Active"
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x01)
rgroup.long 0x0304++0x03
line.long 0x0 "GICD_ICDABR1,Active Status Register 1"
bitfld.long 0x00 31. " ASB63   ,Active Status Bit 63" "Not active,Active"
bitfld.long 0x00 30. "  ASB62   ,Active Status Bit 62" "Not active,Active"
bitfld.long 0x00 29. "  ASB61   ,Active Status Bit 61" "Not active,Active"
textline "                                 "
bitfld.long 0x00 28. " ASB60   ,Active Status Bit 60" "Not active,Active"
bitfld.long 0x00 27. "  ASB59   ,Active Status Bit 59" "Not active,Active"
bitfld.long 0x00 26. "  ASB58   ,Active Status Bit 58" "Not active,Active"
textline "                                 "
bitfld.long 0x00 25. " ASB57   ,Active Status Bit 57" "Not active,Active"
bitfld.long 0x00 24. "  ASB56   ,Active Status Bit 56" "Not active,Active"
bitfld.long 0x00 23. "  ASB55   ,Active Status Bit 55" "Not active,Active"
textline "                                 "
bitfld.long 0x00 22. " ASB54   ,Active Status Bit 54" "Not active,Active"
bitfld.long 0x00 21. "  ASB53   ,Active Status Bit 53" "Not active,Active"
bitfld.long 0x00 20. "  ASB52   ,Active Status Bit 52" "Not active,Active"
textline "                                 "
bitfld.long 0x00 19. " ASB51   ,Active Status Bit 51" "Not active,Active"
bitfld.long 0x00 18. "  ASB50   ,Active Status Bit 50" "Not active,Active"
bitfld.long 0x00 17. "  ASB49   ,Active Status Bit 49" "Not active,Active"
textline "                                 "
bitfld.long 0x00 16. " ASB48   ,Active Status Bit 48" "Not active,Active"
bitfld.long 0x00 15. "  ASB47   ,Active Status Bit 47" "Not active,Active"
bitfld.long 0x00 14. "  ASB46   ,Active Status Bit 46" "Not active,Active"
textline "                                 "
bitfld.long 0x00 13. " ASB45   ,Active Status Bit 45" "Not active,Active"
bitfld.long 0x00 12. "  ASB44   ,Active Status Bit 44" "Not active,Active"
bitfld.long 0x00 11. "  ASB43   ,Active Status Bit 43" "Not active,Active"
textline "                                 "
bitfld.long 0x00 10. " ASB42   ,Active Status Bit 42" "Not active,Active"
bitfld.long 0x00 9. "  ASB41   ,Active Status Bit 41" "Not active,Active"
bitfld.long 0x00 8. "  ASB40   ,Active Status Bit 40" "Not active,Active"
textline "                                 "
bitfld.long 0x00 7. " ASB39   ,Active Status Bit 39" "Not active,Active"
bitfld.long 0x00 6. "  ASB38   ,Active Status Bit 38" "Not active,Active"
bitfld.long 0x00 5. "  ASB37   ,Active Status Bit 37" "Not active,Active"
textline "                                 "
bitfld.long 0x00 4. " ASB36   ,Active Status Bit 36" "Not active,Active"
bitfld.long 0x00 3. "  ASB35   ,Active Status Bit 35" "Not active,Active"
bitfld.long 0x00 2. "  ASB34   ,Active Status Bit 34" "Not active,Active"
textline "                                 "
bitfld.long 0x00 1. " ASB33   ,Active Status Bit 33" "Not active,Active"
bitfld.long 0x00 0. "  ASB32   ,Active Status Bit 32" "Not active,Active"
else
rgroup.long 0x0304++0x03
line.long 0x0 "GICD_ICDABR1,Active Status Register 1"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x02)
rgroup.long 0x0308++0x03
line.long 0x0 "GICD_ICDABR2,Active Status Register 2"
bitfld.long 0x00 31. " ASB95   ,Active Status Bit 95" "Not active,Active"
bitfld.long 0x00 30. "  ASB94   ,Active Status Bit 94" "Not active,Active"
bitfld.long 0x00 29. "  ASB93   ,Active Status Bit 93" "Not active,Active"
textline "                                 "
bitfld.long 0x00 28. " ASB92   ,Active Status Bit 92" "Not active,Active"
bitfld.long 0x00 27. "  ASB91   ,Active Status Bit 91" "Not active,Active"
bitfld.long 0x00 26. "  ASB90   ,Active Status Bit 90" "Not active,Active"
textline "                                 "
bitfld.long 0x00 25. " ASB89   ,Active Status Bit 89" "Not active,Active"
bitfld.long 0x00 24. "  ASB88   ,Active Status Bit 88" "Not active,Active"
bitfld.long 0x00 23. "  ASB87   ,Active Status Bit 87" "Not active,Active"
textline "                                 "
bitfld.long 0x00 22. " ASB86   ,Active Status Bit 86" "Not active,Active"
bitfld.long 0x00 21. "  ASB85   ,Active Status Bit 85" "Not active,Active"
bitfld.long 0x00 20. "  ASB84   ,Active Status Bit 84" "Not active,Active"
textline "                                 "
bitfld.long 0x00 19. " ASB83   ,Active Status Bit 83" "Not active,Active"
bitfld.long 0x00 18. "  ASB82   ,Active Status Bit 82" "Not active,Active"
bitfld.long 0x00 17. "  ASB81   ,Active Status Bit 81" "Not active,Active"
textline "                                 "
bitfld.long 0x00 16. " ASB80   ,Active Status Bit 80" "Not active,Active"
bitfld.long 0x00 15. "  ASB79   ,Active Status Bit 79" "Not active,Active"
bitfld.long 0x00 14. "  ASB78   ,Active Status Bit 78" "Not active,Active"
textline "                                 "
bitfld.long 0x00 13. " ASB77   ,Active Status Bit 77" "Not active,Active"
bitfld.long 0x00 12. "  ASB76   ,Active Status Bit 76" "Not active,Active"
bitfld.long 0x00 11. "  ASB75   ,Active Status Bit 75" "Not active,Active"
textline "                                 "
bitfld.long 0x00 10. " ASB74   ,Active Status Bit 74" "Not active,Active"
bitfld.long 0x00 9. "  ASB73   ,Active Status Bit 73" "Not active,Active"
bitfld.long 0x00 8. "  ASB72   ,Active Status Bit 72" "Not active,Active"
textline "                                 "
bitfld.long 0x00 7. " ASB71   ,Active Status Bit 71" "Not active,Active"
bitfld.long 0x00 6. "  ASB70   ,Active Status Bit 70" "Not active,Active"
bitfld.long 0x00 5. "  ASB69   ,Active Status Bit 69" "Not active,Active"
textline "                                 "
bitfld.long 0x00 4. " ASB68   ,Active Status Bit 68" "Not active,Active"
bitfld.long 0x00 3. "  ASB67   ,Active Status Bit 67" "Not active,Active"
bitfld.long 0x00 2. "  ASB66   ,Active Status Bit 66" "Not active,Active"
textline "                                 "
bitfld.long 0x00 1. " ASB65   ,Active Status Bit 65" "Not active,Active"
bitfld.long 0x00 0. "  ASB64   ,Active Status Bit 64" "Not active,Active"
else
rgroup.long 0x0308++0x03
line.long 0x0 "GICD_ICDABR2,Active Status Register 2"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x03)
rgroup.long 0x030C++0x03
line.long 0x0 "GICD_ICDABR3,Active Status Register 3"
bitfld.long 0x00 31. " ASB127  ,Active Status Bit 127" "Not active,Active"
bitfld.long 0x00 30. "  ASB126  ,Active Status Bit 126" "Not active,Active"
bitfld.long 0x00 29. "  ASB125  ,Active Status Bit 125" "Not active,Active"
textline "                                 "
bitfld.long 0x00 28. " ASB124  ,Active Status Bit 124" "Not active,Active"
bitfld.long 0x00 27. "  ASB123  ,Active Status Bit 123" "Not active,Active"
bitfld.long 0x00 26. "  ASB122  ,Active Status Bit 122" "Not active,Active"
textline "                                 "
bitfld.long 0x00 25. " ASB121  ,Active Status Bit 121" "Not active,Active"
bitfld.long 0x00 24. "  ASB120  ,Active Status Bit 120" "Not active,Active"
bitfld.long 0x00 23. "  ASB119  ,Active Status Bit 119" "Not active,Active"
textline "                                 "
bitfld.long 0x00 22. " ASB118  ,Active Status Bit 118" "Not active,Active"
bitfld.long 0x00 21. "  ASB117  ,Active Status Bit 117" "Not active,Active"
bitfld.long 0x00 20. "  ASB116  ,Active Status Bit 116" "Not active,Active"
textline "                                 "
bitfld.long 0x00 19. " ASB115  ,Active Status Bit 115" "Not active,Active"
bitfld.long 0x00 18. "  ASB114  ,Active Status Bit 114" "Not active,Active"
bitfld.long 0x00 17. "  ASB113  ,Active Status Bit 113" "Not active,Active"
textline "                                 "
bitfld.long 0x00 16. " ASB112  ,Active Status Bit 112" "Not active,Active"
bitfld.long 0x00 15. "  ASB111  ,Active Status Bit 111" "Not active,Active"
bitfld.long 0x00 14. "  ASB110  ,Active Status Bit 110" "Not active,Active"
textline "                                 "
bitfld.long 0x00 13. " ASB109  ,Active Status Bit 109" "Not active,Active"
bitfld.long 0x00 12. "  ASB108  ,Active Status Bit 108" "Not active,Active"
bitfld.long 0x00 11. "  ASB107  ,Active Status Bit 107" "Not active,Active"
textline "                                 "
bitfld.long 0x00 10. " ASB106  ,Active Status Bit 106" "Not active,Active"
bitfld.long 0x00 9. "  ASB105  ,Active Status Bit 105" "Not active,Active"
bitfld.long 0x00 8. "  ASB104  ,Active Status Bit 104" "Not active,Active"
textline "                                 "
bitfld.long 0x00 7. " ASB103  ,Active Status Bit 103" "Not active,Active"
bitfld.long 0x00 6. "  ASB102  ,Active Status Bit 102" "Not active,Active"
bitfld.long 0x00 5. "  ASB101  ,Active Status Bit 101" "Not active,Active"
textline "                                 "
bitfld.long 0x00 4. " ASB100  ,Active Status Bit 100" "Not active,Active"
bitfld.long 0x00 3. "  ASB99   ,Active Status Bit 99" "Not active,Active"
bitfld.long 0x00 2. "  ASB98   ,Active Status Bit 98" "Not active,Active"
textline "                                 "
bitfld.long 0x00 1. " ASB97   ,Active Status Bit 97" "Not active,Active"
bitfld.long 0x00 0. "  ASB96   ,Active Status Bit 96" "Not active,Active"
else
rgroup.long 0x030C++0x03
line.long 0x0 "GICD_ICDABR3,Active Status Register 3"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x04)
rgroup.long 0x0310++0x03
line.long 0x0 "GICD_ICDABR4,Active Status Register 4"
bitfld.long 0x00 31. " ASB159  ,Active Status Bit 159" "Not active,Active"
bitfld.long 0x00 30. "  ASB158  ,Active Status Bit 158" "Not active,Active"
bitfld.long 0x00 29. "  ASB157  ,Active Status Bit 157" "Not active,Active"
textline "                                 "
bitfld.long 0x00 28. " ASB156  ,Active Status Bit 156" "Not active,Active"
bitfld.long 0x00 27. "  ASB155  ,Active Status Bit 155" "Not active,Active"
bitfld.long 0x00 26. "  ASB154  ,Active Status Bit 154" "Not active,Active"
textline "                                 "
bitfld.long 0x00 25. " ASB153  ,Active Status Bit 153" "Not active,Active"
bitfld.long 0x00 24. "  ASB152  ,Active Status Bit 152" "Not active,Active"
bitfld.long 0x00 23. "  ASB151  ,Active Status Bit 151" "Not active,Active"
textline "                                 "
bitfld.long 0x00 22. " ASB150  ,Active Status Bit 150" "Not active,Active"
bitfld.long 0x00 21. "  ASB149  ,Active Status Bit 149" "Not active,Active"
bitfld.long 0x00 20. "  ASB148  ,Active Status Bit 148" "Not active,Active"
textline "                                 "
bitfld.long 0x00 19. " ASB147  ,Active Status Bit 147" "Not active,Active"
bitfld.long 0x00 18. "  ASB146  ,Active Status Bit 146" "Not active,Active"
bitfld.long 0x00 17. "  ASB145  ,Active Status Bit 145" "Not active,Active"
textline "                                 "
bitfld.long 0x00 16. " ASB144  ,Active Status Bit 144" "Not active,Active"
bitfld.long 0x00 15. "  ASB143  ,Active Status Bit 143" "Not active,Active"
bitfld.long 0x00 14. "  ASB142  ,Active Status Bit 142" "Not active,Active"
textline "                                 "
bitfld.long 0x00 13. " ASB141  ,Active Status Bit 141" "Not active,Active"
bitfld.long 0x00 12. "  ASB140  ,Active Status Bit 140" "Not active,Active"
bitfld.long 0x00 11. "  ASB139  ,Active Status Bit 139" "Not active,Active"
textline "                                 "
bitfld.long 0x00 10. " ASB138  ,Active Status Bit 138" "Not active,Active"
bitfld.long 0x00 9. "  ASB137  ,Active Status Bit 137" "Not active,Active"
bitfld.long 0x00 8. "  ASB136  ,Active Status Bit 136" "Not active,Active"
textline "                                 "
bitfld.long 0x00 7. " ASB135  ,Active Status Bit 135" "Not active,Active"
bitfld.long 0x00 6. "  ASB134  ,Active Status Bit 134" "Not active,Active"
bitfld.long 0x00 5. "  ASB133  ,Active Status Bit 133" "Not active,Active"
textline "                                 "
bitfld.long 0x00 4. " ASB132  ,Active Status Bit 132" "Not active,Active"
bitfld.long 0x00 3. "  ASB131  ,Active Status Bit 131" "Not active,Active"
bitfld.long 0x00 2. "  ASB130  ,Active Status Bit 130" "Not active,Active"
textline "                                 "
bitfld.long 0x00 1. " ASB129  ,Active Status Bit 129" "Not active,Active"
bitfld.long 0x00 0. "  ASB128  ,Active Status Bit 128" "Not active,Active"
else
rgroup.long 0x0310++0x03
line.long 0x0 "GICD_ICDABR4,Active Status Register 4"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x05)
rgroup.long 0x0314++0x03
line.long 0x0 "GICD_ICDABR5,Active Status Register 5"
bitfld.long 0x00 31. " ASB191  ,Active Status Bit 191" "Not active,Active"
bitfld.long 0x00 30. "  ASB190  ,Active Status Bit 190" "Not active,Active"
bitfld.long 0x00 29. "  ASB189  ,Active Status Bit 189" "Not active,Active"
textline "                                 "
bitfld.long 0x00 28. " ASB188  ,Active Status Bit 188" "Not active,Active"
bitfld.long 0x00 27. "  ASB187  ,Active Status Bit 187" "Not active,Active"
bitfld.long 0x00 26. "  ASB186  ,Active Status Bit 186" "Not active,Active"
textline "                                 "
bitfld.long 0x00 25. " ASB185  ,Active Status Bit 185" "Not active,Active"
bitfld.long 0x00 24. "  ASB184  ,Active Status Bit 184" "Not active,Active"
bitfld.long 0x00 23. "  ASB183  ,Active Status Bit 183" "Not active,Active"
textline "                                 "
bitfld.long 0x00 22. " ASB182  ,Active Status Bit 182" "Not active,Active"
bitfld.long 0x00 21. "  ASB181  ,Active Status Bit 181" "Not active,Active"
bitfld.long 0x00 20. "  ASB180  ,Active Status Bit 180" "Not active,Active"
textline "                                 "
bitfld.long 0x00 19. " ASB179  ,Active Status Bit 179" "Not active,Active"
bitfld.long 0x00 18. "  ASB178  ,Active Status Bit 178" "Not active,Active"
bitfld.long 0x00 17. "  ASB177  ,Active Status Bit 177" "Not active,Active"
textline "                                 "
bitfld.long 0x00 16. " ASB176  ,Active Status Bit 176" "Not active,Active"
bitfld.long 0x00 15. "  ASB175  ,Active Status Bit 175" "Not active,Active"
bitfld.long 0x00 14. "  ASB174  ,Active Status Bit 174" "Not active,Active"
textline "                                 "
bitfld.long 0x00 13. " ASB173  ,Active Status Bit 173" "Not active,Active"
bitfld.long 0x00 12. "  ASB172  ,Active Status Bit 172" "Not active,Active"
bitfld.long 0x00 11. "  ASB171  ,Active Status Bit 171" "Not active,Active"
textline "                                 "
bitfld.long 0x00 10. " ASB170  ,Active Status Bit 170" "Not active,Active"
bitfld.long 0x00 9. "  ASB169  ,Active Status Bit 169" "Not active,Active"
bitfld.long 0x00 8. "  ASB168  ,Active Status Bit 168" "Not active,Active"
textline "                                 "
bitfld.long 0x00 7. " ASB167  ,Active Status Bit 167" "Not active,Active"
bitfld.long 0x00 6. "  ASB166  ,Active Status Bit 166" "Not active,Active"
bitfld.long 0x00 5. "  ASB165  ,Active Status Bit 165" "Not active,Active"
textline "                                 "
bitfld.long 0x00 4. " ASB164  ,Active Status Bit 164" "Not active,Active"
bitfld.long 0x00 3. "  ASB163  ,Active Status Bit 163" "Not active,Active"
bitfld.long 0x00 2. "  ASB162  ,Active Status Bit 162" "Not active,Active"
textline "                                 "
bitfld.long 0x00 1. " ASB161  ,Active Status Bit 161" "Not active,Active"
bitfld.long 0x00 0. "  ASB160  ,Active Status Bit 160" "Not active,Active"
else
rgroup.long 0x0314++0x03
line.long 0x0 "GICD_ICDABR5,Active Status Register 5"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x06)
rgroup.long 0x0318++0x03
line.long 0x0 "GICD_ICDABR6,Active Status Register 6"
bitfld.long 0x00 31. " ASB223  ,Active Status Bit 223" "Not active,Active"
bitfld.long 0x00 30. "  ASB222  ,Active Status Bit 222" "Not active,Active"
bitfld.long 0x00 29. "  ASB221  ,Active Status Bit 221" "Not active,Active"
textline "                                 "
bitfld.long 0x00 28. " ASB220  ,Active Status Bit 220" "Not active,Active"
bitfld.long 0x00 27. "  ASB219  ,Active Status Bit 219" "Not active,Active"
bitfld.long 0x00 26. "  ASB218  ,Active Status Bit 218" "Not active,Active"
textline "                                 "
bitfld.long 0x00 25. " ASB217  ,Active Status Bit 217" "Not active,Active"
bitfld.long 0x00 24. "  ASB216  ,Active Status Bit 216" "Not active,Active"
bitfld.long 0x00 23. "  ASB215  ,Active Status Bit 215" "Not active,Active"
textline "                                 "
bitfld.long 0x00 22. " ASB214  ,Active Status Bit 214" "Not active,Active"
bitfld.long 0x00 21. "  ASB213  ,Active Status Bit 213" "Not active,Active"
bitfld.long 0x00 20. "  ASB212  ,Active Status Bit 212" "Not active,Active"
textline "                                 "
bitfld.long 0x00 19. " ASB211  ,Active Status Bit 211" "Not active,Active"
bitfld.long 0x00 18. "  ASB210  ,Active Status Bit 210" "Not active,Active"
bitfld.long 0x00 17. "  ASB209  ,Active Status Bit 209" "Not active,Active"
textline "                                 "
bitfld.long 0x00 16. " ASB208  ,Active Status Bit 208" "Not active,Active"
bitfld.long 0x00 15. "  ASB207  ,Active Status Bit 207" "Not active,Active"
bitfld.long 0x00 14. "  ASB206  ,Active Status Bit 206" "Not active,Active"
textline "                                 "
bitfld.long 0x00 13. " ASB205  ,Active Status Bit 205" "Not active,Active"
bitfld.long 0x00 12. "  ASB204  ,Active Status Bit 204" "Not active,Active"
bitfld.long 0x00 11. "  ASB203  ,Active Status Bit 203" "Not active,Active"
textline "                                 "
bitfld.long 0x00 10. " ASB202  ,Active Status Bit 202" "Not active,Active"
bitfld.long 0x00 9. "  ASB201  ,Active Status Bit 201" "Not active,Active"
bitfld.long 0x00 8. "  ASB200  ,Active Status Bit 200" "Not active,Active"
textline "                                 "
bitfld.long 0x00 7. " ASB199  ,Active Status Bit 199" "Not active,Active"
bitfld.long 0x00 6. "  ASB198  ,Active Status Bit 198" "Not active,Active"
bitfld.long 0x00 5. "  ASB197  ,Active Status Bit 197" "Not active,Active"
textline "                                 "
bitfld.long 0x00 4. " ASB196  ,Active Status Bit 196" "Not active,Active"
bitfld.long 0x00 3. "  ASB195  ,Active Status Bit 195" "Not active,Active"
bitfld.long 0x00 2. "  ASB194  ,Active Status Bit 194" "Not active,Active"
textline "                                 "
bitfld.long 0x00 1. " ASB193  ,Active Status Bit 193" "Not active,Active"
bitfld.long 0x00 0. "  ASB192  ,Active Status Bit 192" "Not active,Active"
else
rgroup.long 0x0318++0x03
line.long 0x0 "GICD_ICDABR6,Active Status Register 6"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x07)
rgroup.long 0x031C++0x03
line.long 0x0 "GICD_ICDABR7,Active Status Register 7"
bitfld.long 0x00 31. " ASB255  ,Active Status Bit 255" "Not active,Active"
bitfld.long 0x00 30. "  ASB254  ,Active Status Bit 254" "Not active,Active"
bitfld.long 0x00 29. "  ASB253  ,Active Status Bit 253" "Not active,Active"
textline "                                 "
bitfld.long 0x00 28. " ASB252  ,Active Status Bit 252" "Not active,Active"
bitfld.long 0x00 27. "  ASB251  ,Active Status Bit 251" "Not active,Active"
bitfld.long 0x00 26. "  ASB250  ,Active Status Bit 250" "Not active,Active"
textline "                                 "
bitfld.long 0x00 25. " ASB249  ,Active Status Bit 249" "Not active,Active"
bitfld.long 0x00 24. "  ASB248  ,Active Status Bit 248" "Not active,Active"
bitfld.long 0x00 23. "  ASB247  ,Active Status Bit 247" "Not active,Active"
textline "                                 "
bitfld.long 0x00 22. " ASB246  ,Active Status Bit 246" "Not active,Active"
bitfld.long 0x00 21. "  ASB245  ,Active Status Bit 245" "Not active,Active"
bitfld.long 0x00 20. "  ASB244  ,Active Status Bit 244" "Not active,Active"
textline "                                 "
bitfld.long 0x00 19. " ASB243  ,Active Status Bit 243" "Not active,Active"
bitfld.long 0x00 18. "  ASB242  ,Active Status Bit 242" "Not active,Active"
bitfld.long 0x00 17. "  ASB241  ,Active Status Bit 241" "Not active,Active"
textline "                                 "
bitfld.long 0x00 16. " ASB240  ,Active Status Bit 240" "Not active,Active"
bitfld.long 0x00 15. "  ASB239  ,Active Status Bit 239" "Not active,Active"
bitfld.long 0x00 14. "  ASB238  ,Active Status Bit 238" "Not active,Active"
textline "                                 "
bitfld.long 0x00 13. " ASB237  ,Active Status Bit 237" "Not active,Active"
bitfld.long 0x00 12. "  ASB236  ,Active Status Bit 236" "Not active,Active"
bitfld.long 0x00 11. "  ASB235  ,Active Status Bit 235" "Not active,Active"
textline "                                 "
bitfld.long 0x00 10. " ASB234  ,Active Status Bit 234" "Not active,Active"
bitfld.long 0x00 9. "  ASB233  ,Active Status Bit 233" "Not active,Active"
bitfld.long 0x00 8. "  ASB232  ,Active Status Bit 232" "Not active,Active"
textline "                                 "
bitfld.long 0x00 7. " ASB231  ,Active Status Bit 231" "Not active,Active"
bitfld.long 0x00 6. "  ASB230  ,Active Status Bit 230" "Not active,Active"
bitfld.long 0x00 5. "  ASB229  ,Active Status Bit 229" "Not active,Active"
textline "                                 "
bitfld.long 0x00 4. " ASB228  ,Active Status Bit 228" "Not active,Active"
bitfld.long 0x00 3. "  ASB227  ,Active Status Bit 227" "Not active,Active"
bitfld.long 0x00 2. "  ASB226  ,Active Status Bit 226" "Not active,Active"
textline "                                 "
bitfld.long 0x00 1. " ASB225  ,Active Status Bit 225" "Not active,Active"
bitfld.long 0x00 0. "  ASB224  ,Active Status Bit 224" "Not active,Active"
else
rgroup.long 0x031C++0x03
line.long 0x0 "GICD_ICDABR7,Active Status Register 7"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x08)
rgroup.long 0x0320++0x03
line.long 0x0 "GICD_ICDABR8,Active Status Register 8"
bitfld.long 0x00 31. " ASB287  ,Active Status Bit 287" "Not active,Active"
bitfld.long 0x00 30. "  ASB286  ,Active Status Bit 286" "Not active,Active"
bitfld.long 0x00 29. "  ASB285  ,Active Status Bit 285" "Not active,Active"
textline "                                 "
bitfld.long 0x00 28. " ASB284  ,Active Status Bit 284" "Not active,Active"
bitfld.long 0x00 27. "  ASB283  ,Active Status Bit 283" "Not active,Active"
bitfld.long 0x00 26. "  ASB282  ,Active Status Bit 282" "Not active,Active"
textline "                                 "
bitfld.long 0x00 25. " ASB281  ,Active Status Bit 281" "Not active,Active"
bitfld.long 0x00 24. "  ASB280  ,Active Status Bit 280" "Not active,Active"
bitfld.long 0x00 23. "  ASB279  ,Active Status Bit 279" "Not active,Active"
textline "                                 "
bitfld.long 0x00 22. " ASB278  ,Active Status Bit 278" "Not active,Active"
bitfld.long 0x00 21. "  ASB277  ,Active Status Bit 277" "Not active,Active"
bitfld.long 0x00 20. "  ASB276  ,Active Status Bit 276" "Not active,Active"
textline "                                 "
bitfld.long 0x00 19. " ASB275  ,Active Status Bit 275" "Not active,Active"
bitfld.long 0x00 18. "  ASB274  ,Active Status Bit 274" "Not active,Active"
bitfld.long 0x00 17. "  ASB273  ,Active Status Bit 273" "Not active,Active"
textline "                                 "
bitfld.long 0x00 16. " ASB272  ,Active Status Bit 272" "Not active,Active"
bitfld.long 0x00 15. "  ASB271  ,Active Status Bit 271" "Not active,Active"
bitfld.long 0x00 14. "  ASB270  ,Active Status Bit 270" "Not active,Active"
textline "                                 "
bitfld.long 0x00 13. " ASB269  ,Active Status Bit 269" "Not active,Active"
bitfld.long 0x00 12. "  ASB268  ,Active Status Bit 268" "Not active,Active"
bitfld.long 0x00 11. "  ASB267  ,Active Status Bit 267" "Not active,Active"
textline "                                 "
bitfld.long 0x00 10. " ASB266  ,Active Status Bit 266" "Not active,Active"
bitfld.long 0x00 9. "  ASB265  ,Active Status Bit 265" "Not active,Active"
bitfld.long 0x00 8. "  ASB264  ,Active Status Bit 264" "Not active,Active"
textline "                                 "
bitfld.long 0x00 7. " ASB263  ,Active Status Bit 263" "Not active,Active"
bitfld.long 0x00 6. "  ASB262  ,Active Status Bit 262" "Not active,Active"
bitfld.long 0x00 5. "  ASB261  ,Active Status Bit 261" "Not active,Active"
textline "                                 "
bitfld.long 0x00 4. " ASB260  ,Active Status Bit 260" "Not active,Active"
bitfld.long 0x00 3. "  ASB259  ,Active Status Bit 259" "Not active,Active"
bitfld.long 0x00 2. "  ASB258  ,Active Status Bit 258" "Not active,Active"
textline "                                 "
bitfld.long 0x00 1. " ASB257  ,Active Status Bit 257" "Not active,Active"
bitfld.long 0x00 0. "  ASB256  ,Active Status Bit 256" "Not active,Active"
else
rgroup.long 0x0320++0x03
line.long 0x0 "GICD_ICDABR8,Active Status Register 8"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x09)
rgroup.long 0x0324++0x03
line.long 0x0 "GICD_ICDABR9,Active Status Register 9"
bitfld.long 0x00 31. " ASB319  ,Active Status Bit 319" "Not active,Active"
bitfld.long 0x00 30. "  ASB318  ,Active Status Bit 318" "Not active,Active"
bitfld.long 0x00 29. "  ASB317  ,Active Status Bit 317" "Not active,Active"
textline "                                 "
bitfld.long 0x00 28. " ASB316  ,Active Status Bit 316" "Not active,Active"
bitfld.long 0x00 27. "  ASB315  ,Active Status Bit 315" "Not active,Active"
bitfld.long 0x00 26. "  ASB314  ,Active Status Bit 314" "Not active,Active"
textline "                                 "
bitfld.long 0x00 25. " ASB313  ,Active Status Bit 313" "Not active,Active"
bitfld.long 0x00 24. "  ASB312  ,Active Status Bit 312" "Not active,Active"
bitfld.long 0x00 23. "  ASB311  ,Active Status Bit 311" "Not active,Active"
textline "                                 "
bitfld.long 0x00 22. " ASB310  ,Active Status Bit 310" "Not active,Active"
bitfld.long 0x00 21. "  ASB309  ,Active Status Bit 309" "Not active,Active"
bitfld.long 0x00 20. "  ASB308  ,Active Status Bit 308" "Not active,Active"
textline "                                 "
bitfld.long 0x00 19. " ASB307  ,Active Status Bit 307" "Not active,Active"
bitfld.long 0x00 18. "  ASB306  ,Active Status Bit 306" "Not active,Active"
bitfld.long 0x00 17. "  ASB305  ,Active Status Bit 305" "Not active,Active"
textline "                                 "
bitfld.long 0x00 16. " ASB304  ,Active Status Bit 304" "Not active,Active"
bitfld.long 0x00 15. "  ASB303  ,Active Status Bit 303" "Not active,Active"
bitfld.long 0x00 14. "  ASB302  ,Active Status Bit 302" "Not active,Active"
textline "                                 "
bitfld.long 0x00 13. " ASB301  ,Active Status Bit 301" "Not active,Active"
bitfld.long 0x00 12. "  ASB300  ,Active Status Bit 300" "Not active,Active"
bitfld.long 0x00 11. "  ASB299  ,Active Status Bit 299" "Not active,Active"
textline "                                 "
bitfld.long 0x00 10. " ASB298  ,Active Status Bit 298" "Not active,Active"
bitfld.long 0x00 9. "  ASB297  ,Active Status Bit 297" "Not active,Active"
bitfld.long 0x00 8. "  ASB296  ,Active Status Bit 296" "Not active,Active"
textline "                                 "
bitfld.long 0x00 7. " ASB295  ,Active Status Bit 295" "Not active,Active"
bitfld.long 0x00 6. "  ASB294  ,Active Status Bit 294" "Not active,Active"
bitfld.long 0x00 5. "  ASB293  ,Active Status Bit 293" "Not active,Active"
textline "                                 "
bitfld.long 0x00 4. " ASB292  ,Active Status Bit 292" "Not active,Active"
bitfld.long 0x00 3. "  ASB291  ,Active Status Bit 291" "Not active,Active"
bitfld.long 0x00 2. "  ASB290  ,Active Status Bit 290" "Not active,Active"
textline "                                 "
bitfld.long 0x00 1. " ASB289  ,Active Status Bit 289" "Not active,Active"
bitfld.long 0x00 0. "  ASB288  ,Active Status Bit 288" "Not active,Active"
else
rgroup.long 0x0324++0x03
line.long 0x0 "GICD_ICDABR9,Active Status Register 9"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0A)
rgroup.long 0x0328++0x03
line.long 0x0 "GICD_ICDABR10,Active Status Register 10"
bitfld.long 0x00 31. " ASB351  ,Active Status Bit 351" "Not active,Active"
bitfld.long 0x00 30. "  ASB350  ,Active Status Bit 350" "Not active,Active"
bitfld.long 0x00 29. "  ASB349  ,Active Status Bit 349" "Not active,Active"
textline "                                 "
bitfld.long 0x00 28. " ASB348  ,Active Status Bit 348" "Not active,Active"
bitfld.long 0x00 27. "  ASB347  ,Active Status Bit 347" "Not active,Active"
bitfld.long 0x00 26. "  ASB346  ,Active Status Bit 346" "Not active,Active"
textline "                                 "
bitfld.long 0x00 25. " ASB345  ,Active Status Bit 345" "Not active,Active"
bitfld.long 0x00 24. "  ASB344  ,Active Status Bit 344" "Not active,Active"
bitfld.long 0x00 23. "  ASB343  ,Active Status Bit 343" "Not active,Active"
textline "                                 "
bitfld.long 0x00 22. " ASB342  ,Active Status Bit 342" "Not active,Active"
bitfld.long 0x00 21. "  ASB341  ,Active Status Bit 341" "Not active,Active"
bitfld.long 0x00 20. "  ASB340  ,Active Status Bit 340" "Not active,Active"
textline "                                 "
bitfld.long 0x00 19. " ASB339  ,Active Status Bit 339" "Not active,Active"
bitfld.long 0x00 18. "  ASB338  ,Active Status Bit 338" "Not active,Active"
bitfld.long 0x00 17. "  ASB337  ,Active Status Bit 337" "Not active,Active"
textline "                                 "
bitfld.long 0x00 16. " ASB336  ,Active Status Bit 336" "Not active,Active"
bitfld.long 0x00 15. "  ASB335  ,Active Status Bit 335" "Not active,Active"
bitfld.long 0x00 14. "  ASB334  ,Active Status Bit 334" "Not active,Active"
textline "                                 "
bitfld.long 0x00 13. " ASB333  ,Active Status Bit 333" "Not active,Active"
bitfld.long 0x00 12. "  ASB332  ,Active Status Bit 332" "Not active,Active"
bitfld.long 0x00 11. "  ASB331  ,Active Status Bit 331" "Not active,Active"
textline "                                 "
bitfld.long 0x00 10. " ASB330  ,Active Status Bit 330" "Not active,Active"
bitfld.long 0x00 9. "  ASB329  ,Active Status Bit 329" "Not active,Active"
bitfld.long 0x00 8. "  ASB328  ,Active Status Bit 328" "Not active,Active"
textline "                                 "
bitfld.long 0x00 7. " ASB327  ,Active Status Bit 327" "Not active,Active"
bitfld.long 0x00 6. "  ASB326  ,Active Status Bit 326" "Not active,Active"
bitfld.long 0x00 5. "  ASB325  ,Active Status Bit 325" "Not active,Active"
textline "                                 "
bitfld.long 0x00 4. " ASB324  ,Active Status Bit 324" "Not active,Active"
bitfld.long 0x00 3. "  ASB323  ,Active Status Bit 323" "Not active,Active"
bitfld.long 0x00 2. "  ASB322  ,Active Status Bit 322" "Not active,Active"
textline "                                 "
bitfld.long 0x00 1. " ASB321  ,Active Status Bit 321" "Not active,Active"
bitfld.long 0x00 0. "  ASB320  ,Active Status Bit 320" "Not active,Active"
else
rgroup.long 0x0328++0x03
line.long 0x0 "GICD_ICDABR10,Active Status Register 10"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0B)
rgroup.long 0x032C++0x03
line.long 0x0 "GICD_ICDABR11,Active Status Register 11"
bitfld.long 0x00 31. " ASB383  ,Active Status Bit 383" "Not active,Active"
bitfld.long 0x00 30. "  ASB382  ,Active Status Bit 382" "Not active,Active"
bitfld.long 0x00 29. "  ASB381  ,Active Status Bit 381" "Not active,Active"
textline "                                 "
bitfld.long 0x00 28. " ASB380  ,Active Status Bit 380" "Not active,Active"
bitfld.long 0x00 27. "  ASB379  ,Active Status Bit 379" "Not active,Active"
bitfld.long 0x00 26. "  ASB378  ,Active Status Bit 378" "Not active,Active"
textline "                                 "
bitfld.long 0x00 25. " ASB377  ,Active Status Bit 377" "Not active,Active"
bitfld.long 0x00 24. "  ASB376  ,Active Status Bit 376" "Not active,Active"
bitfld.long 0x00 23. "  ASB375  ,Active Status Bit 375" "Not active,Active"
textline "                                 "
bitfld.long 0x00 22. " ASB374  ,Active Status Bit 374" "Not active,Active"
bitfld.long 0x00 21. "  ASB373  ,Active Status Bit 373" "Not active,Active"
bitfld.long 0x00 20. "  ASB372  ,Active Status Bit 372" "Not active,Active"
textline "                                 "
bitfld.long 0x00 19. " ASB371  ,Active Status Bit 371" "Not active,Active"
bitfld.long 0x00 18. "  ASB370  ,Active Status Bit 370" "Not active,Active"
bitfld.long 0x00 17. "  ASB369  ,Active Status Bit 369" "Not active,Active"
textline "                                 "
bitfld.long 0x00 16. " ASB368  ,Active Status Bit 368" "Not active,Active"
bitfld.long 0x00 15. "  ASB367  ,Active Status Bit 367" "Not active,Active"
bitfld.long 0x00 14. "  ASB366  ,Active Status Bit 366" "Not active,Active"
textline "                                 "
bitfld.long 0x00 13. " ASB365  ,Active Status Bit 365" "Not active,Active"
bitfld.long 0x00 12. "  ASB364  ,Active Status Bit 364" "Not active,Active"
bitfld.long 0x00 11. "  ASB363  ,Active Status Bit 363" "Not active,Active"
textline "                                 "
bitfld.long 0x00 10. " ASB362  ,Active Status Bit 362" "Not active,Active"
bitfld.long 0x00 9. "  ASB361  ,Active Status Bit 361" "Not active,Active"
bitfld.long 0x00 8. "  ASB360  ,Active Status Bit 360" "Not active,Active"
textline "                                 "
bitfld.long 0x00 7. " ASB359  ,Active Status Bit 359" "Not active,Active"
bitfld.long 0x00 6. "  ASB358  ,Active Status Bit 358" "Not active,Active"
bitfld.long 0x00 5. "  ASB357  ,Active Status Bit 357" "Not active,Active"
textline "                                 "
bitfld.long 0x00 4. " ASB356  ,Active Status Bit 356" "Not active,Active"
bitfld.long 0x00 3. "  ASB355  ,Active Status Bit 355" "Not active,Active"
bitfld.long 0x00 2. "  ASB354  ,Active Status Bit 354" "Not active,Active"
textline "                                 "
bitfld.long 0x00 1. " ASB353  ,Active Status Bit 353" "Not active,Active"
bitfld.long 0x00 0. "  ASB352  ,Active Status Bit 352" "Not active,Active"
else
rgroup.long 0x032C++0x03
line.long 0x0 "GICD_ICDABR11,Active Status Register 11"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0C)
rgroup.long 0x0330++0x03
line.long 0x0 "GICD_ICDABR12,Active Status Register 12"
bitfld.long 0x00 31. " ASB415  ,Active Status Bit 415" "Not active,Active"
bitfld.long 0x00 30. "  ASB414  ,Active Status Bit 414" "Not active,Active"
bitfld.long 0x00 29. "  ASB413  ,Active Status Bit 413" "Not active,Active"
textline "                                 "
bitfld.long 0x00 28. " ASB412  ,Active Status Bit 412" "Not active,Active"
bitfld.long 0x00 27. "  ASB411  ,Active Status Bit 411" "Not active,Active"
bitfld.long 0x00 26. "  ASB410  ,Active Status Bit 410" "Not active,Active"
textline "                                 "
bitfld.long 0x00 25. " ASB409  ,Active Status Bit 409" "Not active,Active"
bitfld.long 0x00 24. "  ASB408  ,Active Status Bit 408" "Not active,Active"
bitfld.long 0x00 23. "  ASB407  ,Active Status Bit 407" "Not active,Active"
textline "                                 "
bitfld.long 0x00 22. " ASB406  ,Active Status Bit 406" "Not active,Active"
bitfld.long 0x00 21. "  ASB405  ,Active Status Bit 405" "Not active,Active"
bitfld.long 0x00 20. "  ASB404  ,Active Status Bit 404" "Not active,Active"
textline "                                 "
bitfld.long 0x00 19. " ASB403  ,Active Status Bit 403" "Not active,Active"
bitfld.long 0x00 18. "  ASB402  ,Active Status Bit 402" "Not active,Active"
bitfld.long 0x00 17. "  ASB401  ,Active Status Bit 401" "Not active,Active"
textline "                                 "
bitfld.long 0x00 16. " ASB400  ,Active Status Bit 400" "Not active,Active"
bitfld.long 0x00 15. "  ASB399  ,Active Status Bit 399" "Not active,Active"
bitfld.long 0x00 14. "  ASB398  ,Active Status Bit 398" "Not active,Active"
textline "                                 "
bitfld.long 0x00 13. " ASB397  ,Active Status Bit 397" "Not active,Active"
bitfld.long 0x00 12. "  ASB396  ,Active Status Bit 396" "Not active,Active"
bitfld.long 0x00 11. "  ASB395  ,Active Status Bit 395" "Not active,Active"
textline "                                 "
bitfld.long 0x00 10. " ASB394  ,Active Status Bit 394" "Not active,Active"
bitfld.long 0x00 9. "  ASB393  ,Active Status Bit 393" "Not active,Active"
bitfld.long 0x00 8. "  ASB392  ,Active Status Bit 392" "Not active,Active"
textline "                                 "
bitfld.long 0x00 7. " ASB391  ,Active Status Bit 391" "Not active,Active"
bitfld.long 0x00 6. "  ASB390  ,Active Status Bit 390" "Not active,Active"
bitfld.long 0x00 5. "  ASB389  ,Active Status Bit 389" "Not active,Active"
textline "                                 "
bitfld.long 0x00 4. " ASB388  ,Active Status Bit 388" "Not active,Active"
bitfld.long 0x00 3. "  ASB387  ,Active Status Bit 387" "Not active,Active"
bitfld.long 0x00 2. "  ASB386  ,Active Status Bit 386" "Not active,Active"
textline "                                 "
bitfld.long 0x00 1. " ASB385  ,Active Status Bit 385" "Not active,Active"
bitfld.long 0x00 0. "  ASB384  ,Active Status Bit 384" "Not active,Active"
else
rgroup.long 0x0330++0x03
line.long 0x0 "GICD_ICDABR12,Active Status Register 12"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0D)
rgroup.long 0x0334++0x03
line.long 0x0 "GICD_ICDABR13,Active Status Register 13"
bitfld.long 0x00 31. " ASB447  ,Active Status Bit 447" "Not active,Active"
bitfld.long 0x00 30. "  ASB446  ,Active Status Bit 446" "Not active,Active"
bitfld.long 0x00 29. "  ASB445  ,Active Status Bit 445" "Not active,Active"
textline "                                 "
bitfld.long 0x00 28. " ASB444  ,Active Status Bit 444" "Not active,Active"
bitfld.long 0x00 27. "  ASB443  ,Active Status Bit 443" "Not active,Active"
bitfld.long 0x00 26. "  ASB442  ,Active Status Bit 442" "Not active,Active"
textline "                                 "
bitfld.long 0x00 25. " ASB441  ,Active Status Bit 441" "Not active,Active"
bitfld.long 0x00 24. "  ASB440  ,Active Status Bit 440" "Not active,Active"
bitfld.long 0x00 23. "  ASB439  ,Active Status Bit 439" "Not active,Active"
textline "                                 "
bitfld.long 0x00 22. " ASB438  ,Active Status Bit 438" "Not active,Active"
bitfld.long 0x00 21. "  ASB437  ,Active Status Bit 437" "Not active,Active"
bitfld.long 0x00 20. "  ASB436  ,Active Status Bit 436" "Not active,Active"
textline "                                 "
bitfld.long 0x00 19. " ASB435  ,Active Status Bit 435" "Not active,Active"
bitfld.long 0x00 18. "  ASB434  ,Active Status Bit 434" "Not active,Active"
bitfld.long 0x00 17. "  ASB433  ,Active Status Bit 433" "Not active,Active"
textline "                                 "
bitfld.long 0x00 16. " ASB432  ,Active Status Bit 432" "Not active,Active"
bitfld.long 0x00 15. "  ASB431  ,Active Status Bit 431" "Not active,Active"
bitfld.long 0x00 14. "  ASB430  ,Active Status Bit 430" "Not active,Active"
textline "                                 "
bitfld.long 0x00 13. " ASB429  ,Active Status Bit 429" "Not active,Active"
bitfld.long 0x00 12. "  ASB428  ,Active Status Bit 428" "Not active,Active"
bitfld.long 0x00 11. "  ASB427  ,Active Status Bit 427" "Not active,Active"
textline "                                 "
bitfld.long 0x00 10. " ASB426  ,Active Status Bit 426" "Not active,Active"
bitfld.long 0x00 9. "  ASB425  ,Active Status Bit 425" "Not active,Active"
bitfld.long 0x00 8. "  ASB424  ,Active Status Bit 424" "Not active,Active"
textline "                                 "
bitfld.long 0x00 7. " ASB423  ,Active Status Bit 423" "Not active,Active"
bitfld.long 0x00 6. "  ASB422  ,Active Status Bit 422" "Not active,Active"
bitfld.long 0x00 5. "  ASB421  ,Active Status Bit 421" "Not active,Active"
textline "                                 "
bitfld.long 0x00 4. " ASB420  ,Active Status Bit 420" "Not active,Active"
bitfld.long 0x00 3. "  ASB419  ,Active Status Bit 419" "Not active,Active"
bitfld.long 0x00 2. "  ASB418  ,Active Status Bit 418" "Not active,Active"
textline "                                 "
bitfld.long 0x00 1. " ASB417  ,Active Status Bit 417" "Not active,Active"
bitfld.long 0x00 0. "  ASB416  ,Active Status Bit 416" "Not active,Active"
else
rgroup.long 0x0334++0x03
line.long 0x0 "GICD_ICDABR13,Active Status Register 13"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0E)
rgroup.long 0x0338++0x03
line.long 0x0 "GICD_ICDABR14,Active Status Register 14"
bitfld.long 0x00 31. " ASB479  ,Active Status Bit 479" "Not active,Active"
bitfld.long 0x00 30. "  ASB478  ,Active Status Bit 478" "Not active,Active"
bitfld.long 0x00 29. "  ASB477  ,Active Status Bit 477" "Not active,Active"
textline "                                 "
bitfld.long 0x00 28. " ASB476  ,Active Status Bit 476" "Not active,Active"
bitfld.long 0x00 27. "  ASB475  ,Active Status Bit 475" "Not active,Active"
bitfld.long 0x00 26. "  ASB474  ,Active Status Bit 474" "Not active,Active"
textline "                                 "
bitfld.long 0x00 25. " ASB473  ,Active Status Bit 473" "Not active,Active"
bitfld.long 0x00 24. "  ASB472  ,Active Status Bit 472" "Not active,Active"
bitfld.long 0x00 23. "  ASB471  ,Active Status Bit 471" "Not active,Active"
textline "                                 "
bitfld.long 0x00 22. " ASB470  ,Active Status Bit 470" "Not active,Active"
bitfld.long 0x00 21. "  ASB469  ,Active Status Bit 469" "Not active,Active"
bitfld.long 0x00 20. "  ASB468  ,Active Status Bit 468" "Not active,Active"
textline "                                 "
bitfld.long 0x00 19. " ASB467  ,Active Status Bit 467" "Not active,Active"
bitfld.long 0x00 18. "  ASB466  ,Active Status Bit 466" "Not active,Active"
bitfld.long 0x00 17. "  ASB465  ,Active Status Bit 465" "Not active,Active"
textline "                                 "
bitfld.long 0x00 16. " ASB464  ,Active Status Bit 464" "Not active,Active"
bitfld.long 0x00 15. "  ASB463  ,Active Status Bit 463" "Not active,Active"
bitfld.long 0x00 14. "  ASB462  ,Active Status Bit 462" "Not active,Active"
textline "                                 "
bitfld.long 0x00 13. " ASB461  ,Active Status Bit 461" "Not active,Active"
bitfld.long 0x00 12. "  ASB460  ,Active Status Bit 460" "Not active,Active"
bitfld.long 0x00 11. "  ASB459  ,Active Status Bit 459" "Not active,Active"
textline "                                 "
bitfld.long 0x00 10. " ASB458  ,Active Status Bit 458" "Not active,Active"
bitfld.long 0x00 9. "  ASB457  ,Active Status Bit 457" "Not active,Active"
bitfld.long 0x00 8. "  ASB456  ,Active Status Bit 456" "Not active,Active"
textline "                                 "
bitfld.long 0x00 7. " ASB455  ,Active Status Bit 455" "Not active,Active"
bitfld.long 0x00 6. "  ASB454  ,Active Status Bit 454" "Not active,Active"
bitfld.long 0x00 5. "  ASB453  ,Active Status Bit 453" "Not active,Active"
textline "                                 "
bitfld.long 0x00 4. " ASB452  ,Active Status Bit 452" "Not active,Active"
bitfld.long 0x00 3. "  ASB451  ,Active Status Bit 451" "Not active,Active"
bitfld.long 0x00 2. "  ASB450  ,Active Status Bit 450" "Not active,Active"
textline "                                 "
bitfld.long 0x00 1. " ASB449  ,Active Status Bit 449" "Not active,Active"
bitfld.long 0x00 0. "  ASB448  ,Active Status Bit 448" "Not active,Active"
else
rgroup.long 0x0338++0x03
line.long 0x0 "GICD_ICDABR14,Active Status Register 14"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0F)
rgroup.long 0x033C++0x03
line.long 0x0 "GICD_ICDABR15,Active Status Register 15"
bitfld.long 0x00 31. " ASB511  ,Active Status Bit 511" "Not active,Active"
bitfld.long 0x00 30. "  ASB510  ,Active Status Bit 510" "Not active,Active"
bitfld.long 0x00 29. "  ASB509  ,Active Status Bit 509" "Not active,Active"
textline "                                 "
bitfld.long 0x00 28. " ASB508  ,Active Status Bit 508" "Not active,Active"
bitfld.long 0x00 27. "  ASB507  ,Active Status Bit 507" "Not active,Active"
bitfld.long 0x00 26. "  ASB506  ,Active Status Bit 506" "Not active,Active"
textline "                                 "
bitfld.long 0x00 25. " ASB505  ,Active Status Bit 505" "Not active,Active"
bitfld.long 0x00 24. "  ASB504  ,Active Status Bit 504" "Not active,Active"
bitfld.long 0x00 23. "  ASB503  ,Active Status Bit 503" "Not active,Active"
textline "                                 "
bitfld.long 0x00 22. " ASB502  ,Active Status Bit 502" "Not active,Active"
bitfld.long 0x00 21. "  ASB501  ,Active Status Bit 501" "Not active,Active"
bitfld.long 0x00 20. "  ASB500  ,Active Status Bit 500" "Not active,Active"
textline "                                 "
bitfld.long 0x00 19. " ASB499  ,Active Status Bit 499" "Not active,Active"
bitfld.long 0x00 18. "  ASB498  ,Active Status Bit 498" "Not active,Active"
bitfld.long 0x00 17. "  ASB497  ,Active Status Bit 497" "Not active,Active"
textline "                                 "
bitfld.long 0x00 16. " ASB496  ,Active Status Bit 496" "Not active,Active"
bitfld.long 0x00 15. "  ASB495  ,Active Status Bit 495" "Not active,Active"
bitfld.long 0x00 14. "  ASB494  ,Active Status Bit 494" "Not active,Active"
textline "                                 "
bitfld.long 0x00 13. " ASB493  ,Active Status Bit 493" "Not active,Active"
bitfld.long 0x00 12. "  ASB492  ,Active Status Bit 492" "Not active,Active"
bitfld.long 0x00 11. "  ASB491  ,Active Status Bit 491" "Not active,Active"
textline "                                 "
bitfld.long 0x00 10. " ASB490  ,Active Status Bit 490" "Not active,Active"
bitfld.long 0x00 9. "  ASB489  ,Active Status Bit 489" "Not active,Active"
bitfld.long 0x00 8. "  ASB488  ,Active Status Bit 488" "Not active,Active"
textline "                                 "
bitfld.long 0x00 7. " ASB487  ,Active Status Bit 487" "Not active,Active"
bitfld.long 0x00 6. "  ASB486  ,Active Status Bit 486" "Not active,Active"
bitfld.long 0x00 5. "  ASB485  ,Active Status Bit 485" "Not active,Active"
textline "                                 "
bitfld.long 0x00 4. " ASB484  ,Active Status Bit 484" "Not active,Active"
bitfld.long 0x00 3. "  ASB483  ,Active Status Bit 483" "Not active,Active"
bitfld.long 0x00 2. "  ASB482  ,Active Status Bit 482" "Not active,Active"
textline "                                 "
bitfld.long 0x00 1. " ASB481  ,Active Status Bit 481" "Not active,Active"
bitfld.long 0x00 0. "  ASB480  ,Active Status Bit 480" "Not active,Active"
else
rgroup.long 0x033C++0x03
line.long 0x0 "GICD_ICDABR15,Active Status Register 15"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x10)
rgroup.long 0x0340++0x03
line.long 0x0 "GICD_ICDABR16,Active Status Register 16"
bitfld.long 0x00 31. " ASB543  ,Active Status Bit 543" "Not active,Active"
bitfld.long 0x00 30. "  ASB542  ,Active Status Bit 542" "Not active,Active"
bitfld.long 0x00 29. "  ASB541  ,Active Status Bit 541" "Not active,Active"
textline "                                 "
bitfld.long 0x00 28. " ASB540  ,Active Status Bit 540" "Not active,Active"
bitfld.long 0x00 27. "  ASB539  ,Active Status Bit 539" "Not active,Active"
bitfld.long 0x00 26. "  ASB538  ,Active Status Bit 538" "Not active,Active"
textline "                                 "
bitfld.long 0x00 25. " ASB537  ,Active Status Bit 537" "Not active,Active"
bitfld.long 0x00 24. "  ASB536  ,Active Status Bit 536" "Not active,Active"
bitfld.long 0x00 23. "  ASB535  ,Active Status Bit 535" "Not active,Active"
textline "                                 "
bitfld.long 0x00 22. " ASB534  ,Active Status Bit 534" "Not active,Active"
bitfld.long 0x00 21. "  ASB533  ,Active Status Bit 533" "Not active,Active"
bitfld.long 0x00 20. "  ASB532  ,Active Status Bit 532" "Not active,Active"
textline "                                 "
bitfld.long 0x00 19. " ASB531  ,Active Status Bit 531" "Not active,Active"
bitfld.long 0x00 18. "  ASB530  ,Active Status Bit 530" "Not active,Active"
bitfld.long 0x00 17. "  ASB529  ,Active Status Bit 529" "Not active,Active"
textline "                                 "
bitfld.long 0x00 16. " ASB528  ,Active Status Bit 528" "Not active,Active"
bitfld.long 0x00 15. "  ASB527  ,Active Status Bit 527" "Not active,Active"
bitfld.long 0x00 14. "  ASB526  ,Active Status Bit 526" "Not active,Active"
textline "                                 "
bitfld.long 0x00 13. " ASB525  ,Active Status Bit 525" "Not active,Active"
bitfld.long 0x00 12. "  ASB524  ,Active Status Bit 524" "Not active,Active"
bitfld.long 0x00 11. "  ASB523  ,Active Status Bit 523" "Not active,Active"
textline "                                 "
bitfld.long 0x00 10. " ASB522  ,Active Status Bit 522" "Not active,Active"
bitfld.long 0x00 9. "  ASB521  ,Active Status Bit 521" "Not active,Active"
bitfld.long 0x00 8. "  ASB520  ,Active Status Bit 520" "Not active,Active"
textline "                                 "
bitfld.long 0x00 7. " ASB519  ,Active Status Bit 519" "Not active,Active"
bitfld.long 0x00 6. "  ASB518  ,Active Status Bit 518" "Not active,Active"
bitfld.long 0x00 5. "  ASB517  ,Active Status Bit 517" "Not active,Active"
textline "                                 "
bitfld.long 0x00 4. " ASB516  ,Active Status Bit 516" "Not active,Active"
bitfld.long 0x00 3. "  ASB515  ,Active Status Bit 515" "Not active,Active"
bitfld.long 0x00 2. "  ASB514  ,Active Status Bit 514" "Not active,Active"
textline "                                 "
bitfld.long 0x00 1. " ASB513  ,Active Status Bit 513" "Not active,Active"
bitfld.long 0x00 0. "  ASB512  ,Active Status Bit 512" "Not active,Active"
else
rgroup.long 0x0340++0x03
line.long 0x0 "GICD_ICDABR16,Active Status Register 16"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x11)
rgroup.long 0x0344++0x03
line.long 0x0 "GICD_ICDABR17,Active Status Register 17"
bitfld.long 0x00 31. " ASB575  ,Active Status Bit 575" "Not active,Active"
bitfld.long 0x00 30. "  ASB574  ,Active Status Bit 574" "Not active,Active"
bitfld.long 0x00 29. "  ASB573  ,Active Status Bit 573" "Not active,Active"
textline "                                 "
bitfld.long 0x00 28. " ASB572  ,Active Status Bit 572" "Not active,Active"
bitfld.long 0x00 27. "  ASB571  ,Active Status Bit 571" "Not active,Active"
bitfld.long 0x00 26. "  ASB570  ,Active Status Bit 570" "Not active,Active"
textline "                                 "
bitfld.long 0x00 25. " ASB569  ,Active Status Bit 569" "Not active,Active"
bitfld.long 0x00 24. "  ASB568  ,Active Status Bit 568" "Not active,Active"
bitfld.long 0x00 23. "  ASB567  ,Active Status Bit 567" "Not active,Active"
textline "                                 "
bitfld.long 0x00 22. " ASB566  ,Active Status Bit 566" "Not active,Active"
bitfld.long 0x00 21. "  ASB565  ,Active Status Bit 565" "Not active,Active"
bitfld.long 0x00 20. "  ASB564  ,Active Status Bit 564" "Not active,Active"
textline "                                 "
bitfld.long 0x00 19. " ASB563  ,Active Status Bit 563" "Not active,Active"
bitfld.long 0x00 18. "  ASB562  ,Active Status Bit 562" "Not active,Active"
bitfld.long 0x00 17. "  ASB561  ,Active Status Bit 561" "Not active,Active"
textline "                                 "
bitfld.long 0x00 16. " ASB560  ,Active Status Bit 560" "Not active,Active"
bitfld.long 0x00 15. "  ASB559  ,Active Status Bit 559" "Not active,Active"
bitfld.long 0x00 14. "  ASB558  ,Active Status Bit 558" "Not active,Active"
textline "                                 "
bitfld.long 0x00 13. " ASB557  ,Active Status Bit 557" "Not active,Active"
bitfld.long 0x00 12. "  ASB556  ,Active Status Bit 556" "Not active,Active"
bitfld.long 0x00 11. "  ASB555  ,Active Status Bit 555" "Not active,Active"
textline "                                 "
bitfld.long 0x00 10. " ASB554  ,Active Status Bit 554" "Not active,Active"
bitfld.long 0x00 9. "  ASB553  ,Active Status Bit 553" "Not active,Active"
bitfld.long 0x00 8. "  ASB552  ,Active Status Bit 552" "Not active,Active"
textline "                                 "
bitfld.long 0x00 7. " ASB551  ,Active Status Bit 551" "Not active,Active"
bitfld.long 0x00 6. "  ASB550  ,Active Status Bit 550" "Not active,Active"
bitfld.long 0x00 5. "  ASB549  ,Active Status Bit 549" "Not active,Active"
textline "                                 "
bitfld.long 0x00 4. " ASB548  ,Active Status Bit 548" "Not active,Active"
bitfld.long 0x00 3. "  ASB547  ,Active Status Bit 547" "Not active,Active"
bitfld.long 0x00 2. "  ASB546  ,Active Status Bit 546" "Not active,Active"
textline "                                 "
bitfld.long 0x00 1. " ASB545  ,Active Status Bit 545" "Not active,Active"
bitfld.long 0x00 0. "  ASB544  ,Active Status Bit 544" "Not active,Active"
else
rgroup.long 0x0344++0x03
line.long 0x0 "GICD_ICDABR17,Active Status Register 17"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x12)
rgroup.long 0x0348++0x03
line.long 0x0 "GICD_ICDABR18,Active Status Register 18"
bitfld.long 0x00 31. " ASB607  ,Active Status Bit 607" "Not active,Active"
bitfld.long 0x00 30. "  ASB606  ,Active Status Bit 606" "Not active,Active"
bitfld.long 0x00 29. "  ASB605  ,Active Status Bit 605" "Not active,Active"
textline "                                 "
bitfld.long 0x00 28. " ASB604  ,Active Status Bit 604" "Not active,Active"
bitfld.long 0x00 27. "  ASB603  ,Active Status Bit 603" "Not active,Active"
bitfld.long 0x00 26. "  ASB602  ,Active Status Bit 602" "Not active,Active"
textline "                                 "
bitfld.long 0x00 25. " ASB601  ,Active Status Bit 601" "Not active,Active"
bitfld.long 0x00 24. "  ASB600  ,Active Status Bit 600" "Not active,Active"
bitfld.long 0x00 23. "  ASB599  ,Active Status Bit 599" "Not active,Active"
textline "                                 "
bitfld.long 0x00 22. " ASB598  ,Active Status Bit 598" "Not active,Active"
bitfld.long 0x00 21. "  ASB597  ,Active Status Bit 597" "Not active,Active"
bitfld.long 0x00 20. "  ASB596  ,Active Status Bit 596" "Not active,Active"
textline "                                 "
bitfld.long 0x00 19. " ASB595  ,Active Status Bit 595" "Not active,Active"
bitfld.long 0x00 18. "  ASB594  ,Active Status Bit 594" "Not active,Active"
bitfld.long 0x00 17. "  ASB593  ,Active Status Bit 593" "Not active,Active"
textline "                                 "
bitfld.long 0x00 16. " ASB592  ,Active Status Bit 592" "Not active,Active"
bitfld.long 0x00 15. "  ASB591  ,Active Status Bit 591" "Not active,Active"
bitfld.long 0x00 14. "  ASB590  ,Active Status Bit 590" "Not active,Active"
textline "                                 "
bitfld.long 0x00 13. " ASB589  ,Active Status Bit 589" "Not active,Active"
bitfld.long 0x00 12. "  ASB588  ,Active Status Bit 588" "Not active,Active"
bitfld.long 0x00 11. "  ASB587  ,Active Status Bit 587" "Not active,Active"
textline "                                 "
bitfld.long 0x00 10. " ASB586  ,Active Status Bit 586" "Not active,Active"
bitfld.long 0x00 9. "  ASB585  ,Active Status Bit 585" "Not active,Active"
bitfld.long 0x00 8. "  ASB584  ,Active Status Bit 584" "Not active,Active"
textline "                                 "
bitfld.long 0x00 7. " ASB583  ,Active Status Bit 583" "Not active,Active"
bitfld.long 0x00 6. "  ASB582  ,Active Status Bit 582" "Not active,Active"
bitfld.long 0x00 5. "  ASB581  ,Active Status Bit 581" "Not active,Active"
textline "                                 "
bitfld.long 0x00 4. " ASB580  ,Active Status Bit 580" "Not active,Active"
bitfld.long 0x00 3. "  ASB579  ,Active Status Bit 579" "Not active,Active"
bitfld.long 0x00 2. "  ASB578  ,Active Status Bit 578" "Not active,Active"
textline "                                 "
bitfld.long 0x00 1. " ASB577  ,Active Status Bit 577" "Not active,Active"
bitfld.long 0x00 0. "  ASB576  ,Active Status Bit 576" "Not active,Active"
else
rgroup.long 0x0348++0x03
line.long 0x0 "GICD_ICDABR18,Active Status Register 18"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x13)
rgroup.long 0x034C++0x03
line.long 0x0 "GICD_ICDABR19,Active Status Register 19"
bitfld.long 0x00 31. " ASB639  ,Active Status Bit 639" "Not active,Active"
bitfld.long 0x00 30. "  ASB638  ,Active Status Bit 638" "Not active,Active"
bitfld.long 0x00 29. "  ASB637  ,Active Status Bit 637" "Not active,Active"
textline "                                 "
bitfld.long 0x00 28. " ASB636  ,Active Status Bit 636" "Not active,Active"
bitfld.long 0x00 27. "  ASB635  ,Active Status Bit 635" "Not active,Active"
bitfld.long 0x00 26. "  ASB634  ,Active Status Bit 634" "Not active,Active"
textline "                                 "
bitfld.long 0x00 25. " ASB633  ,Active Status Bit 633" "Not active,Active"
bitfld.long 0x00 24. "  ASB632  ,Active Status Bit 632" "Not active,Active"
bitfld.long 0x00 23. "  ASB631  ,Active Status Bit 631" "Not active,Active"
textline "                                 "
bitfld.long 0x00 22. " ASB630  ,Active Status Bit 630" "Not active,Active"
bitfld.long 0x00 21. "  ASB629  ,Active Status Bit 629" "Not active,Active"
bitfld.long 0x00 20. "  ASB628  ,Active Status Bit 628" "Not active,Active"
textline "                                 "
bitfld.long 0x00 19. " ASB627  ,Active Status Bit 627" "Not active,Active"
bitfld.long 0x00 18. "  ASB626  ,Active Status Bit 626" "Not active,Active"
bitfld.long 0x00 17. "  ASB625  ,Active Status Bit 625" "Not active,Active"
textline "                                 "
bitfld.long 0x00 16. " ASB624  ,Active Status Bit 624" "Not active,Active"
bitfld.long 0x00 15. "  ASB623  ,Active Status Bit 623" "Not active,Active"
bitfld.long 0x00 14. "  ASB622  ,Active Status Bit 622" "Not active,Active"
textline "                                 "
bitfld.long 0x00 13. " ASB621  ,Active Status Bit 621" "Not active,Active"
bitfld.long 0x00 12. "  ASB620  ,Active Status Bit 620" "Not active,Active"
bitfld.long 0x00 11. "  ASB619  ,Active Status Bit 619" "Not active,Active"
textline "                                 "
bitfld.long 0x00 10. " ASB618  ,Active Status Bit 618" "Not active,Active"
bitfld.long 0x00 9. "  ASB617  ,Active Status Bit 617" "Not active,Active"
bitfld.long 0x00 8. "  ASB616  ,Active Status Bit 616" "Not active,Active"
textline "                                 "
bitfld.long 0x00 7. " ASB615  ,Active Status Bit 615" "Not active,Active"
bitfld.long 0x00 6. "  ASB614  ,Active Status Bit 614" "Not active,Active"
bitfld.long 0x00 5. "  ASB613  ,Active Status Bit 613" "Not active,Active"
textline "                                 "
bitfld.long 0x00 4. " ASB612  ,Active Status Bit 612" "Not active,Active"
bitfld.long 0x00 3. "  ASB611  ,Active Status Bit 611" "Not active,Active"
bitfld.long 0x00 2. "  ASB610  ,Active Status Bit 610" "Not active,Active"
textline "                                 "
bitfld.long 0x00 1. " ASB609  ,Active Status Bit 609" "Not active,Active"
bitfld.long 0x00 0. "  ASB608  ,Active Status Bit 608" "Not active,Active"
else
rgroup.long 0x034C++0x03
line.long 0x0 "GICD_ICDABR19,Active Status Register 19"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x14)
rgroup.long 0x0350++0x03
line.long 0x0 "GICD_ICDABR20,Active Status Register 20"
bitfld.long 0x00 31. " ASB671  ,Active Status Bit 671" "Not active,Active"
bitfld.long 0x00 30. "  ASB670  ,Active Status Bit 670" "Not active,Active"
bitfld.long 0x00 29. "  ASB669  ,Active Status Bit 669" "Not active,Active"
textline "                                 "
bitfld.long 0x00 28. " ASB668  ,Active Status Bit 668" "Not active,Active"
bitfld.long 0x00 27. "  ASB667  ,Active Status Bit 667" "Not active,Active"
bitfld.long 0x00 26. "  ASB666  ,Active Status Bit 666" "Not active,Active"
textline "                                 "
bitfld.long 0x00 25. " ASB665  ,Active Status Bit 665" "Not active,Active"
bitfld.long 0x00 24. "  ASB664  ,Active Status Bit 664" "Not active,Active"
bitfld.long 0x00 23. "  ASB663  ,Active Status Bit 663" "Not active,Active"
textline "                                 "
bitfld.long 0x00 22. " ASB662  ,Active Status Bit 662" "Not active,Active"
bitfld.long 0x00 21. "  ASB661  ,Active Status Bit 661" "Not active,Active"
bitfld.long 0x00 20. "  ASB660  ,Active Status Bit 660" "Not active,Active"
textline "                                 "
bitfld.long 0x00 19. " ASB659  ,Active Status Bit 659" "Not active,Active"
bitfld.long 0x00 18. "  ASB658  ,Active Status Bit 658" "Not active,Active"
bitfld.long 0x00 17. "  ASB657  ,Active Status Bit 657" "Not active,Active"
textline "                                 "
bitfld.long 0x00 16. " ASB656  ,Active Status Bit 656" "Not active,Active"
bitfld.long 0x00 15. "  ASB655  ,Active Status Bit 655" "Not active,Active"
bitfld.long 0x00 14. "  ASB654  ,Active Status Bit 654" "Not active,Active"
textline "                                 "
bitfld.long 0x00 13. " ASB653  ,Active Status Bit 653" "Not active,Active"
bitfld.long 0x00 12. "  ASB652  ,Active Status Bit 652" "Not active,Active"
bitfld.long 0x00 11. "  ASB651  ,Active Status Bit 651" "Not active,Active"
textline "                                 "
bitfld.long 0x00 10. " ASB650  ,Active Status Bit 650" "Not active,Active"
bitfld.long 0x00 9. "  ASB649  ,Active Status Bit 649" "Not active,Active"
bitfld.long 0x00 8. "  ASB648  ,Active Status Bit 648" "Not active,Active"
textline "                                 "
bitfld.long 0x00 7. " ASB647  ,Active Status Bit 647" "Not active,Active"
bitfld.long 0x00 6. "  ASB646  ,Active Status Bit 646" "Not active,Active"
bitfld.long 0x00 5. "  ASB645  ,Active Status Bit 645" "Not active,Active"
textline "                                 "
bitfld.long 0x00 4. " ASB644  ,Active Status Bit 644" "Not active,Active"
bitfld.long 0x00 3. "  ASB643  ,Active Status Bit 643" "Not active,Active"
bitfld.long 0x00 2. "  ASB642  ,Active Status Bit 642" "Not active,Active"
textline "                                 "
bitfld.long 0x00 1. " ASB641  ,Active Status Bit 641" "Not active,Active"
bitfld.long 0x00 0. "  ASB640  ,Active Status Bit 640" "Not active,Active"
else
rgroup.long 0x0350++0x03
line.long 0x0 "GICD_ICDABR20,Active Status Register 20"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x15)
rgroup.long 0x0354++0x03
line.long 0x0 "GICD_ICDABR21,Active Status Register 21"
bitfld.long 0x00 31. " ASB703  ,Active Status Bit 703" "Not active,Active"
bitfld.long 0x00 30. "  ASB702  ,Active Status Bit 702" "Not active,Active"
bitfld.long 0x00 29. "  ASB701  ,Active Status Bit 701" "Not active,Active"
textline "                                 "
bitfld.long 0x00 28. " ASB700  ,Active Status Bit 700" "Not active,Active"
bitfld.long 0x00 27. "  ASB699  ,Active Status Bit 699" "Not active,Active"
bitfld.long 0x00 26. "  ASB698  ,Active Status Bit 698" "Not active,Active"
textline "                                 "
bitfld.long 0x00 25. " ASB697  ,Active Status Bit 697" "Not active,Active"
bitfld.long 0x00 24. "  ASB696  ,Active Status Bit 696" "Not active,Active"
bitfld.long 0x00 23. "  ASB695  ,Active Status Bit 695" "Not active,Active"
textline "                                 "
bitfld.long 0x00 22. " ASB694  ,Active Status Bit 694" "Not active,Active"
bitfld.long 0x00 21. "  ASB693  ,Active Status Bit 693" "Not active,Active"
bitfld.long 0x00 20. "  ASB692  ,Active Status Bit 692" "Not active,Active"
textline "                                 "
bitfld.long 0x00 19. " ASB691  ,Active Status Bit 691" "Not active,Active"
bitfld.long 0x00 18. "  ASB690  ,Active Status Bit 690" "Not active,Active"
bitfld.long 0x00 17. "  ASB689  ,Active Status Bit 689" "Not active,Active"
textline "                                 "
bitfld.long 0x00 16. " ASB688  ,Active Status Bit 688" "Not active,Active"
bitfld.long 0x00 15. "  ASB687  ,Active Status Bit 687" "Not active,Active"
bitfld.long 0x00 14. "  ASB686  ,Active Status Bit 686" "Not active,Active"
textline "                                 "
bitfld.long 0x00 13. " ASB685  ,Active Status Bit 685" "Not active,Active"
bitfld.long 0x00 12. "  ASB684  ,Active Status Bit 684" "Not active,Active"
bitfld.long 0x00 11. "  ASB683  ,Active Status Bit 683" "Not active,Active"
textline "                                 "
bitfld.long 0x00 10. " ASB682  ,Active Status Bit 682" "Not active,Active"
bitfld.long 0x00 9. "  ASB681  ,Active Status Bit 681" "Not active,Active"
bitfld.long 0x00 8. "  ASB680  ,Active Status Bit 680" "Not active,Active"
textline "                                 "
bitfld.long 0x00 7. " ASB679  ,Active Status Bit 679" "Not active,Active"
bitfld.long 0x00 6. "  ASB678  ,Active Status Bit 678" "Not active,Active"
bitfld.long 0x00 5. "  ASB677  ,Active Status Bit 677" "Not active,Active"
textline "                                 "
bitfld.long 0x00 4. " ASB676  ,Active Status Bit 676" "Not active,Active"
bitfld.long 0x00 3. "  ASB675  ,Active Status Bit 675" "Not active,Active"
bitfld.long 0x00 2. "  ASB674  ,Active Status Bit 674" "Not active,Active"
textline "                                 "
bitfld.long 0x00 1. " ASB673  ,Active Status Bit 673" "Not active,Active"
bitfld.long 0x00 0. "  ASB672  ,Active Status Bit 672" "Not active,Active"
else
rgroup.long 0x0354++0x03
line.long 0x0 "GICD_ICDABR21,Active Status Register 21"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x16)
rgroup.long 0x0358++0x03
line.long 0x0 "GICD_ICDABR22,Active Status Register 22"
bitfld.long 0x00 31. " ASB735  ,Active Status Bit 735" "Not active,Active"
bitfld.long 0x00 30. "  ASB734  ,Active Status Bit 734" "Not active,Active"
bitfld.long 0x00 29. "  ASB733  ,Active Status Bit 733" "Not active,Active"
textline "                                 "
bitfld.long 0x00 28. " ASB732  ,Active Status Bit 732" "Not active,Active"
bitfld.long 0x00 27. "  ASB731  ,Active Status Bit 731" "Not active,Active"
bitfld.long 0x00 26. "  ASB730  ,Active Status Bit 730" "Not active,Active"
textline "                                 "
bitfld.long 0x00 25. " ASB729  ,Active Status Bit 729" "Not active,Active"
bitfld.long 0x00 24. "  ASB728  ,Active Status Bit 728" "Not active,Active"
bitfld.long 0x00 23. "  ASB727  ,Active Status Bit 727" "Not active,Active"
textline "                                 "
bitfld.long 0x00 22. " ASB726  ,Active Status Bit 726" "Not active,Active"
bitfld.long 0x00 21. "  ASB725  ,Active Status Bit 725" "Not active,Active"
bitfld.long 0x00 20. "  ASB724  ,Active Status Bit 724" "Not active,Active"
textline "                                 "
bitfld.long 0x00 19. " ASB723  ,Active Status Bit 723" "Not active,Active"
bitfld.long 0x00 18. "  ASB722  ,Active Status Bit 722" "Not active,Active"
bitfld.long 0x00 17. "  ASB721  ,Active Status Bit 721" "Not active,Active"
textline "                                 "
bitfld.long 0x00 16. " ASB720  ,Active Status Bit 720" "Not active,Active"
bitfld.long 0x00 15. "  ASB719  ,Active Status Bit 719" "Not active,Active"
bitfld.long 0x00 14. "  ASB718  ,Active Status Bit 718" "Not active,Active"
textline "                                 "
bitfld.long 0x00 13. " ASB717  ,Active Status Bit 717" "Not active,Active"
bitfld.long 0x00 12. "  ASB716  ,Active Status Bit 716" "Not active,Active"
bitfld.long 0x00 11. "  ASB715  ,Active Status Bit 715" "Not active,Active"
textline "                                 "
bitfld.long 0x00 10. " ASB714  ,Active Status Bit 714" "Not active,Active"
bitfld.long 0x00 9. "  ASB713  ,Active Status Bit 713" "Not active,Active"
bitfld.long 0x00 8. "  ASB712  ,Active Status Bit 712" "Not active,Active"
textline "                                 "
bitfld.long 0x00 7. " ASB711  ,Active Status Bit 711" "Not active,Active"
bitfld.long 0x00 6. "  ASB710  ,Active Status Bit 710" "Not active,Active"
bitfld.long 0x00 5. "  ASB709  ,Active Status Bit 709" "Not active,Active"
textline "                                 "
bitfld.long 0x00 4. " ASB708  ,Active Status Bit 708" "Not active,Active"
bitfld.long 0x00 3. "  ASB707  ,Active Status Bit 707" "Not active,Active"
bitfld.long 0x00 2. "  ASB706  ,Active Status Bit 706" "Not active,Active"
textline "                                 "
bitfld.long 0x00 1. " ASB705  ,Active Status Bit 705" "Not active,Active"
bitfld.long 0x00 0. "  ASB704  ,Active Status Bit 704" "Not active,Active"
else
rgroup.long 0x0358++0x03
line.long 0x0 "GICD_ICDABR22,Active Status Register 22"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x17)
rgroup.long 0x035C++0x03
line.long 0x0 "GICD_ICDABR23,Active Status Register 23"
bitfld.long 0x00 31. " ASB767  ,Active Status Bit 767" "Not active,Active"
bitfld.long 0x00 30. "  ASB766  ,Active Status Bit 766" "Not active,Active"
bitfld.long 0x00 29. "  ASB765  ,Active Status Bit 765" "Not active,Active"
textline "                                 "
bitfld.long 0x00 28. " ASB764  ,Active Status Bit 764" "Not active,Active"
bitfld.long 0x00 27. "  ASB763  ,Active Status Bit 763" "Not active,Active"
bitfld.long 0x00 26. "  ASB762  ,Active Status Bit 762" "Not active,Active"
textline "                                 "
bitfld.long 0x00 25. " ASB761  ,Active Status Bit 761" "Not active,Active"
bitfld.long 0x00 24. "  ASB760  ,Active Status Bit 760" "Not active,Active"
bitfld.long 0x00 23. "  ASB759  ,Active Status Bit 759" "Not active,Active"
textline "                                 "
bitfld.long 0x00 22. " ASB758  ,Active Status Bit 758" "Not active,Active"
bitfld.long 0x00 21. "  ASB757  ,Active Status Bit 757" "Not active,Active"
bitfld.long 0x00 20. "  ASB756  ,Active Status Bit 756" "Not active,Active"
textline "                                 "
bitfld.long 0x00 19. " ASB755  ,Active Status Bit 755" "Not active,Active"
bitfld.long 0x00 18. "  ASB754  ,Active Status Bit 754" "Not active,Active"
bitfld.long 0x00 17. "  ASB753  ,Active Status Bit 753" "Not active,Active"
textline "                                 "
bitfld.long 0x00 16. " ASB752  ,Active Status Bit 752" "Not active,Active"
bitfld.long 0x00 15. "  ASB751  ,Active Status Bit 751" "Not active,Active"
bitfld.long 0x00 14. "  ASB750  ,Active Status Bit 750" "Not active,Active"
textline "                                 "
bitfld.long 0x00 13. " ASB749  ,Active Status Bit 749" "Not active,Active"
bitfld.long 0x00 12. "  ASB748  ,Active Status Bit 748" "Not active,Active"
bitfld.long 0x00 11. "  ASB747  ,Active Status Bit 747" "Not active,Active"
textline "                                 "
bitfld.long 0x00 10. " ASB746  ,Active Status Bit 746" "Not active,Active"
bitfld.long 0x00 9. "  ASB745  ,Active Status Bit 745" "Not active,Active"
bitfld.long 0x00 8. "  ASB744  ,Active Status Bit 744" "Not active,Active"
textline "                                 "
bitfld.long 0x00 7. " ASB743  ,Active Status Bit 743" "Not active,Active"
bitfld.long 0x00 6. "  ASB742  ,Active Status Bit 742" "Not active,Active"
bitfld.long 0x00 5. "  ASB741  ,Active Status Bit 741" "Not active,Active"
textline "                                 "
bitfld.long 0x00 4. " ASB740  ,Active Status Bit 740" "Not active,Active"
bitfld.long 0x00 3. "  ASB739  ,Active Status Bit 739" "Not active,Active"
bitfld.long 0x00 2. "  ASB738  ,Active Status Bit 738" "Not active,Active"
textline "                                 "
bitfld.long 0x00 1. " ASB737  ,Active Status Bit 737" "Not active,Active"
bitfld.long 0x00 0. "  ASB736  ,Active Status Bit 736" "Not active,Active"
else
rgroup.long 0x035C++0x03
line.long 0x0 "GICD_ICDABR23,Active Status Register 23"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x18)
rgroup.long 0x0360++0x03
line.long 0x0 "GICD_ICDABR24,Active Status Register 24"
bitfld.long 0x00 31. " ASB799  ,Active Status Bit 799" "Not active,Active"
bitfld.long 0x00 30. "  ASB798  ,Active Status Bit 798" "Not active,Active"
bitfld.long 0x00 29. "  ASB797  ,Active Status Bit 797" "Not active,Active"
textline "                                 "
bitfld.long 0x00 28. " ASB796  ,Active Status Bit 796" "Not active,Active"
bitfld.long 0x00 27. "  ASB795  ,Active Status Bit 795" "Not active,Active"
bitfld.long 0x00 26. "  ASB794  ,Active Status Bit 794" "Not active,Active"
textline "                                 "
bitfld.long 0x00 25. " ASB793  ,Active Status Bit 793" "Not active,Active"
bitfld.long 0x00 24. "  ASB792  ,Active Status Bit 792" "Not active,Active"
bitfld.long 0x00 23. "  ASB791  ,Active Status Bit 791" "Not active,Active"
textline "                                 "
bitfld.long 0x00 22. " ASB790  ,Active Status Bit 790" "Not active,Active"
bitfld.long 0x00 21. "  ASB789  ,Active Status Bit 789" "Not active,Active"
bitfld.long 0x00 20. "  ASB788  ,Active Status Bit 788" "Not active,Active"
textline "                                 "
bitfld.long 0x00 19. " ASB787  ,Active Status Bit 787" "Not active,Active"
bitfld.long 0x00 18. "  ASB786  ,Active Status Bit 786" "Not active,Active"
bitfld.long 0x00 17. "  ASB785  ,Active Status Bit 785" "Not active,Active"
textline "                                 "
bitfld.long 0x00 16. " ASB784  ,Active Status Bit 784" "Not active,Active"
bitfld.long 0x00 15. "  ASB783  ,Active Status Bit 783" "Not active,Active"
bitfld.long 0x00 14. "  ASB782  ,Active Status Bit 782" "Not active,Active"
textline "                                 "
bitfld.long 0x00 13. " ASB781  ,Active Status Bit 781" "Not active,Active"
bitfld.long 0x00 12. "  ASB780  ,Active Status Bit 780" "Not active,Active"
bitfld.long 0x00 11. "  ASB779  ,Active Status Bit 779" "Not active,Active"
textline "                                 "
bitfld.long 0x00 10. " ASB778  ,Active Status Bit 778" "Not active,Active"
bitfld.long 0x00 9. "  ASB777  ,Active Status Bit 777" "Not active,Active"
bitfld.long 0x00 8. "  ASB776  ,Active Status Bit 776" "Not active,Active"
textline "                                 "
bitfld.long 0x00 7. " ASB775  ,Active Status Bit 775" "Not active,Active"
bitfld.long 0x00 6. "  ASB774  ,Active Status Bit 774" "Not active,Active"
bitfld.long 0x00 5. "  ASB773  ,Active Status Bit 773" "Not active,Active"
textline "                                 "
bitfld.long 0x00 4. " ASB772  ,Active Status Bit 772" "Not active,Active"
bitfld.long 0x00 3. "  ASB771  ,Active Status Bit 771" "Not active,Active"
bitfld.long 0x00 2. "  ASB770  ,Active Status Bit 770" "Not active,Active"
textline "                                 "
bitfld.long 0x00 1. " ASB769  ,Active Status Bit 769" "Not active,Active"
bitfld.long 0x00 0. "  ASB768  ,Active Status Bit 768" "Not active,Active"
else
rgroup.long 0x0360++0x03
line.long 0x0 "GICD_ICDABR24,Active Status Register 24"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x19)
rgroup.long 0x0364++0x03
line.long 0x0 "GICD_ICDABR25,Active Status Register 25"
bitfld.long 0x00 31. " ASB831  ,Active Status Bit 831" "Not active,Active"
bitfld.long 0x00 30. "  ASB830  ,Active Status Bit 830" "Not active,Active"
bitfld.long 0x00 29. "  ASB829  ,Active Status Bit 829" "Not active,Active"
textline "                                 "
bitfld.long 0x00 28. " ASB828  ,Active Status Bit 828" "Not active,Active"
bitfld.long 0x00 27. "  ASB827  ,Active Status Bit 827" "Not active,Active"
bitfld.long 0x00 26. "  ASB826  ,Active Status Bit 826" "Not active,Active"
textline "                                 "
bitfld.long 0x00 25. " ASB825  ,Active Status Bit 825" "Not active,Active"
bitfld.long 0x00 24. "  ASB824  ,Active Status Bit 824" "Not active,Active"
bitfld.long 0x00 23. "  ASB823  ,Active Status Bit 823" "Not active,Active"
textline "                                 "
bitfld.long 0x00 22. " ASB822  ,Active Status Bit 822" "Not active,Active"
bitfld.long 0x00 21. "  ASB821  ,Active Status Bit 821" "Not active,Active"
bitfld.long 0x00 20. "  ASB820  ,Active Status Bit 820" "Not active,Active"
textline "                                 "
bitfld.long 0x00 19. " ASB819  ,Active Status Bit 819" "Not active,Active"
bitfld.long 0x00 18. "  ASB818  ,Active Status Bit 818" "Not active,Active"
bitfld.long 0x00 17. "  ASB817  ,Active Status Bit 817" "Not active,Active"
textline "                                 "
bitfld.long 0x00 16. " ASB816  ,Active Status Bit 816" "Not active,Active"
bitfld.long 0x00 15. "  ASB815  ,Active Status Bit 815" "Not active,Active"
bitfld.long 0x00 14. "  ASB814  ,Active Status Bit 814" "Not active,Active"
textline "                                 "
bitfld.long 0x00 13. " ASB813  ,Active Status Bit 813" "Not active,Active"
bitfld.long 0x00 12. "  ASB812  ,Active Status Bit 812" "Not active,Active"
bitfld.long 0x00 11. "  ASB811  ,Active Status Bit 811" "Not active,Active"
textline "                                 "
bitfld.long 0x00 10. " ASB810  ,Active Status Bit 810" "Not active,Active"
bitfld.long 0x00 9. "  ASB809  ,Active Status Bit 809" "Not active,Active"
bitfld.long 0x00 8. "  ASB808  ,Active Status Bit 808" "Not active,Active"
textline "                                 "
bitfld.long 0x00 7. " ASB807  ,Active Status Bit 807" "Not active,Active"
bitfld.long 0x00 6. "  ASB806  ,Active Status Bit 806" "Not active,Active"
bitfld.long 0x00 5. "  ASB805  ,Active Status Bit 805" "Not active,Active"
textline "                                 "
bitfld.long 0x00 4. " ASB804  ,Active Status Bit 804" "Not active,Active"
bitfld.long 0x00 3. "  ASB803  ,Active Status Bit 803" "Not active,Active"
bitfld.long 0x00 2. "  ASB802  ,Active Status Bit 802" "Not active,Active"
textline "                                 "
bitfld.long 0x00 1. " ASB801  ,Active Status Bit 801" "Not active,Active"
bitfld.long 0x00 0. "  ASB800  ,Active Status Bit 800" "Not active,Active"
else
rgroup.long 0x0364++0x03
line.long 0x0 "GICD_ICDABR25,Active Status Register 25"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1A)
rgroup.long 0x0368++0x03
line.long 0x0 "GICD_ICDABR26,Active Status Register 26"
bitfld.long 0x00 31. " ASB863  ,Active Status Bit 863" "Not active,Active"
bitfld.long 0x00 30. "  ASB862  ,Active Status Bit 862" "Not active,Active"
bitfld.long 0x00 29. "  ASB861  ,Active Status Bit 861" "Not active,Active"
textline "                                 "
bitfld.long 0x00 28. " ASB860  ,Active Status Bit 860" "Not active,Active"
bitfld.long 0x00 27. "  ASB859  ,Active Status Bit 859" "Not active,Active"
bitfld.long 0x00 26. "  ASB858  ,Active Status Bit 858" "Not active,Active"
textline "                                 "
bitfld.long 0x00 25. " ASB857  ,Active Status Bit 857" "Not active,Active"
bitfld.long 0x00 24. "  ASB856  ,Active Status Bit 856" "Not active,Active"
bitfld.long 0x00 23. "  ASB855  ,Active Status Bit 855" "Not active,Active"
textline "                                 "
bitfld.long 0x00 22. " ASB854  ,Active Status Bit 854" "Not active,Active"
bitfld.long 0x00 21. "  ASB853  ,Active Status Bit 853" "Not active,Active"
bitfld.long 0x00 20. "  ASB852  ,Active Status Bit 852" "Not active,Active"
textline "                                 "
bitfld.long 0x00 19. " ASB851  ,Active Status Bit 851" "Not active,Active"
bitfld.long 0x00 18. "  ASB850  ,Active Status Bit 850" "Not active,Active"
bitfld.long 0x00 17. "  ASB849  ,Active Status Bit 849" "Not active,Active"
textline "                                 "
bitfld.long 0x00 16. " ASB848  ,Active Status Bit 848" "Not active,Active"
bitfld.long 0x00 15. "  ASB847  ,Active Status Bit 847" "Not active,Active"
bitfld.long 0x00 14. "  ASB846  ,Active Status Bit 846" "Not active,Active"
textline "                                 "
bitfld.long 0x00 13. " ASB845  ,Active Status Bit 845" "Not active,Active"
bitfld.long 0x00 12. "  ASB844  ,Active Status Bit 844" "Not active,Active"
bitfld.long 0x00 11. "  ASB843  ,Active Status Bit 843" "Not active,Active"
textline "                                 "
bitfld.long 0x00 10. " ASB842  ,Active Status Bit 842" "Not active,Active"
bitfld.long 0x00 9. "  ASB841  ,Active Status Bit 841" "Not active,Active"
bitfld.long 0x00 8. "  ASB840  ,Active Status Bit 840" "Not active,Active"
textline "                                 "
bitfld.long 0x00 7. " ASB839  ,Active Status Bit 839" "Not active,Active"
bitfld.long 0x00 6. "  ASB838  ,Active Status Bit 838" "Not active,Active"
bitfld.long 0x00 5. "  ASB837  ,Active Status Bit 837" "Not active,Active"
textline "                                 "
bitfld.long 0x00 4. " ASB836  ,Active Status Bit 836" "Not active,Active"
bitfld.long 0x00 3. "  ASB835  ,Active Status Bit 835" "Not active,Active"
bitfld.long 0x00 2. "  ASB834  ,Active Status Bit 834" "Not active,Active"
textline "                                 "
bitfld.long 0x00 1. " ASB833  ,Active Status Bit 833" "Not active,Active"
bitfld.long 0x00 0. "  ASB832  ,Active Status Bit 832" "Not active,Active"
else
rgroup.long 0x0368++0x03
line.long 0x0 "GICD_ICDABR26,Active Status Register 26"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1B)
rgroup.long 0x036C++0x03
line.long 0x0 "GICD_ICDABR27,Active Status Register 27"
bitfld.long 0x00 31. " ASB895  ,Active Status Bit 895" "Not active,Active"
bitfld.long 0x00 30. "  ASB894  ,Active Status Bit 894" "Not active,Active"
bitfld.long 0x00 29. "  ASB893  ,Active Status Bit 893" "Not active,Active"
textline "                                 "
bitfld.long 0x00 28. " ASB892  ,Active Status Bit 892" "Not active,Active"
bitfld.long 0x00 27. "  ASB891  ,Active Status Bit 891" "Not active,Active"
bitfld.long 0x00 26. "  ASB890  ,Active Status Bit 890" "Not active,Active"
textline "                                 "
bitfld.long 0x00 25. " ASB889  ,Active Status Bit 889" "Not active,Active"
bitfld.long 0x00 24. "  ASB888  ,Active Status Bit 888" "Not active,Active"
bitfld.long 0x00 23. "  ASB887  ,Active Status Bit 887" "Not active,Active"
textline "                                 "
bitfld.long 0x00 22. " ASB886  ,Active Status Bit 886" "Not active,Active"
bitfld.long 0x00 21. "  ASB885  ,Active Status Bit 885" "Not active,Active"
bitfld.long 0x00 20. "  ASB884  ,Active Status Bit 884" "Not active,Active"
textline "                                 "
bitfld.long 0x00 19. " ASB883  ,Active Status Bit 883" "Not active,Active"
bitfld.long 0x00 18. "  ASB882  ,Active Status Bit 882" "Not active,Active"
bitfld.long 0x00 17. "  ASB881  ,Active Status Bit 881" "Not active,Active"
textline "                                 "
bitfld.long 0x00 16. " ASB880  ,Active Status Bit 880" "Not active,Active"
bitfld.long 0x00 15. "  ASB879  ,Active Status Bit 879" "Not active,Active"
bitfld.long 0x00 14. "  ASB878  ,Active Status Bit 878" "Not active,Active"
textline "                                 "
bitfld.long 0x00 13. " ASB877  ,Active Status Bit 877" "Not active,Active"
bitfld.long 0x00 12. "  ASB876  ,Active Status Bit 876" "Not active,Active"
bitfld.long 0x00 11. "  ASB875  ,Active Status Bit 875" "Not active,Active"
textline "                                 "
bitfld.long 0x00 10. " ASB874  ,Active Status Bit 874" "Not active,Active"
bitfld.long 0x00 9. "  ASB873  ,Active Status Bit 873" "Not active,Active"
bitfld.long 0x00 8. "  ASB872  ,Active Status Bit 872" "Not active,Active"
textline "                                 "
bitfld.long 0x00 7. " ASB871  ,Active Status Bit 871" "Not active,Active"
bitfld.long 0x00 6. "  ASB870  ,Active Status Bit 870" "Not active,Active"
bitfld.long 0x00 5. "  ASB869  ,Active Status Bit 869" "Not active,Active"
textline "                                 "
bitfld.long 0x00 4. " ASB868  ,Active Status Bit 868" "Not active,Active"
bitfld.long 0x00 3. "  ASB867  ,Active Status Bit 867" "Not active,Active"
bitfld.long 0x00 2. "  ASB866  ,Active Status Bit 866" "Not active,Active"
textline "                                 "
bitfld.long 0x00 1. " ASB865  ,Active Status Bit 865" "Not active,Active"
bitfld.long 0x00 0. "  ASB864  ,Active Status Bit 864" "Not active,Active"
else
rgroup.long 0x036C++0x03
line.long 0x0 "GICD_ICDABR27,Active Status Register 27"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1C)
rgroup.long 0x0370++0x03
line.long 0x0 "GICD_ICDABR28,Active Status Register 28"
bitfld.long 0x00 31. " ASB927  ,Active Status Bit 927" "Not active,Active"
bitfld.long 0x00 30. "  ASB926  ,Active Status Bit 926" "Not active,Active"
bitfld.long 0x00 29. "  ASB925  ,Active Status Bit 925" "Not active,Active"
textline "                                 "
bitfld.long 0x00 28. " ASB924  ,Active Status Bit 924" "Not active,Active"
bitfld.long 0x00 27. "  ASB923  ,Active Status Bit 923" "Not active,Active"
bitfld.long 0x00 26. "  ASB922  ,Active Status Bit 922" "Not active,Active"
textline "                                 "
bitfld.long 0x00 25. " ASB921  ,Active Status Bit 921" "Not active,Active"
bitfld.long 0x00 24. "  ASB920  ,Active Status Bit 920" "Not active,Active"
bitfld.long 0x00 23. "  ASB919  ,Active Status Bit 919" "Not active,Active"
textline "                                 "
bitfld.long 0x00 22. " ASB918  ,Active Status Bit 918" "Not active,Active"
bitfld.long 0x00 21. "  ASB917  ,Active Status Bit 917" "Not active,Active"
bitfld.long 0x00 20. "  ASB916  ,Active Status Bit 916" "Not active,Active"
textline "                                 "
bitfld.long 0x00 19. " ASB915  ,Active Status Bit 915" "Not active,Active"
bitfld.long 0x00 18. "  ASB914  ,Active Status Bit 914" "Not active,Active"
bitfld.long 0x00 17. "  ASB913  ,Active Status Bit 913" "Not active,Active"
textline "                                 "
bitfld.long 0x00 16. " ASB912  ,Active Status Bit 912" "Not active,Active"
bitfld.long 0x00 15. "  ASB911  ,Active Status Bit 911" "Not active,Active"
bitfld.long 0x00 14. "  ASB910  ,Active Status Bit 910" "Not active,Active"
textline "                                 "
bitfld.long 0x00 13. " ASB909  ,Active Status Bit 909" "Not active,Active"
bitfld.long 0x00 12. "  ASB908  ,Active Status Bit 908" "Not active,Active"
bitfld.long 0x00 11. "  ASB907  ,Active Status Bit 907" "Not active,Active"
textline "                                 "
bitfld.long 0x00 10. " ASB906  ,Active Status Bit 906" "Not active,Active"
bitfld.long 0x00 9. "  ASB905  ,Active Status Bit 905" "Not active,Active"
bitfld.long 0x00 8. "  ASB904  ,Active Status Bit 904" "Not active,Active"
textline "                                 "
bitfld.long 0x00 7. " ASB903  ,Active Status Bit 903" "Not active,Active"
bitfld.long 0x00 6. "  ASB902  ,Active Status Bit 902" "Not active,Active"
bitfld.long 0x00 5. "  ASB901  ,Active Status Bit 901" "Not active,Active"
textline "                                 "
bitfld.long 0x00 4. " ASB900  ,Active Status Bit 900" "Not active,Active"
bitfld.long 0x00 3. "  ASB899  ,Active Status Bit 899" "Not active,Active"
bitfld.long 0x00 2. "  ASB898  ,Active Status Bit 898" "Not active,Active"
textline "                                 "
bitfld.long 0x00 1. " ASB897  ,Active Status Bit 897" "Not active,Active"
bitfld.long 0x00 0. "  ASB896  ,Active Status Bit 896" "Not active,Active"
else
rgroup.long 0x0370++0x03
line.long 0x0 "GICD_ICDABR28,Active Status Register 28"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1D)
rgroup.long 0x0374++0x03
line.long 0x0 "GICD_ICDABR29,Active Status Register 29"
bitfld.long 0x00 31. " ASB959  ,Active Status Bit 959" "Not active,Active"
bitfld.long 0x00 30. "  ASB958  ,Active Status Bit 958" "Not active,Active"
bitfld.long 0x00 29. "  ASB957  ,Active Status Bit 957" "Not active,Active"
textline "                                 "
bitfld.long 0x00 28. " ASB956  ,Active Status Bit 956" "Not active,Active"
bitfld.long 0x00 27. "  ASB955  ,Active Status Bit 955" "Not active,Active"
bitfld.long 0x00 26. "  ASB954  ,Active Status Bit 954" "Not active,Active"
textline "                                 "
bitfld.long 0x00 25. " ASB953  ,Active Status Bit 953" "Not active,Active"
bitfld.long 0x00 24. "  ASB952  ,Active Status Bit 952" "Not active,Active"
bitfld.long 0x00 23. "  ASB951  ,Active Status Bit 951" "Not active,Active"
textline "                                 "
bitfld.long 0x00 22. " ASB950  ,Active Status Bit 950" "Not active,Active"
bitfld.long 0x00 21. "  ASB949  ,Active Status Bit 949" "Not active,Active"
bitfld.long 0x00 20. "  ASB948  ,Active Status Bit 948" "Not active,Active"
textline "                                 "
bitfld.long 0x00 19. " ASB947  ,Active Status Bit 947" "Not active,Active"
bitfld.long 0x00 18. "  ASB946  ,Active Status Bit 946" "Not active,Active"
bitfld.long 0x00 17. "  ASB945  ,Active Status Bit 945" "Not active,Active"
textline "                                 "
bitfld.long 0x00 16. " ASB944  ,Active Status Bit 944" "Not active,Active"
bitfld.long 0x00 15. "  ASB943  ,Active Status Bit 943" "Not active,Active"
bitfld.long 0x00 14. "  ASB942  ,Active Status Bit 942" "Not active,Active"
textline "                                 "
bitfld.long 0x00 13. " ASB941  ,Active Status Bit 941" "Not active,Active"
bitfld.long 0x00 12. "  ASB940  ,Active Status Bit 940" "Not active,Active"
bitfld.long 0x00 11. "  ASB939  ,Active Status Bit 939" "Not active,Active"
textline "                                 "
bitfld.long 0x00 10. " ASB938  ,Active Status Bit 938" "Not active,Active"
bitfld.long 0x00 9. "  ASB937  ,Active Status Bit 937" "Not active,Active"
bitfld.long 0x00 8. "  ASB936  ,Active Status Bit 936" "Not active,Active"
textline "                                 "
bitfld.long 0x00 7. " ASB935  ,Active Status Bit 935" "Not active,Active"
bitfld.long 0x00 6. "  ASB934  ,Active Status Bit 934" "Not active,Active"
bitfld.long 0x00 5. "  ASB933  ,Active Status Bit 933" "Not active,Active"
textline "                                 "
bitfld.long 0x00 4. " ASB932  ,Active Status Bit 932" "Not active,Active"
bitfld.long 0x00 3. "  ASB931  ,Active Status Bit 931" "Not active,Active"
bitfld.long 0x00 2. "  ASB930  ,Active Status Bit 930" "Not active,Active"
textline "                                 "
bitfld.long 0x00 1. " ASB929  ,Active Status Bit 929" "Not active,Active"
bitfld.long 0x00 0. "  ASB928  ,Active Status Bit 928" "Not active,Active"
else
rgroup.long 0x0374++0x03
line.long 0x0 "GICD_ICDABR29,Active Status Register 29"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1E)
rgroup.long 0x0378++0x03
line.long 0x0 "GICD_ICDABR30,Active Status Register 30"
bitfld.long 0x00 31. " ASB991  ,Active Status Bit 991" "Not active,Active"
bitfld.long 0x00 30. "  ASB990  ,Active Status Bit 990" "Not active,Active"
bitfld.long 0x00 29. "  ASB989  ,Active Status Bit 989" "Not active,Active"
textline "                                 "
bitfld.long 0x00 28. " ASB988  ,Active Status Bit 988" "Not active,Active"
bitfld.long 0x00 27. "  ASB987  ,Active Status Bit 987" "Not active,Active"
bitfld.long 0x00 26. "  ASB986  ,Active Status Bit 986" "Not active,Active"
textline "                                 "
bitfld.long 0x00 25. " ASB985  ,Active Status Bit 985" "Not active,Active"
bitfld.long 0x00 24. "  ASB984  ,Active Status Bit 984" "Not active,Active"
bitfld.long 0x00 23. "  ASB983  ,Active Status Bit 983" "Not active,Active"
textline "                                 "
bitfld.long 0x00 22. " ASB982  ,Active Status Bit 982" "Not active,Active"
bitfld.long 0x00 21. "  ASB981  ,Active Status Bit 981" "Not active,Active"
bitfld.long 0x00 20. "  ASB980  ,Active Status Bit 980" "Not active,Active"
textline "                                 "
bitfld.long 0x00 19. " ASB979  ,Active Status Bit 979" "Not active,Active"
bitfld.long 0x00 18. "  ASB978  ,Active Status Bit 978" "Not active,Active"
bitfld.long 0x00 17. "  ASB977  ,Active Status Bit 977" "Not active,Active"
textline "                                 "
bitfld.long 0x00 16. " ASB976  ,Active Status Bit 976" "Not active,Active"
bitfld.long 0x00 15. "  ASB975  ,Active Status Bit 975" "Not active,Active"
bitfld.long 0x00 14. "  ASB974  ,Active Status Bit 974" "Not active,Active"
textline "                                 "
bitfld.long 0x00 13. " ASB973  ,Active Status Bit 973" "Not active,Active"
bitfld.long 0x00 12. "  ASB972  ,Active Status Bit 972" "Not active,Active"
bitfld.long 0x00 11. "  ASB971  ,Active Status Bit 971" "Not active,Active"
textline "                                 "
bitfld.long 0x00 10. " ASB970  ,Active Status Bit 970" "Not active,Active"
bitfld.long 0x00 9. "  ASB969  ,Active Status Bit 969" "Not active,Active"
bitfld.long 0x00 8. "  ASB968  ,Active Status Bit 968" "Not active,Active"
textline "                                 "
bitfld.long 0x00 7. " ASB967  ,Active Status Bit 967" "Not active,Active"
bitfld.long 0x00 6. "  ASB966  ,Active Status Bit 966" "Not active,Active"
bitfld.long 0x00 5. "  ASB965  ,Active Status Bit 965" "Not active,Active"
textline "                                 "
bitfld.long 0x00 4. " ASB964  ,Active Status Bit 964" "Not active,Active"
bitfld.long 0x00 3. "  ASB963  ,Active Status Bit 963" "Not active,Active"
bitfld.long 0x00 2. "  ASB962  ,Active Status Bit 962" "Not active,Active"
textline "                                 "
bitfld.long 0x00 1. " ASB961  ,Active Status Bit 961" "Not active,Active"
bitfld.long 0x00 0. "  ASB960  ,Active Status Bit 960" "Not active,Active"
else
rgroup.long 0x0378++0x03
line.long 0x0 "GICD_ICDABR30,Active Status Register 30"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)==0x1F)
rgroup.long 0x037C++0x03
line.long 0x0 "GICD_ICDABR31,Active Status Register 31"
bitfld.long 0x00 27. " ASB1019 ,Active Status Bit 1019" "Not active,Active"
bitfld.long 0x00 26. "  ASB1018 ,Active Status Bit 1018" "Not active,Active"
textline "                                 "
bitfld.long 0x00 25. " ASB1017 ,Active Status Bit 1017" "Not active,Active"
bitfld.long 0x00 24. "  ASB1016 ,Active Status Bit 1016" "Not active,Active"
bitfld.long 0x00 23. "  ASB1015 ,Active Status Bit 1015" "Not active,Active"
textline "                                 "
bitfld.long 0x00 22. " ASB1014 ,Active Status Bit 1014" "Not active,Active"
bitfld.long 0x00 21. "  ASB1013 ,Active Status Bit 1013" "Not active,Active"
bitfld.long 0x00 20. "  ASB1012 ,Active Status Bit 1012" "Not active,Active"
textline "                                 "
bitfld.long 0x00 19. " ASB1011 ,Active Status Bit 1011" "Not active,Active"
bitfld.long 0x00 18. "  ASB1010 ,Active Status Bit 1010" "Not active,Active"
bitfld.long 0x00 17. "  ASB1009 ,Active Status Bit 1009" "Not active,Active"
textline "                                 "
bitfld.long 0x00 16. " ASB1008 ,Active Status Bit 1008" "Not active,Active"
bitfld.long 0x00 15. "  ASB1007 ,Active Status Bit 1007" "Not active,Active"
bitfld.long 0x00 14. "  ASB1006 ,Active Status Bit 1006" "Not active,Active"
textline "                                 "
bitfld.long 0x00 13. " ASB1005 ,Active Status Bit 1005" "Not active,Active"
bitfld.long 0x00 12. "  ASB1004 ,Active Status Bit 1004" "Not active,Active"
bitfld.long 0x00 11. "  ASB1003 ,Active Status Bit 1003" "Not active,Active"
textline "                                 "
bitfld.long 0x00 10. " ASB1002 ,Active Status Bit 1002" "Not active,Active"
bitfld.long 0x00 9. "  ASB1001 ,Active Status Bit 1001" "Not active,Active"
bitfld.long 0x00 8. "  ASB1000 ,Active Status Bit 1000" "Not active,Active"
textline "                                 "
bitfld.long 0x00 7. " ASB999  ,Active Status Bit 999" "Not active,Active"
bitfld.long 0x00 6. "  ASB998  ,Active Status Bit 998" "Not active,Active"
bitfld.long 0x00 5. "  ASB997  ,Active Status Bit 997" "Not active,Active"
textline "                                 "
bitfld.long 0x00 4. " ASB996  ,Active Status Bit 996" "Not active,Active"
bitfld.long 0x00 3. "  ASB995  ,Active Status Bit 995" "Not active,Active"
bitfld.long 0x00 2. "  ASB994  ,Active Status Bit 994" "Not active,Active"
textline "                                 "
bitfld.long 0x00 1. " ASB993  ,Active Status Bit 993" "Not active,Active"
bitfld.long 0x00 0. "  ASB992  ,Active Status Bit 992" "Not active,Active"
else
rgroup.long 0x037C++0x03
line.long 0x0 "GICD_ICDABR31,Active Status Register 31"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
else
group.long 0x0300++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER0,Interrupt Set/Clear Active Register 0"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE31  ,Set/Clear Active Bit 31" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "    SET/CLRACTIVE30  ,Set/Clear Active Bit 30" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "    SET/CLRACTIVE29  ,Set/Clear Active Bit 29" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE28  ,Set/Clear Active Bit 28" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "    SET/CLRACTIVE27  ,Set/Clear Active Bit 27" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "    SET/CLRACTIVE26  ,Set/Clear Active Bit 26" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE25  ,Set/Clear Active Bit 25" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "    SET/CLRACTIVE24  ,Set/Clear Active Bit 24" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "    SET/CLRACTIVE23  ,Set/Clear Active Bit 23" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE22  ,Set/Clear Active Bit 22" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "    SET/CLRACTIVE21  ,Set/Clear Active Bit 21" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "    SET/CLRACTIVE20  ,Set/Clear Active Bit 20" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE19  ,Set/Clear Active Bit 19" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "    SET/CLRACTIVE18  ,Set/Clear Active Bit 18" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "    SET/CLRACTIVE17  ,Set/Clear Active Bit 17" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE16  ,Set/Clear Active Bit 16" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "    SET/CLRACTIVE15  ,Set/Clear Active Bit 15" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "    SET/CLRACTIVE14  ,Set/Clear Active Bit 14" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE13  ,Set/Clear Active Bit 13" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "    SET/CLRACTIVE12  ,Set/Clear Active Bit 12" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "    SET/CLRACTIVE11  ,Set/Clear Active Bit 11" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE10  ,Set/Clear Active Bit 10" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "    SET/CLRACTIVE9   ,Set/Clear Active Bit 9" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "    SET/CLRACTIVE8   ,Set/Clear Active Bit 8" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE7   ,Set/Clear Active Bit 7" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "    SET/CLRACTIVE6   ,Set/Clear Active Bit 6" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "    SET/CLRACTIVE5   ,Set/Clear Active Bit 5" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE4   ,Set/Clear Active Bit 4" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "    SET/CLRACTIVE3   ,Set/Clear Active Bit 3" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "    SET/CLRACTIVE2   ,Set/Clear Active Bit 2" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE1   ,Set/Clear Active Bit 1" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "    SET/CLRACTIVE0   ,Set/Clear Active Bit 0" "Not active,Active"
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x01)
group.long 0x0304++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER1,Interrupt Set/Clear Active Register 1"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE63  ,Set/Clear Active Bit 63" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "    SET/CLRACTIVE62  ,Set/Clear Active Bit 62" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "    SET/CLRACTIVE61  ,Set/Clear Active Bit 61" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE60  ,Set/Clear Active Bit 60" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "    SET/CLRACTIVE59  ,Set/Clear Active Bit 59" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "    SET/CLRACTIVE58  ,Set/Clear Active Bit 58" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE57  ,Set/Clear Active Bit 57" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "    SET/CLRACTIVE56  ,Set/Clear Active Bit 56" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "    SET/CLRACTIVE55  ,Set/Clear Active Bit 55" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE54  ,Set/Clear Active Bit 54" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "    SET/CLRACTIVE53  ,Set/Clear Active Bit 53" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "    SET/CLRACTIVE52  ,Set/Clear Active Bit 52" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE51  ,Set/Clear Active Bit 51" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "    SET/CLRACTIVE50  ,Set/Clear Active Bit 50" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "    SET/CLRACTIVE49  ,Set/Clear Active Bit 49" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE48  ,Set/Clear Active Bit 48" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "    SET/CLRACTIVE47  ,Set/Clear Active Bit 47" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "    SET/CLRACTIVE46  ,Set/Clear Active Bit 46" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE45  ,Set/Clear Active Bit 45" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "    SET/CLRACTIVE44  ,Set/Clear Active Bit 44" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "    SET/CLRACTIVE43  ,Set/Clear Active Bit 43" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE42  ,Set/Clear Active Bit 42" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "    SET/CLRACTIVE41  ,Set/Clear Active Bit 41" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "    SET/CLRACTIVE40  ,Set/Clear Active Bit 40" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE39  ,Set/Clear Active Bit 39" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "    SET/CLRACTIVE38  ,Set/Clear Active Bit 38" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "    SET/CLRACTIVE37  ,Set/Clear Active Bit 37" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE36  ,Set/Clear Active Bit 36" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "    SET/CLRACTIVE35  ,Set/Clear Active Bit 35" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "    SET/CLRACTIVE34  ,Set/Clear Active Bit 34" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE33  ,Set/Clear Active Bit 33" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "    SET/CLRACTIVE32  ,Set/Clear Active Bit 32" "Not active,Active"
else
rgroup.long 0x0304++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER1,Interrupt Set/Clear Active Register 1"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x02)
group.long 0x0308++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER2,Interrupt Set/Clear Active Register 2"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE95  ,Set/Clear Active Bit 95" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "    SET/CLRACTIVE94  ,Set/Clear Active Bit 94" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "    SET/CLRACTIVE93  ,Set/Clear Active Bit 93" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE92  ,Set/Clear Active Bit 92" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "    SET/CLRACTIVE91  ,Set/Clear Active Bit 91" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "    SET/CLRACTIVE90  ,Set/Clear Active Bit 90" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE89  ,Set/Clear Active Bit 89" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "    SET/CLRACTIVE88  ,Set/Clear Active Bit 88" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "    SET/CLRACTIVE87  ,Set/Clear Active Bit 87" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE86  ,Set/Clear Active Bit 86" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "    SET/CLRACTIVE85  ,Set/Clear Active Bit 85" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "    SET/CLRACTIVE84  ,Set/Clear Active Bit 84" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE83  ,Set/Clear Active Bit 83" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "    SET/CLRACTIVE82  ,Set/Clear Active Bit 82" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "    SET/CLRACTIVE81  ,Set/Clear Active Bit 81" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE80  ,Set/Clear Active Bit 80" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "    SET/CLRACTIVE79  ,Set/Clear Active Bit 79" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "    SET/CLRACTIVE78  ,Set/Clear Active Bit 78" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE77  ,Set/Clear Active Bit 77" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "    SET/CLRACTIVE76  ,Set/Clear Active Bit 76" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "    SET/CLRACTIVE75  ,Set/Clear Active Bit 75" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE74  ,Set/Clear Active Bit 74" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "    SET/CLRACTIVE73  ,Set/Clear Active Bit 73" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "    SET/CLRACTIVE72  ,Set/Clear Active Bit 72" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE71  ,Set/Clear Active Bit 71" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "    SET/CLRACTIVE70  ,Set/Clear Active Bit 70" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "    SET/CLRACTIVE69  ,Set/Clear Active Bit 69" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE68  ,Set/Clear Active Bit 68" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "    SET/CLRACTIVE67  ,Set/Clear Active Bit 67" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "    SET/CLRACTIVE66  ,Set/Clear Active Bit 66" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE65  ,Set/Clear Active Bit 65" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "    SET/CLRACTIVE64  ,Set/Clear Active Bit 64" "Not active,Active"
else
rgroup.long 0x0308++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER2,Interrupt Set/Clear Active Register 2"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x03)
group.long 0x030C++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER3,Interrupt Set/Clear Active Register 3"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE127 ,Set/Clear Active Bit 127" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "    SET/CLRACTIVE126 ,Set/Clear Active Bit 126" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "    SET/CLRACTIVE125 ,Set/Clear Active Bit 125" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE124 ,Set/Clear Active Bit 124" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "    SET/CLRACTIVE123 ,Set/Clear Active Bit 123" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "    SET/CLRACTIVE122 ,Set/Clear Active Bit 122" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE121 ,Set/Clear Active Bit 121" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "    SET/CLRACTIVE120 ,Set/Clear Active Bit 120" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "    SET/CLRACTIVE119 ,Set/Clear Active Bit 119" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE118 ,Set/Clear Active Bit 118" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "    SET/CLRACTIVE117 ,Set/Clear Active Bit 117" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "    SET/CLRACTIVE116 ,Set/Clear Active Bit 116" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE115 ,Set/Clear Active Bit 115" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "    SET/CLRACTIVE114 ,Set/Clear Active Bit 114" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "    SET/CLRACTIVE113 ,Set/Clear Active Bit 113" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE112 ,Set/Clear Active Bit 112" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "    SET/CLRACTIVE111 ,Set/Clear Active Bit 111" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "    SET/CLRACTIVE110 ,Set/Clear Active Bit 110" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE109 ,Set/Clear Active Bit 109" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "    SET/CLRACTIVE108 ,Set/Clear Active Bit 108" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "    SET/CLRACTIVE107 ,Set/Clear Active Bit 107" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE106 ,Set/Clear Active Bit 106" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "    SET/CLRACTIVE105 ,Set/Clear Active Bit 105" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "    SET/CLRACTIVE104 ,Set/Clear Active Bit 104" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE103 ,Set/Clear Active Bit 103" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "    SET/CLRACTIVE102 ,Set/Clear Active Bit 102" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "    SET/CLRACTIVE101 ,Set/Clear Active Bit 101" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE100 ,Set/Clear Active Bit 100" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "    SET/CLRACTIVE99  ,Set/Clear Active Bit 99" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "    SET/CLRACTIVE98  ,Set/Clear Active Bit 98" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE97  ,Set/Clear Active Bit 97" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "    SET/CLRACTIVE96  ,Set/Clear Active Bit 96" "Not active,Active"
else
rgroup.long 0x030C++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER3,Interrupt Set/Clear Active Register 3"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x04)
group.long 0x0310++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER4,Interrupt Set/Clear Active Register 4"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE159 ,Set/Clear Active Bit 159" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "    SET/CLRACTIVE158 ,Set/Clear Active Bit 158" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "    SET/CLRACTIVE157 ,Set/Clear Active Bit 157" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE156 ,Set/Clear Active Bit 156" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "    SET/CLRACTIVE155 ,Set/Clear Active Bit 155" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "    SET/CLRACTIVE154 ,Set/Clear Active Bit 154" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE153 ,Set/Clear Active Bit 153" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "    SET/CLRACTIVE152 ,Set/Clear Active Bit 152" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "    SET/CLRACTIVE151 ,Set/Clear Active Bit 151" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE150 ,Set/Clear Active Bit 150" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "    SET/CLRACTIVE149 ,Set/Clear Active Bit 149" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "    SET/CLRACTIVE148 ,Set/Clear Active Bit 148" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE147 ,Set/Clear Active Bit 147" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "    SET/CLRACTIVE146 ,Set/Clear Active Bit 146" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "    SET/CLRACTIVE145 ,Set/Clear Active Bit 145" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE144 ,Set/Clear Active Bit 144" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "    SET/CLRACTIVE143 ,Set/Clear Active Bit 143" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "    SET/CLRACTIVE142 ,Set/Clear Active Bit 142" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE141 ,Set/Clear Active Bit 141" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "    SET/CLRACTIVE140 ,Set/Clear Active Bit 140" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "    SET/CLRACTIVE139 ,Set/Clear Active Bit 139" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE138 ,Set/Clear Active Bit 138" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "    SET/CLRACTIVE137 ,Set/Clear Active Bit 137" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "    SET/CLRACTIVE136 ,Set/Clear Active Bit 136" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE135 ,Set/Clear Active Bit 135" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "    SET/CLRACTIVE134 ,Set/Clear Active Bit 134" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "    SET/CLRACTIVE133 ,Set/Clear Active Bit 133" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE132 ,Set/Clear Active Bit 132" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "    SET/CLRACTIVE131 ,Set/Clear Active Bit 131" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "    SET/CLRACTIVE130 ,Set/Clear Active Bit 130" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE129 ,Set/Clear Active Bit 129" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "    SET/CLRACTIVE128 ,Set/Clear Active Bit 128" "Not active,Active"
else
rgroup.long 0x0310++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER4,Interrupt Set/Clear Active Register 4"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x05)
group.long 0x0314++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER5,Interrupt Set/Clear Active Register 5"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE191 ,Set/Clear Active Bit 191" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "    SET/CLRACTIVE190 ,Set/Clear Active Bit 190" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "    SET/CLRACTIVE189 ,Set/Clear Active Bit 189" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE188 ,Set/Clear Active Bit 188" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "    SET/CLRACTIVE187 ,Set/Clear Active Bit 187" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "    SET/CLRACTIVE186 ,Set/Clear Active Bit 186" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE185 ,Set/Clear Active Bit 185" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "    SET/CLRACTIVE184 ,Set/Clear Active Bit 184" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "    SET/CLRACTIVE183 ,Set/Clear Active Bit 183" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE182 ,Set/Clear Active Bit 182" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "    SET/CLRACTIVE181 ,Set/Clear Active Bit 181" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "    SET/CLRACTIVE180 ,Set/Clear Active Bit 180" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE179 ,Set/Clear Active Bit 179" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "    SET/CLRACTIVE178 ,Set/Clear Active Bit 178" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "    SET/CLRACTIVE177 ,Set/Clear Active Bit 177" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE176 ,Set/Clear Active Bit 176" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "    SET/CLRACTIVE175 ,Set/Clear Active Bit 175" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "    SET/CLRACTIVE174 ,Set/Clear Active Bit 174" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE173 ,Set/Clear Active Bit 173" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "    SET/CLRACTIVE172 ,Set/Clear Active Bit 172" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "    SET/CLRACTIVE171 ,Set/Clear Active Bit 171" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE170 ,Set/Clear Active Bit 170" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "    SET/CLRACTIVE169 ,Set/Clear Active Bit 169" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "    SET/CLRACTIVE168 ,Set/Clear Active Bit 168" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE167 ,Set/Clear Active Bit 167" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "    SET/CLRACTIVE166 ,Set/Clear Active Bit 166" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "    SET/CLRACTIVE165 ,Set/Clear Active Bit 165" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE164 ,Set/Clear Active Bit 164" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "    SET/CLRACTIVE163 ,Set/Clear Active Bit 163" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "    SET/CLRACTIVE162 ,Set/Clear Active Bit 162" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE161 ,Set/Clear Active Bit 161" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "    SET/CLRACTIVE160 ,Set/Clear Active Bit 160" "Not active,Active"
else
rgroup.long 0x0314++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER5,Interrupt Set/Clear Active Register 5"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x06)
group.long 0x0318++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER6,Interrupt Set/Clear Active Register 6"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE223 ,Set/Clear Active Bit 223" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "    SET/CLRACTIVE222 ,Set/Clear Active Bit 222" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "    SET/CLRACTIVE221 ,Set/Clear Active Bit 221" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE220 ,Set/Clear Active Bit 220" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "    SET/CLRACTIVE219 ,Set/Clear Active Bit 219" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "    SET/CLRACTIVE218 ,Set/Clear Active Bit 218" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE217 ,Set/Clear Active Bit 217" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "    SET/CLRACTIVE216 ,Set/Clear Active Bit 216" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "    SET/CLRACTIVE215 ,Set/Clear Active Bit 215" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE214 ,Set/Clear Active Bit 214" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "    SET/CLRACTIVE213 ,Set/Clear Active Bit 213" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "    SET/CLRACTIVE212 ,Set/Clear Active Bit 212" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE211 ,Set/Clear Active Bit 211" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "    SET/CLRACTIVE210 ,Set/Clear Active Bit 210" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "    SET/CLRACTIVE209 ,Set/Clear Active Bit 209" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE208 ,Set/Clear Active Bit 208" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "    SET/CLRACTIVE207 ,Set/Clear Active Bit 207" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "    SET/CLRACTIVE206 ,Set/Clear Active Bit 206" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE205 ,Set/Clear Active Bit 205" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "    SET/CLRACTIVE204 ,Set/Clear Active Bit 204" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "    SET/CLRACTIVE203 ,Set/Clear Active Bit 203" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE202 ,Set/Clear Active Bit 202" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "    SET/CLRACTIVE201 ,Set/Clear Active Bit 201" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "    SET/CLRACTIVE200 ,Set/Clear Active Bit 200" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE199 ,Set/Clear Active Bit 199" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "    SET/CLRACTIVE198 ,Set/Clear Active Bit 198" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "    SET/CLRACTIVE197 ,Set/Clear Active Bit 197" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE196 ,Set/Clear Active Bit 196" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "    SET/CLRACTIVE195 ,Set/Clear Active Bit 195" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "    SET/CLRACTIVE194 ,Set/Clear Active Bit 194" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE193 ,Set/Clear Active Bit 193" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "    SET/CLRACTIVE192 ,Set/Clear Active Bit 192" "Not active,Active"
else
rgroup.long 0x0318++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER6,Interrupt Set/Clear Active Register 6"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x07)
group.long 0x031C++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER7,Interrupt Set/Clear Active Register 7"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE255 ,Set/Clear Active Bit 255" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "    SET/CLRACTIVE254 ,Set/Clear Active Bit 254" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "    SET/CLRACTIVE253 ,Set/Clear Active Bit 253" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE252 ,Set/Clear Active Bit 252" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "    SET/CLRACTIVE251 ,Set/Clear Active Bit 251" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "    SET/CLRACTIVE250 ,Set/Clear Active Bit 250" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE249 ,Set/Clear Active Bit 249" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "    SET/CLRACTIVE248 ,Set/Clear Active Bit 248" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "    SET/CLRACTIVE247 ,Set/Clear Active Bit 247" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE246 ,Set/Clear Active Bit 246" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "    SET/CLRACTIVE245 ,Set/Clear Active Bit 245" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "    SET/CLRACTIVE244 ,Set/Clear Active Bit 244" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE243 ,Set/Clear Active Bit 243" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "    SET/CLRACTIVE242 ,Set/Clear Active Bit 242" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "    SET/CLRACTIVE241 ,Set/Clear Active Bit 241" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE240 ,Set/Clear Active Bit 240" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "    SET/CLRACTIVE239 ,Set/Clear Active Bit 239" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "    SET/CLRACTIVE238 ,Set/Clear Active Bit 238" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE237 ,Set/Clear Active Bit 237" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "    SET/CLRACTIVE236 ,Set/Clear Active Bit 236" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "    SET/CLRACTIVE235 ,Set/Clear Active Bit 235" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE234 ,Set/Clear Active Bit 234" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "    SET/CLRACTIVE233 ,Set/Clear Active Bit 233" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "    SET/CLRACTIVE232 ,Set/Clear Active Bit 232" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE231 ,Set/Clear Active Bit 231" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "    SET/CLRACTIVE230 ,Set/Clear Active Bit 230" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "    SET/CLRACTIVE229 ,Set/Clear Active Bit 229" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE228 ,Set/Clear Active Bit 228" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "    SET/CLRACTIVE227 ,Set/Clear Active Bit 227" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "    SET/CLRACTIVE226 ,Set/Clear Active Bit 226" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE225 ,Set/Clear Active Bit 225" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "    SET/CLRACTIVE224 ,Set/Clear Active Bit 224" "Not active,Active"
else
rgroup.long 0x031C++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER7,Interrupt Set/Clear Active Register 7"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x08)
group.long 0x0320++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER8,Interrupt Set/Clear Active Register 8"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE287 ,Set/Clear Active Bit 287" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "    SET/CLRACTIVE286 ,Set/Clear Active Bit 286" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "    SET/CLRACTIVE285 ,Set/Clear Active Bit 285" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE284 ,Set/Clear Active Bit 284" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "    SET/CLRACTIVE283 ,Set/Clear Active Bit 283" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "    SET/CLRACTIVE282 ,Set/Clear Active Bit 282" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE281 ,Set/Clear Active Bit 281" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "    SET/CLRACTIVE280 ,Set/Clear Active Bit 280" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "    SET/CLRACTIVE279 ,Set/Clear Active Bit 279" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE278 ,Set/Clear Active Bit 278" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "    SET/CLRACTIVE277 ,Set/Clear Active Bit 277" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "    SET/CLRACTIVE276 ,Set/Clear Active Bit 276" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE275 ,Set/Clear Active Bit 275" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "    SET/CLRACTIVE274 ,Set/Clear Active Bit 274" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "    SET/CLRACTIVE273 ,Set/Clear Active Bit 273" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE272 ,Set/Clear Active Bit 272" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "    SET/CLRACTIVE271 ,Set/Clear Active Bit 271" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "    SET/CLRACTIVE270 ,Set/Clear Active Bit 270" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE269 ,Set/Clear Active Bit 269" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "    SET/CLRACTIVE268 ,Set/Clear Active Bit 268" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "    SET/CLRACTIVE267 ,Set/Clear Active Bit 267" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE266 ,Set/Clear Active Bit 266" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "    SET/CLRACTIVE265 ,Set/Clear Active Bit 265" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "    SET/CLRACTIVE264 ,Set/Clear Active Bit 264" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE263 ,Set/Clear Active Bit 263" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "    SET/CLRACTIVE262 ,Set/Clear Active Bit 262" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "    SET/CLRACTIVE261 ,Set/Clear Active Bit 261" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE260 ,Set/Clear Active Bit 260" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "    SET/CLRACTIVE259 ,Set/Clear Active Bit 259" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "    SET/CLRACTIVE258 ,Set/Clear Active Bit 258" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE257 ,Set/Clear Active Bit 257" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "    SET/CLRACTIVE256 ,Set/Clear Active Bit 256" "Not active,Active"
else
rgroup.long 0x0320++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER8,Interrupt Set/Clear Active Register 8"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x09)
group.long 0x0324++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER9,Interrupt Set/Clear Active Register 9"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE319 ,Set/Clear Active Bit 319" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "    SET/CLRACTIVE318 ,Set/Clear Active Bit 318" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "    SET/CLRACTIVE317 ,Set/Clear Active Bit 317" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE316 ,Set/Clear Active Bit 316" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "    SET/CLRACTIVE315 ,Set/Clear Active Bit 315" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "    SET/CLRACTIVE314 ,Set/Clear Active Bit 314" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE313 ,Set/Clear Active Bit 313" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "    SET/CLRACTIVE312 ,Set/Clear Active Bit 312" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "    SET/CLRACTIVE311 ,Set/Clear Active Bit 311" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE310 ,Set/Clear Active Bit 310" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "    SET/CLRACTIVE309 ,Set/Clear Active Bit 309" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "    SET/CLRACTIVE308 ,Set/Clear Active Bit 308" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE307 ,Set/Clear Active Bit 307" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "    SET/CLRACTIVE306 ,Set/Clear Active Bit 306" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "    SET/CLRACTIVE305 ,Set/Clear Active Bit 305" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE304 ,Set/Clear Active Bit 304" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "    SET/CLRACTIVE303 ,Set/Clear Active Bit 303" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "    SET/CLRACTIVE302 ,Set/Clear Active Bit 302" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE301 ,Set/Clear Active Bit 301" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "    SET/CLRACTIVE300 ,Set/Clear Active Bit 300" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "    SET/CLRACTIVE299 ,Set/Clear Active Bit 299" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE298 ,Set/Clear Active Bit 298" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "    SET/CLRACTIVE297 ,Set/Clear Active Bit 297" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "    SET/CLRACTIVE296 ,Set/Clear Active Bit 296" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE295 ,Set/Clear Active Bit 295" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "    SET/CLRACTIVE294 ,Set/Clear Active Bit 294" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "    SET/CLRACTIVE293 ,Set/Clear Active Bit 293" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE292 ,Set/Clear Active Bit 292" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "    SET/CLRACTIVE291 ,Set/Clear Active Bit 291" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "    SET/CLRACTIVE290 ,Set/Clear Active Bit 290" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE289 ,Set/Clear Active Bit 289" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "    SET/CLRACTIVE288 ,Set/Clear Active Bit 288" "Not active,Active"
else
rgroup.long 0x0324++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER9,Interrupt Set/Clear Active Register 9"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0A)
group.long 0x0328++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER10,Interrupt Set/Clear Active Register 10"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE351 ,Set/Clear Active Bit 351" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "    SET/CLRACTIVE350 ,Set/Clear Active Bit 350" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "    SET/CLRACTIVE349 ,Set/Clear Active Bit 349" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE348 ,Set/Clear Active Bit 348" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "    SET/CLRACTIVE347 ,Set/Clear Active Bit 347" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "    SET/CLRACTIVE346 ,Set/Clear Active Bit 346" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE345 ,Set/Clear Active Bit 345" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "    SET/CLRACTIVE344 ,Set/Clear Active Bit 344" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "    SET/CLRACTIVE343 ,Set/Clear Active Bit 343" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE342 ,Set/Clear Active Bit 342" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "    SET/CLRACTIVE341 ,Set/Clear Active Bit 341" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "    SET/CLRACTIVE340 ,Set/Clear Active Bit 340" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE339 ,Set/Clear Active Bit 339" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "    SET/CLRACTIVE338 ,Set/Clear Active Bit 338" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "    SET/CLRACTIVE337 ,Set/Clear Active Bit 337" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE336 ,Set/Clear Active Bit 336" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "    SET/CLRACTIVE335 ,Set/Clear Active Bit 335" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "    SET/CLRACTIVE334 ,Set/Clear Active Bit 334" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE333 ,Set/Clear Active Bit 333" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "    SET/CLRACTIVE332 ,Set/Clear Active Bit 332" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "    SET/CLRACTIVE331 ,Set/Clear Active Bit 331" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE330 ,Set/Clear Active Bit 330" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "    SET/CLRACTIVE329 ,Set/Clear Active Bit 329" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "    SET/CLRACTIVE328 ,Set/Clear Active Bit 328" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE327 ,Set/Clear Active Bit 327" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "    SET/CLRACTIVE326 ,Set/Clear Active Bit 326" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "    SET/CLRACTIVE325 ,Set/Clear Active Bit 325" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE324 ,Set/Clear Active Bit 324" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "    SET/CLRACTIVE323 ,Set/Clear Active Bit 323" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "    SET/CLRACTIVE322 ,Set/Clear Active Bit 322" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE321 ,Set/Clear Active Bit 321" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "    SET/CLRACTIVE320 ,Set/Clear Active Bit 320" "Not active,Active"
else
rgroup.long 0x0328++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER10,Interrupt Set/Clear Active Register 10"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0B)
group.long 0x032C++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER11,Interrupt Set/Clear Active Register 11"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE383 ,Set/Clear Active Bit 383" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "    SET/CLRACTIVE382 ,Set/Clear Active Bit 382" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "    SET/CLRACTIVE381 ,Set/Clear Active Bit 381" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE380 ,Set/Clear Active Bit 380" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "    SET/CLRACTIVE379 ,Set/Clear Active Bit 379" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "    SET/CLRACTIVE378 ,Set/Clear Active Bit 378" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE377 ,Set/Clear Active Bit 377" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "    SET/CLRACTIVE376 ,Set/Clear Active Bit 376" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "    SET/CLRACTIVE375 ,Set/Clear Active Bit 375" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE374 ,Set/Clear Active Bit 374" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "    SET/CLRACTIVE373 ,Set/Clear Active Bit 373" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "    SET/CLRACTIVE372 ,Set/Clear Active Bit 372" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE371 ,Set/Clear Active Bit 371" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "    SET/CLRACTIVE370 ,Set/Clear Active Bit 370" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "    SET/CLRACTIVE369 ,Set/Clear Active Bit 369" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE368 ,Set/Clear Active Bit 368" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "    SET/CLRACTIVE367 ,Set/Clear Active Bit 367" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "    SET/CLRACTIVE366 ,Set/Clear Active Bit 366" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE365 ,Set/Clear Active Bit 365" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "    SET/CLRACTIVE364 ,Set/Clear Active Bit 364" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "    SET/CLRACTIVE363 ,Set/Clear Active Bit 363" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE362 ,Set/Clear Active Bit 362" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "    SET/CLRACTIVE361 ,Set/Clear Active Bit 361" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "    SET/CLRACTIVE360 ,Set/Clear Active Bit 360" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE359 ,Set/Clear Active Bit 359" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "    SET/CLRACTIVE358 ,Set/Clear Active Bit 358" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "    SET/CLRACTIVE357 ,Set/Clear Active Bit 357" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE356 ,Set/Clear Active Bit 356" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "    SET/CLRACTIVE355 ,Set/Clear Active Bit 355" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "    SET/CLRACTIVE354 ,Set/Clear Active Bit 354" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE353 ,Set/Clear Active Bit 353" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "    SET/CLRACTIVE352 ,Set/Clear Active Bit 352" "Not active,Active"
else
rgroup.long 0x032C++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER11,Interrupt Set/Clear Active Register 11"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0C)
group.long 0x0330++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER12,Interrupt Set/Clear Active Register 12"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE415 ,Set/Clear Active Bit 415" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "    SET/CLRACTIVE414 ,Set/Clear Active Bit 414" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "    SET/CLRACTIVE413 ,Set/Clear Active Bit 413" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE412 ,Set/Clear Active Bit 412" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "    SET/CLRACTIVE411 ,Set/Clear Active Bit 411" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "    SET/CLRACTIVE410 ,Set/Clear Active Bit 410" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE409 ,Set/Clear Active Bit 409" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "    SET/CLRACTIVE408 ,Set/Clear Active Bit 408" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "    SET/CLRACTIVE407 ,Set/Clear Active Bit 407" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE406 ,Set/Clear Active Bit 406" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "    SET/CLRACTIVE405 ,Set/Clear Active Bit 405" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "    SET/CLRACTIVE404 ,Set/Clear Active Bit 404" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE403 ,Set/Clear Active Bit 403" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "    SET/CLRACTIVE402 ,Set/Clear Active Bit 402" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "    SET/CLRACTIVE401 ,Set/Clear Active Bit 401" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE400 ,Set/Clear Active Bit 400" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "    SET/CLRACTIVE399 ,Set/Clear Active Bit 399" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "    SET/CLRACTIVE398 ,Set/Clear Active Bit 398" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE397 ,Set/Clear Active Bit 397" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "    SET/CLRACTIVE396 ,Set/Clear Active Bit 396" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "    SET/CLRACTIVE395 ,Set/Clear Active Bit 395" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE394 ,Set/Clear Active Bit 394" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "    SET/CLRACTIVE393 ,Set/Clear Active Bit 393" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "    SET/CLRACTIVE392 ,Set/Clear Active Bit 392" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE391 ,Set/Clear Active Bit 391" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "    SET/CLRACTIVE390 ,Set/Clear Active Bit 390" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "    SET/CLRACTIVE389 ,Set/Clear Active Bit 389" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE388 ,Set/Clear Active Bit 388" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "    SET/CLRACTIVE387 ,Set/Clear Active Bit 387" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "    SET/CLRACTIVE386 ,Set/Clear Active Bit 386" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE385 ,Set/Clear Active Bit 385" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "    SET/CLRACTIVE384 ,Set/Clear Active Bit 384" "Not active,Active"
else
rgroup.long 0x0330++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER12,Interrupt Set/Clear Active Register 12"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0D)
group.long 0x0334++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER13,Interrupt Set/Clear Active Register 13"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE447 ,Set/Clear Active Bit 447" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "    SET/CLRACTIVE446 ,Set/Clear Active Bit 446" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "    SET/CLRACTIVE445 ,Set/Clear Active Bit 445" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE444 ,Set/Clear Active Bit 444" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "    SET/CLRACTIVE443 ,Set/Clear Active Bit 443" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "    SET/CLRACTIVE442 ,Set/Clear Active Bit 442" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE441 ,Set/Clear Active Bit 441" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "    SET/CLRACTIVE440 ,Set/Clear Active Bit 440" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "    SET/CLRACTIVE439 ,Set/Clear Active Bit 439" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE438 ,Set/Clear Active Bit 438" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "    SET/CLRACTIVE437 ,Set/Clear Active Bit 437" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "    SET/CLRACTIVE436 ,Set/Clear Active Bit 436" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE435 ,Set/Clear Active Bit 435" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "    SET/CLRACTIVE434 ,Set/Clear Active Bit 434" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "    SET/CLRACTIVE433 ,Set/Clear Active Bit 433" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE432 ,Set/Clear Active Bit 432" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "    SET/CLRACTIVE431 ,Set/Clear Active Bit 431" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "    SET/CLRACTIVE430 ,Set/Clear Active Bit 430" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE429 ,Set/Clear Active Bit 429" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "    SET/CLRACTIVE428 ,Set/Clear Active Bit 428" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "    SET/CLRACTIVE427 ,Set/Clear Active Bit 427" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE426 ,Set/Clear Active Bit 426" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "    SET/CLRACTIVE425 ,Set/Clear Active Bit 425" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "    SET/CLRACTIVE424 ,Set/Clear Active Bit 424" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE423 ,Set/Clear Active Bit 423" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "    SET/CLRACTIVE422 ,Set/Clear Active Bit 422" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "    SET/CLRACTIVE421 ,Set/Clear Active Bit 421" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE420 ,Set/Clear Active Bit 420" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "    SET/CLRACTIVE419 ,Set/Clear Active Bit 419" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "    SET/CLRACTIVE418 ,Set/Clear Active Bit 418" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE417 ,Set/Clear Active Bit 417" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "    SET/CLRACTIVE416 ,Set/Clear Active Bit 416" "Not active,Active"
else
rgroup.long 0x0334++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER13,Interrupt Set/Clear Active Register 13"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0E)
group.long 0x0338++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER14,Interrupt Set/Clear Active Register 14"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE479 ,Set/Clear Active Bit 479" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "    SET/CLRACTIVE478 ,Set/Clear Active Bit 478" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "    SET/CLRACTIVE477 ,Set/Clear Active Bit 477" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE476 ,Set/Clear Active Bit 476" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "    SET/CLRACTIVE475 ,Set/Clear Active Bit 475" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "    SET/CLRACTIVE474 ,Set/Clear Active Bit 474" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE473 ,Set/Clear Active Bit 473" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "    SET/CLRACTIVE472 ,Set/Clear Active Bit 472" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "    SET/CLRACTIVE471 ,Set/Clear Active Bit 471" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE470 ,Set/Clear Active Bit 470" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "    SET/CLRACTIVE469 ,Set/Clear Active Bit 469" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "    SET/CLRACTIVE468 ,Set/Clear Active Bit 468" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE467 ,Set/Clear Active Bit 467" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "    SET/CLRACTIVE466 ,Set/Clear Active Bit 466" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "    SET/CLRACTIVE465 ,Set/Clear Active Bit 465" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE464 ,Set/Clear Active Bit 464" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "    SET/CLRACTIVE463 ,Set/Clear Active Bit 463" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "    SET/CLRACTIVE462 ,Set/Clear Active Bit 462" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE461 ,Set/Clear Active Bit 461" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "    SET/CLRACTIVE460 ,Set/Clear Active Bit 460" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "    SET/CLRACTIVE459 ,Set/Clear Active Bit 459" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE458 ,Set/Clear Active Bit 458" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "    SET/CLRACTIVE457 ,Set/Clear Active Bit 457" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "    SET/CLRACTIVE456 ,Set/Clear Active Bit 456" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE455 ,Set/Clear Active Bit 455" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "    SET/CLRACTIVE454 ,Set/Clear Active Bit 454" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "    SET/CLRACTIVE453 ,Set/Clear Active Bit 453" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE452 ,Set/Clear Active Bit 452" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "    SET/CLRACTIVE451 ,Set/Clear Active Bit 451" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "    SET/CLRACTIVE450 ,Set/Clear Active Bit 450" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE449 ,Set/Clear Active Bit 449" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "    SET/CLRACTIVE448 ,Set/Clear Active Bit 448" "Not active,Active"
else
rgroup.long 0x0338++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER14,Interrupt Set/Clear Active Register 14"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0F)
group.long 0x033C++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER15,Interrupt Set/Clear Active Register 15"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE511 ,Set/Clear Active Bit 511" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "    SET/CLRACTIVE510 ,Set/Clear Active Bit 510" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "    SET/CLRACTIVE509 ,Set/Clear Active Bit 509" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE508 ,Set/Clear Active Bit 508" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "    SET/CLRACTIVE507 ,Set/Clear Active Bit 507" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "    SET/CLRACTIVE506 ,Set/Clear Active Bit 506" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE505 ,Set/Clear Active Bit 505" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "    SET/CLRACTIVE504 ,Set/Clear Active Bit 504" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "    SET/CLRACTIVE503 ,Set/Clear Active Bit 503" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE502 ,Set/Clear Active Bit 502" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "    SET/CLRACTIVE501 ,Set/Clear Active Bit 501" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "    SET/CLRACTIVE500 ,Set/Clear Active Bit 500" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE499 ,Set/Clear Active Bit 499" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "    SET/CLRACTIVE498 ,Set/Clear Active Bit 498" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "    SET/CLRACTIVE497 ,Set/Clear Active Bit 497" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE496 ,Set/Clear Active Bit 496" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "    SET/CLRACTIVE495 ,Set/Clear Active Bit 495" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "    SET/CLRACTIVE494 ,Set/Clear Active Bit 494" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE493 ,Set/Clear Active Bit 493" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "    SET/CLRACTIVE492 ,Set/Clear Active Bit 492" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "    SET/CLRACTIVE491 ,Set/Clear Active Bit 491" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE490 ,Set/Clear Active Bit 490" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "    SET/CLRACTIVE489 ,Set/Clear Active Bit 489" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "    SET/CLRACTIVE488 ,Set/Clear Active Bit 488" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE487 ,Set/Clear Active Bit 487" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "    SET/CLRACTIVE486 ,Set/Clear Active Bit 486" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "    SET/CLRACTIVE485 ,Set/Clear Active Bit 485" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE484 ,Set/Clear Active Bit 484" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "    SET/CLRACTIVE483 ,Set/Clear Active Bit 483" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "    SET/CLRACTIVE482 ,Set/Clear Active Bit 482" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE481 ,Set/Clear Active Bit 481" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "    SET/CLRACTIVE480 ,Set/Clear Active Bit 480" "Not active,Active"
else
rgroup.long 0x033C++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER15,Interrupt Set/Clear Active Register 15"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
rgroup.long 0x0340++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER16,Interrupt Set/Clear Active Register 16"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
rgroup.long 0x0344++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER17,Interrupt Set/Clear Active Register 17"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
rgroup.long 0x0348++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER18,Interrupt Set/Clear Active Register 18"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
rgroup.long 0x034C++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER19,Interrupt Set/Clear Active Register 19"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
rgroup.long 0x0350++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER20,Interrupt Set/Clear Active Register 20"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
rgroup.long 0x0354++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER21,Interrupt Set/Clear Active Register 21"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
rgroup.long 0x0358++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER22,Interrupt Set/Clear Active Register 22"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
rgroup.long 0x035C++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER23,Interrupt Set/Clear Active Register 23"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
rgroup.long 0x0360++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER24,Interrupt Set/Clear Active Register 24"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
rgroup.long 0x0364++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER25,Interrupt Set/Clear Active Register 25"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
rgroup.long 0x0368++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER26,Interrupt Set/Clear Active Register 26"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
rgroup.long 0x036C++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER27,Interrupt Set/Clear Active Register 27"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
rgroup.long 0x0370++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER28,Interrupt Set/Clear Active Register 28"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
rgroup.long 0x0374++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER29,Interrupt Set/Clear Active Register 29"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
rgroup.long 0x0378++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER30,Interrupt Set/Clear Active Register 30"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
rgroup.long 0x037C++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER31,Interrupt Set/Clear Active Register 31"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
tree.end
tree "Priority Registers"
group.long 0x400++0x03
line.long 0x00 "GICD_IPRIORITYR0,Interrupt Priority Register 0"
hexmask.long.byte 0x00 24.--31. 1. " INTID3    ,Interrupt ID3    Priority/Priority Byte Offset 3   "
hexmask.long.byte 0x00 16.--23. 1. "  INTID2    ,Interrupt ID2     Priority/Priority Byte Offset 2   "
hexmask.long.byte 0x00 8.--15. 1. "  INTID1    ,Interrupt ID1    Priority/Priority Byte Offset 1   "
hexmask.long.byte 0x00 0.--7. 1. "  INTID0    ,Interrupt ID0     Priority/Priority Byte Offset 0   "
group.long 0x404++0x03
line.long 0x00 "GICD_IPRIORITYR1,Interrupt Priority Register 1"
hexmask.long.byte 0x00 24.--31. 1. " INTID7    ,Interrupt ID7    Priority/Priority Byte Offset 7   "
hexmask.long.byte 0x00 16.--23. 1. "  INTID6    ,Interrupt ID6     Priority/Priority Byte Offset 6   "
hexmask.long.byte 0x00 8.--15. 1. "  INTID5    ,Interrupt ID5    Priority/Priority Byte Offset 5   "
hexmask.long.byte 0x00 0.--7. 1. "  INTID4    ,Interrupt ID4     Priority/Priority Byte Offset 4   "
group.long 0x408++0x03
line.long 0x00 "GICD_IPRIORITYR2,Interrupt Priority Register 2"
hexmask.long.byte 0x00 24.--31. 1. " INTID11   ,Interrupt ID11   Priority/Priority Byte Offset 11  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID10   ,Interrupt ID10    Priority/Priority Byte Offset 10  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID9    ,Interrupt ID9    Priority/Priority Byte Offset 9   "
hexmask.long.byte 0x00 0.--7. 1. "  INTID8    ,Interrupt ID8     Priority/Priority Byte Offset 8   "
group.long 0x40C++0x03
line.long 0x00 "GICD_IPRIORITYR3,Interrupt Priority Register 3"
hexmask.long.byte 0x00 24.--31. 1. " INTID15   ,Interrupt ID15   Priority/Priority Byte Offset 15  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID14   ,Interrupt ID14    Priority/Priority Byte Offset 14  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID13   ,Interrupt ID13   Priority/Priority Byte Offset 13  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID12   ,Interrupt ID12    Priority/Priority Byte Offset 12  "
group.long 0x410++0x03
line.long 0x00 "GICD_IPRIORITYR4,Interrupt Priority Register 4"
hexmask.long.byte 0x00 24.--31. 1. " INTID19   ,Interrupt ID19   Priority/Priority Byte Offset 19  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID18   ,Interrupt ID18    Priority/Priority Byte Offset 18  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID17   ,Interrupt ID17   Priority/Priority Byte Offset 17  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID16   ,Interrupt ID16    Priority/Priority Byte Offset 16  "
group.long 0x414++0x03
line.long 0x00 "GICD_IPRIORITYR5,Interrupt Priority Register 5"
hexmask.long.byte 0x00 24.--31. 1. " INTID23   ,Interrupt ID23   Priority/Priority Byte Offset 23  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID22   ,Interrupt ID22    Priority/Priority Byte Offset 22  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID21   ,Interrupt ID21   Priority/Priority Byte Offset 21  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID20   ,Interrupt ID20    Priority/Priority Byte Offset 20  "
group.long 0x418++0x03
line.long 0x00 "GICD_IPRIORITYR6,Interrupt Priority Register 6"
hexmask.long.byte 0x00 24.--31. 1. " INTID27   ,Interrupt ID27   Priority/Priority Byte Offset 27  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID26   ,Interrupt ID26    Priority/Priority Byte Offset 26  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID25   ,Interrupt ID25   Priority/Priority Byte Offset 25  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID24   ,Interrupt ID24    Priority/Priority Byte Offset 24  "
group.long 0x41C++0x03
line.long 0x00 "GICD_IPRIORITYR7,Interrupt Priority Register 7"
hexmask.long.byte 0x00 24.--31. 1. " INTID31   ,Interrupt ID31   Priority/Priority Byte Offset 31  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID30   ,Interrupt ID30    Priority/Priority Byte Offset 30  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID29   ,Interrupt ID29   Priority/Priority Byte Offset 29  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID28   ,Interrupt ID28    Priority/Priority Byte Offset 28  "
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x01)
group.long 0x420++0x03
line.long 0x00 "GICD_IPRIORITYR8,Interrupt Priority Register 8"
hexmask.long.byte 0x00 24.--31. 1. " INTID35   ,Interrupt ID35   Priority/Priority Byte Offset 35  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID34   ,Interrupt ID34    Priority/Priority Byte Offset 34  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID33   ,Interrupt ID33   Priority/Priority Byte Offset 33  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID32   ,Interrupt ID32    Priority/Priority Byte Offset 32  "
group.long 0x424++0x03
line.long 0x00 "GICD_IPRIORITYR9,Interrupt Priority Register 9"
hexmask.long.byte 0x00 24.--31. 1. " INTID39   ,Interrupt ID39   Priority/Priority Byte Offset 39  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID38   ,Interrupt ID38    Priority/Priority Byte Offset 38  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID37   ,Interrupt ID37   Priority/Priority Byte Offset 37  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID36   ,Interrupt ID36    Priority/Priority Byte Offset 36  "
group.long 0x428++0x03
line.long 0x00 "GICD_IPRIORITYR10,Interrupt Priority Register 10"
hexmask.long.byte 0x00 24.--31. 1. " INTID43   ,Interrupt ID43   Priority/Priority Byte Offset 43  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID42   ,Interrupt ID42    Priority/Priority Byte Offset 42  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID41   ,Interrupt ID41   Priority/Priority Byte Offset 41  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID40   ,Interrupt ID40    Priority/Priority Byte Offset 40  "
group.long 0x42C++0x03
line.long 0x00 "GICD_IPRIORITYR11,Interrupt Priority Register 11"
hexmask.long.byte 0x00 24.--31. 1. " INTID47   ,Interrupt ID47   Priority/Priority Byte Offset 47  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID46   ,Interrupt ID46    Priority/Priority Byte Offset 46  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID45   ,Interrupt ID45   Priority/Priority Byte Offset 45  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID44   ,Interrupt ID44    Priority/Priority Byte Offset 44  "
group.long 0x430++0x03
line.long 0x00 "GICD_IPRIORITYR12,Interrupt Priority Register 12"
hexmask.long.byte 0x00 24.--31. 1. " INTID51   ,Interrupt ID51   Priority/Priority Byte Offset 51  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID50   ,Interrupt ID50    Priority/Priority Byte Offset 50  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID49   ,Interrupt ID49   Priority/Priority Byte Offset 49  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID48   ,Interrupt ID48    Priority/Priority Byte Offset 48  "
group.long 0x434++0x03
line.long 0x00 "GICD_IPRIORITYR13,Interrupt Priority Register 13"
hexmask.long.byte 0x00 24.--31. 1. " INTID55   ,Interrupt ID55   Priority/Priority Byte Offset 55  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID54   ,Interrupt ID54    Priority/Priority Byte Offset 54  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID53   ,Interrupt ID53   Priority/Priority Byte Offset 53  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID52   ,Interrupt ID52    Priority/Priority Byte Offset 52  "
group.long 0x438++0x03
line.long 0x00 "GICD_IPRIORITYR14,Interrupt Priority Register 14"
hexmask.long.byte 0x00 24.--31. 1. " INTID59   ,Interrupt ID59   Priority/Priority Byte Offset 59  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID58   ,Interrupt ID58    Priority/Priority Byte Offset 58  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID57   ,Interrupt ID57   Priority/Priority Byte Offset 57  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID56   ,Interrupt ID56    Priority/Priority Byte Offset 56  "
group.long 0x43C++0x03
line.long 0x00 "GICD_IPRIORITYR15,Interrupt Priority Register 15"
hexmask.long.byte 0x00 24.--31. 1. " INTID63   ,Interrupt ID63   Priority/Priority Byte Offset 63  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID62   ,Interrupt ID62    Priority/Priority Byte Offset 62  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID61   ,Interrupt ID61   Priority/Priority Byte Offset 61  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID60   ,Interrupt ID60    Priority/Priority Byte Offset 60  "
else
rgroup.long 0x420++0x03
line.long 0x00 "GICD_IPRIORITYR8,Interrupt Priority Register 8"
rgroup.long 0x424++0x03
line.long 0x00 "GICD_IPRIORITYR9,Interrupt Priority Register 9"
rgroup.long 0x428++0x03
line.long 0x00 "GICD_IPRIORITYR10,Interrupt Priority Register 10"
rgroup.long 0x42C++0x03
line.long 0x00 "GICD_IPRIORITYR11,Interrupt Priority Register 11"
rgroup.long 0x430++0x03
line.long 0x00 "GICD_IPRIORITYR12,Interrupt Priority Register 12"
rgroup.long 0x434++0x03
line.long 0x00 "GICD_IPRIORITYR13,Interrupt Priority Register 13"
rgroup.long 0x438++0x03
line.long 0x00 "GICD_IPRIORITYR14,Interrupt Priority Register 14"
rgroup.long 0x43C++0x03
line.long 0x00 "GICD_IPRIORITYR15,Interrupt Priority Register 15"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x02)
group.long 0x440++0x03
line.long 0x00 "GICD_IPRIORITYR16,Interrupt Priority Register 16"
hexmask.long.byte 0x00 24.--31. 1. " INTID67   ,Interrupt ID67   Priority/Priority Byte Offset 67  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID66   ,Interrupt ID66    Priority/Priority Byte Offset 66  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID65   ,Interrupt ID65   Priority/Priority Byte Offset 65  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID64   ,Interrupt ID64    Priority/Priority Byte Offset 64  "
group.long 0x444++0x03
line.long 0x00 "GICD_IPRIORITYR17,Interrupt Priority Register 17"
hexmask.long.byte 0x00 24.--31. 1. " INTID71   ,Interrupt ID71   Priority/Priority Byte Offset 71  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID70   ,Interrupt ID70    Priority/Priority Byte Offset 70  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID69   ,Interrupt ID69   Priority/Priority Byte Offset 69  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID68   ,Interrupt ID68    Priority/Priority Byte Offset 68  "
group.long 0x448++0x03
line.long 0x00 "GICD_IPRIORITYR18,Interrupt Priority Register 18"
hexmask.long.byte 0x00 24.--31. 1. " INTID75   ,Interrupt ID75   Priority/Priority Byte Offset 75  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID74   ,Interrupt ID74    Priority/Priority Byte Offset 74  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID73   ,Interrupt ID73   Priority/Priority Byte Offset 73  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID72   ,Interrupt ID72    Priority/Priority Byte Offset 72  "
group.long 0x44C++0x03
line.long 0x00 "GICD_IPRIORITYR19,Interrupt Priority Register 19"
hexmask.long.byte 0x00 24.--31. 1. " INTID79   ,Interrupt ID79   Priority/Priority Byte Offset 79  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID78   ,Interrupt ID78    Priority/Priority Byte Offset 78  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID77   ,Interrupt ID77   Priority/Priority Byte Offset 77  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID76   ,Interrupt ID76    Priority/Priority Byte Offset 76  "
group.long 0x450++0x03
line.long 0x00 "GICD_IPRIORITYR20,Interrupt Priority Register 20"
hexmask.long.byte 0x00 24.--31. 1. " INTID83   ,Interrupt ID83   Priority/Priority Byte Offset 83  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID82   ,Interrupt ID82    Priority/Priority Byte Offset 82  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID81   ,Interrupt ID81   Priority/Priority Byte Offset 81  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID80   ,Interrupt ID80    Priority/Priority Byte Offset 80  "
group.long 0x454++0x03
line.long 0x00 "GICD_IPRIORITYR21,Interrupt Priority Register 21"
hexmask.long.byte 0x00 24.--31. 1. " INTID87   ,Interrupt ID87   Priority/Priority Byte Offset 87  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID86   ,Interrupt ID86    Priority/Priority Byte Offset 86  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID85   ,Interrupt ID85   Priority/Priority Byte Offset 85  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID84   ,Interrupt ID84    Priority/Priority Byte Offset 84  "
group.long 0x458++0x03
line.long 0x00 "GICD_IPRIORITYR22,Interrupt Priority Register 22"
hexmask.long.byte 0x00 24.--31. 1. " INTID91   ,Interrupt ID91   Priority/Priority Byte Offset 91  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID90   ,Interrupt ID90    Priority/Priority Byte Offset 90  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID89   ,Interrupt ID89   Priority/Priority Byte Offset 89  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID88   ,Interrupt ID88    Priority/Priority Byte Offset 88  "
group.long 0x45C++0x03
line.long 0x00 "GICD_IPRIORITYR23,Interrupt Priority Register 23"
hexmask.long.byte 0x00 24.--31. 1. " INTID95   ,Interrupt ID95   Priority/Priority Byte Offset 95  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID94   ,Interrupt ID94    Priority/Priority Byte Offset 94  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID93   ,Interrupt ID93   Priority/Priority Byte Offset 93  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID92   ,Interrupt ID92    Priority/Priority Byte Offset 92  "
else
rgroup.long 0x440++0x03
line.long 0x00 "GICD_IPRIORITYR16,Interrupt Priority Register 16"
rgroup.long 0x444++0x03
line.long 0x00 "GICD_IPRIORITYR17,Interrupt Priority Register 17"
rgroup.long 0x448++0x03
line.long 0x00 "GICD_IPRIORITYR18,Interrupt Priority Register 18"
rgroup.long 0x44C++0x03
line.long 0x00 "GICD_IPRIORITYR19,Interrupt Priority Register 19"
rgroup.long 0x450++0x03
line.long 0x00 "GICD_IPRIORITYR20,Interrupt Priority Register 20"
rgroup.long 0x454++0x03
line.long 0x00 "GICD_IPRIORITYR21,Interrupt Priority Register 21"
rgroup.long 0x458++0x03
line.long 0x00 "GICD_IPRIORITYR22,Interrupt Priority Register 22"
rgroup.long 0x45C++0x03
line.long 0x00 "GICD_IPRIORITYR23,Interrupt Priority Register 23"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x03)
group.long 0x460++0x03
line.long 0x00 "GICD_IPRIORITYR24,Interrupt Priority Register 24"
hexmask.long.byte 0x00 24.--31. 1. " INTID99   ,Interrupt ID99   Priority/Priority Byte Offset 99  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID98   ,Interrupt ID98    Priority/Priority Byte Offset 98  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID97   ,Interrupt ID97   Priority/Priority Byte Offset 97  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID96   ,Interrupt ID96    Priority/Priority Byte Offset 96  "
group.long 0x464++0x03
line.long 0x00 "GICD_IPRIORITYR25,Interrupt Priority Register 25"
hexmask.long.byte 0x00 24.--31. 1. " INTID103  ,Interrupt ID103  Priority/Priority Byte Offset 103 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID102  ,Interrupt ID102   Priority/Priority Byte Offset 102 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID101  ,Interrupt ID101  Priority/Priority Byte Offset 101 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID100  ,Interrupt ID100   Priority/Priority Byte Offset 100 "
group.long 0x468++0x03
line.long 0x00 "GICD_IPRIORITYR26,Interrupt Priority Register 26"
hexmask.long.byte 0x00 24.--31. 1. " INTID107  ,Interrupt ID107  Priority/Priority Byte Offset 107 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID106  ,Interrupt ID106   Priority/Priority Byte Offset 106 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID105  ,Interrupt ID105  Priority/Priority Byte Offset 105 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID104  ,Interrupt ID104   Priority/Priority Byte Offset 104 "
group.long 0x46C++0x03
line.long 0x00 "GICD_IPRIORITYR27,Interrupt Priority Register 27"
hexmask.long.byte 0x00 24.--31. 1. " INTID111  ,Interrupt ID111  Priority/Priority Byte Offset 111 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID110  ,Interrupt ID110   Priority/Priority Byte Offset 110 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID109  ,Interrupt ID109  Priority/Priority Byte Offset 109 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID108  ,Interrupt ID108   Priority/Priority Byte Offset 108 "
group.long 0x470++0x03
line.long 0x00 "GICD_IPRIORITYR28,Interrupt Priority Register 28"
hexmask.long.byte 0x00 24.--31. 1. " INTID115  ,Interrupt ID115  Priority/Priority Byte Offset 115 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID114  ,Interrupt ID114   Priority/Priority Byte Offset 114 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID113  ,Interrupt ID113  Priority/Priority Byte Offset 113 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID112  ,Interrupt ID112   Priority/Priority Byte Offset 112 "
group.long 0x474++0x03
line.long 0x00 "GICD_IPRIORITYR29,Interrupt Priority Register 29"
hexmask.long.byte 0x00 24.--31. 1. " INTID119  ,Interrupt ID119  Priority/Priority Byte Offset 119 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID118  ,Interrupt ID118   Priority/Priority Byte Offset 118 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID117  ,Interrupt ID117  Priority/Priority Byte Offset 117 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID116  ,Interrupt ID116   Priority/Priority Byte Offset 116 "
group.long 0x478++0x03
line.long 0x00 "GICD_IPRIORITYR30,Interrupt Priority Register 30"
hexmask.long.byte 0x00 24.--31. 1. " INTID123  ,Interrupt ID123  Priority/Priority Byte Offset 123 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID122  ,Interrupt ID122   Priority/Priority Byte Offset 122 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID121  ,Interrupt ID121  Priority/Priority Byte Offset 121 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID120  ,Interrupt ID120   Priority/Priority Byte Offset 120 "
group.long 0x47C++0x03
line.long 0x00 "GICD_IPRIORITYR31,Interrupt Priority Register 31"
hexmask.long.byte 0x00 24.--31. 1. " INTID127  ,Interrupt ID127  Priority/Priority Byte Offset 127 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID126  ,Interrupt ID126   Priority/Priority Byte Offset 126 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID125  ,Interrupt ID125  Priority/Priority Byte Offset 125 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID124  ,Interrupt ID124   Priority/Priority Byte Offset 124 "
else
rgroup.long 0x460++0x03
line.long 0x00 "GICD_IPRIORITYR24,Interrupt Priority Register 24"
rgroup.long 0x464++0x03
line.long 0x00 "GICD_IPRIORITYR25,Interrupt Priority Register 25"
rgroup.long 0x468++0x03
line.long 0x00 "GICD_IPRIORITYR26,Interrupt Priority Register 26"
rgroup.long 0x46C++0x03
line.long 0x00 "GICD_IPRIORITYR27,Interrupt Priority Register 27"
rgroup.long 0x470++0x03
line.long 0x00 "GICD_IPRIORITYR28,Interrupt Priority Register 28"
rgroup.long 0x474++0x03
line.long 0x00 "GICD_IPRIORITYR29,Interrupt Priority Register 29"
rgroup.long 0x478++0x03
line.long 0x00 "GICD_IPRIORITYR30,Interrupt Priority Register 30"
rgroup.long 0x47C++0x03
line.long 0x00 "GICD_IPRIORITYR31,Interrupt Priority Register 31"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x04)
group.long 0x480++0x03
line.long 0x00 "GICD_IPRIORITYR32,Interrupt Priority Register 32"
hexmask.long.byte 0x00 24.--31. 1. " INTID131  ,Interrupt ID131  Priority/Priority Byte Offset 131 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID130  ,Interrupt ID130   Priority/Priority Byte Offset 130 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID129  ,Interrupt ID129  Priority/Priority Byte Offset 129 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID128  ,Interrupt ID128   Priority/Priority Byte Offset 128 "
group.long 0x484++0x03
line.long 0x00 "GICD_IPRIORITYR33,Interrupt Priority Register 33"
hexmask.long.byte 0x00 24.--31. 1. " INTID135  ,Interrupt ID135  Priority/Priority Byte Offset 135 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID134  ,Interrupt ID134   Priority/Priority Byte Offset 134 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID133  ,Interrupt ID133  Priority/Priority Byte Offset 133 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID132  ,Interrupt ID132   Priority/Priority Byte Offset 132 "
group.long 0x488++0x03
line.long 0x00 "GICD_IPRIORITYR34,Interrupt Priority Register 34"
hexmask.long.byte 0x00 24.--31. 1. " INTID139  ,Interrupt ID139  Priority/Priority Byte Offset 139 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID138  ,Interrupt ID138   Priority/Priority Byte Offset 138 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID137  ,Interrupt ID137  Priority/Priority Byte Offset 137 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID136  ,Interrupt ID136   Priority/Priority Byte Offset 136 "
group.long 0x48C++0x03
line.long 0x00 "GICD_IPRIORITYR35,Interrupt Priority Register 35"
hexmask.long.byte 0x00 24.--31. 1. " INTID143  ,Interrupt ID143  Priority/Priority Byte Offset 143 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID142  ,Interrupt ID142   Priority/Priority Byte Offset 142 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID141  ,Interrupt ID141  Priority/Priority Byte Offset 141 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID140  ,Interrupt ID140   Priority/Priority Byte Offset 140 "
group.long 0x490++0x03
line.long 0x00 "GICD_IPRIORITYR36,Interrupt Priority Register 36"
hexmask.long.byte 0x00 24.--31. 1. " INTID147  ,Interrupt ID147  Priority/Priority Byte Offset 147 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID146  ,Interrupt ID146   Priority/Priority Byte Offset 146 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID145  ,Interrupt ID145  Priority/Priority Byte Offset 145 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID144  ,Interrupt ID144   Priority/Priority Byte Offset 144 "
group.long 0x494++0x03
line.long 0x00 "GICD_IPRIORITYR37,Interrupt Priority Register 37"
hexmask.long.byte 0x00 24.--31. 1. " INTID151  ,Interrupt ID151  Priority/Priority Byte Offset 151 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID150  ,Interrupt ID150   Priority/Priority Byte Offset 150 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID149  ,Interrupt ID149  Priority/Priority Byte Offset 149 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID148  ,Interrupt ID148   Priority/Priority Byte Offset 148 "
group.long 0x498++0x03
line.long 0x00 "GICD_IPRIORITYR38,Interrupt Priority Register 38"
hexmask.long.byte 0x00 24.--31. 1. " INTID155  ,Interrupt ID155  Priority/Priority Byte Offset 155 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID154  ,Interrupt ID154   Priority/Priority Byte Offset 154 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID153  ,Interrupt ID153  Priority/Priority Byte Offset 153 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID152  ,Interrupt ID152   Priority/Priority Byte Offset 152 "
group.long 0x49C++0x03
line.long 0x00 "GICD_IPRIORITYR39,Interrupt Priority Register 39"
hexmask.long.byte 0x00 24.--31. 1. " INTID159  ,Interrupt ID159  Priority/Priority Byte Offset 159 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID158  ,Interrupt ID158   Priority/Priority Byte Offset 158 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID157  ,Interrupt ID157  Priority/Priority Byte Offset 157 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID156  ,Interrupt ID156   Priority/Priority Byte Offset 156 "
else
rgroup.long 0x480++0x03
line.long 0x00 "GICD_IPRIORITYR32,Interrupt Priority Register 32"
rgroup.long 0x484++0x03
line.long 0x00 "GICD_IPRIORITYR33,Interrupt Priority Register 33"
rgroup.long 0x488++0x03
line.long 0x00 "GICD_IPRIORITYR34,Interrupt Priority Register 34"
rgroup.long 0x48C++0x03
line.long 0x00 "GICD_IPRIORITYR35,Interrupt Priority Register 35"
rgroup.long 0x490++0x03
line.long 0x00 "GICD_IPRIORITYR36,Interrupt Priority Register 36"
rgroup.long 0x494++0x03
line.long 0x00 "GICD_IPRIORITYR37,Interrupt Priority Register 37"
rgroup.long 0x498++0x03
line.long 0x00 "GICD_IPRIORITYR38,Interrupt Priority Register 38"
rgroup.long 0x49C++0x03
line.long 0x00 "GICD_IPRIORITYR39,Interrupt Priority Register 39"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x05)
group.long 0x4A0++0x03
line.long 0x00 "GICD_IPRIORITYR40,Interrupt Priority Register 40"
hexmask.long.byte 0x00 24.--31. 1. " INTID163  ,Interrupt ID163  Priority/Priority Byte Offset 163 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID162  ,Interrupt ID162   Priority/Priority Byte Offset 162 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID161  ,Interrupt ID161  Priority/Priority Byte Offset 161 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID160  ,Interrupt ID160   Priority/Priority Byte Offset 160 "
group.long 0x4A4++0x03
line.long 0x00 "GICD_IPRIORITYR41,Interrupt Priority Register 41"
hexmask.long.byte 0x00 24.--31. 1. " INTID167  ,Interrupt ID167  Priority/Priority Byte Offset 167 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID166  ,Interrupt ID166   Priority/Priority Byte Offset 166 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID165  ,Interrupt ID165  Priority/Priority Byte Offset 165 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID164  ,Interrupt ID164   Priority/Priority Byte Offset 164 "
group.long 0x4A8++0x03
line.long 0x00 "GICD_IPRIORITYR42,Interrupt Priority Register 42"
hexmask.long.byte 0x00 24.--31. 1. " INTID171  ,Interrupt ID171  Priority/Priority Byte Offset 171 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID170  ,Interrupt ID170   Priority/Priority Byte Offset 170 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID169  ,Interrupt ID169  Priority/Priority Byte Offset 169 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID168  ,Interrupt ID168   Priority/Priority Byte Offset 168 "
group.long 0x4AC++0x03
line.long 0x00 "GICD_IPRIORITYR43,Interrupt Priority Register 43"
hexmask.long.byte 0x00 24.--31. 1. " INTID175  ,Interrupt ID175  Priority/Priority Byte Offset 175 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID174  ,Interrupt ID174   Priority/Priority Byte Offset 174 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID173  ,Interrupt ID173  Priority/Priority Byte Offset 173 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID172  ,Interrupt ID172   Priority/Priority Byte Offset 172 "
group.long 0x4B0++0x03
line.long 0x00 "GICD_IPRIORITYR44,Interrupt Priority Register 44"
hexmask.long.byte 0x00 24.--31. 1. " INTID179  ,Interrupt ID179  Priority/Priority Byte Offset 179 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID178  ,Interrupt ID178   Priority/Priority Byte Offset 178 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID177  ,Interrupt ID177  Priority/Priority Byte Offset 177 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID176  ,Interrupt ID176   Priority/Priority Byte Offset 176 "
group.long 0x4B4++0x03
line.long 0x00 "GICD_IPRIORITYR45,Interrupt Priority Register 45"
hexmask.long.byte 0x00 24.--31. 1. " INTID183  ,Interrupt ID183  Priority/Priority Byte Offset 183 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID182  ,Interrupt ID182   Priority/Priority Byte Offset 182 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID181  ,Interrupt ID181  Priority/Priority Byte Offset 181 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID180  ,Interrupt ID180   Priority/Priority Byte Offset 180 "
group.long 0x4B8++0x03
line.long 0x00 "GICD_IPRIORITYR46,Interrupt Priority Register 46"
hexmask.long.byte 0x00 24.--31. 1. " INTID187  ,Interrupt ID187  Priority/Priority Byte Offset 187 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID186  ,Interrupt ID186   Priority/Priority Byte Offset 186 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID185  ,Interrupt ID185  Priority/Priority Byte Offset 185 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID184  ,Interrupt ID184   Priority/Priority Byte Offset 184 "
group.long 0x4BC++0x03
line.long 0x00 "GICD_IPRIORITYR47,Interrupt Priority Register 47"
hexmask.long.byte 0x00 24.--31. 1. " INTID191  ,Interrupt ID191  Priority/Priority Byte Offset 191 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID190  ,Interrupt ID190   Priority/Priority Byte Offset 190 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID189  ,Interrupt ID189  Priority/Priority Byte Offset 189 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID188  ,Interrupt ID188   Priority/Priority Byte Offset 188 "
else
rgroup.long 0x4A0++0x03
line.long 0x00 "GICD_IPRIORITYR40,Interrupt Priority Register 40"
rgroup.long 0x4A4++0x03
line.long 0x00 "GICD_IPRIORITYR41,Interrupt Priority Register 41"
rgroup.long 0x4A8++0x03
line.long 0x00 "GICD_IPRIORITYR42,Interrupt Priority Register 42"
rgroup.long 0x4AC++0x03
line.long 0x00 "GICD_IPRIORITYR43,Interrupt Priority Register 43"
rgroup.long 0x4B0++0x03
line.long 0x00 "GICD_IPRIORITYR44,Interrupt Priority Register 44"
rgroup.long 0x4B4++0x03
line.long 0x00 "GICD_IPRIORITYR45,Interrupt Priority Register 45"
rgroup.long 0x4B8++0x03
line.long 0x00 "GICD_IPRIORITYR46,Interrupt Priority Register 46"
rgroup.long 0x4BC++0x03
line.long 0x00 "GICD_IPRIORITYR47,Interrupt Priority Register 47"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x06)
group.long 0x4C0++0x03
line.long 0x00 "GICD_IPRIORITYR48,Interrupt Priority Register 48"
hexmask.long.byte 0x00 24.--31. 1. " INTID195  ,Interrupt ID195  Priority/Priority Byte Offset 195 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID194  ,Interrupt ID194   Priority/Priority Byte Offset 194 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID193  ,Interrupt ID193  Priority/Priority Byte Offset 193 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID192  ,Interrupt ID192   Priority/Priority Byte Offset 192 "
group.long 0x4C4++0x03
line.long 0x00 "GICD_IPRIORITYR49,Interrupt Priority Register 49"
hexmask.long.byte 0x00 24.--31. 1. " INTID199  ,Interrupt ID199  Priority/Priority Byte Offset 199 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID198  ,Interrupt ID198   Priority/Priority Byte Offset 198 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID197  ,Interrupt ID197  Priority/Priority Byte Offset 197 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID196  ,Interrupt ID196   Priority/Priority Byte Offset 196 "
group.long 0x4C8++0x03
line.long 0x00 "GICD_IPRIORITYR50,Interrupt Priority Register 50"
hexmask.long.byte 0x00 24.--31. 1. " INTID203  ,Interrupt ID203  Priority/Priority Byte Offset 203 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID202  ,Interrupt ID202   Priority/Priority Byte Offset 202 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID201  ,Interrupt ID201  Priority/Priority Byte Offset 201 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID200  ,Interrupt ID200   Priority/Priority Byte Offset 200 "
group.long 0x4CC++0x03
line.long 0x00 "GICD_IPRIORITYR51,Interrupt Priority Register 51"
hexmask.long.byte 0x00 24.--31. 1. " INTID207  ,Interrupt ID207  Priority/Priority Byte Offset 207 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID206  ,Interrupt ID206   Priority/Priority Byte Offset 206 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID205  ,Interrupt ID205  Priority/Priority Byte Offset 205 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID204  ,Interrupt ID204   Priority/Priority Byte Offset 204 "
group.long 0x4D0++0x03
line.long 0x00 "GICD_IPRIORITYR52,Interrupt Priority Register 52"
hexmask.long.byte 0x00 24.--31. 1. " INTID211  ,Interrupt ID211  Priority/Priority Byte Offset 211 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID210  ,Interrupt ID210   Priority/Priority Byte Offset 210 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID209  ,Interrupt ID209  Priority/Priority Byte Offset 209 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID208  ,Interrupt ID208   Priority/Priority Byte Offset 208 "
group.long 0x4D4++0x03
line.long 0x00 "GICD_IPRIORITYR53,Interrupt Priority Register 53"
hexmask.long.byte 0x00 24.--31. 1. " INTID215  ,Interrupt ID215  Priority/Priority Byte Offset 215 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID214  ,Interrupt ID214   Priority/Priority Byte Offset 214 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID213  ,Interrupt ID213  Priority/Priority Byte Offset 213 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID212  ,Interrupt ID212   Priority/Priority Byte Offset 212 "
group.long 0x4D8++0x03
line.long 0x00 "GICD_IPRIORITYR54,Interrupt Priority Register 54"
hexmask.long.byte 0x00 24.--31. 1. " INTID219  ,Interrupt ID219  Priority/Priority Byte Offset 219 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID218  ,Interrupt ID218   Priority/Priority Byte Offset 218 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID217  ,Interrupt ID217  Priority/Priority Byte Offset 217 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID216  ,Interrupt ID216   Priority/Priority Byte Offset 216 "
group.long 0x4DC++0x03
line.long 0x00 "GICD_IPRIORITYR55,Interrupt Priority Register 55"
hexmask.long.byte 0x00 24.--31. 1. " INTID223  ,Interrupt ID223  Priority/Priority Byte Offset 223 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID222  ,Interrupt ID222   Priority/Priority Byte Offset 222 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID221  ,Interrupt ID221  Priority/Priority Byte Offset 221 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID220  ,Interrupt ID220   Priority/Priority Byte Offset 220 "
else
rgroup.long 0x4C0++0x03
line.long 0x00 "GICD_IPRIORITYR48,Interrupt Priority Register 48"
rgroup.long 0x4C4++0x03
line.long 0x00 "GICD_IPRIORITYR49,Interrupt Priority Register 49"
rgroup.long 0x4C8++0x03
line.long 0x00 "GICD_IPRIORITYR50,Interrupt Priority Register 50"
rgroup.long 0x4CC++0x03
line.long 0x00 "GICD_IPRIORITYR51,Interrupt Priority Register 51"
rgroup.long 0x4D0++0x03
line.long 0x00 "GICD_IPRIORITYR52,Interrupt Priority Register 52"
rgroup.long 0x4D4++0x03
line.long 0x00 "GICD_IPRIORITYR53,Interrupt Priority Register 53"
rgroup.long 0x4D8++0x03
line.long 0x00 "GICD_IPRIORITYR54,Interrupt Priority Register 54"
rgroup.long 0x4DC++0x03
line.long 0x00 "GICD_IPRIORITYR55,Interrupt Priority Register 55"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x07)
group.long 0x4E0++0x03
line.long 0x00 "GICD_IPRIORITYR56,Interrupt Priority Register 56"
hexmask.long.byte 0x00 24.--31. 1. " INTID227  ,Interrupt ID227  Priority/Priority Byte Offset 227 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID226  ,Interrupt ID226   Priority/Priority Byte Offset 226 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID225  ,Interrupt ID225  Priority/Priority Byte Offset 225 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID224  ,Interrupt ID224   Priority/Priority Byte Offset 224 "
group.long 0x4E4++0x03
line.long 0x00 "GICD_IPRIORITYR57,Interrupt Priority Register 57"
hexmask.long.byte 0x00 24.--31. 1. " INTID231  ,Interrupt ID231  Priority/Priority Byte Offset 231 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID230  ,Interrupt ID230   Priority/Priority Byte Offset 230 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID229  ,Interrupt ID229  Priority/Priority Byte Offset 229 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID228  ,Interrupt ID228   Priority/Priority Byte Offset 228 "
group.long 0x4E8++0x03
line.long 0x00 "GICD_IPRIORITYR58,Interrupt Priority Register 58"
hexmask.long.byte 0x00 24.--31. 1. " INTID235  ,Interrupt ID235  Priority/Priority Byte Offset 235 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID234  ,Interrupt ID234   Priority/Priority Byte Offset 234 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID233  ,Interrupt ID233  Priority/Priority Byte Offset 233 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID232  ,Interrupt ID232   Priority/Priority Byte Offset 232 "
group.long 0x4EC++0x03
line.long 0x00 "GICD_IPRIORITYR59,Interrupt Priority Register 59"
hexmask.long.byte 0x00 24.--31. 1. " INTID239  ,Interrupt ID239  Priority/Priority Byte Offset 239 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID238  ,Interrupt ID238   Priority/Priority Byte Offset 238 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID237  ,Interrupt ID237  Priority/Priority Byte Offset 237 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID236  ,Interrupt ID236   Priority/Priority Byte Offset 236 "
group.long 0x4F0++0x03
line.long 0x00 "GICD_IPRIORITYR60,Interrupt Priority Register 60"
hexmask.long.byte 0x00 24.--31. 1. " INTID243  ,Interrupt ID243  Priority/Priority Byte Offset 243 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID242  ,Interrupt ID242   Priority/Priority Byte Offset 242 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID241  ,Interrupt ID241  Priority/Priority Byte Offset 241 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID240  ,Interrupt ID240   Priority/Priority Byte Offset 240 "
group.long 0x4F4++0x03
line.long 0x00 "GICD_IPRIORITYR61,Interrupt Priority Register 61"
hexmask.long.byte 0x00 24.--31. 1. " INTID247  ,Interrupt ID247  Priority/Priority Byte Offset 247 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID246  ,Interrupt ID246   Priority/Priority Byte Offset 246 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID245  ,Interrupt ID245  Priority/Priority Byte Offset 245 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID244  ,Interrupt ID244   Priority/Priority Byte Offset 244 "
group.long 0x4F8++0x03
line.long 0x00 "GICD_IPRIORITYR62,Interrupt Priority Register 62"
hexmask.long.byte 0x00 24.--31. 1. " INTID251  ,Interrupt ID251  Priority/Priority Byte Offset 251 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID250  ,Interrupt ID250   Priority/Priority Byte Offset 250 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID249  ,Interrupt ID249  Priority/Priority Byte Offset 249 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID248  ,Interrupt ID248   Priority/Priority Byte Offset 248 "
group.long 0x4FC++0x03
line.long 0x00 "GICD_IPRIORITYR63,Interrupt Priority Register 63"
hexmask.long.byte 0x00 24.--31. 1. " INTID255  ,Interrupt ID255  Priority/Priority Byte Offset 255 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID254  ,Interrupt ID254   Priority/Priority Byte Offset 254 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID253  ,Interrupt ID253  Priority/Priority Byte Offset 253 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID252  ,Interrupt ID252   Priority/Priority Byte Offset 252 "
else
rgroup.long 0x4E0++0x03
line.long 0x00 "GICD_IPRIORITYR56,Interrupt Priority Register 56"
rgroup.long 0x4E4++0x03
line.long 0x00 "GICD_IPRIORITYR57,Interrupt Priority Register 57"
rgroup.long 0x4E8++0x03
line.long 0x00 "GICD_IPRIORITYR58,Interrupt Priority Register 58"
rgroup.long 0x4EC++0x03
line.long 0x00 "GICD_IPRIORITYR59,Interrupt Priority Register 59"
rgroup.long 0x4F0++0x03
line.long 0x00 "GICD_IPRIORITYR60,Interrupt Priority Register 60"
rgroup.long 0x4F4++0x03
line.long 0x00 "GICD_IPRIORITYR61,Interrupt Priority Register 61"
rgroup.long 0x4F8++0x03
line.long 0x00 "GICD_IPRIORITYR62,Interrupt Priority Register 62"
rgroup.long 0x4FC++0x03
line.long 0x00 "GICD_IPRIORITYR63,Interrupt Priority Register 63"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x08)
group.long 0x500++0x03
line.long 0x00 "GICD_IPRIORITYR64,Interrupt Priority Register 64"
hexmask.long.byte 0x00 24.--31. 1. " INTID259  ,Interrupt ID259  Priority/Priority Byte Offset 259 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID258  ,Interrupt ID258   Priority/Priority Byte Offset 258 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID257  ,Interrupt ID257  Priority/Priority Byte Offset 257 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID256  ,Interrupt ID256   Priority/Priority Byte Offset 256 "
group.long 0x504++0x03
line.long 0x00 "GICD_IPRIORITYR65,Interrupt Priority Register 65"
hexmask.long.byte 0x00 24.--31. 1. " INTID263  ,Interrupt ID263  Priority/Priority Byte Offset 263 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID262  ,Interrupt ID262   Priority/Priority Byte Offset 262 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID261  ,Interrupt ID261  Priority/Priority Byte Offset 261 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID260  ,Interrupt ID260   Priority/Priority Byte Offset 260 "
group.long 0x508++0x03
line.long 0x00 "GICD_IPRIORITYR66,Interrupt Priority Register 66"
hexmask.long.byte 0x00 24.--31. 1. " INTID267  ,Interrupt ID267  Priority/Priority Byte Offset 267 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID266  ,Interrupt ID266   Priority/Priority Byte Offset 266 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID265  ,Interrupt ID265  Priority/Priority Byte Offset 265 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID264  ,Interrupt ID264   Priority/Priority Byte Offset 264 "
group.long 0x50C++0x03
line.long 0x00 "GICD_IPRIORITYR67,Interrupt Priority Register 67"
hexmask.long.byte 0x00 24.--31. 1. " INTID271  ,Interrupt ID271  Priority/Priority Byte Offset 271 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID270  ,Interrupt ID270   Priority/Priority Byte Offset 270 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID269  ,Interrupt ID269  Priority/Priority Byte Offset 269 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID268  ,Interrupt ID268   Priority/Priority Byte Offset 268 "
group.long 0x510++0x03
line.long 0x00 "GICD_IPRIORITYR68,Interrupt Priority Register 68"
hexmask.long.byte 0x00 24.--31. 1. " INTID275  ,Interrupt ID275  Priority/Priority Byte Offset 275 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID274  ,Interrupt ID274   Priority/Priority Byte Offset 274 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID273  ,Interrupt ID273  Priority/Priority Byte Offset 273 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID272  ,Interrupt ID272   Priority/Priority Byte Offset 272 "
group.long 0x514++0x03
line.long 0x00 "GICD_IPRIORITYR69,Interrupt Priority Register 69"
hexmask.long.byte 0x00 24.--31. 1. " INTID279  ,Interrupt ID279  Priority/Priority Byte Offset 279 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID278  ,Interrupt ID278   Priority/Priority Byte Offset 278 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID277  ,Interrupt ID277  Priority/Priority Byte Offset 277 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID276  ,Interrupt ID276   Priority/Priority Byte Offset 276 "
group.long 0x518++0x03
line.long 0x00 "GICD_IPRIORITYR70,Interrupt Priority Register 70"
hexmask.long.byte 0x00 24.--31. 1. " INTID283  ,Interrupt ID283  Priority/Priority Byte Offset 283 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID282  ,Interrupt ID282   Priority/Priority Byte Offset 282 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID281  ,Interrupt ID281  Priority/Priority Byte Offset 281 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID280  ,Interrupt ID280   Priority/Priority Byte Offset 280 "
group.long 0x51C++0x03
line.long 0x00 "GICD_IPRIORITYR71,Interrupt Priority Register 71"
hexmask.long.byte 0x00 24.--31. 1. " INTID287  ,Interrupt ID287  Priority/Priority Byte Offset 287 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID286  ,Interrupt ID286   Priority/Priority Byte Offset 286 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID285  ,Interrupt ID285  Priority/Priority Byte Offset 285 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID284  ,Interrupt ID284   Priority/Priority Byte Offset 284 "
else
rgroup.long 0x500++0x03
line.long 0x00 "GICD_IPRIORITYR64,Interrupt Priority Register 64"
rgroup.long 0x504++0x03
line.long 0x00 "GICD_IPRIORITYR65,Interrupt Priority Register 65"
rgroup.long 0x508++0x03
line.long 0x00 "GICD_IPRIORITYR66,Interrupt Priority Register 66"
rgroup.long 0x50C++0x03
line.long 0x00 "GICD_IPRIORITYR67,Interrupt Priority Register 67"
rgroup.long 0x510++0x03
line.long 0x00 "GICD_IPRIORITYR68,Interrupt Priority Register 68"
rgroup.long 0x514++0x03
line.long 0x00 "GICD_IPRIORITYR69,Interrupt Priority Register 69"
rgroup.long 0x518++0x03
line.long 0x00 "GICD_IPRIORITYR70,Interrupt Priority Register 70"
rgroup.long 0x51C++0x03
line.long 0x00 "GICD_IPRIORITYR71,Interrupt Priority Register 71"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x09)
group.long 0x520++0x03
line.long 0x00 "GICD_IPRIORITYR72,Interrupt Priority Register 72"
hexmask.long.byte 0x00 24.--31. 1. " INTID291  ,Interrupt ID291  Priority/Priority Byte Offset 291 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID290  ,Interrupt ID290   Priority/Priority Byte Offset 290 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID289  ,Interrupt ID289  Priority/Priority Byte Offset 289 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID288  ,Interrupt ID288   Priority/Priority Byte Offset 288 "
group.long 0x524++0x03
line.long 0x00 "GICD_IPRIORITYR73,Interrupt Priority Register 73"
hexmask.long.byte 0x00 24.--31. 1. " INTID295  ,Interrupt ID295  Priority/Priority Byte Offset 295 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID294  ,Interrupt ID294   Priority/Priority Byte Offset 294 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID293  ,Interrupt ID293  Priority/Priority Byte Offset 293 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID292  ,Interrupt ID292   Priority/Priority Byte Offset 292 "
group.long 0x528++0x03
line.long 0x00 "GICD_IPRIORITYR74,Interrupt Priority Register 74"
hexmask.long.byte 0x00 24.--31. 1. " INTID299  ,Interrupt ID299  Priority/Priority Byte Offset 299 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID298  ,Interrupt ID298   Priority/Priority Byte Offset 298 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID297  ,Interrupt ID297  Priority/Priority Byte Offset 297 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID296  ,Interrupt ID296   Priority/Priority Byte Offset 296 "
group.long 0x52C++0x03
line.long 0x00 "GICD_IPRIORITYR75,Interrupt Priority Register 75"
hexmask.long.byte 0x00 24.--31. 1. " INTID303  ,Interrupt ID303  Priority/Priority Byte Offset 303 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID302  ,Interrupt ID302   Priority/Priority Byte Offset 302 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID301  ,Interrupt ID301  Priority/Priority Byte Offset 301 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID300  ,Interrupt ID300   Priority/Priority Byte Offset 300 "
group.long 0x530++0x03
line.long 0x00 "GICD_IPRIORITYR76,Interrupt Priority Register 76"
hexmask.long.byte 0x00 24.--31. 1. " INTID307  ,Interrupt ID307  Priority/Priority Byte Offset 307 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID306  ,Interrupt ID306   Priority/Priority Byte Offset 306 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID305  ,Interrupt ID305  Priority/Priority Byte Offset 305 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID304  ,Interrupt ID304   Priority/Priority Byte Offset 304 "
group.long 0x534++0x03
line.long 0x00 "GICD_IPRIORITYR77,Interrupt Priority Register 77"
hexmask.long.byte 0x00 24.--31. 1. " INTID311  ,Interrupt ID311  Priority/Priority Byte Offset 311 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID310  ,Interrupt ID310   Priority/Priority Byte Offset 310 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID309  ,Interrupt ID309  Priority/Priority Byte Offset 309 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID308  ,Interrupt ID308   Priority/Priority Byte Offset 308 "
group.long 0x538++0x03
line.long 0x00 "GICD_IPRIORITYR78,Interrupt Priority Register 78"
hexmask.long.byte 0x00 24.--31. 1. " INTID315  ,Interrupt ID315  Priority/Priority Byte Offset 315 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID314  ,Interrupt ID314   Priority/Priority Byte Offset 314 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID313  ,Interrupt ID313  Priority/Priority Byte Offset 313 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID312  ,Interrupt ID312   Priority/Priority Byte Offset 312 "
group.long 0x53C++0x03
line.long 0x00 "GICD_IPRIORITYR79,Interrupt Priority Register 79"
hexmask.long.byte 0x00 24.--31. 1. " INTID319  ,Interrupt ID319  Priority/Priority Byte Offset 319 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID318  ,Interrupt ID318   Priority/Priority Byte Offset 318 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID317  ,Interrupt ID317  Priority/Priority Byte Offset 317 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID316  ,Interrupt ID316   Priority/Priority Byte Offset 316 "
else
rgroup.long 0x520++0x03
line.long 0x00 "GICD_IPRIORITYR72,Interrupt Priority Register 72"
rgroup.long 0x524++0x03
line.long 0x00 "GICD_IPRIORITYR73,Interrupt Priority Register 73"
rgroup.long 0x528++0x03
line.long 0x00 "GICD_IPRIORITYR74,Interrupt Priority Register 74"
rgroup.long 0x52C++0x03
line.long 0x00 "GICD_IPRIORITYR75,Interrupt Priority Register 75"
rgroup.long 0x530++0x03
line.long 0x00 "GICD_IPRIORITYR76,Interrupt Priority Register 76"
rgroup.long 0x534++0x03
line.long 0x00 "GICD_IPRIORITYR77,Interrupt Priority Register 77"
rgroup.long 0x538++0x03
line.long 0x00 "GICD_IPRIORITYR78,Interrupt Priority Register 78"
rgroup.long 0x53C++0x03
line.long 0x00 "GICD_IPRIORITYR79,Interrupt Priority Register 79"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0A)
group.long 0x540++0x03
line.long 0x00 "GICD_IPRIORITYR80,Interrupt Priority Register 80"
hexmask.long.byte 0x00 24.--31. 1. " INTID323  ,Interrupt ID323  Priority/Priority Byte Offset 323 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID322  ,Interrupt ID322   Priority/Priority Byte Offset 322 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID321  ,Interrupt ID321  Priority/Priority Byte Offset 321 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID320  ,Interrupt ID320   Priority/Priority Byte Offset 320 "
group.long 0x544++0x03
line.long 0x00 "GICD_IPRIORITYR81,Interrupt Priority Register 81"
hexmask.long.byte 0x00 24.--31. 1. " INTID327  ,Interrupt ID327  Priority/Priority Byte Offset 327 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID326  ,Interrupt ID326   Priority/Priority Byte Offset 326 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID325  ,Interrupt ID325  Priority/Priority Byte Offset 325 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID324  ,Interrupt ID324   Priority/Priority Byte Offset 324 "
group.long 0x548++0x03
line.long 0x00 "GICD_IPRIORITYR82,Interrupt Priority Register 82"
hexmask.long.byte 0x00 24.--31. 1. " INTID331  ,Interrupt ID331  Priority/Priority Byte Offset 331 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID330  ,Interrupt ID330   Priority/Priority Byte Offset 330 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID329  ,Interrupt ID329  Priority/Priority Byte Offset 329 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID328  ,Interrupt ID328   Priority/Priority Byte Offset 328 "
group.long 0x54C++0x03
line.long 0x00 "GICD_IPRIORITYR83,Interrupt Priority Register 83"
hexmask.long.byte 0x00 24.--31. 1. " INTID335  ,Interrupt ID335  Priority/Priority Byte Offset 335 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID334  ,Interrupt ID334   Priority/Priority Byte Offset 334 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID333  ,Interrupt ID333  Priority/Priority Byte Offset 333 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID332  ,Interrupt ID332   Priority/Priority Byte Offset 332 "
group.long 0x550++0x03
line.long 0x00 "GICD_IPRIORITYR84,Interrupt Priority Register 84"
hexmask.long.byte 0x00 24.--31. 1. " INTID339  ,Interrupt ID339  Priority/Priority Byte Offset 339 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID338  ,Interrupt ID338   Priority/Priority Byte Offset 338 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID337  ,Interrupt ID337  Priority/Priority Byte Offset 337 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID336  ,Interrupt ID336   Priority/Priority Byte Offset 336 "
group.long 0x554++0x03
line.long 0x00 "GICD_IPRIORITYR85,Interrupt Priority Register 85"
hexmask.long.byte 0x00 24.--31. 1. " INTID343  ,Interrupt ID343  Priority/Priority Byte Offset 343 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID342  ,Interrupt ID342   Priority/Priority Byte Offset 342 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID341  ,Interrupt ID341  Priority/Priority Byte Offset 341 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID340  ,Interrupt ID340   Priority/Priority Byte Offset 340 "
group.long 0x558++0x03
line.long 0x00 "GICD_IPRIORITYR86,Interrupt Priority Register 86"
hexmask.long.byte 0x00 24.--31. 1. " INTID347  ,Interrupt ID347  Priority/Priority Byte Offset 347 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID346  ,Interrupt ID346   Priority/Priority Byte Offset 346 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID345  ,Interrupt ID345  Priority/Priority Byte Offset 345 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID344  ,Interrupt ID344   Priority/Priority Byte Offset 344 "
group.long 0x55C++0x03
line.long 0x00 "GICD_IPRIORITYR87,Interrupt Priority Register 87"
hexmask.long.byte 0x00 24.--31. 1. " INTID351  ,Interrupt ID351  Priority/Priority Byte Offset 351 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID350  ,Interrupt ID350   Priority/Priority Byte Offset 350 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID349  ,Interrupt ID349  Priority/Priority Byte Offset 349 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID348  ,Interrupt ID348   Priority/Priority Byte Offset 348 "
else
rgroup.long 0x540++0x03
line.long 0x00 "GICD_IPRIORITYR80,Interrupt Priority Register 80"
rgroup.long 0x544++0x03
line.long 0x00 "GICD_IPRIORITYR81,Interrupt Priority Register 81"
rgroup.long 0x548++0x03
line.long 0x00 "GICD_IPRIORITYR82,Interrupt Priority Register 82"
rgroup.long 0x54C++0x03
line.long 0x00 "GICD_IPRIORITYR83,Interrupt Priority Register 83"
rgroup.long 0x550++0x03
line.long 0x00 "GICD_IPRIORITYR84,Interrupt Priority Register 84"
rgroup.long 0x554++0x03
line.long 0x00 "GICD_IPRIORITYR85,Interrupt Priority Register 85"
rgroup.long 0x558++0x03
line.long 0x00 "GICD_IPRIORITYR86,Interrupt Priority Register 86"
rgroup.long 0x55C++0x03
line.long 0x00 "GICD_IPRIORITYR87,Interrupt Priority Register 87"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0B)
group.long 0x560++0x03
line.long 0x00 "GICD_IPRIORITYR88,Interrupt Priority Register 88"
hexmask.long.byte 0x00 24.--31. 1. " INTID355  ,Interrupt ID355  Priority/Priority Byte Offset 355 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID354  ,Interrupt ID354   Priority/Priority Byte Offset 354 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID353  ,Interrupt ID353  Priority/Priority Byte Offset 353 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID352  ,Interrupt ID352   Priority/Priority Byte Offset 352 "
group.long 0x564++0x03
line.long 0x00 "GICD_IPRIORITYR89,Interrupt Priority Register 89"
hexmask.long.byte 0x00 24.--31. 1. " INTID359  ,Interrupt ID359  Priority/Priority Byte Offset 359 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID358  ,Interrupt ID358   Priority/Priority Byte Offset 358 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID357  ,Interrupt ID357  Priority/Priority Byte Offset 357 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID356  ,Interrupt ID356   Priority/Priority Byte Offset 356 "
group.long 0x568++0x03
line.long 0x00 "GICD_IPRIORITYR90,Interrupt Priority Register 90"
hexmask.long.byte 0x00 24.--31. 1. " INTID363  ,Interrupt ID363  Priority/Priority Byte Offset 363 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID362  ,Interrupt ID362   Priority/Priority Byte Offset 362 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID361  ,Interrupt ID361  Priority/Priority Byte Offset 361 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID360  ,Interrupt ID360   Priority/Priority Byte Offset 360 "
group.long 0x56C++0x03
line.long 0x00 "GICD_IPRIORITYR91,Interrupt Priority Register 91"
hexmask.long.byte 0x00 24.--31. 1. " INTID367  ,Interrupt ID367  Priority/Priority Byte Offset 367 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID366  ,Interrupt ID366   Priority/Priority Byte Offset 366 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID365  ,Interrupt ID365  Priority/Priority Byte Offset 365 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID364  ,Interrupt ID364   Priority/Priority Byte Offset 364 "
group.long 0x570++0x03
line.long 0x00 "GICD_IPRIORITYR92,Interrupt Priority Register 92"
hexmask.long.byte 0x00 24.--31. 1. " INTID371  ,Interrupt ID371  Priority/Priority Byte Offset 371 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID370  ,Interrupt ID370   Priority/Priority Byte Offset 370 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID369  ,Interrupt ID369  Priority/Priority Byte Offset 369 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID368  ,Interrupt ID368   Priority/Priority Byte Offset 368 "
group.long 0x574++0x03
line.long 0x00 "GICD_IPRIORITYR93,Interrupt Priority Register 93"
hexmask.long.byte 0x00 24.--31. 1. " INTID375  ,Interrupt ID375  Priority/Priority Byte Offset 375 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID374  ,Interrupt ID374   Priority/Priority Byte Offset 374 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID373  ,Interrupt ID373  Priority/Priority Byte Offset 373 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID372  ,Interrupt ID372   Priority/Priority Byte Offset 372 "
group.long 0x578++0x03
line.long 0x00 "GICD_IPRIORITYR94,Interrupt Priority Register 94"
hexmask.long.byte 0x00 24.--31. 1. " INTID379  ,Interrupt ID379  Priority/Priority Byte Offset 379 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID378  ,Interrupt ID378   Priority/Priority Byte Offset 378 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID377  ,Interrupt ID377  Priority/Priority Byte Offset 377 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID376  ,Interrupt ID376   Priority/Priority Byte Offset 376 "
group.long 0x57C++0x03
line.long 0x00 "GICD_IPRIORITYR95,Interrupt Priority Register 95"
hexmask.long.byte 0x00 24.--31. 1. " INTID383  ,Interrupt ID383  Priority/Priority Byte Offset 383 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID382  ,Interrupt ID382   Priority/Priority Byte Offset 382 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID381  ,Interrupt ID381  Priority/Priority Byte Offset 381 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID380  ,Interrupt ID380   Priority/Priority Byte Offset 380 "
else
rgroup.long 0x560++0x03
line.long 0x00 "GICD_IPRIORITYR88,Interrupt Priority Register 88"
rgroup.long 0x564++0x03
line.long 0x00 "GICD_IPRIORITYR89,Interrupt Priority Register 89"
rgroup.long 0x568++0x03
line.long 0x00 "GICD_IPRIORITYR90,Interrupt Priority Register 90"
rgroup.long 0x56C++0x03
line.long 0x00 "GICD_IPRIORITYR91,Interrupt Priority Register 91"
rgroup.long 0x570++0x03
line.long 0x00 "GICD_IPRIORITYR92,Interrupt Priority Register 92"
rgroup.long 0x574++0x03
line.long 0x00 "GICD_IPRIORITYR93,Interrupt Priority Register 93"
rgroup.long 0x578++0x03
line.long 0x00 "GICD_IPRIORITYR94,Interrupt Priority Register 94"
rgroup.long 0x57C++0x03
line.long 0x00 "GICD_IPRIORITYR95,Interrupt Priority Register 95"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0C)
group.long 0x580++0x03
line.long 0x00 "GICD_IPRIORITYR96,Interrupt Priority Register 96"
hexmask.long.byte 0x00 24.--31. 1. " INTID387  ,Interrupt ID387  Priority/Priority Byte Offset 387 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID386  ,Interrupt ID386   Priority/Priority Byte Offset 386 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID385  ,Interrupt ID385  Priority/Priority Byte Offset 385 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID384  ,Interrupt ID384   Priority/Priority Byte Offset 384 "
group.long 0x584++0x03
line.long 0x00 "GICD_IPRIORITYR97,Interrupt Priority Register 97"
hexmask.long.byte 0x00 24.--31. 1. " INTID391  ,Interrupt ID391  Priority/Priority Byte Offset 391 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID390  ,Interrupt ID390   Priority/Priority Byte Offset 390 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID389  ,Interrupt ID389  Priority/Priority Byte Offset 389 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID388  ,Interrupt ID388   Priority/Priority Byte Offset 388 "
group.long 0x588++0x03
line.long 0x00 "GICD_IPRIORITYR98,Interrupt Priority Register 98"
hexmask.long.byte 0x00 24.--31. 1. " INTID395  ,Interrupt ID395  Priority/Priority Byte Offset 395 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID394  ,Interrupt ID394   Priority/Priority Byte Offset 394 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID393  ,Interrupt ID393  Priority/Priority Byte Offset 393 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID392  ,Interrupt ID392   Priority/Priority Byte Offset 392 "
group.long 0x58C++0x03
line.long 0x00 "GICD_IPRIORITYR99,Interrupt Priority Register 99"
hexmask.long.byte 0x00 24.--31. 1. " INTID399  ,Interrupt ID399  Priority/Priority Byte Offset 399 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID398  ,Interrupt ID398   Priority/Priority Byte Offset 398 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID397  ,Interrupt ID397  Priority/Priority Byte Offset 397 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID396  ,Interrupt ID396   Priority/Priority Byte Offset 396 "
group.long 0x590++0x03
line.long 0x00 "GICD_IPRIORITYR100,Interrupt Priority Register 100"
hexmask.long.byte 0x00 24.--31. 1. " INTID403  ,Interrupt ID403  Priority/Priority Byte Offset 403 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID402  ,Interrupt ID402   Priority/Priority Byte Offset 402 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID401  ,Interrupt ID401  Priority/Priority Byte Offset 401 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID400  ,Interrupt ID400   Priority/Priority Byte Offset 400 "
group.long 0x594++0x03
line.long 0x00 "GICD_IPRIORITYR101,Interrupt Priority Register 101"
hexmask.long.byte 0x00 24.--31. 1. " INTID407  ,Interrupt ID407  Priority/Priority Byte Offset 407 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID406  ,Interrupt ID406   Priority/Priority Byte Offset 406 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID405  ,Interrupt ID405  Priority/Priority Byte Offset 405 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID404  ,Interrupt ID404   Priority/Priority Byte Offset 404 "
group.long 0x598++0x03
line.long 0x00 "GICD_IPRIORITYR102,Interrupt Priority Register 102"
hexmask.long.byte 0x00 24.--31. 1. " INTID411  ,Interrupt ID411  Priority/Priority Byte Offset 411 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID410  ,Interrupt ID410   Priority/Priority Byte Offset 410 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID409  ,Interrupt ID409  Priority/Priority Byte Offset 409 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID408  ,Interrupt ID408   Priority/Priority Byte Offset 408 "
group.long 0x59C++0x03
line.long 0x00 "GICD_IPRIORITYR103,Interrupt Priority Register 103"
hexmask.long.byte 0x00 24.--31. 1. " INTID415  ,Interrupt ID415  Priority/Priority Byte Offset 415 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID414  ,Interrupt ID414   Priority/Priority Byte Offset 414 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID413  ,Interrupt ID413  Priority/Priority Byte Offset 413 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID412  ,Interrupt ID412   Priority/Priority Byte Offset 412 "
else
rgroup.long 0x580++0x03
line.long 0x00 "GICD_IPRIORITYR96,Interrupt Priority Register 96"
rgroup.long 0x584++0x03
line.long 0x00 "GICD_IPRIORITYR97,Interrupt Priority Register 97"
rgroup.long 0x588++0x03
line.long 0x00 "GICD_IPRIORITYR98,Interrupt Priority Register 98"
rgroup.long 0x58C++0x03
line.long 0x00 "GICD_IPRIORITYR99,Interrupt Priority Register 99"
rgroup.long 0x590++0x03
line.long 0x00 "GICD_IPRIORITYR100,Interrupt Priority Register 100"
rgroup.long 0x594++0x03
line.long 0x00 "GICD_IPRIORITYR101,Interrupt Priority Register 101"
rgroup.long 0x598++0x03
line.long 0x00 "GICD_IPRIORITYR102,Interrupt Priority Register 102"
rgroup.long 0x59C++0x03
line.long 0x00 "GICD_IPRIORITYR103,Interrupt Priority Register 103"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0D)
group.long 0x5A0++0x03
line.long 0x00 "GICD_IPRIORITYR104,Interrupt Priority Register 104"
hexmask.long.byte 0x00 24.--31. 1. " INTID419  ,Interrupt ID419  Priority/Priority Byte Offset 419 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID418  ,Interrupt ID418   Priority/Priority Byte Offset 418 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID417  ,Interrupt ID417  Priority/Priority Byte Offset 417 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID416  ,Interrupt ID416   Priority/Priority Byte Offset 416 "
group.long 0x5A4++0x03
line.long 0x00 "GICD_IPRIORITYR105,Interrupt Priority Register 105"
hexmask.long.byte 0x00 24.--31. 1. " INTID423  ,Interrupt ID423  Priority/Priority Byte Offset 423 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID422  ,Interrupt ID422   Priority/Priority Byte Offset 422 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID421  ,Interrupt ID421  Priority/Priority Byte Offset 421 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID420  ,Interrupt ID420   Priority/Priority Byte Offset 420 "
group.long 0x5A8++0x03
line.long 0x00 "GICD_IPRIORITYR106,Interrupt Priority Register 106"
hexmask.long.byte 0x00 24.--31. 1. " INTID427  ,Interrupt ID427  Priority/Priority Byte Offset 427 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID426  ,Interrupt ID426   Priority/Priority Byte Offset 426 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID425  ,Interrupt ID425  Priority/Priority Byte Offset 425 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID424  ,Interrupt ID424   Priority/Priority Byte Offset 424 "
group.long 0x5AC++0x03
line.long 0x00 "GICD_IPRIORITYR107,Interrupt Priority Register 107"
hexmask.long.byte 0x00 24.--31. 1. " INTID431  ,Interrupt ID431  Priority/Priority Byte Offset 431 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID430  ,Interrupt ID430   Priority/Priority Byte Offset 430 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID429  ,Interrupt ID429  Priority/Priority Byte Offset 429 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID428  ,Interrupt ID428   Priority/Priority Byte Offset 428 "
group.long 0x5B0++0x03
line.long 0x00 "GICD_IPRIORITYR108,Interrupt Priority Register 108"
hexmask.long.byte 0x00 24.--31. 1. " INTID435  ,Interrupt ID435  Priority/Priority Byte Offset 435 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID434  ,Interrupt ID434   Priority/Priority Byte Offset 434 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID433  ,Interrupt ID433  Priority/Priority Byte Offset 433 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID432  ,Interrupt ID432   Priority/Priority Byte Offset 432 "
group.long 0x5B4++0x03
line.long 0x00 "GICD_IPRIORITYR109,Interrupt Priority Register 109"
hexmask.long.byte 0x00 24.--31. 1. " INTID439  ,Interrupt ID439  Priority/Priority Byte Offset 439 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID438  ,Interrupt ID438   Priority/Priority Byte Offset 438 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID437  ,Interrupt ID437  Priority/Priority Byte Offset 437 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID436  ,Interrupt ID436   Priority/Priority Byte Offset 436 "
group.long 0x5B8++0x03
line.long 0x00 "GICD_IPRIORITYR110,Interrupt Priority Register 110"
hexmask.long.byte 0x00 24.--31. 1. " INTID443  ,Interrupt ID443  Priority/Priority Byte Offset 443 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID442  ,Interrupt ID442   Priority/Priority Byte Offset 442 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID441  ,Interrupt ID441  Priority/Priority Byte Offset 441 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID440  ,Interrupt ID440   Priority/Priority Byte Offset 440 "
group.long 0x5BC++0x03
line.long 0x00 "GICD_IPRIORITYR111,Interrupt Priority Register 111"
hexmask.long.byte 0x00 24.--31. 1. " INTID447  ,Interrupt ID447  Priority/Priority Byte Offset 447 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID446  ,Interrupt ID446   Priority/Priority Byte Offset 446 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID445  ,Interrupt ID445  Priority/Priority Byte Offset 445 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID444  ,Interrupt ID444   Priority/Priority Byte Offset 444 "
else
rgroup.long 0x5A0++0x03
line.long 0x00 "GICD_IPRIORITYR104,Interrupt Priority Register 104"
rgroup.long 0x5A4++0x03
line.long 0x00 "GICD_IPRIORITYR105,Interrupt Priority Register 105"
rgroup.long 0x5A8++0x03
line.long 0x00 "GICD_IPRIORITYR106,Interrupt Priority Register 106"
rgroup.long 0x5AC++0x03
line.long 0x00 "GICD_IPRIORITYR107,Interrupt Priority Register 107"
rgroup.long 0x5B0++0x03
line.long 0x00 "GICD_IPRIORITYR108,Interrupt Priority Register 108"
rgroup.long 0x5B4++0x03
line.long 0x00 "GICD_IPRIORITYR109,Interrupt Priority Register 109"
rgroup.long 0x5B8++0x03
line.long 0x00 "GICD_IPRIORITYR110,Interrupt Priority Register 110"
rgroup.long 0x5BC++0x03
line.long 0x00 "GICD_IPRIORITYR111,Interrupt Priority Register 111"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0E)
group.long 0x5C0++0x03
line.long 0x00 "GICD_IPRIORITYR112,Interrupt Priority Register 112"
hexmask.long.byte 0x00 24.--31. 1. " INTID451  ,Interrupt ID451  Priority/Priority Byte Offset 451 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID450  ,Interrupt ID450   Priority/Priority Byte Offset 450 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID449  ,Interrupt ID449  Priority/Priority Byte Offset 449 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID448  ,Interrupt ID448   Priority/Priority Byte Offset 448 "
group.long 0x5C4++0x03
line.long 0x00 "GICD_IPRIORITYR113,Interrupt Priority Register 113"
hexmask.long.byte 0x00 24.--31. 1. " INTID455  ,Interrupt ID455  Priority/Priority Byte Offset 455 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID454  ,Interrupt ID454   Priority/Priority Byte Offset 454 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID453  ,Interrupt ID453  Priority/Priority Byte Offset 453 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID452  ,Interrupt ID452   Priority/Priority Byte Offset 452 "
group.long 0x5C8++0x03
line.long 0x00 "GICD_IPRIORITYR114,Interrupt Priority Register 114"
hexmask.long.byte 0x00 24.--31. 1. " INTID459  ,Interrupt ID459  Priority/Priority Byte Offset 459 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID458  ,Interrupt ID458   Priority/Priority Byte Offset 458 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID457  ,Interrupt ID457  Priority/Priority Byte Offset 457 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID456  ,Interrupt ID456   Priority/Priority Byte Offset 456 "
group.long 0x5CC++0x03
line.long 0x00 "GICD_IPRIORITYR115,Interrupt Priority Register 115"
hexmask.long.byte 0x00 24.--31. 1. " INTID463  ,Interrupt ID463  Priority/Priority Byte Offset 463 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID462  ,Interrupt ID462   Priority/Priority Byte Offset 462 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID461  ,Interrupt ID461  Priority/Priority Byte Offset 461 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID460  ,Interrupt ID460   Priority/Priority Byte Offset 460 "
group.long 0x5D0++0x03
line.long 0x00 "GICD_IPRIORITYR116,Interrupt Priority Register 116"
hexmask.long.byte 0x00 24.--31. 1. " INTID467  ,Interrupt ID467  Priority/Priority Byte Offset 467 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID466  ,Interrupt ID466   Priority/Priority Byte Offset 466 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID465  ,Interrupt ID465  Priority/Priority Byte Offset 465 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID464  ,Interrupt ID464   Priority/Priority Byte Offset 464 "
group.long 0x5D4++0x03
line.long 0x00 "GICD_IPRIORITYR117,Interrupt Priority Register 117"
hexmask.long.byte 0x00 24.--31. 1. " INTID471  ,Interrupt ID471  Priority/Priority Byte Offset 471 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID470  ,Interrupt ID470   Priority/Priority Byte Offset 470 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID469  ,Interrupt ID469  Priority/Priority Byte Offset 469 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID468  ,Interrupt ID468   Priority/Priority Byte Offset 468 "
group.long 0x5D8++0x03
line.long 0x00 "GICD_IPRIORITYR118,Interrupt Priority Register 118"
hexmask.long.byte 0x00 24.--31. 1. " INTID475  ,Interrupt ID475  Priority/Priority Byte Offset 475 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID474  ,Interrupt ID474   Priority/Priority Byte Offset 474 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID473  ,Interrupt ID473  Priority/Priority Byte Offset 473 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID472  ,Interrupt ID472   Priority/Priority Byte Offset 472 "
group.long 0x5DC++0x03
line.long 0x00 "GICD_IPRIORITYR119,Interrupt Priority Register 119"
hexmask.long.byte 0x00 24.--31. 1. " INTID479  ,Interrupt ID479  Priority/Priority Byte Offset 479 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID478  ,Interrupt ID478   Priority/Priority Byte Offset 478 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID477  ,Interrupt ID477  Priority/Priority Byte Offset 477 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID476  ,Interrupt ID476   Priority/Priority Byte Offset 476 "
else
rgroup.long 0x5C0++0x03
line.long 0x00 "GICD_IPRIORITYR112,Interrupt Priority Register 112"
rgroup.long 0x5C4++0x03
line.long 0x00 "GICD_IPRIORITYR113,Interrupt Priority Register 113"
rgroup.long 0x5C8++0x03
line.long 0x00 "GICD_IPRIORITYR114,Interrupt Priority Register 114"
rgroup.long 0x5CC++0x03
line.long 0x00 "GICD_IPRIORITYR115,Interrupt Priority Register 115"
rgroup.long 0x5D0++0x03
line.long 0x00 "GICD_IPRIORITYR116,Interrupt Priority Register 116"
rgroup.long 0x5D4++0x03
line.long 0x00 "GICD_IPRIORITYR117,Interrupt Priority Register 117"
rgroup.long 0x5D8++0x03
line.long 0x00 "GICD_IPRIORITYR118,Interrupt Priority Register 118"
rgroup.long 0x5DC++0x03
line.long 0x00 "GICD_IPRIORITYR119,Interrupt Priority Register 119"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0F)
group.long 0x5E0++0x03
line.long 0x00 "GICD_IPRIORITYR120,Interrupt Priority Register 120"
hexmask.long.byte 0x00 24.--31. 1. " INTID483  ,Interrupt ID483  Priority/Priority Byte Offset 483 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID482  ,Interrupt ID482   Priority/Priority Byte Offset 482 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID481  ,Interrupt ID481  Priority/Priority Byte Offset 481 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID480  ,Interrupt ID480   Priority/Priority Byte Offset 480 "
group.long 0x5E4++0x03
line.long 0x00 "GICD_IPRIORITYR121,Interrupt Priority Register 121"
hexmask.long.byte 0x00 24.--31. 1. " INTID487  ,Interrupt ID487  Priority/Priority Byte Offset 487 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID486  ,Interrupt ID486   Priority/Priority Byte Offset 486 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID485  ,Interrupt ID485  Priority/Priority Byte Offset 485 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID484  ,Interrupt ID484   Priority/Priority Byte Offset 484 "
group.long 0x5E8++0x03
line.long 0x00 "GICD_IPRIORITYR122,Interrupt Priority Register 122"
hexmask.long.byte 0x00 24.--31. 1. " INTID491  ,Interrupt ID491  Priority/Priority Byte Offset 491 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID490  ,Interrupt ID490   Priority/Priority Byte Offset 490 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID489  ,Interrupt ID489  Priority/Priority Byte Offset 489 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID488  ,Interrupt ID488   Priority/Priority Byte Offset 488 "
group.long 0x5EC++0x03
line.long 0x00 "GICD_IPRIORITYR123,Interrupt Priority Register 123"
hexmask.long.byte 0x00 24.--31. 1. " INTID495  ,Interrupt ID495  Priority/Priority Byte Offset 495 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID494  ,Interrupt ID494   Priority/Priority Byte Offset 494 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID493  ,Interrupt ID493  Priority/Priority Byte Offset 493 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID492  ,Interrupt ID492   Priority/Priority Byte Offset 492 "
group.long 0x5F0++0x03
line.long 0x00 "GICD_IPRIORITYR124,Interrupt Priority Register 124"
hexmask.long.byte 0x00 24.--31. 1. " INTID499  ,Interrupt ID499  Priority/Priority Byte Offset 499 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID498  ,Interrupt ID498   Priority/Priority Byte Offset 498 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID497  ,Interrupt ID497  Priority/Priority Byte Offset 497 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID496  ,Interrupt ID496   Priority/Priority Byte Offset 496 "
group.long 0x5F4++0x03
line.long 0x00 "GICD_IPRIORITYR125,Interrupt Priority Register 125"
hexmask.long.byte 0x00 24.--31. 1. " INTID503  ,Interrupt ID503  Priority/Priority Byte Offset 503 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID502  ,Interrupt ID502   Priority/Priority Byte Offset 502 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID501  ,Interrupt ID501  Priority/Priority Byte Offset 501 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID500  ,Interrupt ID500   Priority/Priority Byte Offset 500 "
group.long 0x5F8++0x03
line.long 0x00 "GICD_IPRIORITYR126,Interrupt Priority Register 126"
hexmask.long.byte 0x00 24.--31. 1. " INTID507  ,Interrupt ID507  Priority/Priority Byte Offset 507 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID506  ,Interrupt ID506   Priority/Priority Byte Offset 506 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID505  ,Interrupt ID505  Priority/Priority Byte Offset 505 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID504  ,Interrupt ID504   Priority/Priority Byte Offset 504 "
group.long 0x5FC++0x03
line.long 0x00 "GICD_IPRIORITYR127,Interrupt Priority Register 127"
hexmask.long.byte 0x00 24.--31. 1. " INTID511  ,Interrupt ID511  Priority/Priority Byte Offset 511 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID510  ,Interrupt ID510   Priority/Priority Byte Offset 510 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID509  ,Interrupt ID509  Priority/Priority Byte Offset 509 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID508  ,Interrupt ID508   Priority/Priority Byte Offset 508 "
else
rgroup.long 0x5E0++0x03
line.long 0x00 "GICD_IPRIORITYR120,Interrupt Priority Register 120"
rgroup.long 0x5E4++0x03
line.long 0x00 "GICD_IPRIORITYR121,Interrupt Priority Register 121"
rgroup.long 0x5E8++0x03
line.long 0x00 "GICD_IPRIORITYR122,Interrupt Priority Register 122"
rgroup.long 0x5EC++0x03
line.long 0x00 "GICD_IPRIORITYR123,Interrupt Priority Register 123"
rgroup.long 0x5F0++0x03
line.long 0x00 "GICD_IPRIORITYR124,Interrupt Priority Register 124"
rgroup.long 0x5F4++0x03
line.long 0x00 "GICD_IPRIORITYR125,Interrupt Priority Register 125"
rgroup.long 0x5F8++0x03
line.long 0x00 "GICD_IPRIORITYR126,Interrupt Priority Register 126"
rgroup.long 0x5FC++0x03
line.long 0x00 "GICD_IPRIORITYR127,Interrupt Priority Register 127"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x10)
group.long 0x600++0x03
line.long 0x00 "GICD_IPRIORITYR128,Interrupt Priority Register 128"
hexmask.long.byte 0x00 24.--31. 1. " INTID515  ,Interrupt ID515  Priority/Priority Byte Offset 515 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID514  ,Interrupt ID514   Priority/Priority Byte Offset 514 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID513  ,Interrupt ID513  Priority/Priority Byte Offset 513 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID512  ,Interrupt ID512   Priority/Priority Byte Offset 512 "
group.long 0x604++0x03
line.long 0x00 "GICD_IPRIORITYR129,Interrupt Priority Register 129"
hexmask.long.byte 0x00 24.--31. 1. " INTID519  ,Interrupt ID519  Priority/Priority Byte Offset 519 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID518  ,Interrupt ID518   Priority/Priority Byte Offset 518 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID517  ,Interrupt ID517  Priority/Priority Byte Offset 517 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID516  ,Interrupt ID516   Priority/Priority Byte Offset 516 "
group.long 0x608++0x03
line.long 0x00 "GICD_IPRIORITYR130,Interrupt Priority Register 130"
hexmask.long.byte 0x00 24.--31. 1. " INTID523  ,Interrupt ID523  Priority/Priority Byte Offset 523 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID522  ,Interrupt ID522   Priority/Priority Byte Offset 522 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID521  ,Interrupt ID521  Priority/Priority Byte Offset 521 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID520  ,Interrupt ID520   Priority/Priority Byte Offset 520 "
group.long 0x60C++0x03
line.long 0x00 "GICD_IPRIORITYR131,Interrupt Priority Register 131"
hexmask.long.byte 0x00 24.--31. 1. " INTID527  ,Interrupt ID527  Priority/Priority Byte Offset 527 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID526  ,Interrupt ID526   Priority/Priority Byte Offset 526 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID525  ,Interrupt ID525  Priority/Priority Byte Offset 525 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID524  ,Interrupt ID524   Priority/Priority Byte Offset 524 "
group.long 0x610++0x03
line.long 0x00 "GICD_IPRIORITYR132,Interrupt Priority Register 132"
hexmask.long.byte 0x00 24.--31. 1. " INTID531  ,Interrupt ID531  Priority/Priority Byte Offset 531 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID530  ,Interrupt ID530   Priority/Priority Byte Offset 530 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID529  ,Interrupt ID529  Priority/Priority Byte Offset 529 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID528  ,Interrupt ID528   Priority/Priority Byte Offset 528 "
group.long 0x614++0x03
line.long 0x00 "GICD_IPRIORITYR133,Interrupt Priority Register 133"
hexmask.long.byte 0x00 24.--31. 1. " INTID535  ,Interrupt ID535  Priority/Priority Byte Offset 535 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID534  ,Interrupt ID534   Priority/Priority Byte Offset 534 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID533  ,Interrupt ID533  Priority/Priority Byte Offset 533 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID532  ,Interrupt ID532   Priority/Priority Byte Offset 532 "
group.long 0x618++0x03
line.long 0x00 "GICD_IPRIORITYR134,Interrupt Priority Register 134"
hexmask.long.byte 0x00 24.--31. 1. " INTID539  ,Interrupt ID539  Priority/Priority Byte Offset 539 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID538  ,Interrupt ID538   Priority/Priority Byte Offset 538 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID537  ,Interrupt ID537  Priority/Priority Byte Offset 537 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID536  ,Interrupt ID536   Priority/Priority Byte Offset 536 "
group.long 0x61C++0x03
line.long 0x00 "GICD_IPRIORITYR135,Interrupt Priority Register 135"
hexmask.long.byte 0x00 24.--31. 1. " INTID543  ,Interrupt ID543  Priority/Priority Byte Offset 543 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID542  ,Interrupt ID542   Priority/Priority Byte Offset 542 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID541  ,Interrupt ID541  Priority/Priority Byte Offset 541 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID540  ,Interrupt ID540   Priority/Priority Byte Offset 540 "
else
rgroup.long 0x600++0x03
line.long 0x00 "GICD_IPRIORITYR128,Interrupt Priority Register 128"
rgroup.long 0x604++0x03
line.long 0x00 "GICD_IPRIORITYR129,Interrupt Priority Register 129"
rgroup.long 0x608++0x03
line.long 0x00 "GICD_IPRIORITYR130,Interrupt Priority Register 130"
rgroup.long 0x60C++0x03
line.long 0x00 "GICD_IPRIORITYR131,Interrupt Priority Register 131"
rgroup.long 0x610++0x03
line.long 0x00 "GICD_IPRIORITYR132,Interrupt Priority Register 132"
rgroup.long 0x614++0x03
line.long 0x00 "GICD_IPRIORITYR133,Interrupt Priority Register 133"
rgroup.long 0x618++0x03
line.long 0x00 "GICD_IPRIORITYR134,Interrupt Priority Register 134"
rgroup.long 0x61C++0x03
line.long 0x00 "GICD_IPRIORITYR135,Interrupt Priority Register 135"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x11)
group.long 0x620++0x03
line.long 0x00 "GICD_IPRIORITYR136,Interrupt Priority Register 136"
hexmask.long.byte 0x00 24.--31. 1. " INTID547  ,Interrupt ID547  Priority/Priority Byte Offset 547 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID546  ,Interrupt ID546   Priority/Priority Byte Offset 546 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID545  ,Interrupt ID545  Priority/Priority Byte Offset 545 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID544  ,Interrupt ID544   Priority/Priority Byte Offset 544 "
group.long 0x624++0x03
line.long 0x00 "GICD_IPRIORITYR137,Interrupt Priority Register 137"
hexmask.long.byte 0x00 24.--31. 1. " INTID551  ,Interrupt ID551  Priority/Priority Byte Offset 551 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID550  ,Interrupt ID550   Priority/Priority Byte Offset 550 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID549  ,Interrupt ID549  Priority/Priority Byte Offset 549 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID548  ,Interrupt ID548   Priority/Priority Byte Offset 548 "
group.long 0x628++0x03
line.long 0x00 "GICD_IPRIORITYR138,Interrupt Priority Register 138"
hexmask.long.byte 0x00 24.--31. 1. " INTID555  ,Interrupt ID555  Priority/Priority Byte Offset 555 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID554  ,Interrupt ID554   Priority/Priority Byte Offset 554 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID553  ,Interrupt ID553  Priority/Priority Byte Offset 553 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID552  ,Interrupt ID552   Priority/Priority Byte Offset 552 "
group.long 0x62C++0x03
line.long 0x00 "GICD_IPRIORITYR139,Interrupt Priority Register 139"
hexmask.long.byte 0x00 24.--31. 1. " INTID559  ,Interrupt ID559  Priority/Priority Byte Offset 559 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID558  ,Interrupt ID558   Priority/Priority Byte Offset 558 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID557  ,Interrupt ID557  Priority/Priority Byte Offset 557 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID556  ,Interrupt ID556   Priority/Priority Byte Offset 556 "
group.long 0x630++0x03
line.long 0x00 "GICD_IPRIORITYR140,Interrupt Priority Register 140"
hexmask.long.byte 0x00 24.--31. 1. " INTID563  ,Interrupt ID563  Priority/Priority Byte Offset 563 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID562  ,Interrupt ID562   Priority/Priority Byte Offset 562 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID561  ,Interrupt ID561  Priority/Priority Byte Offset 561 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID560  ,Interrupt ID560   Priority/Priority Byte Offset 560 "
group.long 0x634++0x03
line.long 0x00 "GICD_IPRIORITYR141,Interrupt Priority Register 141"
hexmask.long.byte 0x00 24.--31. 1. " INTID567  ,Interrupt ID567  Priority/Priority Byte Offset 567 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID566  ,Interrupt ID566   Priority/Priority Byte Offset 566 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID565  ,Interrupt ID565  Priority/Priority Byte Offset 565 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID564  ,Interrupt ID564   Priority/Priority Byte Offset 564 "
group.long 0x638++0x03
line.long 0x00 "GICD_IPRIORITYR142,Interrupt Priority Register 142"
hexmask.long.byte 0x00 24.--31. 1. " INTID571  ,Interrupt ID571  Priority/Priority Byte Offset 571 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID570  ,Interrupt ID570   Priority/Priority Byte Offset 570 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID569  ,Interrupt ID569  Priority/Priority Byte Offset 569 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID568  ,Interrupt ID568   Priority/Priority Byte Offset 568 "
group.long 0x63C++0x03
line.long 0x00 "GICD_IPRIORITYR143,Interrupt Priority Register 143"
hexmask.long.byte 0x00 24.--31. 1. " INTID575  ,Interrupt ID575  Priority/Priority Byte Offset 575 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID574  ,Interrupt ID574   Priority/Priority Byte Offset 574 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID573  ,Interrupt ID573  Priority/Priority Byte Offset 573 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID572  ,Interrupt ID572   Priority/Priority Byte Offset 572 "
else
rgroup.long 0x620++0x03
line.long 0x00 "GICD_IPRIORITYR136,Interrupt Priority Register 136"
rgroup.long 0x624++0x03
line.long 0x00 "GICD_IPRIORITYR137,Interrupt Priority Register 137"
rgroup.long 0x628++0x03
line.long 0x00 "GICD_IPRIORITYR138,Interrupt Priority Register 138"
rgroup.long 0x62C++0x03
line.long 0x00 "GICD_IPRIORITYR139,Interrupt Priority Register 139"
rgroup.long 0x630++0x03
line.long 0x00 "GICD_IPRIORITYR140,Interrupt Priority Register 140"
rgroup.long 0x634++0x03
line.long 0x00 "GICD_IPRIORITYR141,Interrupt Priority Register 141"
rgroup.long 0x638++0x03
line.long 0x00 "GICD_IPRIORITYR142,Interrupt Priority Register 142"
rgroup.long 0x63C++0x03
line.long 0x00 "GICD_IPRIORITYR143,Interrupt Priority Register 143"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x12)
group.long 0x640++0x03
line.long 0x00 "GICD_IPRIORITYR144,Interrupt Priority Register 144"
hexmask.long.byte 0x00 24.--31. 1. " INTID579  ,Interrupt ID579  Priority/Priority Byte Offset 579 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID578  ,Interrupt ID578   Priority/Priority Byte Offset 578 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID577  ,Interrupt ID577  Priority/Priority Byte Offset 577 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID576  ,Interrupt ID576   Priority/Priority Byte Offset 576 "
group.long 0x644++0x03
line.long 0x00 "GICD_IPRIORITYR145,Interrupt Priority Register 145"
hexmask.long.byte 0x00 24.--31. 1. " INTID583  ,Interrupt ID583  Priority/Priority Byte Offset 583 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID582  ,Interrupt ID582   Priority/Priority Byte Offset 582 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID581  ,Interrupt ID581  Priority/Priority Byte Offset 581 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID580  ,Interrupt ID580   Priority/Priority Byte Offset 580 "
group.long 0x648++0x03
line.long 0x00 "GICD_IPRIORITYR146,Interrupt Priority Register 146"
hexmask.long.byte 0x00 24.--31. 1. " INTID587  ,Interrupt ID587  Priority/Priority Byte Offset 587 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID586  ,Interrupt ID586   Priority/Priority Byte Offset 586 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID585  ,Interrupt ID585  Priority/Priority Byte Offset 585 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID584  ,Interrupt ID584   Priority/Priority Byte Offset 584 "
group.long 0x64C++0x03
line.long 0x00 "GICD_IPRIORITYR147,Interrupt Priority Register 147"
hexmask.long.byte 0x00 24.--31. 1. " INTID591  ,Interrupt ID591  Priority/Priority Byte Offset 591 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID590  ,Interrupt ID590   Priority/Priority Byte Offset 590 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID589  ,Interrupt ID589  Priority/Priority Byte Offset 589 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID588  ,Interrupt ID588   Priority/Priority Byte Offset 588 "
group.long 0x650++0x03
line.long 0x00 "GICD_IPRIORITYR148,Interrupt Priority Register 148"
hexmask.long.byte 0x00 24.--31. 1. " INTID595  ,Interrupt ID595  Priority/Priority Byte Offset 595 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID594  ,Interrupt ID594   Priority/Priority Byte Offset 594 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID593  ,Interrupt ID593  Priority/Priority Byte Offset 593 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID592  ,Interrupt ID592   Priority/Priority Byte Offset 592 "
group.long 0x654++0x03
line.long 0x00 "GICD_IPRIORITYR149,Interrupt Priority Register 149"
hexmask.long.byte 0x00 24.--31. 1. " INTID599  ,Interrupt ID599  Priority/Priority Byte Offset 599 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID598  ,Interrupt ID598   Priority/Priority Byte Offset 598 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID597  ,Interrupt ID597  Priority/Priority Byte Offset 597 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID596  ,Interrupt ID596   Priority/Priority Byte Offset 596 "
group.long 0x658++0x03
line.long 0x00 "GICD_IPRIORITYR150,Interrupt Priority Register 150"
hexmask.long.byte 0x00 24.--31. 1. " INTID603  ,Interrupt ID603  Priority/Priority Byte Offset 603 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID602  ,Interrupt ID602   Priority/Priority Byte Offset 602 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID601  ,Interrupt ID601  Priority/Priority Byte Offset 601 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID600  ,Interrupt ID600   Priority/Priority Byte Offset 600 "
group.long 0x65C++0x03
line.long 0x00 "GICD_IPRIORITYR151,Interrupt Priority Register 151"
hexmask.long.byte 0x00 24.--31. 1. " INTID607  ,Interrupt ID607  Priority/Priority Byte Offset 607 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID606  ,Interrupt ID606   Priority/Priority Byte Offset 606 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID605  ,Interrupt ID605  Priority/Priority Byte Offset 605 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID604  ,Interrupt ID604   Priority/Priority Byte Offset 604 "
else
rgroup.long 0x640++0x03
line.long 0x00 "GICD_IPRIORITYR144,Interrupt Priority Register 144"
rgroup.long 0x644++0x03
line.long 0x00 "GICD_IPRIORITYR145,Interrupt Priority Register 145"
rgroup.long 0x648++0x03
line.long 0x00 "GICD_IPRIORITYR146,Interrupt Priority Register 146"
rgroup.long 0x64C++0x03
line.long 0x00 "GICD_IPRIORITYR147,Interrupt Priority Register 147"
rgroup.long 0x650++0x03
line.long 0x00 "GICD_IPRIORITYR148,Interrupt Priority Register 148"
rgroup.long 0x654++0x03
line.long 0x00 "GICD_IPRIORITYR149,Interrupt Priority Register 149"
rgroup.long 0x658++0x03
line.long 0x00 "GICD_IPRIORITYR150,Interrupt Priority Register 150"
rgroup.long 0x65C++0x03
line.long 0x00 "GICD_IPRIORITYR151,Interrupt Priority Register 151"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x13)
group.long 0x660++0x03
line.long 0x00 "GICD_IPRIORITYR152,Interrupt Priority Register 152"
hexmask.long.byte 0x00 24.--31. 1. " INTID611  ,Interrupt ID611  Priority/Priority Byte Offset 611 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID610  ,Interrupt ID610   Priority/Priority Byte Offset 610 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID609  ,Interrupt ID609  Priority/Priority Byte Offset 609 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID608  ,Interrupt ID608   Priority/Priority Byte Offset 608 "
group.long 0x664++0x03
line.long 0x00 "GICD_IPRIORITYR153,Interrupt Priority Register 153"
hexmask.long.byte 0x00 24.--31. 1. " INTID615  ,Interrupt ID615  Priority/Priority Byte Offset 615 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID614  ,Interrupt ID614   Priority/Priority Byte Offset 614 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID613  ,Interrupt ID613  Priority/Priority Byte Offset 613 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID612  ,Interrupt ID612   Priority/Priority Byte Offset 612 "
group.long 0x668++0x03
line.long 0x00 "GICD_IPRIORITYR154,Interrupt Priority Register 154"
hexmask.long.byte 0x00 24.--31. 1. " INTID619  ,Interrupt ID619  Priority/Priority Byte Offset 619 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID618  ,Interrupt ID618   Priority/Priority Byte Offset 618 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID617  ,Interrupt ID617  Priority/Priority Byte Offset 617 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID616  ,Interrupt ID616   Priority/Priority Byte Offset 616 "
group.long 0x66C++0x03
line.long 0x00 "GICD_IPRIORITYR155,Interrupt Priority Register 155"
hexmask.long.byte 0x00 24.--31. 1. " INTID623  ,Interrupt ID623  Priority/Priority Byte Offset 623 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID622  ,Interrupt ID622   Priority/Priority Byte Offset 622 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID621  ,Interrupt ID621  Priority/Priority Byte Offset 621 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID620  ,Interrupt ID620   Priority/Priority Byte Offset 620 "
group.long 0x670++0x03
line.long 0x00 "GICD_IPRIORITYR156,Interrupt Priority Register 156"
hexmask.long.byte 0x00 24.--31. 1. " INTID627  ,Interrupt ID627  Priority/Priority Byte Offset 627 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID626  ,Interrupt ID626   Priority/Priority Byte Offset 626 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID625  ,Interrupt ID625  Priority/Priority Byte Offset 625 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID624  ,Interrupt ID624   Priority/Priority Byte Offset 624 "
group.long 0x674++0x03
line.long 0x00 "GICD_IPRIORITYR157,Interrupt Priority Register 157"
hexmask.long.byte 0x00 24.--31. 1. " INTID631  ,Interrupt ID631  Priority/Priority Byte Offset 631 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID630  ,Interrupt ID630   Priority/Priority Byte Offset 630 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID629  ,Interrupt ID629  Priority/Priority Byte Offset 629 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID628  ,Interrupt ID628   Priority/Priority Byte Offset 628 "
group.long 0x678++0x03
line.long 0x00 "GICD_IPRIORITYR158,Interrupt Priority Register 158"
hexmask.long.byte 0x00 24.--31. 1. " INTID635  ,Interrupt ID635  Priority/Priority Byte Offset 635 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID634  ,Interrupt ID634   Priority/Priority Byte Offset 634 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID633  ,Interrupt ID633  Priority/Priority Byte Offset 633 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID632  ,Interrupt ID632   Priority/Priority Byte Offset 632 "
group.long 0x67C++0x03
line.long 0x00 "GICD_IPRIORITYR159,Interrupt Priority Register 159"
hexmask.long.byte 0x00 24.--31. 1. " INTID639  ,Interrupt ID639  Priority/Priority Byte Offset 639 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID638  ,Interrupt ID638   Priority/Priority Byte Offset 638 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID637  ,Interrupt ID637  Priority/Priority Byte Offset 637 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID636  ,Interrupt ID636   Priority/Priority Byte Offset 636 "
else
rgroup.long 0x660++0x03
line.long 0x00 "GICD_IPRIORITYR152,Interrupt Priority Register 152"
rgroup.long 0x664++0x03
line.long 0x00 "GICD_IPRIORITYR153,Interrupt Priority Register 153"
rgroup.long 0x668++0x03
line.long 0x00 "GICD_IPRIORITYR154,Interrupt Priority Register 154"
rgroup.long 0x66C++0x03
line.long 0x00 "GICD_IPRIORITYR155,Interrupt Priority Register 155"
rgroup.long 0x670++0x03
line.long 0x00 "GICD_IPRIORITYR156,Interrupt Priority Register 156"
rgroup.long 0x674++0x03
line.long 0x00 "GICD_IPRIORITYR157,Interrupt Priority Register 157"
rgroup.long 0x678++0x03
line.long 0x00 "GICD_IPRIORITYR158,Interrupt Priority Register 158"
rgroup.long 0x67C++0x03
line.long 0x00 "GICD_IPRIORITYR159,Interrupt Priority Register 159"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x14)
group.long 0x680++0x03
line.long 0x00 "GICD_IPRIORITYR160,Interrupt Priority Register 160"
hexmask.long.byte 0x00 24.--31. 1. " INTID643  ,Interrupt ID643  Priority/Priority Byte Offset 643 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID642  ,Interrupt ID642   Priority/Priority Byte Offset 642 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID641  ,Interrupt ID641  Priority/Priority Byte Offset 641 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID640  ,Interrupt ID640   Priority/Priority Byte Offset 640 "
group.long 0x684++0x03
line.long 0x00 "GICD_IPRIORITYR161,Interrupt Priority Register 161"
hexmask.long.byte 0x00 24.--31. 1. " INTID647  ,Interrupt ID647  Priority/Priority Byte Offset 647 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID646  ,Interrupt ID646   Priority/Priority Byte Offset 646 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID645  ,Interrupt ID645  Priority/Priority Byte Offset 645 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID644  ,Interrupt ID644   Priority/Priority Byte Offset 644 "
group.long 0x688++0x03
line.long 0x00 "GICD_IPRIORITYR162,Interrupt Priority Register 162"
hexmask.long.byte 0x00 24.--31. 1. " INTID651  ,Interrupt ID651  Priority/Priority Byte Offset 651 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID650  ,Interrupt ID650   Priority/Priority Byte Offset 650 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID649  ,Interrupt ID649  Priority/Priority Byte Offset 649 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID648  ,Interrupt ID648   Priority/Priority Byte Offset 648 "
group.long 0x68C++0x03
line.long 0x00 "GICD_IPRIORITYR163,Interrupt Priority Register 163"
hexmask.long.byte 0x00 24.--31. 1. " INTID655  ,Interrupt ID655  Priority/Priority Byte Offset 655 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID654  ,Interrupt ID654   Priority/Priority Byte Offset 654 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID653  ,Interrupt ID653  Priority/Priority Byte Offset 653 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID652  ,Interrupt ID652   Priority/Priority Byte Offset 652 "
group.long 0x690++0x03
line.long 0x00 "GICD_IPRIORITYR164,Interrupt Priority Register 164"
hexmask.long.byte 0x00 24.--31. 1. " INTID659  ,Interrupt ID659  Priority/Priority Byte Offset 659 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID658  ,Interrupt ID658   Priority/Priority Byte Offset 658 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID657  ,Interrupt ID657  Priority/Priority Byte Offset 657 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID656  ,Interrupt ID656   Priority/Priority Byte Offset 656 "
group.long 0x694++0x03
line.long 0x00 "GICD_IPRIORITYR165,Interrupt Priority Register 165"
hexmask.long.byte 0x00 24.--31. 1. " INTID663  ,Interrupt ID663  Priority/Priority Byte Offset 663 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID662  ,Interrupt ID662   Priority/Priority Byte Offset 662 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID661  ,Interrupt ID661  Priority/Priority Byte Offset 661 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID660  ,Interrupt ID660   Priority/Priority Byte Offset 660 "
group.long 0x698++0x03
line.long 0x00 "GICD_IPRIORITYR166,Interrupt Priority Register 166"
hexmask.long.byte 0x00 24.--31. 1. " INTID667  ,Interrupt ID667  Priority/Priority Byte Offset 667 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID666  ,Interrupt ID666   Priority/Priority Byte Offset 666 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID665  ,Interrupt ID665  Priority/Priority Byte Offset 665 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID664  ,Interrupt ID664   Priority/Priority Byte Offset 664 "
group.long 0x69C++0x03
line.long 0x00 "GICD_IPRIORITYR167,Interrupt Priority Register 167"
hexmask.long.byte 0x00 24.--31. 1. " INTID671  ,Interrupt ID671  Priority/Priority Byte Offset 671 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID670  ,Interrupt ID670   Priority/Priority Byte Offset 670 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID669  ,Interrupt ID669  Priority/Priority Byte Offset 669 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID668  ,Interrupt ID668   Priority/Priority Byte Offset 668 "
else
rgroup.long 0x680++0x03
line.long 0x00 "GICD_IPRIORITYR160,Interrupt Priority Register 160"
rgroup.long 0x684++0x03
line.long 0x00 "GICD_IPRIORITYR161,Interrupt Priority Register 161"
rgroup.long 0x688++0x03
line.long 0x00 "GICD_IPRIORITYR162,Interrupt Priority Register 162"
rgroup.long 0x68C++0x03
line.long 0x00 "GICD_IPRIORITYR163,Interrupt Priority Register 163"
rgroup.long 0x690++0x03
line.long 0x00 "GICD_IPRIORITYR164,Interrupt Priority Register 164"
rgroup.long 0x694++0x03
line.long 0x00 "GICD_IPRIORITYR165,Interrupt Priority Register 165"
rgroup.long 0x698++0x03
line.long 0x00 "GICD_IPRIORITYR166,Interrupt Priority Register 166"
rgroup.long 0x69C++0x03
line.long 0x00 "GICD_IPRIORITYR167,Interrupt Priority Register 167"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x15)
group.long 0x6A0++0x03
line.long 0x00 "GICD_IPRIORITYR168,Interrupt Priority Register 168"
hexmask.long.byte 0x00 24.--31. 1. " INTID675  ,Interrupt ID675  Priority/Priority Byte Offset 675 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID674  ,Interrupt ID674   Priority/Priority Byte Offset 674 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID673  ,Interrupt ID673  Priority/Priority Byte Offset 673 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID672  ,Interrupt ID672   Priority/Priority Byte Offset 672 "
group.long 0x6A4++0x03
line.long 0x00 "GICD_IPRIORITYR169,Interrupt Priority Register 169"
hexmask.long.byte 0x00 24.--31. 1. " INTID679  ,Interrupt ID679  Priority/Priority Byte Offset 679 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID678  ,Interrupt ID678   Priority/Priority Byte Offset 678 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID677  ,Interrupt ID677  Priority/Priority Byte Offset 677 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID676  ,Interrupt ID676   Priority/Priority Byte Offset 676 "
group.long 0x6A8++0x03
line.long 0x00 "GICD_IPRIORITYR170,Interrupt Priority Register 170"
hexmask.long.byte 0x00 24.--31. 1. " INTID683  ,Interrupt ID683  Priority/Priority Byte Offset 683 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID682  ,Interrupt ID682   Priority/Priority Byte Offset 682 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID681  ,Interrupt ID681  Priority/Priority Byte Offset 681 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID680  ,Interrupt ID680   Priority/Priority Byte Offset 680 "
group.long 0x6AC++0x03
line.long 0x00 "GICD_IPRIORITYR171,Interrupt Priority Register 171"
hexmask.long.byte 0x00 24.--31. 1. " INTID687  ,Interrupt ID687  Priority/Priority Byte Offset 687 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID686  ,Interrupt ID686   Priority/Priority Byte Offset 686 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID685  ,Interrupt ID685  Priority/Priority Byte Offset 685 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID684  ,Interrupt ID684   Priority/Priority Byte Offset 684 "
group.long 0x6B0++0x03
line.long 0x00 "GICD_IPRIORITYR172,Interrupt Priority Register 172"
hexmask.long.byte 0x00 24.--31. 1. " INTID691  ,Interrupt ID691  Priority/Priority Byte Offset 691 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID690  ,Interrupt ID690   Priority/Priority Byte Offset 690 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID689  ,Interrupt ID689  Priority/Priority Byte Offset 689 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID688  ,Interrupt ID688   Priority/Priority Byte Offset 688 "
group.long 0x6B4++0x03
line.long 0x00 "GICD_IPRIORITYR173,Interrupt Priority Register 173"
hexmask.long.byte 0x00 24.--31. 1. " INTID695  ,Interrupt ID695  Priority/Priority Byte Offset 695 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID694  ,Interrupt ID694   Priority/Priority Byte Offset 694 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID693  ,Interrupt ID693  Priority/Priority Byte Offset 693 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID692  ,Interrupt ID692   Priority/Priority Byte Offset 692 "
group.long 0x6B8++0x03
line.long 0x00 "GICD_IPRIORITYR174,Interrupt Priority Register 174"
hexmask.long.byte 0x00 24.--31. 1. " INTID699  ,Interrupt ID699  Priority/Priority Byte Offset 699 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID698  ,Interrupt ID698   Priority/Priority Byte Offset 698 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID697  ,Interrupt ID697  Priority/Priority Byte Offset 697 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID696  ,Interrupt ID696   Priority/Priority Byte Offset 696 "
group.long 0x6BC++0x03
line.long 0x00 "GICD_IPRIORITYR175,Interrupt Priority Register 175"
hexmask.long.byte 0x00 24.--31. 1. " INTID703  ,Interrupt ID703  Priority/Priority Byte Offset 703 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID702  ,Interrupt ID702   Priority/Priority Byte Offset 702 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID701  ,Interrupt ID701  Priority/Priority Byte Offset 701 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID700  ,Interrupt ID700   Priority/Priority Byte Offset 700 "
else
rgroup.long 0x6A0++0x03
line.long 0x00 "GICD_IPRIORITYR168,Interrupt Priority Register 168"
rgroup.long 0x6A4++0x03
line.long 0x00 "GICD_IPRIORITYR169,Interrupt Priority Register 169"
rgroup.long 0x6A8++0x03
line.long 0x00 "GICD_IPRIORITYR170,Interrupt Priority Register 170"
rgroup.long 0x6AC++0x03
line.long 0x00 "GICD_IPRIORITYR171,Interrupt Priority Register 171"
rgroup.long 0x6B0++0x03
line.long 0x00 "GICD_IPRIORITYR172,Interrupt Priority Register 172"
rgroup.long 0x6B4++0x03
line.long 0x00 "GICD_IPRIORITYR173,Interrupt Priority Register 173"
rgroup.long 0x6B8++0x03
line.long 0x00 "GICD_IPRIORITYR174,Interrupt Priority Register 174"
rgroup.long 0x6BC++0x03
line.long 0x00 "GICD_IPRIORITYR175,Interrupt Priority Register 175"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x16)
group.long 0x6C0++0x03
line.long 0x00 "GICD_IPRIORITYR176,Interrupt Priority Register 176"
hexmask.long.byte 0x00 24.--31. 1. " INTID707  ,Interrupt ID707  Priority/Priority Byte Offset 707 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID706  ,Interrupt ID706   Priority/Priority Byte Offset 706 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID705  ,Interrupt ID705  Priority/Priority Byte Offset 705 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID704  ,Interrupt ID704   Priority/Priority Byte Offset 704 "
group.long 0x6C4++0x03
line.long 0x00 "GICD_IPRIORITYR177,Interrupt Priority Register 177"
hexmask.long.byte 0x00 24.--31. 1. " INTID711  ,Interrupt ID711  Priority/Priority Byte Offset 711 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID710  ,Interrupt ID710   Priority/Priority Byte Offset 710 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID709  ,Interrupt ID709  Priority/Priority Byte Offset 709 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID708  ,Interrupt ID708   Priority/Priority Byte Offset 708 "
group.long 0x6C8++0x03
line.long 0x00 "GICD_IPRIORITYR178,Interrupt Priority Register 178"
hexmask.long.byte 0x00 24.--31. 1. " INTID715  ,Interrupt ID715  Priority/Priority Byte Offset 715 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID714  ,Interrupt ID714   Priority/Priority Byte Offset 714 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID713  ,Interrupt ID713  Priority/Priority Byte Offset 713 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID712  ,Interrupt ID712   Priority/Priority Byte Offset 712 "
group.long 0x6CC++0x03
line.long 0x00 "GICD_IPRIORITYR179,Interrupt Priority Register 179"
hexmask.long.byte 0x00 24.--31. 1. " INTID719  ,Interrupt ID719  Priority/Priority Byte Offset 719 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID718  ,Interrupt ID718   Priority/Priority Byte Offset 718 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID717  ,Interrupt ID717  Priority/Priority Byte Offset 717 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID716  ,Interrupt ID716   Priority/Priority Byte Offset 716 "
group.long 0x6D0++0x03
line.long 0x00 "GICD_IPRIORITYR180,Interrupt Priority Register 180"
hexmask.long.byte 0x00 24.--31. 1. " INTID723  ,Interrupt ID723  Priority/Priority Byte Offset 723 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID722  ,Interrupt ID722   Priority/Priority Byte Offset 722 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID721  ,Interrupt ID721  Priority/Priority Byte Offset 721 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID720  ,Interrupt ID720   Priority/Priority Byte Offset 720 "
group.long 0x6D4++0x03
line.long 0x00 "GICD_IPRIORITYR181,Interrupt Priority Register 181"
hexmask.long.byte 0x00 24.--31. 1. " INTID727  ,Interrupt ID727  Priority/Priority Byte Offset 727 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID726  ,Interrupt ID726   Priority/Priority Byte Offset 726 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID725  ,Interrupt ID725  Priority/Priority Byte Offset 725 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID724  ,Interrupt ID724   Priority/Priority Byte Offset 724 "
group.long 0x6D8++0x03
line.long 0x00 "GICD_IPRIORITYR182,Interrupt Priority Register 182"
hexmask.long.byte 0x00 24.--31. 1. " INTID731  ,Interrupt ID731  Priority/Priority Byte Offset 731 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID730  ,Interrupt ID730   Priority/Priority Byte Offset 730 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID729  ,Interrupt ID729  Priority/Priority Byte Offset 729 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID728  ,Interrupt ID728   Priority/Priority Byte Offset 728 "
group.long 0x6DC++0x03
line.long 0x00 "GICD_IPRIORITYR183,Interrupt Priority Register 183"
hexmask.long.byte 0x00 24.--31. 1. " INTID735  ,Interrupt ID735  Priority/Priority Byte Offset 735 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID734  ,Interrupt ID734   Priority/Priority Byte Offset 734 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID733  ,Interrupt ID733  Priority/Priority Byte Offset 733 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID732  ,Interrupt ID732   Priority/Priority Byte Offset 732 "
else
rgroup.long 0x6C0++0x03
line.long 0x00 "GICD_IPRIORITYR176,Interrupt Priority Register 176"
rgroup.long 0x6C4++0x03
line.long 0x00 "GICD_IPRIORITYR177,Interrupt Priority Register 177"
rgroup.long 0x6C8++0x03
line.long 0x00 "GICD_IPRIORITYR178,Interrupt Priority Register 178"
rgroup.long 0x6CC++0x03
line.long 0x00 "GICD_IPRIORITYR179,Interrupt Priority Register 179"
rgroup.long 0x6D0++0x03
line.long 0x00 "GICD_IPRIORITYR180,Interrupt Priority Register 180"
rgroup.long 0x6D4++0x03
line.long 0x00 "GICD_IPRIORITYR181,Interrupt Priority Register 181"
rgroup.long 0x6D8++0x03
line.long 0x00 "GICD_IPRIORITYR182,Interrupt Priority Register 182"
rgroup.long 0x6DC++0x03
line.long 0x00 "GICD_IPRIORITYR183,Interrupt Priority Register 183"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x17)
group.long 0x6E0++0x03
line.long 0x00 "GICD_IPRIORITYR184,Interrupt Priority Register 184"
hexmask.long.byte 0x00 24.--31. 1. " INTID739  ,Interrupt ID739  Priority/Priority Byte Offset 739 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID738  ,Interrupt ID738   Priority/Priority Byte Offset 738 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID737  ,Interrupt ID737  Priority/Priority Byte Offset 737 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID736  ,Interrupt ID736   Priority/Priority Byte Offset 736 "
group.long 0x6E4++0x03
line.long 0x00 "GICD_IPRIORITYR185,Interrupt Priority Register 185"
hexmask.long.byte 0x00 24.--31. 1. " INTID743  ,Interrupt ID743  Priority/Priority Byte Offset 743 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID742  ,Interrupt ID742   Priority/Priority Byte Offset 742 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID741  ,Interrupt ID741  Priority/Priority Byte Offset 741 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID740  ,Interrupt ID740   Priority/Priority Byte Offset 740 "
group.long 0x6E8++0x03
line.long 0x00 "GICD_IPRIORITYR186,Interrupt Priority Register 186"
hexmask.long.byte 0x00 24.--31. 1. " INTID747  ,Interrupt ID747  Priority/Priority Byte Offset 747 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID746  ,Interrupt ID746   Priority/Priority Byte Offset 746 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID745  ,Interrupt ID745  Priority/Priority Byte Offset 745 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID744  ,Interrupt ID744   Priority/Priority Byte Offset 744 "
group.long 0x6EC++0x03
line.long 0x00 "GICD_IPRIORITYR187,Interrupt Priority Register 187"
hexmask.long.byte 0x00 24.--31. 1. " INTID751  ,Interrupt ID751  Priority/Priority Byte Offset 751 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID750  ,Interrupt ID750   Priority/Priority Byte Offset 750 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID749  ,Interrupt ID749  Priority/Priority Byte Offset 749 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID748  ,Interrupt ID748   Priority/Priority Byte Offset 748 "
group.long 0x6F0++0x03
line.long 0x00 "GICD_IPRIORITYR188,Interrupt Priority Register 188"
hexmask.long.byte 0x00 24.--31. 1. " INTID755  ,Interrupt ID755  Priority/Priority Byte Offset 755 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID754  ,Interrupt ID754   Priority/Priority Byte Offset 754 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID753  ,Interrupt ID753  Priority/Priority Byte Offset 753 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID752  ,Interrupt ID752   Priority/Priority Byte Offset 752 "
group.long 0x6F4++0x03
line.long 0x00 "GICD_IPRIORITYR189,Interrupt Priority Register 189"
hexmask.long.byte 0x00 24.--31. 1. " INTID759  ,Interrupt ID759  Priority/Priority Byte Offset 759 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID758  ,Interrupt ID758   Priority/Priority Byte Offset 758 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID757  ,Interrupt ID757  Priority/Priority Byte Offset 757 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID756  ,Interrupt ID756   Priority/Priority Byte Offset 756 "
group.long 0x6F8++0x03
line.long 0x00 "GICD_IPRIORITYR190,Interrupt Priority Register 190"
hexmask.long.byte 0x00 24.--31. 1. " INTID763  ,Interrupt ID763  Priority/Priority Byte Offset 763 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID762  ,Interrupt ID762   Priority/Priority Byte Offset 762 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID761  ,Interrupt ID761  Priority/Priority Byte Offset 761 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID760  ,Interrupt ID760   Priority/Priority Byte Offset 760 "
group.long 0x6FC++0x03
line.long 0x00 "GICD_IPRIORITYR191,Interrupt Priority Register 191"
hexmask.long.byte 0x00 24.--31. 1. " INTID767  ,Interrupt ID767  Priority/Priority Byte Offset 767 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID766  ,Interrupt ID766   Priority/Priority Byte Offset 766 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID765  ,Interrupt ID765  Priority/Priority Byte Offset 765 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID764  ,Interrupt ID764   Priority/Priority Byte Offset 764 "
else
rgroup.long 0x6E0++0x03
line.long 0x00 "GICD_IPRIORITYR184,Interrupt Priority Register 184"
rgroup.long 0x6E4++0x03
line.long 0x00 "GICD_IPRIORITYR185,Interrupt Priority Register 185"
rgroup.long 0x6E8++0x03
line.long 0x00 "GICD_IPRIORITYR186,Interrupt Priority Register 186"
rgroup.long 0x6EC++0x03
line.long 0x00 "GICD_IPRIORITYR187,Interrupt Priority Register 187"
rgroup.long 0x6F0++0x03
line.long 0x00 "GICD_IPRIORITYR188,Interrupt Priority Register 188"
rgroup.long 0x6F4++0x03
line.long 0x00 "GICD_IPRIORITYR189,Interrupt Priority Register 189"
rgroup.long 0x6F8++0x03
line.long 0x00 "GICD_IPRIORITYR190,Interrupt Priority Register 190"
rgroup.long 0x6FC++0x03
line.long 0x00 "GICD_IPRIORITYR191,Interrupt Priority Register 191"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x18)
group.long 0x700++0x03
line.long 0x00 "GICD_IPRIORITYR192,Interrupt Priority Register 192"
hexmask.long.byte 0x00 24.--31. 1. " INTID771  ,Interrupt ID771  Priority/Priority Byte Offset 771 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID770  ,Interrupt ID770   Priority/Priority Byte Offset 770 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID769  ,Interrupt ID769  Priority/Priority Byte Offset 769 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID768  ,Interrupt ID768   Priority/Priority Byte Offset 768 "
group.long 0x704++0x03
line.long 0x00 "GICD_IPRIORITYR193,Interrupt Priority Register 193"
hexmask.long.byte 0x00 24.--31. 1. " INTID775  ,Interrupt ID775  Priority/Priority Byte Offset 775 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID774  ,Interrupt ID774   Priority/Priority Byte Offset 774 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID773  ,Interrupt ID773  Priority/Priority Byte Offset 773 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID772  ,Interrupt ID772   Priority/Priority Byte Offset 772 "
group.long 0x708++0x03
line.long 0x00 "GICD_IPRIORITYR194,Interrupt Priority Register 194"
hexmask.long.byte 0x00 24.--31. 1. " INTID779  ,Interrupt ID779  Priority/Priority Byte Offset 779 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID778  ,Interrupt ID778   Priority/Priority Byte Offset 778 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID777  ,Interrupt ID777  Priority/Priority Byte Offset 777 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID776  ,Interrupt ID776   Priority/Priority Byte Offset 776 "
group.long 0x70C++0x03
line.long 0x00 "GICD_IPRIORITYR195,Interrupt Priority Register 195"
hexmask.long.byte 0x00 24.--31. 1. " INTID783  ,Interrupt ID783  Priority/Priority Byte Offset 783 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID782  ,Interrupt ID782   Priority/Priority Byte Offset 782 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID781  ,Interrupt ID781  Priority/Priority Byte Offset 781 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID780  ,Interrupt ID780   Priority/Priority Byte Offset 780 "
group.long 0x710++0x03
line.long 0x00 "GICD_IPRIORITYR196,Interrupt Priority Register 196"
hexmask.long.byte 0x00 24.--31. 1. " INTID787  ,Interrupt ID787  Priority/Priority Byte Offset 787 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID786  ,Interrupt ID786   Priority/Priority Byte Offset 786 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID785  ,Interrupt ID785  Priority/Priority Byte Offset 785 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID784  ,Interrupt ID784   Priority/Priority Byte Offset 784 "
group.long 0x714++0x03
line.long 0x00 "GICD_IPRIORITYR197,Interrupt Priority Register 197"
hexmask.long.byte 0x00 24.--31. 1. " INTID791  ,Interrupt ID791  Priority/Priority Byte Offset 791 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID790  ,Interrupt ID790   Priority/Priority Byte Offset 790 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID789  ,Interrupt ID789  Priority/Priority Byte Offset 789 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID788  ,Interrupt ID788   Priority/Priority Byte Offset 788 "
group.long 0x718++0x03
line.long 0x00 "GICD_IPRIORITYR198,Interrupt Priority Register 198"
hexmask.long.byte 0x00 24.--31. 1. " INTID795  ,Interrupt ID795  Priority/Priority Byte Offset 795 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID794  ,Interrupt ID794   Priority/Priority Byte Offset 794 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID793  ,Interrupt ID793  Priority/Priority Byte Offset 793 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID792  ,Interrupt ID792   Priority/Priority Byte Offset 792 "
group.long 0x71C++0x03
line.long 0x00 "GICD_IPRIORITYR199,Interrupt Priority Register 199"
hexmask.long.byte 0x00 24.--31. 1. " INTID799  ,Interrupt ID799  Priority/Priority Byte Offset 799 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID798  ,Interrupt ID798   Priority/Priority Byte Offset 798 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID797  ,Interrupt ID797  Priority/Priority Byte Offset 797 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID796  ,Interrupt ID796   Priority/Priority Byte Offset 796 "
else
rgroup.long 0x700++0x03
line.long 0x00 "GICD_IPRIORITYR192,Interrupt Priority Register 192"
rgroup.long 0x704++0x03
line.long 0x00 "GICD_IPRIORITYR193,Interrupt Priority Register 193"
rgroup.long 0x708++0x03
line.long 0x00 "GICD_IPRIORITYR194,Interrupt Priority Register 194"
rgroup.long 0x70C++0x03
line.long 0x00 "GICD_IPRIORITYR195,Interrupt Priority Register 195"
rgroup.long 0x710++0x03
line.long 0x00 "GICD_IPRIORITYR196,Interrupt Priority Register 196"
rgroup.long 0x714++0x03
line.long 0x00 "GICD_IPRIORITYR197,Interrupt Priority Register 197"
rgroup.long 0x718++0x03
line.long 0x00 "GICD_IPRIORITYR198,Interrupt Priority Register 198"
rgroup.long 0x71C++0x03
line.long 0x00 "GICD_IPRIORITYR199,Interrupt Priority Register 199"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x19)
group.long 0x720++0x03
line.long 0x00 "GICD_IPRIORITYR200,Interrupt Priority Register 200"
hexmask.long.byte 0x00 24.--31. 1. " INTID803  ,Interrupt ID803  Priority/Priority Byte Offset 803 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID802  ,Interrupt ID802   Priority/Priority Byte Offset 802 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID801  ,Interrupt ID801  Priority/Priority Byte Offset 801 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID800  ,Interrupt ID800   Priority/Priority Byte Offset 800 "
group.long 0x724++0x03
line.long 0x00 "GICD_IPRIORITYR201,Interrupt Priority Register 201"
hexmask.long.byte 0x00 24.--31. 1. " INTID807  ,Interrupt ID807  Priority/Priority Byte Offset 807 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID806  ,Interrupt ID806   Priority/Priority Byte Offset 806 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID805  ,Interrupt ID805  Priority/Priority Byte Offset 805 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID804  ,Interrupt ID804   Priority/Priority Byte Offset 804 "
group.long 0x728++0x03
line.long 0x00 "GICD_IPRIORITYR202,Interrupt Priority Register 202"
hexmask.long.byte 0x00 24.--31. 1. " INTID811  ,Interrupt ID811  Priority/Priority Byte Offset 811 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID810  ,Interrupt ID810   Priority/Priority Byte Offset 810 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID809  ,Interrupt ID809  Priority/Priority Byte Offset 809 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID808  ,Interrupt ID808   Priority/Priority Byte Offset 808 "
group.long 0x72C++0x03
line.long 0x00 "GICD_IPRIORITYR203,Interrupt Priority Register 203"
hexmask.long.byte 0x00 24.--31. 1. " INTID815  ,Interrupt ID815  Priority/Priority Byte Offset 815 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID814  ,Interrupt ID814   Priority/Priority Byte Offset 814 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID813  ,Interrupt ID813  Priority/Priority Byte Offset 813 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID812  ,Interrupt ID812   Priority/Priority Byte Offset 812 "
group.long 0x730++0x03
line.long 0x00 "GICD_IPRIORITYR204,Interrupt Priority Register 204"
hexmask.long.byte 0x00 24.--31. 1. " INTID819  ,Interrupt ID819  Priority/Priority Byte Offset 819 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID818  ,Interrupt ID818   Priority/Priority Byte Offset 818 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID817  ,Interrupt ID817  Priority/Priority Byte Offset 817 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID816  ,Interrupt ID816   Priority/Priority Byte Offset 816 "
group.long 0x734++0x03
line.long 0x00 "GICD_IPRIORITYR205,Interrupt Priority Register 205"
hexmask.long.byte 0x00 24.--31. 1. " INTID823  ,Interrupt ID823  Priority/Priority Byte Offset 823 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID822  ,Interrupt ID822   Priority/Priority Byte Offset 822 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID821  ,Interrupt ID821  Priority/Priority Byte Offset 821 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID820  ,Interrupt ID820   Priority/Priority Byte Offset 820 "
group.long 0x738++0x03
line.long 0x00 "GICD_IPRIORITYR206,Interrupt Priority Register 206"
hexmask.long.byte 0x00 24.--31. 1. " INTID827  ,Interrupt ID827  Priority/Priority Byte Offset 827 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID826  ,Interrupt ID826   Priority/Priority Byte Offset 826 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID825  ,Interrupt ID825  Priority/Priority Byte Offset 825 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID824  ,Interrupt ID824   Priority/Priority Byte Offset 824 "
group.long 0x73C++0x03
line.long 0x00 "GICD_IPRIORITYR207,Interrupt Priority Register 207"
hexmask.long.byte 0x00 24.--31. 1. " INTID831  ,Interrupt ID831  Priority/Priority Byte Offset 831 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID830  ,Interrupt ID830   Priority/Priority Byte Offset 830 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID829  ,Interrupt ID829  Priority/Priority Byte Offset 829 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID828  ,Interrupt ID828   Priority/Priority Byte Offset 828 "
else
rgroup.long 0x720++0x03
line.long 0x00 "GICD_IPRIORITYR200,Interrupt Priority Register 200"
rgroup.long 0x724++0x03
line.long 0x00 "GICD_IPRIORITYR201,Interrupt Priority Register 201"
rgroup.long 0x728++0x03
line.long 0x00 "GICD_IPRIORITYR202,Interrupt Priority Register 202"
rgroup.long 0x72C++0x03
line.long 0x00 "GICD_IPRIORITYR203,Interrupt Priority Register 203"
rgroup.long 0x730++0x03
line.long 0x00 "GICD_IPRIORITYR204,Interrupt Priority Register 204"
rgroup.long 0x734++0x03
line.long 0x00 "GICD_IPRIORITYR205,Interrupt Priority Register 205"
rgroup.long 0x738++0x03
line.long 0x00 "GICD_IPRIORITYR206,Interrupt Priority Register 206"
rgroup.long 0x73C++0x03
line.long 0x00 "GICD_IPRIORITYR207,Interrupt Priority Register 207"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1A)
group.long 0x740++0x03
line.long 0x00 "GICD_IPRIORITYR208,Interrupt Priority Register 208"
hexmask.long.byte 0x00 24.--31. 1. " INTID835  ,Interrupt ID835  Priority/Priority Byte Offset 835 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID834  ,Interrupt ID834   Priority/Priority Byte Offset 834 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID833  ,Interrupt ID833  Priority/Priority Byte Offset 833 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID832  ,Interrupt ID832   Priority/Priority Byte Offset 832 "
group.long 0x744++0x03
line.long 0x00 "GICD_IPRIORITYR209,Interrupt Priority Register 209"
hexmask.long.byte 0x00 24.--31. 1. " INTID839  ,Interrupt ID839  Priority/Priority Byte Offset 839 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID838  ,Interrupt ID838   Priority/Priority Byte Offset 838 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID837  ,Interrupt ID837  Priority/Priority Byte Offset 837 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID836  ,Interrupt ID836   Priority/Priority Byte Offset 836 "
group.long 0x748++0x03
line.long 0x00 "GICD_IPRIORITYR210,Interrupt Priority Register 210"
hexmask.long.byte 0x00 24.--31. 1. " INTID843  ,Interrupt ID843  Priority/Priority Byte Offset 843 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID842  ,Interrupt ID842   Priority/Priority Byte Offset 842 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID841  ,Interrupt ID841  Priority/Priority Byte Offset 841 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID840  ,Interrupt ID840   Priority/Priority Byte Offset 840 "
group.long 0x74C++0x03
line.long 0x00 "GICD_IPRIORITYR211,Interrupt Priority Register 211"
hexmask.long.byte 0x00 24.--31. 1. " INTID847  ,Interrupt ID847  Priority/Priority Byte Offset 847 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID846  ,Interrupt ID846   Priority/Priority Byte Offset 846 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID845  ,Interrupt ID845  Priority/Priority Byte Offset 845 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID844  ,Interrupt ID844   Priority/Priority Byte Offset 844 "
group.long 0x750++0x03
line.long 0x00 "GICD_IPRIORITYR212,Interrupt Priority Register 212"
hexmask.long.byte 0x00 24.--31. 1. " INTID851  ,Interrupt ID851  Priority/Priority Byte Offset 851 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID850  ,Interrupt ID850   Priority/Priority Byte Offset 850 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID849  ,Interrupt ID849  Priority/Priority Byte Offset 849 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID848  ,Interrupt ID848   Priority/Priority Byte Offset 848 "
group.long 0x754++0x03
line.long 0x00 "GICD_IPRIORITYR213,Interrupt Priority Register 213"
hexmask.long.byte 0x00 24.--31. 1. " INTID855  ,Interrupt ID855  Priority/Priority Byte Offset 855 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID854  ,Interrupt ID854   Priority/Priority Byte Offset 854 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID853  ,Interrupt ID853  Priority/Priority Byte Offset 853 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID852  ,Interrupt ID852   Priority/Priority Byte Offset 852 "
group.long 0x758++0x03
line.long 0x00 "GICD_IPRIORITYR214,Interrupt Priority Register 214"
hexmask.long.byte 0x00 24.--31. 1. " INTID859  ,Interrupt ID859  Priority/Priority Byte Offset 859 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID858  ,Interrupt ID858   Priority/Priority Byte Offset 858 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID857  ,Interrupt ID857  Priority/Priority Byte Offset 857 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID856  ,Interrupt ID856   Priority/Priority Byte Offset 856 "
group.long 0x75C++0x03
line.long 0x00 "GICD_IPRIORITYR215,Interrupt Priority Register 215"
hexmask.long.byte 0x00 24.--31. 1. " INTID863  ,Interrupt ID863  Priority/Priority Byte Offset 863 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID862  ,Interrupt ID862   Priority/Priority Byte Offset 862 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID861  ,Interrupt ID861  Priority/Priority Byte Offset 861 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID860  ,Interrupt ID860   Priority/Priority Byte Offset 860 "
else
rgroup.long 0x740++0x03
line.long 0x00 "GICD_IPRIORITYR208,Interrupt Priority Register 208"
rgroup.long 0x744++0x03
line.long 0x00 "GICD_IPRIORITYR209,Interrupt Priority Register 209"
rgroup.long 0x748++0x03
line.long 0x00 "GICD_IPRIORITYR210,Interrupt Priority Register 210"
rgroup.long 0x74C++0x03
line.long 0x00 "GICD_IPRIORITYR211,Interrupt Priority Register 211"
rgroup.long 0x750++0x03
line.long 0x00 "GICD_IPRIORITYR212,Interrupt Priority Register 212"
rgroup.long 0x754++0x03
line.long 0x00 "GICD_IPRIORITYR213,Interrupt Priority Register 213"
rgroup.long 0x758++0x03
line.long 0x00 "GICD_IPRIORITYR214,Interrupt Priority Register 214"
rgroup.long 0x75C++0x03
line.long 0x00 "GICD_IPRIORITYR215,Interrupt Priority Register 215"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1B)
group.long 0x760++0x03
line.long 0x00 "GICD_IPRIORITYR216,Interrupt Priority Register 216"
hexmask.long.byte 0x00 24.--31. 1. " INTID867  ,Interrupt ID867  Priority/Priority Byte Offset 867 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID866  ,Interrupt ID866   Priority/Priority Byte Offset 866 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID865  ,Interrupt ID865  Priority/Priority Byte Offset 865 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID864  ,Interrupt ID864   Priority/Priority Byte Offset 864 "
group.long 0x764++0x03
line.long 0x00 "GICD_IPRIORITYR217,Interrupt Priority Register 217"
hexmask.long.byte 0x00 24.--31. 1. " INTID871  ,Interrupt ID871  Priority/Priority Byte Offset 871 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID870  ,Interrupt ID870   Priority/Priority Byte Offset 870 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID869  ,Interrupt ID869  Priority/Priority Byte Offset 869 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID868  ,Interrupt ID868   Priority/Priority Byte Offset 868 "
group.long 0x768++0x03
line.long 0x00 "GICD_IPRIORITYR218,Interrupt Priority Register 218"
hexmask.long.byte 0x00 24.--31. 1. " INTID875  ,Interrupt ID875  Priority/Priority Byte Offset 875 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID874  ,Interrupt ID874   Priority/Priority Byte Offset 874 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID873  ,Interrupt ID873  Priority/Priority Byte Offset 873 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID872  ,Interrupt ID872   Priority/Priority Byte Offset 872 "
group.long 0x76C++0x03
line.long 0x00 "GICD_IPRIORITYR219,Interrupt Priority Register 219"
hexmask.long.byte 0x00 24.--31. 1. " INTID879  ,Interrupt ID879  Priority/Priority Byte Offset 879 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID878  ,Interrupt ID878   Priority/Priority Byte Offset 878 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID877  ,Interrupt ID877  Priority/Priority Byte Offset 877 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID876  ,Interrupt ID876   Priority/Priority Byte Offset 876 "
group.long 0x770++0x03
line.long 0x00 "GICD_IPRIORITYR220,Interrupt Priority Register 220"
hexmask.long.byte 0x00 24.--31. 1. " INTID883  ,Interrupt ID883  Priority/Priority Byte Offset 883 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID882  ,Interrupt ID882   Priority/Priority Byte Offset 882 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID881  ,Interrupt ID881  Priority/Priority Byte Offset 881 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID880  ,Interrupt ID880   Priority/Priority Byte Offset 880 "
group.long 0x774++0x03
line.long 0x00 "GICD_IPRIORITYR221,Interrupt Priority Register 221"
hexmask.long.byte 0x00 24.--31. 1. " INTID887  ,Interrupt ID887  Priority/Priority Byte Offset 887 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID886  ,Interrupt ID886   Priority/Priority Byte Offset 886 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID885  ,Interrupt ID885  Priority/Priority Byte Offset 885 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID884  ,Interrupt ID884   Priority/Priority Byte Offset 884 "
group.long 0x778++0x03
line.long 0x00 "GICD_IPRIORITYR222,Interrupt Priority Register 222"
hexmask.long.byte 0x00 24.--31. 1. " INTID891  ,Interrupt ID891  Priority/Priority Byte Offset 891 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID890  ,Interrupt ID890   Priority/Priority Byte Offset 890 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID889  ,Interrupt ID889  Priority/Priority Byte Offset 889 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID888  ,Interrupt ID888   Priority/Priority Byte Offset 888 "
group.long 0x77C++0x03
line.long 0x00 "GICD_IPRIORITYR223,Interrupt Priority Register 223"
hexmask.long.byte 0x00 24.--31. 1. " INTID895  ,Interrupt ID895  Priority/Priority Byte Offset 895 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID894  ,Interrupt ID894   Priority/Priority Byte Offset 894 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID893  ,Interrupt ID893  Priority/Priority Byte Offset 893 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID892  ,Interrupt ID892   Priority/Priority Byte Offset 892 "
else
rgroup.long 0x760++0x03
line.long 0x00 "GICD_IPRIORITYR216,Interrupt Priority Register 216"
rgroup.long 0x764++0x03
line.long 0x00 "GICD_IPRIORITYR217,Interrupt Priority Register 217"
rgroup.long 0x768++0x03
line.long 0x00 "GICD_IPRIORITYR218,Interrupt Priority Register 218"
rgroup.long 0x76C++0x03
line.long 0x00 "GICD_IPRIORITYR219,Interrupt Priority Register 219"
rgroup.long 0x770++0x03
line.long 0x00 "GICD_IPRIORITYR220,Interrupt Priority Register 220"
rgroup.long 0x774++0x03
line.long 0x00 "GICD_IPRIORITYR221,Interrupt Priority Register 221"
rgroup.long 0x778++0x03
line.long 0x00 "GICD_IPRIORITYR222,Interrupt Priority Register 222"
rgroup.long 0x77C++0x03
line.long 0x00 "GICD_IPRIORITYR223,Interrupt Priority Register 223"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1C)
group.long 0x780++0x03
line.long 0x00 "GICD_IPRIORITYR224,Interrupt Priority Register 224"
hexmask.long.byte 0x00 24.--31. 1. " INTID899  ,Interrupt ID899  Priority/Priority Byte Offset 899 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID898  ,Interrupt ID898   Priority/Priority Byte Offset 898 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID897  ,Interrupt ID897  Priority/Priority Byte Offset 897 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID896  ,Interrupt ID896   Priority/Priority Byte Offset 896 "
group.long 0x784++0x03
line.long 0x00 "GICD_IPRIORITYR225,Interrupt Priority Register 225"
hexmask.long.byte 0x00 24.--31. 1. " INTID903  ,Interrupt ID903  Priority/Priority Byte Offset 903 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID902  ,Interrupt ID902   Priority/Priority Byte Offset 902 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID901  ,Interrupt ID901  Priority/Priority Byte Offset 901 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID900  ,Interrupt ID900   Priority/Priority Byte Offset 900 "
group.long 0x788++0x03
line.long 0x00 "GICD_IPRIORITYR226,Interrupt Priority Register 226"
hexmask.long.byte 0x00 24.--31. 1. " INTID907  ,Interrupt ID907  Priority/Priority Byte Offset 907 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID906  ,Interrupt ID906   Priority/Priority Byte Offset 906 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID905  ,Interrupt ID905  Priority/Priority Byte Offset 905 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID904  ,Interrupt ID904   Priority/Priority Byte Offset 904 "
group.long 0x78C++0x03
line.long 0x00 "GICD_IPRIORITYR227,Interrupt Priority Register 227"
hexmask.long.byte 0x00 24.--31. 1. " INTID911  ,Interrupt ID911  Priority/Priority Byte Offset 911 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID910  ,Interrupt ID910   Priority/Priority Byte Offset 910 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID909  ,Interrupt ID909  Priority/Priority Byte Offset 909 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID908  ,Interrupt ID908   Priority/Priority Byte Offset 908 "
group.long 0x790++0x03
line.long 0x00 "GICD_IPRIORITYR228,Interrupt Priority Register 228"
hexmask.long.byte 0x00 24.--31. 1. " INTID915  ,Interrupt ID915  Priority/Priority Byte Offset 915 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID914  ,Interrupt ID914   Priority/Priority Byte Offset 914 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID913  ,Interrupt ID913  Priority/Priority Byte Offset 913 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID912  ,Interrupt ID912   Priority/Priority Byte Offset 912 "
group.long 0x794++0x03
line.long 0x00 "GICD_IPRIORITYR229,Interrupt Priority Register 229"
hexmask.long.byte 0x00 24.--31. 1. " INTID919  ,Interrupt ID919  Priority/Priority Byte Offset 919 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID918  ,Interrupt ID918   Priority/Priority Byte Offset 918 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID917  ,Interrupt ID917  Priority/Priority Byte Offset 917 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID916  ,Interrupt ID916   Priority/Priority Byte Offset 916 "
group.long 0x798++0x03
line.long 0x00 "GICD_IPRIORITYR230,Interrupt Priority Register 230"
hexmask.long.byte 0x00 24.--31. 1. " INTID923  ,Interrupt ID923  Priority/Priority Byte Offset 923 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID922  ,Interrupt ID922   Priority/Priority Byte Offset 922 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID921  ,Interrupt ID921  Priority/Priority Byte Offset 921 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID920  ,Interrupt ID920   Priority/Priority Byte Offset 920 "
group.long 0x79C++0x03
line.long 0x00 "GICD_IPRIORITYR231,Interrupt Priority Register 231"
hexmask.long.byte 0x00 24.--31. 1. " INTID927  ,Interrupt ID927  Priority/Priority Byte Offset 927 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID926  ,Interrupt ID926   Priority/Priority Byte Offset 926 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID925  ,Interrupt ID925  Priority/Priority Byte Offset 925 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID924  ,Interrupt ID924   Priority/Priority Byte Offset 924 "
else
rgroup.long 0x780++0x03
line.long 0x00 "GICD_IPRIORITYR224,Interrupt Priority Register 224"
rgroup.long 0x784++0x03
line.long 0x00 "GICD_IPRIORITYR225,Interrupt Priority Register 225"
rgroup.long 0x788++0x03
line.long 0x00 "GICD_IPRIORITYR226,Interrupt Priority Register 226"
rgroup.long 0x78C++0x03
line.long 0x00 "GICD_IPRIORITYR227,Interrupt Priority Register 227"
rgroup.long 0x790++0x03
line.long 0x00 "GICD_IPRIORITYR228,Interrupt Priority Register 228"
rgroup.long 0x794++0x03
line.long 0x00 "GICD_IPRIORITYR229,Interrupt Priority Register 229"
rgroup.long 0x798++0x03
line.long 0x00 "GICD_IPRIORITYR230,Interrupt Priority Register 230"
rgroup.long 0x79C++0x03
line.long 0x00 "GICD_IPRIORITYR231,Interrupt Priority Register 231"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1D)
group.long 0x7A0++0x03
line.long 0x00 "GICD_IPRIORITYR232,Interrupt Priority Register 232"
hexmask.long.byte 0x00 24.--31. 1. " INTID931  ,Interrupt ID931  Priority/Priority Byte Offset 931 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID930  ,Interrupt ID930   Priority/Priority Byte Offset 930 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID929  ,Interrupt ID929  Priority/Priority Byte Offset 929 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID928  ,Interrupt ID928   Priority/Priority Byte Offset 928 "
group.long 0x7A4++0x03
line.long 0x00 "GICD_IPRIORITYR233,Interrupt Priority Register 233"
hexmask.long.byte 0x00 24.--31. 1. " INTID935  ,Interrupt ID935  Priority/Priority Byte Offset 935 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID934  ,Interrupt ID934   Priority/Priority Byte Offset 934 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID933  ,Interrupt ID933  Priority/Priority Byte Offset 933 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID932  ,Interrupt ID932   Priority/Priority Byte Offset 932 "
group.long 0x7A8++0x03
line.long 0x00 "GICD_IPRIORITYR234,Interrupt Priority Register 234"
hexmask.long.byte 0x00 24.--31. 1. " INTID939  ,Interrupt ID939  Priority/Priority Byte Offset 939 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID938  ,Interrupt ID938   Priority/Priority Byte Offset 938 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID937  ,Interrupt ID937  Priority/Priority Byte Offset 937 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID936  ,Interrupt ID936   Priority/Priority Byte Offset 936 "
group.long 0x7AC++0x03
line.long 0x00 "GICD_IPRIORITYR235,Interrupt Priority Register 235"
hexmask.long.byte 0x00 24.--31. 1. " INTID943  ,Interrupt ID943  Priority/Priority Byte Offset 943 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID942  ,Interrupt ID942   Priority/Priority Byte Offset 942 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID941  ,Interrupt ID941  Priority/Priority Byte Offset 941 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID940  ,Interrupt ID940   Priority/Priority Byte Offset 940 "
group.long 0x7B0++0x03
line.long 0x00 "GICD_IPRIORITYR236,Interrupt Priority Register 236"
hexmask.long.byte 0x00 24.--31. 1. " INTID947  ,Interrupt ID947  Priority/Priority Byte Offset 947 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID946  ,Interrupt ID946   Priority/Priority Byte Offset 946 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID945  ,Interrupt ID945  Priority/Priority Byte Offset 945 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID944  ,Interrupt ID944   Priority/Priority Byte Offset 944 "
group.long 0x7B4++0x03
line.long 0x00 "GICD_IPRIORITYR237,Interrupt Priority Register 237"
hexmask.long.byte 0x00 24.--31. 1. " INTID951  ,Interrupt ID951  Priority/Priority Byte Offset 951 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID950  ,Interrupt ID950   Priority/Priority Byte Offset 950 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID949  ,Interrupt ID949  Priority/Priority Byte Offset 949 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID948  ,Interrupt ID948   Priority/Priority Byte Offset 948 "
group.long 0x7B8++0x03
line.long 0x00 "GICD_IPRIORITYR238,Interrupt Priority Register 238"
hexmask.long.byte 0x00 24.--31. 1. " INTID955  ,Interrupt ID955  Priority/Priority Byte Offset 955 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID954  ,Interrupt ID954   Priority/Priority Byte Offset 954 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID953  ,Interrupt ID953  Priority/Priority Byte Offset 953 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID952  ,Interrupt ID952   Priority/Priority Byte Offset 952 "
group.long 0x7BC++0x03
line.long 0x00 "GICD_IPRIORITYR239,Interrupt Priority Register 239"
hexmask.long.byte 0x00 24.--31. 1. " INTID959  ,Interrupt ID959  Priority/Priority Byte Offset 959 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID958  ,Interrupt ID958   Priority/Priority Byte Offset 958 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID957  ,Interrupt ID957  Priority/Priority Byte Offset 957 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID956  ,Interrupt ID956   Priority/Priority Byte Offset 956 "
else
rgroup.long 0x7A0++0x03
line.long 0x00 "GICD_IPRIORITYR232,Interrupt Priority Register 232"
rgroup.long 0x7A4++0x03
line.long 0x00 "GICD_IPRIORITYR233,Interrupt Priority Register 233"
rgroup.long 0x7A8++0x03
line.long 0x00 "GICD_IPRIORITYR234,Interrupt Priority Register 234"
rgroup.long 0x7AC++0x03
line.long 0x00 "GICD_IPRIORITYR235,Interrupt Priority Register 235"
rgroup.long 0x7B0++0x03
line.long 0x00 "GICD_IPRIORITYR236,Interrupt Priority Register 236"
rgroup.long 0x7B4++0x03
line.long 0x00 "GICD_IPRIORITYR237,Interrupt Priority Register 237"
rgroup.long 0x7B8++0x03
line.long 0x00 "GICD_IPRIORITYR238,Interrupt Priority Register 238"
rgroup.long 0x7BC++0x03
line.long 0x00 "GICD_IPRIORITYR239,Interrupt Priority Register 239"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1E)
group.long 0x7C0++0x03
line.long 0x00 "GICD_IPRIORITYR240,Interrupt Priority Register 240"
hexmask.long.byte 0x00 24.--31. 1. " INTID963  ,Interrupt ID963  Priority/Priority Byte Offset 963 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID962  ,Interrupt ID962   Priority/Priority Byte Offset 962 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID961  ,Interrupt ID961  Priority/Priority Byte Offset 961 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID960  ,Interrupt ID960   Priority/Priority Byte Offset 960 "
group.long 0x7C4++0x03
line.long 0x00 "GICD_IPRIORITYR241,Interrupt Priority Register 241"
hexmask.long.byte 0x00 24.--31. 1. " INTID967  ,Interrupt ID967  Priority/Priority Byte Offset 967 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID966  ,Interrupt ID966   Priority/Priority Byte Offset 966 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID965  ,Interrupt ID965  Priority/Priority Byte Offset 965 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID964  ,Interrupt ID964   Priority/Priority Byte Offset 964 "
group.long 0x7C8++0x03
line.long 0x00 "GICD_IPRIORITYR242,Interrupt Priority Register 242"
hexmask.long.byte 0x00 24.--31. 1. " INTID971  ,Interrupt ID971  Priority/Priority Byte Offset 971 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID970  ,Interrupt ID970   Priority/Priority Byte Offset 970 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID969  ,Interrupt ID969  Priority/Priority Byte Offset 969 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID968  ,Interrupt ID968   Priority/Priority Byte Offset 968 "
group.long 0x7CC++0x03
line.long 0x00 "GICD_IPRIORITYR243,Interrupt Priority Register 243"
hexmask.long.byte 0x00 24.--31. 1. " INTID975  ,Interrupt ID975  Priority/Priority Byte Offset 975 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID974  ,Interrupt ID974   Priority/Priority Byte Offset 974 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID973  ,Interrupt ID973  Priority/Priority Byte Offset 973 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID972  ,Interrupt ID972   Priority/Priority Byte Offset 972 "
group.long 0x7D0++0x03
line.long 0x00 "GICD_IPRIORITYR244,Interrupt Priority Register 244"
hexmask.long.byte 0x00 24.--31. 1. " INTID979  ,Interrupt ID979  Priority/Priority Byte Offset 979 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID978  ,Interrupt ID978   Priority/Priority Byte Offset 978 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID977  ,Interrupt ID977  Priority/Priority Byte Offset 977 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID976  ,Interrupt ID976   Priority/Priority Byte Offset 976 "
group.long 0x7D4++0x03
line.long 0x00 "GICD_IPRIORITYR245,Interrupt Priority Register 245"
hexmask.long.byte 0x00 24.--31. 1. " INTID983  ,Interrupt ID983  Priority/Priority Byte Offset 983 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID982  ,Interrupt ID982   Priority/Priority Byte Offset 982 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID981  ,Interrupt ID981  Priority/Priority Byte Offset 981 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID980  ,Interrupt ID980   Priority/Priority Byte Offset 980 "
group.long 0x7D8++0x03
line.long 0x00 "GICD_IPRIORITYR246,Interrupt Priority Register 246"
hexmask.long.byte 0x00 24.--31. 1. " INTID987  ,Interrupt ID987  Priority/Priority Byte Offset 987 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID986  ,Interrupt ID986   Priority/Priority Byte Offset 986 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID985  ,Interrupt ID985  Priority/Priority Byte Offset 985 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID984  ,Interrupt ID984   Priority/Priority Byte Offset 984 "
group.long 0x7DC++0x03
line.long 0x00 "GICD_IPRIORITYR247,Interrupt Priority Register 247"
hexmask.long.byte 0x00 24.--31. 1. " INTID991  ,Interrupt ID991  Priority/Priority Byte Offset 991 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID990  ,Interrupt ID990   Priority/Priority Byte Offset 990 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID989  ,Interrupt ID989  Priority/Priority Byte Offset 989 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID988  ,Interrupt ID988   Priority/Priority Byte Offset 988 "
else
rgroup.long 0x7C0++0x03
line.long 0x00 "GICD_IPRIORITYR240,Interrupt Priority Register 240"
rgroup.long 0x7C4++0x03
line.long 0x00 "GICD_IPRIORITYR241,Interrupt Priority Register 241"
rgroup.long 0x7C8++0x03
line.long 0x00 "GICD_IPRIORITYR242,Interrupt Priority Register 242"
rgroup.long 0x7CC++0x03
line.long 0x00 "GICD_IPRIORITYR243,Interrupt Priority Register 243"
rgroup.long 0x7D0++0x03
line.long 0x00 "GICD_IPRIORITYR244,Interrupt Priority Register 244"
rgroup.long 0x7D4++0x03
line.long 0x00 "GICD_IPRIORITYR245,Interrupt Priority Register 245"
rgroup.long 0x7D8++0x03
line.long 0x00 "GICD_IPRIORITYR246,Interrupt Priority Register 246"
rgroup.long 0x7DC++0x03
line.long 0x00 "GICD_IPRIORITYR247,Interrupt Priority Register 247"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1F)
group.long 0x7E0++0x03
line.long 0x00 "GICD_IPRIORITYR248,Interrupt Priority Register 248"
hexmask.long.byte 0x00 24.--31. 1. " INTID995  ,Interrupt ID995  Priority/Priority Byte Offset 995 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID994  ,Interrupt ID994   Priority/Priority Byte Offset 994 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID993  ,Interrupt ID993  Priority/Priority Byte Offset 993 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID992  ,Interrupt ID992   Priority/Priority Byte Offset 992 "
group.long 0x7E4++0x03
line.long 0x00 "GICD_IPRIORITYR249,Interrupt Priority Register 249"
hexmask.long.byte 0x00 24.--31. 1. " INTID999  ,Interrupt ID999  Priority/Priority Byte Offset 999 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID998  ,Interrupt ID998   Priority/Priority Byte Offset 998 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID997  ,Interrupt ID997  Priority/Priority Byte Offset 997 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID996  ,Interrupt ID996   Priority/Priority Byte Offset 996 "
group.long 0x7E8++0x03
line.long 0x00 "GICD_IPRIORITYR250,Interrupt Priority Register 250"
hexmask.long.byte 0x00 24.--31. 1. " INTID1003 ,Interrupt ID1003 Priority/Priority Byte Offset 1003"
hexmask.long.byte 0x00 16.--23. 1. "  INTID1002 ,Interrupt ID1002  Priority/Priority Byte Offset 1002"
hexmask.long.byte 0x00 8.--15. 1. "  INTID1001 ,Interrupt ID1001 Priority/Priority Byte Offset 1001"
hexmask.long.byte 0x00 0.--7. 1. "  INTID1000 ,Interrupt ID1000  Priority/Priority Byte Offset 1000"
group.long 0x7EC++0x03
line.long 0x00 "GICD_IPRIORITYR251,Interrupt Priority Register 251"
hexmask.long.byte 0x00 24.--31. 1. " INTID1007 ,Interrupt ID1007 Priority/Priority Byte Offset 1007"
hexmask.long.byte 0x00 16.--23. 1. "  INTID1006 ,Interrupt ID1006  Priority/Priority Byte Offset 1006"
hexmask.long.byte 0x00 8.--15. 1. "  INTID1005 ,Interrupt ID1005 Priority/Priority Byte Offset 1005"
hexmask.long.byte 0x00 0.--7. 1. "  INTID1004 ,Interrupt ID1004  Priority/Priority Byte Offset 1004"
group.long 0x7F0++0x03
line.long 0x00 "GICD_IPRIORITYR252,Interrupt Priority Register 252"
hexmask.long.byte 0x00 24.--31. 1. " INTID1011 ,Interrupt ID1011 Priority/Priority Byte Offset 1011"
hexmask.long.byte 0x00 16.--23. 1. "  INTID1010 ,Interrupt ID1010  Priority/Priority Byte Offset 1010"
hexmask.long.byte 0x00 8.--15. 1. "  INTID1009 ,Interrupt ID1009 Priority/Priority Byte Offset 1009"
hexmask.long.byte 0x00 0.--7. 1. "  INTID1008 ,Interrupt ID1008  Priority/Priority Byte Offset 1008"
group.long 0x7F4++0x03
line.long 0x00 "GICD_IPRIORITYR253,Interrupt Priority Register 253"
hexmask.long.byte 0x00 24.--31. 1. " INTID1015 ,Interrupt ID1015 Priority/Priority Byte Offset 1015"
hexmask.long.byte 0x00 16.--23. 1. "  INTID1014 ,Interrupt ID1014  Priority/Priority Byte Offset 1014"
hexmask.long.byte 0x00 8.--15. 1. "  INTID1013 ,Interrupt ID1013 Priority/Priority Byte Offset 1013"
hexmask.long.byte 0x00 0.--7. 1. "  INTID1012 ,Interrupt ID1012  Priority/Priority Byte Offset 1012"
group.long 0x7F8++0x03
line.long 0x00 "GICD_IPRIORITYR254,Interrupt Priority Register 254"
hexmask.long.byte 0x00 24.--31. 1. " INTID1019 ,Interrupt ID1019 Priority/Priority Byte Offset 1019"
hexmask.long.byte 0x00 16.--23. 1. "  INTID1018 ,Interrupt ID1018  Priority/Priority Byte Offset 1018"
hexmask.long.byte 0x00 8.--15. 1. "  INTID1017 ,Interrupt ID1017 Priority/Priority Byte Offset 1017"
hexmask.long.byte 0x00 0.--7. 1. "  INTID1016 ,Interrupt ID1016  Priority/Priority Byte Offset 1016"
else
rgroup.long 0x7E0++0x03
line.long 0x00 "GICD_IPRIORITYR248,Interrupt Priority Register 248"
rgroup.long 0x7E4++0x03
line.long 0x00 "GICD_IPRIORITYR249,Interrupt Priority Register 249"
rgroup.long 0x7E8++0x03
line.long 0x00 "GICD_IPRIORITYR250,Interrupt Priority Register 250"
rgroup.long 0x7EC++0x03
line.long 0x00 "GICD_IPRIORITYR251,Interrupt Priority Register 251"
rgroup.long 0x7F0++0x03
line.long 0x00 "GICD_IPRIORITYR252,Interrupt Priority Register 252"
rgroup.long 0x7F4++0x03
line.long 0x00 "GICD_IPRIORITYR253,Interrupt Priority Register 253"
rgroup.long 0x7F8++0x03
line.long 0x00 "GICD_IPRIORITYR254,Interrupt Priority Register 254"
endif
tree.end
width 19.
tree "Processor Targets Registers"
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x000000E0)>0x1)
rgroup.long 0x800++0x03
line.long 0x00 "GICD_ITARGETSR0,Interrupt Processor Targets Register 0"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3    ,CPU Targets Byte Offset 3   "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO2    ,CPU Targets Byte Offset 2   "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO1    ,CPU Targets Byte Offset 1   "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO0    ,CPU Targets Byte Offset 0   "
rgroup.long 0x804++0x03
line.long 0x00 "GICD_ITARGETSR1,Interrupt Processor Targets Register 1"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO7    ,CPU Targets Byte Offset 7   "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO6    ,CPU Targets Byte Offset 6   "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO5    ,CPU Targets Byte Offset 5   "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO4    ,CPU Targets Byte Offset 4   "
rgroup.long 0x808++0x03
line.long 0x00 "GICD_ITARGETSR2,Interrupt Processor Targets Register 2"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO11   ,CPU Targets Byte Offset 11  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO10   ,CPU Targets Byte Offset 10  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO9    ,CPU Targets Byte Offset 9   "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO8    ,CPU Targets Byte Offset 8   "
rgroup.long 0x80C++0x03
line.long 0x00 "GICD_ITARGETSR3,Interrupt Processor Targets Register 3"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO15   ,CPU Targets Byte Offset 15  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO14   ,CPU Targets Byte Offset 14  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO13   ,CPU Targets Byte Offset 13  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO12   ,CPU Targets Byte Offset 12  "
rgroup.long 0x810++0x03
line.long 0x00 "GICD_ITARGETSR4,Interrupt Processor Targets Register 4"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO19   ,CPU Targets Byte Offset 19  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO18   ,CPU Targets Byte Offset 18  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO17   ,CPU Targets Byte Offset 17  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO16   ,CPU Targets Byte Offset 16  "
rgroup.long 0x814++0x03
line.long 0x00 "GICD_ITARGETSR5,Interrupt Processor Targets Register 5"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO23   ,CPU Targets Byte Offset 23  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO22   ,CPU Targets Byte Offset 22  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO21   ,CPU Targets Byte Offset 21  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO20   ,CPU Targets Byte Offset 20  "
rgroup.long 0x818++0x03
line.long 0x00 "GICD_ITARGETSR6,Interrupt Processor Targets Register 6"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO27   ,CPU Targets Byte Offset 27  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO26   ,CPU Targets Byte Offset 26  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO25   ,CPU Targets Byte Offset 25  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO24   ,CPU Targets Byte Offset 24  "
rgroup.long 0x81C++0x03
line.long 0x00 "GICD_ITARGETSR7,Interrupt Processor Targets Register 7"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO31   ,CPU Targets Byte Offset 31  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO30   ,CPU Targets Byte Offset 30  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO29   ,CPU Targets Byte Offset 29  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO28   ,CPU Targets Byte Offset 28  "
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x01)
group.long 0x820++0x03
line.long 0x00 "GICD_ITARGETSR8,Interrupt Processor Targets Register 8"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO35   ,CPU Targets Byte Offset 35  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO34   ,CPU Targets Byte Offset 34  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO33   ,CPU Targets Byte Offset 33  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO32   ,CPU Targets Byte Offset 32  "
group.long 0x824++0x03
line.long 0x00 "GICD_ITARGETSR9,Interrupt Processor Targets Register 9"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO39   ,CPU Targets Byte Offset 39  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO38   ,CPU Targets Byte Offset 38  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO37   ,CPU Targets Byte Offset 37  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO36   ,CPU Targets Byte Offset 36  "
group.long 0x828++0x03
line.long 0x00 "GICD_ITARGETSR10,Interrupt Processor Targets Register 10"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO43   ,CPU Targets Byte Offset 43  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO42   ,CPU Targets Byte Offset 42  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO41   ,CPU Targets Byte Offset 41  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO40   ,CPU Targets Byte Offset 40  "
group.long 0x82C++0x03
line.long 0x00 "GICD_ITARGETSR11,Interrupt Processor Targets Register 11"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO47   ,CPU Targets Byte Offset 47  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO46   ,CPU Targets Byte Offset 46  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO45   ,CPU Targets Byte Offset 45  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO44   ,CPU Targets Byte Offset 44  "
group.long 0x830++0x03
line.long 0x00 "GICD_ITARGETSR12,Interrupt Processor Targets Register 12"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO51   ,CPU Targets Byte Offset 51  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO50   ,CPU Targets Byte Offset 50  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO49   ,CPU Targets Byte Offset 49  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO48   ,CPU Targets Byte Offset 48  "
group.long 0x834++0x03
line.long 0x00 "GICD_ITARGETSR13,Interrupt Processor Targets Register 13"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO55   ,CPU Targets Byte Offset 55  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO54   ,CPU Targets Byte Offset 54  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO53   ,CPU Targets Byte Offset 53  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO52   ,CPU Targets Byte Offset 52  "
group.long 0x838++0x03
line.long 0x00 "GICD_ITARGETSR14,Interrupt Processor Targets Register 14"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO59   ,CPU Targets Byte Offset 59  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO58   ,CPU Targets Byte Offset 58  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO57   ,CPU Targets Byte Offset 57  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO56   ,CPU Targets Byte Offset 56  "
group.long 0x83C++0x03
line.long 0x00 "GICD_ITARGETSR15,Interrupt Processor Targets Register 15"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO63   ,CPU Targets Byte Offset 63  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO62   ,CPU Targets Byte Offset 62  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO61   ,CPU Targets Byte Offset 61  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO60   ,CPU Targets Byte Offset 60  "
else
rgroup.long 0x820++0x03
line.long 0x00 "GICD_ITARGETSR8,Interrupt Processor Targets Register 8"
rgroup.long 0x824++0x03
line.long 0x00 "GICD_ITARGETSR9,Interrupt Processor Targets Register 9"
rgroup.long 0x828++0x03
line.long 0x00 "GICD_ITARGETSR10,Interrupt Processor Targets Register 10"
rgroup.long 0x82C++0x03
line.long 0x00 "GICD_ITARGETSR11,Interrupt Processor Targets Register 11"
rgroup.long 0x830++0x03
line.long 0x00 "GICD_ITARGETSR12,Interrupt Processor Targets Register 12"
rgroup.long 0x834++0x03
line.long 0x00 "GICD_ITARGETSR13,Interrupt Processor Targets Register 13"
rgroup.long 0x838++0x03
line.long 0x00 "GICD_ITARGETSR14,Interrupt Processor Targets Register 14"
rgroup.long 0x83C++0x03
line.long 0x00 "GICD_ITARGETSR15,Interrupt Processor Targets Register 15"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x02)
group.long 0x840++0x03
line.long 0x00 "GICD_ITARGETSR16,Interrupt Processor Targets Register 16"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO67   ,CPU Targets Byte Offset 67  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO66   ,CPU Targets Byte Offset 66  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO65   ,CPU Targets Byte Offset 65  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO64   ,CPU Targets Byte Offset 64  "
group.long 0x844++0x03
line.long 0x00 "GICD_ITARGETSR17,Interrupt Processor Targets Register 17"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO71   ,CPU Targets Byte Offset 71  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO70   ,CPU Targets Byte Offset 70  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO69   ,CPU Targets Byte Offset 69  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO68   ,CPU Targets Byte Offset 68  "
group.long 0x848++0x03
line.long 0x00 "GICD_ITARGETSR18,Interrupt Processor Targets Register 18"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO75   ,CPU Targets Byte Offset 75  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO74   ,CPU Targets Byte Offset 74  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO73   ,CPU Targets Byte Offset 73  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO72   ,CPU Targets Byte Offset 72  "
group.long 0x84C++0x03
line.long 0x00 "GICD_ITARGETSR19,Interrupt Processor Targets Register 19"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO79   ,CPU Targets Byte Offset 79  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO78   ,CPU Targets Byte Offset 78  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO77   ,CPU Targets Byte Offset 77  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO76   ,CPU Targets Byte Offset 76  "
group.long 0x850++0x03
line.long 0x00 "GICD_ITARGETSR20,Interrupt Processor Targets Register 20"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO83   ,CPU Targets Byte Offset 83  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO82   ,CPU Targets Byte Offset 82  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO81   ,CPU Targets Byte Offset 81  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO80   ,CPU Targets Byte Offset 80  "
group.long 0x854++0x03
line.long 0x00 "GICD_ITARGETSR21,Interrupt Processor Targets Register 21"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO87   ,CPU Targets Byte Offset 87  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO86   ,CPU Targets Byte Offset 86  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO85   ,CPU Targets Byte Offset 85  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO84   ,CPU Targets Byte Offset 84  "
group.long 0x858++0x03
line.long 0x00 "GICD_ITARGETSR22,Interrupt Processor Targets Register 22"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO91   ,CPU Targets Byte Offset 91  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO90   ,CPU Targets Byte Offset 90  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO89   ,CPU Targets Byte Offset 89  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO88   ,CPU Targets Byte Offset 88  "
group.long 0x85C++0x03
line.long 0x00 "GICD_ITARGETSR23,Interrupt Processor Targets Register 23"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO95   ,CPU Targets Byte Offset 95  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO94   ,CPU Targets Byte Offset 94  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO93   ,CPU Targets Byte Offset 93  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO92   ,CPU Targets Byte Offset 92  "
else
rgroup.long 0x840++0x03
line.long 0x00 "GICD_ITARGETSR16,Interrupt Processor Targets Register 16"
rgroup.long 0x844++0x03
line.long 0x00 "GICD_ITARGETSR17,Interrupt Processor Targets Register 17"
rgroup.long 0x848++0x03
line.long 0x00 "GICD_ITARGETSR18,Interrupt Processor Targets Register 18"
rgroup.long 0x84C++0x03
line.long 0x00 "GICD_ITARGETSR19,Interrupt Processor Targets Register 19"
rgroup.long 0x850++0x03
line.long 0x00 "GICD_ITARGETSR20,Interrupt Processor Targets Register 20"
rgroup.long 0x854++0x03
line.long 0x00 "GICD_ITARGETSR21,Interrupt Processor Targets Register 21"
rgroup.long 0x858++0x03
line.long 0x00 "GICD_ITARGETSR22,Interrupt Processor Targets Register 22"
rgroup.long 0x85C++0x03
line.long 0x00 "GICD_ITARGETSR23,Interrupt Processor Targets Register 23"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x03)
group.long 0x860++0x03
line.long 0x00 "GICD_ITARGETSR24,Interrupt Processor Targets Register 24"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO99   ,CPU Targets Byte Offset 99  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO98   ,CPU Targets Byte Offset 98  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO97   ,CPU Targets Byte Offset 97  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO96   ,CPU Targets Byte Offset 96  "
group.long 0x864++0x03
line.long 0x00 "GICD_ITARGETSR25,Interrupt Processor Targets Register 25"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO103  ,CPU Targets Byte Offset 103 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO102  ,CPU Targets Byte Offset 102 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO101  ,CPU Targets Byte Offset 101 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO100  ,CPU Targets Byte Offset 100 "
group.long 0x868++0x03
line.long 0x00 "GICD_ITARGETSR26,Interrupt Processor Targets Register 26"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO107  ,CPU Targets Byte Offset 107 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO106  ,CPU Targets Byte Offset 106 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO105  ,CPU Targets Byte Offset 105 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO104  ,CPU Targets Byte Offset 104 "
group.long 0x86C++0x03
line.long 0x00 "GICD_ITARGETSR27,Interrupt Processor Targets Register 27"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO111  ,CPU Targets Byte Offset 111 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO110  ,CPU Targets Byte Offset 110 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO109  ,CPU Targets Byte Offset 109 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO108  ,CPU Targets Byte Offset 108 "
group.long 0x870++0x03
line.long 0x00 "GICD_ITARGETSR28,Interrupt Processor Targets Register 28"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO115  ,CPU Targets Byte Offset 115 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO114  ,CPU Targets Byte Offset 114 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO113  ,CPU Targets Byte Offset 113 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO112  ,CPU Targets Byte Offset 112 "
group.long 0x874++0x03
line.long 0x00 "GICD_ITARGETSR29,Interrupt Processor Targets Register 29"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO119  ,CPU Targets Byte Offset 119 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO118  ,CPU Targets Byte Offset 118 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO117  ,CPU Targets Byte Offset 117 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO116  ,CPU Targets Byte Offset 116 "
group.long 0x878++0x03
line.long 0x00 "GICD_ITARGETSR30,Interrupt Processor Targets Register 30"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO123  ,CPU Targets Byte Offset 123 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO122  ,CPU Targets Byte Offset 122 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO121  ,CPU Targets Byte Offset 121 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO120  ,CPU Targets Byte Offset 120 "
group.long 0x87C++0x03
line.long 0x00 "GICD_ITARGETSR31,Interrupt Processor Targets Register 31"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO127  ,CPU Targets Byte Offset 127 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO126  ,CPU Targets Byte Offset 126 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO125  ,CPU Targets Byte Offset 125 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO124  ,CPU Targets Byte Offset 124 "
else
rgroup.long 0x860++0x03
line.long 0x00 "GICD_ITARGETSR24,Interrupt Processor Targets Register 24"
rgroup.long 0x864++0x03
line.long 0x00 "GICD_ITARGETSR25,Interrupt Processor Targets Register 25"
rgroup.long 0x868++0x03
line.long 0x00 "GICD_ITARGETSR26,Interrupt Processor Targets Register 26"
rgroup.long 0x86C++0x03
line.long 0x00 "GICD_ITARGETSR27,Interrupt Processor Targets Register 27"
rgroup.long 0x870++0x03
line.long 0x00 "GICD_ITARGETSR28,Interrupt Processor Targets Register 28"
rgroup.long 0x874++0x03
line.long 0x00 "GICD_ITARGETSR29,Interrupt Processor Targets Register 29"
rgroup.long 0x878++0x03
line.long 0x00 "GICD_ITARGETSR30,Interrupt Processor Targets Register 30"
rgroup.long 0x87C++0x03
line.long 0x00 "GICD_ITARGETSR31,Interrupt Processor Targets Register 31"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x04)
group.long 0x880++0x03
line.long 0x00 "GICD_ITARGETSR32,Interrupt Processor Targets Register 32"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO131  ,CPU Targets Byte Offset 131 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO130  ,CPU Targets Byte Offset 130 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO129  ,CPU Targets Byte Offset 129 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO128  ,CPU Targets Byte Offset 128 "
group.long 0x884++0x03
line.long 0x00 "GICD_ITARGETSR33,Interrupt Processor Targets Register 33"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO135  ,CPU Targets Byte Offset 135 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO134  ,CPU Targets Byte Offset 134 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO133  ,CPU Targets Byte Offset 133 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO132  ,CPU Targets Byte Offset 132 "
group.long 0x888++0x03
line.long 0x00 "GICD_ITARGETSR34,Interrupt Processor Targets Register 34"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO139  ,CPU Targets Byte Offset 139 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO138  ,CPU Targets Byte Offset 138 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO137  ,CPU Targets Byte Offset 137 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO136  ,CPU Targets Byte Offset 136 "
group.long 0x88C++0x03
line.long 0x00 "GICD_ITARGETSR35,Interrupt Processor Targets Register 35"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO143  ,CPU Targets Byte Offset 143 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO142  ,CPU Targets Byte Offset 142 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO141  ,CPU Targets Byte Offset 141 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO140  ,CPU Targets Byte Offset 140 "
group.long 0x890++0x03
line.long 0x00 "GICD_ITARGETSR36,Interrupt Processor Targets Register 36"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO147  ,CPU Targets Byte Offset 147 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO146  ,CPU Targets Byte Offset 146 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO145  ,CPU Targets Byte Offset 145 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO144  ,CPU Targets Byte Offset 144 "
group.long 0x894++0x03
line.long 0x00 "GICD_ITARGETSR37,Interrupt Processor Targets Register 37"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO151  ,CPU Targets Byte Offset 151 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO150  ,CPU Targets Byte Offset 150 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO149  ,CPU Targets Byte Offset 149 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO148  ,CPU Targets Byte Offset 148 "
group.long 0x898++0x03
line.long 0x00 "GICD_ITARGETSR38,Interrupt Processor Targets Register 38"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO155  ,CPU Targets Byte Offset 155 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO154  ,CPU Targets Byte Offset 154 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO153  ,CPU Targets Byte Offset 153 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO152  ,CPU Targets Byte Offset 152 "
group.long 0x89C++0x03
line.long 0x00 "GICD_ITARGETSR39,Interrupt Processor Targets Register 39"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO159  ,CPU Targets Byte Offset 159 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO158  ,CPU Targets Byte Offset 158 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO157  ,CPU Targets Byte Offset 157 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO156  ,CPU Targets Byte Offset 156 "
else
rgroup.long 0x880++0x03
line.long 0x00 "GICD_ITARGETSR32,Interrupt Processor Targets Register 32"
rgroup.long 0x884++0x03
line.long 0x00 "GICD_ITARGETSR33,Interrupt Processor Targets Register 33"
rgroup.long 0x888++0x03
line.long 0x00 "GICD_ITARGETSR34,Interrupt Processor Targets Register 34"
rgroup.long 0x88C++0x03
line.long 0x00 "GICD_ITARGETSR35,Interrupt Processor Targets Register 35"
rgroup.long 0x890++0x03
line.long 0x00 "GICD_ITARGETSR36,Interrupt Processor Targets Register 36"
rgroup.long 0x894++0x03
line.long 0x00 "GICD_ITARGETSR37,Interrupt Processor Targets Register 37"
rgroup.long 0x898++0x03
line.long 0x00 "GICD_ITARGETSR38,Interrupt Processor Targets Register 38"
rgroup.long 0x89C++0x03
line.long 0x00 "GICD_ITARGETSR39,Interrupt Processor Targets Register 39"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x05)
group.long 0x8A0++0x03
line.long 0x00 "GICD_ITARGETSR40,Interrupt Processor Targets Register 40"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO163  ,CPU Targets Byte Offset 163 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO162  ,CPU Targets Byte Offset 162 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO161  ,CPU Targets Byte Offset 161 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO160  ,CPU Targets Byte Offset 160 "
group.long 0x8A4++0x03
line.long 0x00 "GICD_ITARGETSR41,Interrupt Processor Targets Register 41"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO167  ,CPU Targets Byte Offset 167 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO166  ,CPU Targets Byte Offset 166 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO165  ,CPU Targets Byte Offset 165 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO164  ,CPU Targets Byte Offset 164 "
group.long 0x8A8++0x03
line.long 0x00 "GICD_ITARGETSR42,Interrupt Processor Targets Register 42"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO171  ,CPU Targets Byte Offset 171 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO170  ,CPU Targets Byte Offset 170 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO169  ,CPU Targets Byte Offset 169 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO168  ,CPU Targets Byte Offset 168 "
group.long 0x8AC++0x03
line.long 0x00 "GICD_ITARGETSR43,Interrupt Processor Targets Register 43"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO175  ,CPU Targets Byte Offset 175 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO174  ,CPU Targets Byte Offset 174 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO173  ,CPU Targets Byte Offset 173 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO172  ,CPU Targets Byte Offset 172 "
group.long 0x8B0++0x03
line.long 0x00 "GICD_ITARGETSR44,Interrupt Processor Targets Register 44"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO179  ,CPU Targets Byte Offset 179 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO178  ,CPU Targets Byte Offset 178 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO177  ,CPU Targets Byte Offset 177 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO176  ,CPU Targets Byte Offset 176 "
group.long 0x8B4++0x03
line.long 0x00 "GICD_ITARGETSR45,Interrupt Processor Targets Register 45"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO183  ,CPU Targets Byte Offset 183 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO182  ,CPU Targets Byte Offset 182 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO181  ,CPU Targets Byte Offset 181 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO180  ,CPU Targets Byte Offset 180 "
group.long 0x8B8++0x03
line.long 0x00 "GICD_ITARGETSR46,Interrupt Processor Targets Register 46"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO187  ,CPU Targets Byte Offset 187 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO186  ,CPU Targets Byte Offset 186 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO185  ,CPU Targets Byte Offset 185 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO184  ,CPU Targets Byte Offset 184 "
group.long 0x8BC++0x03
line.long 0x00 "GICD_ITARGETSR47,Interrupt Processor Targets Register 47"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO191  ,CPU Targets Byte Offset 191 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO190  ,CPU Targets Byte Offset 190 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO189  ,CPU Targets Byte Offset 189 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO188  ,CPU Targets Byte Offset 188 "
else
rgroup.long 0x8A0++0x03
line.long 0x00 "GICD_ITARGETSR40,Interrupt Processor Targets Register 40"
rgroup.long 0x8A4++0x03
line.long 0x00 "GICD_ITARGETSR41,Interrupt Processor Targets Register 41"
rgroup.long 0x8A8++0x03
line.long 0x00 "GICD_ITARGETSR42,Interrupt Processor Targets Register 42"
rgroup.long 0x8AC++0x03
line.long 0x00 "GICD_ITARGETSR43,Interrupt Processor Targets Register 43"
rgroup.long 0x8B0++0x03
line.long 0x00 "GICD_ITARGETSR44,Interrupt Processor Targets Register 44"
rgroup.long 0x8B4++0x03
line.long 0x00 "GICD_ITARGETSR45,Interrupt Processor Targets Register 45"
rgroup.long 0x8B8++0x03
line.long 0x00 "GICD_ITARGETSR46,Interrupt Processor Targets Register 46"
rgroup.long 0x8BC++0x03
line.long 0x00 "GICD_ITARGETSR47,Interrupt Processor Targets Register 47"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x06)
group.long 0x8C0++0x03
line.long 0x00 "GICD_ITARGETSR48,Interrupt Processor Targets Register 48"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO195  ,CPU Targets Byte Offset 195 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO194  ,CPU Targets Byte Offset 194 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO193  ,CPU Targets Byte Offset 193 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO192  ,CPU Targets Byte Offset 192 "
group.long 0x8C4++0x03
line.long 0x00 "GICD_ITARGETSR49,Interrupt Processor Targets Register 49"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO199  ,CPU Targets Byte Offset 199 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO198  ,CPU Targets Byte Offset 198 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO197  ,CPU Targets Byte Offset 197 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO196  ,CPU Targets Byte Offset 196 "
group.long 0x8C8++0x03
line.long 0x00 "GICD_ITARGETSR50,Interrupt Processor Targets Register 50"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO203  ,CPU Targets Byte Offset 203 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO202  ,CPU Targets Byte Offset 202 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO201  ,CPU Targets Byte Offset 201 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO200  ,CPU Targets Byte Offset 200 "
group.long 0x8CC++0x03
line.long 0x00 "GICD_ITARGETSR51,Interrupt Processor Targets Register 51"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO207  ,CPU Targets Byte Offset 207 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO206  ,CPU Targets Byte Offset 206 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO205  ,CPU Targets Byte Offset 205 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO204  ,CPU Targets Byte Offset 204 "
group.long 0x8D0++0x03
line.long 0x00 "GICD_ITARGETSR52,Interrupt Processor Targets Register 52"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO211  ,CPU Targets Byte Offset 211 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO210  ,CPU Targets Byte Offset 210 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO209  ,CPU Targets Byte Offset 209 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO208  ,CPU Targets Byte Offset 208 "
group.long 0x8D4++0x03
line.long 0x00 "GICD_ITARGETSR53,Interrupt Processor Targets Register 53"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO215  ,CPU Targets Byte Offset 215 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO214  ,CPU Targets Byte Offset 214 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO213  ,CPU Targets Byte Offset 213 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO212  ,CPU Targets Byte Offset 212 "
group.long 0x8D8++0x03
line.long 0x00 "GICD_ITARGETSR54,Interrupt Processor Targets Register 54"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO219  ,CPU Targets Byte Offset 219 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO218  ,CPU Targets Byte Offset 218 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO217  ,CPU Targets Byte Offset 217 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO216  ,CPU Targets Byte Offset 216 "
group.long 0x8DC++0x03
line.long 0x00 "GICD_ITARGETSR55,Interrupt Processor Targets Register 55"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO223  ,CPU Targets Byte Offset 223 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO222  ,CPU Targets Byte Offset 222 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO221  ,CPU Targets Byte Offset 221 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO220  ,CPU Targets Byte Offset 220 "
else
rgroup.long 0x8C0++0x03
line.long 0x00 "GICD_ITARGETSR48,Interrupt Processor Targets Register 48"
rgroup.long 0x8C4++0x03
line.long 0x00 "GICD_ITARGETSR49,Interrupt Processor Targets Register 49"
rgroup.long 0x8C8++0x03
line.long 0x00 "GICD_ITARGETSR50,Interrupt Processor Targets Register 50"
rgroup.long 0x8CC++0x03
line.long 0x00 "GICD_ITARGETSR51,Interrupt Processor Targets Register 51"
rgroup.long 0x8D0++0x03
line.long 0x00 "GICD_ITARGETSR52,Interrupt Processor Targets Register 52"
rgroup.long 0x8D4++0x03
line.long 0x00 "GICD_ITARGETSR53,Interrupt Processor Targets Register 53"
rgroup.long 0x8D8++0x03
line.long 0x00 "GICD_ITARGETSR54,Interrupt Processor Targets Register 54"
rgroup.long 0x8DC++0x03
line.long 0x00 "GICD_ITARGETSR55,Interrupt Processor Targets Register 55"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x07)
group.long 0x8E0++0x03
line.long 0x00 "GICD_ITARGETSR56,Interrupt Processor Targets Register 56"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO227  ,CPU Targets Byte Offset 227 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO226  ,CPU Targets Byte Offset 226 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO225  ,CPU Targets Byte Offset 225 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO224  ,CPU Targets Byte Offset 224 "
group.long 0x8E4++0x03
line.long 0x00 "GICD_ITARGETSR57,Interrupt Processor Targets Register 57"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO231  ,CPU Targets Byte Offset 231 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO230  ,CPU Targets Byte Offset 230 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO229  ,CPU Targets Byte Offset 229 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO228  ,CPU Targets Byte Offset 228 "
group.long 0x8E8++0x03
line.long 0x00 "GICD_ITARGETSR58,Interrupt Processor Targets Register 58"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO235  ,CPU Targets Byte Offset 235 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO234  ,CPU Targets Byte Offset 234 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO233  ,CPU Targets Byte Offset 233 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO232  ,CPU Targets Byte Offset 232 "
group.long 0x8EC++0x03
line.long 0x00 "GICD_ITARGETSR59,Interrupt Processor Targets Register 59"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO239  ,CPU Targets Byte Offset 239 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO238  ,CPU Targets Byte Offset 238 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO237  ,CPU Targets Byte Offset 237 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO236  ,CPU Targets Byte Offset 236 "
group.long 0x8F0++0x03
line.long 0x00 "GICD_ITARGETSR60,Interrupt Processor Targets Register 60"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO243  ,CPU Targets Byte Offset 243 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO242  ,CPU Targets Byte Offset 242 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO241  ,CPU Targets Byte Offset 241 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO240  ,CPU Targets Byte Offset 240 "
group.long 0x8F4++0x03
line.long 0x00 "GICD_ITARGETSR61,Interrupt Processor Targets Register 61"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO247  ,CPU Targets Byte Offset 247 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO246  ,CPU Targets Byte Offset 246 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO245  ,CPU Targets Byte Offset 245 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO244  ,CPU Targets Byte Offset 244 "
group.long 0x8F8++0x03
line.long 0x00 "GICD_ITARGETSR62,Interrupt Processor Targets Register 62"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO251  ,CPU Targets Byte Offset 251 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO250  ,CPU Targets Byte Offset 250 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO249  ,CPU Targets Byte Offset 249 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO248  ,CPU Targets Byte Offset 248 "
group.long 0x8FC++0x03
line.long 0x00 "GICD_ITARGETSR63,Interrupt Processor Targets Register 63"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO255  ,CPU Targets Byte Offset 255 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO254  ,CPU Targets Byte Offset 254 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO253  ,CPU Targets Byte Offset 253 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO252  ,CPU Targets Byte Offset 252 "
else
rgroup.long 0x8E0++0x03
line.long 0x00 "GICD_ITARGETSR56,Interrupt Processor Targets Register 56"
rgroup.long 0x8E4++0x03
line.long 0x00 "GICD_ITARGETSR57,Interrupt Processor Targets Register 57"
rgroup.long 0x8E8++0x03
line.long 0x00 "GICD_ITARGETSR58,Interrupt Processor Targets Register 58"
rgroup.long 0x8EC++0x03
line.long 0x00 "GICD_ITARGETSR59,Interrupt Processor Targets Register 59"
rgroup.long 0x8F0++0x03
line.long 0x00 "GICD_ITARGETSR60,Interrupt Processor Targets Register 60"
rgroup.long 0x8F4++0x03
line.long 0x00 "GICD_ITARGETSR61,Interrupt Processor Targets Register 61"
rgroup.long 0x8F8++0x03
line.long 0x00 "GICD_ITARGETSR62,Interrupt Processor Targets Register 62"
rgroup.long 0x8FC++0x03
line.long 0x00 "GICD_ITARGETSR63,Interrupt Processor Targets Register 63"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x08)
group.long 0x900++0x03
line.long 0x00 "GICD_ITARGETSR64,Interrupt Processor Targets Register 64"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO259  ,CPU Targets Byte Offset 259 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO258  ,CPU Targets Byte Offset 258 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO257  ,CPU Targets Byte Offset 257 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO256  ,CPU Targets Byte Offset 256 "
group.long 0x904++0x03
line.long 0x00 "GICD_ITARGETSR65,Interrupt Processor Targets Register 65"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO263  ,CPU Targets Byte Offset 263 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO262  ,CPU Targets Byte Offset 262 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO261  ,CPU Targets Byte Offset 261 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO260  ,CPU Targets Byte Offset 260 "
group.long 0x908++0x03
line.long 0x00 "GICD_ITARGETSR66,Interrupt Processor Targets Register 66"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO267  ,CPU Targets Byte Offset 267 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO266  ,CPU Targets Byte Offset 266 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO265  ,CPU Targets Byte Offset 265 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO264  ,CPU Targets Byte Offset 264 "
group.long 0x90C++0x03
line.long 0x00 "GICD_ITARGETSR67,Interrupt Processor Targets Register 67"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO271  ,CPU Targets Byte Offset 271 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO270  ,CPU Targets Byte Offset 270 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO269  ,CPU Targets Byte Offset 269 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO268  ,CPU Targets Byte Offset 268 "
group.long 0x910++0x03
line.long 0x00 "GICD_ITARGETSR68,Interrupt Processor Targets Register 68"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO275  ,CPU Targets Byte Offset 275 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO274  ,CPU Targets Byte Offset 274 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO273  ,CPU Targets Byte Offset 273 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO272  ,CPU Targets Byte Offset 272 "
group.long 0x914++0x03
line.long 0x00 "GICD_ITARGETSR69,Interrupt Processor Targets Register 69"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO279  ,CPU Targets Byte Offset 279 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO278  ,CPU Targets Byte Offset 278 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO277  ,CPU Targets Byte Offset 277 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO276  ,CPU Targets Byte Offset 276 "
group.long 0x918++0x03
line.long 0x00 "GICD_ITARGETSR70,Interrupt Processor Targets Register 70"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO283  ,CPU Targets Byte Offset 283 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO282  ,CPU Targets Byte Offset 282 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO281  ,CPU Targets Byte Offset 281 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO280  ,CPU Targets Byte Offset 280 "
group.long 0x91C++0x03
line.long 0x00 "GICD_ITARGETSR71,Interrupt Processor Targets Register 71"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO287  ,CPU Targets Byte Offset 287 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO286  ,CPU Targets Byte Offset 286 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO285  ,CPU Targets Byte Offset 285 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO284  ,CPU Targets Byte Offset 284 "
else
rgroup.long 0x900++0x03
line.long 0x00 "GICD_ITARGETSR64,Interrupt Processor Targets Register 64"
rgroup.long 0x904++0x03
line.long 0x00 "GICD_ITARGETSR65,Interrupt Processor Targets Register 65"
rgroup.long 0x908++0x03
line.long 0x00 "GICD_ITARGETSR66,Interrupt Processor Targets Register 66"
rgroup.long 0x90C++0x03
line.long 0x00 "GICD_ITARGETSR67,Interrupt Processor Targets Register 67"
rgroup.long 0x910++0x03
line.long 0x00 "GICD_ITARGETSR68,Interrupt Processor Targets Register 68"
rgroup.long 0x914++0x03
line.long 0x00 "GICD_ITARGETSR69,Interrupt Processor Targets Register 69"
rgroup.long 0x918++0x03
line.long 0x00 "GICD_ITARGETSR70,Interrupt Processor Targets Register 70"
rgroup.long 0x91C++0x03
line.long 0x00 "GICD_ITARGETSR71,Interrupt Processor Targets Register 71"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x09)
group.long 0x920++0x03
line.long 0x00 "GICD_ITARGETSR72,Interrupt Processor Targets Register 72"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO291  ,CPU Targets Byte Offset 291 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO290  ,CPU Targets Byte Offset 290 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO289  ,CPU Targets Byte Offset 289 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO288  ,CPU Targets Byte Offset 288 "
group.long 0x924++0x03
line.long 0x00 "GICD_ITARGETSR73,Interrupt Processor Targets Register 73"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO295  ,CPU Targets Byte Offset 295 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO294  ,CPU Targets Byte Offset 294 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO293  ,CPU Targets Byte Offset 293 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO292  ,CPU Targets Byte Offset 292 "
group.long 0x928++0x03
line.long 0x00 "GICD_ITARGETSR74,Interrupt Processor Targets Register 74"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO299  ,CPU Targets Byte Offset 299 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO298  ,CPU Targets Byte Offset 298 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO297  ,CPU Targets Byte Offset 297 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO296  ,CPU Targets Byte Offset 296 "
group.long 0x92C++0x03
line.long 0x00 "GICD_ITARGETSR75,Interrupt Processor Targets Register 75"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO303  ,CPU Targets Byte Offset 303 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO302  ,CPU Targets Byte Offset 302 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO301  ,CPU Targets Byte Offset 301 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO300  ,CPU Targets Byte Offset 300 "
group.long 0x930++0x03
line.long 0x00 "GICD_ITARGETSR76,Interrupt Processor Targets Register 76"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO307  ,CPU Targets Byte Offset 307 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO306  ,CPU Targets Byte Offset 306 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO305  ,CPU Targets Byte Offset 305 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO304  ,CPU Targets Byte Offset 304 "
group.long 0x934++0x03
line.long 0x00 "GICD_ITARGETSR77,Interrupt Processor Targets Register 77"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO311  ,CPU Targets Byte Offset 311 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO310  ,CPU Targets Byte Offset 310 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO309  ,CPU Targets Byte Offset 309 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO308  ,CPU Targets Byte Offset 308 "
group.long 0x938++0x03
line.long 0x00 "GICD_ITARGETSR78,Interrupt Processor Targets Register 78"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO315  ,CPU Targets Byte Offset 315 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO314  ,CPU Targets Byte Offset 314 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO313  ,CPU Targets Byte Offset 313 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO312  ,CPU Targets Byte Offset 312 "
group.long 0x93C++0x03
line.long 0x00 "GICD_ITARGETSR79,Interrupt Processor Targets Register 79"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO319  ,CPU Targets Byte Offset 319 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO318  ,CPU Targets Byte Offset 318 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO317  ,CPU Targets Byte Offset 317 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO316  ,CPU Targets Byte Offset 316 "
else
rgroup.long 0x920++0x03
line.long 0x00 "GICD_ITARGETSR72,Interrupt Processor Targets Register 72"
rgroup.long 0x924++0x03
line.long 0x00 "GICD_ITARGETSR73,Interrupt Processor Targets Register 73"
rgroup.long 0x928++0x03
line.long 0x00 "GICD_ITARGETSR74,Interrupt Processor Targets Register 74"
rgroup.long 0x92C++0x03
line.long 0x00 "GICD_ITARGETSR75,Interrupt Processor Targets Register 75"
rgroup.long 0x930++0x03
line.long 0x00 "GICD_ITARGETSR76,Interrupt Processor Targets Register 76"
rgroup.long 0x934++0x03
line.long 0x00 "GICD_ITARGETSR77,Interrupt Processor Targets Register 77"
rgroup.long 0x938++0x03
line.long 0x00 "GICD_ITARGETSR78,Interrupt Processor Targets Register 78"
rgroup.long 0x93C++0x03
line.long 0x00 "GICD_ITARGETSR79,Interrupt Processor Targets Register 79"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0A)
group.long 0x940++0x03
line.long 0x00 "GICD_ITARGETSR80,Interrupt Processor Targets Register 80"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO323  ,CPU Targets Byte Offset 323 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO322  ,CPU Targets Byte Offset 322 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO321  ,CPU Targets Byte Offset 321 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO320  ,CPU Targets Byte Offset 320 "
group.long 0x944++0x03
line.long 0x00 "GICD_ITARGETSR81,Interrupt Processor Targets Register 81"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO327  ,CPU Targets Byte Offset 327 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO326  ,CPU Targets Byte Offset 326 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO325  ,CPU Targets Byte Offset 325 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO324  ,CPU Targets Byte Offset 324 "
group.long 0x948++0x03
line.long 0x00 "GICD_ITARGETSR82,Interrupt Processor Targets Register 82"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO331  ,CPU Targets Byte Offset 331 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO330  ,CPU Targets Byte Offset 330 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO329  ,CPU Targets Byte Offset 329 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO328  ,CPU Targets Byte Offset 328 "
group.long 0x94C++0x03
line.long 0x00 "GICD_ITARGETSR83,Interrupt Processor Targets Register 83"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO335  ,CPU Targets Byte Offset 335 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO334  ,CPU Targets Byte Offset 334 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO333  ,CPU Targets Byte Offset 333 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO332  ,CPU Targets Byte Offset 332 "
group.long 0x950++0x03
line.long 0x00 "GICD_ITARGETSR84,Interrupt Processor Targets Register 84"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO339  ,CPU Targets Byte Offset 339 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO338  ,CPU Targets Byte Offset 338 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO337  ,CPU Targets Byte Offset 337 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO336  ,CPU Targets Byte Offset 336 "
group.long 0x954++0x03
line.long 0x00 "GICD_ITARGETSR85,Interrupt Processor Targets Register 85"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO343  ,CPU Targets Byte Offset 343 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO342  ,CPU Targets Byte Offset 342 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO341  ,CPU Targets Byte Offset 341 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO340  ,CPU Targets Byte Offset 340 "
group.long 0x958++0x03
line.long 0x00 "GICD_ITARGETSR86,Interrupt Processor Targets Register 86"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO347  ,CPU Targets Byte Offset 347 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO346  ,CPU Targets Byte Offset 346 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO345  ,CPU Targets Byte Offset 345 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO344  ,CPU Targets Byte Offset 344 "
group.long 0x95C++0x03
line.long 0x00 "GICD_ITARGETSR87,Interrupt Processor Targets Register 87"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO351  ,CPU Targets Byte Offset 351 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO350  ,CPU Targets Byte Offset 350 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO349  ,CPU Targets Byte Offset 349 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO348  ,CPU Targets Byte Offset 348 "
else
rgroup.long 0x940++0x03
line.long 0x00 "GICD_ITARGETSR80,Interrupt Processor Targets Register 80"
rgroup.long 0x944++0x03
line.long 0x00 "GICD_ITARGETSR81,Interrupt Processor Targets Register 81"
rgroup.long 0x948++0x03
line.long 0x00 "GICD_ITARGETSR82,Interrupt Processor Targets Register 82"
rgroup.long 0x94C++0x03
line.long 0x00 "GICD_ITARGETSR83,Interrupt Processor Targets Register 83"
rgroup.long 0x950++0x03
line.long 0x00 "GICD_ITARGETSR84,Interrupt Processor Targets Register 84"
rgroup.long 0x954++0x03
line.long 0x00 "GICD_ITARGETSR85,Interrupt Processor Targets Register 85"
rgroup.long 0x958++0x03
line.long 0x00 "GICD_ITARGETSR86,Interrupt Processor Targets Register 86"
rgroup.long 0x95C++0x03
line.long 0x00 "GICD_ITARGETSR87,Interrupt Processor Targets Register 87"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0B)
group.long 0x960++0x03
line.long 0x00 "GICD_ITARGETSR88,Interrupt Processor Targets Register 88"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO355  ,CPU Targets Byte Offset 355 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO354  ,CPU Targets Byte Offset 354 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO353  ,CPU Targets Byte Offset 353 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO352  ,CPU Targets Byte Offset 352 "
group.long 0x964++0x03
line.long 0x00 "GICD_ITARGETSR89,Interrupt Processor Targets Register 89"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO359  ,CPU Targets Byte Offset 359 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO358  ,CPU Targets Byte Offset 358 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO357  ,CPU Targets Byte Offset 357 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO356  ,CPU Targets Byte Offset 356 "
group.long 0x968++0x03
line.long 0x00 "GICD_ITARGETSR90,Interrupt Processor Targets Register 90"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO363  ,CPU Targets Byte Offset 363 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO362  ,CPU Targets Byte Offset 362 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO361  ,CPU Targets Byte Offset 361 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO360  ,CPU Targets Byte Offset 360 "
group.long 0x96C++0x03
line.long 0x00 "GICD_ITARGETSR91,Interrupt Processor Targets Register 91"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO367  ,CPU Targets Byte Offset 367 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO366  ,CPU Targets Byte Offset 366 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO365  ,CPU Targets Byte Offset 365 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO364  ,CPU Targets Byte Offset 364 "
group.long 0x970++0x03
line.long 0x00 "GICD_ITARGETSR92,Interrupt Processor Targets Register 92"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO371  ,CPU Targets Byte Offset 371 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO370  ,CPU Targets Byte Offset 370 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO369  ,CPU Targets Byte Offset 369 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO368  ,CPU Targets Byte Offset 368 "
group.long 0x974++0x03
line.long 0x00 "GICD_ITARGETSR93,Interrupt Processor Targets Register 93"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO375  ,CPU Targets Byte Offset 375 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO374  ,CPU Targets Byte Offset 374 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO373  ,CPU Targets Byte Offset 373 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO372  ,CPU Targets Byte Offset 372 "
group.long 0x978++0x03
line.long 0x00 "GICD_ITARGETSR94,Interrupt Processor Targets Register 94"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO379  ,CPU Targets Byte Offset 379 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO378  ,CPU Targets Byte Offset 378 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO377  ,CPU Targets Byte Offset 377 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO376  ,CPU Targets Byte Offset 376 "
group.long 0x97C++0x03
line.long 0x00 "GICD_ITARGETSR95,Interrupt Processor Targets Register 95"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO383  ,CPU Targets Byte Offset 383 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO382  ,CPU Targets Byte Offset 382 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO381  ,CPU Targets Byte Offset 381 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO380  ,CPU Targets Byte Offset 380 "
else
rgroup.long 0x960++0x03
line.long 0x00 "GICD_ITARGETSR88,Interrupt Processor Targets Register 88"
rgroup.long 0x964++0x03
line.long 0x00 "GICD_ITARGETSR89,Interrupt Processor Targets Register 89"
rgroup.long 0x968++0x03
line.long 0x00 "GICD_ITARGETSR90,Interrupt Processor Targets Register 90"
rgroup.long 0x96C++0x03
line.long 0x00 "GICD_ITARGETSR91,Interrupt Processor Targets Register 91"
rgroup.long 0x970++0x03
line.long 0x00 "GICD_ITARGETSR92,Interrupt Processor Targets Register 92"
rgroup.long 0x974++0x03
line.long 0x00 "GICD_ITARGETSR93,Interrupt Processor Targets Register 93"
rgroup.long 0x978++0x03
line.long 0x00 "GICD_ITARGETSR94,Interrupt Processor Targets Register 94"
rgroup.long 0x97C++0x03
line.long 0x00 "GICD_ITARGETSR95,Interrupt Processor Targets Register 95"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0C)
group.long 0x980++0x03
line.long 0x00 "GICD_ITARGETSR96,Interrupt Processor Targets Register 96"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO387  ,CPU Targets Byte Offset 387 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO386  ,CPU Targets Byte Offset 386 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO385  ,CPU Targets Byte Offset 385 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO384  ,CPU Targets Byte Offset 384 "
group.long 0x984++0x03
line.long 0x00 "GICD_ITARGETSR97,Interrupt Processor Targets Register 97"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO391  ,CPU Targets Byte Offset 391 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO390  ,CPU Targets Byte Offset 390 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO389  ,CPU Targets Byte Offset 389 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO388  ,CPU Targets Byte Offset 388 "
group.long 0x988++0x03
line.long 0x00 "GICD_ITARGETSR98,Interrupt Processor Targets Register 98"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO395  ,CPU Targets Byte Offset 395 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO394  ,CPU Targets Byte Offset 394 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO393  ,CPU Targets Byte Offset 393 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO392  ,CPU Targets Byte Offset 392 "
group.long 0x98C++0x03
line.long 0x00 "GICD_ITARGETSR99,Interrupt Processor Targets Register 99"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO399  ,CPU Targets Byte Offset 399 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO398  ,CPU Targets Byte Offset 398 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO397  ,CPU Targets Byte Offset 397 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO396  ,CPU Targets Byte Offset 396 "
group.long 0x990++0x03
line.long 0x00 "GICD_ITARGETSR100,Interrupt Processor Targets Register 100"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO403  ,CPU Targets Byte Offset 403 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO402  ,CPU Targets Byte Offset 402 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO401  ,CPU Targets Byte Offset 401 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO400  ,CPU Targets Byte Offset 400 "
group.long 0x994++0x03
line.long 0x00 "GICD_ITARGETSR101,Interrupt Processor Targets Register 101"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO407  ,CPU Targets Byte Offset 407 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO406  ,CPU Targets Byte Offset 406 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO405  ,CPU Targets Byte Offset 405 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO404  ,CPU Targets Byte Offset 404 "
group.long 0x998++0x03
line.long 0x00 "GICD_ITARGETSR102,Interrupt Processor Targets Register 102"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO411  ,CPU Targets Byte Offset 411 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO410  ,CPU Targets Byte Offset 410 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO409  ,CPU Targets Byte Offset 409 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO408  ,CPU Targets Byte Offset 408 "
group.long 0x99C++0x03
line.long 0x00 "GICD_ITARGETSR103,Interrupt Processor Targets Register 103"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO415  ,CPU Targets Byte Offset 415 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO414  ,CPU Targets Byte Offset 414 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO413  ,CPU Targets Byte Offset 413 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO412  ,CPU Targets Byte Offset 412 "
else
rgroup.long 0x980++0x03
line.long 0x00 "GICD_ITARGETSR96,Interrupt Processor Targets Register 96"
rgroup.long 0x984++0x03
line.long 0x00 "GICD_ITARGETSR97,Interrupt Processor Targets Register 97"
rgroup.long 0x988++0x03
line.long 0x00 "GICD_ITARGETSR98,Interrupt Processor Targets Register 98"
rgroup.long 0x98C++0x03
line.long 0x00 "GICD_ITARGETSR99,Interrupt Processor Targets Register 99"
rgroup.long 0x990++0x03
line.long 0x00 "GICD_ITARGETSR100,Interrupt Processor Targets Register 100"
rgroup.long 0x994++0x03
line.long 0x00 "GICD_ITARGETSR101,Interrupt Processor Targets Register 101"
rgroup.long 0x998++0x03
line.long 0x00 "GICD_ITARGETSR102,Interrupt Processor Targets Register 102"
rgroup.long 0x99C++0x03
line.long 0x00 "GICD_ITARGETSR103,Interrupt Processor Targets Register 103"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0D)
group.long 0x9A0++0x03
line.long 0x00 "GICD_ITARGETSR104,Interrupt Processor Targets Register 104"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO419  ,CPU Targets Byte Offset 419 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO418  ,CPU Targets Byte Offset 418 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO417  ,CPU Targets Byte Offset 417 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO416  ,CPU Targets Byte Offset 416 "
group.long 0x9A4++0x03
line.long 0x00 "GICD_ITARGETSR105,Interrupt Processor Targets Register 105"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO423  ,CPU Targets Byte Offset 423 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO422  ,CPU Targets Byte Offset 422 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO421  ,CPU Targets Byte Offset 421 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO420  ,CPU Targets Byte Offset 420 "
group.long 0x9A8++0x03
line.long 0x00 "GICD_ITARGETSR106,Interrupt Processor Targets Register 106"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO427  ,CPU Targets Byte Offset 427 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO426  ,CPU Targets Byte Offset 426 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO425  ,CPU Targets Byte Offset 425 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO424  ,CPU Targets Byte Offset 424 "
group.long 0x9AC++0x03
line.long 0x00 "GICD_ITARGETSR107,Interrupt Processor Targets Register 107"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO431  ,CPU Targets Byte Offset 431 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO430  ,CPU Targets Byte Offset 430 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO429  ,CPU Targets Byte Offset 429 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO428  ,CPU Targets Byte Offset 428 "
group.long 0x9B0++0x03
line.long 0x00 "GICD_ITARGETSR108,Interrupt Processor Targets Register 108"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO435  ,CPU Targets Byte Offset 435 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO434  ,CPU Targets Byte Offset 434 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO433  ,CPU Targets Byte Offset 433 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO432  ,CPU Targets Byte Offset 432 "
group.long 0x9B4++0x03
line.long 0x00 "GICD_ITARGETSR109,Interrupt Processor Targets Register 109"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO439  ,CPU Targets Byte Offset 439 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO438  ,CPU Targets Byte Offset 438 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO437  ,CPU Targets Byte Offset 437 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO436  ,CPU Targets Byte Offset 436 "
group.long 0x9B8++0x03
line.long 0x00 "GICD_ITARGETSR110,Interrupt Processor Targets Register 110"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO443  ,CPU Targets Byte Offset 443 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO442  ,CPU Targets Byte Offset 442 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO441  ,CPU Targets Byte Offset 441 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO440  ,CPU Targets Byte Offset 440 "
group.long 0x9BC++0x03
line.long 0x00 "GICD_ITARGETSR111,Interrupt Processor Targets Register 111"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO447  ,CPU Targets Byte Offset 447 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO446  ,CPU Targets Byte Offset 446 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO445  ,CPU Targets Byte Offset 445 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO444  ,CPU Targets Byte Offset 444 "
else
rgroup.long 0x9A0++0x03
line.long 0x00 "GICD_ITARGETSR104,Interrupt Processor Targets Register 104"
rgroup.long 0x9A4++0x03
line.long 0x00 "GICD_ITARGETSR105,Interrupt Processor Targets Register 105"
rgroup.long 0x9A8++0x03
line.long 0x00 "GICD_ITARGETSR106,Interrupt Processor Targets Register 106"
rgroup.long 0x9AC++0x03
line.long 0x00 "GICD_ITARGETSR107,Interrupt Processor Targets Register 107"
rgroup.long 0x9B0++0x03
line.long 0x00 "GICD_ITARGETSR108,Interrupt Processor Targets Register 108"
rgroup.long 0x9B4++0x03
line.long 0x00 "GICD_ITARGETSR109,Interrupt Processor Targets Register 109"
rgroup.long 0x9B8++0x03
line.long 0x00 "GICD_ITARGETSR110,Interrupt Processor Targets Register 110"
rgroup.long 0x9BC++0x03
line.long 0x00 "GICD_ITARGETSR111,Interrupt Processor Targets Register 111"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0E)
group.long 0x9C0++0x03
line.long 0x00 "GICD_ITARGETSR112,Interrupt Processor Targets Register 112"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO451  ,CPU Targets Byte Offset 451 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO450  ,CPU Targets Byte Offset 450 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO449  ,CPU Targets Byte Offset 449 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO448  ,CPU Targets Byte Offset 448 "
group.long 0x9C4++0x03
line.long 0x00 "GICD_ITARGETSR113,Interrupt Processor Targets Register 113"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO455  ,CPU Targets Byte Offset 455 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO454  ,CPU Targets Byte Offset 454 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO453  ,CPU Targets Byte Offset 453 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO452  ,CPU Targets Byte Offset 452 "
group.long 0x9C8++0x03
line.long 0x00 "GICD_ITARGETSR114,Interrupt Processor Targets Register 114"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO459  ,CPU Targets Byte Offset 459 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO458  ,CPU Targets Byte Offset 458 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO457  ,CPU Targets Byte Offset 457 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO456  ,CPU Targets Byte Offset 456 "
group.long 0x9CC++0x03
line.long 0x00 "GICD_ITARGETSR115,Interrupt Processor Targets Register 115"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO463  ,CPU Targets Byte Offset 463 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO462  ,CPU Targets Byte Offset 462 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO461  ,CPU Targets Byte Offset 461 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO460  ,CPU Targets Byte Offset 460 "
group.long 0x9D0++0x03
line.long 0x00 "GICD_ITARGETSR116,Interrupt Processor Targets Register 116"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO467  ,CPU Targets Byte Offset 467 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO466  ,CPU Targets Byte Offset 466 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO465  ,CPU Targets Byte Offset 465 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO464  ,CPU Targets Byte Offset 464 "
group.long 0x9D4++0x03
line.long 0x00 "GICD_ITARGETSR117,Interrupt Processor Targets Register 117"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO471  ,CPU Targets Byte Offset 471 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO470  ,CPU Targets Byte Offset 470 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO469  ,CPU Targets Byte Offset 469 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO468  ,CPU Targets Byte Offset 468 "
group.long 0x9D8++0x03
line.long 0x00 "GICD_ITARGETSR118,Interrupt Processor Targets Register 118"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO475  ,CPU Targets Byte Offset 475 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO474  ,CPU Targets Byte Offset 474 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO473  ,CPU Targets Byte Offset 473 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO472  ,CPU Targets Byte Offset 472 "
group.long 0x9DC++0x03
line.long 0x00 "GICD_ITARGETSR119,Interrupt Processor Targets Register 119"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO479  ,CPU Targets Byte Offset 479 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO478  ,CPU Targets Byte Offset 478 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO477  ,CPU Targets Byte Offset 477 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO476  ,CPU Targets Byte Offset 476 "
else
rgroup.long 0x9C0++0x03
line.long 0x00 "GICD_ITARGETSR112,Interrupt Processor Targets Register 112"
rgroup.long 0x9C4++0x03
line.long 0x00 "GICD_ITARGETSR113,Interrupt Processor Targets Register 113"
rgroup.long 0x9C8++0x03
line.long 0x00 "GICD_ITARGETSR114,Interrupt Processor Targets Register 114"
rgroup.long 0x9CC++0x03
line.long 0x00 "GICD_ITARGETSR115,Interrupt Processor Targets Register 115"
rgroup.long 0x9D0++0x03
line.long 0x00 "GICD_ITARGETSR116,Interrupt Processor Targets Register 116"
rgroup.long 0x9D4++0x03
line.long 0x00 "GICD_ITARGETSR117,Interrupt Processor Targets Register 117"
rgroup.long 0x9D8++0x03
line.long 0x00 "GICD_ITARGETSR118,Interrupt Processor Targets Register 118"
rgroup.long 0x9DC++0x03
line.long 0x00 "GICD_ITARGETSR119,Interrupt Processor Targets Register 119"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0F)
group.long 0x9E0++0x03
line.long 0x00 "GICD_ITARGETSR120,Interrupt Processor Targets Register 120"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO483  ,CPU Targets Byte Offset 483 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO482  ,CPU Targets Byte Offset 482 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO481  ,CPU Targets Byte Offset 481 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO480  ,CPU Targets Byte Offset 480 "
group.long 0x9E4++0x03
line.long 0x00 "GICD_ITARGETSR121,Interrupt Processor Targets Register 121"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO487  ,CPU Targets Byte Offset 487 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO486  ,CPU Targets Byte Offset 486 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO485  ,CPU Targets Byte Offset 485 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO484  ,CPU Targets Byte Offset 484 "
group.long 0x9E8++0x03
line.long 0x00 "GICD_ITARGETSR122,Interrupt Processor Targets Register 122"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO491  ,CPU Targets Byte Offset 491 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO490  ,CPU Targets Byte Offset 490 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO489  ,CPU Targets Byte Offset 489 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO488  ,CPU Targets Byte Offset 488 "
group.long 0x9EC++0x03
line.long 0x00 "GICD_ITARGETSR123,Interrupt Processor Targets Register 123"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO495  ,CPU Targets Byte Offset 495 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO494  ,CPU Targets Byte Offset 494 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO493  ,CPU Targets Byte Offset 493 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO492  ,CPU Targets Byte Offset 492 "
group.long 0x9F0++0x03
line.long 0x00 "GICD_ITARGETSR124,Interrupt Processor Targets Register 124"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO499  ,CPU Targets Byte Offset 499 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO498  ,CPU Targets Byte Offset 498 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO497  ,CPU Targets Byte Offset 497 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO496  ,CPU Targets Byte Offset 496 "
group.long 0x9F4++0x03
line.long 0x00 "GICD_ITARGETSR125,Interrupt Processor Targets Register 125"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO503  ,CPU Targets Byte Offset 503 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO502  ,CPU Targets Byte Offset 502 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO501  ,CPU Targets Byte Offset 501 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO500  ,CPU Targets Byte Offset 500 "
group.long 0x9F8++0x03
line.long 0x00 "GICD_ITARGETSR126,Interrupt Processor Targets Register 126"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO507  ,CPU Targets Byte Offset 507 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO506  ,CPU Targets Byte Offset 506 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO505  ,CPU Targets Byte Offset 505 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO504  ,CPU Targets Byte Offset 504 "
group.long 0x9FC++0x03
line.long 0x00 "GICD_ITARGETSR127,Interrupt Processor Targets Register 127"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO511  ,CPU Targets Byte Offset 511 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO510  ,CPU Targets Byte Offset 510 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO509  ,CPU Targets Byte Offset 509 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO508  ,CPU Targets Byte Offset 508 "
else
rgroup.long 0x9E0++0x03
line.long 0x00 "GICD_ITARGETSR120,Interrupt Processor Targets Register 120"
rgroup.long 0x9E4++0x03
line.long 0x00 "GICD_ITARGETSR121,Interrupt Processor Targets Register 121"
rgroup.long 0x9E8++0x03
line.long 0x00 "GICD_ITARGETSR122,Interrupt Processor Targets Register 122"
rgroup.long 0x9EC++0x03
line.long 0x00 "GICD_ITARGETSR123,Interrupt Processor Targets Register 123"
rgroup.long 0x9F0++0x03
line.long 0x00 "GICD_ITARGETSR124,Interrupt Processor Targets Register 124"
rgroup.long 0x9F4++0x03
line.long 0x00 "GICD_ITARGETSR125,Interrupt Processor Targets Register 125"
rgroup.long 0x9F8++0x03
line.long 0x00 "GICD_ITARGETSR126,Interrupt Processor Targets Register 126"
rgroup.long 0x9FC++0x03
line.long 0x00 "GICD_ITARGETSR127,Interrupt Processor Targets Register 127"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x10)
group.long 0xA00++0x03
line.long 0x00 "GICD_ITARGETSR128,Interrupt Processor Targets Register 128"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO515  ,CPU Targets Byte Offset 515 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO514  ,CPU Targets Byte Offset 514 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO513  ,CPU Targets Byte Offset 513 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO512  ,CPU Targets Byte Offset 512 "
group.long 0xA04++0x03
line.long 0x00 "GICD_ITARGETSR129,Interrupt Processor Targets Register 129"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO519  ,CPU Targets Byte Offset 519 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO518  ,CPU Targets Byte Offset 518 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO517  ,CPU Targets Byte Offset 517 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO516  ,CPU Targets Byte Offset 516 "
group.long 0xA08++0x03
line.long 0x00 "GICD_ITARGETSR130,Interrupt Processor Targets Register 130"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO523  ,CPU Targets Byte Offset 523 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO522  ,CPU Targets Byte Offset 522 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO521  ,CPU Targets Byte Offset 521 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO520  ,CPU Targets Byte Offset 520 "
group.long 0xA0C++0x03
line.long 0x00 "GICD_ITARGETSR131,Interrupt Processor Targets Register 131"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO527  ,CPU Targets Byte Offset 527 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO526  ,CPU Targets Byte Offset 526 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO525  ,CPU Targets Byte Offset 525 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO524  ,CPU Targets Byte Offset 524 "
group.long 0xA10++0x03
line.long 0x00 "GICD_ITARGETSR132,Interrupt Processor Targets Register 132"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO531  ,CPU Targets Byte Offset 531 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO530  ,CPU Targets Byte Offset 530 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO529  ,CPU Targets Byte Offset 529 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO528  ,CPU Targets Byte Offset 528 "
group.long 0xA14++0x03
line.long 0x00 "GICD_ITARGETSR133,Interrupt Processor Targets Register 133"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO535  ,CPU Targets Byte Offset 535 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO534  ,CPU Targets Byte Offset 534 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO533  ,CPU Targets Byte Offset 533 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO532  ,CPU Targets Byte Offset 532 "
group.long 0xA18++0x03
line.long 0x00 "GICD_ITARGETSR134,Interrupt Processor Targets Register 134"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO539  ,CPU Targets Byte Offset 539 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO538  ,CPU Targets Byte Offset 538 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO537  ,CPU Targets Byte Offset 537 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO536  ,CPU Targets Byte Offset 536 "
group.long 0xA1C++0x03
line.long 0x00 "GICD_ITARGETSR135,Interrupt Processor Targets Register 135"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO543  ,CPU Targets Byte Offset 543 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO542  ,CPU Targets Byte Offset 542 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO541  ,CPU Targets Byte Offset 541 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO540  ,CPU Targets Byte Offset 540 "
else
rgroup.long 0xA00++0x03
line.long 0x00 "GICD_ITARGETSR128,Interrupt Processor Targets Register 128"
rgroup.long 0xA04++0x03
line.long 0x00 "GICD_ITARGETSR129,Interrupt Processor Targets Register 129"
rgroup.long 0xA08++0x03
line.long 0x00 "GICD_ITARGETSR130,Interrupt Processor Targets Register 130"
rgroup.long 0xA0C++0x03
line.long 0x00 "GICD_ITARGETSR131,Interrupt Processor Targets Register 131"
rgroup.long 0xA10++0x03
line.long 0x00 "GICD_ITARGETSR132,Interrupt Processor Targets Register 132"
rgroup.long 0xA14++0x03
line.long 0x00 "GICD_ITARGETSR133,Interrupt Processor Targets Register 133"
rgroup.long 0xA18++0x03
line.long 0x00 "GICD_ITARGETSR134,Interrupt Processor Targets Register 134"
rgroup.long 0xA1C++0x03
line.long 0x00 "GICD_ITARGETSR135,Interrupt Processor Targets Register 135"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x11)
group.long 0xA20++0x03
line.long 0x00 "GICD_ITARGETSR136,Interrupt Processor Targets Register 136"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO547  ,CPU Targets Byte Offset 547 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO546  ,CPU Targets Byte Offset 546 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO545  ,CPU Targets Byte Offset 545 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO544  ,CPU Targets Byte Offset 544 "
group.long 0xA24++0x03
line.long 0x00 "GICD_ITARGETSR137,Interrupt Processor Targets Register 137"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO551  ,CPU Targets Byte Offset 551 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO550  ,CPU Targets Byte Offset 550 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO549  ,CPU Targets Byte Offset 549 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO548  ,CPU Targets Byte Offset 548 "
group.long 0xA28++0x03
line.long 0x00 "GICD_ITARGETSR138,Interrupt Processor Targets Register 138"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO555  ,CPU Targets Byte Offset 555 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO554  ,CPU Targets Byte Offset 554 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO553  ,CPU Targets Byte Offset 553 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO552  ,CPU Targets Byte Offset 552 "
group.long 0xA2C++0x03
line.long 0x00 "GICD_ITARGETSR139,Interrupt Processor Targets Register 139"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO559  ,CPU Targets Byte Offset 559 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO558  ,CPU Targets Byte Offset 558 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO557  ,CPU Targets Byte Offset 557 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO556  ,CPU Targets Byte Offset 556 "
group.long 0xA30++0x03
line.long 0x00 "GICD_ITARGETSR140,Interrupt Processor Targets Register 140"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO563  ,CPU Targets Byte Offset 563 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO562  ,CPU Targets Byte Offset 562 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO561  ,CPU Targets Byte Offset 561 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO560  ,CPU Targets Byte Offset 560 "
group.long 0xA34++0x03
line.long 0x00 "GICD_ITARGETSR141,Interrupt Processor Targets Register 141"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO567  ,CPU Targets Byte Offset 567 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO566  ,CPU Targets Byte Offset 566 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO565  ,CPU Targets Byte Offset 565 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO564  ,CPU Targets Byte Offset 564 "
group.long 0xA38++0x03
line.long 0x00 "GICD_ITARGETSR142,Interrupt Processor Targets Register 142"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO571  ,CPU Targets Byte Offset 571 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO570  ,CPU Targets Byte Offset 570 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO569  ,CPU Targets Byte Offset 569 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO568  ,CPU Targets Byte Offset 568 "
group.long 0xA3C++0x03
line.long 0x00 "GICD_ITARGETSR143,Interrupt Processor Targets Register 143"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO575  ,CPU Targets Byte Offset 575 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO574  ,CPU Targets Byte Offset 574 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO573  ,CPU Targets Byte Offset 573 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO572  ,CPU Targets Byte Offset 572 "
else
rgroup.long 0xA20++0x03
line.long 0x00 "GICD_ITARGETSR136,Interrupt Processor Targets Register 136"
rgroup.long 0xA24++0x03
line.long 0x00 "GICD_ITARGETSR137,Interrupt Processor Targets Register 137"
rgroup.long 0xA28++0x03
line.long 0x00 "GICD_ITARGETSR138,Interrupt Processor Targets Register 138"
rgroup.long 0xA2C++0x03
line.long 0x00 "GICD_ITARGETSR139,Interrupt Processor Targets Register 139"
rgroup.long 0xA30++0x03
line.long 0x00 "GICD_ITARGETSR140,Interrupt Processor Targets Register 140"
rgroup.long 0xA34++0x03
line.long 0x00 "GICD_ITARGETSR141,Interrupt Processor Targets Register 141"
rgroup.long 0xA38++0x03
line.long 0x00 "GICD_ITARGETSR142,Interrupt Processor Targets Register 142"
rgroup.long 0xA3C++0x03
line.long 0x00 "GICD_ITARGETSR143,Interrupt Processor Targets Register 143"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x12)
group.long 0xA40++0x03
line.long 0x00 "GICD_ITARGETSR144,Interrupt Processor Targets Register 144"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO579  ,CPU Targets Byte Offset 579 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO578  ,CPU Targets Byte Offset 578 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO577  ,CPU Targets Byte Offset 577 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO576  ,CPU Targets Byte Offset 576 "
group.long 0xA44++0x03
line.long 0x00 "GICD_ITARGETSR145,Interrupt Processor Targets Register 145"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO583  ,CPU Targets Byte Offset 583 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO582  ,CPU Targets Byte Offset 582 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO581  ,CPU Targets Byte Offset 581 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO580  ,CPU Targets Byte Offset 580 "
group.long 0xA48++0x03
line.long 0x00 "GICD_ITARGETSR146,Interrupt Processor Targets Register 146"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO587  ,CPU Targets Byte Offset 587 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO586  ,CPU Targets Byte Offset 586 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO585  ,CPU Targets Byte Offset 585 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO584  ,CPU Targets Byte Offset 584 "
group.long 0xA4C++0x03
line.long 0x00 "GICD_ITARGETSR147,Interrupt Processor Targets Register 147"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO591  ,CPU Targets Byte Offset 591 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO590  ,CPU Targets Byte Offset 590 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO589  ,CPU Targets Byte Offset 589 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO588  ,CPU Targets Byte Offset 588 "
group.long 0xA50++0x03
line.long 0x00 "GICD_ITARGETSR148,Interrupt Processor Targets Register 148"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO595  ,CPU Targets Byte Offset 595 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO594  ,CPU Targets Byte Offset 594 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO593  ,CPU Targets Byte Offset 593 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO592  ,CPU Targets Byte Offset 592 "
group.long 0xA54++0x03
line.long 0x00 "GICD_ITARGETSR149,Interrupt Processor Targets Register 149"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO599  ,CPU Targets Byte Offset 599 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO598  ,CPU Targets Byte Offset 598 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO597  ,CPU Targets Byte Offset 597 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO596  ,CPU Targets Byte Offset 596 "
group.long 0xA58++0x03
line.long 0x00 "GICD_ITARGETSR150,Interrupt Processor Targets Register 150"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO603  ,CPU Targets Byte Offset 603 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO602  ,CPU Targets Byte Offset 602 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO601  ,CPU Targets Byte Offset 601 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO600  ,CPU Targets Byte Offset 600 "
group.long 0xA5C++0x03
line.long 0x00 "GICD_ITARGETSR151,Interrupt Processor Targets Register 151"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO607  ,CPU Targets Byte Offset 607 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO606  ,CPU Targets Byte Offset 606 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO605  ,CPU Targets Byte Offset 605 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO604  ,CPU Targets Byte Offset 604 "
else
rgroup.long 0xA40++0x03
line.long 0x00 "GICD_ITARGETSR144,Interrupt Processor Targets Register 144"
rgroup.long 0xA44++0x03
line.long 0x00 "GICD_ITARGETSR145,Interrupt Processor Targets Register 145"
rgroup.long 0xA48++0x03
line.long 0x00 "GICD_ITARGETSR146,Interrupt Processor Targets Register 146"
rgroup.long 0xA4C++0x03
line.long 0x00 "GICD_ITARGETSR147,Interrupt Processor Targets Register 147"
rgroup.long 0xA50++0x03
line.long 0x00 "GICD_ITARGETSR148,Interrupt Processor Targets Register 148"
rgroup.long 0xA54++0x03
line.long 0x00 "GICD_ITARGETSR149,Interrupt Processor Targets Register 149"
rgroup.long 0xA58++0x03
line.long 0x00 "GICD_ITARGETSR150,Interrupt Processor Targets Register 150"
rgroup.long 0xA5C++0x03
line.long 0x00 "GICD_ITARGETSR151,Interrupt Processor Targets Register 151"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x13)
group.long 0xA60++0x03
line.long 0x00 "GICD_ITARGETSR152,Interrupt Processor Targets Register 152"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO611  ,CPU Targets Byte Offset 611 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO610  ,CPU Targets Byte Offset 610 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO609  ,CPU Targets Byte Offset 609 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO608  ,CPU Targets Byte Offset 608 "
group.long 0xA64++0x03
line.long 0x00 "GICD_ITARGETSR153,Interrupt Processor Targets Register 153"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO615  ,CPU Targets Byte Offset 615 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO614  ,CPU Targets Byte Offset 614 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO613  ,CPU Targets Byte Offset 613 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO612  ,CPU Targets Byte Offset 612 "
group.long 0xA68++0x03
line.long 0x00 "GICD_ITARGETSR154,Interrupt Processor Targets Register 154"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO619  ,CPU Targets Byte Offset 619 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO618  ,CPU Targets Byte Offset 618 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO617  ,CPU Targets Byte Offset 617 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO616  ,CPU Targets Byte Offset 616 "
group.long 0xA6C++0x03
line.long 0x00 "GICD_ITARGETSR155,Interrupt Processor Targets Register 155"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO623  ,CPU Targets Byte Offset 623 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO622  ,CPU Targets Byte Offset 622 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO621  ,CPU Targets Byte Offset 621 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO620  ,CPU Targets Byte Offset 620 "
group.long 0xA70++0x03
line.long 0x00 "GICD_ITARGETSR156,Interrupt Processor Targets Register 156"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO627  ,CPU Targets Byte Offset 627 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO626  ,CPU Targets Byte Offset 626 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO625  ,CPU Targets Byte Offset 625 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO624  ,CPU Targets Byte Offset 624 "
group.long 0xA74++0x03
line.long 0x00 "GICD_ITARGETSR157,Interrupt Processor Targets Register 157"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO631  ,CPU Targets Byte Offset 631 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO630  ,CPU Targets Byte Offset 630 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO629  ,CPU Targets Byte Offset 629 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO628  ,CPU Targets Byte Offset 628 "
group.long 0xA78++0x03
line.long 0x00 "GICD_ITARGETSR158,Interrupt Processor Targets Register 158"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO635  ,CPU Targets Byte Offset 635 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO634  ,CPU Targets Byte Offset 634 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO633  ,CPU Targets Byte Offset 633 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO632  ,CPU Targets Byte Offset 632 "
group.long 0xA7C++0x03
line.long 0x00 "GICD_ITARGETSR159,Interrupt Processor Targets Register 159"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO639  ,CPU Targets Byte Offset 639 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO638  ,CPU Targets Byte Offset 638 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO637  ,CPU Targets Byte Offset 637 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO636  ,CPU Targets Byte Offset 636 "
else
rgroup.long 0xA60++0x03
line.long 0x00 "GICD_ITARGETSR152,Interrupt Processor Targets Register 152"
rgroup.long 0xA64++0x03
line.long 0x00 "GICD_ITARGETSR153,Interrupt Processor Targets Register 153"
rgroup.long 0xA68++0x03
line.long 0x00 "GICD_ITARGETSR154,Interrupt Processor Targets Register 154"
rgroup.long 0xA6C++0x03
line.long 0x00 "GICD_ITARGETSR155,Interrupt Processor Targets Register 155"
rgroup.long 0xA70++0x03
line.long 0x00 "GICD_ITARGETSR156,Interrupt Processor Targets Register 156"
rgroup.long 0xA74++0x03
line.long 0x00 "GICD_ITARGETSR157,Interrupt Processor Targets Register 157"
rgroup.long 0xA78++0x03
line.long 0x00 "GICD_ITARGETSR158,Interrupt Processor Targets Register 158"
rgroup.long 0xA7C++0x03
line.long 0x00 "GICD_ITARGETSR159,Interrupt Processor Targets Register 159"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x14)
group.long 0xA80++0x03
line.long 0x00 "GICD_ITARGETSR160,Interrupt Processor Targets Register 160"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO643  ,CPU Targets Byte Offset 643 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO642  ,CPU Targets Byte Offset 642 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO641  ,CPU Targets Byte Offset 641 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO640  ,CPU Targets Byte Offset 640 "
group.long 0xA84++0x03
line.long 0x00 "GICD_ITARGETSR161,Interrupt Processor Targets Register 161"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO647  ,CPU Targets Byte Offset 647 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO646  ,CPU Targets Byte Offset 646 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO645  ,CPU Targets Byte Offset 645 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO644  ,CPU Targets Byte Offset 644 "
group.long 0xA88++0x03
line.long 0x00 "GICD_ITARGETSR162,Interrupt Processor Targets Register 162"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO651  ,CPU Targets Byte Offset 651 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO650  ,CPU Targets Byte Offset 650 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO649  ,CPU Targets Byte Offset 649 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO648  ,CPU Targets Byte Offset 648 "
group.long 0xA8C++0x03
line.long 0x00 "GICD_ITARGETSR163,Interrupt Processor Targets Register 163"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO655  ,CPU Targets Byte Offset 655 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO654  ,CPU Targets Byte Offset 654 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO653  ,CPU Targets Byte Offset 653 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO652  ,CPU Targets Byte Offset 652 "
group.long 0xA90++0x03
line.long 0x00 "GICD_ITARGETSR164,Interrupt Processor Targets Register 164"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO659  ,CPU Targets Byte Offset 659 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO658  ,CPU Targets Byte Offset 658 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO657  ,CPU Targets Byte Offset 657 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO656  ,CPU Targets Byte Offset 656 "
group.long 0xA94++0x03
line.long 0x00 "GICD_ITARGETSR165,Interrupt Processor Targets Register 165"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO663  ,CPU Targets Byte Offset 663 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO662  ,CPU Targets Byte Offset 662 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO661  ,CPU Targets Byte Offset 661 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO660  ,CPU Targets Byte Offset 660 "
group.long 0xA98++0x03
line.long 0x00 "GICD_ITARGETSR166,Interrupt Processor Targets Register 166"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO667  ,CPU Targets Byte Offset 667 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO666  ,CPU Targets Byte Offset 666 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO665  ,CPU Targets Byte Offset 665 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO664  ,CPU Targets Byte Offset 664 "
group.long 0xA9C++0x03
line.long 0x00 "GICD_ITARGETSR167,Interrupt Processor Targets Register 167"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO671  ,CPU Targets Byte Offset 671 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO670  ,CPU Targets Byte Offset 670 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO669  ,CPU Targets Byte Offset 669 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO668  ,CPU Targets Byte Offset 668 "
else
rgroup.long 0xA80++0x03
line.long 0x00 "GICD_ITARGETSR160,Interrupt Processor Targets Register 160"
rgroup.long 0xA84++0x03
line.long 0x00 "GICD_ITARGETSR161,Interrupt Processor Targets Register 161"
rgroup.long 0xA88++0x03
line.long 0x00 "GICD_ITARGETSR162,Interrupt Processor Targets Register 162"
rgroup.long 0xA8C++0x03
line.long 0x00 "GICD_ITARGETSR163,Interrupt Processor Targets Register 163"
rgroup.long 0xA90++0x03
line.long 0x00 "GICD_ITARGETSR164,Interrupt Processor Targets Register 164"
rgroup.long 0xA94++0x03
line.long 0x00 "GICD_ITARGETSR165,Interrupt Processor Targets Register 165"
rgroup.long 0xA98++0x03
line.long 0x00 "GICD_ITARGETSR166,Interrupt Processor Targets Register 166"
rgroup.long 0xA9C++0x03
line.long 0x00 "GICD_ITARGETSR167,Interrupt Processor Targets Register 167"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x15)
group.long 0xAA0++0x03
line.long 0x00 "GICD_ITARGETSR168,Interrupt Processor Targets Register 168"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO675  ,CPU Targets Byte Offset 675 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO674  ,CPU Targets Byte Offset 674 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO673  ,CPU Targets Byte Offset 673 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO672  ,CPU Targets Byte Offset 672 "
group.long 0xAA4++0x03
line.long 0x00 "GICD_ITARGETSR169,Interrupt Processor Targets Register 169"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO679  ,CPU Targets Byte Offset 679 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO678  ,CPU Targets Byte Offset 678 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO677  ,CPU Targets Byte Offset 677 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO676  ,CPU Targets Byte Offset 676 "
group.long 0xAA8++0x03
line.long 0x00 "GICD_ITARGETSR170,Interrupt Processor Targets Register 170"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO683  ,CPU Targets Byte Offset 683 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO682  ,CPU Targets Byte Offset 682 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO681  ,CPU Targets Byte Offset 681 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO680  ,CPU Targets Byte Offset 680 "
group.long 0xAAC++0x03
line.long 0x00 "GICD_ITARGETSR171,Interrupt Processor Targets Register 171"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO687  ,CPU Targets Byte Offset 687 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO686  ,CPU Targets Byte Offset 686 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO685  ,CPU Targets Byte Offset 685 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO684  ,CPU Targets Byte Offset 684 "
group.long 0xAB0++0x03
line.long 0x00 "GICD_ITARGETSR172,Interrupt Processor Targets Register 172"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO691  ,CPU Targets Byte Offset 691 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO690  ,CPU Targets Byte Offset 690 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO689  ,CPU Targets Byte Offset 689 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO688  ,CPU Targets Byte Offset 688 "
group.long 0xAB4++0x03
line.long 0x00 "GICD_ITARGETSR173,Interrupt Processor Targets Register 173"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO695  ,CPU Targets Byte Offset 695 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO694  ,CPU Targets Byte Offset 694 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO693  ,CPU Targets Byte Offset 693 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO692  ,CPU Targets Byte Offset 692 "
group.long 0xAB8++0x03
line.long 0x00 "GICD_ITARGETSR174,Interrupt Processor Targets Register 174"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO699  ,CPU Targets Byte Offset 699 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO698  ,CPU Targets Byte Offset 698 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO697  ,CPU Targets Byte Offset 697 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO696  ,CPU Targets Byte Offset 696 "
group.long 0xABC++0x03
line.long 0x00 "GICD_ITARGETSR175,Interrupt Processor Targets Register 175"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO703  ,CPU Targets Byte Offset 703 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO702  ,CPU Targets Byte Offset 702 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO701  ,CPU Targets Byte Offset 701 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO700  ,CPU Targets Byte Offset 700 "
else
rgroup.long 0xAA0++0x03
line.long 0x00 "GICD_ITARGETSR168,Interrupt Processor Targets Register 168"
rgroup.long 0xAA4++0x03
line.long 0x00 "GICD_ITARGETSR169,Interrupt Processor Targets Register 169"
rgroup.long 0xAA8++0x03
line.long 0x00 "GICD_ITARGETSR170,Interrupt Processor Targets Register 170"
rgroup.long 0xAAC++0x03
line.long 0x00 "GICD_ITARGETSR171,Interrupt Processor Targets Register 171"
rgroup.long 0xAB0++0x03
line.long 0x00 "GICD_ITARGETSR172,Interrupt Processor Targets Register 172"
rgroup.long 0xAB4++0x03
line.long 0x00 "GICD_ITARGETSR173,Interrupt Processor Targets Register 173"
rgroup.long 0xAB8++0x03
line.long 0x00 "GICD_ITARGETSR174,Interrupt Processor Targets Register 174"
rgroup.long 0xABC++0x03
line.long 0x00 "GICD_ITARGETSR175,Interrupt Processor Targets Register 175"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x16)
group.long 0xAC0++0x03
line.long 0x00 "GICD_ITARGETSR176,Interrupt Processor Targets Register 176"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO707  ,CPU Targets Byte Offset 707 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO706  ,CPU Targets Byte Offset 706 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO705  ,CPU Targets Byte Offset 705 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO704  ,CPU Targets Byte Offset 704 "
group.long 0xAC4++0x03
line.long 0x00 "GICD_ITARGETSR177,Interrupt Processor Targets Register 177"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO711  ,CPU Targets Byte Offset 711 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO710  ,CPU Targets Byte Offset 710 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO709  ,CPU Targets Byte Offset 709 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO708  ,CPU Targets Byte Offset 708 "
group.long 0xAC8++0x03
line.long 0x00 "GICD_ITARGETSR178,Interrupt Processor Targets Register 178"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO715  ,CPU Targets Byte Offset 715 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO714  ,CPU Targets Byte Offset 714 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO713  ,CPU Targets Byte Offset 713 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO712  ,CPU Targets Byte Offset 712 "
group.long 0xACC++0x03
line.long 0x00 "GICD_ITARGETSR179,Interrupt Processor Targets Register 179"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO719  ,CPU Targets Byte Offset 719 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO718  ,CPU Targets Byte Offset 718 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO717  ,CPU Targets Byte Offset 717 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO716  ,CPU Targets Byte Offset 716 "
group.long 0xAD0++0x03
line.long 0x00 "GICD_ITARGETSR180,Interrupt Processor Targets Register 180"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO723  ,CPU Targets Byte Offset 723 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO722  ,CPU Targets Byte Offset 722 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO721  ,CPU Targets Byte Offset 721 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO720  ,CPU Targets Byte Offset 720 "
group.long 0xAD4++0x03
line.long 0x00 "GICD_ITARGETSR181,Interrupt Processor Targets Register 181"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO727  ,CPU Targets Byte Offset 727 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO726  ,CPU Targets Byte Offset 726 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO725  ,CPU Targets Byte Offset 725 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO724  ,CPU Targets Byte Offset 724 "
group.long 0xAD8++0x03
line.long 0x00 "GICD_ITARGETSR182,Interrupt Processor Targets Register 182"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO731  ,CPU Targets Byte Offset 731 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO730  ,CPU Targets Byte Offset 730 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO729  ,CPU Targets Byte Offset 729 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO728  ,CPU Targets Byte Offset 728 "
group.long 0xADC++0x03
line.long 0x00 "GICD_ITARGETSR183,Interrupt Processor Targets Register 183"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO735  ,CPU Targets Byte Offset 735 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO734  ,CPU Targets Byte Offset 734 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO733  ,CPU Targets Byte Offset 733 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO732  ,CPU Targets Byte Offset 732 "
else
rgroup.long 0xAC0++0x03
line.long 0x00 "GICD_ITARGETSR176,Interrupt Processor Targets Register 176"
rgroup.long 0xAC4++0x03
line.long 0x00 "GICD_ITARGETSR177,Interrupt Processor Targets Register 177"
rgroup.long 0xAC8++0x03
line.long 0x00 "GICD_ITARGETSR178,Interrupt Processor Targets Register 178"
rgroup.long 0xACC++0x03
line.long 0x00 "GICD_ITARGETSR179,Interrupt Processor Targets Register 179"
rgroup.long 0xAD0++0x03
line.long 0x00 "GICD_ITARGETSR180,Interrupt Processor Targets Register 180"
rgroup.long 0xAD4++0x03
line.long 0x00 "GICD_ITARGETSR181,Interrupt Processor Targets Register 181"
rgroup.long 0xAD8++0x03
line.long 0x00 "GICD_ITARGETSR182,Interrupt Processor Targets Register 182"
rgroup.long 0xADC++0x03
line.long 0x00 "GICD_ITARGETSR183,Interrupt Processor Targets Register 183"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x17)
group.long 0xAE0++0x03
line.long 0x00 "GICD_ITARGETSR184,Interrupt Processor Targets Register 184"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO739  ,CPU Targets Byte Offset 739 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO738  ,CPU Targets Byte Offset 738 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO737  ,CPU Targets Byte Offset 737 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO736  ,CPU Targets Byte Offset 736 "
group.long 0xAE4++0x03
line.long 0x00 "GICD_ITARGETSR185,Interrupt Processor Targets Register 185"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO743  ,CPU Targets Byte Offset 743 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO742  ,CPU Targets Byte Offset 742 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO741  ,CPU Targets Byte Offset 741 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO740  ,CPU Targets Byte Offset 740 "
group.long 0xAE8++0x03
line.long 0x00 "GICD_ITARGETSR186,Interrupt Processor Targets Register 186"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO747  ,CPU Targets Byte Offset 747 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO746  ,CPU Targets Byte Offset 746 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO745  ,CPU Targets Byte Offset 745 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO744  ,CPU Targets Byte Offset 744 "
group.long 0xAEC++0x03
line.long 0x00 "GICD_ITARGETSR187,Interrupt Processor Targets Register 187"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO751  ,CPU Targets Byte Offset 751 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO750  ,CPU Targets Byte Offset 750 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO749  ,CPU Targets Byte Offset 749 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO748  ,CPU Targets Byte Offset 748 "
group.long 0xAF0++0x03
line.long 0x00 "GICD_ITARGETSR188,Interrupt Processor Targets Register 188"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO755  ,CPU Targets Byte Offset 755 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO754  ,CPU Targets Byte Offset 754 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO753  ,CPU Targets Byte Offset 753 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO752  ,CPU Targets Byte Offset 752 "
group.long 0xAF4++0x03
line.long 0x00 "GICD_ITARGETSR189,Interrupt Processor Targets Register 189"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO759  ,CPU Targets Byte Offset 759 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO758  ,CPU Targets Byte Offset 758 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO757  ,CPU Targets Byte Offset 757 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO756  ,CPU Targets Byte Offset 756 "
group.long 0xAF8++0x03
line.long 0x00 "GICD_ITARGETSR190,Interrupt Processor Targets Register 190"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO763  ,CPU Targets Byte Offset 763 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO762  ,CPU Targets Byte Offset 762 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO761  ,CPU Targets Byte Offset 761 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO760  ,CPU Targets Byte Offset 760 "
group.long 0xAFC++0x03
line.long 0x00 "GICD_ITARGETSR191,Interrupt Processor Targets Register 191"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO767  ,CPU Targets Byte Offset 767 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO766  ,CPU Targets Byte Offset 766 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO765  ,CPU Targets Byte Offset 765 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO764  ,CPU Targets Byte Offset 764 "
else
rgroup.long 0xAE0++0x03
line.long 0x00 "GICD_ITARGETSR184,Interrupt Processor Targets Register 184"
rgroup.long 0xAE4++0x03
line.long 0x00 "GICD_ITARGETSR185,Interrupt Processor Targets Register 185"
rgroup.long 0xAE8++0x03
line.long 0x00 "GICD_ITARGETSR186,Interrupt Processor Targets Register 186"
rgroup.long 0xAEC++0x03
line.long 0x00 "GICD_ITARGETSR187,Interrupt Processor Targets Register 187"
rgroup.long 0xAF0++0x03
line.long 0x00 "GICD_ITARGETSR188,Interrupt Processor Targets Register 188"
rgroup.long 0xAF4++0x03
line.long 0x00 "GICD_ITARGETSR189,Interrupt Processor Targets Register 189"
rgroup.long 0xAF8++0x03
line.long 0x00 "GICD_ITARGETSR190,Interrupt Processor Targets Register 190"
rgroup.long 0xAFC++0x03
line.long 0x00 "GICD_ITARGETSR191,Interrupt Processor Targets Register 191"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x18)
group.long 0xB00++0x03
line.long 0x00 "GICD_ITARGETSR192,Interrupt Processor Targets Register 192"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO771  ,CPU Targets Byte Offset 771 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO770  ,CPU Targets Byte Offset 770 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO769  ,CPU Targets Byte Offset 769 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO768  ,CPU Targets Byte Offset 768 "
group.long 0xB04++0x03
line.long 0x00 "GICD_ITARGETSR193,Interrupt Processor Targets Register 193"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO775  ,CPU Targets Byte Offset 775 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO774  ,CPU Targets Byte Offset 774 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO773  ,CPU Targets Byte Offset 773 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO772  ,CPU Targets Byte Offset 772 "
group.long 0xB08++0x03
line.long 0x00 "GICD_ITARGETSR194,Interrupt Processor Targets Register 194"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO779  ,CPU Targets Byte Offset 779 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO778  ,CPU Targets Byte Offset 778 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO777  ,CPU Targets Byte Offset 777 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO776  ,CPU Targets Byte Offset 776 "
group.long 0xB0C++0x03
line.long 0x00 "GICD_ITARGETSR195,Interrupt Processor Targets Register 195"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO783  ,CPU Targets Byte Offset 783 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO782  ,CPU Targets Byte Offset 782 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO781  ,CPU Targets Byte Offset 781 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO780  ,CPU Targets Byte Offset 780 "
group.long 0xB10++0x03
line.long 0x00 "GICD_ITARGETSR196,Interrupt Processor Targets Register 196"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO787  ,CPU Targets Byte Offset 787 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO786  ,CPU Targets Byte Offset 786 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO785  ,CPU Targets Byte Offset 785 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO784  ,CPU Targets Byte Offset 784 "
group.long 0xB14++0x03
line.long 0x00 "GICD_ITARGETSR197,Interrupt Processor Targets Register 197"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO791  ,CPU Targets Byte Offset 791 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO790  ,CPU Targets Byte Offset 790 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO789  ,CPU Targets Byte Offset 789 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO788  ,CPU Targets Byte Offset 788 "
group.long 0xB18++0x03
line.long 0x00 "GICD_ITARGETSR198,Interrupt Processor Targets Register 198"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO795  ,CPU Targets Byte Offset 795 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO794  ,CPU Targets Byte Offset 794 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO793  ,CPU Targets Byte Offset 793 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO792  ,CPU Targets Byte Offset 792 "
group.long 0xB1C++0x03
line.long 0x00 "GICD_ITARGETSR199,Interrupt Processor Targets Register 199"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO799  ,CPU Targets Byte Offset 799 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO798  ,CPU Targets Byte Offset 798 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO797  ,CPU Targets Byte Offset 797 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO796  ,CPU Targets Byte Offset 796 "
else
rgroup.long 0xB00++0x03
line.long 0x00 "GICD_ITARGETSR192,Interrupt Processor Targets Register 192"
rgroup.long 0xB04++0x03
line.long 0x00 "GICD_ITARGETSR193,Interrupt Processor Targets Register 193"
rgroup.long 0xB08++0x03
line.long 0x00 "GICD_ITARGETSR194,Interrupt Processor Targets Register 194"
rgroup.long 0xB0C++0x03
line.long 0x00 "GICD_ITARGETSR195,Interrupt Processor Targets Register 195"
rgroup.long 0xB10++0x03
line.long 0x00 "GICD_ITARGETSR196,Interrupt Processor Targets Register 196"
rgroup.long 0xB14++0x03
line.long 0x00 "GICD_ITARGETSR197,Interrupt Processor Targets Register 197"
rgroup.long 0xB18++0x03
line.long 0x00 "GICD_ITARGETSR198,Interrupt Processor Targets Register 198"
rgroup.long 0xB1C++0x03
line.long 0x00 "GICD_ITARGETSR199,Interrupt Processor Targets Register 199"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x19)
group.long 0xB20++0x03
line.long 0x00 "GICD_ITARGETSR200,Interrupt Processor Targets Register 200"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO803  ,CPU Targets Byte Offset 803 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO802  ,CPU Targets Byte Offset 802 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO801  ,CPU Targets Byte Offset 801 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO800  ,CPU Targets Byte Offset 800 "
group.long 0xB24++0x03
line.long 0x00 "GICD_ITARGETSR201,Interrupt Processor Targets Register 201"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO807  ,CPU Targets Byte Offset 807 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO806  ,CPU Targets Byte Offset 806 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO805  ,CPU Targets Byte Offset 805 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO804  ,CPU Targets Byte Offset 804 "
group.long 0xB28++0x03
line.long 0x00 "GICD_ITARGETSR202,Interrupt Processor Targets Register 202"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO811  ,CPU Targets Byte Offset 811 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO810  ,CPU Targets Byte Offset 810 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO809  ,CPU Targets Byte Offset 809 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO808  ,CPU Targets Byte Offset 808 "
group.long 0xB2C++0x03
line.long 0x00 "GICD_ITARGETSR203,Interrupt Processor Targets Register 203"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO815  ,CPU Targets Byte Offset 815 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO814  ,CPU Targets Byte Offset 814 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO813  ,CPU Targets Byte Offset 813 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO812  ,CPU Targets Byte Offset 812 "
group.long 0xB30++0x03
line.long 0x00 "GICD_ITARGETSR204,Interrupt Processor Targets Register 204"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO819  ,CPU Targets Byte Offset 819 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO818  ,CPU Targets Byte Offset 818 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO817  ,CPU Targets Byte Offset 817 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO816  ,CPU Targets Byte Offset 816 "
group.long 0xB34++0x03
line.long 0x00 "GICD_ITARGETSR205,Interrupt Processor Targets Register 205"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO823  ,CPU Targets Byte Offset 823 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO822  ,CPU Targets Byte Offset 822 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO821  ,CPU Targets Byte Offset 821 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO820  ,CPU Targets Byte Offset 820 "
group.long 0xB38++0x03
line.long 0x00 "GICD_ITARGETSR206,Interrupt Processor Targets Register 206"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO827  ,CPU Targets Byte Offset 827 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO826  ,CPU Targets Byte Offset 826 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO825  ,CPU Targets Byte Offset 825 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO824  ,CPU Targets Byte Offset 824 "
group.long 0xB3C++0x03
line.long 0x00 "GICD_ITARGETSR207,Interrupt Processor Targets Register 207"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO831  ,CPU Targets Byte Offset 831 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO830  ,CPU Targets Byte Offset 830 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO829  ,CPU Targets Byte Offset 829 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO828  ,CPU Targets Byte Offset 828 "
else
rgroup.long 0xB20++0x03
line.long 0x00 "GICD_ITARGETSR200,Interrupt Processor Targets Register 200"
rgroup.long 0xB24++0x03
line.long 0x00 "GICD_ITARGETSR201,Interrupt Processor Targets Register 201"
rgroup.long 0xB28++0x03
line.long 0x00 "GICD_ITARGETSR202,Interrupt Processor Targets Register 202"
rgroup.long 0xB2C++0x03
line.long 0x00 "GICD_ITARGETSR203,Interrupt Processor Targets Register 203"
rgroup.long 0xB30++0x03
line.long 0x00 "GICD_ITARGETSR204,Interrupt Processor Targets Register 204"
rgroup.long 0xB34++0x03
line.long 0x00 "GICD_ITARGETSR205,Interrupt Processor Targets Register 205"
rgroup.long 0xB38++0x03
line.long 0x00 "GICD_ITARGETSR206,Interrupt Processor Targets Register 206"
rgroup.long 0xB3C++0x03
line.long 0x00 "GICD_ITARGETSR207,Interrupt Processor Targets Register 207"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1A)
group.long 0xB40++0x03
line.long 0x00 "GICD_ITARGETSR208,Interrupt Processor Targets Register 208"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO835  ,CPU Targets Byte Offset 835 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO834  ,CPU Targets Byte Offset 834 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO833  ,CPU Targets Byte Offset 833 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO832  ,CPU Targets Byte Offset 832 "
group.long 0xB44++0x03
line.long 0x00 "GICD_ITARGETSR209,Interrupt Processor Targets Register 209"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO839  ,CPU Targets Byte Offset 839 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO838  ,CPU Targets Byte Offset 838 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO837  ,CPU Targets Byte Offset 837 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO836  ,CPU Targets Byte Offset 836 "
group.long 0xB48++0x03
line.long 0x00 "GICD_ITARGETSR210,Interrupt Processor Targets Register 210"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO843  ,CPU Targets Byte Offset 843 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO842  ,CPU Targets Byte Offset 842 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO841  ,CPU Targets Byte Offset 841 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO840  ,CPU Targets Byte Offset 840 "
group.long 0xB4C++0x03
line.long 0x00 "GICD_ITARGETSR211,Interrupt Processor Targets Register 211"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO847  ,CPU Targets Byte Offset 847 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO846  ,CPU Targets Byte Offset 846 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO845  ,CPU Targets Byte Offset 845 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO844  ,CPU Targets Byte Offset 844 "
group.long 0xB50++0x03
line.long 0x00 "GICD_ITARGETSR212,Interrupt Processor Targets Register 212"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO851  ,CPU Targets Byte Offset 851 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO850  ,CPU Targets Byte Offset 850 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO849  ,CPU Targets Byte Offset 849 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO848  ,CPU Targets Byte Offset 848 "
group.long 0xB54++0x03
line.long 0x00 "GICD_ITARGETSR213,Interrupt Processor Targets Register 213"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO855  ,CPU Targets Byte Offset 855 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO854  ,CPU Targets Byte Offset 854 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO853  ,CPU Targets Byte Offset 853 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO852  ,CPU Targets Byte Offset 852 "
group.long 0xB58++0x03
line.long 0x00 "GICD_ITARGETSR214,Interrupt Processor Targets Register 214"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO859  ,CPU Targets Byte Offset 859 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO858  ,CPU Targets Byte Offset 858 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO857  ,CPU Targets Byte Offset 857 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO856  ,CPU Targets Byte Offset 856 "
group.long 0xB5C++0x03
line.long 0x00 "GICD_ITARGETSR215,Interrupt Processor Targets Register 215"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO863  ,CPU Targets Byte Offset 863 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO862  ,CPU Targets Byte Offset 862 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO861  ,CPU Targets Byte Offset 861 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO860  ,CPU Targets Byte Offset 860 "
else
rgroup.long 0xB40++0x03
line.long 0x00 "GICD_ITARGETSR208,Interrupt Processor Targets Register 208"
rgroup.long 0xB44++0x03
line.long 0x00 "GICD_ITARGETSR209,Interrupt Processor Targets Register 209"
rgroup.long 0xB48++0x03
line.long 0x00 "GICD_ITARGETSR210,Interrupt Processor Targets Register 210"
rgroup.long 0xB4C++0x03
line.long 0x00 "GICD_ITARGETSR211,Interrupt Processor Targets Register 211"
rgroup.long 0xB50++0x03
line.long 0x00 "GICD_ITARGETSR212,Interrupt Processor Targets Register 212"
rgroup.long 0xB54++0x03
line.long 0x00 "GICD_ITARGETSR213,Interrupt Processor Targets Register 213"
rgroup.long 0xB58++0x03
line.long 0x00 "GICD_ITARGETSR214,Interrupt Processor Targets Register 214"
rgroup.long 0xB5C++0x03
line.long 0x00 "GICD_ITARGETSR215,Interrupt Processor Targets Register 215"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1B)
group.long 0xB60++0x03
line.long 0x00 "GICD_ITARGETSR216,Interrupt Processor Targets Register 216"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO867  ,CPU Targets Byte Offset 867 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO866  ,CPU Targets Byte Offset 866 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO865  ,CPU Targets Byte Offset 865 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO864  ,CPU Targets Byte Offset 864 "
group.long 0xB64++0x03
line.long 0x00 "GICD_ITARGETSR217,Interrupt Processor Targets Register 217"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO871  ,CPU Targets Byte Offset 871 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO870  ,CPU Targets Byte Offset 870 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO869  ,CPU Targets Byte Offset 869 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO868  ,CPU Targets Byte Offset 868 "
group.long 0xB68++0x03
line.long 0x00 "GICD_ITARGETSR218,Interrupt Processor Targets Register 218"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO875  ,CPU Targets Byte Offset 875 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO874  ,CPU Targets Byte Offset 874 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO873  ,CPU Targets Byte Offset 873 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO872  ,CPU Targets Byte Offset 872 "
group.long 0xB6C++0x03
line.long 0x00 "GICD_ITARGETSR219,Interrupt Processor Targets Register 219"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO879  ,CPU Targets Byte Offset 879 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO878  ,CPU Targets Byte Offset 878 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO877  ,CPU Targets Byte Offset 877 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO876  ,CPU Targets Byte Offset 876 "
group.long 0xB70++0x03
line.long 0x00 "GICD_ITARGETSR220,Interrupt Processor Targets Register 220"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO883  ,CPU Targets Byte Offset 883 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO882  ,CPU Targets Byte Offset 882 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO881  ,CPU Targets Byte Offset 881 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO880  ,CPU Targets Byte Offset 880 "
group.long 0xB74++0x03
line.long 0x00 "GICD_ITARGETSR221,Interrupt Processor Targets Register 221"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO887  ,CPU Targets Byte Offset 887 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO886  ,CPU Targets Byte Offset 886 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO885  ,CPU Targets Byte Offset 885 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO884  ,CPU Targets Byte Offset 884 "
group.long 0xB78++0x03
line.long 0x00 "GICD_ITARGETSR222,Interrupt Processor Targets Register 222"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO891  ,CPU Targets Byte Offset 891 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO890  ,CPU Targets Byte Offset 890 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO889  ,CPU Targets Byte Offset 889 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO888  ,CPU Targets Byte Offset 888 "
group.long 0xB7C++0x03
line.long 0x00 "GICD_ITARGETSR223,Interrupt Processor Targets Register 223"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO895  ,CPU Targets Byte Offset 895 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO894  ,CPU Targets Byte Offset 894 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO893  ,CPU Targets Byte Offset 893 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO892  ,CPU Targets Byte Offset 892 "
else
rgroup.long 0xB60++0x03
line.long 0x00 "GICD_ITARGETSR216,Interrupt Processor Targets Register 216"
rgroup.long 0xB64++0x03
line.long 0x00 "GICD_ITARGETSR217,Interrupt Processor Targets Register 217"
rgroup.long 0xB68++0x03
line.long 0x00 "GICD_ITARGETSR218,Interrupt Processor Targets Register 218"
rgroup.long 0xB6C++0x03
line.long 0x00 "GICD_ITARGETSR219,Interrupt Processor Targets Register 219"
rgroup.long 0xB70++0x03
line.long 0x00 "GICD_ITARGETSR220,Interrupt Processor Targets Register 220"
rgroup.long 0xB74++0x03
line.long 0x00 "GICD_ITARGETSR221,Interrupt Processor Targets Register 221"
rgroup.long 0xB78++0x03
line.long 0x00 "GICD_ITARGETSR222,Interrupt Processor Targets Register 222"
rgroup.long 0xB7C++0x03
line.long 0x00 "GICD_ITARGETSR223,Interrupt Processor Targets Register 223"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1C)
group.long 0xB80++0x03
line.long 0x00 "GICD_ITARGETSR224,Interrupt Processor Targets Register 224"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO899  ,CPU Targets Byte Offset 899 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO898  ,CPU Targets Byte Offset 898 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO897  ,CPU Targets Byte Offset 897 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO896  ,CPU Targets Byte Offset 896 "
group.long 0xB84++0x03
line.long 0x00 "GICD_ITARGETSR225,Interrupt Processor Targets Register 225"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO903  ,CPU Targets Byte Offset 903 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO902  ,CPU Targets Byte Offset 902 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO901  ,CPU Targets Byte Offset 901 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO900  ,CPU Targets Byte Offset 900 "
group.long 0xB88++0x03
line.long 0x00 "GICD_ITARGETSR226,Interrupt Processor Targets Register 226"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO907  ,CPU Targets Byte Offset 907 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO906  ,CPU Targets Byte Offset 906 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO905  ,CPU Targets Byte Offset 905 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO904  ,CPU Targets Byte Offset 904 "
group.long 0xB8C++0x03
line.long 0x00 "GICD_ITARGETSR227,Interrupt Processor Targets Register 227"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO911  ,CPU Targets Byte Offset 911 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO910  ,CPU Targets Byte Offset 910 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO909  ,CPU Targets Byte Offset 909 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO908  ,CPU Targets Byte Offset 908 "
group.long 0xB90++0x03
line.long 0x00 "GICD_ITARGETSR228,Interrupt Processor Targets Register 228"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO915  ,CPU Targets Byte Offset 915 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO914  ,CPU Targets Byte Offset 914 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO913  ,CPU Targets Byte Offset 913 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO912  ,CPU Targets Byte Offset 912 "
group.long 0xB94++0x03
line.long 0x00 "GICD_ITARGETSR229,Interrupt Processor Targets Register 229"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO919  ,CPU Targets Byte Offset 919 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO918  ,CPU Targets Byte Offset 918 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO917  ,CPU Targets Byte Offset 917 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO916  ,CPU Targets Byte Offset 916 "
group.long 0xB98++0x03
line.long 0x00 "GICD_ITARGETSR230,Interrupt Processor Targets Register 230"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO923  ,CPU Targets Byte Offset 923 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO922  ,CPU Targets Byte Offset 922 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO921  ,CPU Targets Byte Offset 921 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO920  ,CPU Targets Byte Offset 920 "
group.long 0xB9C++0x03
line.long 0x00 "GICD_ITARGETSR231,Interrupt Processor Targets Register 231"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO927  ,CPU Targets Byte Offset 927 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO926  ,CPU Targets Byte Offset 926 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO925  ,CPU Targets Byte Offset 925 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO924  ,CPU Targets Byte Offset 924 "
else
rgroup.long 0xB80++0x03
line.long 0x00 "GICD_ITARGETSR224,Interrupt Processor Targets Register 224"
rgroup.long 0xB84++0x03
line.long 0x00 "GICD_ITARGETSR225,Interrupt Processor Targets Register 225"
rgroup.long 0xB88++0x03
line.long 0x00 "GICD_ITARGETSR226,Interrupt Processor Targets Register 226"
rgroup.long 0xB8C++0x03
line.long 0x00 "GICD_ITARGETSR227,Interrupt Processor Targets Register 227"
rgroup.long 0xB90++0x03
line.long 0x00 "GICD_ITARGETSR228,Interrupt Processor Targets Register 228"
rgroup.long 0xB94++0x03
line.long 0x00 "GICD_ITARGETSR229,Interrupt Processor Targets Register 229"
rgroup.long 0xB98++0x03
line.long 0x00 "GICD_ITARGETSR230,Interrupt Processor Targets Register 230"
rgroup.long 0xB9C++0x03
line.long 0x00 "GICD_ITARGETSR231,Interrupt Processor Targets Register 231"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1D)
group.long 0xBA0++0x03
line.long 0x00 "GICD_ITARGETSR232,Interrupt Processor Targets Register 232"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO931  ,CPU Targets Byte Offset 931 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO930  ,CPU Targets Byte Offset 930 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO929  ,CPU Targets Byte Offset 929 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO928  ,CPU Targets Byte Offset 928 "
group.long 0xBA4++0x03
line.long 0x00 "GICD_ITARGETSR233,Interrupt Processor Targets Register 233"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO935  ,CPU Targets Byte Offset 935 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO934  ,CPU Targets Byte Offset 934 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO933  ,CPU Targets Byte Offset 933 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO932  ,CPU Targets Byte Offset 932 "
group.long 0xBA8++0x03
line.long 0x00 "GICD_ITARGETSR234,Interrupt Processor Targets Register 234"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO939  ,CPU Targets Byte Offset 939 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO938  ,CPU Targets Byte Offset 938 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO937  ,CPU Targets Byte Offset 937 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO936  ,CPU Targets Byte Offset 936 "
group.long 0xBAC++0x03
line.long 0x00 "GICD_ITARGETSR235,Interrupt Processor Targets Register 235"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO943  ,CPU Targets Byte Offset 943 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO942  ,CPU Targets Byte Offset 942 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO941  ,CPU Targets Byte Offset 941 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO940  ,CPU Targets Byte Offset 940 "
group.long 0xBB0++0x03
line.long 0x00 "GICD_ITARGETSR236,Interrupt Processor Targets Register 236"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO947  ,CPU Targets Byte Offset 947 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO946  ,CPU Targets Byte Offset 946 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO945  ,CPU Targets Byte Offset 945 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO944  ,CPU Targets Byte Offset 944 "
group.long 0xBB4++0x03
line.long 0x00 "GICD_ITARGETSR237,Interrupt Processor Targets Register 237"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO951  ,CPU Targets Byte Offset 951 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO950  ,CPU Targets Byte Offset 950 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO949  ,CPU Targets Byte Offset 949 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO948  ,CPU Targets Byte Offset 948 "
group.long 0xBB8++0x03
line.long 0x00 "GICD_ITARGETSR238,Interrupt Processor Targets Register 238"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO955  ,CPU Targets Byte Offset 955 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO954  ,CPU Targets Byte Offset 954 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO953  ,CPU Targets Byte Offset 953 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO952  ,CPU Targets Byte Offset 952 "
group.long 0xBBC++0x03
line.long 0x00 "GICD_ITARGETSR239,Interrupt Processor Targets Register 239"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO959  ,CPU Targets Byte Offset 959 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO958  ,CPU Targets Byte Offset 958 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO957  ,CPU Targets Byte Offset 957 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO956  ,CPU Targets Byte Offset 956 "
else
rgroup.long 0xBA0++0x03
line.long 0x00 "GICD_ITARGETSR232,Interrupt Processor Targets Register 232"
rgroup.long 0xBA4++0x03
line.long 0x00 "GICD_ITARGETSR233,Interrupt Processor Targets Register 233"
rgroup.long 0xBA8++0x03
line.long 0x00 "GICD_ITARGETSR234,Interrupt Processor Targets Register 234"
rgroup.long 0xBAC++0x03
line.long 0x00 "GICD_ITARGETSR235,Interrupt Processor Targets Register 235"
rgroup.long 0xBB0++0x03
line.long 0x00 "GICD_ITARGETSR236,Interrupt Processor Targets Register 236"
rgroup.long 0xBB4++0x03
line.long 0x00 "GICD_ITARGETSR237,Interrupt Processor Targets Register 237"
rgroup.long 0xBB8++0x03
line.long 0x00 "GICD_ITARGETSR238,Interrupt Processor Targets Register 238"
rgroup.long 0xBBC++0x03
line.long 0x00 "GICD_ITARGETSR239,Interrupt Processor Targets Register 239"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1E)
group.long 0xBC0++0x03
line.long 0x00 "GICD_ITARGETSR240,Interrupt Processor Targets Register 240"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO963  ,CPU Targets Byte Offset 963 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO962  ,CPU Targets Byte Offset 962 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO961  ,CPU Targets Byte Offset 961 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO960  ,CPU Targets Byte Offset 960 "
group.long 0xBC4++0x03
line.long 0x00 "GICD_ITARGETSR241,Interrupt Processor Targets Register 241"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO967  ,CPU Targets Byte Offset 967 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO966  ,CPU Targets Byte Offset 966 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO965  ,CPU Targets Byte Offset 965 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO964  ,CPU Targets Byte Offset 964 "
group.long 0xBC8++0x03
line.long 0x00 "GICD_ITARGETSR242,Interrupt Processor Targets Register 242"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO971  ,CPU Targets Byte Offset 971 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO970  ,CPU Targets Byte Offset 970 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO969  ,CPU Targets Byte Offset 969 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO968  ,CPU Targets Byte Offset 968 "
group.long 0xBCC++0x03
line.long 0x00 "GICD_ITARGETSR243,Interrupt Processor Targets Register 243"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO975  ,CPU Targets Byte Offset 975 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO974  ,CPU Targets Byte Offset 974 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO973  ,CPU Targets Byte Offset 973 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO972  ,CPU Targets Byte Offset 972 "
group.long 0xBD0++0x03
line.long 0x00 "GICD_ITARGETSR244,Interrupt Processor Targets Register 244"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO979  ,CPU Targets Byte Offset 979 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO978  ,CPU Targets Byte Offset 978 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO977  ,CPU Targets Byte Offset 977 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO976  ,CPU Targets Byte Offset 976 "
group.long 0xBD4++0x03
line.long 0x00 "GICD_ITARGETSR245,Interrupt Processor Targets Register 245"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO983  ,CPU Targets Byte Offset 983 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO982  ,CPU Targets Byte Offset 982 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO981  ,CPU Targets Byte Offset 981 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO980  ,CPU Targets Byte Offset 980 "
group.long 0xBD8++0x03
line.long 0x00 "GICD_ITARGETSR246,Interrupt Processor Targets Register 246"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO987  ,CPU Targets Byte Offset 987 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO986  ,CPU Targets Byte Offset 986 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO985  ,CPU Targets Byte Offset 985 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO984  ,CPU Targets Byte Offset 984 "
group.long 0xBDC++0x03
line.long 0x00 "GICD_ITARGETSR247,Interrupt Processor Targets Register 247"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO991  ,CPU Targets Byte Offset 991 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO990  ,CPU Targets Byte Offset 990 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO989  ,CPU Targets Byte Offset 989 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO988  ,CPU Targets Byte Offset 988 "
else
rgroup.long 0xBC0++0x03
line.long 0x00 "GICD_ITARGETSR240,Interrupt Processor Targets Register 240"
rgroup.long 0xBC4++0x03
line.long 0x00 "GICD_ITARGETSR241,Interrupt Processor Targets Register 241"
rgroup.long 0xBC8++0x03
line.long 0x00 "GICD_ITARGETSR242,Interrupt Processor Targets Register 242"
rgroup.long 0xBCC++0x03
line.long 0x00 "GICD_ITARGETSR243,Interrupt Processor Targets Register 243"
rgroup.long 0xBD0++0x03
line.long 0x00 "GICD_ITARGETSR244,Interrupt Processor Targets Register 244"
rgroup.long 0xBD4++0x03
line.long 0x00 "GICD_ITARGETSR245,Interrupt Processor Targets Register 245"
rgroup.long 0xBD8++0x03
line.long 0x00 "GICD_ITARGETSR246,Interrupt Processor Targets Register 246"
rgroup.long 0xBDC++0x03
line.long 0x00 "GICD_ITARGETSR247,Interrupt Processor Targets Register 247"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1F)
group.long 0xBE0++0x03
line.long 0x00 "GICD_ITARGETSR248,Interrupt Processor Targets Register 248"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO995  ,CPU Targets Byte Offset 995 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO994  ,CPU Targets Byte Offset 994 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO993  ,CPU Targets Byte Offset 993 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO992  ,CPU Targets Byte Offset 992 "
group.long 0xBE4++0x03
line.long 0x00 "GICD_ITARGETSR249,Interrupt Processor Targets Register 249"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO999  ,CPU Targets Byte Offset 999 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO998  ,CPU Targets Byte Offset 998 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO997  ,CPU Targets Byte Offset 997 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO996  ,CPU Targets Byte Offset 996 "
group.long 0xBE8++0x03
line.long 0x00 "GICD_ITARGETSR250,Interrupt Processor Targets Register 250"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO1003 ,CPU Targets Byte Offset 1003"
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO1002 ,CPU Targets Byte Offset 1002"
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO1001 ,CPU Targets Byte Offset 1001"
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO1000 ,CPU Targets Byte Offset 1000"
group.long 0xBEC++0x03
line.long 0x00 "GICD_ITARGETSR251,Interrupt Processor Targets Register 251"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO1007 ,CPU Targets Byte Offset 1007"
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO1006 ,CPU Targets Byte Offset 1006"
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO1005 ,CPU Targets Byte Offset 1005"
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO1004 ,CPU Targets Byte Offset 1004"
group.long 0xBF0++0x03
line.long 0x00 "GICD_ITARGETSR252,Interrupt Processor Targets Register 252"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO1011 ,CPU Targets Byte Offset 1011"
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO1010 ,CPU Targets Byte Offset 1010"
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO1009 ,CPU Targets Byte Offset 1009"
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO1008 ,CPU Targets Byte Offset 1008"
group.long 0xBF4++0x03
line.long 0x00 "GICD_ITARGETSR253,Interrupt Processor Targets Register 253"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO1015 ,CPU Targets Byte Offset 1015"
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO1014 ,CPU Targets Byte Offset 1014"
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO1013 ,CPU Targets Byte Offset 1013"
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO1012 ,CPU Targets Byte Offset 1012"
group.long 0xBF8++0x03
line.long 0x00 "GICD_ITARGETSR254,Interrupt Processor Targets Register 254"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO1019 ,CPU Targets Byte Offset 1019"
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO1018 ,CPU Targets Byte Offset 1018"
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO1017 ,CPU Targets Byte Offset 1017"
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO1016 ,CPU Targets Byte Offset 1016"
else
rgroup.long 0xBE0++0x03
line.long 0x00 "GICD_ITARGETSR248,Interrupt Processor Targets Register 248"
rgroup.long 0xBE4++0x03
line.long 0x00 "GICD_ITARGETSR249,Interrupt Processor Targets Register 249"
rgroup.long 0xBE8++0x03
line.long 0x00 "GICD_ITARGETSR250,Interrupt Processor Targets Register 250"
rgroup.long 0xBEC++0x03
line.long 0x00 "GICD_ITARGETSR251,Interrupt Processor Targets Register 251"
rgroup.long 0xBF0++0x03
line.long 0x00 "GICD_ITARGETSR252,Interrupt Processor Targets Register 252"
rgroup.long 0xBF4++0x03
line.long 0x00 "GICD_ITARGETSR253,Interrupt Processor Targets Register 253"
rgroup.long 0xBF8++0x03
line.long 0x00 "GICD_ITARGETSR254,Interrupt Processor Targets Register 254"
endif
else
rgroup.long 0x800++0x03
line.long 0x00 "GICD_ITARGETSR0  ,Interrupt Processor Targets Register 0  "
rgroup.long 0x804++0x03
line.long 0x00 "GICD_ITARGETSR1  ,Interrupt Processor Targets Register 1  "
rgroup.long 0x808++0x03
line.long 0x00 "GICD_ITARGETSR2  ,Interrupt Processor Targets Register 2  "
rgroup.long 0x80C++0x03
line.long 0x00 "GICD_ITARGETSR3  ,Interrupt Processor Targets Register 3  "
rgroup.long 0x810++0x03
line.long 0x00 "GICD_ITARGETSR4  ,Interrupt Processor Targets Register 4  "
rgroup.long 0x814++0x03
line.long 0x00 "GICD_ITARGETSR5  ,Interrupt Processor Targets Register 5  "
rgroup.long 0x818++0x03
line.long 0x00 "GICD_ITARGETSR6  ,Interrupt Processor Targets Register 6  "
rgroup.long 0x81C++0x03
line.long 0x00 "GICD_ITARGETSR7  ,Interrupt Processor Targets Register 7  "
rgroup.long 0x820++0x03
line.long 0x00 "GICD_ITARGETSR8  ,Interrupt Processor Targets Register 8  "
rgroup.long 0x824++0x03
line.long 0x00 "GICD_ITARGETSR9  ,Interrupt Processor Targets Register 9  "
rgroup.long 0x828++0x03
line.long 0x00 "GICD_ITARGETSR10 ,Interrupt Processor Targets Register 10 "
rgroup.long 0x82C++0x03
line.long 0x00 "GICD_ITARGETSR11 ,Interrupt Processor Targets Register 11 "
rgroup.long 0x830++0x03
line.long 0x00 "GICD_ITARGETSR12 ,Interrupt Processor Targets Register 12 "
rgroup.long 0x834++0x03
line.long 0x00 "GICD_ITARGETSR13 ,Interrupt Processor Targets Register 13 "
rgroup.long 0x838++0x03
line.long 0x00 "GICD_ITARGETSR14 ,Interrupt Processor Targets Register 14 "
rgroup.long 0x83C++0x03
line.long 0x00 "GICD_ITARGETSR15 ,Interrupt Processor Targets Register 15 "
rgroup.long 0x840++0x03
line.long 0x00 "GICD_ITARGETSR16 ,Interrupt Processor Targets Register 16 "
rgroup.long 0x844++0x03
line.long 0x00 "GICD_ITARGETSR17 ,Interrupt Processor Targets Register 17 "
rgroup.long 0x848++0x03
line.long 0x00 "GICD_ITARGETSR18 ,Interrupt Processor Targets Register 18 "
rgroup.long 0x84C++0x03
line.long 0x00 "GICD_ITARGETSR19 ,Interrupt Processor Targets Register 19 "
rgroup.long 0x850++0x03
line.long 0x00 "GICD_ITARGETSR20 ,Interrupt Processor Targets Register 20 "
rgroup.long 0x854++0x03
line.long 0x00 "GICD_ITARGETSR21 ,Interrupt Processor Targets Register 21 "
rgroup.long 0x858++0x03
line.long 0x00 "GICD_ITARGETSR22 ,Interrupt Processor Targets Register 22 "
rgroup.long 0x85C++0x03
line.long 0x00 "GICD_ITARGETSR23 ,Interrupt Processor Targets Register 23 "
rgroup.long 0x860++0x03
line.long 0x00 "GICD_ITARGETSR24 ,Interrupt Processor Targets Register 24 "
rgroup.long 0x864++0x03
line.long 0x00 "GICD_ITARGETSR25 ,Interrupt Processor Targets Register 25 "
rgroup.long 0x868++0x03
line.long 0x00 "GICD_ITARGETSR26 ,Interrupt Processor Targets Register 26 "
rgroup.long 0x86C++0x03
line.long 0x00 "GICD_ITARGETSR27 ,Interrupt Processor Targets Register 27 "
rgroup.long 0x870++0x03
line.long 0x00 "GICD_ITARGETSR28 ,Interrupt Processor Targets Register 28 "
rgroup.long 0x874++0x03
line.long 0x00 "GICD_ITARGETSR29 ,Interrupt Processor Targets Register 29 "
rgroup.long 0x878++0x03
line.long 0x00 "GICD_ITARGETSR30 ,Interrupt Processor Targets Register 30 "
rgroup.long 0x87C++0x03
line.long 0x00 "GICD_ITARGETSR31 ,Interrupt Processor Targets Register 31 "
rgroup.long 0x880++0x03
line.long 0x00 "GICD_ITARGETSR32 ,Interrupt Processor Targets Register 32 "
rgroup.long 0x884++0x03
line.long 0x00 "GICD_ITARGETSR33 ,Interrupt Processor Targets Register 33 "
rgroup.long 0x888++0x03
line.long 0x00 "GICD_ITARGETSR34 ,Interrupt Processor Targets Register 34 "
rgroup.long 0x88C++0x03
line.long 0x00 "GICD_ITARGETSR35 ,Interrupt Processor Targets Register 35 "
rgroup.long 0x890++0x03
line.long 0x00 "GICD_ITARGETSR36 ,Interrupt Processor Targets Register 36 "
rgroup.long 0x894++0x03
line.long 0x00 "GICD_ITARGETSR37 ,Interrupt Processor Targets Register 37 "
rgroup.long 0x898++0x03
line.long 0x00 "GICD_ITARGETSR38 ,Interrupt Processor Targets Register 38 "
rgroup.long 0x89C++0x03
line.long 0x00 "GICD_ITARGETSR39 ,Interrupt Processor Targets Register 39 "
rgroup.long 0x8A0++0x03
line.long 0x00 "GICD_ITARGETSR40 ,Interrupt Processor Targets Register 40 "
rgroup.long 0x8A4++0x03
line.long 0x00 "GICD_ITARGETSR41 ,Interrupt Processor Targets Register 41 "
rgroup.long 0x8A8++0x03
line.long 0x00 "GICD_ITARGETSR42 ,Interrupt Processor Targets Register 42 "
rgroup.long 0x8AC++0x03
line.long 0x00 "GICD_ITARGETSR43 ,Interrupt Processor Targets Register 43 "
rgroup.long 0x8B0++0x03
line.long 0x00 "GICD_ITARGETSR44 ,Interrupt Processor Targets Register 44 "
rgroup.long 0x8B4++0x03
line.long 0x00 "GICD_ITARGETSR45 ,Interrupt Processor Targets Register 45 "
rgroup.long 0x8B8++0x03
line.long 0x00 "GICD_ITARGETSR46 ,Interrupt Processor Targets Register 46 "
rgroup.long 0x8BC++0x03
line.long 0x00 "GICD_ITARGETSR47 ,Interrupt Processor Targets Register 47 "
rgroup.long 0x8C0++0x03
line.long 0x00 "GICD_ITARGETSR48 ,Interrupt Processor Targets Register 48 "
rgroup.long 0x8C4++0x03
line.long 0x00 "GICD_ITARGETSR49 ,Interrupt Processor Targets Register 49 "
rgroup.long 0x8C8++0x03
line.long 0x00 "GICD_ITARGETSR50 ,Interrupt Processor Targets Register 50 "
rgroup.long 0x8CC++0x03
line.long 0x00 "GICD_ITARGETSR51 ,Interrupt Processor Targets Register 51 "
rgroup.long 0x8D0++0x03
line.long 0x00 "GICD_ITARGETSR52 ,Interrupt Processor Targets Register 52 "
rgroup.long 0x8D4++0x03
line.long 0x00 "GICD_ITARGETSR53 ,Interrupt Processor Targets Register 53 "
rgroup.long 0x8D8++0x03
line.long 0x00 "GICD_ITARGETSR54 ,Interrupt Processor Targets Register 54 "
rgroup.long 0x8DC++0x03
line.long 0x00 "GICD_ITARGETSR55 ,Interrupt Processor Targets Register 55 "
rgroup.long 0x8E0++0x03
line.long 0x00 "GICD_ITARGETSR56 ,Interrupt Processor Targets Register 56 "
rgroup.long 0x8E4++0x03
line.long 0x00 "GICD_ITARGETSR57 ,Interrupt Processor Targets Register 57 "
rgroup.long 0x8E8++0x03
line.long 0x00 "GICD_ITARGETSR58 ,Interrupt Processor Targets Register 58 "
rgroup.long 0x8EC++0x03
line.long 0x00 "GICD_ITARGETSR59 ,Interrupt Processor Targets Register 59 "
rgroup.long 0x8F0++0x03
line.long 0x00 "GICD_ITARGETSR60 ,Interrupt Processor Targets Register 60 "
rgroup.long 0x8F4++0x03
line.long 0x00 "GICD_ITARGETSR61 ,Interrupt Processor Targets Register 61 "
rgroup.long 0x8F8++0x03
line.long 0x00 "GICD_ITARGETSR62 ,Interrupt Processor Targets Register 62 "
rgroup.long 0x8FC++0x03
line.long 0x00 "GICD_ITARGETSR63 ,Interrupt Processor Targets Register 63 "
rgroup.long 0x900++0x03
line.long 0x00 "GICD_ITARGETSR64 ,Interrupt Processor Targets Register 64 "
rgroup.long 0x904++0x03
line.long 0x00 "GICD_ITARGETSR65 ,Interrupt Processor Targets Register 65 "
rgroup.long 0x908++0x03
line.long 0x00 "GICD_ITARGETSR66 ,Interrupt Processor Targets Register 66 "
rgroup.long 0x90C++0x03
line.long 0x00 "GICD_ITARGETSR67 ,Interrupt Processor Targets Register 67 "
rgroup.long 0x910++0x03
line.long 0x00 "GICD_ITARGETSR68 ,Interrupt Processor Targets Register 68 "
rgroup.long 0x914++0x03
line.long 0x00 "GICD_ITARGETSR69 ,Interrupt Processor Targets Register 69 "
rgroup.long 0x918++0x03
line.long 0x00 "GICD_ITARGETSR70 ,Interrupt Processor Targets Register 70 "
rgroup.long 0x91C++0x03
line.long 0x00 "GICD_ITARGETSR71 ,Interrupt Processor Targets Register 71 "
rgroup.long 0x920++0x03
line.long 0x00 "GICD_ITARGETSR72 ,Interrupt Processor Targets Register 72 "
rgroup.long 0x924++0x03
line.long 0x00 "GICD_ITARGETSR73 ,Interrupt Processor Targets Register 73 "
rgroup.long 0x928++0x03
line.long 0x00 "GICD_ITARGETSR74 ,Interrupt Processor Targets Register 74 "
rgroup.long 0x92C++0x03
line.long 0x00 "GICD_ITARGETSR75 ,Interrupt Processor Targets Register 75 "
rgroup.long 0x930++0x03
line.long 0x00 "GICD_ITARGETSR76 ,Interrupt Processor Targets Register 76 "
rgroup.long 0x934++0x03
line.long 0x00 "GICD_ITARGETSR77 ,Interrupt Processor Targets Register 77 "
rgroup.long 0x938++0x03
line.long 0x00 "GICD_ITARGETSR78 ,Interrupt Processor Targets Register 78 "
rgroup.long 0x93C++0x03
line.long 0x00 "GICD_ITARGETSR79 ,Interrupt Processor Targets Register 79 "
rgroup.long 0x940++0x03
line.long 0x00 "GICD_ITARGETSR80 ,Interrupt Processor Targets Register 80 "
rgroup.long 0x944++0x03
line.long 0x00 "GICD_ITARGETSR81 ,Interrupt Processor Targets Register 81 "
rgroup.long 0x948++0x03
line.long 0x00 "GICD_ITARGETSR82 ,Interrupt Processor Targets Register 82 "
rgroup.long 0x94C++0x03
line.long 0x00 "GICD_ITARGETSR83 ,Interrupt Processor Targets Register 83 "
rgroup.long 0x950++0x03
line.long 0x00 "GICD_ITARGETSR84 ,Interrupt Processor Targets Register 84 "
rgroup.long 0x954++0x03
line.long 0x00 "GICD_ITARGETSR85 ,Interrupt Processor Targets Register 85 "
rgroup.long 0x958++0x03
line.long 0x00 "GICD_ITARGETSR86 ,Interrupt Processor Targets Register 86 "
rgroup.long 0x95C++0x03
line.long 0x00 "GICD_ITARGETSR87 ,Interrupt Processor Targets Register 87 "
rgroup.long 0x960++0x03
line.long 0x00 "GICD_ITARGETSR88 ,Interrupt Processor Targets Register 88 "
rgroup.long 0x964++0x03
line.long 0x00 "GICD_ITARGETSR89 ,Interrupt Processor Targets Register 89 "
rgroup.long 0x968++0x03
line.long 0x00 "GICD_ITARGETSR90 ,Interrupt Processor Targets Register 90 "
rgroup.long 0x96C++0x03
line.long 0x00 "GICD_ITARGETSR91 ,Interrupt Processor Targets Register 91 "
rgroup.long 0x970++0x03
line.long 0x00 "GICD_ITARGETSR92 ,Interrupt Processor Targets Register 92 "
rgroup.long 0x974++0x03
line.long 0x00 "GICD_ITARGETSR93 ,Interrupt Processor Targets Register 93 "
rgroup.long 0x978++0x03
line.long 0x00 "GICD_ITARGETSR94 ,Interrupt Processor Targets Register 94 "
rgroup.long 0x97C++0x03
line.long 0x00 "GICD_ITARGETSR95 ,Interrupt Processor Targets Register 95 "
rgroup.long 0x980++0x03
line.long 0x00 "GICD_ITARGETSR96 ,Interrupt Processor Targets Register 96 "
rgroup.long 0x984++0x03
line.long 0x00 "GICD_ITARGETSR97 ,Interrupt Processor Targets Register 97 "
rgroup.long 0x988++0x03
line.long 0x00 "GICD_ITARGETSR98 ,Interrupt Processor Targets Register 98 "
rgroup.long 0x98C++0x03
line.long 0x00 "GICD_ITARGETSR99 ,Interrupt Processor Targets Register 99 "
rgroup.long 0x990++0x03
line.long 0x00 "GICD_ITARGETSR100,Interrupt Processor Targets Register 100"
rgroup.long 0x994++0x03
line.long 0x00 "GICD_ITARGETSR101,Interrupt Processor Targets Register 101"
rgroup.long 0x998++0x03
line.long 0x00 "GICD_ITARGETSR102,Interrupt Processor Targets Register 102"
rgroup.long 0x99C++0x03
line.long 0x00 "GICD_ITARGETSR103,Interrupt Processor Targets Register 103"
rgroup.long 0x9A0++0x03
line.long 0x00 "GICD_ITARGETSR104,Interrupt Processor Targets Register 104"
rgroup.long 0x9A4++0x03
line.long 0x00 "GICD_ITARGETSR105,Interrupt Processor Targets Register 105"
rgroup.long 0x9A8++0x03
line.long 0x00 "GICD_ITARGETSR106,Interrupt Processor Targets Register 106"
rgroup.long 0x9AC++0x03
line.long 0x00 "GICD_ITARGETSR107,Interrupt Processor Targets Register 107"
rgroup.long 0x9B0++0x03
line.long 0x00 "GICD_ITARGETSR108,Interrupt Processor Targets Register 108"
rgroup.long 0x9B4++0x03
line.long 0x00 "GICD_ITARGETSR109,Interrupt Processor Targets Register 109"
rgroup.long 0x9B8++0x03
line.long 0x00 "GICD_ITARGETSR110,Interrupt Processor Targets Register 110"
rgroup.long 0x9BC++0x03
line.long 0x00 "GICD_ITARGETSR111,Interrupt Processor Targets Register 111"
rgroup.long 0x9C0++0x03
line.long 0x00 "GICD_ITARGETSR112,Interrupt Processor Targets Register 112"
rgroup.long 0x9C4++0x03
line.long 0x00 "GICD_ITARGETSR113,Interrupt Processor Targets Register 113"
rgroup.long 0x9C8++0x03
line.long 0x00 "GICD_ITARGETSR114,Interrupt Processor Targets Register 114"
rgroup.long 0x9CC++0x03
line.long 0x00 "GICD_ITARGETSR115,Interrupt Processor Targets Register 115"
rgroup.long 0x9D0++0x03
line.long 0x00 "GICD_ITARGETSR116,Interrupt Processor Targets Register 116"
rgroup.long 0x9D4++0x03
line.long 0x00 "GICD_ITARGETSR117,Interrupt Processor Targets Register 117"
rgroup.long 0x9D8++0x03
line.long 0x00 "GICD_ITARGETSR118,Interrupt Processor Targets Register 118"
rgroup.long 0x9DC++0x03
line.long 0x00 "GICD_ITARGETSR119,Interrupt Processor Targets Register 119"
rgroup.long 0x9E0++0x03
line.long 0x00 "GICD_ITARGETSR120,Interrupt Processor Targets Register 120"
rgroup.long 0x9E4++0x03
line.long 0x00 "GICD_ITARGETSR121,Interrupt Processor Targets Register 121"
rgroup.long 0x9E8++0x03
line.long 0x00 "GICD_ITARGETSR122,Interrupt Processor Targets Register 122"
rgroup.long 0x9EC++0x03
line.long 0x00 "GICD_ITARGETSR123,Interrupt Processor Targets Register 123"
rgroup.long 0x9F0++0x03
line.long 0x00 "GICD_ITARGETSR124,Interrupt Processor Targets Register 124"
rgroup.long 0x9F4++0x03
line.long 0x00 "GICD_ITARGETSR125,Interrupt Processor Targets Register 125"
rgroup.long 0x9F8++0x03
line.long 0x00 "GICD_ITARGETSR126,Interrupt Processor Targets Register 126"
rgroup.long 0x9FC++0x03
line.long 0x00 "GICD_ITARGETSR127,Interrupt Processor Targets Register 127"
rgroup.long 0xA00++0x03
line.long 0x00 "GICD_ITARGETSR128,Interrupt Processor Targets Register 128"
rgroup.long 0xA04++0x03
line.long 0x00 "GICD_ITARGETSR129,Interrupt Processor Targets Register 129"
rgroup.long 0xA08++0x03
line.long 0x00 "GICD_ITARGETSR130,Interrupt Processor Targets Register 130"
rgroup.long 0xA0C++0x03
line.long 0x00 "GICD_ITARGETSR131,Interrupt Processor Targets Register 131"
rgroup.long 0xA10++0x03
line.long 0x00 "GICD_ITARGETSR132,Interrupt Processor Targets Register 132"
rgroup.long 0xA14++0x03
line.long 0x00 "GICD_ITARGETSR133,Interrupt Processor Targets Register 133"
rgroup.long 0xA18++0x03
line.long 0x00 "GICD_ITARGETSR134,Interrupt Processor Targets Register 134"
rgroup.long 0xA1C++0x03
line.long 0x00 "GICD_ITARGETSR135,Interrupt Processor Targets Register 135"
rgroup.long 0xA20++0x03
line.long 0x00 "GICD_ITARGETSR136,Interrupt Processor Targets Register 136"
rgroup.long 0xA24++0x03
line.long 0x00 "GICD_ITARGETSR137,Interrupt Processor Targets Register 137"
rgroup.long 0xA28++0x03
line.long 0x00 "GICD_ITARGETSR138,Interrupt Processor Targets Register 138"
rgroup.long 0xA2C++0x03
line.long 0x00 "GICD_ITARGETSR139,Interrupt Processor Targets Register 139"
rgroup.long 0xA30++0x03
line.long 0x00 "GICD_ITARGETSR140,Interrupt Processor Targets Register 140"
rgroup.long 0xA34++0x03
line.long 0x00 "GICD_ITARGETSR141,Interrupt Processor Targets Register 141"
rgroup.long 0xA38++0x03
line.long 0x00 "GICD_ITARGETSR142,Interrupt Processor Targets Register 142"
rgroup.long 0xA3C++0x03
line.long 0x00 "GICD_ITARGETSR143,Interrupt Processor Targets Register 143"
rgroup.long 0xA40++0x03
line.long 0x00 "GICD_ITARGETSR144,Interrupt Processor Targets Register 144"
rgroup.long 0xA44++0x03
line.long 0x00 "GICD_ITARGETSR145,Interrupt Processor Targets Register 145"
rgroup.long 0xA48++0x03
line.long 0x00 "GICD_ITARGETSR146,Interrupt Processor Targets Register 146"
rgroup.long 0xA4C++0x03
line.long 0x00 "GICD_ITARGETSR147,Interrupt Processor Targets Register 147"
rgroup.long 0xA50++0x03
line.long 0x00 "GICD_ITARGETSR148,Interrupt Processor Targets Register 148"
rgroup.long 0xA54++0x03
line.long 0x00 "GICD_ITARGETSR149,Interrupt Processor Targets Register 149"
rgroup.long 0xA58++0x03
line.long 0x00 "GICD_ITARGETSR150,Interrupt Processor Targets Register 150"
rgroup.long 0xA5C++0x03
line.long 0x00 "GICD_ITARGETSR151,Interrupt Processor Targets Register 151"
rgroup.long 0xA60++0x03
line.long 0x00 "GICD_ITARGETSR152,Interrupt Processor Targets Register 152"
rgroup.long 0xA64++0x03
line.long 0x00 "GICD_ITARGETSR153,Interrupt Processor Targets Register 153"
rgroup.long 0xA68++0x03
line.long 0x00 "GICD_ITARGETSR154,Interrupt Processor Targets Register 154"
rgroup.long 0xA6C++0x03
line.long 0x00 "GICD_ITARGETSR155,Interrupt Processor Targets Register 155"
rgroup.long 0xA70++0x03
line.long 0x00 "GICD_ITARGETSR156,Interrupt Processor Targets Register 156"
rgroup.long 0xA74++0x03
line.long 0x00 "GICD_ITARGETSR157,Interrupt Processor Targets Register 157"
rgroup.long 0xA78++0x03
line.long 0x00 "GICD_ITARGETSR158,Interrupt Processor Targets Register 158"
rgroup.long 0xA7C++0x03
line.long 0x00 "GICD_ITARGETSR159,Interrupt Processor Targets Register 159"
rgroup.long 0xA80++0x03
line.long 0x00 "GICD_ITARGETSR160,Interrupt Processor Targets Register 160"
rgroup.long 0xA84++0x03
line.long 0x00 "GICD_ITARGETSR161,Interrupt Processor Targets Register 161"
rgroup.long 0xA88++0x03
line.long 0x00 "GICD_ITARGETSR162,Interrupt Processor Targets Register 162"
rgroup.long 0xA8C++0x03
line.long 0x00 "GICD_ITARGETSR163,Interrupt Processor Targets Register 163"
rgroup.long 0xA90++0x03
line.long 0x00 "GICD_ITARGETSR164,Interrupt Processor Targets Register 164"
rgroup.long 0xA94++0x03
line.long 0x00 "GICD_ITARGETSR165,Interrupt Processor Targets Register 165"
rgroup.long 0xA98++0x03
line.long 0x00 "GICD_ITARGETSR166,Interrupt Processor Targets Register 166"
rgroup.long 0xA9C++0x03
line.long 0x00 "GICD_ITARGETSR167,Interrupt Processor Targets Register 167"
rgroup.long 0xAA0++0x03
line.long 0x00 "GICD_ITARGETSR168,Interrupt Processor Targets Register 168"
rgroup.long 0xAA4++0x03
line.long 0x00 "GICD_ITARGETSR169,Interrupt Processor Targets Register 169"
rgroup.long 0xAA8++0x03
line.long 0x00 "GICD_ITARGETSR170,Interrupt Processor Targets Register 170"
rgroup.long 0xAAC++0x03
line.long 0x00 "GICD_ITARGETSR171,Interrupt Processor Targets Register 171"
rgroup.long 0xAB0++0x03
line.long 0x00 "GICD_ITARGETSR172,Interrupt Processor Targets Register 172"
rgroup.long 0xAB4++0x03
line.long 0x00 "GICD_ITARGETSR173,Interrupt Processor Targets Register 173"
rgroup.long 0xAB8++0x03
line.long 0x00 "GICD_ITARGETSR174,Interrupt Processor Targets Register 174"
rgroup.long 0xABC++0x03
line.long 0x00 "GICD_ITARGETSR175,Interrupt Processor Targets Register 175"
rgroup.long 0xAC0++0x03
line.long 0x00 "GICD_ITARGETSR176,Interrupt Processor Targets Register 176"
rgroup.long 0xAC4++0x03
line.long 0x00 "GICD_ITARGETSR177,Interrupt Processor Targets Register 177"
rgroup.long 0xAC8++0x03
line.long 0x00 "GICD_ITARGETSR178,Interrupt Processor Targets Register 178"
rgroup.long 0xACC++0x03
line.long 0x00 "GICD_ITARGETSR179,Interrupt Processor Targets Register 179"
rgroup.long 0xAD0++0x03
line.long 0x00 "GICD_ITARGETSR180,Interrupt Processor Targets Register 180"
rgroup.long 0xAD4++0x03
line.long 0x00 "GICD_ITARGETSR181,Interrupt Processor Targets Register 181"
rgroup.long 0xAD8++0x03
line.long 0x00 "GICD_ITARGETSR182,Interrupt Processor Targets Register 182"
rgroup.long 0xADC++0x03
line.long 0x00 "GICD_ITARGETSR183,Interrupt Processor Targets Register 183"
rgroup.long 0xAE0++0x03
line.long 0x00 "GICD_ITARGETSR184,Interrupt Processor Targets Register 184"
rgroup.long 0xAE4++0x03
line.long 0x00 "GICD_ITARGETSR185,Interrupt Processor Targets Register 185"
rgroup.long 0xAE8++0x03
line.long 0x00 "GICD_ITARGETSR186,Interrupt Processor Targets Register 186"
rgroup.long 0xAEC++0x03
line.long 0x00 "GICD_ITARGETSR187,Interrupt Processor Targets Register 187"
rgroup.long 0xAF0++0x03
line.long 0x00 "GICD_ITARGETSR188,Interrupt Processor Targets Register 188"
rgroup.long 0xAF4++0x03
line.long 0x00 "GICD_ITARGETSR189,Interrupt Processor Targets Register 189"
rgroup.long 0xAF8++0x03
line.long 0x00 "GICD_ITARGETSR190,Interrupt Processor Targets Register 190"
rgroup.long 0xAFC++0x03
line.long 0x00 "GICD_ITARGETSR191,Interrupt Processor Targets Register 191"
rgroup.long 0xB00++0x03
line.long 0x00 "GICD_ITARGETSR192,Interrupt Processor Targets Register 192"
rgroup.long 0xB04++0x03
line.long 0x00 "GICD_ITARGETSR193,Interrupt Processor Targets Register 193"
rgroup.long 0xB08++0x03
line.long 0x00 "GICD_ITARGETSR194,Interrupt Processor Targets Register 194"
rgroup.long 0xB0C++0x03
line.long 0x00 "GICD_ITARGETSR195,Interrupt Processor Targets Register 195"
rgroup.long 0xB10++0x03
line.long 0x00 "GICD_ITARGETSR196,Interrupt Processor Targets Register 196"
rgroup.long 0xB14++0x03
line.long 0x00 "GICD_ITARGETSR197,Interrupt Processor Targets Register 197"
rgroup.long 0xB18++0x03
line.long 0x00 "GICD_ITARGETSR198,Interrupt Processor Targets Register 198"
rgroup.long 0xB1C++0x03
line.long 0x00 "GICD_ITARGETSR199,Interrupt Processor Targets Register 199"
rgroup.long 0xB20++0x03
line.long 0x00 "GICD_ITARGETSR200,Interrupt Processor Targets Register 200"
rgroup.long 0xB24++0x03
line.long 0x00 "GICD_ITARGETSR201,Interrupt Processor Targets Register 201"
rgroup.long 0xB28++0x03
line.long 0x00 "GICD_ITARGETSR202,Interrupt Processor Targets Register 202"
rgroup.long 0xB2C++0x03
line.long 0x00 "GICD_ITARGETSR203,Interrupt Processor Targets Register 203"
rgroup.long 0xB30++0x03
line.long 0x00 "GICD_ITARGETSR204,Interrupt Processor Targets Register 204"
rgroup.long 0xB34++0x03
line.long 0x00 "GICD_ITARGETSR205,Interrupt Processor Targets Register 205"
rgroup.long 0xB38++0x03
line.long 0x00 "GICD_ITARGETSR206,Interrupt Processor Targets Register 206"
rgroup.long 0xB3C++0x03
line.long 0x00 "GICD_ITARGETSR207,Interrupt Processor Targets Register 207"
rgroup.long 0xB40++0x03
line.long 0x00 "GICD_ITARGETSR208,Interrupt Processor Targets Register 208"
rgroup.long 0xB44++0x03
line.long 0x00 "GICD_ITARGETSR209,Interrupt Processor Targets Register 209"
rgroup.long 0xB48++0x03
line.long 0x00 "GICD_ITARGETSR210,Interrupt Processor Targets Register 210"
rgroup.long 0xB4C++0x03
line.long 0x00 "GICD_ITARGETSR211,Interrupt Processor Targets Register 211"
rgroup.long 0xB50++0x03
line.long 0x00 "GICD_ITARGETSR212,Interrupt Processor Targets Register 212"
rgroup.long 0xB54++0x03
line.long 0x00 "GICD_ITARGETSR213,Interrupt Processor Targets Register 213"
rgroup.long 0xB58++0x03
line.long 0x00 "GICD_ITARGETSR214,Interrupt Processor Targets Register 214"
rgroup.long 0xB5C++0x03
line.long 0x00 "GICD_ITARGETSR215,Interrupt Processor Targets Register 215"
rgroup.long 0xB60++0x03
line.long 0x00 "GICD_ITARGETSR216,Interrupt Processor Targets Register 216"
rgroup.long 0xB64++0x03
line.long 0x00 "GICD_ITARGETSR217,Interrupt Processor Targets Register 217"
rgroup.long 0xB68++0x03
line.long 0x00 "GICD_ITARGETSR218,Interrupt Processor Targets Register 218"
rgroup.long 0xB6C++0x03
line.long 0x00 "GICD_ITARGETSR219,Interrupt Processor Targets Register 219"
rgroup.long 0xB70++0x03
line.long 0x00 "GICD_ITARGETSR220,Interrupt Processor Targets Register 220"
rgroup.long 0xB74++0x03
line.long 0x00 "GICD_ITARGETSR221,Interrupt Processor Targets Register 221"
rgroup.long 0xB78++0x03
line.long 0x00 "GICD_ITARGETSR222,Interrupt Processor Targets Register 222"
rgroup.long 0xB7C++0x03
line.long 0x00 "GICD_ITARGETSR223,Interrupt Processor Targets Register 223"
rgroup.long 0xB80++0x03
line.long 0x00 "GICD_ITARGETSR224,Interrupt Processor Targets Register 224"
rgroup.long 0xB84++0x03
line.long 0x00 "GICD_ITARGETSR225,Interrupt Processor Targets Register 225"
rgroup.long 0xB88++0x03
line.long 0x00 "GICD_ITARGETSR226,Interrupt Processor Targets Register 226"
rgroup.long 0xB8C++0x03
line.long 0x00 "GICD_ITARGETSR227,Interrupt Processor Targets Register 227"
rgroup.long 0xB90++0x03
line.long 0x00 "GICD_ITARGETSR228,Interrupt Processor Targets Register 228"
rgroup.long 0xB94++0x03
line.long 0x00 "GICD_ITARGETSR229,Interrupt Processor Targets Register 229"
rgroup.long 0xB98++0x03
line.long 0x00 "GICD_ITARGETSR230,Interrupt Processor Targets Register 230"
rgroup.long 0xB9C++0x03
line.long 0x00 "GICD_ITARGETSR231,Interrupt Processor Targets Register 231"
rgroup.long 0xBA0++0x03
line.long 0x00 "GICD_ITARGETSR232,Interrupt Processor Targets Register 232"
rgroup.long 0xBA4++0x03
line.long 0x00 "GICD_ITARGETSR233,Interrupt Processor Targets Register 233"
rgroup.long 0xBA8++0x03
line.long 0x00 "GICD_ITARGETSR234,Interrupt Processor Targets Register 234"
rgroup.long 0xBAC++0x03
line.long 0x00 "GICD_ITARGETSR235,Interrupt Processor Targets Register 235"
rgroup.long 0xBB0++0x03
line.long 0x00 "GICD_ITARGETSR236,Interrupt Processor Targets Register 236"
rgroup.long 0xBB4++0x03
line.long 0x00 "GICD_ITARGETSR237,Interrupt Processor Targets Register 237"
rgroup.long 0xBB8++0x03
line.long 0x00 "GICD_ITARGETSR238,Interrupt Processor Targets Register 238"
rgroup.long 0xBBC++0x03
line.long 0x00 "GICD_ITARGETSR239,Interrupt Processor Targets Register 239"
rgroup.long 0xBC0++0x03
line.long 0x00 "GICD_ITARGETSR240,Interrupt Processor Targets Register 240"
rgroup.long 0xBC4++0x03
line.long 0x00 "GICD_ITARGETSR241,Interrupt Processor Targets Register 241"
rgroup.long 0xBC8++0x03
line.long 0x00 "GICD_ITARGETSR242,Interrupt Processor Targets Register 242"
rgroup.long 0xBCC++0x03
line.long 0x00 "GICD_ITARGETSR243,Interrupt Processor Targets Register 243"
rgroup.long 0xBD0++0x03
line.long 0x00 "GICD_ITARGETSR244,Interrupt Processor Targets Register 244"
rgroup.long 0xBD4++0x03
line.long 0x00 "GICD_ITARGETSR245,Interrupt Processor Targets Register 245"
rgroup.long 0xBD8++0x03
line.long 0x00 "GICD_ITARGETSR246,Interrupt Processor Targets Register 246"
rgroup.long 0xBDC++0x03
line.long 0x00 "GICD_ITARGETSR247,Interrupt Processor Targets Register 247"
rgroup.long 0xBE0++0x03
line.long 0x00 "GICD_ITARGETSR248,Interrupt Processor Targets Register 248"
rgroup.long 0xBE4++0x03
line.long 0x00 "GICD_ITARGETSR249,Interrupt Processor Targets Register 249"
rgroup.long 0xBE8++0x03
line.long 0x00 "GICD_ITARGETSR250,Interrupt Processor Targets Register 250"
rgroup.long 0xBEC++0x03
line.long 0x00 "GICD_ITARGETSR251,Interrupt Processor Targets Register 251"
rgroup.long 0xBF0++0x03
line.long 0x00 "GICD_ITARGETSR252,Interrupt Processor Targets Register 252"
rgroup.long 0xBF4++0x03
line.long 0x00 "GICD_ITARGETSR253,Interrupt Processor Targets Register 253"
rgroup.long 0xBF8++0x03
line.long 0x00 "GICD_ITARGETSR254,Interrupt Processor Targets Register 254"
endif
tree.end
width 14.
tree "Configuration Registers"
rgroup.long 0xC00++0x03
line.long 0x00 "GICD_ICFGR0,Interrupt Configuration Register"
textline "                       "
rgroup.long 0xC04++0x03
line.long 0x00 "GICD_ICFGR1,Interrupt Configuration Register"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1)
group.long 0xC08++0x03
line.long 0x00 "GICD_ICFGR2,Interrupt Configuration Register 2"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
group.long 0xC0C++0x03
line.long 0x00 "GICD_ICFGR3,Interrupt Configuration Register 3"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
else
rgroup.long 0xC08++0x03
line.long 0x00 "GICD_ICFGR2,Interrupt Configuration Register 2"
rgroup.long 0xC0C++0x03
line.long 0x00 "GICD_ICFGR3,Interrupt Configuration Register 3"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x2)
group.long 0xC10++0x03
line.long 0x00 "GICD_ICFGR4,Interrupt Configuration Register 4"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
group.long 0xC14++0x03
line.long 0x00 "GICD_ICFGR5,Interrupt Configuration Register 5"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
else
rgroup.long 0xC10++0x03
line.long 0x00 "GICD_ICFGR4,Interrupt Configuration Register 4"
rgroup.long 0xC14++0x03
line.long 0x00 "GICD_ICFGR5,Interrupt Configuration Register 5"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x3)
group.long 0xC18++0x03
line.long 0x00 "GICD_ICFGR6,Interrupt Configuration Register 6"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
group.long 0xC1C++0x03
line.long 0x00 "GICD_ICFGR7,Interrupt Configuration Register 7"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
else
rgroup.long 0xC18++0x03
line.long 0x00 "GICD_ICFGR6,Interrupt Configuration Register 6"
rgroup.long 0xC1C++0x03
line.long 0x00 "GICD_ICFGR7,Interrupt Configuration Register 7"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x4)
group.long 0xC20++0x03
line.long 0x00 "GICD_ICFGR8,Interrupt Configuration Register 8"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
group.long 0xC24++0x03
line.long 0x00 "GICD_ICFGR9,Interrupt Configuration Register 9"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
else
rgroup.long 0xC20++0x03
line.long 0x00 "GICD_ICFGR8,Interrupt Configuration Register 8"
rgroup.long 0xC24++0x03
line.long 0x00 "GICD_ICFGR9,Interrupt Configuration Register 9"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x5)
group.long 0xC28++0x03
line.long 0x00 "GICD_ICFGR10,Interrupt Configuration Register 10"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
group.long 0xC2C++0x03
line.long 0x00 "GICD_ICFGR11,Interrupt Configuration Register 11"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
else
rgroup.long 0xC28++0x03
line.long 0x00 "GICD_ICFGR10,Interrupt Configuration Register 10"
rgroup.long 0xC2C++0x03
line.long 0x00 "GICD_ICFGR11,Interrupt Configuration Register 11"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x6)
group.long 0xC30++0x03
line.long 0x00 "GICD_ICFGR12,Interrupt Configuration Register 12"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
group.long 0xC34++0x03
line.long 0x00 "GICD_ICFGR13,Interrupt Configuration Register 13"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
else
rgroup.long 0xC30++0x03
line.long 0x00 "GICD_ICFGR12,Interrupt Configuration Register 12"
rgroup.long 0xC34++0x03
line.long 0x00 "GICD_ICFGR13,Interrupt Configuration Register 13"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x7)
group.long 0xC38++0x03
line.long 0x00 "GICD_ICFGR14,Interrupt Configuration Register 14"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
group.long 0xC3C++0x03
line.long 0x00 "GICD_ICFGR15,Interrupt Configuration Register 15"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
else
rgroup.long 0xC38++0x03
line.long 0x00 "GICD_ICFGR14,Interrupt Configuration Register 14"
rgroup.long 0xC3C++0x03
line.long 0x00 "GICD_ICFGR15,Interrupt Configuration Register 15"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x8)
group.long 0xC40++0x03
line.long 0x00 "GICD_ICFGR16,Interrupt Configuration Register 16"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
group.long 0xC44++0x03
line.long 0x00 "GICD_ICFGR17,Interrupt Configuration Register 17"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
else
rgroup.long 0xC40++0x03
line.long 0x00 "GICD_ICFGR16,Interrupt Configuration Register 16"
rgroup.long 0xC44++0x03
line.long 0x00 "GICD_ICFGR17,Interrupt Configuration Register 17"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x9)
group.long 0xC48++0x03
line.long 0x00 "GICD_ICFGR18,Interrupt Configuration Register 18"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
group.long 0xC4C++0x03
line.long 0x00 "GICD_ICFGR19,Interrupt Configuration Register 19"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
else
rgroup.long 0xC48++0x03
line.long 0x00 "GICD_ICFGR18,Interrupt Configuration Register 18"
rgroup.long 0xC4C++0x03
line.long 0x00 "GICD_ICFGR19,Interrupt Configuration Register 19"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0xA)
group.long 0xC50++0x03
line.long 0x00 "GICD_ICFGR20,Interrupt Configuration Register 20"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
group.long 0xC54++0x03
line.long 0x00 "GICD_ICFGR21,Interrupt Configuration Register 21"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
else
rgroup.long 0xC50++0x03
line.long 0x00 "GICD_ICFGR20,Interrupt Configuration Register 20"
rgroup.long 0xC54++0x03
line.long 0x00 "GICD_ICFGR21,Interrupt Configuration Register 21"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0xB)
group.long 0xC58++0x03
line.long 0x00 "GICD_ICFGR22,Interrupt Configuration Register 22"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
group.long 0xC5C++0x03
line.long 0x00 "GICD_ICFGR23,Interrupt Configuration Register 23"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
else
rgroup.long 0xC58++0x03
line.long 0x00 "GICD_ICFGR22,Interrupt Configuration Register 22"
rgroup.long 0xC5C++0x03
line.long 0x00 "GICD_ICFGR23,Interrupt Configuration Register 23"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0xC)
group.long 0xC60++0x03
line.long 0x00 "GICD_ICFGR24,Interrupt Configuration Register 24"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
group.long 0xC64++0x03
line.long 0x00 "GICD_ICFGR25,Interrupt Configuration Register 25"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
else
rgroup.long 0xC60++0x03
line.long 0x00 "GICD_ICFGR24,Interrupt Configuration Register 24"
rgroup.long 0xC64++0x03
line.long 0x00 "GICD_ICFGR25,Interrupt Configuration Register 25"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0xD)
group.long 0xC68++0x03
line.long 0x00 "GICD_ICFGR26,Interrupt Configuration Register 26"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
group.long 0xC6C++0x03
line.long 0x00 "GICD_ICFGR27,Interrupt Configuration Register 27"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
else
rgroup.long 0xC68++0x03
line.long 0x00 "GICD_ICFGR26,Interrupt Configuration Register 26"
rgroup.long 0xC6C++0x03
line.long 0x00 "GICD_ICFGR27,Interrupt Configuration Register 27"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0xE)
group.long 0xC70++0x03
line.long 0x00 "GICD_ICFGR28,Interrupt Configuration Register 28"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
group.long 0xC74++0x03
line.long 0x00 "GICD_ICFGR29,Interrupt Configuration Register 29"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
else
rgroup.long 0xC70++0x03
line.long 0x00 "GICD_ICFGR28,Interrupt Configuration Register 28"
rgroup.long 0xC74++0x03
line.long 0x00 "GICD_ICFGR29,Interrupt Configuration Register 29"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0xF)
group.long 0xC78++0x03
line.long 0x00 "GICD_ICFGR30,Interrupt Configuration Register 30"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
group.long 0xC7C++0x03
line.long 0x00 "GICD_ICFGR31,Interrupt Configuration Register 31"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
else
rgroup.long 0xC78++0x03
line.long 0x00 "GICD_ICFGR30,Interrupt Configuration Register 30"
rgroup.long 0xC7C++0x03
line.long 0x00 "GICD_ICFGR31,Interrupt Configuration Register 31"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x10)
group.long 0xC80++0x03
line.long 0x00 "GICD_ICFGR32,Interrupt Configuration Register 32"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
group.long 0xC84++0x03
line.long 0x00 "GICD_ICFGR33,Interrupt Configuration Register 33"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
else
rgroup.long 0xC80++0x03
line.long 0x00 "GICD_ICFGR32,Interrupt Configuration Register 32"
rgroup.long 0xC84++0x03
line.long 0x00 "GICD_ICFGR33,Interrupt Configuration Register 33"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x11)
group.long 0xC88++0x03
line.long 0x00 "GICD_ICFGR34,Interrupt Configuration Register 34"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
group.long 0xC8C++0x03
line.long 0x00 "GICD_ICFGR35,Interrupt Configuration Register 35"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
else
rgroup.long 0xC88++0x03
line.long 0x00 "GICD_ICFGR34,Interrupt Configuration Register 34"
rgroup.long 0xC8C++0x03
line.long 0x00 "GICD_ICFGR35,Interrupt Configuration Register 35"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x12)
group.long 0xC90++0x03
line.long 0x00 "GICD_ICFGR36,Interrupt Configuration Register 36"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
group.long 0xC94++0x03
line.long 0x00 "GICD_ICFGR37,Interrupt Configuration Register 37"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
else
rgroup.long 0xC90++0x03
line.long 0x00 "GICD_ICFGR36,Interrupt Configuration Register 36"
rgroup.long 0xC94++0x03
line.long 0x00 "GICD_ICFGR37,Interrupt Configuration Register 37"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x13)
group.long 0xC98++0x03
line.long 0x00 "GICD_ICFGR38,Interrupt Configuration Register 38"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
group.long 0xC9C++0x03
line.long 0x00 "GICD_ICFGR39,Interrupt Configuration Register 39"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
else
rgroup.long 0xC98++0x03
line.long 0x00 "GICD_ICFGR38,Interrupt Configuration Register 38"
rgroup.long 0xC9C++0x03
line.long 0x00 "GICD_ICFGR39,Interrupt Configuration Register 39"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x14)
group.long 0xCA0++0x03
line.long 0x00 "GICD_ICFGR40,Interrupt Configuration Register 40"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
group.long 0xCA4++0x03
line.long 0x00 "GICD_ICFGR41,Interrupt Configuration Register 41"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
else
rgroup.long 0xCA0++0x03
line.long 0x00 "GICD_ICFGR40,Interrupt Configuration Register 40"
rgroup.long 0xCA4++0x03
line.long 0x00 "GICD_ICFGR41,Interrupt Configuration Register 41"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x15)
group.long 0xCA8++0x03
line.long 0x00 "GICD_ICFGR42,Interrupt Configuration Register 42"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
group.long 0xCAC++0x03
line.long 0x00 "GICD_ICFGR43,Interrupt Configuration Register 43"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
else
rgroup.long 0xCA8++0x03
line.long 0x00 "GICD_ICFGR42,Interrupt Configuration Register 42"
rgroup.long 0xCAC++0x03
line.long 0x00 "GICD_ICFGR43,Interrupt Configuration Register 43"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x16)
group.long 0xCB0++0x03
line.long 0x00 "GICD_ICFGR44,Interrupt Configuration Register 44"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
group.long 0xCB4++0x03
line.long 0x00 "GICD_ICFGR45,Interrupt Configuration Register 45"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
else
rgroup.long 0xCB0++0x03
line.long 0x00 "GICD_ICFGR44,Interrupt Configuration Register 44"
rgroup.long 0xCB4++0x03
line.long 0x00 "GICD_ICFGR45,Interrupt Configuration Register 45"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x17)
group.long 0xCB8++0x03
line.long 0x00 "GICD_ICFGR46,Interrupt Configuration Register 46"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
group.long 0xCBC++0x03
line.long 0x00 "GICD_ICFGR47,Interrupt Configuration Register 47"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
else
rgroup.long 0xCB8++0x03
line.long 0x00 "GICD_ICFGR46,Interrupt Configuration Register 46"
rgroup.long 0xCBC++0x03
line.long 0x00 "GICD_ICFGR47,Interrupt Configuration Register 47"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x18)
group.long 0xCC0++0x03
line.long 0x00 "GICD_ICFGR48,Interrupt Configuration Register 48"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
group.long 0xCC4++0x03
line.long 0x00 "GICD_ICFGR49,Interrupt Configuration Register 49"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
else
rgroup.long 0xCC0++0x03
line.long 0x00 "GICD_ICFGR48,Interrupt Configuration Register 48"
rgroup.long 0xCC4++0x03
line.long 0x00 "GICD_ICFGR49,Interrupt Configuration Register 49"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x19)
group.long 0xCC8++0x03
line.long 0x00 "GICD_ICFGR50,Interrupt Configuration Register 50"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
group.long 0xCCC++0x03
line.long 0x00 "GICD_ICFGR51,Interrupt Configuration Register 51"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
else
rgroup.long 0xCC8++0x03
line.long 0x00 "GICD_ICFGR50,Interrupt Configuration Register 50"
rgroup.long 0xCCC++0x03
line.long 0x00 "GICD_ICFGR51,Interrupt Configuration Register 51"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1A)
group.long 0xCD0++0x03
line.long 0x00 "GICD_ICFGR52,Interrupt Configuration Register 52"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
group.long 0xCD4++0x03
line.long 0x00 "GICD_ICFGR53,Interrupt Configuration Register 53"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
else
rgroup.long 0xCD0++0x03
line.long 0x00 "GICD_ICFGR52,Interrupt Configuration Register 52"
rgroup.long 0xCD4++0x03
line.long 0x00 "GICD_ICFGR53,Interrupt Configuration Register 53"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1B)
group.long 0xCD8++0x03
line.long 0x00 "GICD_ICFGR54,Interrupt Configuration Register 54"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
group.long 0xCDC++0x03
line.long 0x00 "GICD_ICFGR55,Interrupt Configuration Register 55"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
else
rgroup.long 0xCD8++0x03
line.long 0x00 "GICD_ICFGR54,Interrupt Configuration Register 54"
rgroup.long 0xCDC++0x03
line.long 0x00 "GICD_ICFGR55,Interrupt Configuration Register 55"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1C)
group.long 0xCE0++0x03
line.long 0x00 "GICD_ICFGR56,Interrupt Configuration Register 56"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
group.long 0xCE4++0x03
line.long 0x00 "GICD_ICFGR57,Interrupt Configuration Register 57"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
else
rgroup.long 0xCE0++0x03
line.long 0x00 "GICD_ICFGR56,Interrupt Configuration Register 56"
rgroup.long 0xCE4++0x03
line.long 0x00 "GICD_ICFGR57,Interrupt Configuration Register 57"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1D)
group.long 0xCE8++0x03
line.long 0x00 "GICD_ICFGR58,Interrupt Configuration Register 58"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
group.long 0xCEC++0x03
line.long 0x00 "GICD_ICFGR59,Interrupt Configuration Register 59"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
else
rgroup.long 0xCE8++0x03
line.long 0x00 "GICD_ICFGR58,Interrupt Configuration Register 58"
rgroup.long 0xCEC++0x03
line.long 0x00 "GICD_ICFGR59,Interrupt Configuration Register 59"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1E)
group.long 0xCF0++0x03
line.long 0x00 "GICD_ICFGR60,Interrupt Configuration Register 60"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
group.long 0xCF4++0x03
line.long 0x00 "GICD_ICFGR61,Interrupt Configuration Register 61"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
else
rgroup.long 0xCF0++0x03
line.long 0x00 "GICD_ICFGR60,Interrupt Configuration Register 60"
rgroup.long 0xCF4++0x03
line.long 0x00 "GICD_ICFGR61,Interrupt Configuration Register 61"
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1F)
group.long 0xCF8++0x03
line.long 0x00 "GICD_ICFGR62,Interrupt Configuration Register 62"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
group.long 0xCFC++0x03
line.long 0x00 "GICD_ICFGR63,Interrupt Configuration Register 63"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
else
rgroup.long 0xCF8++0x03
line.long 0x00 "GICD_ICFGR62,Interrupt Configuration Register 62"
rgroup.long 0xCFC++0x03
line.long 0x00 "GICD_ICFGR63,Interrupt Configuration Register 63"
endif
tree.end
width 12.
tree "Peripheral Interrupt Status Registers"
rgroup.long 0x0D00++0x03
line.long 0x00 "GICD_PPISR,Private Peripheral Interrupt Status Register"
bitfld.long 0x00 15. " PPI3S     ,nIRQ pin status" "No interrupt,Interrupt"
bitfld.long 0x00 14. "  PPI2S     ,Non-secure Physical Timer event status" "No interrupt,Interrupt"
textline "                     "
bitfld.long 0x00 13. " PPI1S     ,Secure Physical Timer event status" "No interrupt,Interrupt"
bitfld.long 0x00 12. "  PPI0S     ,nFIQ pin status" "No interrupt,Interrupt"
textline "                     "
bitfld.long 0x00 11. " PPI4S     ,Virtual Timer event status" "No interrupt,Interrupt"
bitfld.long 0x00 10. "  PPI5S     ,Hypervisor Timer event status" "No interrupt,Interrupt"
textline "                     "
bitfld.long 0x00 9. " PPI6S     ,Virtual Maintenance Status" "No interrupt,Interrupt"
textline "                               "
width 22.
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x01)
rgroup.long 0x0D04++0x03
line.long 0x0 "GICD_SPISR0,Shared Peripheral Interrupt Status Register 0"
bitfld.long 0x00 31. " IRQS31  ,IRQS Status Bit 31" "Low,High"
bitfld.long 0x00 30. "  IRQS30  ,IRQS Status Bit 30" "Low,High"
bitfld.long 0x00 29. "  IRQS29  ,IRQS Status Bit 29" "Low,High"
textline "                               "
bitfld.long 0x00 28. " IRQS28  ,IRQS Status Bit 28" "Low,High"
bitfld.long 0x00 27. "  IRQS27  ,IRQS Status Bit 27" "Low,High"
bitfld.long 0x00 26. "  IRQS26  ,IRQS Status Bit 26" "Low,High"
textline "                               "
bitfld.long 0x00 25. " IRQS25  ,IRQS Status Bit 25" "Low,High"
bitfld.long 0x00 24. "  IRQS24  ,IRQS Status Bit 24" "Low,High"
bitfld.long 0x00 23. "  IRQS23  ,IRQS Status Bit 23" "Low,High"
textline "                               "
bitfld.long 0x00 22. " IRQS22  ,IRQS Status Bit 22" "Low,High"
bitfld.long 0x00 21. "  IRQS21  ,IRQS Status Bit 21" "Low,High"
bitfld.long 0x00 20. "  IRQS20  ,IRQS Status Bit 20" "Low,High"
textline "                               "
bitfld.long 0x00 19. " IRQS19  ,IRQS Status Bit 19" "Low,High"
bitfld.long 0x00 18. "  IRQS18  ,IRQS Status Bit 18" "Low,High"
bitfld.long 0x00 17. "  IRQS17  ,IRQS Status Bit 17" "Low,High"
textline "                               "
bitfld.long 0x00 16. " IRQS16  ,IRQS Status Bit 16" "Low,High"
bitfld.long 0x00 15. "  IRQS15  ,IRQS Status Bit 15" "Low,High"
bitfld.long 0x00 14. "  IRQS14  ,IRQS Status Bit 14" "Low,High"
textline "                               "
bitfld.long 0x00 13. " IRQS13  ,IRQS Status Bit 13" "Low,High"
bitfld.long 0x00 12. "  IRQS12  ,IRQS Status Bit 12" "Low,High"
bitfld.long 0x00 11. "  IRQS11  ,IRQS Status Bit 11" "Low,High"
textline "                               "
bitfld.long 0x00 10. " IRQS10  ,IRQS Status Bit 10" "Low,High"
bitfld.long 0x00 9. "  IRQS9   ,IRQS Status Bit 9" "Low,High"
bitfld.long 0x00 8. "  IRQS8   ,IRQS Status Bit 8" "Low,High"
textline "                               "
bitfld.long 0x00 7. " IRQS7   ,IRQS Status Bit 7" "Low,High"
bitfld.long 0x00 6. "  IRQS6   ,IRQS Status Bit 6" "Low,High"
bitfld.long 0x00 5. "  IRQS5   ,IRQS Status Bit 5" "Low,High"
textline "                               "
bitfld.long 0x00 4. " IRQS4   ,IRQS Status Bit 4" "Low,High"
bitfld.long 0x00 3. "  IRQS3   ,IRQS Status Bit 3" "Low,High"
bitfld.long 0x00 2. "  IRQS2   ,IRQS Status Bit 2" "Low,High"
textline "                               "
bitfld.long 0x00 1. " IRQS1   ,IRQS Status Bit 1" "Low,High"
bitfld.long 0x00 0. "  IRQS0   ,IRQS Status Bit 0" "Low,High"
else
rgroup.long 0x0D04++0x03
line.long 0x0 "GICD_SPISR0,Shared Peripheral Interrupt Status Register 1"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x02)
rgroup.long 0x0D08++0x03
line.long 0x0 "GICD_SPISR1,Shared Peripheral Interrupt Status Register 1"
bitfld.long 0x00 31. " IRQS63  ,IRQS Status Bit 63" "Low,High"
bitfld.long 0x00 30. "  IRQS62  ,IRQS Status Bit 62" "Low,High"
bitfld.long 0x00 29. "  IRQS61  ,IRQS Status Bit 61" "Low,High"
textline "                               "
bitfld.long 0x00 28. " IRQS60  ,IRQS Status Bit 60" "Low,High"
bitfld.long 0x00 27. "  IRQS59  ,IRQS Status Bit 59" "Low,High"
bitfld.long 0x00 26. "  IRQS58  ,IRQS Status Bit 58" "Low,High"
textline "                               "
bitfld.long 0x00 25. " IRQS57  ,IRQS Status Bit 57" "Low,High"
bitfld.long 0x00 24. "  IRQS56  ,IRQS Status Bit 56" "Low,High"
bitfld.long 0x00 23. "  IRQS55  ,IRQS Status Bit 55" "Low,High"
textline "                               "
bitfld.long 0x00 22. " IRQS54  ,IRQS Status Bit 54" "Low,High"
bitfld.long 0x00 21. "  IRQS53  ,IRQS Status Bit 53" "Low,High"
bitfld.long 0x00 20. "  IRQS52  ,IRQS Status Bit 52" "Low,High"
textline "                               "
bitfld.long 0x00 19. " IRQS51  ,IRQS Status Bit 51" "Low,High"
bitfld.long 0x00 18. "  IRQS50  ,IRQS Status Bit 50" "Low,High"
bitfld.long 0x00 17. "  IRQS49  ,IRQS Status Bit 49" "Low,High"
textline "                               "
bitfld.long 0x00 16. " IRQS48  ,IRQS Status Bit 48" "Low,High"
bitfld.long 0x00 15. "  IRQS47  ,IRQS Status Bit 47" "Low,High"
bitfld.long 0x00 14. "  IRQS46  ,IRQS Status Bit 46" "Low,High"
textline "                               "
bitfld.long 0x00 13. " IRQS45  ,IRQS Status Bit 45" "Low,High"
bitfld.long 0x00 12. "  IRQS44  ,IRQS Status Bit 44" "Low,High"
bitfld.long 0x00 11. "  IRQS43  ,IRQS Status Bit 43" "Low,High"
textline "                               "
bitfld.long 0x00 10. " IRQS42  ,IRQS Status Bit 42" "Low,High"
bitfld.long 0x00 9. "  IRQS41  ,IRQS Status Bit 41" "Low,High"
bitfld.long 0x00 8. "  IRQS40  ,IRQS Status Bit 40" "Low,High"
textline "                               "
bitfld.long 0x00 7. " IRQS39  ,IRQS Status Bit 39" "Low,High"
bitfld.long 0x00 6. "  IRQS38  ,IRQS Status Bit 38" "Low,High"
bitfld.long 0x00 5. "  IRQS37  ,IRQS Status Bit 37" "Low,High"
textline "                               "
bitfld.long 0x00 4. " IRQS36  ,IRQS Status Bit 36" "Low,High"
bitfld.long 0x00 3. "  IRQS35  ,IRQS Status Bit 35" "Low,High"
bitfld.long 0x00 2. "  IRQS34  ,IRQS Status Bit 34" "Low,High"
textline "                               "
bitfld.long 0x00 1. " IRQS33  ,IRQS Status Bit 33" "Low,High"
bitfld.long 0x00 0. "  IRQS32  ,IRQS Status Bit 32" "Low,High"
else
rgroup.long 0x0D08++0x03
line.long 0x0 "GICD_SPISR1,Shared Peripheral Interrupt Status Register 1"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x03)
rgroup.long 0x0D0C++0x03
line.long 0x0 "GICD_SPISR2,Shared Peripheral Interrupt Status Register 2"
bitfld.long 0x00 31. " IRQS95  ,IRQS Status Bit 95" "Low,High"
bitfld.long 0x00 30. "  IRQS94  ,IRQS Status Bit 94" "Low,High"
bitfld.long 0x00 29. "  IRQS93  ,IRQS Status Bit 93" "Low,High"
textline "                               "
bitfld.long 0x00 28. " IRQS92  ,IRQS Status Bit 92" "Low,High"
bitfld.long 0x00 27. "  IRQS91  ,IRQS Status Bit 91" "Low,High"
bitfld.long 0x00 26. "  IRQS90  ,IRQS Status Bit 90" "Low,High"
textline "                               "
bitfld.long 0x00 25. " IRQS89  ,IRQS Status Bit 89" "Low,High"
bitfld.long 0x00 24. "  IRQS88  ,IRQS Status Bit 88" "Low,High"
bitfld.long 0x00 23. "  IRQS87  ,IRQS Status Bit 87" "Low,High"
textline "                               "
bitfld.long 0x00 22. " IRQS86  ,IRQS Status Bit 86" "Low,High"
bitfld.long 0x00 21. "  IRQS85  ,IRQS Status Bit 85" "Low,High"
bitfld.long 0x00 20. "  IRQS84  ,IRQS Status Bit 84" "Low,High"
textline "                               "
bitfld.long 0x00 19. " IRQS83  ,IRQS Status Bit 83" "Low,High"
bitfld.long 0x00 18. "  IRQS82  ,IRQS Status Bit 82" "Low,High"
bitfld.long 0x00 17. "  IRQS81  ,IRQS Status Bit 81" "Low,High"
textline "                               "
bitfld.long 0x00 16. " IRQS80  ,IRQS Status Bit 80" "Low,High"
bitfld.long 0x00 15. "  IRQS79  ,IRQS Status Bit 79" "Low,High"
bitfld.long 0x00 14. "  IRQS78  ,IRQS Status Bit 78" "Low,High"
textline "                               "
bitfld.long 0x00 13. " IRQS77  ,IRQS Status Bit 77" "Low,High"
bitfld.long 0x00 12. "  IRQS76  ,IRQS Status Bit 76" "Low,High"
bitfld.long 0x00 11. "  IRQS75  ,IRQS Status Bit 75" "Low,High"
textline "                               "
bitfld.long 0x00 10. " IRQS74  ,IRQS Status Bit 74" "Low,High"
bitfld.long 0x00 9. "  IRQS73  ,IRQS Status Bit 73" "Low,High"
bitfld.long 0x00 8. "  IRQS72  ,IRQS Status Bit 72" "Low,High"
textline "                               "
bitfld.long 0x00 7. " IRQS71  ,IRQS Status Bit 71" "Low,High"
bitfld.long 0x00 6. "  IRQS70  ,IRQS Status Bit 70" "Low,High"
bitfld.long 0x00 5. "  IRQS69  ,IRQS Status Bit 69" "Low,High"
textline "                               "
bitfld.long 0x00 4. " IRQS68  ,IRQS Status Bit 68" "Low,High"
bitfld.long 0x00 3. "  IRQS67  ,IRQS Status Bit 67" "Low,High"
bitfld.long 0x00 2. "  IRQS66  ,IRQS Status Bit 66" "Low,High"
textline "                               "
bitfld.long 0x00 1. " IRQS65  ,IRQS Status Bit 65" "Low,High"
bitfld.long 0x00 0. "  IRQS64  ,IRQS Status Bit 64" "Low,High"
else
rgroup.long 0x0D0C++0x03
line.long 0x0 "GICD_SPISR2,Shared Peripheral Interrupt Status Register 2"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x04)
rgroup.long 0x0D10++0x03
line.long 0x0 "GICD_SPISR3,Shared Peripheral Interrupt Status Register 3"
bitfld.long 0x00 31. " IRQS127 ,IRQS Status Bit 127" "Low,High"
bitfld.long 0x00 30. "  IRQS126 ,IRQS Status Bit 126" "Low,High"
bitfld.long 0x00 29. "  IRQS125 ,IRQS Status Bit 125" "Low,High"
textline "                               "
bitfld.long 0x00 28. " IRQS124 ,IRQS Status Bit 124" "Low,High"
bitfld.long 0x00 27. "  IRQS123 ,IRQS Status Bit 123" "Low,High"
bitfld.long 0x00 26. "  IRQS122 ,IRQS Status Bit 122" "Low,High"
textline "                               "
bitfld.long 0x00 25. " IRQS121 ,IRQS Status Bit 121" "Low,High"
bitfld.long 0x00 24. "  IRQS120 ,IRQS Status Bit 120" "Low,High"
bitfld.long 0x00 23. "  IRQS119 ,IRQS Status Bit 119" "Low,High"
textline "                               "
bitfld.long 0x00 22. " IRQS118 ,IRQS Status Bit 118" "Low,High"
bitfld.long 0x00 21. "  IRQS117 ,IRQS Status Bit 117" "Low,High"
bitfld.long 0x00 20. "  IRQS116 ,IRQS Status Bit 116" "Low,High"
textline "                               "
bitfld.long 0x00 19. " IRQS115 ,IRQS Status Bit 115" "Low,High"
bitfld.long 0x00 18. "  IRQS114 ,IRQS Status Bit 114" "Low,High"
bitfld.long 0x00 17. "  IRQS113 ,IRQS Status Bit 113" "Low,High"
textline "                               "
bitfld.long 0x00 16. " IRQS112 ,IRQS Status Bit 112" "Low,High"
bitfld.long 0x00 15. "  IRQS111 ,IRQS Status Bit 111" "Low,High"
bitfld.long 0x00 14. "  IRQS110 ,IRQS Status Bit 110" "Low,High"
textline "                               "
bitfld.long 0x00 13. " IRQS109 ,IRQS Status Bit 109" "Low,High"
bitfld.long 0x00 12. "  IRQS108 ,IRQS Status Bit 108" "Low,High"
bitfld.long 0x00 11. "  IRQS107 ,IRQS Status Bit 107" "Low,High"
textline "                               "
bitfld.long 0x00 10. " IRQS106 ,IRQS Status Bit 106" "Low,High"
bitfld.long 0x00 9. "  IRQS105 ,IRQS Status Bit 105" "Low,High"
bitfld.long 0x00 8. "  IRQS104 ,IRQS Status Bit 104" "Low,High"
textline "                               "
bitfld.long 0x00 7. " IRQS103 ,IRQS Status Bit 103" "Low,High"
bitfld.long 0x00 6. "  IRQS102 ,IRQS Status Bit 102" "Low,High"
bitfld.long 0x00 5. "  IRQS101 ,IRQS Status Bit 101" "Low,High"
textline "                               "
bitfld.long 0x00 4. " IRQS100 ,IRQS Status Bit 100" "Low,High"
bitfld.long 0x00 3. "  IRQS99  ,IRQS Status Bit 99" "Low,High"
bitfld.long 0x00 2. "  IRQS98  ,IRQS Status Bit 98" "Low,High"
textline "                               "
bitfld.long 0x00 1. " IRQS97  ,IRQS Status Bit 97" "Low,High"
bitfld.long 0x00 0. "  IRQS96  ,IRQS Status Bit 96" "Low,High"
else
rgroup.long 0x0D10++0x03
line.long 0x0 "GICD_SPISR3,Shared Peripheral Interrupt Status Register 3"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x05)
rgroup.long 0x0D14++0x03
line.long 0x0 "GICD_SPISR4,Shared Peripheral Interrupt Status Register 4"
bitfld.long 0x00 31. " IRQS159 ,IRQS Status Bit 159" "Low,High"
bitfld.long 0x00 30. "  IRQS158 ,IRQS Status Bit 158" "Low,High"
bitfld.long 0x00 29. "  IRQS157 ,IRQS Status Bit 157" "Low,High"
textline "                               "
bitfld.long 0x00 28. " IRQS156 ,IRQS Status Bit 156" "Low,High"
bitfld.long 0x00 27. "  IRQS155 ,IRQS Status Bit 155" "Low,High"
bitfld.long 0x00 26. "  IRQS154 ,IRQS Status Bit 154" "Low,High"
textline "                               "
bitfld.long 0x00 25. " IRQS153 ,IRQS Status Bit 153" "Low,High"
bitfld.long 0x00 24. "  IRQS152 ,IRQS Status Bit 152" "Low,High"
bitfld.long 0x00 23. "  IRQS151 ,IRQS Status Bit 151" "Low,High"
textline "                               "
bitfld.long 0x00 22. " IRQS150 ,IRQS Status Bit 150" "Low,High"
bitfld.long 0x00 21. "  IRQS149 ,IRQS Status Bit 149" "Low,High"
bitfld.long 0x00 20. "  IRQS148 ,IRQS Status Bit 148" "Low,High"
textline "                               "
bitfld.long 0x00 19. " IRQS147 ,IRQS Status Bit 147" "Low,High"
bitfld.long 0x00 18. "  IRQS146 ,IRQS Status Bit 146" "Low,High"
bitfld.long 0x00 17. "  IRQS145 ,IRQS Status Bit 145" "Low,High"
textline "                               "
bitfld.long 0x00 16. " IRQS144 ,IRQS Status Bit 144" "Low,High"
bitfld.long 0x00 15. "  IRQS143 ,IRQS Status Bit 143" "Low,High"
bitfld.long 0x00 14. "  IRQS142 ,IRQS Status Bit 142" "Low,High"
textline "                               "
bitfld.long 0x00 13. " IRQS141 ,IRQS Status Bit 141" "Low,High"
bitfld.long 0x00 12. "  IRQS140 ,IRQS Status Bit 140" "Low,High"
bitfld.long 0x00 11. "  IRQS139 ,IRQS Status Bit 139" "Low,High"
textline "                               "
bitfld.long 0x00 10. " IRQS138 ,IRQS Status Bit 138" "Low,High"
bitfld.long 0x00 9. "  IRQS137 ,IRQS Status Bit 137" "Low,High"
bitfld.long 0x00 8. "  IRQS136 ,IRQS Status Bit 136" "Low,High"
textline "                               "
bitfld.long 0x00 7. " IRQS135 ,IRQS Status Bit 135" "Low,High"
bitfld.long 0x00 6. "  IRQS134 ,IRQS Status Bit 134" "Low,High"
bitfld.long 0x00 5. "  IRQS133 ,IRQS Status Bit 133" "Low,High"
textline "                               "
bitfld.long 0x00 4. " IRQS132 ,IRQS Status Bit 132" "Low,High"
bitfld.long 0x00 3. "  IRQS131 ,IRQS Status Bit 131" "Low,High"
bitfld.long 0x00 2. "  IRQS130 ,IRQS Status Bit 130" "Low,High"
textline "                               "
bitfld.long 0x00 1. " IRQS129 ,IRQS Status Bit 129" "Low,High"
bitfld.long 0x00 0. "  IRQS128 ,IRQS Status Bit 128" "Low,High"
else
rgroup.long 0x0D14++0x03
line.long 0x0 "GICD_SPISR4,Shared Peripheral Interrupt Status Register 4"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x06)
rgroup.long 0x0D18++0x03
line.long 0x0 "GICD_SPISR5,Shared Peripheral Interrupt Status Register 5"
bitfld.long 0x00 31. " IRQS191 ,IRQS Status Bit 191" "Low,High"
bitfld.long 0x00 30. "  IRQS190 ,IRQS Status Bit 190" "Low,High"
bitfld.long 0x00 29. "  IRQS189 ,IRQS Status Bit 189" "Low,High"
textline "                               "
bitfld.long 0x00 28. " IRQS188 ,IRQS Status Bit 188" "Low,High"
bitfld.long 0x00 27. "  IRQS187 ,IRQS Status Bit 187" "Low,High"
bitfld.long 0x00 26. "  IRQS186 ,IRQS Status Bit 186" "Low,High"
textline "                               "
bitfld.long 0x00 25. " IRQS185 ,IRQS Status Bit 185" "Low,High"
bitfld.long 0x00 24. "  IRQS184 ,IRQS Status Bit 184" "Low,High"
bitfld.long 0x00 23. "  IRQS183 ,IRQS Status Bit 183" "Low,High"
textline "                               "
bitfld.long 0x00 22. " IRQS182 ,IRQS Status Bit 182" "Low,High"
bitfld.long 0x00 21. "  IRQS181 ,IRQS Status Bit 181" "Low,High"
bitfld.long 0x00 20. "  IRQS180 ,IRQS Status Bit 180" "Low,High"
textline "                               "
bitfld.long 0x00 19. " IRQS179 ,IRQS Status Bit 179" "Low,High"
bitfld.long 0x00 18. "  IRQS178 ,IRQS Status Bit 178" "Low,High"
bitfld.long 0x00 17. "  IRQS177 ,IRQS Status Bit 177" "Low,High"
textline "                               "
bitfld.long 0x00 16. " IRQS176 ,IRQS Status Bit 176" "Low,High"
bitfld.long 0x00 15. "  IRQS175 ,IRQS Status Bit 175" "Low,High"
bitfld.long 0x00 14. "  IRQS174 ,IRQS Status Bit 174" "Low,High"
textline "                               "
bitfld.long 0x00 13. " IRQS173 ,IRQS Status Bit 173" "Low,High"
bitfld.long 0x00 12. "  IRQS172 ,IRQS Status Bit 172" "Low,High"
bitfld.long 0x00 11. "  IRQS171 ,IRQS Status Bit 171" "Low,High"
textline "                               "
bitfld.long 0x00 10. " IRQS170 ,IRQS Status Bit 170" "Low,High"
bitfld.long 0x00 9. "  IRQS169 ,IRQS Status Bit 169" "Low,High"
bitfld.long 0x00 8. "  IRQS168 ,IRQS Status Bit 168" "Low,High"
textline "                               "
bitfld.long 0x00 7. " IRQS167 ,IRQS Status Bit 167" "Low,High"
bitfld.long 0x00 6. "  IRQS166 ,IRQS Status Bit 166" "Low,High"
bitfld.long 0x00 5. "  IRQS165 ,IRQS Status Bit 165" "Low,High"
textline "                               "
bitfld.long 0x00 4. " IRQS164 ,IRQS Status Bit 164" "Low,High"
bitfld.long 0x00 3. "  IRQS163 ,IRQS Status Bit 163" "Low,High"
bitfld.long 0x00 2. "  IRQS162 ,IRQS Status Bit 162" "Low,High"
textline "                               "
bitfld.long 0x00 1. " IRQS161 ,IRQS Status Bit 161" "Low,High"
bitfld.long 0x00 0. "  IRQS160 ,IRQS Status Bit 160" "Low,High"
else
rgroup.long 0x0D18++0x03
line.long 0x0 "GICD_SPISR5,Shared Peripheral Interrupt Status Register 5"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x07)
rgroup.long 0x0D1C++0x03
line.long 0x0 "GICD_SPISR6,Shared Peripheral Interrupt Status Register 6"
bitfld.long 0x00 31. " IRQS223 ,IRQS Status Bit 223" "Low,High"
bitfld.long 0x00 30. "  IRQS222 ,IRQS Status Bit 222" "Low,High"
bitfld.long 0x00 29. "  IRQS221 ,IRQS Status Bit 221" "Low,High"
textline "                               "
bitfld.long 0x00 28. " IRQS220 ,IRQS Status Bit 220" "Low,High"
bitfld.long 0x00 27. "  IRQS219 ,IRQS Status Bit 219" "Low,High"
bitfld.long 0x00 26. "  IRQS218 ,IRQS Status Bit 218" "Low,High"
textline "                               "
bitfld.long 0x00 25. " IRQS217 ,IRQS Status Bit 217" "Low,High"
bitfld.long 0x00 24. "  IRQS216 ,IRQS Status Bit 216" "Low,High"
bitfld.long 0x00 23. "  IRQS215 ,IRQS Status Bit 215" "Low,High"
textline "                               "
bitfld.long 0x00 22. " IRQS214 ,IRQS Status Bit 214" "Low,High"
bitfld.long 0x00 21. "  IRQS213 ,IRQS Status Bit 213" "Low,High"
bitfld.long 0x00 20. "  IRQS212 ,IRQS Status Bit 212" "Low,High"
textline "                               "
bitfld.long 0x00 19. " IRQS211 ,IRQS Status Bit 211" "Low,High"
bitfld.long 0x00 18. "  IRQS210 ,IRQS Status Bit 210" "Low,High"
bitfld.long 0x00 17. "  IRQS209 ,IRQS Status Bit 209" "Low,High"
textline "                               "
bitfld.long 0x00 16. " IRQS208 ,IRQS Status Bit 208" "Low,High"
bitfld.long 0x00 15. "  IRQS207 ,IRQS Status Bit 207" "Low,High"
bitfld.long 0x00 14. "  IRQS206 ,IRQS Status Bit 206" "Low,High"
textline "                               "
bitfld.long 0x00 13. " IRQS205 ,IRQS Status Bit 205" "Low,High"
bitfld.long 0x00 12. "  IRQS204 ,IRQS Status Bit 204" "Low,High"
bitfld.long 0x00 11. "  IRQS203 ,IRQS Status Bit 203" "Low,High"
textline "                               "
bitfld.long 0x00 10. " IRQS202 ,IRQS Status Bit 202" "Low,High"
bitfld.long 0x00 9. "  IRQS201 ,IRQS Status Bit 201" "Low,High"
bitfld.long 0x00 8. "  IRQS200 ,IRQS Status Bit 200" "Low,High"
textline "                               "
bitfld.long 0x00 7. " IRQS199 ,IRQS Status Bit 199" "Low,High"
bitfld.long 0x00 6. "  IRQS198 ,IRQS Status Bit 198" "Low,High"
bitfld.long 0x00 5. "  IRQS197 ,IRQS Status Bit 197" "Low,High"
textline "                               "
bitfld.long 0x00 4. " IRQS196 ,IRQS Status Bit 196" "Low,High"
bitfld.long 0x00 3. "  IRQS195 ,IRQS Status Bit 195" "Low,High"
bitfld.long 0x00 2. "  IRQS194 ,IRQS Status Bit 194" "Low,High"
textline "                               "
bitfld.long 0x00 1. " IRQS193 ,IRQS Status Bit 193" "Low,High"
bitfld.long 0x00 0. "  IRQS192 ,IRQS Status Bit 192" "Low,High"
else
rgroup.long 0x0D1C++0x03
line.long 0x0 "GICD_SPISR6,Shared Peripheral Interrupt Status Register 6"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x08)
rgroup.long 0x0D20++0x03
line.long 0x0 "GICD_SPISR7,Shared Peripheral Interrupt Status Register 7"
bitfld.long 0x00 31. " IRQS255 ,IRQS Status Bit 255" "Low,High"
bitfld.long 0x00 30. "  IRQS254 ,IRQS Status Bit 254" "Low,High"
bitfld.long 0x00 29. "  IRQS253 ,IRQS Status Bit 253" "Low,High"
textline "                               "
bitfld.long 0x00 28. " IRQS252 ,IRQS Status Bit 252" "Low,High"
bitfld.long 0x00 27. "  IRQS251 ,IRQS Status Bit 251" "Low,High"
bitfld.long 0x00 26. "  IRQS250 ,IRQS Status Bit 250" "Low,High"
textline "                               "
bitfld.long 0x00 25. " IRQS249 ,IRQS Status Bit 249" "Low,High"
bitfld.long 0x00 24. "  IRQS248 ,IRQS Status Bit 248" "Low,High"
bitfld.long 0x00 23. "  IRQS247 ,IRQS Status Bit 247" "Low,High"
textline "                               "
bitfld.long 0x00 22. " IRQS246 ,IRQS Status Bit 246" "Low,High"
bitfld.long 0x00 21. "  IRQS245 ,IRQS Status Bit 245" "Low,High"
bitfld.long 0x00 20. "  IRQS244 ,IRQS Status Bit 244" "Low,High"
textline "                               "
bitfld.long 0x00 19. " IRQS243 ,IRQS Status Bit 243" "Low,High"
bitfld.long 0x00 18. "  IRQS242 ,IRQS Status Bit 242" "Low,High"
bitfld.long 0x00 17. "  IRQS241 ,IRQS Status Bit 241" "Low,High"
textline "                               "
bitfld.long 0x00 16. " IRQS240 ,IRQS Status Bit 240" "Low,High"
bitfld.long 0x00 15. "  IRQS239 ,IRQS Status Bit 239" "Low,High"
bitfld.long 0x00 14. "  IRQS238 ,IRQS Status Bit 238" "Low,High"
textline "                               "
bitfld.long 0x00 13. " IRQS237 ,IRQS Status Bit 237" "Low,High"
bitfld.long 0x00 12. "  IRQS236 ,IRQS Status Bit 236" "Low,High"
bitfld.long 0x00 11. "  IRQS235 ,IRQS Status Bit 235" "Low,High"
textline "                               "
bitfld.long 0x00 10. " IRQS234 ,IRQS Status Bit 234" "Low,High"
bitfld.long 0x00 9. "  IRQS233 ,IRQS Status Bit 233" "Low,High"
bitfld.long 0x00 8. "  IRQS232 ,IRQS Status Bit 232" "Low,High"
textline "                               "
bitfld.long 0x00 7. " IRQS231 ,IRQS Status Bit 231" "Low,High"
bitfld.long 0x00 6. "  IRQS230 ,IRQS Status Bit 230" "Low,High"
bitfld.long 0x00 5. "  IRQS229 ,IRQS Status Bit 229" "Low,High"
textline "                               "
bitfld.long 0x00 4. " IRQS228 ,IRQS Status Bit 228" "Low,High"
bitfld.long 0x00 3. "  IRQS227 ,IRQS Status Bit 227" "Low,High"
bitfld.long 0x00 2. "  IRQS226 ,IRQS Status Bit 226" "Low,High"
textline "                               "
bitfld.long 0x00 1. " IRQS225 ,IRQS Status Bit 225" "Low,High"
bitfld.long 0x00 0. "  IRQS224 ,IRQS Status Bit 224" "Low,High"
else
rgroup.long 0x0D20++0x03
line.long 0x0 "GICD_SPISR7,Shared Peripheral Interrupt Status Register 7"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x09)
rgroup.long 0x0D24++0x03
line.long 0x0 "GICD_SPISR8,Shared Peripheral Interrupt Status Register 8"
bitfld.long 0x00 31. " IRQS287 ,IRQS Status Bit 287" "Low,High"
bitfld.long 0x00 30. "  IRQS286 ,IRQS Status Bit 286" "Low,High"
bitfld.long 0x00 29. "  IRQS285 ,IRQS Status Bit 285" "Low,High"
textline "                               "
bitfld.long 0x00 28. " IRQS284 ,IRQS Status Bit 284" "Low,High"
bitfld.long 0x00 27. "  IRQS283 ,IRQS Status Bit 283" "Low,High"
bitfld.long 0x00 26. "  IRQS282 ,IRQS Status Bit 282" "Low,High"
textline "                               "
bitfld.long 0x00 25. " IRQS281 ,IRQS Status Bit 281" "Low,High"
bitfld.long 0x00 24. "  IRQS280 ,IRQS Status Bit 280" "Low,High"
bitfld.long 0x00 23. "  IRQS279 ,IRQS Status Bit 279" "Low,High"
textline "                               "
bitfld.long 0x00 22. " IRQS278 ,IRQS Status Bit 278" "Low,High"
bitfld.long 0x00 21. "  IRQS277 ,IRQS Status Bit 277" "Low,High"
bitfld.long 0x00 20. "  IRQS276 ,IRQS Status Bit 276" "Low,High"
textline "                               "
bitfld.long 0x00 19. " IRQS275 ,IRQS Status Bit 275" "Low,High"
bitfld.long 0x00 18. "  IRQS274 ,IRQS Status Bit 274" "Low,High"
bitfld.long 0x00 17. "  IRQS273 ,IRQS Status Bit 273" "Low,High"
textline "                               "
bitfld.long 0x00 16. " IRQS272 ,IRQS Status Bit 272" "Low,High"
bitfld.long 0x00 15. "  IRQS271 ,IRQS Status Bit 271" "Low,High"
bitfld.long 0x00 14. "  IRQS270 ,IRQS Status Bit 270" "Low,High"
textline "                               "
bitfld.long 0x00 13. " IRQS269 ,IRQS Status Bit 269" "Low,High"
bitfld.long 0x00 12. "  IRQS268 ,IRQS Status Bit 268" "Low,High"
bitfld.long 0x00 11. "  IRQS267 ,IRQS Status Bit 267" "Low,High"
textline "                               "
bitfld.long 0x00 10. " IRQS266 ,IRQS Status Bit 266" "Low,High"
bitfld.long 0x00 9. "  IRQS265 ,IRQS Status Bit 265" "Low,High"
bitfld.long 0x00 8. "  IRQS264 ,IRQS Status Bit 264" "Low,High"
textline "                               "
bitfld.long 0x00 7. " IRQS263 ,IRQS Status Bit 263" "Low,High"
bitfld.long 0x00 6. "  IRQS262 ,IRQS Status Bit 262" "Low,High"
bitfld.long 0x00 5. "  IRQS261 ,IRQS Status Bit 261" "Low,High"
textline "                               "
bitfld.long 0x00 4. " IRQS260 ,IRQS Status Bit 260" "Low,High"
bitfld.long 0x00 3. "  IRQS259 ,IRQS Status Bit 259" "Low,High"
bitfld.long 0x00 2. "  IRQS258 ,IRQS Status Bit 258" "Low,High"
textline "                               "
bitfld.long 0x00 1. " IRQS257 ,IRQS Status Bit 257" "Low,High"
bitfld.long 0x00 0. "  IRQS256 ,IRQS Status Bit 256" "Low,High"
else
rgroup.long 0x0D24++0x03
line.long 0x0 "GICD_SPISR8,Shared Peripheral Interrupt Status Register 8"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0A)
rgroup.long 0x0D28++0x03
line.long 0x0 "GICD_SPISR9,Shared Peripheral Interrupt Status Register 9"
bitfld.long 0x00 31. " IRQS319 ,IRQS Status Bit 319" "Low,High"
bitfld.long 0x00 30. "  IRQS318 ,IRQS Status Bit 318" "Low,High"
bitfld.long 0x00 29. "  IRQS317 ,IRQS Status Bit 317" "Low,High"
textline "                               "
bitfld.long 0x00 28. " IRQS316 ,IRQS Status Bit 316" "Low,High"
bitfld.long 0x00 27. "  IRQS315 ,IRQS Status Bit 315" "Low,High"
bitfld.long 0x00 26. "  IRQS314 ,IRQS Status Bit 314" "Low,High"
textline "                               "
bitfld.long 0x00 25. " IRQS313 ,IRQS Status Bit 313" "Low,High"
bitfld.long 0x00 24. "  IRQS312 ,IRQS Status Bit 312" "Low,High"
bitfld.long 0x00 23. "  IRQS311 ,IRQS Status Bit 311" "Low,High"
textline "                               "
bitfld.long 0x00 22. " IRQS310 ,IRQS Status Bit 310" "Low,High"
bitfld.long 0x00 21. "  IRQS309 ,IRQS Status Bit 309" "Low,High"
bitfld.long 0x00 20. "  IRQS308 ,IRQS Status Bit 308" "Low,High"
textline "                               "
bitfld.long 0x00 19. " IRQS307 ,IRQS Status Bit 307" "Low,High"
bitfld.long 0x00 18. "  IRQS306 ,IRQS Status Bit 306" "Low,High"
bitfld.long 0x00 17. "  IRQS305 ,IRQS Status Bit 305" "Low,High"
textline "                               "
bitfld.long 0x00 16. " IRQS304 ,IRQS Status Bit 304" "Low,High"
bitfld.long 0x00 15. "  IRQS303 ,IRQS Status Bit 303" "Low,High"
bitfld.long 0x00 14. "  IRQS302 ,IRQS Status Bit 302" "Low,High"
textline "                               "
bitfld.long 0x00 13. " IRQS301 ,IRQS Status Bit 301" "Low,High"
bitfld.long 0x00 12. "  IRQS300 ,IRQS Status Bit 300" "Low,High"
bitfld.long 0x00 11. "  IRQS299 ,IRQS Status Bit 299" "Low,High"
textline "                               "
bitfld.long 0x00 10. " IRQS298 ,IRQS Status Bit 298" "Low,High"
bitfld.long 0x00 9. "  IRQS297 ,IRQS Status Bit 297" "Low,High"
bitfld.long 0x00 8. "  IRQS296 ,IRQS Status Bit 296" "Low,High"
textline "                               "
bitfld.long 0x00 7. " IRQS295 ,IRQS Status Bit 295" "Low,High"
bitfld.long 0x00 6. "  IRQS294 ,IRQS Status Bit 294" "Low,High"
bitfld.long 0x00 5. "  IRQS293 ,IRQS Status Bit 293" "Low,High"
textline "                               "
bitfld.long 0x00 4. " IRQS292 ,IRQS Status Bit 292" "Low,High"
bitfld.long 0x00 3. "  IRQS291 ,IRQS Status Bit 291" "Low,High"
bitfld.long 0x00 2. "  IRQS290 ,IRQS Status Bit 290" "Low,High"
textline "                               "
bitfld.long 0x00 1. " IRQS289 ,IRQS Status Bit 289" "Low,High"
bitfld.long 0x00 0. "  IRQS288 ,IRQS Status Bit 288" "Low,High"
else
rgroup.long 0x0D28++0x03
line.long 0x0 "GICD_SPISR9,Shared Peripheral Interrupt Status Register 9"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0B)
rgroup.long 0x0D2C++0x03
line.long 0x0 "GICD_SPISR10,Shared Peripheral Interrupt Status Register 10"
bitfld.long 0x00 31. " IRQS351 ,IRQS Status Bit 351" "Low,High"
bitfld.long 0x00 30. "  IRQS350 ,IRQS Status Bit 350" "Low,High"
bitfld.long 0x00 29. "  IRQS349 ,IRQS Status Bit 349" "Low,High"
textline "                               "
bitfld.long 0x00 28. " IRQS348 ,IRQS Status Bit 348" "Low,High"
bitfld.long 0x00 27. "  IRQS347 ,IRQS Status Bit 347" "Low,High"
bitfld.long 0x00 26. "  IRQS346 ,IRQS Status Bit 346" "Low,High"
textline "                               "
bitfld.long 0x00 25. " IRQS345 ,IRQS Status Bit 345" "Low,High"
bitfld.long 0x00 24. "  IRQS344 ,IRQS Status Bit 344" "Low,High"
bitfld.long 0x00 23. "  IRQS343 ,IRQS Status Bit 343" "Low,High"
textline "                               "
bitfld.long 0x00 22. " IRQS342 ,IRQS Status Bit 342" "Low,High"
bitfld.long 0x00 21. "  IRQS341 ,IRQS Status Bit 341" "Low,High"
bitfld.long 0x00 20. "  IRQS340 ,IRQS Status Bit 340" "Low,High"
textline "                               "
bitfld.long 0x00 19. " IRQS339 ,IRQS Status Bit 339" "Low,High"
bitfld.long 0x00 18. "  IRQS338 ,IRQS Status Bit 338" "Low,High"
bitfld.long 0x00 17. "  IRQS337 ,IRQS Status Bit 337" "Low,High"
textline "                               "
bitfld.long 0x00 16. " IRQS336 ,IRQS Status Bit 336" "Low,High"
bitfld.long 0x00 15. "  IRQS335 ,IRQS Status Bit 335" "Low,High"
bitfld.long 0x00 14. "  IRQS334 ,IRQS Status Bit 334" "Low,High"
textline "                               "
bitfld.long 0x00 13. " IRQS333 ,IRQS Status Bit 333" "Low,High"
bitfld.long 0x00 12. "  IRQS332 ,IRQS Status Bit 332" "Low,High"
bitfld.long 0x00 11. "  IRQS331 ,IRQS Status Bit 331" "Low,High"
textline "                               "
bitfld.long 0x00 10. " IRQS330 ,IRQS Status Bit 330" "Low,High"
bitfld.long 0x00 9. "  IRQS329 ,IRQS Status Bit 329" "Low,High"
bitfld.long 0x00 8. "  IRQS328 ,IRQS Status Bit 328" "Low,High"
textline "                               "
bitfld.long 0x00 7. " IRQS327 ,IRQS Status Bit 327" "Low,High"
bitfld.long 0x00 6. "  IRQS326 ,IRQS Status Bit 326" "Low,High"
bitfld.long 0x00 5. "  IRQS325 ,IRQS Status Bit 325" "Low,High"
textline "                               "
bitfld.long 0x00 4. " IRQS324 ,IRQS Status Bit 324" "Low,High"
bitfld.long 0x00 3. "  IRQS323 ,IRQS Status Bit 323" "Low,High"
bitfld.long 0x00 2. "  IRQS322 ,IRQS Status Bit 322" "Low,High"
textline "                               "
bitfld.long 0x00 1. " IRQS321 ,IRQS Status Bit 321" "Low,High"
bitfld.long 0x00 0. "  IRQS320 ,IRQS Status Bit 320" "Low,High"
else
rgroup.long 0x0D2C++0x03
line.long 0x0 "GICD_SPISR10,Shared Peripheral Interrupt Status Register 10"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0C)
rgroup.long 0x0D30++0x03
line.long 0x0 "GICD_SPISR11,Shared Peripheral Interrupt Status Register 11"
bitfld.long 0x00 31. " IRQS383 ,IRQS Status Bit 383" "Low,High"
bitfld.long 0x00 30. "  IRQS382 ,IRQS Status Bit 382" "Low,High"
bitfld.long 0x00 29. "  IRQS381 ,IRQS Status Bit 381" "Low,High"
textline "                               "
bitfld.long 0x00 28. " IRQS380 ,IRQS Status Bit 380" "Low,High"
bitfld.long 0x00 27. "  IRQS379 ,IRQS Status Bit 379" "Low,High"
bitfld.long 0x00 26. "  IRQS378 ,IRQS Status Bit 378" "Low,High"
textline "                               "
bitfld.long 0x00 25. " IRQS377 ,IRQS Status Bit 377" "Low,High"
bitfld.long 0x00 24. "  IRQS376 ,IRQS Status Bit 376" "Low,High"
bitfld.long 0x00 23. "  IRQS375 ,IRQS Status Bit 375" "Low,High"
textline "                               "
bitfld.long 0x00 22. " IRQS374 ,IRQS Status Bit 374" "Low,High"
bitfld.long 0x00 21. "  IRQS373 ,IRQS Status Bit 373" "Low,High"
bitfld.long 0x00 20. "  IRQS372 ,IRQS Status Bit 372" "Low,High"
textline "                               "
bitfld.long 0x00 19. " IRQS371 ,IRQS Status Bit 371" "Low,High"
bitfld.long 0x00 18. "  IRQS370 ,IRQS Status Bit 370" "Low,High"
bitfld.long 0x00 17. "  IRQS369 ,IRQS Status Bit 369" "Low,High"
textline "                               "
bitfld.long 0x00 16. " IRQS368 ,IRQS Status Bit 368" "Low,High"
bitfld.long 0x00 15. "  IRQS367 ,IRQS Status Bit 367" "Low,High"
bitfld.long 0x00 14. "  IRQS366 ,IRQS Status Bit 366" "Low,High"
textline "                               "
bitfld.long 0x00 13. " IRQS365 ,IRQS Status Bit 365" "Low,High"
bitfld.long 0x00 12. "  IRQS364 ,IRQS Status Bit 364" "Low,High"
bitfld.long 0x00 11. "  IRQS363 ,IRQS Status Bit 363" "Low,High"
textline "                               "
bitfld.long 0x00 10. " IRQS362 ,IRQS Status Bit 362" "Low,High"
bitfld.long 0x00 9. "  IRQS361 ,IRQS Status Bit 361" "Low,High"
bitfld.long 0x00 8. "  IRQS360 ,IRQS Status Bit 360" "Low,High"
textline "                               "
bitfld.long 0x00 7. " IRQS359 ,IRQS Status Bit 359" "Low,High"
bitfld.long 0x00 6. "  IRQS358 ,IRQS Status Bit 358" "Low,High"
bitfld.long 0x00 5. "  IRQS357 ,IRQS Status Bit 357" "Low,High"
textline "                               "
bitfld.long 0x00 4. " IRQS356 ,IRQS Status Bit 356" "Low,High"
bitfld.long 0x00 3. "  IRQS355 ,IRQS Status Bit 355" "Low,High"
bitfld.long 0x00 2. "  IRQS354 ,IRQS Status Bit 354" "Low,High"
textline "                               "
bitfld.long 0x00 1. " IRQS353 ,IRQS Status Bit 353" "Low,High"
bitfld.long 0x00 0. "  IRQS352 ,IRQS Status Bit 352" "Low,High"
else
rgroup.long 0x0D30++0x03
line.long 0x0 "GICD_SPISR11,Shared Peripheral Interrupt Status Register 11"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0D)
rgroup.long 0x0D34++0x03
line.long 0x0 "GICD_SPISR12,Shared Peripheral Interrupt Status Register 12"
bitfld.long 0x00 31. " IRQS415 ,IRQS Status Bit 415" "Low,High"
bitfld.long 0x00 30. "  IRQS414 ,IRQS Status Bit 414" "Low,High"
bitfld.long 0x00 29. "  IRQS413 ,IRQS Status Bit 413" "Low,High"
textline "                               "
bitfld.long 0x00 28. " IRQS412 ,IRQS Status Bit 412" "Low,High"
bitfld.long 0x00 27. "  IRQS411 ,IRQS Status Bit 411" "Low,High"
bitfld.long 0x00 26. "  IRQS410 ,IRQS Status Bit 410" "Low,High"
textline "                               "
bitfld.long 0x00 25. " IRQS409 ,IRQS Status Bit 409" "Low,High"
bitfld.long 0x00 24. "  IRQS408 ,IRQS Status Bit 408" "Low,High"
bitfld.long 0x00 23. "  IRQS407 ,IRQS Status Bit 407" "Low,High"
textline "                               "
bitfld.long 0x00 22. " IRQS406 ,IRQS Status Bit 406" "Low,High"
bitfld.long 0x00 21. "  IRQS405 ,IRQS Status Bit 405" "Low,High"
bitfld.long 0x00 20. "  IRQS404 ,IRQS Status Bit 404" "Low,High"
textline "                               "
bitfld.long 0x00 19. " IRQS403 ,IRQS Status Bit 403" "Low,High"
bitfld.long 0x00 18. "  IRQS402 ,IRQS Status Bit 402" "Low,High"
bitfld.long 0x00 17. "  IRQS401 ,IRQS Status Bit 401" "Low,High"
textline "                               "
bitfld.long 0x00 16. " IRQS400 ,IRQS Status Bit 400" "Low,High"
bitfld.long 0x00 15. "  IRQS399 ,IRQS Status Bit 399" "Low,High"
bitfld.long 0x00 14. "  IRQS398 ,IRQS Status Bit 398" "Low,High"
textline "                               "
bitfld.long 0x00 13. " IRQS397 ,IRQS Status Bit 397" "Low,High"
bitfld.long 0x00 12. "  IRQS396 ,IRQS Status Bit 396" "Low,High"
bitfld.long 0x00 11. "  IRQS395 ,IRQS Status Bit 395" "Low,High"
textline "                               "
bitfld.long 0x00 10. " IRQS394 ,IRQS Status Bit 394" "Low,High"
bitfld.long 0x00 9. "  IRQS393 ,IRQS Status Bit 393" "Low,High"
bitfld.long 0x00 8. "  IRQS392 ,IRQS Status Bit 392" "Low,High"
textline "                               "
bitfld.long 0x00 7. " IRQS391 ,IRQS Status Bit 391" "Low,High"
bitfld.long 0x00 6. "  IRQS390 ,IRQS Status Bit 390" "Low,High"
bitfld.long 0x00 5. "  IRQS389 ,IRQS Status Bit 389" "Low,High"
textline "                               "
bitfld.long 0x00 4. " IRQS388 ,IRQS Status Bit 388" "Low,High"
bitfld.long 0x00 3. "  IRQS387 ,IRQS Status Bit 387" "Low,High"
bitfld.long 0x00 2. "  IRQS386 ,IRQS Status Bit 386" "Low,High"
textline "                               "
bitfld.long 0x00 1. " IRQS385 ,IRQS Status Bit 385" "Low,High"
bitfld.long 0x00 0. "  IRQS384 ,IRQS Status Bit 384" "Low,High"
else
rgroup.long 0x0D34++0x03
line.long 0x0 "GICD_SPISR12,Shared Peripheral Interrupt Status Register 12"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0E)
rgroup.long 0x0D38++0x03
line.long 0x0 "GICD_SPISR13,Shared Peripheral Interrupt Status Register 13"
bitfld.long 0x00 31. " IRQS447 ,IRQS Status Bit 447" "Low,High"
bitfld.long 0x00 30. "  IRQS446 ,IRQS Status Bit 446" "Low,High"
bitfld.long 0x00 29. "  IRQS445 ,IRQS Status Bit 445" "Low,High"
textline "                               "
bitfld.long 0x00 28. " IRQS444 ,IRQS Status Bit 444" "Low,High"
bitfld.long 0x00 27. "  IRQS443 ,IRQS Status Bit 443" "Low,High"
bitfld.long 0x00 26. "  IRQS442 ,IRQS Status Bit 442" "Low,High"
textline "                               "
bitfld.long 0x00 25. " IRQS441 ,IRQS Status Bit 441" "Low,High"
bitfld.long 0x00 24. "  IRQS440 ,IRQS Status Bit 440" "Low,High"
bitfld.long 0x00 23. "  IRQS439 ,IRQS Status Bit 439" "Low,High"
textline "                               "
bitfld.long 0x00 22. " IRQS438 ,IRQS Status Bit 438" "Low,High"
bitfld.long 0x00 21. "  IRQS437 ,IRQS Status Bit 437" "Low,High"
bitfld.long 0x00 20. "  IRQS436 ,IRQS Status Bit 436" "Low,High"
textline "                               "
bitfld.long 0x00 19. " IRQS435 ,IRQS Status Bit 435" "Low,High"
bitfld.long 0x00 18. "  IRQS434 ,IRQS Status Bit 434" "Low,High"
bitfld.long 0x00 17. "  IRQS433 ,IRQS Status Bit 433" "Low,High"
textline "                               "
bitfld.long 0x00 16. " IRQS432 ,IRQS Status Bit 432" "Low,High"
bitfld.long 0x00 15. "  IRQS431 ,IRQS Status Bit 431" "Low,High"
bitfld.long 0x00 14. "  IRQS430 ,IRQS Status Bit 430" "Low,High"
textline "                               "
bitfld.long 0x00 13. " IRQS429 ,IRQS Status Bit 429" "Low,High"
bitfld.long 0x00 12. "  IRQS428 ,IRQS Status Bit 428" "Low,High"
bitfld.long 0x00 11. "  IRQS427 ,IRQS Status Bit 427" "Low,High"
textline "                               "
bitfld.long 0x00 10. " IRQS426 ,IRQS Status Bit 426" "Low,High"
bitfld.long 0x00 9. "  IRQS425 ,IRQS Status Bit 425" "Low,High"
bitfld.long 0x00 8. "  IRQS424 ,IRQS Status Bit 424" "Low,High"
textline "                               "
bitfld.long 0x00 7. " IRQS423 ,IRQS Status Bit 423" "Low,High"
bitfld.long 0x00 6. "  IRQS422 ,IRQS Status Bit 422" "Low,High"
bitfld.long 0x00 5. "  IRQS421 ,IRQS Status Bit 421" "Low,High"
textline "                               "
bitfld.long 0x00 4. " IRQS420 ,IRQS Status Bit 420" "Low,High"
bitfld.long 0x00 3. "  IRQS419 ,IRQS Status Bit 419" "Low,High"
bitfld.long 0x00 2. "  IRQS418 ,IRQS Status Bit 418" "Low,High"
textline "                               "
bitfld.long 0x00 1. " IRQS417 ,IRQS Status Bit 417" "Low,High"
bitfld.long 0x00 0. "  IRQS416 ,IRQS Status Bit 416" "Low,High"
else
rgroup.long 0x0D38++0x03
line.long 0x0 "GICD_SPISR13,Shared Peripheral Interrupt Status Register 13"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0F)
rgroup.long 0x0D3C++0x03
line.long 0x0 "GICD_SPISR14,Shared Peripheral Interrupt Status Register 14"
bitfld.long 0x00 31. " IRQS479 ,IRQS Status Bit 479" "Low,High"
bitfld.long 0x00 30. "  IRQS478 ,IRQS Status Bit 478" "Low,High"
bitfld.long 0x00 29. "  IRQS477 ,IRQS Status Bit 477" "Low,High"
textline "                               "
bitfld.long 0x00 28. " IRQS476 ,IRQS Status Bit 476" "Low,High"
bitfld.long 0x00 27. "  IRQS475 ,IRQS Status Bit 475" "Low,High"
bitfld.long 0x00 26. "  IRQS474 ,IRQS Status Bit 474" "Low,High"
textline "                               "
bitfld.long 0x00 25. " IRQS473 ,IRQS Status Bit 473" "Low,High"
bitfld.long 0x00 24. "  IRQS472 ,IRQS Status Bit 472" "Low,High"
bitfld.long 0x00 23. "  IRQS471 ,IRQS Status Bit 471" "Low,High"
textline "                               "
bitfld.long 0x00 22. " IRQS470 ,IRQS Status Bit 470" "Low,High"
bitfld.long 0x00 21. "  IRQS469 ,IRQS Status Bit 469" "Low,High"
bitfld.long 0x00 20. "  IRQS468 ,IRQS Status Bit 468" "Low,High"
textline "                               "
bitfld.long 0x00 19. " IRQS467 ,IRQS Status Bit 467" "Low,High"
bitfld.long 0x00 18. "  IRQS466 ,IRQS Status Bit 466" "Low,High"
bitfld.long 0x00 17. "  IRQS465 ,IRQS Status Bit 465" "Low,High"
textline "                               "
bitfld.long 0x00 16. " IRQS464 ,IRQS Status Bit 464" "Low,High"
bitfld.long 0x00 15. "  IRQS463 ,IRQS Status Bit 463" "Low,High"
bitfld.long 0x00 14. "  IRQS462 ,IRQS Status Bit 462" "Low,High"
textline "                               "
bitfld.long 0x00 13. " IRQS461 ,IRQS Status Bit 461" "Low,High"
bitfld.long 0x00 12. "  IRQS460 ,IRQS Status Bit 460" "Low,High"
bitfld.long 0x00 11. "  IRQS459 ,IRQS Status Bit 459" "Low,High"
textline "                               "
bitfld.long 0x00 10. " IRQS458 ,IRQS Status Bit 458" "Low,High"
bitfld.long 0x00 9. "  IRQS457 ,IRQS Status Bit 457" "Low,High"
bitfld.long 0x00 8. "  IRQS456 ,IRQS Status Bit 456" "Low,High"
textline "                               "
bitfld.long 0x00 7. " IRQS455 ,IRQS Status Bit 455" "Low,High"
bitfld.long 0x00 6. "  IRQS454 ,IRQS Status Bit 454" "Low,High"
bitfld.long 0x00 5. "  IRQS453 ,IRQS Status Bit 453" "Low,High"
textline "                               "
bitfld.long 0x00 4. " IRQS452 ,IRQS Status Bit 452" "Low,High"
bitfld.long 0x00 3. "  IRQS451 ,IRQS Status Bit 451" "Low,High"
bitfld.long 0x00 2. "  IRQS450 ,IRQS Status Bit 450" "Low,High"
textline "                               "
bitfld.long 0x00 1. " IRQS449 ,IRQS Status Bit 449" "Low,High"
bitfld.long 0x00 0. "  IRQS448 ,IRQS Status Bit 448" "Low,High"
else
rgroup.long 0x0D3C++0x03
line.long 0x0 "GICD_SPISR14,Shared Peripheral Interrupt Status Register 14"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x10)
rgroup.long 0x0D40++0x03
line.long 0x0 "GICD_SPISR15,Shared Peripheral Interrupt Status Register 15"
bitfld.long 0x00 31. " IRQS511 ,IRQS Status Bit 511" "Low,High"
bitfld.long 0x00 30. "  IRQS510 ,IRQS Status Bit 510" "Low,High"
bitfld.long 0x00 29. "  IRQS509 ,IRQS Status Bit 509" "Low,High"
textline "                               "
bitfld.long 0x00 28. " IRQS508 ,IRQS Status Bit 508" "Low,High"
bitfld.long 0x00 27. "  IRQS507 ,IRQS Status Bit 507" "Low,High"
bitfld.long 0x00 26. "  IRQS506 ,IRQS Status Bit 506" "Low,High"
textline "                               "
bitfld.long 0x00 25. " IRQS505 ,IRQS Status Bit 505" "Low,High"
bitfld.long 0x00 24. "  IRQS504 ,IRQS Status Bit 504" "Low,High"
bitfld.long 0x00 23. "  IRQS503 ,IRQS Status Bit 503" "Low,High"
textline "                               "
bitfld.long 0x00 22. " IRQS502 ,IRQS Status Bit 502" "Low,High"
bitfld.long 0x00 21. "  IRQS501 ,IRQS Status Bit 501" "Low,High"
bitfld.long 0x00 20. "  IRQS500 ,IRQS Status Bit 500" "Low,High"
textline "                               "
bitfld.long 0x00 19. " IRQS499 ,IRQS Status Bit 499" "Low,High"
bitfld.long 0x00 18. "  IRQS498 ,IRQS Status Bit 498" "Low,High"
bitfld.long 0x00 17. "  IRQS497 ,IRQS Status Bit 497" "Low,High"
textline "                               "
bitfld.long 0x00 16. " IRQS496 ,IRQS Status Bit 496" "Low,High"
bitfld.long 0x00 15. "  IRQS495 ,IRQS Status Bit 495" "Low,High"
bitfld.long 0x00 14. "  IRQS494 ,IRQS Status Bit 494" "Low,High"
textline "                               "
bitfld.long 0x00 13. " IRQS493 ,IRQS Status Bit 493" "Low,High"
bitfld.long 0x00 12. "  IRQS492 ,IRQS Status Bit 492" "Low,High"
bitfld.long 0x00 11. "  IRQS491 ,IRQS Status Bit 491" "Low,High"
textline "                               "
bitfld.long 0x00 10. " IRQS490 ,IRQS Status Bit 490" "Low,High"
bitfld.long 0x00 9. "  IRQS489 ,IRQS Status Bit 489" "Low,High"
bitfld.long 0x00 8. "  IRQS488 ,IRQS Status Bit 488" "Low,High"
textline "                               "
bitfld.long 0x00 7. " IRQS487 ,IRQS Status Bit 487" "Low,High"
bitfld.long 0x00 6. "  IRQS486 ,IRQS Status Bit 486" "Low,High"
bitfld.long 0x00 5. "  IRQS485 ,IRQS Status Bit 485" "Low,High"
textline "                               "
bitfld.long 0x00 4. " IRQS484 ,IRQS Status Bit 484" "Low,High"
bitfld.long 0x00 3. "  IRQS483 ,IRQS Status Bit 483" "Low,High"
bitfld.long 0x00 2. "  IRQS482 ,IRQS Status Bit 482" "Low,High"
textline "                               "
bitfld.long 0x00 1. " IRQS481 ,IRQS Status Bit 481" "Low,High"
bitfld.long 0x00 0. "  IRQS480 ,IRQS Status Bit 480" "Low,High"
else
rgroup.long 0x0D40++0x03
line.long 0x0 "GICD_SPISR15,Shared Peripheral Interrupt Status Register 15"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x11)
rgroup.long 0x0D44++0x03
line.long 0x0 "GICD_SPISR16,Shared Peripheral Interrupt Status Register 16"
bitfld.long 0x00 31. " IRQS543 ,IRQS Status Bit 543" "Low,High"
bitfld.long 0x00 30. "  IRQS542 ,IRQS Status Bit 542" "Low,High"
bitfld.long 0x00 29. "  IRQS541 ,IRQS Status Bit 541" "Low,High"
textline "                               "
bitfld.long 0x00 28. " IRQS540 ,IRQS Status Bit 540" "Low,High"
bitfld.long 0x00 27. "  IRQS539 ,IRQS Status Bit 539" "Low,High"
bitfld.long 0x00 26. "  IRQS538 ,IRQS Status Bit 538" "Low,High"
textline "                               "
bitfld.long 0x00 25. " IRQS537 ,IRQS Status Bit 537" "Low,High"
bitfld.long 0x00 24. "  IRQS536 ,IRQS Status Bit 536" "Low,High"
bitfld.long 0x00 23. "  IRQS535 ,IRQS Status Bit 535" "Low,High"
textline "                               "
bitfld.long 0x00 22. " IRQS534 ,IRQS Status Bit 534" "Low,High"
bitfld.long 0x00 21. "  IRQS533 ,IRQS Status Bit 533" "Low,High"
bitfld.long 0x00 20. "  IRQS532 ,IRQS Status Bit 532" "Low,High"
textline "                               "
bitfld.long 0x00 19. " IRQS531 ,IRQS Status Bit 531" "Low,High"
bitfld.long 0x00 18. "  IRQS530 ,IRQS Status Bit 530" "Low,High"
bitfld.long 0x00 17. "  IRQS529 ,IRQS Status Bit 529" "Low,High"
textline "                               "
bitfld.long 0x00 16. " IRQS528 ,IRQS Status Bit 528" "Low,High"
bitfld.long 0x00 15. "  IRQS527 ,IRQS Status Bit 527" "Low,High"
bitfld.long 0x00 14. "  IRQS526 ,IRQS Status Bit 526" "Low,High"
textline "                               "
bitfld.long 0x00 13. " IRQS525 ,IRQS Status Bit 525" "Low,High"
bitfld.long 0x00 12. "  IRQS524 ,IRQS Status Bit 524" "Low,High"
bitfld.long 0x00 11. "  IRQS523 ,IRQS Status Bit 523" "Low,High"
textline "                               "
bitfld.long 0x00 10. " IRQS522 ,IRQS Status Bit 522" "Low,High"
bitfld.long 0x00 9. "  IRQS521 ,IRQS Status Bit 521" "Low,High"
bitfld.long 0x00 8. "  IRQS520 ,IRQS Status Bit 520" "Low,High"
textline "                               "
bitfld.long 0x00 7. " IRQS519 ,IRQS Status Bit 519" "Low,High"
bitfld.long 0x00 6. "  IRQS518 ,IRQS Status Bit 518" "Low,High"
bitfld.long 0x00 5. "  IRQS517 ,IRQS Status Bit 517" "Low,High"
textline "                               "
bitfld.long 0x00 4. " IRQS516 ,IRQS Status Bit 516" "Low,High"
bitfld.long 0x00 3. "  IRQS515 ,IRQS Status Bit 515" "Low,High"
bitfld.long 0x00 2. "  IRQS514 ,IRQS Status Bit 514" "Low,High"
textline "                               "
bitfld.long 0x00 1. " IRQS513 ,IRQS Status Bit 513" "Low,High"
bitfld.long 0x00 0. "  IRQS512 ,IRQS Status Bit 512" "Low,High"
else
rgroup.long 0x0D44++0x03
line.long 0x0 "GICD_SPISR16,Shared Peripheral Interrupt Status Register 16"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x12)
rgroup.long 0x0D48++0x03
line.long 0x0 "GICD_SPISR17,Shared Peripheral Interrupt Status Register 17"
bitfld.long 0x00 31. " IRQS575 ,IRQS Status Bit 575" "Low,High"
bitfld.long 0x00 30. "  IRQS574 ,IRQS Status Bit 574" "Low,High"
bitfld.long 0x00 29. "  IRQS573 ,IRQS Status Bit 573" "Low,High"
textline "                               "
bitfld.long 0x00 28. " IRQS572 ,IRQS Status Bit 572" "Low,High"
bitfld.long 0x00 27. "  IRQS571 ,IRQS Status Bit 571" "Low,High"
bitfld.long 0x00 26. "  IRQS570 ,IRQS Status Bit 570" "Low,High"
textline "                               "
bitfld.long 0x00 25. " IRQS569 ,IRQS Status Bit 569" "Low,High"
bitfld.long 0x00 24. "  IRQS568 ,IRQS Status Bit 568" "Low,High"
bitfld.long 0x00 23. "  IRQS567 ,IRQS Status Bit 567" "Low,High"
textline "                               "
bitfld.long 0x00 22. " IRQS566 ,IRQS Status Bit 566" "Low,High"
bitfld.long 0x00 21. "  IRQS565 ,IRQS Status Bit 565" "Low,High"
bitfld.long 0x00 20. "  IRQS564 ,IRQS Status Bit 564" "Low,High"
textline "                               "
bitfld.long 0x00 19. " IRQS563 ,IRQS Status Bit 563" "Low,High"
bitfld.long 0x00 18. "  IRQS562 ,IRQS Status Bit 562" "Low,High"
bitfld.long 0x00 17. "  IRQS561 ,IRQS Status Bit 561" "Low,High"
textline "                               "
bitfld.long 0x00 16. " IRQS560 ,IRQS Status Bit 560" "Low,High"
bitfld.long 0x00 15. "  IRQS559 ,IRQS Status Bit 559" "Low,High"
bitfld.long 0x00 14. "  IRQS558 ,IRQS Status Bit 558" "Low,High"
textline "                               "
bitfld.long 0x00 13. " IRQS557 ,IRQS Status Bit 557" "Low,High"
bitfld.long 0x00 12. "  IRQS556 ,IRQS Status Bit 556" "Low,High"
bitfld.long 0x00 11. "  IRQS555 ,IRQS Status Bit 555" "Low,High"
textline "                               "
bitfld.long 0x00 10. " IRQS554 ,IRQS Status Bit 554" "Low,High"
bitfld.long 0x00 9. "  IRQS553 ,IRQS Status Bit 553" "Low,High"
bitfld.long 0x00 8. "  IRQS552 ,IRQS Status Bit 552" "Low,High"
textline "                               "
bitfld.long 0x00 7. " IRQS551 ,IRQS Status Bit 551" "Low,High"
bitfld.long 0x00 6. "  IRQS550 ,IRQS Status Bit 550" "Low,High"
bitfld.long 0x00 5. "  IRQS549 ,IRQS Status Bit 549" "Low,High"
textline "                               "
bitfld.long 0x00 4. " IRQS548 ,IRQS Status Bit 548" "Low,High"
bitfld.long 0x00 3. "  IRQS547 ,IRQS Status Bit 547" "Low,High"
bitfld.long 0x00 2. "  IRQS546 ,IRQS Status Bit 546" "Low,High"
textline "                               "
bitfld.long 0x00 1. " IRQS545 ,IRQS Status Bit 545" "Low,High"
bitfld.long 0x00 0. "  IRQS544 ,IRQS Status Bit 544" "Low,High"
else
rgroup.long 0x0D48++0x03
line.long 0x0 "GICD_SPISR17,Shared Peripheral Interrupt Status Register 17"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x13)
rgroup.long 0x0D4C++0x03
line.long 0x0 "GICD_SPISR18,Shared Peripheral Interrupt Status Register 18"
bitfld.long 0x00 31. " IRQS607 ,IRQS Status Bit 607" "Low,High"
bitfld.long 0x00 30. "  IRQS606 ,IRQS Status Bit 606" "Low,High"
bitfld.long 0x00 29. "  IRQS605 ,IRQS Status Bit 605" "Low,High"
textline "                               "
bitfld.long 0x00 28. " IRQS604 ,IRQS Status Bit 604" "Low,High"
bitfld.long 0x00 27. "  IRQS603 ,IRQS Status Bit 603" "Low,High"
bitfld.long 0x00 26. "  IRQS602 ,IRQS Status Bit 602" "Low,High"
textline "                               "
bitfld.long 0x00 25. " IRQS601 ,IRQS Status Bit 601" "Low,High"
bitfld.long 0x00 24. "  IRQS600 ,IRQS Status Bit 600" "Low,High"
bitfld.long 0x00 23. "  IRQS599 ,IRQS Status Bit 599" "Low,High"
textline "                               "
bitfld.long 0x00 22. " IRQS598 ,IRQS Status Bit 598" "Low,High"
bitfld.long 0x00 21. "  IRQS597 ,IRQS Status Bit 597" "Low,High"
bitfld.long 0x00 20. "  IRQS596 ,IRQS Status Bit 596" "Low,High"
textline "                               "
bitfld.long 0x00 19. " IRQS595 ,IRQS Status Bit 595" "Low,High"
bitfld.long 0x00 18. "  IRQS594 ,IRQS Status Bit 594" "Low,High"
bitfld.long 0x00 17. "  IRQS593 ,IRQS Status Bit 593" "Low,High"
textline "                               "
bitfld.long 0x00 16. " IRQS592 ,IRQS Status Bit 592" "Low,High"
bitfld.long 0x00 15. "  IRQS591 ,IRQS Status Bit 591" "Low,High"
bitfld.long 0x00 14. "  IRQS590 ,IRQS Status Bit 590" "Low,High"
textline "                               "
bitfld.long 0x00 13. " IRQS589 ,IRQS Status Bit 589" "Low,High"
bitfld.long 0x00 12. "  IRQS588 ,IRQS Status Bit 588" "Low,High"
bitfld.long 0x00 11. "  IRQS587 ,IRQS Status Bit 587" "Low,High"
textline "                               "
bitfld.long 0x00 10. " IRQS586 ,IRQS Status Bit 586" "Low,High"
bitfld.long 0x00 9. "  IRQS585 ,IRQS Status Bit 585" "Low,High"
bitfld.long 0x00 8. "  IRQS584 ,IRQS Status Bit 584" "Low,High"
textline "                               "
bitfld.long 0x00 7. " IRQS583 ,IRQS Status Bit 583" "Low,High"
bitfld.long 0x00 6. "  IRQS582 ,IRQS Status Bit 582" "Low,High"
bitfld.long 0x00 5. "  IRQS581 ,IRQS Status Bit 581" "Low,High"
textline "                               "
bitfld.long 0x00 4. " IRQS580 ,IRQS Status Bit 580" "Low,High"
bitfld.long 0x00 3. "  IRQS579 ,IRQS Status Bit 579" "Low,High"
bitfld.long 0x00 2. "  IRQS578 ,IRQS Status Bit 578" "Low,High"
textline "                               "
bitfld.long 0x00 1. " IRQS577 ,IRQS Status Bit 577" "Low,High"
bitfld.long 0x00 0. "  IRQS576 ,IRQS Status Bit 576" "Low,High"
else
rgroup.long 0x0D4C++0x03
line.long 0x0 "GICD_SPISR18,Shared Peripheral Interrupt Status Register 18"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x14)
rgroup.long 0x0D50++0x03
line.long 0x0 "GICD_SPISR19,Shared Peripheral Interrupt Status Register 19"
bitfld.long 0x00 31. " IRQS639 ,IRQS Status Bit 639" "Low,High"
bitfld.long 0x00 30. "  IRQS638 ,IRQS Status Bit 638" "Low,High"
bitfld.long 0x00 29. "  IRQS637 ,IRQS Status Bit 637" "Low,High"
textline "                               "
bitfld.long 0x00 28. " IRQS636 ,IRQS Status Bit 636" "Low,High"
bitfld.long 0x00 27. "  IRQS635 ,IRQS Status Bit 635" "Low,High"
bitfld.long 0x00 26. "  IRQS634 ,IRQS Status Bit 634" "Low,High"
textline "                               "
bitfld.long 0x00 25. " IRQS633 ,IRQS Status Bit 633" "Low,High"
bitfld.long 0x00 24. "  IRQS632 ,IRQS Status Bit 632" "Low,High"
bitfld.long 0x00 23. "  IRQS631 ,IRQS Status Bit 631" "Low,High"
textline "                               "
bitfld.long 0x00 22. " IRQS630 ,IRQS Status Bit 630" "Low,High"
bitfld.long 0x00 21. "  IRQS629 ,IRQS Status Bit 629" "Low,High"
bitfld.long 0x00 20. "  IRQS628 ,IRQS Status Bit 628" "Low,High"
textline "                               "
bitfld.long 0x00 19. " IRQS627 ,IRQS Status Bit 627" "Low,High"
bitfld.long 0x00 18. "  IRQS626 ,IRQS Status Bit 626" "Low,High"
bitfld.long 0x00 17. "  IRQS625 ,IRQS Status Bit 625" "Low,High"
textline "                               "
bitfld.long 0x00 16. " IRQS624 ,IRQS Status Bit 624" "Low,High"
bitfld.long 0x00 15. "  IRQS623 ,IRQS Status Bit 623" "Low,High"
bitfld.long 0x00 14. "  IRQS622 ,IRQS Status Bit 622" "Low,High"
textline "                               "
bitfld.long 0x00 13. " IRQS621 ,IRQS Status Bit 621" "Low,High"
bitfld.long 0x00 12. "  IRQS620 ,IRQS Status Bit 620" "Low,High"
bitfld.long 0x00 11. "  IRQS619 ,IRQS Status Bit 619" "Low,High"
textline "                               "
bitfld.long 0x00 10. " IRQS618 ,IRQS Status Bit 618" "Low,High"
bitfld.long 0x00 9. "  IRQS617 ,IRQS Status Bit 617" "Low,High"
bitfld.long 0x00 8. "  IRQS616 ,IRQS Status Bit 616" "Low,High"
textline "                               "
bitfld.long 0x00 7. " IRQS615 ,IRQS Status Bit 615" "Low,High"
bitfld.long 0x00 6. "  IRQS614 ,IRQS Status Bit 614" "Low,High"
bitfld.long 0x00 5. "  IRQS613 ,IRQS Status Bit 613" "Low,High"
textline "                               "
bitfld.long 0x00 4. " IRQS612 ,IRQS Status Bit 612" "Low,High"
bitfld.long 0x00 3. "  IRQS611 ,IRQS Status Bit 611" "Low,High"
bitfld.long 0x00 2. "  IRQS610 ,IRQS Status Bit 610" "Low,High"
textline "                               "
bitfld.long 0x00 1. " IRQS609 ,IRQS Status Bit 609" "Low,High"
bitfld.long 0x00 0. "  IRQS608 ,IRQS Status Bit 608" "Low,High"
else
rgroup.long 0x0D50++0x03
line.long 0x0 "GICD_SPISR19,Shared Peripheral Interrupt Status Register 19"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x15)
rgroup.long 0x0D54++0x03
line.long 0x0 "GICD_SPISR20,Shared Peripheral Interrupt Status Register 20"
bitfld.long 0x00 31. " IRQS671 ,IRQS Status Bit 671" "Low,High"
bitfld.long 0x00 30. "  IRQS670 ,IRQS Status Bit 670" "Low,High"
bitfld.long 0x00 29. "  IRQS669 ,IRQS Status Bit 669" "Low,High"
textline "                               "
bitfld.long 0x00 28. " IRQS668 ,IRQS Status Bit 668" "Low,High"
bitfld.long 0x00 27. "  IRQS667 ,IRQS Status Bit 667" "Low,High"
bitfld.long 0x00 26. "  IRQS666 ,IRQS Status Bit 666" "Low,High"
textline "                               "
bitfld.long 0x00 25. " IRQS665 ,IRQS Status Bit 665" "Low,High"
bitfld.long 0x00 24. "  IRQS664 ,IRQS Status Bit 664" "Low,High"
bitfld.long 0x00 23. "  IRQS663 ,IRQS Status Bit 663" "Low,High"
textline "                               "
bitfld.long 0x00 22. " IRQS662 ,IRQS Status Bit 662" "Low,High"
bitfld.long 0x00 21. "  IRQS661 ,IRQS Status Bit 661" "Low,High"
bitfld.long 0x00 20. "  IRQS660 ,IRQS Status Bit 660" "Low,High"
textline "                               "
bitfld.long 0x00 19. " IRQS659 ,IRQS Status Bit 659" "Low,High"
bitfld.long 0x00 18. "  IRQS658 ,IRQS Status Bit 658" "Low,High"
bitfld.long 0x00 17. "  IRQS657 ,IRQS Status Bit 657" "Low,High"
textline "                               "
bitfld.long 0x00 16. " IRQS656 ,IRQS Status Bit 656" "Low,High"
bitfld.long 0x00 15. "  IRQS655 ,IRQS Status Bit 655" "Low,High"
bitfld.long 0x00 14. "  IRQS654 ,IRQS Status Bit 654" "Low,High"
textline "                               "
bitfld.long 0x00 13. " IRQS653 ,IRQS Status Bit 653" "Low,High"
bitfld.long 0x00 12. "  IRQS652 ,IRQS Status Bit 652" "Low,High"
bitfld.long 0x00 11. "  IRQS651 ,IRQS Status Bit 651" "Low,High"
textline "                               "
bitfld.long 0x00 10. " IRQS650 ,IRQS Status Bit 650" "Low,High"
bitfld.long 0x00 9. "  IRQS649 ,IRQS Status Bit 649" "Low,High"
bitfld.long 0x00 8. "  IRQS648 ,IRQS Status Bit 648" "Low,High"
textline "                               "
bitfld.long 0x00 7. " IRQS647 ,IRQS Status Bit 647" "Low,High"
bitfld.long 0x00 6. "  IRQS646 ,IRQS Status Bit 646" "Low,High"
bitfld.long 0x00 5. "  IRQS645 ,IRQS Status Bit 645" "Low,High"
textline "                               "
bitfld.long 0x00 4. " IRQS644 ,IRQS Status Bit 644" "Low,High"
bitfld.long 0x00 3. "  IRQS643 ,IRQS Status Bit 643" "Low,High"
bitfld.long 0x00 2. "  IRQS642 ,IRQS Status Bit 642" "Low,High"
textline "                               "
bitfld.long 0x00 1. " IRQS641 ,IRQS Status Bit 641" "Low,High"
bitfld.long 0x00 0. "  IRQS640 ,IRQS Status Bit 640" "Low,High"
else
rgroup.long 0x0D54++0x03
line.long 0x0 "GICD_SPISR20,Shared Peripheral Interrupt Status Register 20"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x16)
rgroup.long 0x0D58++0x03
line.long 0x0 "GICD_SPISR21,Shared Peripheral Interrupt Status Register 21"
bitfld.long 0x00 31. " IRQS703 ,IRQS Status Bit 703" "Low,High"
bitfld.long 0x00 30. "  IRQS702 ,IRQS Status Bit 702" "Low,High"
bitfld.long 0x00 29. "  IRQS701 ,IRQS Status Bit 701" "Low,High"
textline "                               "
bitfld.long 0x00 28. " IRQS700 ,IRQS Status Bit 700" "Low,High"
bitfld.long 0x00 27. "  IRQS699 ,IRQS Status Bit 699" "Low,High"
bitfld.long 0x00 26. "  IRQS698 ,IRQS Status Bit 698" "Low,High"
textline "                               "
bitfld.long 0x00 25. " IRQS697 ,IRQS Status Bit 697" "Low,High"
bitfld.long 0x00 24. "  IRQS696 ,IRQS Status Bit 696" "Low,High"
bitfld.long 0x00 23. "  IRQS695 ,IRQS Status Bit 695" "Low,High"
textline "                               "
bitfld.long 0x00 22. " IRQS694 ,IRQS Status Bit 694" "Low,High"
bitfld.long 0x00 21. "  IRQS693 ,IRQS Status Bit 693" "Low,High"
bitfld.long 0x00 20. "  IRQS692 ,IRQS Status Bit 692" "Low,High"
textline "                               "
bitfld.long 0x00 19. " IRQS691 ,IRQS Status Bit 691" "Low,High"
bitfld.long 0x00 18. "  IRQS690 ,IRQS Status Bit 690" "Low,High"
bitfld.long 0x00 17. "  IRQS689 ,IRQS Status Bit 689" "Low,High"
textline "                               "
bitfld.long 0x00 16. " IRQS688 ,IRQS Status Bit 688" "Low,High"
bitfld.long 0x00 15. "  IRQS687 ,IRQS Status Bit 687" "Low,High"
bitfld.long 0x00 14. "  IRQS686 ,IRQS Status Bit 686" "Low,High"
textline "                               "
bitfld.long 0x00 13. " IRQS685 ,IRQS Status Bit 685" "Low,High"
bitfld.long 0x00 12. "  IRQS684 ,IRQS Status Bit 684" "Low,High"
bitfld.long 0x00 11. "  IRQS683 ,IRQS Status Bit 683" "Low,High"
textline "                               "
bitfld.long 0x00 10. " IRQS682 ,IRQS Status Bit 682" "Low,High"
bitfld.long 0x00 9. "  IRQS681 ,IRQS Status Bit 681" "Low,High"
bitfld.long 0x00 8. "  IRQS680 ,IRQS Status Bit 680" "Low,High"
textline "                               "
bitfld.long 0x00 7. " IRQS679 ,IRQS Status Bit 679" "Low,High"
bitfld.long 0x00 6. "  IRQS678 ,IRQS Status Bit 678" "Low,High"
bitfld.long 0x00 5. "  IRQS677 ,IRQS Status Bit 677" "Low,High"
textline "                               "
bitfld.long 0x00 4. " IRQS676 ,IRQS Status Bit 676" "Low,High"
bitfld.long 0x00 3. "  IRQS675 ,IRQS Status Bit 675" "Low,High"
bitfld.long 0x00 2. "  IRQS674 ,IRQS Status Bit 674" "Low,High"
textline "                               "
bitfld.long 0x00 1. " IRQS673 ,IRQS Status Bit 673" "Low,High"
bitfld.long 0x00 0. "  IRQS672 ,IRQS Status Bit 672" "Low,High"
else
rgroup.long 0x0D58++0x03
line.long 0x0 "GICD_SPISR21,Shared Peripheral Interrupt Status Register 21"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x17)
rgroup.long 0x0D5C++0x03
line.long 0x0 "GICD_SPISR22,Shared Peripheral Interrupt Status Register 22"
bitfld.long 0x00 31. " IRQS735 ,IRQS Status Bit 735" "Low,High"
bitfld.long 0x00 30. "  IRQS734 ,IRQS Status Bit 734" "Low,High"
bitfld.long 0x00 29. "  IRQS733 ,IRQS Status Bit 733" "Low,High"
textline "                               "
bitfld.long 0x00 28. " IRQS732 ,IRQS Status Bit 732" "Low,High"
bitfld.long 0x00 27. "  IRQS731 ,IRQS Status Bit 731" "Low,High"
bitfld.long 0x00 26. "  IRQS730 ,IRQS Status Bit 730" "Low,High"
textline "                               "
bitfld.long 0x00 25. " IRQS729 ,IRQS Status Bit 729" "Low,High"
bitfld.long 0x00 24. "  IRQS728 ,IRQS Status Bit 728" "Low,High"
bitfld.long 0x00 23. "  IRQS727 ,IRQS Status Bit 727" "Low,High"
textline "                               "
bitfld.long 0x00 22. " IRQS726 ,IRQS Status Bit 726" "Low,High"
bitfld.long 0x00 21. "  IRQS725 ,IRQS Status Bit 725" "Low,High"
bitfld.long 0x00 20. "  IRQS724 ,IRQS Status Bit 724" "Low,High"
textline "                               "
bitfld.long 0x00 19. " IRQS723 ,IRQS Status Bit 723" "Low,High"
bitfld.long 0x00 18. "  IRQS722 ,IRQS Status Bit 722" "Low,High"
bitfld.long 0x00 17. "  IRQS721 ,IRQS Status Bit 721" "Low,High"
textline "                               "
bitfld.long 0x00 16. " IRQS720 ,IRQS Status Bit 720" "Low,High"
bitfld.long 0x00 15. "  IRQS719 ,IRQS Status Bit 719" "Low,High"
bitfld.long 0x00 14. "  IRQS718 ,IRQS Status Bit 718" "Low,High"
textline "                               "
bitfld.long 0x00 13. " IRQS717 ,IRQS Status Bit 717" "Low,High"
bitfld.long 0x00 12. "  IRQS716 ,IRQS Status Bit 716" "Low,High"
bitfld.long 0x00 11. "  IRQS715 ,IRQS Status Bit 715" "Low,High"
textline "                               "
bitfld.long 0x00 10. " IRQS714 ,IRQS Status Bit 714" "Low,High"
bitfld.long 0x00 9. "  IRQS713 ,IRQS Status Bit 713" "Low,High"
bitfld.long 0x00 8. "  IRQS712 ,IRQS Status Bit 712" "Low,High"
textline "                               "
bitfld.long 0x00 7. " IRQS711 ,IRQS Status Bit 711" "Low,High"
bitfld.long 0x00 6. "  IRQS710 ,IRQS Status Bit 710" "Low,High"
bitfld.long 0x00 5. "  IRQS709 ,IRQS Status Bit 709" "Low,High"
textline "                               "
bitfld.long 0x00 4. " IRQS708 ,IRQS Status Bit 708" "Low,High"
bitfld.long 0x00 3. "  IRQS707 ,IRQS Status Bit 707" "Low,High"
bitfld.long 0x00 2. "  IRQS706 ,IRQS Status Bit 706" "Low,High"
textline "                               "
bitfld.long 0x00 1. " IRQS705 ,IRQS Status Bit 705" "Low,High"
bitfld.long 0x00 0. "  IRQS704 ,IRQS Status Bit 704" "Low,High"
else
rgroup.long 0x0D5C++0x03
line.long 0x0 "GICD_SPISR22,Shared Peripheral Interrupt Status Register 22"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x18)
rgroup.long 0x060++0x03
line.long 0x0 "GICD_SPISR23,Shared Peripheral Interrupt Status Register 23"
bitfld.long 0x00 31. " IRQS767 ,IRQS Status Bit 767" "Low,High"
bitfld.long 0x00 30. "  IRQS766 ,IRQS Status Bit 766" "Low,High"
bitfld.long 0x00 29. "  IRQS765 ,IRQS Status Bit 765" "Low,High"
textline "                               "
bitfld.long 0x00 28. " IRQS764 ,IRQS Status Bit 764" "Low,High"
bitfld.long 0x00 27. "  IRQS763 ,IRQS Status Bit 763" "Low,High"
bitfld.long 0x00 26. "  IRQS762 ,IRQS Status Bit 762" "Low,High"
textline "                               "
bitfld.long 0x00 25. " IRQS761 ,IRQS Status Bit 761" "Low,High"
bitfld.long 0x00 24. "  IRQS760 ,IRQS Status Bit 760" "Low,High"
bitfld.long 0x00 23. "  IRQS759 ,IRQS Status Bit 759" "Low,High"
textline "                               "
bitfld.long 0x00 22. " IRQS758 ,IRQS Status Bit 758" "Low,High"
bitfld.long 0x00 21. "  IRQS757 ,IRQS Status Bit 757" "Low,High"
bitfld.long 0x00 20. "  IRQS756 ,IRQS Status Bit 756" "Low,High"
textline "                               "
bitfld.long 0x00 19. " IRQS755 ,IRQS Status Bit 755" "Low,High"
bitfld.long 0x00 18. "  IRQS754 ,IRQS Status Bit 754" "Low,High"
bitfld.long 0x00 17. "  IRQS753 ,IRQS Status Bit 753" "Low,High"
textline "                               "
bitfld.long 0x00 16. " IRQS752 ,IRQS Status Bit 752" "Low,High"
bitfld.long 0x00 15. "  IRQS751 ,IRQS Status Bit 751" "Low,High"
bitfld.long 0x00 14. "  IRQS750 ,IRQS Status Bit 750" "Low,High"
textline "                               "
bitfld.long 0x00 13. " IRQS749 ,IRQS Status Bit 749" "Low,High"
bitfld.long 0x00 12. "  IRQS748 ,IRQS Status Bit 748" "Low,High"
bitfld.long 0x00 11. "  IRQS747 ,IRQS Status Bit 747" "Low,High"
textline "                               "
bitfld.long 0x00 10. " IRQS746 ,IRQS Status Bit 746" "Low,High"
bitfld.long 0x00 9. "  IRQS745 ,IRQS Status Bit 745" "Low,High"
bitfld.long 0x00 8. "  IRQS744 ,IRQS Status Bit 744" "Low,High"
textline "                               "
bitfld.long 0x00 7. " IRQS743 ,IRQS Status Bit 743" "Low,High"
bitfld.long 0x00 6. "  IRQS742 ,IRQS Status Bit 742" "Low,High"
bitfld.long 0x00 5. "  IRQS741 ,IRQS Status Bit 741" "Low,High"
textline "                               "
bitfld.long 0x00 4. " IRQS740 ,IRQS Status Bit 740" "Low,High"
bitfld.long 0x00 3. "  IRQS739 ,IRQS Status Bit 739" "Low,High"
bitfld.long 0x00 2. "  IRQS738 ,IRQS Status Bit 738" "Low,High"
textline "                               "
bitfld.long 0x00 1. " IRQS737 ,IRQS Status Bit 737" "Low,High"
bitfld.long 0x00 0. "  IRQS736 ,IRQS Status Bit 736" "Low,High"
else
rgroup.long 0x0D60++0x03
line.long 0x0 "GICD_SPISR23,Shared Peripheral Interrupt Status Register 23"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x19)
rgroup.long 0x0D64++0x03
line.long 0x0 "GICD_SPISR24,Shared Peripheral Interrupt Status Register 24"
bitfld.long 0x00 31. " IRQS799 ,IRQS Status Bit 799" "Low,High"
bitfld.long 0x00 30. "  IRQS798 ,IRQS Status Bit 798" "Low,High"
bitfld.long 0x00 29. "  IRQS797 ,IRQS Status Bit 797" "Low,High"
textline "                               "
bitfld.long 0x00 28. " IRQS796 ,IRQS Status Bit 796" "Low,High"
bitfld.long 0x00 27. "  IRQS795 ,IRQS Status Bit 795" "Low,High"
bitfld.long 0x00 26. "  IRQS794 ,IRQS Status Bit 794" "Low,High"
textline "                               "
bitfld.long 0x00 25. " IRQS793 ,IRQS Status Bit 793" "Low,High"
bitfld.long 0x00 24. "  IRQS792 ,IRQS Status Bit 792" "Low,High"
bitfld.long 0x00 23. "  IRQS791 ,IRQS Status Bit 791" "Low,High"
textline "                               "
bitfld.long 0x00 22. " IRQS790 ,IRQS Status Bit 790" "Low,High"
bitfld.long 0x00 21. "  IRQS789 ,IRQS Status Bit 789" "Low,High"
bitfld.long 0x00 20. "  IRQS788 ,IRQS Status Bit 788" "Low,High"
textline "                               "
bitfld.long 0x00 19. " IRQS787 ,IRQS Status Bit 787" "Low,High"
bitfld.long 0x00 18. "  IRQS786 ,IRQS Status Bit 786" "Low,High"
bitfld.long 0x00 17. "  IRQS785 ,IRQS Status Bit 785" "Low,High"
textline "                               "
bitfld.long 0x00 16. " IRQS784 ,IRQS Status Bit 784" "Low,High"
bitfld.long 0x00 15. "  IRQS783 ,IRQS Status Bit 783" "Low,High"
bitfld.long 0x00 14. "  IRQS782 ,IRQS Status Bit 782" "Low,High"
textline "                               "
bitfld.long 0x00 13. " IRQS781 ,IRQS Status Bit 781" "Low,High"
bitfld.long 0x00 12. "  IRQS780 ,IRQS Status Bit 780" "Low,High"
bitfld.long 0x00 11. "  IRQS779 ,IRQS Status Bit 779" "Low,High"
textline "                               "
bitfld.long 0x00 10. " IRQS778 ,IRQS Status Bit 778" "Low,High"
bitfld.long 0x00 9. "  IRQS777 ,IRQS Status Bit 777" "Low,High"
bitfld.long 0x00 8. "  IRQS776 ,IRQS Status Bit 776" "Low,High"
textline "                               "
bitfld.long 0x00 7. " IRQS775 ,IRQS Status Bit 775" "Low,High"
bitfld.long 0x00 6. "  IRQS774 ,IRQS Status Bit 774" "Low,High"
bitfld.long 0x00 5. "  IRQS773 ,IRQS Status Bit 773" "Low,High"
textline "                               "
bitfld.long 0x00 4. " IRQS772 ,IRQS Status Bit 772" "Low,High"
bitfld.long 0x00 3. "  IRQS771 ,IRQS Status Bit 771" "Low,High"
bitfld.long 0x00 2. "  IRQS770 ,IRQS Status Bit 770" "Low,High"
textline "                               "
bitfld.long 0x00 1. " IRQS769 ,IRQS Status Bit 769" "Low,High"
bitfld.long 0x00 0. "  IRQS768 ,IRQS Status Bit 768" "Low,High"
else
rgroup.long 0x0D64++0x03
line.long 0x0 "GICD_SPISR24,Shared Peripheral Interrupt Status Register 24"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1A)
rgroup.long 0x0D68++0x03
line.long 0x0 "GICD_SPISR25,Shared Peripheral Interrupt Status Register 25"
bitfld.long 0x00 31. " IRQS831 ,IRQS Status Bit 831" "Low,High"
bitfld.long 0x00 30. "  IRQS830 ,IRQS Status Bit 830" "Low,High"
bitfld.long 0x00 29. "  IRQS829 ,IRQS Status Bit 829" "Low,High"
textline "                               "
bitfld.long 0x00 28. " IRQS828 ,IRQS Status Bit 828" "Low,High"
bitfld.long 0x00 27. "  IRQS827 ,IRQS Status Bit 827" "Low,High"
bitfld.long 0x00 26. "  IRQS826 ,IRQS Status Bit 826" "Low,High"
textline "                               "
bitfld.long 0x00 25. " IRQS825 ,IRQS Status Bit 825" "Low,High"
bitfld.long 0x00 24. "  IRQS824 ,IRQS Status Bit 824" "Low,High"
bitfld.long 0x00 23. "  IRQS823 ,IRQS Status Bit 823" "Low,High"
textline "                               "
bitfld.long 0x00 22. " IRQS822 ,IRQS Status Bit 822" "Low,High"
bitfld.long 0x00 21. "  IRQS821 ,IRQS Status Bit 821" "Low,High"
bitfld.long 0x00 20. "  IRQS820 ,IRQS Status Bit 820" "Low,High"
textline "                               "
bitfld.long 0x00 19. " IRQS819 ,IRQS Status Bit 819" "Low,High"
bitfld.long 0x00 18. "  IRQS818 ,IRQS Status Bit 818" "Low,High"
bitfld.long 0x00 17. "  IRQS817 ,IRQS Status Bit 817" "Low,High"
textline "                               "
bitfld.long 0x00 16. " IRQS816 ,IRQS Status Bit 816" "Low,High"
bitfld.long 0x00 15. "  IRQS815 ,IRQS Status Bit 815" "Low,High"
bitfld.long 0x00 14. "  IRQS814 ,IRQS Status Bit 814" "Low,High"
textline "                               "
bitfld.long 0x00 13. " IRQS813 ,IRQS Status Bit 813" "Low,High"
bitfld.long 0x00 12. "  IRQS812 ,IRQS Status Bit 812" "Low,High"
bitfld.long 0x00 11. "  IRQS811 ,IRQS Status Bit 811" "Low,High"
textline "                               "
bitfld.long 0x00 10. " IRQS810 ,IRQS Status Bit 810" "Low,High"
bitfld.long 0x00 9. "  IRQS809 ,IRQS Status Bit 809" "Low,High"
bitfld.long 0x00 8. "  IRQS808 ,IRQS Status Bit 808" "Low,High"
textline "                               "
bitfld.long 0x00 7. " IRQS807 ,IRQS Status Bit 807" "Low,High"
bitfld.long 0x00 6. "  IRQS806 ,IRQS Status Bit 806" "Low,High"
bitfld.long 0x00 5. "  IRQS805 ,IRQS Status Bit 805" "Low,High"
textline "                               "
bitfld.long 0x00 4. " IRQS804 ,IRQS Status Bit 804" "Low,High"
bitfld.long 0x00 3. "  IRQS803 ,IRQS Status Bit 803" "Low,High"
bitfld.long 0x00 2. "  IRQS802 ,IRQS Status Bit 802" "Low,High"
textline "                               "
bitfld.long 0x00 1. " IRQS801 ,IRQS Status Bit 801" "Low,High"
bitfld.long 0x00 0. "  IRQS800 ,IRQS Status Bit 800" "Low,High"
else
rgroup.long 0x0D68++0x03
line.long 0x0 "GICD_SPISR25,Shared Peripheral Interrupt Status Register 25"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1B)
rgroup.long 0x0D6C++0x03
line.long 0x0 "GICD_SPISR26,Shared Peripheral Interrupt Status Register 26"
bitfld.long 0x00 31. " IRQS863 ,IRQS Status Bit 863" "Low,High"
bitfld.long 0x00 30. "  IRQS862 ,IRQS Status Bit 862" "Low,High"
bitfld.long 0x00 29. "  IRQS861 ,IRQS Status Bit 861" "Low,High"
textline "                               "
bitfld.long 0x00 28. " IRQS860 ,IRQS Status Bit 860" "Low,High"
bitfld.long 0x00 27. "  IRQS859 ,IRQS Status Bit 859" "Low,High"
bitfld.long 0x00 26. "  IRQS858 ,IRQS Status Bit 858" "Low,High"
textline "                               "
bitfld.long 0x00 25. " IRQS857 ,IRQS Status Bit 857" "Low,High"
bitfld.long 0x00 24. "  IRQS856 ,IRQS Status Bit 856" "Low,High"
bitfld.long 0x00 23. "  IRQS855 ,IRQS Status Bit 855" "Low,High"
textline "                               "
bitfld.long 0x00 22. " IRQS854 ,IRQS Status Bit 854" "Low,High"
bitfld.long 0x00 21. "  IRQS853 ,IRQS Status Bit 853" "Low,High"
bitfld.long 0x00 20. "  IRQS852 ,IRQS Status Bit 852" "Low,High"
textline "                               "
bitfld.long 0x00 19. " IRQS851 ,IRQS Status Bit 851" "Low,High"
bitfld.long 0x00 18. "  IRQS850 ,IRQS Status Bit 850" "Low,High"
bitfld.long 0x00 17. "  IRQS849 ,IRQS Status Bit 849" "Low,High"
textline "                               "
bitfld.long 0x00 16. " IRQS848 ,IRQS Status Bit 848" "Low,High"
bitfld.long 0x00 15. "  IRQS847 ,IRQS Status Bit 847" "Low,High"
bitfld.long 0x00 14. "  IRQS846 ,IRQS Status Bit 846" "Low,High"
textline "                               "
bitfld.long 0x00 13. " IRQS845 ,IRQS Status Bit 845" "Low,High"
bitfld.long 0x00 12. "  IRQS844 ,IRQS Status Bit 844" "Low,High"
bitfld.long 0x00 11. "  IRQS843 ,IRQS Status Bit 843" "Low,High"
textline "                               "
bitfld.long 0x00 10. " IRQS842 ,IRQS Status Bit 842" "Low,High"
bitfld.long 0x00 9. "  IRQS841 ,IRQS Status Bit 841" "Low,High"
bitfld.long 0x00 8. "  IRQS840 ,IRQS Status Bit 840" "Low,High"
textline "                               "
bitfld.long 0x00 7. " IRQS839 ,IRQS Status Bit 839" "Low,High"
bitfld.long 0x00 6. "  IRQS838 ,IRQS Status Bit 838" "Low,High"
bitfld.long 0x00 5. "  IRQS837 ,IRQS Status Bit 837" "Low,High"
textline "                               "
bitfld.long 0x00 4. " IRQS836 ,IRQS Status Bit 836" "Low,High"
bitfld.long 0x00 3. "  IRQS835 ,IRQS Status Bit 835" "Low,High"
bitfld.long 0x00 2. "  IRQS834 ,IRQS Status Bit 834" "Low,High"
textline "                               "
bitfld.long 0x00 1. " IRQS833 ,IRQS Status Bit 833" "Low,High"
bitfld.long 0x00 0. "  IRQS832 ,IRQS Status Bit 832" "Low,High"
else
rgroup.long 0x0D6C++0x03
line.long 0x0 "GICD_SPISR26,Shared Peripheral Interrupt Status Register 26"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1C)
rgroup.long 0x0D70++0x03
line.long 0x0 "GICD_SPISR27,Shared Peripheral Interrupt Status Register 27"
bitfld.long 0x00 31. " IRQS895 ,IRQS Status Bit 895" "Low,High"
bitfld.long 0x00 30. "  IRQS894 ,IRQS Status Bit 894" "Low,High"
bitfld.long 0x00 29. "  IRQS893 ,IRQS Status Bit 893" "Low,High"
textline "                               "
bitfld.long 0x00 28. " IRQS892 ,IRQS Status Bit 892" "Low,High"
bitfld.long 0x00 27. "  IRQS891 ,IRQS Status Bit 891" "Low,High"
bitfld.long 0x00 26. "  IRQS890 ,IRQS Status Bit 890" "Low,High"
textline "                               "
bitfld.long 0x00 25. " IRQS889 ,IRQS Status Bit 889" "Low,High"
bitfld.long 0x00 24. "  IRQS888 ,IRQS Status Bit 888" "Low,High"
bitfld.long 0x00 23. "  IRQS887 ,IRQS Status Bit 887" "Low,High"
textline "                               "
bitfld.long 0x00 22. " IRQS886 ,IRQS Status Bit 886" "Low,High"
bitfld.long 0x00 21. "  IRQS885 ,IRQS Status Bit 885" "Low,High"
bitfld.long 0x00 20. "  IRQS884 ,IRQS Status Bit 884" "Low,High"
textline "                               "
bitfld.long 0x00 19. " IRQS883 ,IRQS Status Bit 883" "Low,High"
bitfld.long 0x00 18. "  IRQS882 ,IRQS Status Bit 882" "Low,High"
bitfld.long 0x00 17. "  IRQS881 ,IRQS Status Bit 881" "Low,High"
textline "                               "
bitfld.long 0x00 16. " IRQS880 ,IRQS Status Bit 880" "Low,High"
bitfld.long 0x00 15. "  IRQS879 ,IRQS Status Bit 879" "Low,High"
bitfld.long 0x00 14. "  IRQS878 ,IRQS Status Bit 878" "Low,High"
textline "                               "
bitfld.long 0x00 13. " IRQS877 ,IRQS Status Bit 877" "Low,High"
bitfld.long 0x00 12. "  IRQS876 ,IRQS Status Bit 876" "Low,High"
bitfld.long 0x00 11. "  IRQS875 ,IRQS Status Bit 875" "Low,High"
textline "                               "
bitfld.long 0x00 10. " IRQS874 ,IRQS Status Bit 874" "Low,High"
bitfld.long 0x00 9. "  IRQS873 ,IRQS Status Bit 873" "Low,High"
bitfld.long 0x00 8. "  IRQS872 ,IRQS Status Bit 872" "Low,High"
textline "                               "
bitfld.long 0x00 7. " IRQS871 ,IRQS Status Bit 871" "Low,High"
bitfld.long 0x00 6. "  IRQS870 ,IRQS Status Bit 870" "Low,High"
bitfld.long 0x00 5. "  IRQS869 ,IRQS Status Bit 869" "Low,High"
textline "                               "
bitfld.long 0x00 4. " IRQS868 ,IRQS Status Bit 868" "Low,High"
bitfld.long 0x00 3. "  IRQS867 ,IRQS Status Bit 867" "Low,High"
bitfld.long 0x00 2. "  IRQS866 ,IRQS Status Bit 866" "Low,High"
textline "                               "
bitfld.long 0x00 1. " IRQS865 ,IRQS Status Bit 865" "Low,High"
bitfld.long 0x00 0. "  IRQS864 ,IRQS Status Bit 864" "Low,High"
else
rgroup.long 0x0D70++0x03
line.long 0x0 "GICD_SPISR27,Shared Peripheral Interrupt Status Register 27"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1D)
rgroup.long 0x0D74++0x03
line.long 0x0 "GICD_SPISR28,Shared Peripheral Interrupt Status Register 28"
bitfld.long 0x00 31. " IRQS927 ,IRQS Status Bit 927" "Low,High"
bitfld.long 0x00 30. "  IRQS926 ,IRQS Status Bit 926" "Low,High"
bitfld.long 0x00 29. "  IRQS925 ,IRQS Status Bit 925" "Low,High"
textline "                               "
bitfld.long 0x00 28. " IRQS924 ,IRQS Status Bit 924" "Low,High"
bitfld.long 0x00 27. "  IRQS923 ,IRQS Status Bit 923" "Low,High"
bitfld.long 0x00 26. "  IRQS922 ,IRQS Status Bit 922" "Low,High"
textline "                               "
bitfld.long 0x00 25. " IRQS921 ,IRQS Status Bit 921" "Low,High"
bitfld.long 0x00 24. "  IRQS920 ,IRQS Status Bit 920" "Low,High"
bitfld.long 0x00 23. "  IRQS919 ,IRQS Status Bit 919" "Low,High"
textline "                               "
bitfld.long 0x00 22. " IRQS918 ,IRQS Status Bit 918" "Low,High"
bitfld.long 0x00 21. "  IRQS917 ,IRQS Status Bit 917" "Low,High"
bitfld.long 0x00 20. "  IRQS916 ,IRQS Status Bit 916" "Low,High"
textline "                               "
bitfld.long 0x00 19. " IRQS915 ,IRQS Status Bit 915" "Low,High"
bitfld.long 0x00 18. "  IRQS914 ,IRQS Status Bit 914" "Low,High"
bitfld.long 0x00 17. "  IRQS913 ,IRQS Status Bit 913" "Low,High"
textline "                               "
bitfld.long 0x00 16. " IRQS912 ,IRQS Status Bit 912" "Low,High"
bitfld.long 0x00 15. "  IRQS911 ,IRQS Status Bit 911" "Low,High"
bitfld.long 0x00 14. "  IRQS910 ,IRQS Status Bit 910" "Low,High"
textline "                               "
bitfld.long 0x00 13. " IRQS909 ,IRQS Status Bit 909" "Low,High"
bitfld.long 0x00 12. "  IRQS908 ,IRQS Status Bit 908" "Low,High"
bitfld.long 0x00 11. "  IRQS907 ,IRQS Status Bit 907" "Low,High"
textline "                               "
bitfld.long 0x00 10. " IRQS906 ,IRQS Status Bit 906" "Low,High"
bitfld.long 0x00 9. "  IRQS905 ,IRQS Status Bit 905" "Low,High"
bitfld.long 0x00 8. "  IRQS904 ,IRQS Status Bit 904" "Low,High"
textline "                               "
bitfld.long 0x00 7. " IRQS903 ,IRQS Status Bit 903" "Low,High"
bitfld.long 0x00 6. "  IRQS902 ,IRQS Status Bit 902" "Low,High"
bitfld.long 0x00 5. "  IRQS901 ,IRQS Status Bit 901" "Low,High"
textline "                               "
bitfld.long 0x00 4. " IRQS900 ,IRQS Status Bit 900" "Low,High"
bitfld.long 0x00 3. "  IRQS899 ,IRQS Status Bit 899" "Low,High"
bitfld.long 0x00 2. "  IRQS898 ,IRQS Status Bit 898" "Low,High"
textline "                               "
bitfld.long 0x00 1. " IRQS897 ,IRQS Status Bit 897" "Low,High"
bitfld.long 0x00 0. "  IRQS896 ,IRQS Status Bit 896" "Low,High"
else
rgroup.long 0x0D74++0x03
line.long 0x0 "GICD_SPISR28,Shared Peripheral Interrupt Status Register 28"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1E)
rgroup.long 0x0D78++0x03
line.long 0x0 "GICD_SPISR29,Shared Peripheral Interrupt Status Register 29"
bitfld.long 0x00 31. " IRQS959 ,IRQS Status Bit 959" "Low,High"
bitfld.long 0x00 30. "  IRQS958 ,IRQS Status Bit 958" "Low,High"
bitfld.long 0x00 29. "  IRQS957 ,IRQS Status Bit 957" "Low,High"
textline "                               "
bitfld.long 0x00 28. " IRQS956 ,IRQS Status Bit 956" "Low,High"
bitfld.long 0x00 27. "  IRQS955 ,IRQS Status Bit 955" "Low,High"
bitfld.long 0x00 26. "  IRQS954 ,IRQS Status Bit 954" "Low,High"
textline "                               "
bitfld.long 0x00 25. " IRQS953 ,IRQS Status Bit 953" "Low,High"
bitfld.long 0x00 24. "  IRQS952 ,IRQS Status Bit 952" "Low,High"
bitfld.long 0x00 23. "  IRQS951 ,IRQS Status Bit 951" "Low,High"
textline "                               "
bitfld.long 0x00 22. " IRQS950 ,IRQS Status Bit 950" "Low,High"
bitfld.long 0x00 21. "  IRQS949 ,IRQS Status Bit 949" "Low,High"
bitfld.long 0x00 20. "  IRQS948 ,IRQS Status Bit 948" "Low,High"
textline "                               "
bitfld.long 0x00 19. " IRQS947 ,IRQS Status Bit 947" "Low,High"
bitfld.long 0x00 18. "  IRQS946 ,IRQS Status Bit 946" "Low,High"
bitfld.long 0x00 17. "  IRQS945 ,IRQS Status Bit 945" "Low,High"
textline "                               "
bitfld.long 0x00 16. " IRQS944 ,IRQS Status Bit 944" "Low,High"
bitfld.long 0x00 15. "  IRQS943 ,IRQS Status Bit 943" "Low,High"
bitfld.long 0x00 14. "  IRQS942 ,IRQS Status Bit 942" "Low,High"
textline "                               "
bitfld.long 0x00 13. " IRQS941 ,IRQS Status Bit 941" "Low,High"
bitfld.long 0x00 12. "  IRQS940 ,IRQS Status Bit 940" "Low,High"
bitfld.long 0x00 11. "  IRQS939 ,IRQS Status Bit 939" "Low,High"
textline "                               "
bitfld.long 0x00 10. " IRQS938 ,IRQS Status Bit 938" "Low,High"
bitfld.long 0x00 9. "  IRQS937 ,IRQS Status Bit 937" "Low,High"
bitfld.long 0x00 8. "  IRQS936 ,IRQS Status Bit 936" "Low,High"
textline "                               "
bitfld.long 0x00 7. " IRQS935 ,IRQS Status Bit 935" "Low,High"
bitfld.long 0x00 6. "  IRQS934 ,IRQS Status Bit 934" "Low,High"
bitfld.long 0x00 5. "  IRQS933 ,IRQS Status Bit 933" "Low,High"
textline "                               "
bitfld.long 0x00 4. " IRQS932 ,IRQS Status Bit 932" "Low,High"
bitfld.long 0x00 3. "  IRQS931 ,IRQS Status Bit 931" "Low,High"
bitfld.long 0x00 2. "  IRQS930 ,IRQS Status Bit 930" "Low,High"
textline "                               "
bitfld.long 0x00 1. " IRQS929 ,IRQS Status Bit 929" "Low,High"
bitfld.long 0x00 0. "  IRQS928 ,IRQS Status Bit 928" "Low,High"
else
rgroup.long 0x0D78++0x03
line.long 0x0 "GICD_SPISR29,Shared Peripheral Interrupt Status Register 29"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1F)
rgroup.long 0x0D7C++0x03
line.long 0x0 "GICD_SPISR30,Shared Peripheral Interrupt Status Register 30"
bitfld.long 0x00 27. " IRQS987 ,IRQS Status Bit 987" "Low,High"
bitfld.long 0x00 26. "  IRQS986 ,IRQS Status Bit 986" "Low,High"
textline "                               "
bitfld.long 0x00 25. " IRQS985 ,IRQS Status Bit 985" "Low,High"
bitfld.long 0x00 24. "  IRQS984 ,IRQS Status Bit 984" "Low,High"
bitfld.long 0x00 23. "  IRQS983 ,IRQS Status Bit 983" "Low,High"
textline "                               "
bitfld.long 0x00 22. " IRQS982 ,IRQS Status Bit 982" "Low,High"
bitfld.long 0x00 21. "  IRQS981 ,IRQS Status Bit 981" "Low,High"
bitfld.long 0x00 20. "  IRQS980 ,IRQS Status Bit 980" "Low,High"
textline "                               "
bitfld.long 0x00 19. " IRQS979 ,IRQS Status Bit 979" "Low,High"
bitfld.long 0x00 18. "  IRQS978 ,IRQS Status Bit 978" "Low,High"
bitfld.long 0x00 17. "  IRQS977 ,IRQS Status Bit 977" "Low,High"
textline "                               "
bitfld.long 0x00 16. " IRQS976 ,IRQS Status Bit 976" "Low,High"
bitfld.long 0x00 15. "  IRQS975 ,IRQS Status Bit 975" "Low,High"
bitfld.long 0x00 14. "  IRQS974 ,IRQS Status Bit 974" "Low,High"
textline "                               "
bitfld.long 0x00 13. " IRQS973 ,IRQS Status Bit 973" "Low,High"
bitfld.long 0x00 12. "  IRQS972 ,IRQS Status Bit 972" "Low,High"
bitfld.long 0x00 11. "  IRQS971 ,IRQS Status Bit 971" "Low,High"
textline "                               "
bitfld.long 0x00 10. " IRQS970 ,IRQS Status Bit 970" "Low,High"
bitfld.long 0x00 9. "  IRQS969 ,IRQS Status Bit 969" "Low,High"
bitfld.long 0x00 8. "  IRQS968 ,IRQS Status Bit 968" "Low,High"
textline "                               "
bitfld.long 0x00 7. " IRQS967 ,IRQS Status Bit 967" "Low,High"
bitfld.long 0x00 6. "  IRQS966 ,IRQS Status Bit 966" "Low,High"
bitfld.long 0x00 5. "  IRQS965 ,IRQS Status Bit 965" "Low,High"
textline "                               "
bitfld.long 0x00 4. " IRQS964 ,IRQS Status Bit 964" "Low,High"
bitfld.long 0x00 3. "  IRQS963 ,IRQS Status Bit 963" "Low,High"
bitfld.long 0x00 2. "  IRQS962 ,IRQS Status Bit 962" "Low,High"
textline "                               "
bitfld.long 0x00 1. " IRQS961 ,IRQS Status Bit 961" "Low,High"
bitfld.long 0x00 0. "  IRQS960 ,IRQS Status Bit 960" "Low,High"
else
rgroup.long 0x0D7C++0x03
line.long 0x0 "GICD_SPISR30,Shared Peripheral Interrupt Status Register 30"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
tree.end
width 25.
tree "Software Generated Interrupt"
if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x400)==0x400)
wgroup.long 0x0F00++0x03
line.long 0x00 "GICD_SGIR,Software Generated Interrupt Register"
bitfld.long 0x00 24.--25. " TLF           ,Target List Filter" "TargetList,All CPUs,Request CPU,?..."
hexmask.long.byte 0x00 16.--23. 1. "  CPUTL         ,CPU Target List"
textline "                                  "
bitfld.long 0x00 15. " NSATT         ,NSATT" "Secure,Non-secure"
bitfld.long 0x00 0.--3. "   SGINTID       ,SGI Interrupt ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
else
wgroup.long 0x0F00++0x03
line.long 0x00 "GICD_SGIR,Software Generated Interrupt Register"
bitfld.long 0x00 24.--25. " TLF           ,Target List Filter" "TargetList,All CPUs,Request CPU,?..."
hexmask.long.byte 0x00 16.--23. 1. "  CPUTL         ,CPU Target List"
textline "                                  "
bitfld.long 0x00 0.--3. " SGINTID       ,SGI Interrupt ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
endif
group.long 0x0F20++0x03
line.long 0x00 "GICD_SET/CLR_PENDSGIR0,SGI Set/Clear Pending Register 0"
setclrfld.long 0x00 31. 0x00 31. -0x10 31. " SET/CLR_SGI0  ,SGI0 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. -0x10 30. "     SET/CLR_SGI0  ,SGI0 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. -0x10 29. "  SET/CLR_SGI0  ,SGI0 Set/Clear Pending Bit" "Disabled,Enabled"
textline "                                  "
setclrfld.long 0x00 28. 0x00 28. -0x10 28. " SET/CLR_SGI0  ,SGI0 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. -0x10 27. "     SET/CLR_SGI0  ,SGI0 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. -0x10 26. "  SET/CLR_SGI0  ,SGI0 Set/Clear Pending Bit" "Disabled,Enabled"
textline "                                  "
setclrfld.long 0x00 25. 0x00 25. -0x10 25. " SET/CLR_SGI0  ,SGI0 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. -0x10 24. "     SET/CLR_SGI0  ,SGI0 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. -0x10 23. "  SET/CLR_SGI1  ,SGI1 Set/Clear Pending Bit" "Disabled,Enabled"
textline "                                  "
setclrfld.long 0x00 22. 0x00 22. -0x10 22. " SET/CLR_SGI1  ,SGI1 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. -0x10 21. "     SET/CLR_SGI1  ,SGI1 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. -0x10 20. "  SET/CLR_SGI1  ,SGI1 Set/Clear Pending Bit" "Disabled,Enabled"
textline "                                  "
setclrfld.long 0x00 19. 0x00 19. -0x10 19. " SET/CLR_SGI1  ,SGI1 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. -0x10 18. "     SET/CLR_SGI1  ,SGI1 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. -0x10 17. "  SET/CLR_SGI1  ,SGI1 Set/Clear Pending Bit" "Disabled,Enabled"
textline "                                  "
setclrfld.long 0x00 16. 0x00 16. -0x10 16. " SET/CLR_SGI1  ,SGI1 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. -0x10 15. "     SET/CLR_SGI2  ,SGI2 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. -0x10 14. "  SET/CLR_SGI2  ,SGI2 Set/Clear Pending Bit" "Disabled,Enabled"
textline "                                  "
setclrfld.long 0x00 13. 0x00 13. -0x10 13. " SET/CLR_SGI2  ,SGI2 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. -0x10 12. "     SET/CLR_SGI2  ,SGI2 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. -0x10 11. "  SET/CLR_SGI2  ,SGI2 Set/Clear Pending Bit" "Disabled,Enabled"
textline "                                  "
setclrfld.long 0x00 10. 0x00 10. -0x10 10. " SET/CLR_SGI2  ,SGI2 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. -0x10 9. "     SET/CLR_SGI2  ,SGI2 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. -0x10 8. "  SET/CLR_SGI2  ,SGI2 Set/Clear Pending Bit" "Disabled,Enabled"
textline "                                  "
setclrfld.long 0x00 7. 0x00 7. -0x10 7. " SET/CLR_SGI3  ,SGI3 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. -0x10 6. "     SET/CLR_SGI3  ,SGI3 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. -0x10 5. "  SET/CLR_SGI3  ,SGI3 Set/Clear Pending Bit" "Disabled,Enabled"
textline "                                  "
setclrfld.long 0x00 4. 0x00 4. -0x10 4. " SET/CLR_SGI3  ,SGI3 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. -0x10 3. "     SET/CLR_SGI3  ,SGI3 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. -0x10 2. "  SET/CLR_SGI3  ,SGI3 Set/Clear Pending Bit" "Disabled,Enabled"
textline "                                  "
setclrfld.long 0x00 1. 0x00 1. -0x10 1. " SET/CLR_SGI3  ,SGI3 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. -0x10 0. "     SET/CLR_SGI3  ,SGI3 Set/Clear Pending Bit" "Disabled,Enabled"
group.long 0x0F24++0x03
line.long 0x00 "GICD_SET/CLR_PENDSGIR1,SGI Set/Clear Pending Register 1"
setclrfld.long 0x00 31. 0x00 31. -0x10 31. " SET/CLR_SGI4  ,SGI4 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. -0x10 30. "     SET/CLR_SGI4  ,SGI4 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. -0x10 29. "  SET/CLR_SGI4  ,SGI4 Set/Clear Pending Bit" "Disabled,Enabled"
textline "                                  "
setclrfld.long 0x00 28. 0x00 28. -0x10 28. " SET/CLR_SGI4  ,SGI4 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. -0x10 27. "     SET/CLR_SGI4  ,SGI4 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. -0x10 26. "  SET/CLR_SGI4  ,SGI4 Set/Clear Pending Bit" "Disabled,Enabled"
textline "                                  "
setclrfld.long 0x00 25. 0x00 25. -0x10 25. " SET/CLR_SGI4  ,SGI4 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. -0x10 24. "     SET/CLR_SGI4  ,SGI4 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. -0x10 23. "  SET/CLR_SGI5  ,SGI5 Set/Clear Pending Bit" "Disabled,Enabled"
textline "                                  "
setclrfld.long 0x00 22. 0x00 22. -0x10 22. " SET/CLR_SGI5  ,SGI5 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. -0x10 21. "     SET/CLR_SGI5  ,SGI5 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. -0x10 20. "  SET/CLR_SGI5  ,SGI5 Set/Clear Pending Bit" "Disabled,Enabled"
textline "                                  "
setclrfld.long 0x00 19. 0x00 19. -0x10 19. " SET/CLR_SGI5  ,SGI5 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. -0x10 18. "     SET/CLR_SGI5  ,SGI5 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. -0x10 17. "  SET/CLR_SGI5  ,SGI5 Set/Clear Pending Bit" "Disabled,Enabled"
textline "                                  "
setclrfld.long 0x00 16. 0x00 16. -0x10 16. " SET/CLR_SGI5  ,SGI5 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. -0x10 15. "     SET/CLR_SGI6  ,SGI6 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. -0x10 14. "  SET/CLR_SGI6  ,SGI6 Set/Clear Pending Bit" "Disabled,Enabled"
textline "                                  "
setclrfld.long 0x00 13. 0x00 13. -0x10 13. " SET/CLR_SGI6  ,SGI6 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. -0x10 12. "     SET/CLR_SGI6  ,SGI6 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. -0x10 11. "  SET/CLR_SGI6  ,SGI6 Set/Clear Pending Bit" "Disabled,Enabled"
textline "                                  "
setclrfld.long 0x00 10. 0x00 10. -0x10 10. " SET/CLR_SGI6  ,SGI6 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. -0x10 9. "     SET/CLR_SGI6  ,SGI6 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. -0x10 8. "  SET/CLR_SGI6  ,SGI6 Set/Clear Pending Bit" "Disabled,Enabled"
textline "                                  "
setclrfld.long 0x00 7. 0x00 7. -0x10 7. " SET/CLR_SGI7  ,SGI7 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. -0x10 6. "     SET/CLR_SGI7  ,SGI7 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. -0x10 5. "  SET/CLR_SGI7  ,SGI7 Set/Clear Pending Bit" "Disabled,Enabled"
textline "                                  "
setclrfld.long 0x00 4. 0x00 4. -0x10 4. " SET/CLR_SGI7  ,SGI7 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. -0x10 3. "     SET/CLR_SGI7  ,SGI7 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. -0x10 2. "  SET/CLR_SGI7  ,SGI7 Set/Clear Pending Bit" "Disabled,Enabled"
textline "                                  "
setclrfld.long 0x00 1. 0x00 1. -0x10 1. " SET/CLR_SGI7  ,SGI7 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. -0x10 0. "     SET/CLR_SGI7  ,SGI7 Set/Clear Pending Bit" "Disabled,Enabled"
group.long 0x0F28++0x03
line.long 0x00 "GICD_SET/CLR_PENDSGIR2,SGI Set/Clear Pending Register 2"
setclrfld.long 0x00 31. 0x00 31. -0x10 31. " SET/CLR_SGI8  ,SGI8 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. -0x10 30. "     SET/CLR_SGI8  ,SGI8 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. -0x10 29. "  SET/CLR_SGI8  ,SGI8 Set/Clear Pending Bit" "Disabled,Enabled"
textline "                                  "
setclrfld.long 0x00 28. 0x00 28. -0x10 28. " SET/CLR_SGI8  ,SGI8 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. -0x10 27. "     SET/CLR_SGI8  ,SGI8 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. -0x10 26. "  SET/CLR_SGI8  ,SGI8 Set/Clear Pending Bit" "Disabled,Enabled"
textline "                                  "
setclrfld.long 0x00 25. 0x00 25. -0x10 25. " SET/CLR_SGI8  ,SGI8 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. -0x10 24. "     SET/CLR_SGI8  ,SGI8 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. -0x10 23. "  SET/CLR_SGI9  ,SGI9 Set/Clear Pending Bit" "Disabled,Enabled"
textline "                                  "
setclrfld.long 0x00 22. 0x00 22. -0x10 22. " SET/CLR_SGI9  ,SGI9 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. -0x10 21. "     SET/CLR_SGI9  ,SGI9 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. -0x10 20. "  SET/CLR_SGI9  ,SGI9 Set/Clear Pending Bit" "Disabled,Enabled"
textline "                                  "
setclrfld.long 0x00 19. 0x00 19. -0x10 19. " SET/CLR_SGI9  ,SGI9 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. -0x10 18. "     SET/CLR_SGI9  ,SGI9 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. -0x10 17. "  SET/CLR_SGI9  ,SGI9 Set/Clear Pending Bit" "Disabled,Enabled"
textline "                                  "
setclrfld.long 0x00 16. 0x00 16. -0x10 16. " SET/CLR_SGI9  ,SGI9 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. -0x10 15. "     SET/CLR_SGI10 ,SGI10 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. -0x10 14. "  SET/CLR_SGI10 ,SGI10 Set/Clear Pending Bit" "Disabled,Enabled"
textline "                                  "
setclrfld.long 0x00 13. 0x00 13. -0x10 13. " SET/CLR_SGI10 ,SGI10 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. -0x10 12. "     SET/CLR_SGI10 ,SGI10 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. -0x10 11. "  SET/CLR_SGI10 ,SGI10 Set/Clear Pending Bit" "Disabled,Enabled"
textline "                                  "
setclrfld.long 0x00 10. 0x00 10. -0x10 10. " SET/CLR_SGI10 ,SGI10 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. -0x10 9. "     SET/CLR_SGI10 ,SGI10 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. -0x10 8. "  SET/CLR_SGI10 ,SGI10 Set/Clear Pending Bit" "Disabled,Enabled"
textline "                                  "
setclrfld.long 0x00 7. 0x00 7. -0x10 7. " SET/CLR_SGI11 ,SGI11 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. -0x10 6. "     SET/CLR_SGI11 ,SGI11 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. -0x10 5. "  SET/CLR_SGI11 ,SGI11 Set/Clear Pending Bit" "Disabled,Enabled"
textline "                                  "
setclrfld.long 0x00 4. 0x00 4. -0x10 4. " SET/CLR_SGI11 ,SGI11 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. -0x10 3. "     SET/CLR_SGI11 ,SGI11 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. -0x10 2. "  SET/CLR_SGI11 ,SGI11 Set/Clear Pending Bit" "Disabled,Enabled"
textline "                                  "
setclrfld.long 0x00 1. 0x00 1. -0x10 1. " SET/CLR_SGI11 ,SGI11 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. -0x10 0. "     SET/CLR_SGI11 ,SGI11 Set/Clear Pending Bit" "Disabled,Enabled"
group.long 0x0F2C++0x03
line.long 0x00 "GICD_SET/CLR_PENDSGIR2,SGI Set/Clear Pending Register 3"
setclrfld.long 0x00 31. 0x00 31. -0x10 31. " SET/CLR_SGI12 ,SGI12 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. -0x10 30. "     SET/CLR_SGI12 ,SGI12 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. -0x10 29. "  SET/CLR_SGI12 ,SGI12 Set/Clear Pending Bit" "Disabled,Enabled"
textline "                                  "
setclrfld.long 0x00 28. 0x00 28. -0x10 28. " SET/CLR_SGI12 ,SGI12 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. -0x10 27. "     SET/CLR_SGI12 ,SGI12 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. -0x10 26. "  SET/CLR_SGI12 ,SGI12 Set/Clear Pending Bit" "Disabled,Enabled"
textline "                                  "
setclrfld.long 0x00 25. 0x00 25. -0x10 25. " SET/CLR_SGI12 ,SGI12 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. -0x10 24. "     SET/CLR_SGI12 ,SGI12 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. -0x10 23. "  SET/CLR_SGI13 ,SGI13 Set/Clear Pending Bit" "Disabled,Enabled"
textline "                                  "
setclrfld.long 0x00 22. 0x00 22. -0x10 22. " SET/CLR_SGI13 ,SGI13 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. -0x10 21. "     SET/CLR_SGI13 ,SGI13 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. -0x10 20. "  SET/CLR_SGI13 ,SGI13 Set/Clear Pending Bit" "Disabled,Enabled"
textline "                                  "
setclrfld.long 0x00 19. 0x00 19. -0x10 19. " SET/CLR_SGI13 ,SGI13 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. -0x10 18. "     SET/CLR_SGI13 ,SGI13 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. -0x10 17. "  SET/CLR_SGI13 ,SGI13 Set/Clear Pending Bit" "Disabled,Enabled"
textline "                                  "
setclrfld.long 0x00 16. 0x00 16. -0x10 16. " SET/CLR_SGI13 ,SGI13 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. -0x10 15. "     SET/CLR_SGI14 ,SGI14 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. -0x10 14. "  SET/CLR_SGI14 ,SGI14 Set/Clear Pending Bit" "Disabled,Enabled"
textline "                                  "
setclrfld.long 0x00 13. 0x00 13. -0x10 13. " SET/CLR_SGI14 ,SGI14 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. -0x10 12. "     SET/CLR_SGI14 ,SGI14 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. -0x10 11. "  SET/CLR_SGI14 ,SGI14 Set/Clear Pending Bit" "Disabled,Enabled"
textline "                                  "
setclrfld.long 0x00 10. 0x00 10. -0x10 10. " SET/CLR_SGI14 ,SGI14 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. -0x10 9. "     SET/CLR_SGI14 ,SGI14 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. -0x10 8. "  SET/CLR_SGI14 ,SGI14 Set/Clear Pending Bit" "Disabled,Enabled"
textline "                                  "
setclrfld.long 0x00 7. 0x00 7. -0x10 7. " SET/CLR_SGI15 ,SGI15 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. -0x10 6. "     SET/CLR_SGI15 ,SGI15 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. -0x10 5. "  SET/CLR_SGI15 ,SGI15 Set/Clear Pending Bit" "Disabled,Enabled"
textline "                                  "
setclrfld.long 0x00 4. 0x00 4. -0x10 4. " SET/CLR_SGI15 ,SGI15 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. -0x10 3. "     SET/CLR_SGI15 ,SGI15 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. -0x10 2. "  SET/CLR_SGI15 ,SGI15 Set/Clear Pending Bit" "Disabled,Enabled"
textline "                                  "
setclrfld.long 0x00 1. 0x00 1. -0x10 1. " SET/CLR_SGI15 ,SGI15 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. -0x10 0. "     SET/CLR_SGI15 ,SGI15 Set/Clear Pending Bit" "Disabled,Enabled"
tree.end
width 12.
tree "Peripheral/Component ID Registers"
rgroup.byte 0x0FE0++0x00
line.byte 0x00 "GICD_PIDR0,Peripheral ID0 Register"
hexmask.byte 0x00 0.--7. 1. " DEVID         ,DevID field"
rgroup.byte 0x0FE4++0x00
line.byte 0x00 "GICD_PIDR1,Peripheral ID1 Register"
bitfld.byte 0x00 4.--7. " ARCHID        ,ArchID field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "             DEVID         ,DevID field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.byte 0x0FE8++0x00
line.byte 0x00 "GICD_PIDR2,Peripheral ID2 Register"
bitfld.byte 0x00 4.--7. " ARCHREV       ,ArchRev field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 3. "             UJEPCODE      ,UsesJEPcode field" "Low,High"
bitfld.byte 0x00 0.--2. "           ARCHID         ,ArchID field" "0,1,2,3,4,5,6,7"
rgroup.byte 0x0FEC++0x00
line.byte 0x00 "GICD_PIDR3,Peripheral ID3 Register"
bitfld.byte 0x00 4.--7. " REVID         ,Revision field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.byte 0x0FD0++0x00
line.byte 0x00 "GICD_PIDR4,Peripheral ID4 Register"
bitfld.byte 0x00 0.--3. " CC            ,ContinuationCode field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.byte 0xFD4++0x00
line.byte 0x00 "GICD_PIDR5,Peripheral ID5 Register"
rgroup.byte 0xFD8++0x00
line.byte 0x00 "GICD_PIDR6,Peripheral ID6 Register"
rgroup.byte 0xFDC++0x00
line.byte 0x00 "GICD_PIDR7,Peripheral ID7 Register"
textline "                 "
rgroup.byte 0xFF0++0x00
line.byte 0x00 "GICD_CIDR0,Component ID0 Register"
hexmask.byte 0x00 0.--7. 1. " FIXVAL        ,ARM-defined fixed values for the preamble for component discovery"
rgroup.byte 0xFF4++0x00
line.byte 0x00 "GICD_CIDR1,Component ID1 Register"
hexmask.byte 0x00 0.--7. 1. " FIXVAL        ,ARM-defined fixed values for the preamble for component discovery"
rgroup.byte 0xFF8++0x00
line.byte 0x00 "GICD_CIDR2,Component ID2 Register"
hexmask.byte 0x00 0.--7. 1. " FIXVAL        ,ARM-defined fixed values for the preamble for component discovery"
rgroup.byte 0xFFC++0x00
line.byte 0x00 "GICD_CIDR3,Component ID3 Register"
hexmask.byte 0x00 0.--7. 1. " FIXVAL        ,ARM-defined fixed values for the preamble for component discovery"
textline "                 "
tree.end
tree.end
width 0x0B
tree.end
tree.end
elif (CORENAME()=="CORTEXR52")
tree "Core Registers (Cortex-R52)"
AUTOINDENT.PUSH
AUTOINDENT.ON center tree
tree "ID Registers"
rgroup.long c15:0x0010++0x00
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
bitfld.long 0x00 12.--15. "STATE3,Thumb execution environment (thumb-EE) support" "Not supported,?..."
bitfld.long 0x00 8.--11. "STATE2,Support for jazelle extension" "Reserved,No cleaning,?..."
bitfld.long 0x00 4.--7. "STATE1,Thumb encoding supported by the processor type" "Reserved,Reserved,Reserved,After thumb-2,?..."
newline
bitfld.long 0x00 0.--3. "STATE0,ARM instruction set support" "Reserved,Supported,?..."
rgroup.long c15:0x0110++0x00
line.long 0x00 "ID_PFR1,Processor Feature Register 1"
bitfld.long 0x00 28.--31. "GIC_CPU,GIC CPU support" "Reserved,Enabled,?..."
bitfld.long 0x00 24.--27. "VF,Virtualization fractional support" "Not supported,?..."
bitfld.long 0x00 20.--23. "SF,Security fractional support" "Reserved,VBAR,?..."
newline
bitfld.long 0x00 16.--19. "GT,Generic timer support" "Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "VE,Virtualization extensions support" "Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "MPM,Microcontroller programmer's model support" "Not supported,?..."
newline
bitfld.long 0x00 4.--7. "SE,Security extensions architecture v1 support" "Not supported,?..."
bitfld.long 0x00 0.--3. "PM,Standard ARMv4 programmer's model support" "Reserved,Supported,?..."
rgroup.long c15:0x0310++0x00
line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
rgroup.long c15:0x0410++0x00
line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
bitfld.long 0x00 28.--31. "IS,Indicates innermost shareability domain implemented" "Non-cacheable,?..."
bitfld.long 0x00 24.--27. "FCSE,Fast context switch memory mappings support" "Not supported,?..."
bitfld.long 0x00 20.--23. "AR,Auxiliary register support" "Reserved,Reserved,Control/fault status,?..."
newline
bitfld.long 0x00 16.--19. "TCM,TCM and associated DMA support" "Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "SL,Shareability levels" "Reserved,Implemented 2 levels,?..."
bitfld.long 0x00 8.--11. "OSS,Outer shareable support" "Non-cacheable,?..."
newline
bitfld.long 0x00 4.--7. "PMSA,Physical memory system architecture (PMSA) support" "Reserved,Reserved,Reserved,Reserved,ARMv8-R base+limit PMSA,?..."
bitfld.long 0x00 0.--3. "VMSA,Virtual memory system architecture (VMSA) support" "Not supported,?..."
rgroup.long c15:0x0510++0x00
line.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
bitfld.long 0x00 28.--31. "BTB,Branch predictor" "Reserved,Reserved,Reserved,Reserved,No flushing,?..."
bitfld.long 0x00 24.--27. "L1TCO,Test and clean operations on data cache/harvard/unified architecture support" "Not supported,?..."
bitfld.long 0x00 20.--23. "L1UCMO,L1 cache/all maintenance operations/unified architecture support" "Not supported,?..."
newline
bitfld.long 0x00 16.--19. "L1HCMO,L1 Cache/all maintenance operations/harvard architecture support" "Not supported,?..."
bitfld.long 0x00 12.--15. "L1UCLMOSW,L1 cache line maintenance operations by set and way/unified architecture support" "Not supported,?..."
bitfld.long 0x00 8.--11. "L1HCLMOSW,L1 cache line maintenance operations by set and way/harvard architecture support" "Not supported,?..."
newline
bitfld.long 0x00 4.--7. "L1UCLMOMVA,L1 cache line maintenance operations by MVA/unified architecture support" "Not supported,?..."
bitfld.long 0x00 0.--3. "L1HCLMOMVA,L1 cache line maintenance operations by MVA/harvard architecture" "Not supported,?..."
rgroup.long c15:0x0610++0x00
line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
bitfld.long 0x00 28.--31. "HAF,Hardware access flag support" "Not supported,?..."
bitfld.long 0x00 24.--27. "WFI,Wait for interrupt stalling support" "Reserved,Supported,?..."
bitfld.long 0x00 20.--23. "MBF,Memory barrier operations support" "Reserved,Reserved,DSB/ISB/DMB,?..."
newline
bitfld.long 0x00 16.--19. "UTLBMO,TLB maintenance operations/unified architecture support" "Not supported,?..."
bitfld.long 0x00 12.--15. "HTLBMO,TLB maintenance operations/harvard architecture support" "Not supported,?..."
bitfld.long 0x00 8.--11. "HL1CMRO,Cache maintenance range operations/harvard architecture support" "Not supported,?..."
newline
bitfld.long 0x00 4.--7. "HL1BPCRO,Background prefetch cache range operations/harvard architecture support" "Not supported,?..."
bitfld.long 0x00 0.--3. "HL1FPCRO,Foreground prefetch cache range operations/harvard architecture support" "Not supported,?..."
rgroup.long c15:0x0710++0x00
line.long 0x00 "ID_MMFR3,Memory Model Feature Register 3"
bitfld.long 0x00 28.--31. "SS,Supersection support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Not supported"
bitfld.long 0x00 24.--27. "CMEMSZ,Cached memory size" "4GByte,?..."
bitfld.long 0x00 20.--23. "CW,Coherent walk. Indicates whether translation table updates require a clean to the point of unification" "Reserved,Not required,?..."
newline
bitfld.long 0x00 12.--15. "MB,Maintenance broadcast support" "Reserved,Reserved,Shareability/defined behavior,?..."
bitfld.long 0x00 8.--11. "BPM,Invalidate branch predictor support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 4.--7. "HCMOSW,Invalidate cache by set and way/clean by set and way/invalidate and clean by set and way support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 0.--3. "HCMOMVA,Invalidate cache MVA support" "Reserved,Supported,?..."
rgroup.long c15:0x0620++0x00
line.long 0x00 "ID_MMFR4,Memory Model Feature Register 4"
bitfld.long 0x00 4.--7. "AC2,Extension of ACTLR and HACTLR by ACTLR2 and HACTLR2" "Reserved,Supported,?..."
rgroup.long c15:0x0020++0x00
line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0"
bitfld.long 0x00 24.--27. "DIVI,Divide instructions support" "Reserved,Reserved,T32/A32,?..."
bitfld.long 0x00 20.--23. "DEBI,Debug instructions support" "Reserved,Supported,?..."
bitfld.long 0x00 16.--19. "CI,Coprocessor instructions support" "Not supported,?..."
newline
bitfld.long 0x00 12.--15. "CBI,Combined compare and branch instructions support" "Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "BI,Bitfield instructions support" "Reserved,Supported,?..."
bitfld.long 0x00 4.--7. "BCI,Bit counting instructions support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 0.--3. "SI,Swap instructions support" "Not supported,?..."
rgroup.long c15:0x0120++0x00
line.long 0x00 "ID_ISAR1,Instruction Set Attributes Register 1"
bitfld.long 0x00 28.--31. "JI,Jazelle instructions support" "Reserved,Supported,?..."
bitfld.long 0x00 24.--27. "INTI,Interwork instructions support" "Reserved,Reserved,Reserved,A32-BX like,?..."
bitfld.long 0x00 20.--23. "IMMI,Immediate instructions support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 16.--19. "ITEI,If then instructions support" "Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "EXTI,Extend instructions support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "EARI,Exception A and R instructions support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 4.--7. "EXIN,Exception in ARM instructions support" "Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "ENDI,Endian instructions support" "Reserved,Supported,?..."
rgroup.long c15:0x0220++0x00
line.long 0x00 "ID_ISAR2,Instruction Set Attributes Register 2"
bitfld.long 0x00 28.--31. "RI,Reversal instructions support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 24.--27. "PSRI,PSR instructions support" "Reserved,Supported,?..."
bitfld.long 0x00 20.--23. "UMI,Advanced unsigned multiply instructions support" "Reserved,Reserved,Supported,?..."
newline
bitfld.long 0x00 16.--19. "SMI,Advanced signed multiply instructions support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "MI,Multiply instructions support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "II,Multi-access interruptible instructions support" "Reserved,Restartable,?..."
newline
bitfld.long 0x00 4.--7. "MHI,Memory hint instructions support" "Reserved,Reserved,Reserved,Reserved,PLD/PLI/PLDW,?..."
bitfld.long 0x00 0.--3. "LSI,Load and store instructions support" "Reserved,Reserved,Supported,?..."
rgroup.long c15:0x0320++0x00
line.long 0x00 "ID_ISAR3,Instruction Set Attributes Register 3"
bitfld.long 0x00 28.--31. "TEEEI,Thumb-EE extensions support" "Not supported,?..."
bitfld.long 0x00 24.--27. "NOPI,True NOP instructions support" "Reserved,Supported,?..."
bitfld.long 0x00 20.--23. "TCI,Thumb copy instructions support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 16.--19. "TBI,Table branch instructions support" "Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "SPI,Synchronization primitive instructions support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "SVCI,SVC instructions support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 4.--7. "SIMDI,Single instruction multiple data (SIMD) instructions support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "SI,Saturate instructions support" "Reserved,Supported,?..."
rgroup.long c15:0x0420++0x00
line.long 0x00 "ID_ISAR4,Instruction Set Attributes Register 4"
bitfld.long 0x00 28.--31. "SWP_FRAC,Memory system locking support" "Not supported,?..."
bitfld.long 0x00 24.--27. "PSR_M_I,PSR_M instructions support" "Not supported,?..."
bitfld.long 0x00 20.--23. "SPRI,Synchronization primitive instructions" "Supported,?..."
newline
bitfld.long 0x00 16.--19. "BI,Barrier instructions support" "Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "SMCI,SMC instructions support" "Not supported,?..."
bitfld.long 0x00 8.--11. "WBI,Write-back instructions support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 4.--7. "WSI,With-shift instructions support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "UI,Unprivileged instructions support" "Reserved,Reserved,Supported,?..."
rgroup.long c15:0x0520++0x00
line.long 0x00 "ID_ISAR5,Instruction Set Attribute Register 5"
bitfld.long 0x00 16.--19. "CRC32,CRC32 instructions support" "Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "SHA2,SHA2 instructions support" "Not supported,?..."
bitfld.long 0x00 8.--11. "SHA1,SHA1 instructions support" "Not supported,?..."
newline
bitfld.long 0x00 4.--7. "AES,AES instructions support" "Not supported,?..."
bitfld.long 0x00 0.--3. "SEVL,SEVL instructions support" "Reserved,Supported,?..."
rgroup.long c15:0x0210++0x00
line.long 0x00 "ID_DFR0,Debug Feature Register 0"
bitfld.long 0x00 24.--27. "PMM,Performance monitor model support" "Reserved,Reserved,Reserved,PMUv3,?..."
bitfld.long 0x00 20.--23. "MDM_MM,Memory-mapped debug model for M profile processors support" "Not supported,?..."
bitfld.long 0x00 16.--19. "TM_MM,Trace model (memory-mapped) support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 12.--15. "CTM_CB,Coprocessor-based trace debug model support" "Not supported,?..."
bitfld.long 0x00 0.--3. "CDM_CB,Secure debug model (Coprocessor) support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..."
rgroup.long c15:0x0000++0x00
line.long 0x00 "MIDR,Main ID Register"
hexmask.long.byte 0x00 24.--31. 1. "IMPL,Implementer code"
bitfld.long 0x00 20.--23. "VAR,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 16.--19. "ARCH,Architecture" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CPUID scheme"
hexmask.long.word 0x00 4.--15. 1. "PART,Primary part number"
newline
bitfld.long 0x00 0.--3. "REV,Revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long c15:0x0700++0x00
line.long 0x00 "MIDR,Main ID Register (Alias)"
hexmask.long.byte 0x00 24.--31. 1. "IMPL,Implementer code"
bitfld.long 0x00 20.--23. "VAR,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 16.--19. "ARCH,Architecture" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CPUID scheme"
hexmask.long.word 0x00 4.--15. 1. "PART,Primary part number"
newline
bitfld.long 0x00 0.--3. "REV,Revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long c15:0x0200++0x00
line.long 0x00 "TCMTR,TCM Type Register"
bitfld.long 0x00 29.--31. "TCMS,TCM implemented" "No TCMs,Reserved,Reserved,Reserved,1 TCMs,?..."
bitfld.long 0x00 2. "CTCM,CTCM implemented with non zero size" "Not implemented,Implemented"
bitfld.long 0x00 1. "BTCM,BTCM implemented with non zero size" "Not implemented,Implemented"
newline
bitfld.long 0x00 0. "ATCM,ATCM implemented with non zero size" "Not implemented,Implemented"
rgroup.long c15:0x0300++0x00
line.long 0x00 "TLBTR,TLB Type Register"
rgroup.long c15:0x0500++0x00
line.long 0x00 "MPIDR,Multiprocessor Affinity Register"
bitfld.long 0x00 30. "U,Single core system as distinct from core 0 in a cluster" "Part of a cluster,?..."
bitfld.long 0x00 24. "MT,Lowest level of affinity consist of logical processors" "Largely independent,?..."
newline
hexmask.long.byte 0x00 16.--23. 1. "AFF2,Affinity level 2. The least significant affinity field for this PE in the system"
hexmask.long.byte 0x00 8.--15. 1. "AFF1,Affinity level 1. The intermediate affinity level field for this PE in the system"
hexmask.long.byte 0x00 0.--7. 1. "AFF0,Affinity level 0. The most significant affinity level field for this PE in the system"
rgroup.long c15:0x0600++0x00
line.long 0x00 "REVIDR,Revision ID Register"
hexmask.long.word 0x00 0.--11. 1. "IDNUMBER,Implementation-specific revision information"
rgroup.long c15:0x1700++0x00
line.long 0x00 "AIDR,Auxiliary ID Register"
tree.end
tree "System Control and Configuration"
group.long c15:0x0001++0x00
line.long 0x00 "SCTLR,System Control Register"
bitfld.long 0x00 30. "TE,Thumb exception enable" "A32,T32"
bitfld.long 0x00 25. "EE,Exception endianness" "Little,Big"
rbitfld.long 0x00 21. "FI,Fast interrupts configuration enable" "Disabled,Enabled"
newline
bitfld.long 0x00 20. "UWXN,Unprivileged write permission implies EL1 Execute Never (XN)" "Not forced,Forced"
bitfld.long 0x00 19. "WXN,Write permission implies Execute Never (XN)" "Not forced,Forced"
newline
bitfld.long 0x00 18. "NTWE,Do not trap WFE (Wait for Event) instruction" "Trapped,Not trapped"
bitfld.long 0x00 17. "BR,Background region enable" "Disabled,Enabled"
newline
bitfld.long 0x00 16. "NTWI,Do not trap WFI (Wait For Interrupt) instruction" "Trapped,Not trapped"
bitfld.long 0x00 12. "I,Instruction cache enable" "Disabled,Enabled"
newline
bitfld.long 0x00 8. "SED,SETEND instruction disable" "No,Yes"
bitfld.long 0x00 7. "ITD,IT instruction disable" "No,Yes"
bitfld.long 0x00 5. "CP15BEN,CP15* barrier operations enable" "Disabled,Enabled"
newline
bitfld.long 0x00 2. "C,Data/Unified cache enable" "Disabled,Enabled"
bitfld.long 0x00 1. "A,Alignment fault checking enable" "Disabled,Enabled"
bitfld.long 0x00 0. "M,EL1-controlled MPU enable" "Disabled,Enabled"
group.long c15:0x0201++0x00
line.long 0x00 "CPACR,Architectural Feature Access Control Register"
bitfld.long 0x00 31. "ASEDIS,Disable advanced SIMD extension functionality" "No,Yes"
bitfld.long 0x00 22.--23. "CP11,Coprocessor access control" "Denied,Privileged,Reserved,Full"
bitfld.long 0x00 20.--21. "CP10,Coprocessor access control" "Denied,Privileged,Reserved,Full"
rgroup.long c15:0x0101++0x00
line.long 0x00 "ACTLR,Auxiliary Control Register"
rgroup.long c15:0x0301++0x00
line.long 0x00 "ACTLR2,Auxiliary Control Register 2"
rgroup.long c15:0x0211++0x00
line.long 0x00 "NSACR,Non-Secure Access Control Register"
group.long c15:0x000B++0x00
line.long 0x00 "IMP_SLAVEPCTLR,Slave Port Control Register"
bitfld.long 0x00 0.--1. "TCMACCLVL,Indicates the privilege level required for the AXIS to access the TCM" "Denied,Privileged,Reserved,Full"
group.long c15:0x000C++0x00
line.long 0x00 "VBAR,Vector Base Address Register"
hexmask.long 0x00 5.--31. 0x20 "VBA,Vector base address"
rgroup.long c15:0x010C++0x00
line.long 0x00 "RVBAR,Reset Vector Base Address Register"
hexmask.long 0x00 1.--31. 0x02 "ADDR,Reset address"
rgroup.long c15:0x001C++0x00
line.long 0x00 "ISR,Interrupt Status Register"
bitfld.long 0x00 8. "A,External abort pending flag" "Not pending,Pending"
bitfld.long 0x00 7. "I,Interrupt pending flag" "Not pending,Pending"
bitfld.long 0x00 6. "F,Fast interrupt pending flag" "Not pending,Pending"
group.long c15:0x0015++0x00
line.long 0x00 "ADFSR,Auxiliary Data Fault Status Register"
bitfld.long 0x00 2.--4. "PORT,Memory or port that caused the fault" "AXIM,Flash interface,LLPP,Internal interface,ATCM,BTCM,CTCM,Overlap"
bitfld.long 0x00 0.--1. "TYPE,Fault type" "Other error,External bus control,TCM/cache/bus data,Bus timeout"
group.long c15:0x0115++0x00
line.long 0x00 "AIFSR,Auxiliary Instruction Fault Status Register"
bitfld.long 0x00 2.--4. "PORT,Memory or port that caused the fault" "AXIM,Flash interface,LLPP,Reserved,ATCM,BTCM,CTCM,Overlap"
bitfld.long 0x00 0.--1. "TYPE,Fault type" "Other error,External bus control,TCM/cache/bus data,Bus timeout"
group.long c15:0x0005++0x00
line.long 0x00 "DFSR,Data Fault Status Register"
bitfld.long 0x00 13. "CM,Cache maintenance fault" "No fault,Fault"
bitfld.long 0x00 12. "EXT,External abort qualifier" "DECERR,SLVERR"
newline
bitfld.long 0x00 11. "WNR,Access caused an abort type" "Read,Write"
bitfld.long 0x00 0.--5. "STATUS,Fault status bits" "Reserved,Reserved,Reserved,Reserved,Translation fault/0th level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Permission fault/0th level,Reserved,Reserved,Reserved,Synchronous external abort,Asynchronous external abort,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Synchronous parity error on memory access,Asynchronous parity error on memory access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment fault,Debug event,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,LDREX or STREX,?..."
group.long c15:0x0105++0x00
line.long 0x00 "IFSR,Instruction Fault Status Register"
bitfld.long 0x00 16. "FNV,FAR not Valid for a Synchronous External abort" "Valid,?..."
bitfld.long 0x00 12. "EXT,External abort qualifier" "DECERR,SLVERR"
newline
bitfld.long 0x00 9. "LPAE,Translation table formats on Data Abort exception" "Reserved,Long-descriptor"
bitfld.long 0x00 0.--5. "STATUS,Fault status bits" "Reserved,Reserved,Reserved,Reserved,Translation fault/0th level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Permission fault/0th level,Reserved,Reserved,Reserved,Synchronous external abort,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Synchronous parity error on memory access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment fault,Debug event,?..."
group.long c15:0x0006++0x00
line.long 0x00 "DFAR,Data Fault Address Register"
group.long c15:0x0206++0x00
line.long 0x00 "IFAR,Instruction Fault Address Register"
rgroup.long c15:0x000D++0x00
line.long 0x00 "FCSEIDR,FCSE PID Register"
rgroup.long c15:0x103F++0x00
line.long 0x00 "IMP_CBAR,Configuration Base Address Register"
hexmask.long.word 0x00 21.--31. 0x20 "PERIPHBASE,Upper bits of base physical address of memory-mapped peripherals"
group.long c15:0x020D++0x00
line.long 0x00 "TPIDRURW,Thread Pointer ID Register Unprivileged Read-Write"
group.long c15:0x030D++0x00
line.long 0x00 "TPIDRURO,Thread Pointer ID Register Unprivileged Read-Only"
group.long c15:0x040D++0x00
line.long 0x00 "TPIDRPRW,Thread Pointer ID Register Privileged Read-Write"
tree "System Instructions"
wgroup.long c15:0x0017++0x00
line.long 0x00 "ICIALLUIS,ICIALLUIS"
wgroup.long c15:0x0617++0x00
line.long 0x00 "BPIALLIS,BPIALLIS"
wgroup.long c15:0x0057++0x00
line.long 0x00 "ICIALLU,ICIALLU"
wgroup.long c15:0x0157++0x00
line.long 0x00 "ICIMVAU,ICIMVAU"
wgroup.long c15:0x0457++0x00
line.long 0x00 "CP15ISB,CP15ISB"
wgroup.long c15:0x0657++0x00
line.long 0x00 "BPIALL,BPIALL"
wgroup.long c15:0x0757++0x00
line.long 0x00 "BPIMVA,BPIMVA"
wgroup.long c15:0x0167++0x00
line.long 0x00 "DCIMVAC,DCIMVAC"
wgroup.long c15:0x0267++0x00
line.long 0x00 "DCISW,DCISW"
wgroup.long c15:0x0087++0x00
line.long 0x00 "ATS1CPR,ATS1CPR"
wgroup.long c15:0x0187++0x00
line.long 0x00 "ATS1CPW,ATS1CPW"
wgroup.long c15:0x0287++0x00
line.long 0x00 "ATS1CUR,ATS1CUR"
wgroup.long c15:0x0387++0x00
line.long 0x00 "ATS1CUW,ATS1CUW"
wgroup.long c15:0x0487++0x00
line.long 0x00 "ATS12NSOPR,ATS12NSOPR"
wgroup.long c15:0x0587++0x00
line.long 0x00 "ATS12NSOPW,ATS12NSOPW"
wgroup.long c15:0x0687++0x00
line.long 0x00 "ATS12NSOUR,ATS12NSOUR"
wgroup.long c15:0x0787++0x00
line.long 0x00 "ATS12NSOUW,ATS12NSOUW"
wgroup.long c15:0x01A7++0x00
line.long 0x00 "DCCMVAC,DCCMVAC"
wgroup.long c15:0x02A7++0x00
line.long 0x00 "DCCSW,DCCSW"
wgroup.long c15:0x04A7++0x00
line.long 0x00 "CP15DSB,CP15DSB"
wgroup.long c15:0x05A7++0x00
line.long 0x00 "CP15DMB,CP15DMB"
wgroup.long c15:0x01B7++0x00
line.long 0x00 "DCCMVAU,DCCMVAU"
wgroup.long c15:0x01E7++0x00
line.long 0x00 "DCCIMVAC,DCCIMVAC"
wgroup.long c15:0x02E7++0x00
line.long 0x00 "DCCISW,DCCISW"
wgroup.long c15:0x4087++0x00
line.long 0x00 "ATS1HR,ATS1HR"
wgroup.long c15:0x4187++0x00
line.long 0x00 "ATS1HW,ATS1HW"
tree.end
tree.end
tree "MPU Control and Configuration"
group.long c15:0x0001++0x00
line.long 0x00 "SCTLR,System Control Register"
bitfld.long 0x00 30. "TE,Thumb exception enable" "A32,T32"
bitfld.long 0x00 25. "EE,Exception endianness" "Little,Big"
rbitfld.long 0x00 21. "FI,Fast interrupts configuration enable" "Disabled,Enabled"
newline
bitfld.long 0x00 20. "UWXN,Unprivileged write permission implies EL1 Execute Never (XN)" "Not forced,Forced"
bitfld.long 0x00 19. "WXN,Write permission implies Execute Never (XN)" "Not forced,Forced"
newline
bitfld.long 0x00 18. "NTWE,Do not trap WFE (Wait for Event) instruction" "Trapped,Not trapped"
bitfld.long 0x00 17. "BR,Background region enable" "Disabled,Enabled"
newline
bitfld.long 0x00 16. "NTWI,Do not trap WFI (Wait For Interrupt) instruction" "Trapped,Not trapped"
bitfld.long 0x00 12. "I,Instruction cache enable" "Disabled,Enabled"
newline
bitfld.long 0x00 8. "SED,SETEND instruction disable" "No,Yes"
bitfld.long 0x00 7. "ITD,IT instruction disable" "No,Yes"
bitfld.long 0x00 5. "CP15BEN,CP15* barrier operations enable" "Disabled,Enabled"
newline
bitfld.long 0x00 2. "C,Data/Unified cache enable" "Disabled,Enabled"
bitfld.long 0x00 1. "A,Alignment fault checking enable" "Disabled,Enabled"
bitfld.long 0x00 0. "M,EL1-controlled MPU enable" "Disabled,Enabled"
if (((per.l(c15:0x10070))&0x1)==0x0)
group.quad c15:0x10070++0x01
line.quad 0x00 "PAR,Physical Address Register"
hexmask.quad.byte 0x00 56.--63. 1. "ATTR,Memory attributes for the returned PA"
hexmask.quad.long 0x00 12.--31. 0x1000 "PA,Physical address"
newline
bitfld.quad 0x00 9. "NS,Non-secure" "Reserved,Yes"
bitfld.quad 0x00 7.--8. "SHA,Shareable attribute" "Non-shareable,Reserved,Outer shareable,Inner shareable"
newline
bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted"
else
group.quad c15:0x10070++0x01
line.quad 0x00 "PAR,Physical Address Register"
bitfld.quad 0x00 9. "FSTAGE,Indicates the translation stage at which the translation aborted" "Stage 1,Stage 2"
bitfld.quad 0x00 8. "S2WLK,Translation aborted because of a stage 2 fault during a stage 1 translation table walk" "No,?..."
newline
bitfld.quad 0x00 1.--6. "FST,Fault Status Field" "Reserved,Reserved,Reserved,Reserved,Translation fault/0th level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Permission fault/0th level,Reserved,Reserved,Reserved,Synchronous external abort,Asynchronous external abort,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Synchronous parity error on memory access,Asynchronous parity error on memory access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment fault,Debug event,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Unsupported Exclusive access,?..."
newline
bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted"
endif
tree.open "Memory Attribute Indirection Registers"
group.long c15:0x402A++0x00
line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0"
bitfld.long 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
group.long c15:0x412A++0x00
line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1"
bitfld.long 0x00 28.--31. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 20.--23. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 12.--15. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 4.--7. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
group.long c15:0x002A++0x00
line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0"
bitfld.long 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
group.long c15:0x012A++0x00
line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1"
bitfld.long 0x00 28.--31. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 20.--23. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 12.--15. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 4.--7. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
rgroup.long c15:0x003A++0x00
line.long 0x00 "AMAIR0,Auxiliary Memory Attribute Indirection Register 0"
rgroup.long c15:0x013A++0x00
line.long 0x00 "AMAIR1,Auxiliary Memory Attribute Indirection Register 1"
rgroup.long c15:0x403A++0x00
line.long 0x00 "HAMAIR0,Hypervisor Auxiliary Memory Attribute Indirection Register 0"
rgroup.long c15:0x413A++0x00
line.long 0x00 "HAMAIR1,Hypervisor Auxiliary Memory Attribute Indirection Register 1"
group.long c15:0x010D++0x00
line.long 0x00 "CONTEXTIDR,Context ID Register"
tree.end
newline
group.long c15:(0x0019+0x0)++0x00
line.long 0x00 "IMP_ATCMREGIONR,TCM Region Register A"
hexmask.long.long 0x00 13.--31. 0x2000 "BASEADDRESS,TCM base address"
bitfld.long 0x00 8. "WAITSTATES,Wait states for TCM accesses" "0,1"
newline
bitfld.long 0x00 2.--6. "SIZE,TCM size" "No TCM,Reserved,Reserved,Reserved,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,?..."
bitfld.long 0x00 1. "ENABLEEL2,Enable TCM at EL2" "Disabled,Enabled"
newline
bitfld.long 0x00 0. "ENABLEEL10,Enable TCM at EL1 and EL0" "Disabled,Enabled"
group.long c15:(0x0019+0x100)++0x00
line.long 0x00 "IMP_BTCMREGIONR,TCM Region Register B"
hexmask.long.long 0x00 13.--31. 0x2000 "BASEADDRESS,TCM base address"
bitfld.long 0x00 8. "WAITSTATES,Wait states for TCM accesses" "0,1"
newline
bitfld.long 0x00 2.--6. "SIZE,TCM size" "No TCM,Reserved,Reserved,Reserved,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,?..."
bitfld.long 0x00 1. "ENABLEEL2,Enable TCM at EL2" "Disabled,Enabled"
newline
bitfld.long 0x00 0. "ENABLEEL10,Enable TCM at EL1 and EL0" "Disabled,Enabled"
group.long c15:(0x0019+0x200)++0x00
line.long 0x00 "IMP_CTCMREGIONR,TCM Region Register C"
hexmask.long.long 0x00 13.--31. 0x2000 "BASEADDRESS,TCM base address"
bitfld.long 0x00 8. "WAITSTATES,Wait states for TCM accesses" "0,1"
newline
bitfld.long 0x00 2.--6. "SIZE,TCM size" "No TCM,Reserved,Reserved,Reserved,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,?..."
bitfld.long 0x00 1. "ENABLEEL2,Enable TCM at EL2" "Disabled,Enabled"
newline
bitfld.long 0x00 0. "ENABLEEL10,Enable TCM at EL1 and EL0" "Disabled,Enabled"
group.long c15:0x1219++0x00
line.long 0x00 "IMP_MEMPROTCTLR,Memory Protection Control Register"
rbitfld.long 0x00 5. "FLASHPROTIMP,Flash protection implemented" "Not implemented,Implemented"
rbitfld.long 0x00 4. "RAMPROTIMP,RAM protection implemented" "Not implemented,Implemented"
newline
bitfld.long 0x00 1. "FLASHPROTEN,Flash interface protection enable" "Disabled,Enabled"
bitfld.long 0x00 0. "RAMPROTEN,TCM and L1 cache RAM protection enable" "Disabled,Enabled"
group.long c15:0x000F++0x00
line.long 0x00 "IMP_PERIPHPREGIONR,Peripheral Port Region Register"
hexmask.long.tbyte 0x00 12.--31. 0x10 "BASEADDRESS,Peripheral port region base address"
bitfld.long 0x00 2.--6. "SIZE,Peripheral port region size" "No peripheral port,Reserved,Reserved,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,?..."
newline
bitfld.long 0x00 1. "ENABLEEL2,Enable peripheral port at EL2" "Disabled,Enabled"
bitfld.long 0x00 0. "ENABLEEL10,Enable peripheral port at EL1 and EL0" "Disabled,Enabled"
group.long c15:0x010F++0x00
line.long 0x00 "IMP_FLASHIFREGIONR,Flash Interface Region Register"
hexmask.long.byte 0x00 27.--31. 0x08 "BASEADDRESS,Peripheral port region base address"
bitfld.long 0x00 2.--6. "SIZE,Flash interface region size" "No flash,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,128 MB,?..."
newline
bitfld.long 0x00 0. "ENABLE,Enable the flash interface" "Disabled,Enabled"
rgroup.long c15:0x002F++0x00
line.long 0x00 "IMP_BUILDOPTR,Build Options Register"
bitfld.long 0x00 30.--31. "LOCK_STEP,DCLS functionality implemented" "Not implemented,DCLS configuration,Split/lock configuration,?..."
bitfld.long 0x00 28.--29. "BUS_PROTECTION,Bus protection scheme implemented (signal integrity/interconnect protection)" "Not implemented,Implemented/Not implemented,Implemented,?..."
newline
bitfld.long 0x00 26.--27. "FLASH_DATA_ECC_SCHEME,Flash memory interface data ECC chunk size" "Reserved,64 bit,128 bit,?..."
bitfld.long 0x00 20.--23. "AXIS_ID_WIDTH,Width of AXIS interface ID signals" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8. "NUM_GIC_EXT_DEV,Number of external device interfaces to the GIC" "0,1"
bitfld.long 0x00 0.--3. "NUM_CORES,Number of cores in the Cortex-R52 processor" "0,1,2,3,?..."
rgroup.long c15:0x072F++0x00
line.long 0x00 "IMP_PINOPTR,Pin Options Register"
hexmask.long.byte 0x00 24.--31. 1. "CFGAXISTCMBASEADDR,Value of the CFGAXISTCMBASEADDR signal"
bitfld.long 0x00 23. "CFGSLSPLIT,Value of the CFGSLSPLIT signal" "0,1"
newline
bitfld.long 0x00 21.--22. "CFGCLUSTERUTID,Value of the CFGCLUSTERUTID signal" "0,1,2,3"
bitfld.long 0x00 18. "CFGFLASHPROTEN,Value of the CFGFLASHPROTEN signal" "0,1"
newline
bitfld.long 0x00 17. "CFGRAMPROTEN,Value of the CFGRAMPROTEN signal" "0,1"
bitfld.long 0x00 16. "CFGINITREG,Value of the CFGINITREG signal" "0,1"
newline
bitfld.long 0x00 15. "CFGMRPEN,Value of the CFGMRPEN signal" "0,1"
bitfld.long 0x00 6. "CFGL1CACHEINVDISX,Value of the CFGL1CACHEINVDISx signal" "0,1"
newline
bitfld.long 0x00 5. "CFGENDIANNESSX,Value of the CFGENDIANNESSX signal" "0,1"
bitfld.long 0x00 4. "CFGTHUMBEXCEPTIONSX,Value of the CFGTHUMBEXCEPTIONSx signal" "0,1"
newline
bitfld.long 0x00 2. "CFGFLASHENX,Value of the CFGFLASHENx signal" "0,1"
bitfld.long 0x00 0. "CFGTCMBOOTX,Value of the CFGTCMBOOTx signal" "0,1"
group.long c15:0x113F++0x00
line.long 0x00 "IMP_QOSR,Quality Of Service Register"
bitfld.long 0x00 8.--11. "AWQOS[3:0],QoS identifier sent on the write address channel for each write transaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "ARQOS[3:0],QoS identifier sent on the read address channel for each read transaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long c15:0x123F++0x00
line.long 0x00 "IMP_BUSTIMEOUTR,Bus Timeout Register"
hexmask.long.byte 0x00 24.--31. 1. "MAXCYCLESBY16FLASH,Flash interface timeout value in cycles divided by 16"
hexmask.long.byte 0x00 16.--23. 1. "MAXCYCLESBY16LLPP,LLPP timeout value in cycles divided by 16"
newline
hexmask.long.byte 0x00 8.--15. 1. "MAXCYCLESBY16AXIM,AXIM interface timeout value in cycles divided by 16"
bitfld.long 0x00 6. "ABORTFLASH,Abort flash access" "Not aborted,Aborted"
newline
bitfld.long 0x00 5. "ABORTLLPP,Abort LLPP access" "Not aborted,Aborted"
bitfld.long 0x00 4. "ABORTAXIM,Abort AXIM access" "Not aborted,Aborted"
newline
bitfld.long 0x00 2. "ENABLEFLASH,Timeout counter enable for flash interface" "Disabled,Enabled"
bitfld.long 0x00 1. "ENABLELLPP,Timeout counter enable for LLPP" "Disabled,Enabled"
newline
bitfld.long 0x00 0. "ENABLEAXIM,Timeout counter enable for AXIM interface" "Disabled,Enabled"
group.long c15:0x143F++0x00
line.long 0x00 "IMP_INTMONR,Interrupt Monitoring Register"
hexmask.long.byte 0x00 8.--15. 1. "MAXCYCLESBY16,Maximum count divided by 16"
bitfld.long 0x00 4. "MODE,Operation mode of the counter" "Watchdog,Maximum value monitor"
newline
bitfld.long 0x00 2. "ENABLESER,Enable counting of cycles in which physical system errors are masked" "Disabled,Enabled"
bitfld.long 0x00 1. "ENABLEIRQ,Enable counting of physical interrupts that cannot be taken" "Disabled,Enabled"
newline
bitfld.long 0x00 0. "ENABLEFIQ,Enable counting of fast interrupts that cannot be taken" "Disabled,Enabled"
group.long c15:(0x200F+0x0)++0x00
line.long 0x00 "IMP_ICERR0,Instruction Cache Error Record Register 0"
hexmask.long.byte 0x00 24.--31. 1. "RAMID,RAM bank"
hexmask.long.byte 0x00 4.--10. 1. "INDEX,Instruction cache index"
newline
bitfld.long 0x00 0. "VALID,Register contents are valid" "Not valid,Valid"
group.long c15:(0x200F+0x100)++0x00
line.long 0x00 "IMP_ICERR1,Instruction Cache Error Record Register 1"
hexmask.long.byte 0x00 24.--31. 1. "RAMID,RAM bank"
hexmask.long.byte 0x00 4.--10. 1. "INDEX,Instruction cache index"
newline
bitfld.long 0x00 0. "VALID,Register contents are valid" "Not valid,Valid"
group.long c15:(0x201F+0x0)++0x00
line.long 0x00 "IMP_DCERR0,Data Cache Error Record Register 0"
hexmask.long.word 0x00 20.--31. 1. "RAMID,RAM bank"
hexmask.long.byte 0x00 4.--10. 1. "INDEX,Data cache index"
newline
bitfld.long 0x00 0. "VALID,Register contents are valid" "Not valid,Valid"
group.long c15:(0x201F+0x100)++0x00
line.long 0x00 "IMP_DCERR1,Data Cache Error Record Register 1"
hexmask.long.word 0x00 20.--31. 1. "RAMID,RAM bank"
hexmask.long.byte 0x00 4.--10. 1. "INDEX,Data cache index"
newline
bitfld.long 0x00 0. "VALID,Register contents are valid" "Not valid,Valid"
group.long c15:(0x202F+0x0)++0x00
line.long 0x00 "IMP_TCMERR0,TCM Error Record Register 0"
hexmask.long.byte 0x00 24.--31. 1. "RAMID,RAM bank"
hexmask.long.tbyte 0x00 4.--20. 1. "INDEX,Bits [19:3] of the access address"
newline
bitfld.long 0x00 1. "FATAL,Fatal error" "Correctable,Fatal"
bitfld.long 0x00 0. "VALID,Register contents are valid" "Not valid,Valid"
group.long c15:(0x202F+0x100)++0x00
line.long 0x00 "IMP_TCMERR1,TCM Error Record Register 1"
hexmask.long.byte 0x00 24.--31. 1. "RAMID,RAM bank"
hexmask.long.tbyte 0x00 4.--20. 1. "INDEX,Bits [19:3] of the access address"
newline
bitfld.long 0x00 1. "FATAL,Fatal error" "Correctable,Fatal"
bitfld.long 0x00 0. "VALID,Register contents are valid" "Not valid,Valid"
rgroup.long c15:(0x222F+0x0)++0x00
line.long 0x00 "IMP_TCMSYNDR0,TCM Syndrome Register 0"
hexmask.long.byte 0x00 8.--14. 1. "BANK1,Syndrome for a bank 1 error"
hexmask.long.byte 0x00 0.--7. 1. "BANK0,Syndrome for a bank 0 error"
rgroup.long c15:(0x222F+0x100)++0x00
line.long 0x00 "IMP_TCMSYNDR1,TCM Syndrome Register 1"
hexmask.long.byte 0x00 8.--14. 1. "BANK1,Syndrome for a bank 1 error"
hexmask.long.byte 0x00 0.--7. 1. "BANK0,Syndrome for a bank 0 error"
group.long c15:(0x203F+0x0)++0x00
line.long 0x00 "IMP_FLASHERR0,Flash Error Record Register 0"
hexmask.long 0x00 4.--28. 1. "INDEX,Bits [25:1] of the access address"
bitfld.long 0x00 2. "LATE,Late error" "Not late,Late"
newline
bitfld.long 0x00 1. "FATAL,Fatal error" "Correctable,Fatal"
bitfld.long 0x00 0. "VALID,Register contents are valid" "Not valid,Valid"
group.long c15:(0x203F+0x100)++0x00
line.long 0x00 "IMP_FLASHERR1,Flash Error Record Register 1"
hexmask.long 0x00 4.--28. 1. "INDEX,Bits [25:1] of the access address"
bitfld.long 0x00 2. "LATE,Late error" "Not late,Late"
newline
bitfld.long 0x00 1. "FATAL,Fatal error" "Correctable,Fatal"
bitfld.long 0x00 0. "VALID,Register contents are valid" "Not valid,Valid"
rgroup.long c15:0x400F++0x00
line.long 0x00 "IMP_TESTR0,Test Register 0"
bitfld.long 0x00 5. "VSEI,Virtual system error interrupt signal value" "0,1"
bitfld.long 0x00 4. "SEI,System error interrupt signal value" "0,1"
newline
bitfld.long 0x00 3. "VIRQ,Virtual IRQ interrupt signal value" "0,1"
bitfld.long 0x00 2. "IRQ,IRQ interrupt signal value" "0,1"
newline
bitfld.long 0x00 1. "VFIQ,Virtual FIQ interrupt signal value" "0,1"
bitfld.long 0x00 0. "FIQ,FIQ interrupt signal value" "0,1"
wgroup.long c15:0x410F++0x00
line.long 0x00 "IMP_TESTR1,Test Register 1"
tree.end
tree "Memory Protection Unit PL1"
rgroup.long c15:0x400++0x00
line.long 0x00 "MPUIR,MPU Type Register"
bitfld.long 0x00 8.--15. 1. "DREGION,Number of programmable memory regions" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16,Reserved,Reserved,Reserved,20,Reserved,Reserved,Reserved,24,?..."
bitfld.long 0x00 0. "NU,Not unified MPU" "Unified,?..."
if (((per.l(c15:0x400))&0xFF00)>=0x1800)
group.long c15:0x0126++0x00
line.long 0x00 "PRSELR,Protection Region Selection Register"
bitfld.long 0x00 0.--4. "REGION,Indicates the memory region accessed by PRBAR and PRBAR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
elif (((per.l(c15:0x400))&0xFF00)>=0x1400)
group.long c15:0x0126++0x00
line.long 0x00 "PRSELR,Protection Region Selection Register"
bitfld.long 0x00 0.--4. "REGION,Indicates the memory region accessed by PRBAR and PRBAR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,?..."
elif (((per.l(c15:0x400))&0xFF00)>=0x1000)
group.long c15:0x0126++0x00
line.long 0x00 "PRSELR,Protection Region Selection Register"
bitfld.long 0x00 0.--3. "REGION,Indicates the memory region accessed by PRBAR and PRBAR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
else
hgroup.long c15:0x0126++0x00
hide.long 0x00 "PRSELR,Protection Region Selection Register"
endif
group.long c15:0x0036++0x00
line.long 0x00 "PRBAR,Protection Region Base Address Register"
hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL1 MPU memory region"
bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable"
bitfld.long 0x00 1.--2. "AP,Access permission bits" "None/RW,R/W,None/RO,RO"
newline
bitfld.long 0x00 0. "XN,Execute-never" "0,1"
group.long c15:0x0136++0x00
line.long 0x00 "PRLAR,Protection Region Limit Address Register"
hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL1 MPU memory region"
bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled"
tree "MPU regions"
if (((per.l(c15:0x400))&0xFF00)>=0x1000)
group.long c15:(0x0086+0x0)++0x00 "Region 0"
line.long 0x00 "PRBAR0,Protection Region Base Address Register 0"
hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL1 MPU memory region"
bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable"
bitfld.long 0x00 1.--2. "AP,Access permission bits" "None/RW,R/W,None/RO,RO"
newline
bitfld.long 0x00 0. "XN,Execute-never" "0,1"
group.long c15:(0x0186+0x0)++0x00
line.long 0x00 "PRLAR0,Protection Region Limit Address Register 0"
hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL1 MPU memory region"
bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled"
group.long c15:(0x0486+0x0)++0x00 "Region 1"
line.long 0x00 "PRBAR1,Protection Region Base Address Register 1"
hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL1 MPU memory region"
bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable"
bitfld.long 0x00 1.--2. "AP,Access permission bits" "None/RW,R/W,None/RO,RO"
newline
bitfld.long 0x00 0. "XN,Execute-never" "0,1"
group.long c15:(0x0586+0x0)++0x00
line.long 0x00 "PRLAR1,Protection Region Limit Address Register 1"
hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL1 MPU memory region"
bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled"
group.long c15:(0x0086+0x10)++0x00 "Region 2"
line.long 0x00 "PRBAR2,Protection Region Base Address Register 2"
hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL1 MPU memory region"
bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable"
bitfld.long 0x00 1.--2. "AP,Access permission bits" "None/RW,R/W,None/RO,RO"
newline
bitfld.long 0x00 0. "XN,Execute-never" "0,1"
group.long c15:(0x0186+0x10)++0x00
line.long 0x00 "PRLAR2,Protection Region Limit Address Register 2"
hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL1 MPU memory region"
bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled"
group.long c15:(0x0486+0x10)++0x00 "Region 3"
line.long 0x00 "PRBAR3,Protection Region Base Address Register 3"
hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL1 MPU memory region"
bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable"
bitfld.long 0x00 1.--2. "AP,Access permission bits" "None/RW,R/W,None/RO,RO"
newline
bitfld.long 0x00 0. "XN,Execute-never" "0,1"
group.long c15:(0x0586+0x10)++0x00
line.long 0x00 "PRLAR3,Protection Region Limit Address Register 3"
hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL1 MPU memory region"
bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled"
group.long c15:(0x0086+0x20)++0x00 "Region 4"
line.long 0x00 "PRBAR4,Protection Region Base Address Register 4"
hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL1 MPU memory region"
bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable"
bitfld.long 0x00 1.--2. "AP,Access permission bits" "None/RW,R/W,None/RO,RO"
newline
bitfld.long 0x00 0. "XN,Execute-never" "0,1"
group.long c15:(0x0186+0x20)++0x00
line.long 0x00 "PRLAR4,Protection Region Limit Address Register 4"
hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL1 MPU memory region"
bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled"
group.long c15:(0x0486+0x20)++0x00 "Region 5"
line.long 0x00 "PRBAR5,Protection Region Base Address Register 5"
hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL1 MPU memory region"
bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable"
bitfld.long 0x00 1.--2. "AP,Access permission bits" "None/RW,R/W,None/RO,RO"
newline
bitfld.long 0x00 0. "XN,Execute-never" "0,1"
group.long c15:(0x0586+0x20)++0x00
line.long 0x00 "PRLAR5,Protection Region Limit Address Register 5"
hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL1 MPU memory region"
bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled"
group.long c15:(0x0086+0x30)++0x00 "Region 6"
line.long 0x00 "PRBAR6,Protection Region Base Address Register 6"
hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL1 MPU memory region"
bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable"
bitfld.long 0x00 1.--2. "AP,Access permission bits" "None/RW,R/W,None/RO,RO"
newline
bitfld.long 0x00 0. "XN,Execute-never" "0,1"
group.long c15:(0x0186+0x30)++0x00
line.long 0x00 "PRLAR6,Protection Region Limit Address Register 6"
hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL1 MPU memory region"
bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled"
group.long c15:(0x0486+0x30)++0x00 "Region 7"
line.long 0x00 "PRBAR7,Protection Region Base Address Register 7"
hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL1 MPU memory region"
bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable"
bitfld.long 0x00 1.--2. "AP,Access permission bits" "None/RW,R/W,None/RO,RO"
newline
bitfld.long 0x00 0. "XN,Execute-never" "0,1"
group.long c15:(0x0586+0x30)++0x00
line.long 0x00 "PRLAR7,Protection Region Limit Address Register 7"
hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL1 MPU memory region"
bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled"
group.long c15:(0x0086+0x40)++0x00 "Region 8"
line.long 0x00 "PRBAR8,Protection Region Base Address Register 8"
hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL1 MPU memory region"
bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable"
bitfld.long 0x00 1.--2. "AP,Access permission bits" "None/RW,R/W,None/RO,RO"
newline
bitfld.long 0x00 0. "XN,Execute-never" "0,1"
group.long c15:(0x0186+0x40)++0x00
line.long 0x00 "PRLAR8,Protection Region Limit Address Register 8"
hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL1 MPU memory region"
bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled"
group.long c15:(0x0486+0x40)++0x00 "Region 9"
line.long 0x00 "PRBAR9,Protection Region Base Address Register 9"
hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL1 MPU memory region"
bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable"
bitfld.long 0x00 1.--2. "AP,Access permission bits" "None/RW,R/W,None/RO,RO"
newline
bitfld.long 0x00 0. "XN,Execute-never" "0,1"
group.long c15:(0x0586+0x40)++0x00
line.long 0x00 "PRLAR9,Protection Region Limit Address Register 9"
hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL1 MPU memory region"
bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled"
group.long c15:(0x0086+0x50)++0x00 "Region 10"
line.long 0x00 "PRBAR10,Protection Region Base Address Register 10"
hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL1 MPU memory region"
bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable"
bitfld.long 0x00 1.--2. "AP,Access permission bits" "None/RW,R/W,None/RO,RO"
newline
bitfld.long 0x00 0. "XN,Execute-never" "0,1"
group.long c15:(0x0186+0x50)++0x00
line.long 0x00 "PRLAR10,Protection Region Limit Address Register 10"
hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL1 MPU memory region"
bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled"
group.long c15:(0x0486+0x50)++0x00 "Region 11"
line.long 0x00 "PRBAR11,Protection Region Base Address Register 11"
hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL1 MPU memory region"
bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable"
bitfld.long 0x00 1.--2. "AP,Access permission bits" "None/RW,R/W,None/RO,RO"
newline
bitfld.long 0x00 0. "XN,Execute-never" "0,1"
group.long c15:(0x0586+0x50)++0x00
line.long 0x00 "PRLAR11,Protection Region Limit Address Register 11"
hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL1 MPU memory region"
bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled"
group.long c15:(0x0086+0x60)++0x00 "Region 12"
line.long 0x00 "PRBAR12,Protection Region Base Address Register 12"
hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL1 MPU memory region"
bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable"
bitfld.long 0x00 1.--2. "AP,Access permission bits" "None/RW,R/W,None/RO,RO"
newline
bitfld.long 0x00 0. "XN,Execute-never" "0,1"
group.long c15:(0x0186+0x60)++0x00
line.long 0x00 "PRLAR12,Protection Region Limit Address Register 12"
hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL1 MPU memory region"
bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled"
group.long c15:(0x0486+0x60)++0x00 "Region 13"
line.long 0x00 "PRBAR13,Protection Region Base Address Register 13"
hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL1 MPU memory region"
bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable"
bitfld.long 0x00 1.--2. "AP,Access permission bits" "None/RW,R/W,None/RO,RO"
newline
bitfld.long 0x00 0. "XN,Execute-never" "0,1"
group.long c15:(0x0586+0x60)++0x00
line.long 0x00 "PRLAR13,Protection Region Limit Address Register 13"
hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL1 MPU memory region"
bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled"
group.long c15:(0x0086+0x70)++0x00 "Region 14"
line.long 0x00 "PRBAR14,Protection Region Base Address Register 14"
hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL1 MPU memory region"
bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable"
bitfld.long 0x00 1.--2. "AP,Access permission bits" "None/RW,R/W,None/RO,RO"
newline
bitfld.long 0x00 0. "XN,Execute-never" "0,1"
group.long c15:(0x0186+0x70)++0x00
line.long 0x00 "PRLAR14,Protection Region Limit Address Register 14"
hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL1 MPU memory region"
bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled"
group.long c15:(0x0486+0x70)++0x00 "Region 15"
line.long 0x00 "PRBAR15,Protection Region Base Address Register 15"
hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL1 MPU memory region"
bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable"
bitfld.long 0x00 1.--2. "AP,Access permission bits" "None/RW,R/W,None/RO,RO"
newline
bitfld.long 0x00 0. "XN,Execute-never" "0,1"
group.long c15:(0x0586+0x70)++0x00
line.long 0x00 "PRLAR15,Protection Region Limit Address Register 15"
hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL1 MPU memory region"
bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled"
else
hgroup.long c15:(0x0086+0x0)++0x00 "Region 0 (not implemented)"
hide.long 0x00 "PRBAR0,Protection Region Base Address Register 0"
newline
hgroup.long c15:(0x0186+0x0)++0x00
hide.long 0x00 "PRLAR0,Protection Region Limit Address Register 0"
hgroup.long c15:(0x0486+0x0)++0x00 "Region 1 (not implemented)"
hide.long 0x00 "PRBAR1,Protection Region Base Address Register 1"
newline
hgroup.long c15:(0x0586+0x0)++0x00
hide.long 0x00 "PRLAR1,Protection Region Limit Address Register 1"
hgroup.long c15:(0x0086+0x10)++0x00 "Region 2 (not implemented)"
hide.long 0x00 "PRBAR2,Protection Region Base Address Register 2"
newline
hgroup.long c15:(0x0186+0x10)++0x00
hide.long 0x00 "PRLAR2,Protection Region Limit Address Register 2"
hgroup.long c15:(0x0486+0x10)++0x00 "Region 3 (not implemented)"
hide.long 0x00 "PRBAR3,Protection Region Base Address Register 3"
newline
hgroup.long c15:(0x0586+0x10)++0x00
hide.long 0x00 "PRLAR3,Protection Region Limit Address Register 3"
hgroup.long c15:(0x0086+0x20)++0x00 "Region 4 (not implemented)"
hide.long 0x00 "PRBAR4,Protection Region Base Address Register 4"
newline
hgroup.long c15:(0x0186+0x20)++0x00
hide.long 0x00 "PRLAR4,Protection Region Limit Address Register 4"
hgroup.long c15:(0x0486+0x20)++0x00 "Region 5 (not implemented)"
hide.long 0x00 "PRBAR5,Protection Region Base Address Register 5"
newline
hgroup.long c15:(0x0586+0x20)++0x00
hide.long 0x00 "PRLAR5,Protection Region Limit Address Register 5"
hgroup.long c15:(0x0086+0x30)++0x00 "Region 6 (not implemented)"
hide.long 0x00 "PRBAR6,Protection Region Base Address Register 6"
newline
hgroup.long c15:(0x0186+0x30)++0x00
hide.long 0x00 "PRLAR6,Protection Region Limit Address Register 6"
hgroup.long c15:(0x0486+0x30)++0x00 "Region 7 (not implemented)"
hide.long 0x00 "PRBAR7,Protection Region Base Address Register 7"
newline
hgroup.long c15:(0x0586+0x30)++0x00
hide.long 0x00 "PRLAR7,Protection Region Limit Address Register 7"
hgroup.long c15:(0x0086+0x40)++0x00 "Region 8 (not implemented)"
hide.long 0x00 "PRBAR8,Protection Region Base Address Register 8"
newline
hgroup.long c15:(0x0186+0x40)++0x00
hide.long 0x00 "PRLAR8,Protection Region Limit Address Register 8"
hgroup.long c15:(0x0486+0x40)++0x00 "Region 9 (not implemented)"
hide.long 0x00 "PRBAR9,Protection Region Base Address Register 9"
newline
hgroup.long c15:(0x0586+0x40)++0x00
hide.long 0x00 "PRLAR9,Protection Region Limit Address Register 9"
hgroup.long c15:(0x0086+0x50)++0x00 "Region 10 (not implemented)"
hide.long 0x00 "PRBAR10,Protection Region Base Address Register 10"
newline
hgroup.long c15:(0x0186+0x50)++0x00
hide.long 0x00 "PRLAR10,Protection Region Limit Address Register 10"
hgroup.long c15:(0x0486+0x50)++0x00 "Region 11 (not implemented)"
hide.long 0x00 "PRBAR11,Protection Region Base Address Register 11"
newline
hgroup.long c15:(0x0586+0x50)++0x00
hide.long 0x00 "PRLAR11,Protection Region Limit Address Register 11"
hgroup.long c15:(0x0086+0x60)++0x00 "Region 12 (not implemented)"
hide.long 0x00 "PRBAR12,Protection Region Base Address Register 12"
newline
hgroup.long c15:(0x0186+0x60)++0x00
hide.long 0x00 "PRLAR12,Protection Region Limit Address Register 12"
hgroup.long c15:(0x0486+0x60)++0x00 "Region 13 (not implemented)"
hide.long 0x00 "PRBAR13,Protection Region Base Address Register 13"
newline
hgroup.long c15:(0x0586+0x60)++0x00
hide.long 0x00 "PRLAR13,Protection Region Limit Address Register 13"
hgroup.long c15:(0x0086+0x70)++0x00 "Region 14 (not implemented)"
hide.long 0x00 "PRBAR14,Protection Region Base Address Register 14"
newline
hgroup.long c15:(0x0186+0x70)++0x00
hide.long 0x00 "PRLAR14,Protection Region Limit Address Register 14"
hgroup.long c15:(0x0486+0x70)++0x00 "Region 15 (not implemented)"
hide.long 0x00 "PRBAR15,Protection Region Base Address Register 15"
newline
hgroup.long c15:(0x0586+0x70)++0x00
hide.long 0x00 "PRLAR15,Protection Region Limit Address Register 15"
endif
if (((per.l(c15:0x400))&0xFF00)>=0x1400)
group.long c15:(0x1086+0x0)++0x00 "Region 16"
line.long 0x00 "PRBAR16,Protection Region Base Address Register 16"
hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL1 MPU memory region"
bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. "AP,Access Permission bits" "None/RW,R/W,None/RO,RO"
newline
bitfld.long 0x00 0. "XN,Execute-never" "0,1"
group.long c15:(0x1186+0x0)++0x00
line.long 0x00 "PRLAR16,Protection Region Limit Address Register 16"
hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL1 MPU memory region"
bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled"
group.long c15:(0x1486+0x0)++0x00 "Region 17"
line.long 0x00 "PRBAR17,Protection Region Base Address Register 17"
hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL1 MPU memory region"
bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable"
bitfld.long 0x00 1.--2. "AP,Access Permission bits" "None/RW,R/W,None/RO,RO"
newline
bitfld.long 0x00 0. "XN,Execute-never" "0,1"
group.long c15:(0x1586+0x0)++0x00
line.long 0x00 "PRLAR17,Protection Region Limit Address Register 17"
hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL1 MPU memory region"
bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled"
group.long c15:(0x1086+0x10)++0x00 "Region 18"
line.long 0x00 "PRBAR18,Protection Region Base Address Register 18"
hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL1 MPU memory region"
bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. "AP,Access Permission bits" "None/RW,R/W,None/RO,RO"
newline
bitfld.long 0x00 0. "XN,Execute-never" "0,1"
group.long c15:(0x1186+0x10)++0x00
line.long 0x00 "PRLAR18,Protection Region Limit Address Register 18"
hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL1 MPU memory region"
bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled"
group.long c15:(0x1486+0x10)++0x00 "Region 19"
line.long 0x00 "PRBAR19,Protection Region Base Address Register 19"
hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL1 MPU memory region"
bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable"
bitfld.long 0x00 1.--2. "AP,Access Permission bits" "None/RW,R/W,None/RO,RO"
newline
bitfld.long 0x00 0. "XN,Execute-never" "0,1"
group.long c15:(0x1586+0x10)++0x00
line.long 0x00 "PRLAR19,Protection Region Limit Address Register 19"
hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL1 MPU memory region"
bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled"
else
hgroup.long c15:(0x1086+0x0)++0x00 "Region 16 (not implemented)"
hide.long 0x00 "PRBAR16,Protection Region Base Address Register 16"
newline
hgroup.long c15:(0x1186+0x0)++0x00
hide.long 0x00 "PRLAR16,Protection Region Limit Address Register 16"
hgroup.long c15:(0x1486+0x0)++0x00 "Region 17 (not implemented)"
hide.long 0x00 "PRBAR17,Protection Region Base Address Register 17"
newline
hgroup.long c15:(0x1586+0x0)++0x00
hide.long 0x00 "PRLAR17,Protection Region Limit Address Register 17"
hgroup.long c15:(0x1086+0x10)++0x00 "Region 18 (not implemented)"
hide.long 0x00 "PRBAR18,Protection Region Base Address Register 18"
newline
hgroup.long c15:(0x1186+0x10)++0x00
hide.long 0x00 "PRLAR18,Protection Region Limit Address Register 18"
hgroup.long c15:(0x1486+0x10)++0x00 "Region 19 (not implemented)"
hide.long 0x00 "PRBAR19,Protection Region Base Address Register 19"
newline
hgroup.long c15:(0x1586+0x10)++0x00
hide.long 0x00 "PRLAR19,Protection Region Limit Address Register 19"
endif
if (((per.l(c15:0x400))&0xFF00)>=0x1800)
group.long c15:(0x1086+0x20)++0x00 "Region 20"
line.long 0x00 "PRBAR20,Protection Region Base Address Register 20"
hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL1 MPU memory region"
bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. "AP,Access Permission bits" "None/RW,R/W,None/RO,RO"
newline
bitfld.long 0x00 0. "XN,Execute-never" "0,1"
group.long c15:(0x1186+0x20)++0x00
line.long 0x00 "PRLAR20,Protection Region Limit Address Register 20"
hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL1 MPU memory region"
bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled"
group.long c15:(0x1486+0x20)++0x00 "Region 21"
line.long 0x00 "PRBAR21,Protection Region Base Address Register 21"
hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL1 MPU memory region"
bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable"
bitfld.long 0x00 1.--2. "AP,Access Permission bits" "None/RW,R/W,None/RO,RO"
newline
bitfld.long 0x00 0. "XN,Execute-never" "0,1"
group.long c15:(0x1586+0x20)++0x00
line.long 0x00 "PRLAR21,Protection Region Limit Address Register 21"
hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL1 MPU memory region"
bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled"
group.long c15:(0x1086+0x30)++0x00 "Region 22"
line.long 0x00 "PRBAR22,Protection Region Base Address Register 22"
hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL1 MPU memory region"
bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. "AP,Access Permission bits" "None/RW,R/W,None/RO,RO"
newline
bitfld.long 0x00 0. "XN,Execute-never" "0,1"
group.long c15:(0x1186+0x30)++0x00
line.long 0x00 "PRLAR22,Protection Region Limit Address Register 22"
hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL1 MPU memory region"
bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled"
group.long c15:(0x1486+0x30)++0x00 "Region 23"
line.long 0x00 "PRBAR23,Protection Region Base Address Register 23"
hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL1 MPU memory region"
bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable"
bitfld.long 0x00 1.--2. "AP,Access Permission bits" "None/RW,R/W,None/RO,RO"
newline
bitfld.long 0x00 0. "XN,Execute-never" "0,1"
group.long c15:(0x1586+0x30)++0x00
line.long 0x00 "PRLAR23,Protection Region Limit Address Register 23"
hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL1 MPU memory region"
bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled"
else
hgroup.long c15:(0x1086+0x20)++0x00 "Region 20 (not implemented)"
hide.long 0x00 "PRBAR20,Protection Region Base Address Register 20"
newline
hgroup.long c15:(0x1186+0x20)++0x00
hide.long 0x00 "PRLAR20,Protection Region Limit Address Register 20"
hgroup.long c15:(0x1486+0x20)++0x00 "Region 21 (not implemented)"
hide.long 0x00 "PRBAR21,Protection Region Base Address Register 21"
newline
hgroup.long c15:(0x1586+0x20)++0x00
hide.long 0x00 "PRLAR21,Protection Region Limit Address Register 21"
hgroup.long c15:(0x1086+0x30)++0x00 "Region 22 (not implemented)"
hide.long 0x00 "PRBAR22,Protection Region Base Address Register 22"
newline
hgroup.long c15:(0x1186+0x30)++0x00
hide.long 0x00 "PRLAR22,Protection Region Limit Address Register 22"
hgroup.long c15:(0x1486+0x30)++0x00 "Region 23 (not implemented)"
hide.long 0x00 "PRBAR23,Protection Region Base Address Register 23"
newline
hgroup.long c15:(0x1586+0x30)++0x00
hide.long 0x00 "PRLAR23,Protection Region Limit Address Register 23"
endif
tree.end
tree.end
tree "Memory Protection Unit PL2"
rgroup.long c15:0x4400++0x00
line.long 0x00 "HMPUIR,Hypervisor MPU Type Register"
bitfld.long 0x00 0.--7. 1. "REGION,Identifies the number of implemented regions" "0,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16,Reserved,Reserved,Reserved,20,Reserved,Reserved,Reserved,24,?..."
if (((per.l(c15:0x4400))&0xFF)>=0x18)
group.long c15:0x4116++0x00
line.long 0x00 "HPRENR,Hypervisor MPU Region Enable Register"
bitfld.long 0x00 23. "EN23,Region enable 23" "Disabled,Enabled"
bitfld.long 0x00 22. "EN22,Region enable 22" "Disabled,Enabled"
bitfld.long 0x00 21. "EN21,Region enable 21" "Disabled,Enabled"
newline
bitfld.long 0x00 20. "EN20,Region enable 20" "Disabled,Enabled"
bitfld.long 0x00 19. "EN19,Region enable 19" "Disabled,Enabled"
bitfld.long 0x00 18. "EN18,Region enable 18" "Disabled,Enabled"
newline
bitfld.long 0x00 17. "EN17,Region enable 17" "Disabled,Enabled"
bitfld.long 0x00 16. "EN16,Region enable 16" "Disabled,Enabled"
bitfld.long 0x00 15. "EN15,Region enable 15" "Disabled,Enabled"
newline
bitfld.long 0x00 14. "EN14,Region enable 14" "Disabled,Enabled"
bitfld.long 0x00 13. "EN13,Region enable 13" "Disabled,Enabled"
bitfld.long 0x00 12. "EN12,Region enable 12" "Disabled,Enabled"
newline
bitfld.long 0x00 11. "EN11,Region enable 11" "Disabled,Enabled"
bitfld.long 0x00 10. "EN10,Region enable 10" "Disabled,Enabled"
bitfld.long 0x00 9. "EN9,Region enable 9" "Disabled,Enabled"
newline
bitfld.long 0x00 8. "EN8,Region enable 8" "Disabled,Enabled"
bitfld.long 0x00 7. "EN7,Region enable 7" "Disabled,Enabled"
bitfld.long 0x00 6. "EN6,Region enable 6" "Disabled,Enabled"
newline
bitfld.long 0x00 5. "EN5,Region enable 5" "Disabled,Enabled"
bitfld.long 0x00 4. "EN4,Region enable 4" "Disabled,Enabled"
bitfld.long 0x00 3. "EN3,Region enable 3" "Disabled,Enabled"
newline
bitfld.long 0x00 2. "EN2,Region enable 2" "Disabled,Enabled"
bitfld.long 0x00 1. "EN1,Region enable 1" "Disabled,Enabled"
bitfld.long 0x00 0. "EN0,Region enable 0" "Disabled,Enabled"
elif (((per.l(c15:0x4400))&0xFF)>=0x14)
group.long c15:0x4116++0x00
line.long 0x00 "HPRENR,Hypervisor MPU Region Enable Register"
bitfld.long 0x00 19. "EN19,Region enable 19" "Disabled,Enabled"
bitfld.long 0x00 18. "EN18,Region enable 18" "Disabled,Enabled"
bitfld.long 0x00 17. "EN17,Region enable 17" "Disabled,Enabled"
newline
bitfld.long 0x00 16. "EN16,Region enable 16" "Disabled,Enabled"
bitfld.long 0x00 15. "EN15,Region enable 15" "Disabled,Enabled"
bitfld.long 0x00 14. "EN14,Region enable 14" "Disabled,Enabled"
newline
bitfld.long 0x00 13. "EN13,Region enable 13" "Disabled,Enabled"
bitfld.long 0x00 12. "EN12,Region enable 12" "Disabled,Enabled"
bitfld.long 0x00 11. "EN11,Region enable 11" "Disabled,Enabled"
newline
bitfld.long 0x00 10. "EN10,Region enable 10" "Disabled,Enabled"
bitfld.long 0x00 9. "EN9,Region enable 9" "Disabled,Enabled"
bitfld.long 0x00 8. "EN8,Region enable 8" "Disabled,Enabled"
newline
bitfld.long 0x00 7. "EN7,Region enable 7" "Disabled,Enabled"
bitfld.long 0x00 6. "EN6,Region enable 6" "Disabled,Enabled"
bitfld.long 0x00 5. "EN5,Region enable 5" "Disabled,Enabled"
newline
bitfld.long 0x00 4. "EN4,Region enable 4" "Disabled,Enabled"
bitfld.long 0x00 3. "EN3,Region enable 3" "Disabled,Enabled"
bitfld.long 0x00 2. "EN2,Region enable 2" "Disabled,Enabled"
newline
bitfld.long 0x00 1. "EN1,Region enable 1" "Disabled,Enabled"
bitfld.long 0x00 0. "EN0,Region enable 0" "Disabled,Enabled"
elif (((per.l(c15:0x4400))&0xFF)>=0x10)
group.long c15:0x4116++0x00
line.long 0x00 "HPRENR,Hypervisor MPU Region Enable Register"
bitfld.long 0x00 15. "EN15,Region enable 15" "Disabled,Enabled"
bitfld.long 0x00 14. "EN14,Region enable 14" "Disabled,Enabled"
bitfld.long 0x00 13. "EN13,Region enable 13" "Disabled,Enabled"
newline
bitfld.long 0x00 12. "EN12,Region enable 12" "Disabled,Enabled"
bitfld.long 0x00 11. "EN11,Region enable 11" "Disabled,Enabled"
bitfld.long 0x00 10. "EN10,Region enable 10" "Disabled,Enabled"
newline
bitfld.long 0x00 9. "EN9,Region enable 9" "Disabled,Enabled"
bitfld.long 0x00 8. "EN8,Region enable 8" "Disabled,Enabled"
bitfld.long 0x00 7. "EN7,Region enable 7" "Disabled,Enabled"
newline
bitfld.long 0x00 6. "EN6,Region enable 6" "Disabled,Enabled"
bitfld.long 0x00 5. "EN5,Region enable 5" "Disabled,Enabled"
bitfld.long 0x00 4. "EN4,Region enable 4" "Disabled,Enabled"
newline
bitfld.long 0x00 3. "EN3,Region enable 3" "Disabled,Enabled"
bitfld.long 0x00 2. "EN2,Region enable 2" "Disabled,Enabled"
bitfld.long 0x00 1. "EN1,Region enable 1" "Disabled,Enabled"
newline
bitfld.long 0x00 0. "EN0,Region enable 0" "Disabled,Enabled"
else
rgroup.long c15:0x4116++0x00
line.long 0x00 "HPRENR,Hypervisor MPU Region Enable Register"
endif
if (((per.l(c15:0x4400))&0xFF)>=0x18)
group.long c15:0x4126++0x00
line.long 0x00 "HPRSELR,Hypervisor Protection Region Selection Register"
bitfld.long 0x00 0.--4. "REGION,The number of the current region visible in HPRBAR and HPRLAR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
elif (((per.l(c15:0x4400))&0xFF)>=0x14)
group.long c15:0x4126++0x00
line.long 0x00 "HPRSELR,Hypervisor Protection Region Selection Register"
bitfld.long 0x00 0.--4. "REGION,The number of the current region visible in HPRBAR and HPRLAR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,?..."
elif (((per.l(c15:0x4400))&0xFF)>=0x10)
group.long c15:0x4126++0x00
line.long 0x00 "HPRSELR,Hypervisor Protection Region Selection Register"
bitfld.long 0x00 0.--3. "REGION,The number of the current region visible in HPRBAR and HPRLAR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
else
hgroup.long c15:0x4126++0x00
hide.long 0x00 "HPRSELR,Hypervisor Protection Region Selection Register"
endif
group.long c15:0x4036++0x00
line.long 0x00 "HPRBAR,Hypervisor Protection Region Base Address Register"
hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL2 MPU memory region"
bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable"
bitfld.long 0x00 1.--2. "AP,Access permission bits" "R/W EL2 only,R/W,RO EL2 only,RO"
newline
bitfld.long 0x00 0. "XN,Execute-never" "0,1"
group.long c15:0x4136++0x00
line.long 0x00 "HPRLAR,Hypervisor Protection Region Limit Address Register"
hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL2 MPU memory region"
bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled"
tree "MPU regions"
if (((per.l(c15:0x4400))&0xFF)>=0x10)
group.long c15:(0x4086+0x0)++0x00 "Region 0"
line.long 0x00 "HPRBAR0,Hypervisor Protection Region Base Address Register 0"
hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL2 MPU memory region"
bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable"
bitfld.long 0x00 1.--2. "AP,Access permission bits" "R/W PL2 only,R/W,RO PL2 only,RO"
newline
bitfld.long 0x00 0. "XN,Execute-never" "0,1"
group.long c15:(0x4186+0x0)++0x00
line.long 0x00 "HPRLAR0,Hypervisor Protection Region Limit Address Register 0"
hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL2 MPU memory region"
bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled"
group.long c15:(0x4486+0x0)++0x00 "Region 1"
line.long 0x00 "HPRBAR1,Hypervisor Protection Region Base Address Register 1"
hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL2 MPU memory region"
bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable"
bitfld.long 0x00 1.--2. "AP,Access permission bits" "R/W PL2 only,R/W,RO PL2 only,RO"
newline
bitfld.long 0x00 0. "XN,Execute-never" "0,1"
group.long c15:(0x4586+0x0)++0x00
line.long 0x00 "HPRLAR1,Hypervisor Protection Region Limit Address Register 1"
hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL2 MPU memory region"
bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled"
group.long c15:(0x4086+0x10)++0x00 "Region 2"
line.long 0x00 "HPRBAR2,Hypervisor Protection Region Base Address Register 2"
hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL2 MPU memory region"
bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable"
bitfld.long 0x00 1.--2. "AP,Access permission bits" "R/W PL2 only,R/W,RO PL2 only,RO"
newline
bitfld.long 0x00 0. "XN,Execute-never" "0,1"
group.long c15:(0x4186+0x10)++0x00
line.long 0x00 "HPRLAR2,Hypervisor Protection Region Limit Address Register 2"
hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL2 MPU memory region"
bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled"
group.long c15:(0x4486+0x10)++0x00 "Region 3"
line.long 0x00 "HPRBAR3,Hypervisor Protection Region Base Address Register 3"
hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL2 MPU memory region"
bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable"
bitfld.long 0x00 1.--2. "AP,Access permission bits" "R/W PL2 only,R/W,RO PL2 only,RO"
newline
bitfld.long 0x00 0. "XN,Execute-never" "0,1"
group.long c15:(0x4586+0x10)++0x00
line.long 0x00 "HPRLAR3,Hypervisor Protection Region Limit Address Register 3"
hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL2 MPU memory region"
bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled"
group.long c15:(0x4086+0x20)++0x00 "Region 4"
line.long 0x00 "HPRBAR4,Hypervisor Protection Region Base Address Register 4"
hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL2 MPU memory region"
bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable"
bitfld.long 0x00 1.--2. "AP,Access permission bits" "R/W PL2 only,R/W,RO PL2 only,RO"
newline
bitfld.long 0x00 0. "XN,Execute-never" "0,1"
group.long c15:(0x4186+0x20)++0x00
line.long 0x00 "HPRLAR4,Hypervisor Protection Region Limit Address Register 4"
hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL2 MPU memory region"
bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled"
group.long c15:(0x4486+0x20)++0x00 "Region 5"
line.long 0x00 "HPRBAR5,Hypervisor Protection Region Base Address Register 5"
hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL2 MPU memory region"
bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable"
bitfld.long 0x00 1.--2. "AP,Access permission bits" "R/W PL2 only,R/W,RO PL2 only,RO"
newline
bitfld.long 0x00 0. "XN,Execute-never" "0,1"
group.long c15:(0x4586+0x20)++0x00
line.long 0x00 "HPRLAR5,Hypervisor Protection Region Limit Address Register 5"
hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL2 MPU memory region"
bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled"
group.long c15:(0x4086+0x30)++0x00 "Region 6"
line.long 0x00 "HPRBAR6,Hypervisor Protection Region Base Address Register 6"
hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL2 MPU memory region"
bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable"
bitfld.long 0x00 1.--2. "AP,Access permission bits" "R/W PL2 only,R/W,RO PL2 only,RO"
newline
bitfld.long 0x00 0. "XN,Execute-never" "0,1"
group.long c15:(0x4186+0x30)++0x00
line.long 0x00 "HPRLAR6,Hypervisor Protection Region Limit Address Register 6"
hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL2 MPU memory region"
bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled"
group.long c15:(0x4486+0x30)++0x00 "Region 7"
line.long 0x00 "HPRBAR7,Hypervisor Protection Region Base Address Register 7"
hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL2 MPU memory region"
bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable"
bitfld.long 0x00 1.--2. "AP,Access permission bits" "R/W PL2 only,R/W,RO PL2 only,RO"
newline
bitfld.long 0x00 0. "XN,Execute-never" "0,1"
group.long c15:(0x4586+0x30)++0x00
line.long 0x00 "HPRLAR7,Hypervisor Protection Region Limit Address Register 7"
hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL2 MPU memory region"
bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled"
group.long c15:(0x4086+0x40)++0x00 "Region 8"
line.long 0x00 "HPRBAR8,Hypervisor Protection Region Base Address Register 8"
hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL2 MPU memory region"
bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable"
bitfld.long 0x00 1.--2. "AP,Access permission bits" "R/W PL2 only,R/W,RO PL2 only,RO"
newline
bitfld.long 0x00 0. "XN,Execute-never" "0,1"
group.long c15:(0x4186+0x40)++0x00
line.long 0x00 "HPRLAR8,Hypervisor Protection Region Limit Address Register 8"
hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL2 MPU memory region"
bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled"
group.long c15:(0x4486+0x40)++0x00 "Region 9"
line.long 0x00 "HPRBAR9,Hypervisor Protection Region Base Address Register 9"
hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL2 MPU memory region"
bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable"
bitfld.long 0x00 1.--2. "AP,Access permission bits" "R/W PL2 only,R/W,RO PL2 only,RO"
newline
bitfld.long 0x00 0. "XN,Execute-never" "0,1"
group.long c15:(0x4586+0x40)++0x00
line.long 0x00 "HPRLAR9,Hypervisor Protection Region Limit Address Register 9"
hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL2 MPU memory region"
bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled"
group.long c15:(0x4086+0x50)++0x00 "Region 10"
line.long 0x00 "HPRBAR10,Hypervisor Protection Region Base Address Register 10"
hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL2 MPU memory region"
bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable"
bitfld.long 0x00 1.--2. "AP,Access permission bits" "R/W PL2 only,R/W,RO PL2 only,RO"
newline
bitfld.long 0x00 0. "XN,Execute-never" "0,1"
group.long c15:(0x4186+0x50)++0x00
line.long 0x00 "HPRLAR10,Hypervisor Protection Region Limit Address Register 10"
hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL2 MPU memory region"
bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled"
group.long c15:(0x4486+0x50)++0x00 "Region 11"
line.long 0x00 "HPRBAR11,Hypervisor Protection Region Base Address Register 11"
hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL2 MPU memory region"
bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable"
bitfld.long 0x00 1.--2. "AP,Access permission bits" "R/W PL2 only,R/W,RO PL2 only,RO"
newline
bitfld.long 0x00 0. "XN,Execute-never" "0,1"
group.long c15:(0x4586+0x50)++0x00
line.long 0x00 "HPRLAR11,Hypervisor Protection Region Limit Address Register 11"
hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL2 MPU memory region"
bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled"
group.long c15:(0x4086+0x60)++0x00 "Region 12"
line.long 0x00 "HPRBAR12,Hypervisor Protection Region Base Address Register 12"
hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL2 MPU memory region"
bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable"
bitfld.long 0x00 1.--2. "AP,Access permission bits" "R/W PL2 only,R/W,RO PL2 only,RO"
newline
bitfld.long 0x00 0. "XN,Execute-never" "0,1"
group.long c15:(0x4186+0x60)++0x00
line.long 0x00 "HPRLAR12,Hypervisor Protection Region Limit Address Register 12"
hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL2 MPU memory region"
bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled"
group.long c15:(0x4486+0x60)++0x00 "Region 13"
line.long 0x00 "HPRBAR13,Hypervisor Protection Region Base Address Register 13"
hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL2 MPU memory region"
bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable"
bitfld.long 0x00 1.--2. "AP,Access permission bits" "R/W PL2 only,R/W,RO PL2 only,RO"
newline
bitfld.long 0x00 0. "XN,Execute-never" "0,1"
group.long c15:(0x4586+0x60)++0x00
line.long 0x00 "HPRLAR13,Hypervisor Protection Region Limit Address Register 13"
hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL2 MPU memory region"
bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled"
group.long c15:(0x4086+0x70)++0x00 "Region 14"
line.long 0x00 "HPRBAR14,Hypervisor Protection Region Base Address Register 14"
hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL2 MPU memory region"
bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable"
bitfld.long 0x00 1.--2. "AP,Access permission bits" "R/W PL2 only,R/W,RO PL2 only,RO"
newline
bitfld.long 0x00 0. "XN,Execute-never" "0,1"
group.long c15:(0x4186+0x70)++0x00
line.long 0x00 "HPRLAR14,Hypervisor Protection Region Limit Address Register 14"
hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL2 MPU memory region"
bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled"
group.long c15:(0x4486+0x70)++0x00 "Region 15"
line.long 0x00 "HPRBAR15,Hypervisor Protection Region Base Address Register 15"
hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL2 MPU memory region"
bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable"
bitfld.long 0x00 1.--2. "AP,Access permission bits" "R/W PL2 only,R/W,RO PL2 only,RO"
newline
bitfld.long 0x00 0. "XN,Execute-never" "0,1"
group.long c15:(0x4586+0x70)++0x00
line.long 0x00 "HPRLAR15,Hypervisor Protection Region Limit Address Register 15"
hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL2 MPU memory region"
bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled"
else
hgroup.long c15:(0x4086+0x0)++0x00 "Region 0 (not implemented)"
hide.long 0x00 "HPRBAR0,Hypervisor Protection Region Base Address Register 0"
newline
hgroup.long c15:(0x4186+0x0)++0x00
hide.long 0x00 "HPRLAR0,Hypervisor Protection Region Limit Address Register 0"
hgroup.long c15:(0x4486+0x0)++0x00 "Region 1 (not implemented)"
hide.long 0x00 "HPRBAR1,Hypervisor Protection Region Base Address Register 1"
newline
hgroup.long c15:(0x4586+0x0)++0x00
hide.long 0x00 "HPRLAR1,Hypervisor Protection Region Limit Address Register 1"
hgroup.long c15:(0x4086+0x10)++0x00 "Region 2 (not implemented)"
hide.long 0x00 "HPRBAR2,Hypervisor Protection Region Base Address Register 2"
newline
hgroup.long c15:(0x4186+0x10)++0x00
hide.long 0x00 "HPRLAR2,Hypervisor Protection Region Limit Address Register 2"
hgroup.long c15:(0x4486+0x10)++0x00 "Region 3 (not implemented)"
hide.long 0x00 "HPRBAR3,Hypervisor Protection Region Base Address Register 3"
newline
hgroup.long c15:(0x4586+0x10)++0x00
hide.long 0x00 "HPRLAR3,Hypervisor Protection Region Limit Address Register 3"
hgroup.long c15:(0x4086+0x20)++0x00 "Region 4 (not implemented)"
hide.long 0x00 "HPRBAR4,Hypervisor Protection Region Base Address Register 4"
newline
hgroup.long c15:(0x4186+0x20)++0x00
hide.long 0x00 "HPRLAR4,Hypervisor Protection Region Limit Address Register 4"
hgroup.long c15:(0x4486+0x20)++0x00 "Region 5 (not implemented)"
hide.long 0x00 "HPRBAR5,Hypervisor Protection Region Base Address Register 5"
newline
hgroup.long c15:(0x4586+0x20)++0x00
hide.long 0x00 "HPRLAR5,Hypervisor Protection Region Limit Address Register 5"
hgroup.long c15:(0x4086+0x30)++0x00 "Region 6 (not implemented)"
hide.long 0x00 "HPRBAR6,Hypervisor Protection Region Base Address Register 6"
newline
hgroup.long c15:(0x4186+0x30)++0x00
hide.long 0x00 "HPRLAR6,Hypervisor Protection Region Limit Address Register 6"
hgroup.long c15:(0x4486+0x30)++0x00 "Region 7 (not implemented)"
hide.long 0x00 "HPRBAR7,Hypervisor Protection Region Base Address Register 7"
newline
hgroup.long c15:(0x4586+0x30)++0x00
hide.long 0x00 "HPRLAR7,Hypervisor Protection Region Limit Address Register 7"
hgroup.long c15:(0x4086+0x40)++0x00 "Region 8 (not implemented)"
hide.long 0x00 "HPRBAR8,Hypervisor Protection Region Base Address Register 8"
newline
hgroup.long c15:(0x4186+0x40)++0x00
hide.long 0x00 "HPRLAR8,Hypervisor Protection Region Limit Address Register 8"
hgroup.long c15:(0x4486+0x40)++0x00 "Region 9 (not implemented)"
hide.long 0x00 "HPRBAR9,Hypervisor Protection Region Base Address Register 9"
newline
hgroup.long c15:(0x4586+0x40)++0x00
hide.long 0x00 "HPRLAR9,Hypervisor Protection Region Limit Address Register 9"
hgroup.long c15:(0x4086+0x50)++0x00 "Region 10 (not implemented)"
hide.long 0x00 "HPRBAR10,Hypervisor Protection Region Base Address Register 10"
newline
hgroup.long c15:(0x4186+0x50)++0x00
hide.long 0x00 "HPRLAR10,Hypervisor Protection Region Limit Address Register 10"
hgroup.long c15:(0x4486+0x50)++0x00 "Region 11 (not implemented)"
hide.long 0x00 "HPRBAR11,Hypervisor Protection Region Base Address Register 11"
newline
hgroup.long c15:(0x4586+0x50)++0x00
hide.long 0x00 "HPRLAR11,Hypervisor Protection Region Limit Address Register 11"
hgroup.long c15:(0x4086+0x60)++0x00 "Region 12 (not implemented)"
hide.long 0x00 "HPRBAR12,Hypervisor Protection Region Base Address Register 12"
newline
hgroup.long c15:(0x4186+0x60)++0x00
hide.long 0x00 "HPRLAR12,Hypervisor Protection Region Limit Address Register 12"
hgroup.long c15:(0x4486+0x60)++0x00 "Region 13 (not implemented)"
hide.long 0x00 "HPRBAR13,Hypervisor Protection Region Base Address Register 13"
newline
hgroup.long c15:(0x4586+0x60)++0x00
hide.long 0x00 "HPRLAR13,Hypervisor Protection Region Limit Address Register 13"
hgroup.long c15:(0x4086+0x70)++0x00 "Region 14 (not implemented)"
hide.long 0x00 "HPRBAR14,Hypervisor Protection Region Base Address Register 14"
newline
hgroup.long c15:(0x4186+0x70)++0x00
hide.long 0x00 "HPRLAR14,Hypervisor Protection Region Limit Address Register 14"
hgroup.long c15:(0x4486+0x70)++0x00 "Region 15 (not implemented)"
hide.long 0x00 "HPRBAR15,Hypervisor Protection Region Base Address Register 15"
newline
hgroup.long c15:(0x4586+0x70)++0x00
hide.long 0x00 "HPRLAR15,Hypervisor Protection Region Limit Address Register 15"
endif
if (((per.l(c15:0x4400))&0xFF)>=0x14)
group.long c15:(0x5086+0x0)++0x00 "Region 16"
line.long 0x00 "HPRBAR16,Hypervisor Protection Region Base Address Register 16"
hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL2 MPU memory region"
bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable"
bitfld.long 0x00 1.--2. "AP,Access permission bits" "R/W PL2 only,R/W,RO PL2 only,RO"
newline
bitfld.long 0x00 0. "XN,Execute-never" "0,1"
group.long c15:(0x5186+0x0)++0x00
line.long 0x00 "HPRLAR16,Hypervisor Protection Region Limit Address Register 16"
hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL2 MPU memory region"
bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled"
group.long c15:(0x5486+0x0)++0x00 "Region 17"
line.long 0x00 "HPRBAR17,Hypervisor Protection Region Base Address Register 17"
hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL2 MPU memory region"
bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable"
bitfld.long 0x00 1.--2. "AP,Access permission bits" "R/W PL2 only,R/W,RO PL2 only,RO"
newline
bitfld.long 0x00 0. "XN,Execute-never" "0,1"
group.long c15:(0x5586+0x0)++0x00
line.long 0x00 "HPRLAR17,Hypervisor Protection Region Limit Address Register 17"
hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL2 MPU memory region"
bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled"
group.long c15:(0x5086+0x10)++0x00 "Region 18"
line.long 0x00 "HPRBAR18,Hypervisor Protection Region Base Address Register 18"
hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL2 MPU memory region"
bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable"
bitfld.long 0x00 1.--2. "AP,Access permission bits" "R/W PL2 only,R/W,RO PL2 only,RO"
newline
bitfld.long 0x00 0. "XN,Execute-never" "0,1"
group.long c15:(0x5186+0x10)++0x00
line.long 0x00 "HPRLAR18,Hypervisor Protection Region Limit Address Register 18"
hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL2 MPU memory region"
bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled"
group.long c15:(0x5486+0x10)++0x00 "Region 19"
line.long 0x00 "HPRBAR19,Hypervisor Protection Region Base Address Register 19"
hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL2 MPU memory region"
bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable"
bitfld.long 0x00 1.--2. "AP,Access permission bits" "R/W PL2 only,R/W,RO PL2 only,RO"
newline
bitfld.long 0x00 0. "XN,Execute-never" "0,1"
group.long c15:(0x5586+0x10)++0x00
line.long 0x00 "HPRLAR19,Hypervisor Protection Region Limit Address Register 19"
hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL2 MPU memory region"
bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled"
else
hgroup.long c15:(0x5086+0x0)++0x00 "Region 16 (not implemented)"
hide.long 0x00 "HPRBAR16,Hypervisor Protection Region Base Address Register 16"
newline
hgroup.long c15:(0x5186+0x0)++0x00
hide.long 0x00 "HPRLAR16,Hypervisor Protection Region Limit Address Register 16"
hgroup.long c15:(0x5486+0x0)++0x00 "Region 17 (not implemented)"
hide.long 0x00 "HPRBAR17,Hypervisor Protection Region Base Address Register 17"
newline
hgroup.long c15:(0x5586+0x0)++0x00
hide.long 0x00 "HPRLAR17,Hypervisor Protection Region Limit Address Register 17"
hgroup.long c15:(0x5086+0x10)++0x00 "Region 18 (not implemented)"
hide.long 0x00 "HPRBAR18,Hypervisor Protection Region Base Address Register 18"
newline
hgroup.long c15:(0x5186+0x10)++0x00
hide.long 0x00 "HPRLAR18,Hypervisor Protection Region Limit Address Register 18"
hgroup.long c15:(0x5486+0x10)++0x00 "Region 19 (not implemented)"
hide.long 0x00 "HPRBAR19,Hypervisor Protection Region Base Address Register 19"
newline
hgroup.long c15:(0x5586+0x10)++0x00
hide.long 0x00 "HPRLAR19,Hypervisor Protection Region Limit Address Register 19"
endif
if (((per.l(c15:0x4400))&0xFF)>=0x18)
group.long c15:(0x5086+0x20)++0x00 "Region 20"
line.long 0x00 "HPRBAR20,Hypervisor Protection Region Base Address Register 20"
hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL2 MPU memory region"
bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable"
bitfld.long 0x00 1.--2. "AP,Access permission bits" "R/W PL2 only,R/W,RO PL2 only,RO"
newline
bitfld.long 0x00 0. "XN,Execute-never" "0,1"
group.long c15:(0x5186+0x20)++0x00
line.long 0x00 "HPRLAR20,Hypervisor Protection Region Limit Address Register 20"
hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL2 MPU memory region"
bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled"
group.long c15:(0x5486+0x20)++0x00 "Region 21"
line.long 0x00 "HPRBAR21,Hypervisor Protection Region Base Address Register 21"
hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL2 MPU memory region"
bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable"
bitfld.long 0x00 1.--2. "AP,Access permission bits" "R/W PL2 only,R/W,RO PL2 only,RO"
newline
bitfld.long 0x00 0. "XN,Execute-never" "0,1"
group.long c15:(0x5586+0x20)++0x00
line.long 0x00 "HPRLAR21,Hypervisor Protection Region Limit Address Register 21"
hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL2 MPU memory region"
bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled"
group.long c15:(0x5086+0x30)++0x00 "Region 22"
line.long 0x00 "HPRBAR22,Hypervisor Protection Region Base Address Register 22"
hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL2 MPU memory region"
bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable"
bitfld.long 0x00 1.--2. "AP,Access permission bits" "R/W PL2 only,R/W,RO PL2 only,RO"
newline
bitfld.long 0x00 0. "XN,Execute-never" "0,1"
group.long c15:(0x5186+0x30)++0x00
line.long 0x00 "HPRLAR22,Hypervisor Protection Region Limit Address Register 22"
hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL2 MPU memory region"
bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled"
group.long c15:(0x5486+0x30)++0x00 "Region 23"
line.long 0x00 "HPRBAR23,Hypervisor Protection Region Base Address Register 23"
hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected PL2 MPU memory region"
bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable"
bitfld.long 0x00 1.--2. "AP,Access permission bits" "R/W PL2 only,R/W,RO PL2 only,RO"
newline
bitfld.long 0x00 0. "XN,Execute-never" "0,1"
group.long c15:(0x5586+0x30)++0x00
line.long 0x00 "HPRLAR23,Hypervisor Protection Region Limit Address Register 23"
hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected PL2 MPU memory region"
bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled"
else
hgroup.long c15:(0x5086+0x20)++0x00 "Region 20 (not implemented)"
hide.long 0x00 "HPRBAR20,Hypervisor Protection Region Base Address Register 20"
newline
hgroup.long c15:(0x5186+0x20)++0x00
hide.long 0x00 "HPRLAR20,Hypervisor Protection Region Limit Address Register 20"
hgroup.long c15:(0x5486+0x20)++0x00 "Region 21 (not implemented)"
hide.long 0x00 "HPRBAR21,Hypervisor Protection Region Base Address Register 21"
newline
hgroup.long c15:(0x5586+0x20)++0x00
hide.long 0x00 "HPRLAR21,Hypervisor Protection Region Limit Address Register 21"
hgroup.long c15:(0x5086+0x30)++0x00 "Region 22 (not implemented)"
hide.long 0x00 "HPRBAR22,Hypervisor Protection Region Base Address Register 22"
newline
hgroup.long c15:(0x5186+0x30)++0x00
hide.long 0x00 "HPRLAR22,Hypervisor Protection Region Limit Address Register 22"
hgroup.long c15:(0x5486+0x30)++0x00 "Region 23 (not implemented)"
hide.long 0x00 "HPRBAR23,Hypervisor Protection Region Base Address Register 23"
newline
hgroup.long c15:(0x5586+0x30)++0x00
hide.long 0x00 "HPRLAR23,Hypervisor Protection Region Limit Address Register 23"
endif
tree.end
tree.end
tree "Virtualization Extensions"
group.long c15:0x4000++0x00
line.long 0x00 "VPIDR,Virtualization Processor ID Register"
hexmask.long.byte 0x00 24.--31. 1. "IMPL,Implementer code"
bitfld.long 0x00 20.--23. "VAR,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 16.--19. "ARCH,Architecture" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CPUID scheme"
hexmask.long.word 0x00 4.--15. 1. "PART,Primary part number"
newline
bitfld.long 0x00 0.--3. "REV,Minor revision of the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long c15:0x4500++0x00
line.long 0x00 "VMPIDR,Virtualization Multiprocessor ID Register"
bitfld.long 0x00 30. "U,Single core system as distinct from core 0 in a cluster" "Part of a cluster,?..."
bitfld.long 0x00 24. "MT,Multi-threading type approach for logical cores in lowest level of affinity" "Largely independent,?..."
newline
hexmask.long.byte 0x00 16.--23. 1. "AFF2,Affinity level 2"
hexmask.long.byte 0x00 8.--15. 1. "AFF1,Affinity level 1"
hexmask.long.byte 0x00 0.--7. 1. "AFF0,Affinity level 0"
group.long c15:0x420D++0x00
line.long 0x00 "HTPIDR,Hypervisor Software Thread ID Register"
group.long c15:0x4001++0x00
line.long 0x00 "HSCTLR,Hypervisor System Control Register"
bitfld.long 0x00 30. "TE,Thumb exception enable" "A32,T32"
bitfld.long 0x00 25. "EE,Exception endianness" "Little,Big"
bitfld.long 0x00 21. "FI,Fast interrupts configuration enable" "Disabled,Enabled"
newline
bitfld.long 0x00 19. "WXN,Write permission implies Execute Never (XN)" "Not forced,Forced"
bitfld.long 0x00 17. "BR,Background region enable" "Disabled,Enabled"
bitfld.long 0x00 12. "I,Instruction cache enable" "Disabled,Enabled"
newline
bitfld.long 0x00 8. "SED,SETEND instruction disable" "No,Yes"
bitfld.long 0x00 7. "ITD,IT instruction disable" "No,Yes"
bitfld.long 0x00 5. "CP15BEN,CP15* barrier operations enable" "Disabled,Enabled"
newline
bitfld.long 0x00 2. "C,Data cache enable" "Disabled,Enabled"
bitfld.long 0x00 1. "A,Alignment fault checking enable" "Disabled,Enabled"
bitfld.long 0x00 0. "M,EL2-controlled MPU enable" "Disabled,Enabled"
group.long c15:0x4002++0x00
line.long 0x00 "VSCTLR,Virtualization System Control Register"
hexmask.long.byte 0x00 16.--23. 1. "VMID,Virtual machine ID"
bitfld.long 0x00 2. "S2NIE,Stage-2 normal interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 1. "S2DMAD,Stage-2 device multiple access disable" "Disabled,Enabled"
group.long c15:0x4101++0x00
line.long 0x00 "HACTLR,Hypervisor Auxiliary Control Register"
bitfld.long 0x00 15. "TESTR1,Controls access to TESTR1 at EL0 and EL1" "Trapped,Enabled"
bitfld.long 0x00 13. "ERR,Controls access to IMP_DCERR0, IMP_DCERR1, IMP_ICERR0, IMP_ICERR1, IMP_TCMERR0, IMP_TCMERR1, IMP_FLASHERR0 and IMP_FLASHERR1 registers" "Trapped,Enabled"
bitfld.long 0x00 12. "INTMONR,Controls access to IMP_INTMONR at EL1" "Trapped,Enabled"
newline
bitfld.long 0x00 10. "BUSTIMEOUTR,Controls access to IMP_BUSTIMEOUTR at EL1" "Trapped,Enabled"
bitfld.long 0x00 9. "QOSR,Controls access to QOSR at EL1" "Trapped,Enabled"
bitfld.long 0x00 8. "PERIPHPREGIONR,Controls access to IMP_PERIPHPREGIONR at EL1" "Trapped,Enabled"
newline
bitfld.long 0x00 7. "FLASHIFREGIONR,Controls access to IMP_FLASHIFREGIONR at EL1" "Trapped,Enabled"
bitfld.long 0x00 1. "CDBGDCI,Controls access to CDBGDCI at EL1" "Trapped,Enabled"
bitfld.long 0x00 0. "CPUACTLR,IMP_CPUACTLR write access control" "Trapped,Enabled"
rgroup.long c15:0x4711++0x00
line.long 0x00 "HACR,Hypervisor Auxiliary Configuration Register"
group.long c15:0x4011++0x00
line.long 0x00 "HCR,Hypervisor Configuration Register"
bitfld.long 0x00 30. "TRVM,Trap read of virtual memory controls" "Disabled,Enabled"
bitfld.long 0x00 29. "HCD,HVC instruction disable" "No,Yes"
bitfld.long 0x00 27. "TGE,Trap general exceptions" "Disabled,Enabled"
newline
bitfld.long 0x00 26. "TVM,Trap virtual memory controls" "Disabled,Enabled"
bitfld.long 0x00 24. "TPU,Trap cache maintenance instructions that operate to the point of unification" "Disabled,Enabled"
bitfld.long 0x00 23. "TPC,Trap Data Cache maintenance operations that operate to the point of coherency" "Disabled,Enabled"
newline
bitfld.long 0x00 22. "TSW,Trap data/unified cache maintenance instructions by set/way" "Disabled,Enabled"
bitfld.long 0x00 21. "TAC,Trap ACTLR accesses" "Disabled,Enabled"
bitfld.long 0x00 20. "TIDCP,Trap lockdown" "Disabled,Enabled"
newline
bitfld.long 0x00 18. "TID3,Trap ID Group 3" "Disabled,Enabled"
bitfld.long 0x00 17. "TID2,Trap ID Group 2" "Disabled,Enabled"
bitfld.long 0x00 16. "TID1,Trap ID Group 1" "Disabled,Enabled"
newline
bitfld.long 0x00 15. "TID0,Trap ID Group 0" "Disabled,Enabled"
bitfld.long 0x00 14. "TWE,Trap WFE" "Disabled,Enabled"
bitfld.long 0x00 13. "TWI,Trap WFI" "Disabled,Enabled"
newline
bitfld.long 0x00 12. "DC,Default cacheable" "Disabled,Enabled"
bitfld.long 0x00 10.--11. "BSU,Barrier shareability upgrade" "No effect,Inner shareable,Outer shareable,Full system"
bitfld.long 0x00 9. "FB,Force broadcast" "Not forced,Forced"
newline
bitfld.long 0x00 8. "VA,Virtual asynchronous abort exception" "Not pending,Pending"
bitfld.long 0x00 7. "VI,Virtual IRQ exception" "Not pending,Pending"
bitfld.long 0x00 6. "VF,Virtual FIQ exception" "Not pending,Pending"
newline
bitfld.long 0x00 5. "AMO,A-bit mask override" "Disabled,Enabled"
bitfld.long 0x00 4. "IMO,I-bit mask override" "Disabled,Enabled"
bitfld.long 0x00 3. "FMO,F-bit mask override" "Disabled,Enabled"
newline
bitfld.long 0x00 1. "SWIO,Set/Way Invalidation Override" "No override,Override"
bitfld.long 0x00 0. "VM,Second stage of translation enable" "Disabled,Enabled"
rgroup.long c15:0x4411++0x00
line.long 0x00 "HCR2,Hypervisor Configuration Register 2"
group.long c15:0x3054++0x00
line.long 0x00 "DSPSR,Debug Saved Program Status Register"
bitfld.long 0x00 31. "N,Negative condition flag" "Not negative,Negative"
bitfld.long 0x00 30. "Z,Zero condition flag" "Not zero,Zero"
bitfld.long 0x00 29. "C,Carry condition flag" "Not carry,Carry"
newline
bitfld.long 0x00 28. "V,Overflow condition flag" "No overflow,Overflow"
bitfld.long 0x00 27. "Q,Cumulative condition flag" "Not occurred,Occurred"
bitfld.long 0x00 21. "SS,Software step" "0,1"
newline
bitfld.long 0x00 20. "IL,Illegal execution state" "0,1"
bitfld.long 0x00 14.--15. 25.--26. "IT[4:7],IT block state bits for the T32 IT (if-then) instruction - base condition for the IT block" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 10.--13. "IT[0:3],IT block state bits for the T32 IT (if-then) instruction - size of the IT block" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 16.--19. "GE,Greater than or equal flags" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 9. "E,Endianness state bit" "Little,Big"
bitfld.long 0x00 8. "A,Asynchronous data abort mask bit" "Not masked,Masked"
newline
bitfld.long 0x00 7. "I,IRQ mask bit" "Not masked,Masked"
bitfld.long 0x00 6. "F,FIQ mask bit" "Not masked,Masked"
bitfld.long 0x00 5. "T,T32 Instruction set state" "A32,T32"
newline
bitfld.long 0x00 4. "M[4],Execution state that the exception was taken from" "Reserved,AArch32"
bitfld.long 0x00 0.--3. "M[3:0],Current PE mode" "User,FIQ,IRQ,Supervisor,Reserved,Reserved,Monitor,Abort,Reserved,Reserved,Hyp,Undefined,Reserved,Reserved,Reserved,System"
group.long c15:0x4111++0x00
line.long 0x00 "HDCR,Hypervisor Debug Control Register"
bitfld.long 0x00 21. "EPMAD,External debugger access to hypervisor performance monitors registers disabled" "No,Yes"
bitfld.long 0x00 17. "HPMD,Hypervisor performance monitors disable" "No,Yes"
bitfld.long 0x00 11. "TDRA,Trap debug ROM access" "No effect,Valid"
newline
bitfld.long 0x00 10. "TDOSA,Trap debug OS-related register access" "No effect,Valid"
bitfld.long 0x00 9. "TDA,Trap debug access" "No effect,Valid"
bitfld.long 0x00 8. "TDE,Trap debug exceptions" "No effect,Valid"
newline
bitfld.long 0x00 7. "HPME,Hypervisor performance monitors enable" "Disabled,Enabled"
bitfld.long 0x00 6. "TPM,Trap performance monitors accesses" "No effect,Valid"
bitfld.long 0x00 5. "TPMCR,Trap performance monitor control register accesses" "No effect,Valid"
newline
bitfld.long 0x00 0.--4. "HPMN,Defines the number of performance monitors counters" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long c15:0x4211++0x00
line.long 0x00 "HCPTR,Hypervisor Architectural Feature Trap Register"
bitfld.long 0x00 31. "TCPAC,Trap coprocessor access control" "Not trapped,Trapped"
bitfld.long 0x00 15. "TASE,Trap advanced SIMD extensions" "Not trapped,Trapped"
newline
bitfld.long 0x00 11. "TCP11,Trap coprocessor 11" "Not trapped,Trapped"
bitfld.long 0x00 10. "TCP10,Trap coprocessor 10" "Not trapped,Trapped"
group.long c15:0x4311++0x00
line.long 0x00 "HSTR,Hypervisor System Trap Register"
bitfld.long 0x00 15. "T15,Trap to Hypervisor mode Non-secure priv 15" "No effect,Trap"
bitfld.long 0x00 13. "T13,Trap to Hypervisor mode Non-secure priv 13" "No effect,Trap"
bitfld.long 0x00 12. "T12,Trap to Hypervisor mode Non-secure priv 12" "No effect,Trap"
newline
bitfld.long 0x00 11. "T11,Trap to Hypervisor mode Non-secure priv 11" "No effect,Trap"
bitfld.long 0x00 10. "T10,Trap to Hypervisor mode Non-secure priv 10" "No effect,Trap"
bitfld.long 0x00 9. "T9,Trap to Hypervisor mode Non-secure priv 9" "No effect,Trap"
newline
bitfld.long 0x00 8. "T8,Trap to Hypervisor mode Non-secure priv 8" "No effect,Trap"
bitfld.long 0x00 7. "T7,Trap to Hypervisor mode Non-secure priv 7" "No effect,Trap"
bitfld.long 0x00 6. "T6,Trap to Hypervisor mode Non-secure priv 6" "No effect,Trap"
newline
bitfld.long 0x00 5. "T5,Trap to Hypervisor mode Non-secure priv 5" "No effect,Trap"
bitfld.long 0x00 3. "T3,Trap to Hypervisor mode Non-secure priv 3" "No effect,Trap"
bitfld.long 0x00 2. "T2,Trap to Hypervisor mode Non-secure priv 2" "No effect,Trap"
newline
bitfld.long 0x00 1. "T1,Trap to Hypervisor mode Non-secure priv 1" "No effect,Trap"
bitfld.long 0x00 0. "T0,Trap to Hypervisor mode Non-secure priv 0" "No effect,Trap"
rgroup.long c15:0x4301++0x00
line.long 0x00 "HACTLR2,Hypervisor Auxiliary Control Register 2"
group.long c15:0x3154++0x00
line.long 0x00 "DLR,Debug Link Register"
group.long c15:0x4015++0x00
line.long 0x00 "HADFSR,Hypervisor Auxiliary Data Fault Status Syndrome Register"
bitfld.long 0x00 2.--4. "PORT,Memory or port that caused the fault" "AXIM,Flash interface,LLPP,Internal interface,ATCM,BTCM,CTCM,?..."
bitfld.long 0x00 0.--1. "TYPE,Fault type" "Undefined,Response,ECC on data,Bus timeout"
group.long c15:0x4006++0x00
line.long 0x00 "HDFAR,Hypervisor Data Fault Address Register"
if (((per.l(c15:0x4025))&0xFC000000)==(0x00000000||0x38000000||0x88000000))
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hypervisor Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/MRC,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC executed,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Prefetch abort routed to hyp,Prefetch abort taken from hyp,PC alignment fault,Reserved,Data abort routed to hyp,Data abort taken from hyp,?..."
elif (((per.l(c15:0x4025))&0xFC000000)==0x04000000)
if (((per.l(c15:0x4025))&0x01000000)==0x01000000)
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hypervisor Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/MRC,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC executed,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Prefetch abort routed to hyp,Prefetch abort taken from hyp,PC alignment fault,Reserved,Data abort routed to hyp,Data abort taken from hyp,?..."
bitfld.long 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 0. "TI,Trapped instruction" "WFI,WFE"
else
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hypervisor Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/MRC,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC executed,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Prefetch abort routed to hyp,Prefetch abort taken from hyp,PC alignment fault,Reserved,Data abort routed to hyp,Data abort taken from hyp,?..."
bitfld.long 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
newline
bitfld.long 0x00 0. "TI,Trapped instruction" "WFI,WFE"
endif
elif (((per.l(c15:0x4025))&0xFC000000)==(0x0C000000||0x14000000||0x20000000))
if (((per.l(c15:0x4025))&0x01000000)==0x01000000)
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hypervisor Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/MRC,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC executed,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Prefetch abort routed to hyp,Prefetch abort taken from hyp,PC alignment fault,Reserved,Data abort routed to hyp,Data abort taken from hyp,?..."
bitfld.long 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 17.--19. "OPC2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 14.--16. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 5.--8. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
else
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hypervisor Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/MRC,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC executed,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Prefetch abort routed to hyp,Prefetch abort taken from hyp,PC alignment fault,Reserved,Data abort routed to hyp,Data abort taken from hyp,?..."
bitfld.long 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
newline
bitfld.long 0x00 17.--19. "OPC2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 14.--16. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 5.--8. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
endif
elif (((per.l(c15:0x4025))&0xFC000000)==(0x10000000||0x30000000))
if (((per.l(c15:0x4025))&0x01000000)==0x01000000)
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hypervisor Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/MRC,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC executed,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Prefetch abort routed to hyp,Prefetch abort taken from hyp,PC alignment fault,Reserved,Data abort routed to hyp,Data abort taken from hyp,?..."
bitfld.long 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 16.--19. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 10.--13. "RT2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 5.--8. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
else
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hypervisor Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/MRC,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC executed,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Prefetch abort routed to hyp,Prefetch abort taken from hyp,PC alignment fault,Reserved,Data abort routed to hyp,Data abort taken from hyp,?..."
bitfld.long 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
newline
bitfld.long 0x00 16.--19. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 10.--13. "RT2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 5.--8. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
endif
elif (((per.l(c15:0x4025))&0xFC000000)==0x18000000)
if (((per.l(c15:0x4025))&0x01000000)==0x01000000)
if (((per.l(c15:0x4025))&0x08)==0x00)
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hypervisor Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/MRC,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC executed,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Prefetch abort routed to hyp,Prefetch abort taken from hyp,PC alignment fault,Reserved,Data abort routed to hyp,Data abort taken from hyp,?..."
bitfld.long 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
hexmask.long.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction"
bitfld.long 0x00 5.--8. "RN,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
bitfld.long 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,?..."
newline
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
else
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hypervisor Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/MRC,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC executed,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Prefetch abort routed to hyp,Prefetch abort taken from hyp,PC alignment fault,Reserved,Data abort routed to hyp,Data abort taken from hyp,?..."
bitfld.long 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
hexmask.long.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction"
newline
bitfld.long 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
bitfld.long 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,?..."
newline
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
endif
else
if (((per.l(c15:0x4025))&0x08)==0x00)
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hypervisor Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/MRC,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC executed,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Prefetch abort routed to hyp,Prefetch abort taken from hyp,PC alignment fault,Reserved,Data abort routed to hyp,Data abort taken from hyp,?..."
bitfld.long 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
newline
hexmask.long.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction"
bitfld.long 0x00 5.--8. "RN,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
bitfld.long 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved"
newline
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
else
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hypervisor Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/MRC,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC executed,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Prefetch abort routed to hyp,Prefetch abort taken from hyp,PC alignment fault,Reserved,Data abort routed to hyp,Data abort taken from hyp,?..."
bitfld.long 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
newline
hexmask.long.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction"
newline
bitfld.long 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
bitfld.long 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved"
newline
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
endif
endif
elif (((per.l(c15:0x4025))&0xFC000000)==0x1C000000)
if (((per.l(c15:0x4025))&0x01000000)==0x01000000)
if (((per.l(c15:0x4025))&0x20)==0x20)
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hypervisor Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/MRC,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC executed,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Prefetch abort routed to hyp,Prefetch abort taken from hyp,PC alignment fault,Reserved,Data abort routed to hyp,Data abort taken from hyp,?..."
bitfld.long 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 5. "TA,Indicates trapped use of advanced SIMD functionality" "Not trapped,Trapped"
bitfld.long 0x00 0.--3. "COPROC,COPROC" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,0b1010,?..."
else
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hypervisor Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/MRC,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC executed,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Prefetch abort routed to hyp,Prefetch abort taken from hyp,PC alignment fault,Reserved,Data abort routed to hyp,Data abort taken from hyp,?..."
bitfld.long 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 5. "TA,Indicates trapped use of advanced SIMD functionality" "Not trapped,Trapped"
endif
else
if (((per.l(c15:0x4025))&0x20)==0x20)
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hypervisor Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/MRC,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC executed,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Prefetch abort routed to hyp,Prefetch abort taken from hyp,PC alignment fault,Reserved,Data abort routed to hyp,Data abort taken from hyp,?..."
bitfld.long 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
newline
bitfld.long 0x00 5. "TA,Indicates trapped use of advanced SIMD functionality" "Not trapped,Trapped"
bitfld.long 0x00 0.--3. "COPROC,COPROC" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,0b1010,?..."
else
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hypervisor Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/MRC,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC executed,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Prefetch abort routed to hyp,Prefetch abort taken from hyp,PC alignment fault,Reserved,Data abort routed to hyp,Data abort taken from hyp,?..."
bitfld.long 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
newline
bitfld.long 0x00 5. "TA,Indicates trapped use of advanced SIMD functionality" "Not trapped,Trapped"
endif
endif
elif (((per.l(c15:0x4025))&0xFC000000)==(0x44000000||0x48000000))
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hypervisor Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/MRC,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC executed,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Prefetch abort routed to hyp,Prefetch abort taken from hyp,PC alignment fault,Reserved,Data abort routed to hyp,Data abort taken from hyp,?..."
bitfld.long 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.long.word 0x00 0.--15. 1. "IMM16,The value of the immediate field from the HVC or SVC instruction"
elif (((per.l(c15:0x4025))&0xFC000000)==(0x80000000||0x84000000))
if (((per.l(c15:0x4025))&0x3F)==0x10)
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hypervisor Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/MRC,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC executed,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Prefetch abort routed to hyp,Prefetch abort taken from hyp,PC alignment fault,Reserved,Data abort routed to hyp,Data abort taken from hyp,?..."
bitfld.long 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 10. "FNV,FAR not valid" "No,Yes"
newline
bitfld.long 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.long 0x00 0.--5. "IFSC,Instruction fault status code" "Reserved,Reserved,Reserved,Reserved,Translation fault,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Permission fault,Reserved,Reserved,Reserved,Synch. external abort,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Synch. parity/ECC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Debug,?..."
else
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hypervisor Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/MRC,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC executed,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Prefetch abort routed to hyp,Prefetch abort taken from hyp,PC alignment fault,Reserved,Data abort routed to hyp,Data abort taken from hyp,?..."
bitfld.long 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
newline
bitfld.long 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.long 0x00 0.--5. "IFSC,Instruction fault status code" "Reserved,Reserved,Reserved,Reserved,Translation fault,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Permission fault,Reserved,Reserved,Reserved,Synch. external abort,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Synch. parity/ECC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Debug,?..."
endif
elif (((per.l(c15:0x4025))&0xFD00003F)==(0x95000010||0x91000010))
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hypervisor Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/MRC,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC executed,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Prefetch abort routed to hyp,Prefetch abort taken from hyp,PC alignment fault,Reserved,Data abort routed to hyp,Data abort taken from hyp,?..."
bitfld.long 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
newline
bitfld.long 0x00 22.--23. "SAS,Syndrome access size" "Byte,Halfword,Word,Doubleword"
bitfld.long 0x00 21. "SSE,Syndrome sign extend" "Not required,Required"
bitfld.long 0x00 16.--19. "SRT,Syndrome register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14. "AR,Acquire/Release" "No,Yes"
newline
bitfld.long 0x00 10. "FNV,FAR not valid" "No,Yes"
newline
bitfld.long 0x00 9. "EA,External abort type" "DECERR,SLVERR"
bitfld.long 0x00 8. "CM,Fault came from a cache maintenance instruction other than DC ZVA" "No,Yes"
bitfld.long 0x00 6. "WNR,Write not read" "Read,Write"
newline
bitfld.long 0x00 0.--5. "DFSC,Data fault status code" "Reserved,Reserved,Reserved,Reserved,Translation fault,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Permission fault,Reserved,Reserved,Reserved,Synch. external abort,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Synch. parity/ECC,SError/parity/ECC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment fault,Debug,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Cache lockdown fault,Unsupported Exclusive access,?..."
elif (((per.l(c15:0x4025))&0xFD000000)==(0x95000000||0x91000000))
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hypervisor Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/MRC,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC executed,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Prefetch abort routed to hyp,Prefetch abort taken from hyp,PC alignment fault,Reserved,Data abort routed to hyp,Data abort taken from hyp,?..."
bitfld.long 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
newline
bitfld.long 0x00 22.--23. "SAS,Syndrome access size" "Byte,Halfword,Word,Doubleword"
bitfld.long 0x00 21. "SSE,Syndrome sign extend" "Not required,Required"
bitfld.long 0x00 16.--19. "SRT,Syndrome register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14. "AR,Acquire/Release" "No,Yes"
newline
newline
bitfld.long 0x00 9. "EA,External abort type" "DECERR,SLVERR"
bitfld.long 0x00 8. "CM,Fault came from a cache maintenance instruction other than DC ZVA" "No,Yes"
bitfld.long 0x00 6. "WNR,Write not read" "Read,Write"
newline
bitfld.long 0x00 0.--5. "DFSC,Data fault status code" "Reserved,Reserved,Reserved,Reserved,Translation fault,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Permission fault,Reserved,Reserved,Reserved,Synch. external abort,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Synch. parity/ECC,SError/parity/ECC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment fault,Debug,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Cache lockdown fault,Unsupported Exclusive access,?..."
elif (((per.l(c15:0x4025))&0xFD00003F)==(0x90000010||0x94000010))
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hypervisor Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/MRC,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC executed,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Prefetch abort routed to hyp,Prefetch abort taken from hyp,PC alignment fault,Reserved,Data abort routed to hyp,Data abort taken from hyp,?..."
bitfld.long 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
newline
newline
newline
bitfld.long 0x00 10. "FNV,FAR not valid" "No,Yes"
newline
bitfld.long 0x00 9. "EA,External abort type" "DECERR,SLVERR"
bitfld.long 0x00 8. "CM,Fault came from a cache maintenance instruction other than DC ZVA" "No,Yes"
bitfld.long 0x00 6. "WNR,Write not read" "Read,Write"
newline
bitfld.long 0x00 0.--5. "DFSC,Data fault status code" "Reserved,Reserved,Reserved,Reserved,Translation fault,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Permission fault,Reserved,Reserved,Reserved,Synch. external abort,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Synch. parity/ECC,SError/parity/ECC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment fault,Debug,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Cache lockdown fault,Unsupported Exclusive access,?..."
elif (((per.l(c15:0x4025))&0xFD000000)==(0x90000000||0x94000000))
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hypervisor Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/MRC,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC executed,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Prefetch abort routed to hyp,Prefetch abort taken from hyp,PC alignment fault,Reserved,Data abort routed to hyp,Data abort taken from hyp,?..."
bitfld.long 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
newline
newline
newline
newline
bitfld.long 0x00 9. "EA,External abort type" "DECERR,SLVERR"
bitfld.long 0x00 8. "CM,Fault came from a cache maintenance instruction other than DC ZVA" "No,Yes"
bitfld.long 0x00 6. "WNR,Write not read" "Read,Write"
newline
bitfld.long 0x00 0.--5. "DFSC,Data fault status code" "Reserved,Reserved,Reserved,Reserved,Translation fault,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Permission fault,Reserved,Reserved,Reserved,Synch. external abort,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Synch. parity/ECC,SError/parity/ECC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment fault,Debug,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Cache lockdown fault,Unsupported Exclusive access,?..."
else
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hypervisor Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/MRC,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC executed,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Prefetch abort routed to hyp,Prefetch abort taken from hyp,PC alignment fault,Reserved,Data abort routed to hyp,Data abort taken from hyp,?..."
bitfld.long 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
endif
group.long c15:0x4115++0x00
line.long 0x00 "HAIFSR,Hypervisor Auxiliary Instruction Fault Status Register"
bitfld.long 0x00 2.--4. "PORT,Memory or port that caused the fault" "AXIM,Flash interface,LLPP,Reserved,ATCM,BTCM,CTCM,UNKNOWN"
bitfld.long 0x00 0.--1. "TYPE,Fault type" "Undefined,Response,ECC on data,Bus timeout"
group.long c15:0x4206++0x00
line.long 0x00 "HIFAR,Hypervisor Instruction Fault Address Register"
group.long c15:0x4406++0x00
line.long 0x00 "HPFAR,Hypervisor IPA Fault Address Register"
hexmask.long 0x00 4.--31. 1. "FIPA,Faulting IPA bits"
tree.open "Hypervisor Memory Attribute Indirection Registers"
group.long c15:0x402A++0x00
line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0"
bitfld.long 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
group.long c15:0x412A++0x00
line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1"
bitfld.long 0x00 28.--31. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 20.--23. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 12.--15. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 4.--7. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
rgroup.long c15:0x403A++0x00
line.long 0x00 "HAMAIR0,Hypervisor Auxiliary Memory Attribute Indirection Register 0"
rgroup.long c15:0x413A++0x00
line.long 0x00 "HAMAIR1,Hypervisor Auxiliary Memory Attribute Indirection Register 1"
tree.end
newline
group.long c15:0x400C++0x00
line.long 0x00 "HVBAR,Hypervisor Vector Base Address Register"
hexmask.long 0x00 5.--31. 0x20 "VBA,Vector base address"
group.long c15:0x420C++0x00
line.long 0x00 "HRMR,Hypervisor Reset Management Register"
bitfld.long 0x00 1. "RR,Reset request" "Not requested,Requested"
group.long c15:0x1119++0x00
line.long 0x00 "IMP_BPCTLR,Branch Predictor Control Register"
bitfld.long 0x00 2. "DBPEL2DIS,Disable dynamic branch predictor when running at EL2" "No,Yes"
bitfld.long 0x00 1. "DBPEL1DIS,Disable dynamic branch predictor when running at EL1" "No,Yes"
bitfld.long 0x00 0. "DBPEL0DIS,Disable dynamic branch predictor when running at EL0" "No,Yes"
tree.end
tree "Cache Control and Configuration"
rgroup.long c15:0x0100++0x00
line.long 0x00 "CTR,Cache Type Register"
bitfld.long 0x00 24.--27. "CWG,Cache write-back granule" "Reserved,2 words,?..."
bitfld.long 0x00 20.--23. "ERG,Exclusives reservation granule" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
newline
bitfld.long 0x00 16.--19. "DMINLINE,D-cache minimum line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
bitfld.long 0x00 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,Reserved,PIPT"
bitfld.long 0x00 0.--3. "IMINLINE,I-cache minimum line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
group.long c15:0x2000++0x00
line.long 0x00 "CSSELR,Cache Size Selection Register"
rbitfld.long 0x00 1.--3. "LEVEL,Cache level of required cache" "Level 1,?..."
bitfld.long 0x00 0. "IND,Instruction/not data" "Data/unified,Instruction"
rgroup.long c15:0x1000++0x00
line.long 0x00 "CCSIDR,Current Cache Size ID Register"
bitfld.long 0x00 31. "WT,Write-through" "Not supported,Supported"
bitfld.long 0x00 30. "WB,Write-back" "Not supported,?..."
newline
bitfld.long 0x00 29. "RA,Read-allocate" "Reserved,Supported"
bitfld.long 0x00 28. "WA,Write-allocate" "Not supported,Supported"
newline
hexmask.long.word 0x00 13.--27. 1. 1. "SETS,Number of sets"
hexmask.long.word 0x00 3.--12. 1. 1. "ASSOC,Associativity"
newline
bitfld.long 0x00 0.--2. "LSIZE,Number of words in each cache line" "Reserved,Reserved,16,?..."
rgroup.long c15:0x1100++0x00
line.long 0x00 "CLIDR,Cache Level ID Register"
bitfld.long 0x00 30.--31. "ICB,Inner cache boundary" "Not disclosed,?..."
bitfld.long 0x00 27.--29. "LOUU,Level of unification" "Level 0,Level 1,?..."
bitfld.long 0x00 24.--26. "LOC,Level of coherency" "Level 0,Level 1,?..."
newline
bitfld.long 0x00 21.--23. "LOUIS,Level of unification inner shareable" "Level 0,Level 1,?..."
bitfld.long 0x00 18.--20. "CTYPE7,Cache type for levels 7" "No cache,?..."
newline
bitfld.long 0x00 15.--17. "CTYPE6,Cache type for levels 6" "No cache,?..."
bitfld.long 0x00 12.--14. "CTYPE5,Cache type for levels 5" "No cache,?..."
newline
bitfld.long 0x00 9.--11. "CTYPE4,Cache type for levels 4" "No cache,?..."
bitfld.long 0x00 6.--8. "CTYPE3,Cache type for levels 3" "No cache,?..."
newline
bitfld.long 0x00 3.--5. "CTYPE2,Cache type for levels 2" "No cache,?..."
bitfld.long 0x00 0.--2. "CTYPE1,Cache type for levels 1" "No cache,Instruction cache,Data cache,Both separated,?..."
group.long c15:0x1019++0x00
line.long 0x00 "IMP_CSCTLR,Cache Segregation Control Register"
bitfld.long 0x00 8.--10. "IFLW,Instruction cache flash ways" "Reserved,0,0-1,0-2,0-3,?..."
bitfld.long 0x00 0.--2. "DFLW,Data cache flash ways" "Reserved,0,0-1,0-2,0-3,?..."
group.quad c15:0x100F0++0x01
line.quad 0x00 "CPUACTLR,CPU Auxiliary Control Register"
bitfld.quad 0x00 47. "FIXEDDIV,Enable fixed latency for integer divide instructions" "Disabled,Enabled"
bitfld.quad 0x00 46. "ETACDIS,Disable PFU exception target address cache" "No,Yes"
bitfld.quad 0x00 45. "OOODIVDIS,Disable out-of-order completion of divide instructions" "No,Yes"
newline
bitfld.quad 0x00 41. "TLACDIS,Disable the store unit (STU) tag lookup avoidance cache" "No,Yes"
bitfld.quad 0x00 40. "FLASHNDDIS,Disable flash accesses use of non-flash-dedicated resources" "No,Yes"
bitfld.quad 0x00 39. "FLASHARBCTL,Flash interface arbitration control" "D-side,I-side"
newline
bitfld.quad 0x00 38. "AXIMARBCTL,AXIM interface arbitration control" "D-side,I-side"
bitfld.quad 0x00 33. "ISPECDIS,Disable I-side speculative access" "No,Yes"
bitfld.quad 0x00 32. "DSPECDIS,Disable D-side speculative access" "No,Yes"
newline
bitfld.quad 0x00 30. "FPDIDIS,Disable floating-point dual issue" "No,Yes"
bitfld.quad 0x00 29. "DIDIS,Disable Dual Issue" "No,Yes"
bitfld.quad 0x00 25.--26. "WSTRNOL1ACTL,Write streaming no-L1-allocate threshold" "4th,64th,128th,Disabled streaming"
newline
bitfld.quad 0x00 19.--20. "DPFSTRCTL,Number of independent data prefetch streams" "1,2,3,4"
bitfld.quad 0x00 17. "STRIDECTL,Enable stride detection" "2,3"
bitfld.quad 0x00 13.--15. "L1DPFCTL,L1 Data prefetch control" "Disabled,1 outstanding prefetch,2 outstanding prefetch,3 outstanding prefetch,4 outstanding prefetch,5 outstanding prefetch,6 outstanding prefetch,8 outstanding prefetch"
newline
bitfld.quad 0x00 11. "L1IPFCTL,L1 Instruction prefetch control" "Disabled,Enabled"
bitfld.quad 0x00 10. "DMB2DSBEN,Enable data memory barrier behaving as data synchronization barrier" "Disabled,Enabled"
wgroup.long c15:0x10EF++0x00
line.long 0x00 "IMP_CDBGDCI,Invalidate All Register"
tree "Level 1 memory system"
rgroup.long c15:0x300F++0x00
line.long 0x00 "IMP_CDBGDR0,Cache Debug Data Register 0"
bitfld.long 0x00 22. "V,Valid" "0,1"
hexmask.long.tbyte 0x00 0.--21. 1. "TB,Tag bits"
rgroup.long c15:0x310F++0x00
line.long 0x00 "IMP_CDBGDR1,Cache Debug Data Register 1"
wgroup.long c15:0x302F++0x00
line.long 0x00 "IMP_CDBGDCT,Data Cache Tag Read Operation Register"
bitfld.long 0x00 30.--31. "CW,Cache way" "0,1,2,3"
hexmask.long.word 0x00 6.--12. 1. "SETIND,Set index"
wgroup.long c15:0x312F++0x00
line.long 0x00 "IMP_CDBGICT,Instruction Cache Tag Read Operation Register"
bitfld.long 0x00 30.--31. "CW,Cache way" "0,1,2,3"
hexmask.long.word 0x00 6.--12. 1. "SETIND,Set index"
wgroup.long c15:0x304F++0x00
line.long 0x00 "IMP_CDBGDCD,Data Cache Data Read Operation Register"
bitfld.long 0x00 30.--31. "CW,Cache way" "0,1,2,3"
hexmask.long.word 0x00 6.--12. 1. "SETIND,Set index"
bitfld.long 0x00 3.--5. "DO,Data offset" "0,1,2,3,4,5,6,7"
wgroup.long c15:0x314F++0x00
line.long 0x00 "IMP_CDBGICD,Instruction Cache Data Read Operation Register"
bitfld.long 0x00 30.--31. "CW,Cache way" "0,1,2,3"
hexmask.long.word 0x00 6.--12. 1. "SETIND,Set index"
bitfld.long 0x00 3.--5. "DO,Data offset" "0,1,2,3,4,5,6,7"
tree.end
tree.end
tree "System Performance Monitor"
group.long c15:0x00C9++0x00
line.long 0x00 "PMCR,Performance Monitors Control Register"
hexmask.long.byte 0x00 24.--31. 1. "IMP,Implementer code"
hexmask.long.byte 0x00 16.--23. 1. "IDCODE,Identification code"
rbitfld.long 0x00 11.--15. "N,Number of counters implemented" "Reserved,Reserved,Reserved,Reserved,4,?..."
bitfld.long 0x00 6. "LC,Long cycle counter enable" "Disabled,Enabled"
newline
bitfld.long 0x00 5. "DP,Disable CCNT when prohibited" "No,Yes"
bitfld.long 0x00 4. "X,Export enable" "Disabled,Enabled"
bitfld.long 0x00 3. "D,Clock divider" "Every cycle,64th cycle"
bitfld.long 0x00 2. "C,Clock counter reset" "No reset,Reset"
newline
bitfld.long 0x00 1. "P,Performance counter reset" "No reset,Reset"
bitfld.long 0x00 0. "E,All counters enable" "Disabled,Enabled"
group.long c15:0x01C9++0x00
line.long 0x00 "PMCNTENSET,Count Enable Set Register"
bitfld.long 0x00 31. "C,CCNT overflow interrupt enable" "Disabled,Enabled"
newline
bitfld.long 0x00 3. "P3,Event counter PMN 3 enable bit" "Disabled,Enabled"
bitfld.long 0x00 2. "P2,Event counter PMN 2 enable bit" "Disabled,Enabled"
bitfld.long 0x00 1. "P1,Event counter PMN 1 enable bit" "Disabled,Enabled"
bitfld.long 0x00 0. "P0,Event counter PMN 0 enable bit" "Disabled,Enabled"
group.long c15:0x02C9++0x00
line.long 0x00 "PMCNTENCLR,Count Enable Clear Register"
bitfld.long 0x00 31. "C,CCNT overflow interrupt enable" "Disabled,Enabled"
newline
bitfld.long 0x00 3. "P3,Event counter PMN 3 enable bit" "Disabled,Enabled"
bitfld.long 0x00 2. "P2,Event counter PMN 2 enable bit" "Disabled,Enabled"
bitfld.long 0x00 1. "P1,Event counter PMN 1 enable bit" "Disabled,Enabled"
bitfld.long 0x00 0. "P0,Event counter PMN 0 enable bit" "Disabled,Enabled"
group.long c15:0x03C9++0x00
line.long 0x00 "PMOVSR,Overflow Status Flags Register"
eventfld.long 0x00 31. "C,PMCCNTR overflow" "No overflow,Overflow"
newline
eventfld.long 0x00 3. "P3,PMN3 overflow" "No overflow,Overflow"
eventfld.long 0x00 2. "P2,PMN2 overflow" "No overflow,Overflow"
eventfld.long 0x00 1. "P1,PMN1 overflow" "No overflow,Overflow"
eventfld.long 0x00 0. "P0,PMN0 overflow" "No overflow,Overflow"
wgroup.long c15:0x04C9++0x00
line.long 0x00 "PMSWINC,Software Increment Register"
bitfld.long 0x00 3. "P3,PMN3 software increment" "No effect,Increment"
bitfld.long 0x00 2. "P2,PMN2 software increment" "No effect,Increment"
bitfld.long 0x00 1. "P1,PMN1 software increment" "No effect,Increment"
bitfld.long 0x00 0. "P0,PMN0 software increment" "No effect,Increment"
group.long c15:0x05C9++0x00
line.long 0x00 "PMSELR,Event Counter Selection Register"
bitfld.long 0x00 0.--4. "SEL,Current event counter select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.open "Common Event Identification Registers"
rgroup.long c15:0x06C9++0x00
line.long 0x00 "PMCEID0,Common Event Identification Register 0"
bitfld.long 0x00 30. "CHAIN,Chain" "Not implemented,Implemented"
bitfld.long 0x00 29. "BUS_CYCLES,Bus cycle" "Not implemented,Implemented"
bitfld.long 0x00 27. "INST_SPEC,Instruction speculatively executed" "Not implemented,Implemented"
bitfld.long 0x00 26. "MEMORY_ERROR,Local memory error" "Not implemented,Implemented"
newline
bitfld.long 0x00 25. "BUS_ACCESS,Bus access" "Not implemented,Implemented"
bitfld.long 0x00 20. "L1I_CACHE,Level 1 instruction cache access" "Not implemented,Implemented"
bitfld.long 0x00 19. "MEM_ACCESS,Data memory access" "Not implemented,Implemented"
bitfld.long 0x00 18. "BR_PRED,Predictable branch speculatively executed" "Not implemented,Implemented"
newline
bitfld.long 0x00 17. "CPU_CYCLES,CPU cycle" "Not implemented,Implemented"
bitfld.long 0x00 16. "BR_MIS_PRED,Mispredicted or not predicted branch speculatively executed" "Not implemented,Implemented"
bitfld.long 0x00 15. "UNALIGNED_LDST_RETIRED,Instruction architecturally executed condition code check pass unaligned load or store" "Not implemented,Implemented"
bitfld.long 0x00 14. "BR_RETURN_RETIRED,Instruction architecturally executed condition check pass procedure return" "Not implemented,Implemented"
newline
bitfld.long 0x00 13. "BR_IMMED_RETIRED,Instruction architecturally executed immediate branch" "Not implemented,Implemented"
bitfld.long 0x00 12. "PC_WRITE_RETIRED,Instruction architecturally executed condition check pass software change of the PC" "Not implemented,Implemented"
bitfld.long 0x00 11. "CID_WRITE_RETIRED,Instruction architecturally executed condition check pass write to CONTEXTIDR" "Not implemented,Implemented"
bitfld.long 0x00 10. "EXC_RETURN,Instruction architecturally executed condition check pass exception return" "Not implemented,Implemented"
newline
bitfld.long 0x00 9. "EXC_TAKEN,Exception taken" "Not implemented,Implemented"
bitfld.long 0x00 8. "INST_RETIRED,Instruction architecturally executed" "Not implemented,Implemented"
bitfld.long 0x00 7. "ST_RETIRED,Instruction architecturally executed condition check pass store" "Not implemented,Implemented"
bitfld.long 0x00 6. "LD_RETIRED,Instruction architecturally executed condition check pass load" "Not implemented,Implemented"
newline
bitfld.long 0x00 4. "L1D_CACHE,Level 1 data cache access" "Not implemented,Implemented"
bitfld.long 0x00 3. "L1D_CACHE_REFILL,Level 1 data cache refill" "Not implemented,Implemented"
bitfld.long 0x00 1. "L1I_CACHE_REFILL,Level 1 instruction cache refill" "Not implemented,Implemented"
bitfld.long 0x00 0. "SW_INCR,Software increment" "Not implemented,Implemented"
rgroup.long c15:0x07C9++0x00
line.long 0x00 "PMCEID1,Common Event Identification Register 1"
bitfld.long 0x00 19. "STALL_BACKEND,No operation issued due to backend" "Not implemented,Implemented"
bitfld.long 0x00 18. "STALL_FRONTEND,No operation issued due to the frontend" "Not implemented,Implemented"
bitfld.long 0x00 17. "BR_MIS_PRED_RETIRED,Instruction architecturally executed mispredicted branch" "Not implemented,Implemented"
bitfld.long 0x00 16. "BR_RETIRED,Instruction architecturally executed branch" "Not implemented,Implemented"
tree.end
newline
group.long c15:0x00D9++0x00
line.long 0x00 "PMCCNTR,Performance Monitor Cycle Count Register [31:0]"
group.quad c15:0x10090++0x01
line.quad 0x00 "PMCCNTR,Performance Monitor Cycle Count Register [63:0]"
if (((per.l(c15:0x05C9))&0x1F)==0x1F)
group.long c15:0x01D9++0x00
line.long 0x00 "PMXEVTYPER,Selected Event Type and Filter Register - PMCCFILTR"
bitfld.long 0x00 31. "P,Privileged modes filtering" "Disabled,Enabled"
bitfld.long 0x00 30. "U,User modes filtering" "Disabled,Enabled"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering" "Disabled,Enabled"
newline
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering" "Disabled,Enabled"
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering" "Disabled,Enabled"
elif (((per.l(c15:0x05C9))&0x1F)<=0x03)
group.long c15:0x01D9++0x00
line.long 0x00 "PMXEVTYPER,Selected Event Type and Filter Register - PMEVTYPER"
bitfld.long 0x00 31. "P,Privileged modes filtering" "Disabled,Enabled"
bitfld.long 0x00 30. "U,User modes filtering" "Disabled,Enabled"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering" "Disabled,Enabled"
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering" "Disabled,Enabled"
newline
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering" "Disabled,Enabled"
bitfld.long 0x00 25. "MT,Multithreading" "Disabled,Enabled"
hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event number"
else
rgroup.long c15:0x01D9++0x00
line.long 0x00 "PMXEVTYPER,Selected Event Type and Filter Register"
endif
group.long c15:0x02D9++0x00
line.long 0x00 "PMXEVCNTR,Selected Event Counter Register"
group.long c15:0x00E9++0x00
line.long 0x00 "PMUSERENR,User Enable Register"
bitfld.long 0x00 3. "ER,Event counter read enable" "Disabled,Enabled"
bitfld.long 0x00 2. "CR,Cycle counter read enable" "Disabled,Enabled"
newline
bitfld.long 0x00 1. "SW,Software Increment write enable" "Disabled,Enabled"
bitfld.long 0x00 0. "EN,User enable" "Disabled,Enabled"
group.long c15:0x01E9++0x00
line.long 0x00 "PMINTENSET,Interrupt Enable Set Register"
bitfld.long 0x00 31. "C,CCNT overflow interrupt enable" "Disabled,Enabled"
newline
bitfld.long 0x00 3. "P3,PMCNT3 overflow interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 2. "P2,PMCNT2 overflow interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 1. "P1,PMCNT1 overflow interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 0. "P0,PMCNT0 overflow interrupt enable" "Disabled,Enabled"
group.long c15:0x02E9++0x00
line.long 0x00 "PMINTENCLR,Interrupt Enable Clear Register"
eventfld.long 0x00 31. "C,CCNT overflow interrupt enable" "Disabled,Enabled"
newline
eventfld.long 0x00 3. "P3,PMCNT3 overflow interrupt enable" "Disabled,Enabled"
eventfld.long 0x00 2. "P2,PMCNT2 overflow interrupt enable" "Disabled,Enabled"
eventfld.long 0x00 1. "P1,PMCNT1 overflow interrupt enable" "Disabled,Enabled"
eventfld.long 0x00 0. "P0,PMCNT0 overflow interrupt enable" "Disabled,Enabled"
group.long c15:0x3E9++0x00
line.long 0x00 "PMOVSSET,Performance Monitor Overflow Flag Status Set Register"
group.long c15:(0x008E+0x0)++0x00
line.long 0x00 "PMEVCNTR0,Performance Monitors Event Count Register 0"
group.long c15:(0x00CE+0x0)++0x00
line.long 0x00 "PMEVTYPER0,Performance Monitors Event Type Register 0"
group.long c15:(0x008E+0x100)++0x00
line.long 0x00 "PMEVCNTR1,Performance Monitors Event Count Register 1"
group.long c15:(0x00CE+0x100)++0x00
line.long 0x00 "PMEVTYPER1,Performance Monitors Event Type Register 1"
group.long c15:(0x008E+0x200)++0x00
line.long 0x00 "PMEVCNTR2,Performance Monitors Event Count Register 2"
group.long c15:(0x00CE+0x200)++0x00
line.long 0x00 "PMEVTYPER2,Performance Monitors Event Type Register 2"
group.long c15:(0x008E+0x300)++0x00
line.long 0x00 "PMEVCNTR3,Performance Monitors Event Count Register 3"
group.long c15:(0x00CE+0x300)++0x00
line.long 0x00 "PMEVTYPER3,Performance Monitors Event Type Register 3"
group.long c15:0x07FE++0x00
line.long 0x00 "PMCCFILTR,Performance Monitors Cycle Count Filter Register"
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
newline
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
tree.end
tree "System Timer Registers"
rgroup.long c15:0x000E++0x00
line.long 0x00 "CNTFRQ,Counter Frequency Register"
rgroup.quad c15:0x100E0++0x01
line.quad 0x00 "CNTPCT,Counter Physical Count Register"
rgroup.quad c15:0x110E0++0x01
line.quad 0x00 "CNTVCT,Counter Virtual Count Register"
group.quad c15:0x140E0++0x01
line.quad 0x00 "CNTVOFF,Counter Virtual Offset Register"
group.long c15:0x001E++0x00
line.long 0x00 "CNTKCTL,Timer PL1 Control Register"
bitfld.long 0x00 9. "EL0PTEN,Controls whether the physical timer registers are accessible from EL0 mode" "Disabled,Enabled"
bitfld.long 0x00 8. "EL0VTEN,Controls whether the virtual timer registers are accessible from EL0 mode" "Disabled,Enabled"
bitfld.long 0x00 4.--7. "EVNTI,Selects which bit of CNTVCT is the trigger for the event stream generated from the virtual counter, when that stream is enabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit" "0 to 1,1 to 0"
newline
bitfld.long 0x00 2. "EVNTEN,Enables the generation of an event stream from the virtual counter" "Disabled,Enabled"
bitfld.long 0x00 1. "EL0VCTEN,Controls whether the virtual counter, CNTVCT, and the frequency register CNTFRQ, are accessible from EL0 mode" "Disabled,Enabled"
bitfld.long 0x00 0. "EL0PCTEN,Controls whether the physical counter, CNTPCT, and the frequency register CNTFRQ, are accessible from EL0 mode" "Disabled,Enabled"
group.long c15:0x401E++0x00
line.long 0x00 "CNTHCTL,Counter Non-secure PL2 Control Register"
bitfld.long 0x00 4.--7. "EVNTI,Selects which bit of CNTPCT is the trigger for the event stream generated from the physical counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 3. "EVNTDIR,Controls which transition of the CNTPCT trigger bit, defined by EVNTI" "0 to 1,1 to 0"
bitfld.long 0x00 2. "EVNTEN,Enables the generation of an event stream from the physical counter" "Disabled,Enabled"
bitfld.long 0x00 1. "EL1PCEN,Controls whether the Non-secure copies of the physical timer registers are accessible from Non-secure EL1 and EL0 modes" "Not accessible,Accessible"
newline
bitfld.long 0x00 0. "EL1PCTEN,Controls whether the physical counter, CNTPCT, is accessible from Non-secure EL1 and EL0 modes" "Not accessible,Accessible"
group.long c15:0x002E++0x00
line.long 0x00 "CNTP_TVAL,Counter EL1 Physical Timer Value Register"
group.long c15:0x012E++0x00
line.long 0x00 "CNTP_CTL,Counter EL1 Physical Timer Control Register"
bitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt"
bitfld.long 0x00 1. "IMASK,Timer interrupt mask" "Not masked,Masked"
bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
group.quad c15:0x120E0++0x01
line.quad 0x00 "CNTP_CVAL,Counter EL1 Physical Compare Value Register"
group.long c15:0x003E++0x00
line.long 0x00 "CNTV_TVAL,Counter EL1 Virtual Timer Value Register"
group.long c15:0x013E++0x00
line.long 0x00 "CNTV_CTL,Counter EL1 Virtual Timer Control Register"
bitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt"
bitfld.long 0x00 1. "IMASK,Timer interrupt mask" "Not masked,Masked"
bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
group.quad c15:0x130E0++0x01
line.quad 0x00 "CNTV_CVAL,Counter EL1 Virtual Compare Value Register"
group.long c15:0x402E++0x00
line.long 0x00 "CNTHP_TVAL,Counter Non-secure EL2 Physical Timer Value Register"
group.long c15:0x412E++0x00
line.long 0x00 "CNTHP_CTL,Counter Non-secure EL2 Physical Timer Control Register"
bitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt"
bitfld.long 0x00 1. "IMASK,Timer interrupt mask" "Not masked,Masked"
bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
group.quad c15:0x160E0++0x01
line.quad 0x00 "CNTHP_CVAL,Counter Non-secure EL2 Physical Compare Value Register"
tree.end
tree "Generic Interrupt Controller CPU Interface"
tree "AArch32 GIC Physical CPU Interface System Registers"
tree.open "Interrupt Controller Active Priorities Registers"
group.long c15:(0x048C+0x0)++0x00
line.long 0x00 "ICC_AP0R0,Interrupt Controller Active Priorities Group 0x0 Register"
bitfld.long 0x00 31. "P[31],Group 0 interrupt active with priority level 31" "No interrupt,Interrupt"
bitfld.long 0x00 30. "P[30],Group 0 interrupt active with priority level 30" "No interrupt,Interrupt"
bitfld.long 0x00 29. "P[29],Group 0 interrupt active with priority level 29" "No interrupt,Interrupt"
bitfld.long 0x00 28. "P[28],Group 0 interrupt active with priority level 28" "No interrupt,Interrupt"
newline
bitfld.long 0x00 27. "P[27],Group 0 interrupt active with priority level 27" "No interrupt,Interrupt"
bitfld.long 0x00 26. "P[26],Group 0 interrupt active with priority level 26" "No interrupt,Interrupt"
bitfld.long 0x00 25. "P[25],Group 0 interrupt active with priority level 25" "No interrupt,Interrupt"
bitfld.long 0x00 24. "P[24],Group 0 interrupt active with priority level 24" "No interrupt,Interrupt"
newline
bitfld.long 0x00 23. "P[23],Group 0 interrupt active with priority level 23" "No interrupt,Interrupt"
bitfld.long 0x00 22. "P[22],Group 0 interrupt active with priority level 22" "No interrupt,Interrupt"
bitfld.long 0x00 21. "P[21],Group 0 interrupt active with priority level 21" "No interrupt,Interrupt"
bitfld.long 0x00 20. "P[20],Group 0 interrupt active with priority level 20" "No interrupt,Interrupt"
newline
bitfld.long 0x00 19. "P[19],Group 0 interrupt active with priority level 19" "No interrupt,Interrupt"
bitfld.long 0x00 18. "P[18],Group 0 interrupt active with priority level 18" "No interrupt,Interrupt"
bitfld.long 0x00 17. "P[17],Group 0 interrupt active with priority level 17" "No interrupt,Interrupt"
bitfld.long 0x00 16. "P[16],Group 0 interrupt active with priority level 16" "No interrupt,Interrupt"
newline
bitfld.long 0x00 15. "P[15],Group 0 interrupt active with priority level 15" "No interrupt,Interrupt"
bitfld.long 0x00 14. "P[14],Group 0 interrupt active with priority level 14" "No interrupt,Interrupt"
bitfld.long 0x00 13. "P[13],Group 0 interrupt active with priority level 13" "No interrupt,Interrupt"
bitfld.long 0x00 12. "P[12],Group 0 interrupt active with priority level 12" "No interrupt,Interrupt"
newline
bitfld.long 0x00 11. "P[11],Group 0 interrupt active with priority level 11" "No interrupt,Interrupt"
bitfld.long 0x00 10. "P[10],Group 0 interrupt active with priority level 10" "No interrupt,Interrupt"
bitfld.long 0x00 9. "P[9],Group 0 interrupt active with priority level 9" "No interrupt,Interrupt"
bitfld.long 0x00 8. "P[8],Group 0 interrupt active with priority level 8" "No interrupt,Interrupt"
newline
bitfld.long 0x00 7. "P[7],Group 0 interrupt active with priority level 7" "No interrupt,Interrupt"
bitfld.long 0x00 6. "P[6],Group 0 interrupt active with priority level 6" "No interrupt,Interrupt"
bitfld.long 0x00 5. "P[5],Group 0 interrupt active with priority level 5" "No interrupt,Interrupt"
bitfld.long 0x00 4. "P[4],Group 0 interrupt active with priority level 4" "No interrupt,Interrupt"
newline
bitfld.long 0x00 3. "P[3],Group 0 interrupt active with priority level 3" "No interrupt,Interrupt"
bitfld.long 0x00 2. "P[2],Group 0 interrupt active with priority level 2" "No interrupt,Interrupt"
bitfld.long 0x00 1. "P[1],Group 0 interrupt active with priority level 1" "No interrupt,Interrupt"
bitfld.long 0x00 0. "P[0],Group 0 interrupt active with priority level 0" "No interrupt,Interrupt"
group.long c15:(0x048C+0xFFFFFFFFFFFFFC10)++0x00
line.long 0x00 "ICC_AP1R0,Interrupt Controller Active Priorities Group 0xFFFFFFFFFFFFFC10 Register"
bitfld.long 0x00 31. "P[31],Group 1 interrupt active with priority level 31" "No interrupt,Interrupt"
bitfld.long 0x00 30. "P[30],Group 1 interrupt active with priority level 30" "No interrupt,Interrupt"
bitfld.long 0x00 29. "P[29],Group 1 interrupt active with priority level 29" "No interrupt,Interrupt"
bitfld.long 0x00 28. "P[28],Group 1 interrupt active with priority level 28" "No interrupt,Interrupt"
newline
bitfld.long 0x00 27. "P[27],Group 1 interrupt active with priority level 27" "No interrupt,Interrupt"
bitfld.long 0x00 26. "P[26],Group 1 interrupt active with priority level 26" "No interrupt,Interrupt"
bitfld.long 0x00 25. "P[25],Group 1 interrupt active with priority level 25" "No interrupt,Interrupt"
bitfld.long 0x00 24. "P[24],Group 1 interrupt active with priority level 24" "No interrupt,Interrupt"
newline
bitfld.long 0x00 23. "P[23],Group 1 interrupt active with priority level 23" "No interrupt,Interrupt"
bitfld.long 0x00 22. "P[22],Group 1 interrupt active with priority level 22" "No interrupt,Interrupt"
bitfld.long 0x00 21. "P[21],Group 1 interrupt active with priority level 21" "No interrupt,Interrupt"
bitfld.long 0x00 20. "P[20],Group 1 interrupt active with priority level 20" "No interrupt,Interrupt"
newline
bitfld.long 0x00 19. "P[19],Group 1 interrupt active with priority level 19" "No interrupt,Interrupt"
bitfld.long 0x00 18. "P[18],Group 1 interrupt active with priority level 18" "No interrupt,Interrupt"
bitfld.long 0x00 17. "P[17],Group 1 interrupt active with priority level 17" "No interrupt,Interrupt"
bitfld.long 0x00 16. "P[16],Group 1 interrupt active with priority level 16" "No interrupt,Interrupt"
newline
bitfld.long 0x00 15. "P[15],Group 1 interrupt active with priority level 15" "No interrupt,Interrupt"
bitfld.long 0x00 14. "P[14],Group 1 interrupt active with priority level 14" "No interrupt,Interrupt"
bitfld.long 0x00 13. "P[13],Group 1 interrupt active with priority level 13" "No interrupt,Interrupt"
bitfld.long 0x00 12. "P[12],Group 1 interrupt active with priority level 12" "No interrupt,Interrupt"
newline
bitfld.long 0x00 11. "P[11],Group 1 interrupt active with priority level 11" "No interrupt,Interrupt"
bitfld.long 0x00 10. "P[10],Group 1 interrupt active with priority level 10" "No interrupt,Interrupt"
bitfld.long 0x00 9. "P[9],Group 1 interrupt active with priority level 9" "No interrupt,Interrupt"
bitfld.long 0x00 8. "P[8],Group 1 interrupt active with priority level 8" "No interrupt,Interrupt"
newline
bitfld.long 0x00 7. "P[7],Group 1 interrupt active with priority level 7" "No interrupt,Interrupt"
bitfld.long 0x00 6. "P[6],Group 1 interrupt active with priority level 6" "No interrupt,Interrupt"
bitfld.long 0x00 5. "P[5],Group 1 interrupt active with priority level 5" "No interrupt,Interrupt"
bitfld.long 0x00 4. "P[4],Group 1 interrupt active with priority level 4" "No interrupt,Interrupt"
newline
bitfld.long 0x00 3. "P[3],Group 1 interrupt active with priority level 3" "No interrupt,Interrupt"
bitfld.long 0x00 2. "P[2],Group 1 interrupt active with priority level 2" "No interrupt,Interrupt"
bitfld.long 0x00 1. "P[1],Group 1 interrupt active with priority level 1" "No interrupt,Interrupt"
bitfld.long 0x00 0. "P[0],Group 1 interrupt active with priority level 0" "No interrupt,Interrupt"
tree.end
newline
group.long c15:(0x038C+0x0)++0x00
line.long 0x00 "ICC_BPR0,Interrupt Controller Binary Point Register 0"
bitfld.long 0x00 0.--2. "BINARYPOINT,5-bit interrupt priority field control" "Reserved,Reserved,2,3,4,5,6,7"
group.long c15:(0x038C+0x40)++0x00
line.long 0x00 "ICC_BPR1,Interrupt Controller Binary Point Register 1"
bitfld.long 0x00 0.--2. "BINARYPOINT,5-bit interrupt priority field control" "Reserved,Reserved,2,3,4,5,6,7"
group.long c15:0x04CC++0x00
line.long 0x00 "ICC_CTLR,Interrupt Control Register for EL1"
rbitfld.long 0x00 15. "A3V,Affinity 3 valid" "Not supported,?..."
rbitfld.long 0x00 14. "SEIS,SEI support" "Not supported,?..."
rbitfld.long 0x00 11.--13. "IDBITS,Number of physical interrupt identifier bits supported" "16 bits,?..."
newline
rbitfld.long 0x00 8.--10. "PRIBITS,Number of priority bits implemented" "Reserved,Reserved,Reserved,Reserved,5,?..."
bitfld.long 0x00 1. "EOIMODE,Alias of ICC_MCTLR.EOImode_EL1" "0,1"
bitfld.long 0x00 0. "CBPR,Common binary point register" "0,1"
wgroup.long c15:0x01BC++0x00
line.long 0x00 "ICC_DIR,Interrupt Controller Deactivate Interrupt Register"
hexmask.long.word 0x00 0.--9. 1. "INTID,Interrupt ID"
wgroup.long c15:(0x018C+0x0)++0x00
line.long 0x00 "ICC_EOIR0,Interrupt Controller End Of Interrupt Register 0"
hexmask.long.word 0x00 0.--9. 1. "INTID,INTID from the corresponding ICC_IAR0 access"
rgroup.long c15:(0x028C+0x0)++0x00
line.long 0x00 "ICC_HPPIR0,Interrupt Controller Highest Priority Pending Interrupt Register 0"
hexmask.long.word 0x00 0.--9. 1. "INTID,INTID of the highest priority pending Group 0 interrupt"
rgroup.long c15:(0x008C+0x0)++0x00
line.long 0x00 "ICC_IAR0,Interrupt Controller Interrupt Acknowledge Register 0"
hexmask.long.word 0x00 0.--9. 1. "INTID,INTID of the signaled interrupt"
group.long c15:(0x06CC+0x0)++0x00
line.long 0x00 "ICC_IGRPEN0,Interrupt Controller Group Enable Register 0"
bitfld.long 0x00 0. "ENABLE,Enable group 0 interrupts" "Disabled,Enabled"
wgroup.long c15:(0x018C+0x40)++0x00
line.long 0x00 "ICC_EOIR1,Interrupt Controller End Of Interrupt Register 1"
hexmask.long.word 0x00 0.--9. 1. "INTID,INTID from the corresponding ICC_IAR0 access"
rgroup.long c15:(0x028C+0x40)++0x00
line.long 0x00 "ICC_HPPIR1,Interrupt Controller Highest Priority Pending Interrupt Register 1"
hexmask.long.word 0x00 0.--9. 1. "INTID,INTID of the highest priority pending Group 1 interrupt"
rgroup.long c15:(0x008C+0x40)++0x00
line.long 0x00 "ICC_IAR1,Interrupt Controller Interrupt Acknowledge Register 1"
hexmask.long.word 0x00 0.--9. 1. "INTID,INTID of the signaled interrupt"
group.long c15:(0x06CC+0x100)++0x00
line.long 0x00 "ICC_IGRPEN1,Interrupt Controller Group Enable Register 1"
bitfld.long 0x00 0. "ENABLE,Enable group 1 interrupts" "Disabled,Enabled"
group.long c15:0x0064++0x00
line.long 0x00 "ICC_PMR,Interrupt Controller Interrupt Priority Mask Register"
bitfld.long 0x00 3.--7. "PRIORITY,The priority mask level for the CPU interface" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,Lowest"
rgroup.long c15:0x03BC++0x00
line.long 0x00 "ICC_RPR,Interrupt Controller Running Priority Register"
hexmask.long.byte 0x00 0.--7. 1. "PRIORITY,Current running priority on the CPU interface"
wgroup.quad c15:(0x120C0-0x0)++0x01
line.quad 0x00 "ICC_SGI0R,SGI Generation Register 0"
hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3"
bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Disabled,Enabled"
hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2"
newline
bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1"
bitfld.quad 0x00 0.--4. "TARGETLIST,Target list" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
wgroup.quad c15:(0x120C0-0x2000)++0x01
line.quad 0x00 "ICC_SGI1R,SGI Generation Register 1"
hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3"
bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Disabled,Enabled"
hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2"
newline
bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1"
bitfld.quad 0x00 0.--4. "TARGETLIST,Target list" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
wgroup.quad c15:0x110C0++0x01
line.quad 0x00 "ICC_ASGI1R,Alias SGI Generation Register $2"
hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3"
bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Disabled,Enabled"
hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2"
newline
bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1"
bitfld.quad 0x00 0.--4. "TARGETLIST,Target list" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long c15:0x05CC++0x00
line.long 0x00 "ICC_SRE,System Register Enable Register for EL1"
bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "Reserved,Yes"
bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "Reserved,Yes"
bitfld.long 0x00 0. "SRE,System register enable" "Reserved,Enabled"
group.long c15:0x459C++0x00
line.long 0x00 "ICC_HSRE,System Register Enable Register for EL2"
bitfld.long 0x00 3. "ENABLE,Enable lower exception level access to ICC_SRE_EL1" "Reserved,Enabled"
bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "Reserved,Yes"
bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "Reserved,Yes"
newline
bitfld.long 0x00 0. "SRE,System register enable" "Reserved,Enabled"
tree.end
tree "AArch32 GIC Virtual CPU Interface System Registers"
tree.open "Interrupt Controller Active Priorities Registers"
group.long c15:(0x048C+0x0)++0x00
line.long 0x00 "ICV_AP0R0,Interrupt Controller Virtual Active Priorities Group 0x0 Register 0"
bitfld.long 0x00 31. "P[31],Group 0 interrupt active with priority level 31" "No interrupt,Interrupt"
bitfld.long 0x00 30. "P[30],Group 0 interrupt active with priority level 30" "No interrupt,Interrupt"
bitfld.long 0x00 29. "P[29],Group 0 interrupt active with priority level 29" "No interrupt,Interrupt"
bitfld.long 0x00 28. "P[28],Group 0 interrupt active with priority level 28" "No interrupt,Interrupt"
newline
bitfld.long 0x00 27. "P[27],Group 0 interrupt active with priority level 27" "No interrupt,Interrupt"
bitfld.long 0x00 26. "P[26],Group 0 interrupt active with priority level 26" "No interrupt,Interrupt"
bitfld.long 0x00 25. "P[25],Group 0 interrupt active with priority level 25" "No interrupt,Interrupt"
bitfld.long 0x00 24. "P[24],Group 0 interrupt active with priority level 24" "No interrupt,Interrupt"
newline
bitfld.long 0x00 23. "P[23],Group 0 interrupt active with priority level 23" "No interrupt,Interrupt"
bitfld.long 0x00 22. "P[22],Group 0 interrupt active with priority level 22" "No interrupt,Interrupt"
bitfld.long 0x00 21. "P[21],Group 0 interrupt active with priority level 21" "No interrupt,Interrupt"
bitfld.long 0x00 20. "P[20],Group 0 interrupt active with priority level 20" "No interrupt,Interrupt"
newline
bitfld.long 0x00 19. "P[19],Group 0 interrupt active with priority level 19" "No interrupt,Interrupt"
bitfld.long 0x00 18. "P[18],Group 0 interrupt active with priority level 18" "No interrupt,Interrupt"
bitfld.long 0x00 17. "P[17],Group 0 interrupt active with priority level 17" "No interrupt,Interrupt"
bitfld.long 0x00 16. "P[16],Group 0 interrupt active with priority level 16" "No interrupt,Interrupt"
newline
bitfld.long 0x00 15. "P[15],Group 0 interrupt active with priority level 15" "No interrupt,Interrupt"
bitfld.long 0x00 14. "P[14],Group 0 interrupt active with priority level 14" "No interrupt,Interrupt"
bitfld.long 0x00 13. "P[13],Group 0 interrupt active with priority level 13" "No interrupt,Interrupt"
bitfld.long 0x00 12. "P[12],Group 0 interrupt active with priority level 12" "No interrupt,Interrupt"
newline
bitfld.long 0x00 11. "P[11],Group 0 interrupt active with priority level 11" "No interrupt,Interrupt"
bitfld.long 0x00 10. "P[10],Group 0 interrupt active with priority level 10" "No interrupt,Interrupt"
bitfld.long 0x00 9. "P[9],Group 0 interrupt active with priority level 9" "No interrupt,Interrupt"
bitfld.long 0x00 8. "P[8],Group 0 interrupt active with priority level 8" "No interrupt,Interrupt"
newline
bitfld.long 0x00 7. "P[7],Group 0 interrupt active with priority level 7" "No interrupt,Interrupt"
bitfld.long 0x00 6. "P[6],Group 0 interrupt active with priority level 6" "No interrupt,Interrupt"
bitfld.long 0x00 5. "P[5],Group 0 interrupt active with priority level 5" "No interrupt,Interrupt"
bitfld.long 0x00 4. "P[4],Group 0 interrupt active with priority level 4" "No interrupt,Interrupt"
newline
bitfld.long 0x00 3. "P[3],Group 0 interrupt active with priority level 3" "No interrupt,Interrupt"
bitfld.long 0x00 2. "P[2],Group 0 interrupt active with priority level 2" "No interrupt,Interrupt"
bitfld.long 0x00 1. "P[1],Group 0 interrupt active with priority level 1" "No interrupt,Interrupt"
bitfld.long 0x00 0. "P[0],Group 0 interrupt active with priority level 0" "No interrupt,Interrupt"
group.long c15:(0x048C+0xFFFFFFFFFFFFFC10)++0x00
line.long 0x00 "ICV_AP1R0,Interrupt Controller Virtual Active Priorities Group 0xFFFFFFFFFFFFFC10 Register 0"
bitfld.long 0x00 31. "P[31],Group 1 interrupt active with priority level 31" "No interrupt,Interrupt"
bitfld.long 0x00 30. "P[30],Group 1 interrupt active with priority level 30" "No interrupt,Interrupt"
bitfld.long 0x00 29. "P[29],Group 1 interrupt active with priority level 29" "No interrupt,Interrupt"
bitfld.long 0x00 28. "P[28],Group 1 interrupt active with priority level 28" "No interrupt,Interrupt"
newline
bitfld.long 0x00 27. "P[27],Group 1 interrupt active with priority level 27" "No interrupt,Interrupt"
bitfld.long 0x00 26. "P[26],Group 1 interrupt active with priority level 26" "No interrupt,Interrupt"
bitfld.long 0x00 25. "P[25],Group 1 interrupt active with priority level 25" "No interrupt,Interrupt"
bitfld.long 0x00 24. "P[24],Group 1 interrupt active with priority level 24" "No interrupt,Interrupt"
newline
bitfld.long 0x00 23. "P[23],Group 1 interrupt active with priority level 23" "No interrupt,Interrupt"
bitfld.long 0x00 22. "P[22],Group 1 interrupt active with priority level 22" "No interrupt,Interrupt"
bitfld.long 0x00 21. "P[21],Group 1 interrupt active with priority level 21" "No interrupt,Interrupt"
bitfld.long 0x00 20. "P[20],Group 1 interrupt active with priority level 20" "No interrupt,Interrupt"
newline
bitfld.long 0x00 19. "P[19],Group 1 interrupt active with priority level 19" "No interrupt,Interrupt"
bitfld.long 0x00 18. "P[18],Group 1 interrupt active with priority level 18" "No interrupt,Interrupt"
bitfld.long 0x00 17. "P[17],Group 1 interrupt active with priority level 17" "No interrupt,Interrupt"
bitfld.long 0x00 16. "P[16],Group 1 interrupt active with priority level 16" "No interrupt,Interrupt"
newline
bitfld.long 0x00 15. "P[15],Group 1 interrupt active with priority level 15" "No interrupt,Interrupt"
bitfld.long 0x00 14. "P[14],Group 1 interrupt active with priority level 14" "No interrupt,Interrupt"
bitfld.long 0x00 13. "P[13],Group 1 interrupt active with priority level 13" "No interrupt,Interrupt"
bitfld.long 0x00 12. "P[12],Group 1 interrupt active with priority level 12" "No interrupt,Interrupt"
newline
bitfld.long 0x00 11. "P[11],Group 1 interrupt active with priority level 11" "No interrupt,Interrupt"
bitfld.long 0x00 10. "P[10],Group 1 interrupt active with priority level 10" "No interrupt,Interrupt"
bitfld.long 0x00 9. "P[9],Group 1 interrupt active with priority level 9" "No interrupt,Interrupt"
bitfld.long 0x00 8. "P[8],Group 1 interrupt active with priority level 8" "No interrupt,Interrupt"
newline
bitfld.long 0x00 7. "P[7],Group 1 interrupt active with priority level 7" "No interrupt,Interrupt"
bitfld.long 0x00 6. "P[6],Group 1 interrupt active with priority level 6" "No interrupt,Interrupt"
bitfld.long 0x00 5. "P[5],Group 1 interrupt active with priority level 5" "No interrupt,Interrupt"
bitfld.long 0x00 4. "P[4],Group 1 interrupt active with priority level 4" "No interrupt,Interrupt"
newline
bitfld.long 0x00 3. "P[3],Group 1 interrupt active with priority level 3" "No interrupt,Interrupt"
bitfld.long 0x00 2. "P[2],Group 1 interrupt active with priority level 2" "No interrupt,Interrupt"
bitfld.long 0x00 1. "P[1],Group 1 interrupt active with priority level 1" "No interrupt,Interrupt"
bitfld.long 0x00 0. "P[0],Group 1 interrupt active with priority level 0" "No interrupt,Interrupt"
tree.end
newline
group.long c15:0x04CC++0x00
line.long 0x00 "ICV_CTLR,Interrupt Controller Virtual Control Register"
rbitfld.long 0x00 15. "A3V,Affinity 3 valid" "Not supported,?..."
rbitfld.long 0x00 14. "SEIS,SEI support" "Not supported,?..."
rbitfld.long 0x00 11.--13. "IDBITS,Number of physical interrupt identifier bits supported" "16 bits,?..."
newline
rbitfld.long 0x00 8.--10. "PRIBITS,Number of priority bits implemented" "Reserved,Reserved,Reserved,Reserved,5,?..."
bitfld.long 0x00 1. "EOIMODE,Alias of ICC_MCTLR.EOImode_EL1" "0,1"
bitfld.long 0x00 0. "CBPR,Common binary point register" "0,1"
wgroup.long c15:0x01BC++0x00
line.long 0x00 "ICV_DIR,Interrupt Controller Virtual Deactivate Interrupt Register"
hexmask.long.word 0x00 0.--15. 1. "INTID,Interrupt ID"
hgroup.long c15:(0x008C+0x0)++0x00
hide.long 0x00 "ICV_IAR0,Interrupt Controller Vitrtual Interrupt Acknowledge Register 0"
wgroup.long c15:(0x018C+0x0)++0x00
line.long 0x00 "ICV_EOIR0,Interrupt Controller Vitrtual End Of Interrupt Register 0"
hexmask.long.word 0x00 0.--15. 1. "INTID,INTID from the corresponding ICC_IAR0 access"
rgroup.long c15:(0x028C+0x0)++0x00
line.long 0x00 "ICV_HPPIR0,Interrupt Controller Vitrtual Highest Priority Pending Interrupt Register 0"
hexmask.long.word 0x00 0.--15. 1. "INTID,INTID of the highest priority pending Group 0 interrupt"
group.long c15:(0x038C+0x0)++0x00
line.long 0x00 "ICV_BPR0,Interrupt Controller Vitrtual Binary Point Register 0"
bitfld.long 0x00 0.--2. "BINARYPOINT,5-bit interrupt priority field control" "Reserved,Reserved,2,3,4,5,6,7"
hgroup.long c15:(0x008C+0x40)++0x00
hide.long 0x00 "ICV_IAR1,Interrupt Controller Vitrtual Interrupt Acknowledge Register 1"
wgroup.long c15:(0x018C+0x40)++0x00
line.long 0x00 "ICV_EOIR1,Interrupt Controller Vitrtual End Of Interrupt Register 1"
hexmask.long.word 0x00 0.--15. 1. "INTID,INTID from the corresponding ICC_IAR1 access"
rgroup.long c15:(0x028C+0x40)++0x00
line.long 0x00 "ICV_HPPIR1,Interrupt Controller Vitrtual Highest Priority Pending Interrupt Register 1"
hexmask.long.word 0x00 0.--15. 1. "INTID,INTID of the highest priority pending Group 1 interrupt"
group.long c15:(0x038C+0x40)++0x00
line.long 0x00 "ICV_BPR1,Interrupt Controller Vitrtual Binary Point Register 1"
bitfld.long 0x00 0.--2. "BINARYPOINT,5-bit interrupt priority field control" "Reserved,Reserved,2,3,4,5,6,7"
group.long c15:0x07CC++0x00
line.long 0x00 "ICV_IGRPEN1,Interrupt Controller Virtual Group Enable Register 1"
bitfld.long 0x00 0. "ENABLE,Enable group 1 interrupts" "Disabled,Enabled"
group.long c15:0x06CC++0x00
line.long 0x00 "ICV_IGRPEN0,Interrupt Controller Virtual Interrupt Group 0 Enable Register"
bitfld.long 0x00 0. "ENABLE,Enable group 0 interrupts" "Disabled,Enabled"
group.long c15:0x0064++0x00
line.long 0x00 "ICV_PMR,Interrupt Controller Virtual Interrupt Priority Mask Register"
bitfld.long 0x00 3.--7. "PRIORITY,The priority mask level for the CPU interface" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,Lowest"
rgroup.long c15:0x03BC++0x00
line.long 0x00 "ICV_RPR,Interrupt Controller Virtual Running Priority Register"
hexmask.long.byte 0x00 0.--7. 1. "PRIORITY,Current running priority on the CPU interface"
tree.end
tree "AArch32 Virtual Interface Control System Registers"
tree.open "Interrupt Controller Hypervisor Active Priorities Register"
group.long c15:0x408C++0x00
line.long 0x00 "ICH_AP0R0,Interrupt Controller Hypervisor Active Priorities Group 0 Register 0"
bitfld.long 0x00 31. "P[31],Group 0 interrupt active with priority level 31" "No interrupt,Interrupt"
bitfld.long 0x00 30. "P[30],Group 0 interrupt active with priority level 30" "No interrupt,Interrupt"
bitfld.long 0x00 29. "P[29],Group 0 interrupt active with priority level 29" "No interrupt,Interrupt"
bitfld.long 0x00 28. "P[28],Group 0 interrupt active with priority level 28" "No interrupt,Interrupt"
newline
bitfld.long 0x00 27. "P[27],Group 0 interrupt active with priority level 27" "No interrupt,Interrupt"
bitfld.long 0x00 26. "P[26],Group 0 interrupt active with priority level 26" "No interrupt,Interrupt"
bitfld.long 0x00 25. "P[25],Group 0 interrupt active with priority level 25" "No interrupt,Interrupt"
bitfld.long 0x00 24. "P[24],Group 0 interrupt active with priority level 24" "No interrupt,Interrupt"
newline
bitfld.long 0x00 23. "P[23],Group 0 interrupt active with priority level 23" "No interrupt,Interrupt"
bitfld.long 0x00 22. "P[22],Group 0 interrupt active with priority level 22" "No interrupt,Interrupt"
bitfld.long 0x00 21. "P[21],Group 0 interrupt active with priority level 21" "No interrupt,Interrupt"
bitfld.long 0x00 20. "P[20],Group 0 interrupt active with priority level 20" "No interrupt,Interrupt"
newline
bitfld.long 0x00 19. "P[19],Group 0 interrupt active with priority level 19" "No interrupt,Interrupt"
bitfld.long 0x00 18. "P[18],Group 0 interrupt active with priority level 18" "No interrupt,Interrupt"
bitfld.long 0x00 17. "P[17],Group 0 interrupt active with priority level 17" "No interrupt,Interrupt"
bitfld.long 0x00 16. "P[16],Group 0 interrupt active with priority level 16" "No interrupt,Interrupt"
newline
bitfld.long 0x00 15. "P[15],Group 0 interrupt active with priority level 15" "No interrupt,Interrupt"
bitfld.long 0x00 14. "P[14],Group 0 interrupt active with priority level 14" "No interrupt,Interrupt"
bitfld.long 0x00 13. "P[13],Group 0 interrupt active with priority level 13" "No interrupt,Interrupt"
bitfld.long 0x00 12. "P[12],Group 0 interrupt active with priority level 12" "No interrupt,Interrupt"
newline
bitfld.long 0x00 11. "P[11],Group 0 interrupt active with priority level 11" "No interrupt,Interrupt"
bitfld.long 0x00 10. "P[10],Group 0 interrupt active with priority level 10" "No interrupt,Interrupt"
bitfld.long 0x00 9. "P[9],Group 0 interrupt active with priority level 9" "No interrupt,Interrupt"
bitfld.long 0x00 8. "P[8],Group 0 interrupt active with priority level 8" "No interrupt,Interrupt"
newline
bitfld.long 0x00 7. "P[7],Group 0 interrupt active with priority level 7" "No interrupt,Interrupt"
bitfld.long 0x00 6. "P[6],Group 0 interrupt active with priority level 6" "No interrupt,Interrupt"
bitfld.long 0x00 5. "P[5],Group 0 interrupt active with priority level 5" "No interrupt,Interrupt"
bitfld.long 0x00 4. "P[4],Group 0 interrupt active with priority level 4" "No interrupt,Interrupt"
newline
bitfld.long 0x00 3. "P[3],Group 0 interrupt active with priority level 3" "No interrupt,Interrupt"
bitfld.long 0x00 2. "P[2],Group 0 interrupt active with priority level 2" "No interrupt,Interrupt"
bitfld.long 0x00 1. "P[1],Group 0 interrupt active with priority level 1" "No interrupt,Interrupt"
bitfld.long 0x00 0. "P[0],Group 0 interrupt active with priority level 0" "No interrupt,Interrupt"
group.long c15:0x409C++0x00
line.long 0x00 "ICH_AP1R0,Interrupt Controller Hypervisor Active Priorities Group 1 Register 0"
bitfld.long 0x00 31. "P[31],Group 1 interrupt active with priority level 31" "No interrupt,Interrupt"
bitfld.long 0x00 30. "P[30],Group 1 interrupt active with priority level 30" "No interrupt,Interrupt"
bitfld.long 0x00 29. "P[29],Group 1 interrupt active with priority level 29" "No interrupt,Interrupt"
bitfld.long 0x00 28. "P[28],Group 1 interrupt active with priority level 28" "No interrupt,Interrupt"
newline
bitfld.long 0x00 27. "P[27],Group 1 interrupt active with priority level 27" "No interrupt,Interrupt"
bitfld.long 0x00 26. "P[26],Group 1 interrupt active with priority level 26" "No interrupt,Interrupt"
bitfld.long 0x00 25. "P[25],Group 1 interrupt active with priority level 25" "No interrupt,Interrupt"
bitfld.long 0x00 24. "P[24],Group 1 interrupt active with priority level 24" "No interrupt,Interrupt"
newline
bitfld.long 0x00 23. "P[23],Group 1 interrupt active with priority level 23" "No interrupt,Interrupt"
bitfld.long 0x00 22. "P[22],Group 1 interrupt active with priority level 22" "No interrupt,Interrupt"
bitfld.long 0x00 21. "P[21],Group 1 interrupt active with priority level 21" "No interrupt,Interrupt"
bitfld.long 0x00 20. "P[20],Group 1 interrupt active with priority level 20" "No interrupt,Interrupt"
newline
bitfld.long 0x00 19. "P[19],Group 1 interrupt active with priority level 19" "No interrupt,Interrupt"
bitfld.long 0x00 18. "P[18],Group 1 interrupt active with priority level 18" "No interrupt,Interrupt"
bitfld.long 0x00 18. "P[17],Group 1 interrupt active with priority level 17" "No interrupt,Interrupt"
bitfld.long 0x00 16. "P[16],Group 1 interrupt active with priority level 16" "No interrupt,Interrupt"
newline
bitfld.long 0x00 15. "P[15],Group 1 interrupt active with priority level 15" "No interrupt,Interrupt"
bitfld.long 0x00 14. "P[14],Group 1 interrupt active with priority level 14" "No interrupt,Interrupt"
bitfld.long 0x00 13. "P[13],Group 1 interrupt active with priority level 13" "No interrupt,Interrupt"
bitfld.long 0x00 12. "P[12],Group 1 interrupt active with priority level 12" "No interrupt,Interrupt"
newline
bitfld.long 0x00 11. "P[11],Group 1 interrupt active with priority level 11" "No interrupt,Interrupt"
bitfld.long 0x00 10. "P[10],Group 1 interrupt active with priority level 10" "No interrupt,Interrupt"
bitfld.long 0x00 9. "P[9],Group 1 interrupt active with priority level 9" "No interrupt,Interrupt"
bitfld.long 0x00 8. "P[8],Group 1 interrupt active with priority level 8" "No interrupt,Interrupt"
newline
bitfld.long 0x00 7. "P[7],Group 1 interrupt active with priority level 7" "No interrupt,Interrupt"
bitfld.long 0x00 6. "P[6],Group 1 interrupt active with priority level 6" "No interrupt,Interrupt"
bitfld.long 0x00 5. "P[5],Group 1 interrupt active with priority level 5" "No interrupt,Interrupt"
bitfld.long 0x00 4. "P[4],Group 1 interrupt active with priority level 4" "No interrupt,Interrupt"
newline
bitfld.long 0x00 3. "P[3],Group 1 interrupt active with priority level 3" "No interrupt,Interrupt"
bitfld.long 0x00 2. "P[2],Group 1 interrupt active with priority level 2" "No interrupt,Interrupt"
bitfld.long 0x00 1. "P[1],Group 1 interrupt active with priority level 1" "No interrupt,Interrupt"
bitfld.long 0x00 0. "P[0],Group 1 interrupt active with priority level 0" "No interrupt,Interrupt"
tree.end
newline
group.long c15:0x40BC++0x00
line.long 0x00 "ICH_HCR,Interrupt Controller Hypervisor Control Register"
bitfld.long 0x00 27.--31. "EOICOUNT,Number of successful write to a virtual EOIR or DIR resulted in a virtual interrupt deactivation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 14. "TDIR,Trap virtual EL1 writes to ICC_DIR" "Not trapped,Trapped"
bitfld.long 0x00 12. "TALL1,Trap all virtual EL1 accesses to ICC_* system registers for Group 1 interrupts to EL2" "Not trapped,Trapped"
newline
bitfld.long 0x00 11. "TALL0,Trap all virtual EL1 accesses to ICC_* system registers for Group 0 interrupts to EL2" "Not trapped,Trapped"
bitfld.long 0x00 10. "TC,Trap all virtual EL1 accesses to system registers that are common to Group 0 and Group 1 to EL2" "Not trapped,Trapped"
bitfld.long 0x00 7. "VGRP1DIE,VM group 1 disabled interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 6. "VGRP1EIE,VM group 1 enabled interrupt enable" "Disabled,Enabled"
newline
bitfld.long 0x00 5. "VGRP0DIE,VM group 0 disabled interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 4. "VGRP0EIE,VM group 0 enabled interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 3. "NPIE,No pending interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 2. "LRENPIE,List register entry not present interrupt enable" "Disabled,Enabled"
newline
bitfld.long 0x00 1. "UIE,Underflow interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 0. "EN,Global enable bit for the virtual CPU interface" "Disabled,Enabled"
rgroup.long c15:0x41BC++0x00
line.long 0x00 "ICH_VTR,Interrupt Controller Hypervisor Control VGIC Type Register"
bitfld.long 0x00 29.--31. "PRIBITS,Priority bits" "Reserved,Reserved,Reserved,Reserved,5,?..."
bitfld.long 0x00 26.--28. "PREBITS,Preemption bits" "Reserved,Reserved,Reserved,Reserved,5,?..."
bitfld.long 0x00 23.--25. "IDBITS,The number of virtual interrupt identifier bits supported" "16 bits,?..."
bitfld.long 0x00 22. "SEIS,SEI Support" "Not supported,?..."
newline
bitfld.long 0x00 21. "A3V,Affinity 3 support" "Not supported,?..."
bitfld.long 0x00 20. "NV4,GICv4 direct injection of virtual interrupts not supported" "Reserved,Not supported"
bitfld.long 0x00 19. "TDS,Separate trapping EL1 writes to ICV_DIR supported" "Reserved,Supported"
bitfld.long 0x00 0.--4. "LISTREGS,The number of implemented List registers" "Reserved,Reserved,Reserved,4,?..."
rgroup.long c15:0x42BC++0x00
line.long 0x00 "ICH_MISR,Interrupt Controller Maintenance Interrupt Status Register"
bitfld.long 0x00 7. "VGRP1D,vPE group 1 disabled" "No,Yes"
bitfld.long 0x00 6. "VGRP1E,vPE group 1 enabled" "Disabled,Enabled"
bitfld.long 0x00 5. "VGRP0D,vPE group 0 disabled" "No,Yes"
bitfld.long 0x00 4. "VGRP0E,vPE group 0 enabled" "Disabled,Enabled"
newline
bitfld.long 0x00 3. "NP,No pending maintenance interrupt assertion" "Not asserted,Asserted"
bitfld.long 0x00 2. "LRENP,List register entry not present" "Not present,Present"
bitfld.long 0x00 1. "U,Underflow assertion" "Not asserted,Asserted"
bitfld.long 0x00 0. "EOI,End of interrupt assertion" "Not asserted,Asserted"
rgroup.long c15:0x43BC++0x00
line.long 0x00 "ICH_EISR,Interrupt Controller End of Interrupt Status Register"
bitfld.long 0x00 3. "STATUS[3],EOI maintenance interrupt status bit for List (ICH_LR3) register 3" "No interrupt,Interrupt"
bitfld.long 0x00 2. "STATUS[2],EOI maintenance interrupt status bit for List (ICH_LR2) register 2" "No interrupt,Interrupt"
bitfld.long 0x00 1. "STATUS[1],EOI maintenance interrupt status bit for List (ICH_LR1) register 1" "No interrupt,Interrupt"
bitfld.long 0x00 0. "STATUS[0],EOI maintenance interrupt status bit for List (ICH_LR0) register 0" "No interrupt,Interrupt"
group.long c15:0x47BC++0x00
line.long 0x00 "ICH_VMCR,Interrupt Controller Virtual Machine Control Register"
bitfld.long 0x00 27.--31. "VPMR,Virtual priority mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 21.--23. "VBPR0,Virtual binary point register for group 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "VBPR1,Virtual binary point register for group 1" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 9. "VEOIM,Virtual EOI mode" "Drop & interrupt,Drop"
newline
bitfld.long 0x00 4. "VCBPR,Virtual common binary point register" "Separate,Both"
bitfld.long 0x00 1. "VENG1,Virtual group 1 interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 0. "VENG0,Virtual group 0 interrupt enable" "Disabled,Enabled"
rgroup.long c15:0x45BC++0x00
line.long 0x00 "ICH_ELRSR,Interrupt Controller Empty List Register Status Register"
bitfld.long 0x00 3. "STATUS[3],Status bit for list (ICH_LR3) register 3" "Interrupt,No interrupt"
bitfld.long 0x00 2. "STATUS[2],Status bit for list (ICH_LR2) register 2" "Interrupt,No interrupt"
bitfld.long 0x00 1. "STATUS[1],Status bit for list (ICH_LR1) register 1" "Interrupt,No interrupt"
bitfld.long 0x00 0. "STATUS[0],Status bit for list (ICH_LR0) register 0" "Interrupt,No interrupt"
group.long c15:(0x40CC+0x0)++0x00
line.long 0x00 "ICH_LR0,Interrupt Controller List Register 0"
hexmask.long.word 0x00 0.--15. 1. "VINTID,Virtual INTID of the interrupt"
group.long c15:(0x40CC+0x100)++0x00
line.long 0x00 "ICH_LR1,Interrupt Controller List Register 1"
hexmask.long.word 0x00 0.--15. 1. "VINTID,Virtual INTID of the interrupt"
group.long c15:(0x40CC+0x200)++0x00
line.long 0x00 "ICH_LR2,Interrupt Controller List Register 2"
hexmask.long.word 0x00 0.--15. 1. "VINTID,Virtual INTID of the interrupt"
group.long c15:(0x40CC+0x300)++0x00
line.long 0x00 "ICH_LR3,Interrupt Controller List Register 3"
hexmask.long.word 0x00 0.--15. 1. "VINTID,Virtual INTID of the interrupt"
if (((per.l(c15:0x40EC+0x0))&0x20000000)==0x00)
group.long c15:(0x40EC+0x0)++0x00
line.long 0x00 "ICH_LRC0,Interrupt Controller List Register 0"
bitfld.long 0x00 30.--31. "STATE,Interrupt state" "Inactive,Pending,Active,Pending and active"
bitfld.long 0x00 29. "HW,Virtual interrupt maps directly to a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 28. "GROUP,Group for this virtual interrupt" "Group 0,Group 1"
newline
bitfld.long 0x00 19.--23. "PRIORITY,Priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 9. "EOI,End of interrupt" "Not EOI,EOI"
else
group.long c15:(0x40EC+0x0)++0x00
line.long 0x00 "ICH_LRC0,Interrupt Controller List Register 0"
bitfld.long 0x00 30.--31. "STATE,Interrupt state" "Inactive,Pending,Active,Pending and active"
bitfld.long 0x00 29. "HW,Virtual interrupt maps directly to a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 28. "GROUP,Group for this virtual interrupt" "Group 0,Group 1"
newline
bitfld.long 0x00 19.--23. "PRIORITY,Priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts"
endif
if (((per.l(c15:0x40EC+0x100))&0x20000000)==0x00)
group.long c15:(0x40EC+0x100)++0x00
line.long 0x00 "ICH_LRC1,Interrupt Controller List Register 1"
bitfld.long 0x00 30.--31. "STATE,Interrupt state" "Inactive,Pending,Active,Pending and active"
bitfld.long 0x00 29. "HW,Virtual interrupt maps directly to a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 28. "GROUP,Group for this virtual interrupt" "Group 0,Group 1"
newline
bitfld.long 0x00 19.--23. "PRIORITY,Priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 9. "EOI,End of interrupt" "Not EOI,EOI"
else
group.long c15:(0x40EC+0x100)++0x00
line.long 0x00 "ICH_LRC1,Interrupt Controller List Register 1"
bitfld.long 0x00 30.--31. "STATE,Interrupt state" "Inactive,Pending,Active,Pending and active"
bitfld.long 0x00 29. "HW,Virtual interrupt maps directly to a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 28. "GROUP,Group for this virtual interrupt" "Group 0,Group 1"
newline
bitfld.long 0x00 19.--23. "PRIORITY,Priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts"
endif
if (((per.l(c15:0x40EC+0x200))&0x20000000)==0x00)
group.long c15:(0x40EC+0x200)++0x00
line.long 0x00 "ICH_LRC2,Interrupt Controller List Register 2"
bitfld.long 0x00 30.--31. "STATE,Interrupt state" "Inactive,Pending,Active,Pending and active"
bitfld.long 0x00 29. "HW,Virtual interrupt maps directly to a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 28. "GROUP,Group for this virtual interrupt" "Group 0,Group 1"
newline
bitfld.long 0x00 19.--23. "PRIORITY,Priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 9. "EOI,End of interrupt" "Not EOI,EOI"
else
group.long c15:(0x40EC+0x200)++0x00
line.long 0x00 "ICH_LRC2,Interrupt Controller List Register 2"
bitfld.long 0x00 30.--31. "STATE,Interrupt state" "Inactive,Pending,Active,Pending and active"
bitfld.long 0x00 29. "HW,Virtual interrupt maps directly to a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 28. "GROUP,Group for this virtual interrupt" "Group 0,Group 1"
newline
bitfld.long 0x00 19.--23. "PRIORITY,Priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts"
endif
if (((per.l(c15:0x40EC+0x300))&0x20000000)==0x00)
group.long c15:(0x40EC+0x300)++0x00
line.long 0x00 "ICH_LRC3,Interrupt Controller List Register 3"
bitfld.long 0x00 30.--31. "STATE,Interrupt state" "Inactive,Pending,Active,Pending and active"
bitfld.long 0x00 29. "HW,Virtual interrupt maps directly to a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 28. "GROUP,Group for this virtual interrupt" "Group 0,Group 1"
newline
bitfld.long 0x00 19.--23. "PRIORITY,Priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 9. "EOI,End of interrupt" "Not EOI,EOI"
else
group.long c15:(0x40EC+0x300)++0x00
line.long 0x00 "ICH_LRC3,Interrupt Controller List Register 3"
bitfld.long 0x00 30.--31. "STATE,Interrupt state" "Inactive,Pending,Active,Pending and active"
bitfld.long 0x00 29. "HW,Virtual interrupt maps directly to a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 28. "GROUP,Group for this virtual interrupt" "Group 0,Group 1"
newline
bitfld.long 0x00 19.--23. "PRIORITY,Priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts"
endif
tree.end
tree.end
tree "Debug Registers"
tree "Coresight Management Registers"
rgroup.long c14:0x0000++0x00
line.long 0x00 "DBGDIDR,Debug ID Register"
bitfld.long 0x00 28.--31. "WRP,Number of watchpoint register pairs" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,8,?..."
bitfld.long 0x00 24.--27. "BRP,Number of breakpoint register pairs" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,8,?..."
newline
bitfld.long 0x00 20.--23. "CTX_CMP,Number of BRPs with context ID comparison capability" "Reserved,2,?..."
bitfld.long 0x00 16.--19. "VERSION,Debug architecture version" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ARMv8,?..."
newline
bitfld.long 0x00 14. "NSUHD_IMP,Secure user halting debug-mode" "Not supported,?..."
bitfld.long 0x00 12. "SE_IMP,Security extensions implemented" "Not implemented,?..."
rgroup.long c14:0x0060++0x00
line.long 0x00 "DBGWFAR,Debug Watchpoint Fault Address Register"
group.long c14:0x0070++0x00
line.long 0x00 "DBGVCR,Debug Vector Catch Register"
bitfld.long 0x00 7. "FIQVCE,FIQ vector catch enable" "Disabled,Enabled"
bitfld.long 0x00 6. "IRQVCE,IRQ vector catch enable" "Disabled,Enabled"
newline
bitfld.long 0x00 4. "DAVCE,Data abort vector catch enable" "Disabled,Enabled"
bitfld.long 0x00 3. "PAVCE,Prefetch abort vector catch enable" "Disabled,Enabled"
newline
bitfld.long 0x00 2. "SVCVCE,Supervisor call (SVC) vector catch enable" "Disabled,Enabled"
bitfld.long 0x00 1. "UIVCE,Undefined instruction vector catch enable" "Disabled,Enabled"
group.long c14:0x0200++0x00
line.long 0x00 "DBGDTRRXEXT,Debug Receive Register (External View)"
rgroup.long c14:0x0050++0x00
line.long 0x00 "DBGDTRRXINT,Debug Receive Register (Internal View)"
group.long c14:0x0020++0x00
line.long 0x00 "DBGDCCINT,Debug Comms Channel Interrupt Enable Register"
bitfld.long 0x00 30. "RX,DCC interrupt enable controls" "Disabled,Enabled"
bitfld.long 0x00 29. "TX,DCC interrupt enable controls" "Disabled,Enabled"
rgroup.long c14:0x0010++0x00
line.long 0x00 "DBGDSCRINT,Debug Status and Control Register (Internal View)"
bitfld.long 0x00 30. "RXFULL,DBGDTRRX register full" "Empty,Full"
bitfld.long 0x00 29. "TXFULL,DBGDTRTX register full" "Empty,Full"
newline
bitfld.long 0x00 18. "NS,Non-secure status bit" "Secure,Non-secure"
bitfld.long 0x00 15. "MDBGEN,Monitor debug-mode enable" "Disabled,Enabled"
newline
bitfld.long 0x00 12. "UDCCDIS,User mode access to communications channel disable" "No,Yes"
bitfld.long 0x00 2.--5. "MOE,Method of debug entry field" "Reserved,Breakpoint,Reserved,Software breakpoint (BKPT),Reserved,Vector catch,Reserved,Reserved,Reserved,Reserved,Watchpoint,?..."
if (((per.l(c14:0x0411))&0x02)==0x02)
group.long c14:0x0220++0x00
line.long 0x00 "DBGDSCREXT,Debug Status and Control Register (External View)"
bitfld.long 0x00 30. "RXFULL,DBGDTRRX register full" "Empty,Full"
bitfld.long 0x00 29. "TXFULL,DBGDTRTX register full" "Empty,Full"
newline
bitfld.long 0x00 27. "RXO,DBGDTRRX overflow" "No overflow,Overflow"
bitfld.long 0x00 26. "TXU,DBGDTRTX underflow" "No underflow,Underflow"
newline
bitfld.long 0x00 22.--23. "INTDIS,Interrupt disable" "Don't disable interrupts,Disable interrupts targeting non-sec EL1,Disable interrupts targeting EL1 & EL2,Disable all interrupts"
bitfld.long 0x00 21. "TDA,Trap debug register access" "Not trapped,Trapped"
newline
rbitfld.long 0x00 18. "NS,Non-secure status bit" "Reserved,Non-secure"
bitfld.long 0x00 15. "MDBGEN,Monitor debug-mode enable" "Disabled,Enabled"
newline
bitfld.long 0x00 14. "HDE,Halting debug-mode" "Disabled,Enabled"
bitfld.long 0x00 12. "UDCCDIS,User mode access to communications channel disable" "No,Yes"
newline
bitfld.long 0x00 6. "ERR,Cummulative error flag" "Not error,Error"
bitfld.long 0x00 2.--5. "MOE,Method of debug entry field" "Reserved,Breakpoint,Reserved,Software breakpoint (BKPT),Reserved,Vector catch,Reserved,Reserved,Reserved,Reserved,Watchpoint,?..."
else
group.long c14:0x0220++0x00
line.long 0x00 "DBGDSCREXT,Debug Status and Control Register (External View)"
rbitfld.long 0x00 30. "RXFULL,DBGDTRRX register full" "Empty,Full"
rbitfld.long 0x00 29. "TXFULL,DBGDTRTX register full" "Empty,Full"
newline
rbitfld.long 0x00 27. "RXO,DBGDTRRX overflow" "No overflow,Overflow"
rbitfld.long 0x00 26. "TXU,DBGDTRTX underflow" "No underflow,Underflow"
newline
rbitfld.long 0x00 22.--23. "INTDIS,Interrupt disable" "Don't disable interrupts,Disable interrupts targeting non-sec EL1,Disable interrupts targeting EL1 & EL2,Disable all interrupts"
rbitfld.long 0x00 21. "TDA,Trap debug register access" "Not trapped,Trapped"
newline
rbitfld.long 0x00 18. "NS,Non-secure status bit" "Reserved,Non-secure"
bitfld.long 0x00 15. "MDBGEN,Monitor debug-mode enable" "Disabled,Enabled"
newline
rbitfld.long 0x00 14. "HDE,Halting debug-mode" "Disabled,Enabled"
bitfld.long 0x00 12. "UDCCDIS,User mode access to communications channel disable" "No,Yes"
newline
rbitfld.long 0x00 6. "ERR,Cummulative error flag" "Not error,Error"
bitfld.long 0x00 2.--5. "MOE,Method of debug entry field" "Reserved,Breakpoint,Reserved,Software breakpoint (BKPT),Reserved,Vector catch,Reserved,Reserved,Reserved,Reserved,Watchpoint,?..."
endif
group.long c14:0x0230++0x00
line.long 0x00 "DBGDTRTXEXT,Debug Transmit Register (External View)"
if (((per.l(c14:0x0411))&0x02)==0x02)
group.long c14:0x0260++0x00
line.long 0x00 "DBGOSECCR,Debug OS Lock Exception Catch Control Register"
else
rgroup.long c14:0x0260++0x00
line.long 0x00 "DBGOSECCR,Debug OS Lock Exception Catch Control Register"
endif
wgroup.long c14:0x0050++0x00
line.long 0x00 "DBGDTRTXINT,Debug Transmit Register (Internal View)"
rgroup.long c14:0x0707++0x00
line.long 0x00 "DBGDEVID2,Debug Device ID Register 2"
rgroup.long c14:0x0717++0x00
line.long 0x00 "DBGDEVID1,Debug Device ID Register 1"
bitfld.long 0x00 0.--3. "PCSROFFSET,PC samples returned offset" "Reserved,Reserved,No offset,?..."
rgroup.long c14:0x0727++0x00
line.long 0x00 "DBGDEVID0,Debug Device ID Register 0"
bitfld.long 0x00 28.--31. "CIDMASK,Level of support for the context ID matching breakpoint masking capability." "Not implemented,?..."
bitfld.long 0x00 24.--27. "AR,Debug external auxiliary control register support status" "Not supported,?..."
newline
bitfld.long 0x00 20.--23. "DL,Support for debug OS double lock register" "Reserved,Supported,?..."
bitfld.long 0x00 16.--19. "VE,Specifies implementation of virtualization extension" "Reserved,Implemented,?..."
newline
bitfld.long 0x00 12.--15. "VC,Form of the vector catch event implemented" "Implemented,?..."
bitfld.long 0x00 8.--11. "BPAM,Level of support for immediate virtual address matching breakpoint masking capability" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Not implemented"
newline
bitfld.long 0x00 4.--7. "WPAM,Level of support for the DVA matching watchpoint masking capability" "Reserved,Implemented,?..."
bitfld.long 0x00 0.--3. "PCS,Level of support for program counter sampling using debug registers 40 and 43" "Reserved,Reserved,Reserved,Implemented,?..."
newline
tree.end
rgroup.long c14:0x0001++0x00
line.long 0x00 "DBGDRAR,Debug ROM Address Register"
hexmask.long 0x00 12.--31. 0x1000 "ROMADDR,ROM physical address"
newline
bitfld.long 0x00 0. "VALID,ROM table address valid" "Not valid,Valid"
rgroup.long c14:0x0002++0x00
line.long 0x00 "DBGDSAR,Debug Self Address Register"
wgroup.long c14:0x0401++0x00
line.long 0x00 "DBGOSLAR,Operating System Lock Access Register"
rgroup.long c14:0x0411++0x00
line.long 0x00 "DBGOSLSR,Operating System Lock Status Register"
bitfld.long 0x00 2. "NTT,32-bit access" "Not required,Required"
bitfld.long 0x00 1. "OSLK,Status of the OS Lock" "Not locked,Locked"
newline
bitfld.long 0x00 0. 3. "OSLM,OS Lock Model implemented Bit" "Reserved,Reserved,Implemented,?..."
group.long c14:0x0431++0x00
line.long 0x00 "DBGOSDLR,OS Double-lock Register"
bitfld.long 0x00 0. "DLK,OS double-lock control" "Not locked,Locked"
group.long c14:0x0441++0x00
line.long 0x00 "DBGPRCR,Device Power-Down and Reset Control Register"
bitfld.long 0x00 0. "CORENPDRQ,Core No Power down Request" "Powered down,Emulated"
group.long c14:0x0687++0x00
line.long 0x00 "DBGCLAIMSET,Debug Claim Tag Set Register"
bitfld.long 0x00 7. "CT7,Claim Tag 7 Set" "Not set,Set"
bitfld.long 0x00 6. "CT6,Claim Tag 6 Set" "Not set,Set"
newline
bitfld.long 0x00 5. "CT5,Claim Tag 5 Set" "Not set,Set"
bitfld.long 0x00 4. "CT4,Claim Tag 4 Set" "Not set,Set"
newline
bitfld.long 0x00 3. "CT3,Claim Tag 3 Set" "Not set,Set"
bitfld.long 0x00 2. "CT2,Claim Tag 2 Set" "Not set,Set"
newline
bitfld.long 0x00 1. "CT1,Claim Tag 1 Set" "Not set,Set"
bitfld.long 0x00 0. "CT0,Claim Tag 0 Set" "Not set,Set"
group.long c14:0x0697++0x00
line.long 0x00 "DBGCLAIMCLR,Debug Claim Tag Clear Register"
bitfld.long 0x00 7. "CT7,Claim Tag 7 Clear" "Not cleared,Cleared"
bitfld.long 0x00 6. "CT6,Claim Tag 6 Clear" "Not cleared,Cleared"
newline
bitfld.long 0x00 5. "CT5,Claim Tag 5 Clear" "Not cleared,Cleared"
bitfld.long 0x00 4. "CT4,Claim Tag 4 Clear" "Not cleared,Cleared"
newline
bitfld.long 0x00 3. "CT3,Claim Tag 3 Clear" "Not cleared,Cleared"
bitfld.long 0x00 2. "CT2,Claim Tag 2 Clear" "Not cleared,Cleared"
newline
bitfld.long 0x00 1. "CT1,Claim Tag 1 Clear" "Not cleared,Cleared"
bitfld.long 0x00 0. "CT0,Claim Tag 0 Clear" "Not cleared,Cleared"
rgroup.long c14:0x06E7++0x00
line.long 0x00 "DBGAUTHSTATUS,Debug Authentication Status Register"
bitfld.long 0x00 10.--11. "HNID,Hyp non-invasive debug" "Reserved,Reserved,Disabled,Enabled"
bitfld.long 0x00 8.--9. "HID,Hyp invasive debug"  "Reserved,Reserved,Disabled,Enabled"
newline
bitfld.long 0x00 6.--7. "SNID,Secure non-invasive debug" "Not implemented,?..."
bitfld.long 0x00 4.--5. "SID,Secure invasive debug" "Not implemented,?..."
newline
bitfld.long 0x00 2.--3. "NSNID,Non-secure non-invasive debug" "Reserved,Reserved,Disabled,Enabled"
bitfld.long 0x00 0.--1. "NSID,Non-secure invasive debug" "Reserved,Reserved,Disabled,Enabled"
rgroup.long c14:0x7000++0x00 "Jazelle Registers"
line.long 0x00 "JIDR,Jazelle ID Register"
rgroup.long c14:0x7001++0x00
line.long 0x00 "JOSCR,Jazelle OS Control Register"
rgroup.long c14:0x7002++0x00
line.long 0x00 "JMCR,Jazelle Main Configuration Register"
tree.end
tree "Breakpoint Registers"
tree "Breakpoint 0"
if (((per.l(c14:0x0500+0x0))&0xA00000)==0x0)
group.long c14:(0x0400+0x0)++0x00
line.long 0x00 "DBGBVR0,Debug Breakpoint Value Register"
hexmask.long 0x0 2.--31. 0x4 "VA,Address Value for comparison bits (31:2)"
elif (((per.l(c14:0x0500+0x0))&0xA00000)==(0xA00000||0x200000))
group.long c14:(0x0400+0x0)++0x00
line.long 0x00 "DBGBVR0,Debug Breakpoint Value Register"
else
rgroup.long c14:(0x0400+0x0)++0x00
line.long 0x00 "DBGBVR0,Debug Breakpoint Value Register"
endif
if ((per.l(c14:0x0500+0x0)&0x2000)==0x2000)
if ((per.l(c14:0x0500+0x0)&0xC000)==(0x0000||0x4000))
group.long c14:(0x0500+0x0)++0x00
line.long 0x00 "DBGBCR0,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
newline
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System/Supervisor,Reserved,User/System/Supervisor"
newline
bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
elif ((per.l(c14:0x0500+0x0)&0xC000)==0x8000)
group.long c14:(0x0500+0x0)++0x00
line.long 0x00 "DBGBCR0,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
newline
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System,Reserved,User/System"
newline
bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
else
group.long c14:(0x0500+0x0)++0x00
line.long 0x00 "DBGBCR0,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
newline
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,?..."
newline
bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
endif
else
group.long c14:(0x0500+0x0)++0x00
line.long 0x00 "DBGBCR0,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
newline
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System,System,User,User/System"
newline
bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
endif
tree.end
tree "Breakpoint 1"
if (((per.l(c14:0x0500+0x10))&0xA00000)==0x0)
group.long c14:(0x0400+0x10)++0x00
line.long 0x00 "DBGBVR1,Debug Breakpoint Value Register"
hexmask.long 0x0 2.--31. 0x4 "VA,Address Value for comparison bits (31:2)"
elif (((per.l(c14:0x0500+0x10))&0xA00000)==(0xA00000||0x200000))
group.long c14:(0x0400+0x10)++0x00
line.long 0x00 "DBGBVR1,Debug Breakpoint Value Register"
else
rgroup.long c14:(0x0400+0x10)++0x00
line.long 0x00 "DBGBVR1,Debug Breakpoint Value Register"
endif
if ((per.l(c14:0x0500+0x10)&0x2000)==0x2000)
if ((per.l(c14:0x0500+0x10)&0xC000)==(0x0000||0x4000))
group.long c14:(0x0500+0x10)++0x00
line.long 0x00 "DBGBCR1,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
newline
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System/Supervisor,Reserved,User/System/Supervisor"
newline
bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
elif ((per.l(c14:0x0500+0x10)&0xC000)==0x8000)
group.long c14:(0x0500+0x10)++0x00
line.long 0x00 "DBGBCR1,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
newline
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System,Reserved,User/System"
newline
bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
else
group.long c14:(0x0500+0x10)++0x00
line.long 0x00 "DBGBCR1,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
newline
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,?..."
newline
bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
endif
else
group.long c14:(0x0500+0x10)++0x00
line.long 0x00 "DBGBCR1,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
newline
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System,System,User,User/System"
newline
bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
endif
tree.end
tree "Breakpoint 2"
if (((per.l(c14:0x0500+0x20))&0xA00000)==0x0)
group.long c14:(0x0400+0x20)++0x00
line.long 0x00 "DBGBVR2,Debug Breakpoint Value Register"
hexmask.long 0x0 2.--31. 0x4 "VA,Address Value for comparison bits (31:2)"
elif (((per.l(c14:0x0500+0x20))&0xA00000)==(0xA00000||0x200000))
group.long c14:(0x0400+0x20)++0x00
line.long 0x00 "DBGBVR2,Debug Breakpoint Value Register"
else
rgroup.long c14:(0x0400+0x20)++0x00
line.long 0x00 "DBGBVR2,Debug Breakpoint Value Register"
endif
if ((per.l(c14:0x0500+0x20)&0x2000)==0x2000)
if ((per.l(c14:0x0500+0x20)&0xC000)==(0x0000||0x4000))
group.long c14:(0x0500+0x20)++0x00
line.long 0x00 "DBGBCR2,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
newline
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System/Supervisor,Reserved,User/System/Supervisor"
newline
bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
elif ((per.l(c14:0x0500+0x20)&0xC000)==0x8000)
group.long c14:(0x0500+0x20)++0x00
line.long 0x00 "DBGBCR2,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
newline
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System,Reserved,User/System"
newline
bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
else
group.long c14:(0x0500+0x20)++0x00
line.long 0x00 "DBGBCR2,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
newline
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,?..."
newline
bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
endif
else
group.long c14:(0x0500+0x20)++0x00
line.long 0x00 "DBGBCR2,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
newline
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System,System,User,User/System"
newline
bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
endif
tree.end
tree "Breakpoint 3"
if (((per.l(c14:0x0500+0x30))&0xA00000)==0x0)
group.long c14:(0x0400+0x30)++0x00
line.long 0x00 "DBGBVR3,Debug Breakpoint Value Register"
hexmask.long 0x0 2.--31. 0x4 "VA,Address Value for comparison bits (31:2)"
elif (((per.l(c14:0x0500+0x30))&0xA00000)==(0xA00000||0x200000))
group.long c14:(0x0400+0x30)++0x00
line.long 0x00 "DBGBVR3,Debug Breakpoint Value Register"
else
rgroup.long c14:(0x0400+0x30)++0x00
line.long 0x00 "DBGBVR3,Debug Breakpoint Value Register"
endif
if ((per.l(c14:0x0500+0x30)&0x2000)==0x2000)
if ((per.l(c14:0x0500+0x30)&0xC000)==(0x0000||0x4000))
group.long c14:(0x0500+0x30)++0x00
line.long 0x00 "DBGBCR3,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
newline
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System/Supervisor,Reserved,User/System/Supervisor"
newline
bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
elif ((per.l(c14:0x0500+0x30)&0xC000)==0x8000)
group.long c14:(0x0500+0x30)++0x00
line.long 0x00 "DBGBCR3,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
newline
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System,Reserved,User/System"
newline
bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
else
group.long c14:(0x0500+0x30)++0x00
line.long 0x00 "DBGBCR3,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
newline
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,?..."
newline
bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
endif
else
group.long c14:(0x0500+0x30)++0x00
line.long 0x00 "DBGBCR3,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
newline
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System,System,User,User/System"
newline
bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
endif
tree.end
tree "Breakpoint 4"
if (((per.l(c14:0x0500+0x40))&0xA00000)==0x0)
group.long c14:(0x0400+0x40)++0x00
line.long 0x00 "DBGBVR4,Debug Breakpoint Value Register"
hexmask.long 0x0 2.--31. 0x4 "VA,Address Value for comparison bits (31:2)"
elif (((per.l(c14:0x0500+0x40))&0xA00000)==(0xA00000||0x200000))
group.long c14:(0x0400+0x40)++0x00
line.long 0x00 "DBGBVR4,Debug Breakpoint Value Register"
else
rgroup.long c14:(0x0400+0x40)++0x00
line.long 0x00 "DBGBVR4,Debug Breakpoint Value Register"
endif
if ((per.l(c14:0x0500+0x40)&0x2000)==0x2000)
if ((per.l(c14:0x0500+0x40)&0xC000)==(0x0000||0x4000))
group.long c14:(0x0500+0x40)++0x00
line.long 0x00 "DBGBCR4,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
newline
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System/Supervisor,Reserved,User/System/Supervisor"
newline
bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
elif ((per.l(c14:0x0500+0x40)&0xC000)==0x8000)
group.long c14:(0x0500+0x40)++0x00
line.long 0x00 "DBGBCR4,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
newline
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System,Reserved,User/System"
newline
bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
else
group.long c14:(0x0500+0x40)++0x00
line.long 0x00 "DBGBCR4,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
newline
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,?..."
newline
bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
endif
else
group.long c14:(0x0500+0x40)++0x00
line.long 0x00 "DBGBCR4,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
newline
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System,System,User,User/System"
newline
bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
endif
tree.end
tree "Breakpoint 5"
if (((per.l(c14:0x0500+0x50))&0xA00000)==0x0)
group.long c14:(0x0400+0x50)++0x00
line.long 0x00 "DBGBVR5,Debug Breakpoint Value Register"
hexmask.long 0x0 2.--31. 0x4 "VA,Address Value for comparison bits (31:2)"
elif (((per.l(c14:0x0500+0x50))&0xA00000)==(0xA00000||0x200000))
group.long c14:(0x0400+0x50)++0x00
line.long 0x00 "DBGBVR5,Debug Breakpoint Value Register"
else
rgroup.long c14:(0x0400+0x50)++0x00
line.long 0x00 "DBGBVR5,Debug Breakpoint Value Register"
endif
if ((per.l(c14:0x0500+0x50)&0x2000)==0x2000)
if ((per.l(c14:0x0500+0x50)&0xC000)==(0x0000||0x4000))
group.long c14:(0x0500+0x50)++0x00
line.long 0x00 "DBGBCR5,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
newline
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System/Supervisor,Reserved,User/System/Supervisor"
newline
bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
elif ((per.l(c14:0x0500+0x50)&0xC000)==0x8000)
group.long c14:(0x0500+0x50)++0x00
line.long 0x00 "DBGBCR5,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
newline
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System,Reserved,User/System"
newline
bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
else
group.long c14:(0x0500+0x50)++0x00
line.long 0x00 "DBGBCR5,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
newline
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,?..."
newline
bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
endif
else
group.long c14:(0x0500+0x50)++0x00
line.long 0x00 "DBGBCR5,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
newline
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System,System,User,User/System"
newline
bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
endif
tree.end
tree "Breakpoint 6"
if (((per.l(c14:0x0500+0x60))&0xA00000)==0x0)
group.long c14:(0x0400+0x60)++0x00
line.long 0x00 "DBGBVR6,Debug Breakpoint Value Register"
hexmask.long 0x0 2.--31. 0x4 "VA,Address Value for comparison bits (31:2)"
elif (((per.l(c14:0x0500+0x60))&0xA00000)==(0xA00000||0x200000))
group.long c14:(0x0400+0x60)++0x00
line.long 0x00 "DBGBVR6,Debug Breakpoint Value Register"
else
rgroup.long c14:(0x0400+0x60)++0x00
line.long 0x00 "DBGBVR6,Debug Breakpoint Value Register"
endif
group.long c14:(0x0101+0x60)++0x00
line.long 0x00 "DBGBXVR6,Breakpoint Extended Value Register"
hexmask.long.byte 0x00 0.--7. 1. "VMID,VMID value for comparison"
if ((per.l(c14:0x0500+0x60)&0x2000)==0x2000)
if ((per.l(c14:0x0500+0x60)&0xC000)==(0x0000||0x4000))
group.long c14:(0x0500+0x60)++0x00
line.long 0x00 "DBGBCR6,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
newline
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System/Supervisor,Reserved,User/System/Supervisor"
newline
bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
elif ((per.l(c14:0x0500+0x60)&0xC000)==0x8000)
group.long c14:(0x0500+0x60)++0x00
line.long 0x00 "DBGBCR6,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
newline
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System,Reserved,User/System"
newline
bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
else
group.long c14:(0x0500+0x60)++0x00
line.long 0x00 "DBGBCR6,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
newline
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,?..."
newline
bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
endif
else
group.long c14:(0x0500+0x60)++0x00
line.long 0x00 "DBGBCR6,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
newline
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System,System,User,User/System"
newline
bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
endif
tree.end
tree "Breakpoint 7"
if (((per.l(c14:0x0500+0x70))&0xA00000)==0x0)
group.long c14:(0x0400+0x70)++0x00
line.long 0x00 "DBGBVR7,Debug Breakpoint Value Register"
hexmask.long 0x0 2.--31. 0x4 "VA,Address Value for comparison bits (31:2)"
elif (((per.l(c14:0x0500+0x70))&0xA00000)==(0xA00000||0x200000))
group.long c14:(0x0400+0x70)++0x00
line.long 0x00 "DBGBVR7,Debug Breakpoint Value Register"
else
rgroup.long c14:(0x0400+0x70)++0x00
line.long 0x00 "DBGBVR7,Debug Breakpoint Value Register"
endif
group.long c14:(0x0101+0x70)++0x00
line.long 0x00 "DBGBXVR7,Breakpoint Extended Value Register"
hexmask.long.byte 0x00 0.--7. 1. "VMID,VMID value for comparison"
if ((per.l(c14:0x0500+0x70)&0x2000)==0x2000)
if ((per.l(c14:0x0500+0x70)&0xC000)==(0x0000||0x4000))
group.long c14:(0x0500+0x70)++0x00
line.long 0x00 "DBGBCR7,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
newline
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System/Supervisor,Reserved,User/System/Supervisor"
newline
bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
elif ((per.l(c14:0x0500+0x70)&0xC000)==0x8000)
group.long c14:(0x0500+0x70)++0x00
line.long 0x00 "DBGBCR7,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
newline
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System,Reserved,User/System"
newline
bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
else
group.long c14:(0x0500+0x70)++0x00
line.long 0x00 "DBGBCR7,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
newline
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,?..."
newline
bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
endif
else
group.long c14:(0x0500+0x70)++0x00
line.long 0x00 "DBGBCR7,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
newline
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System,System,User,User/System"
newline
bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
endif
tree.end
tree.end
tree "Watchpoint Registers"
tree "Watchpoint 0"
group.long c14:(0x0600+0x0)++0x00
line.long 0x00 "DBGWVR0,Watchpoint Value Register"
hexmask.long 0x00 2.--31. 0x4 "VA,Address value"
if ((per.l(c14:0x0700+0x0)&0x2000)==0x2000)
if ((per.l(c14:(0x0700+0x0))&0xC000)==(0x0000||0x4000))
group.long c14:(0x0700+0x0)++0x00
line.long 0x00 "DBGWCR0,Watchpoint Control Register"
bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select"
newline
bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both"
bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System/Supervisor,Reserved,User/System/Supervisor"
bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled"
elif ((per.l(c14:0x0700+0x0)&0xC000)==0x8000)
group.long c14:(0x0700+0x0)++0x00
line.long 0x00 "DBGWCR0,Watchpoint Control Register"
bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select"
newline
bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both"
bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System,Reserved,User/System"
bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled"
else
group.long c14:(0x0700+0x0)++0x00
line.long 0x00 "DBGWCR0,Watchpoint Control Register"
bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select"
newline
bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both"
bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Supervisor,?..."
bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled"
endif
else
group.long c14:(0x0700+0x0)++0x00
line.long 0x00 "DBGWCR0,Watchpoint Control Register"
bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select"
newline
bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both"
bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System,User,User/System"
bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled"
endif
tree.end
tree "Watchpoint 1"
group.long c14:(0x0600+0x10)++0x00
line.long 0x00 "DBGWVR1,Watchpoint Value Register"
hexmask.long 0x00 2.--31. 0x4 "VA,Address value"
if ((per.l(c14:0x0700+0x10)&0x2000)==0x2000)
if ((per.l(c14:(0x0700+0x10))&0xC000)==(0x0000||0x4000))
group.long c14:(0x0700+0x10)++0x00
line.long 0x00 "DBGWCR1,Watchpoint Control Register"
bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select"
newline
bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both"
bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System/Supervisor,Reserved,User/System/Supervisor"
bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled"
elif ((per.l(c14:0x0700+0x10)&0xC000)==0x8000)
group.long c14:(0x0700+0x10)++0x00
line.long 0x00 "DBGWCR1,Watchpoint Control Register"
bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select"
newline
bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both"
bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System,Reserved,User/System"
bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled"
else
group.long c14:(0x0700+0x10)++0x00
line.long 0x00 "DBGWCR1,Watchpoint Control Register"
bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select"
newline
bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both"
bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Supervisor,?..."
bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled"
endif
else
group.long c14:(0x0700+0x10)++0x00
line.long 0x00 "DBGWCR1,Watchpoint Control Register"
bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select"
newline
bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both"
bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System,User,User/System"
bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled"
endif
tree.end
tree "Watchpoint 2"
group.long c14:(0x0600+0x20)++0x00
line.long 0x00 "DBGWVR2,Watchpoint Value Register"
hexmask.long 0x00 2.--31. 0x4 "VA,Address value"
if ((per.l(c14:0x0700+0x20)&0x2000)==0x2000)
if ((per.l(c14:(0x0700+0x20))&0xC000)==(0x0000||0x4000))
group.long c14:(0x0700+0x20)++0x00
line.long 0x00 "DBGWCR2,Watchpoint Control Register"
bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select"
newline
bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both"
bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System/Supervisor,Reserved,User/System/Supervisor"
bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled"
elif ((per.l(c14:0x0700+0x20)&0xC000)==0x8000)
group.long c14:(0x0700+0x20)++0x00
line.long 0x00 "DBGWCR2,Watchpoint Control Register"
bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select"
newline
bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both"
bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System,Reserved,User/System"
bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled"
else
group.long c14:(0x0700+0x20)++0x00
line.long 0x00 "DBGWCR2,Watchpoint Control Register"
bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select"
newline
bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both"
bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Supervisor,?..."
bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled"
endif
else
group.long c14:(0x0700+0x20)++0x00
line.long 0x00 "DBGWCR2,Watchpoint Control Register"
bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select"
newline
bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both"
bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System,User,User/System"
bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled"
endif
tree.end
tree "Watchpoint 3"
group.long c14:(0x0600+0x30)++0x00
line.long 0x00 "DBGWVR3,Watchpoint Value Register"
hexmask.long 0x00 2.--31. 0x4 "VA,Address value"
if ((per.l(c14:0x0700+0x30)&0x2000)==0x2000)
if ((per.l(c14:(0x0700+0x30))&0xC000)==(0x0000||0x4000))
group.long c14:(0x0700+0x30)++0x00
line.long 0x00 "DBGWCR3,Watchpoint Control Register"
bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select"
newline
bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both"
bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System/Supervisor,Reserved,User/System/Supervisor"
bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled"
elif ((per.l(c14:0x0700+0x30)&0xC000)==0x8000)
group.long c14:(0x0700+0x30)++0x00
line.long 0x00 "DBGWCR3,Watchpoint Control Register"
bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select"
newline
bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both"
bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System,Reserved,User/System"
bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled"
else
group.long c14:(0x0700+0x30)++0x00
line.long 0x00 "DBGWCR3,Watchpoint Control Register"
bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select"
newline
bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both"
bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Supervisor,?..."
bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled"
endif
else
group.long c14:(0x0700+0x30)++0x00
line.long 0x00 "DBGWCR3,Watchpoint Control Register"
bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select"
newline
bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both"
bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System,User,User/System"
bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled"
endif
tree.end
tree "Watchpoint 4"
group.long c14:(0x0600+0x40)++0x00
line.long 0x00 "DBGWVR4,Watchpoint Value Register"
hexmask.long 0x00 2.--31. 0x4 "VA,Address value"
if ((per.l(c14:0x0700+0x40)&0x2000)==0x2000)
if ((per.l(c14:(0x0700+0x40))&0xC000)==(0x0000||0x4000))
group.long c14:(0x0700+0x40)++0x00
line.long 0x00 "DBGWCR4,Watchpoint Control Register"
bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select"
newline
bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both"
bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System/Supervisor,Reserved,User/System/Supervisor"
bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled"
elif ((per.l(c14:0x0700+0x40)&0xC000)==0x8000)
group.long c14:(0x0700+0x40)++0x00
line.long 0x00 "DBGWCR4,Watchpoint Control Register"
bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select"
newline
bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both"
bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System,Reserved,User/System"
bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled"
else
group.long c14:(0x0700+0x40)++0x00
line.long 0x00 "DBGWCR4,Watchpoint Control Register"
bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select"
newline
bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both"
bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Supervisor,?..."
bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled"
endif
else
group.long c14:(0x0700+0x40)++0x00
line.long 0x00 "DBGWCR4,Watchpoint Control Register"
bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select"
newline
bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both"
bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System,User,User/System"
bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled"
endif
tree.end
tree "Watchpoint 5"
group.long c14:(0x0600+0x50)++0x00
line.long 0x00 "DBGWVR5,Watchpoint Value Register"
hexmask.long 0x00 2.--31. 0x4 "VA,Address value"
if ((per.l(c14:0x0700+0x50)&0x2000)==0x2000)
if ((per.l(c14:(0x0700+0x50))&0xC000)==(0x0000||0x4000))
group.long c14:(0x0700+0x50)++0x00
line.long 0x00 "DBGWCR5,Watchpoint Control Register"
bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select"
newline
bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both"
bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System/Supervisor,Reserved,User/System/Supervisor"
bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled"
elif ((per.l(c14:0x0700+0x50)&0xC000)==0x8000)
group.long c14:(0x0700+0x50)++0x00
line.long 0x00 "DBGWCR5,Watchpoint Control Register"
bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select"
newline
bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both"
bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System,Reserved,User/System"
bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled"
else
group.long c14:(0x0700+0x50)++0x00
line.long 0x00 "DBGWCR5,Watchpoint Control Register"
bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select"
newline
bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both"
bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Supervisor,?..."
bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled"
endif
else
group.long c14:(0x0700+0x50)++0x00
line.long 0x00 "DBGWCR5,Watchpoint Control Register"
bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select"
newline
bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both"
bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System,User,User/System"
bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled"
endif
tree.end
tree "Watchpoint 6"
group.long c14:(0x0600+0x60)++0x00
line.long 0x00 "DBGWVR6,Watchpoint Value Register"
hexmask.long 0x00 2.--31. 0x4 "VA,Address value"
if ((per.l(c14:0x0700+0x60)&0x2000)==0x2000)
if ((per.l(c14:(0x0700+0x60))&0xC000)==(0x0000||0x4000))
group.long c14:(0x0700+0x60)++0x00
line.long 0x00 "DBGWCR6,Watchpoint Control Register"
bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select"
newline
bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both"
bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System/Supervisor,Reserved,User/System/Supervisor"
bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled"
elif ((per.l(c14:0x0700+0x60)&0xC000)==0x8000)
group.long c14:(0x0700+0x60)++0x00
line.long 0x00 "DBGWCR6,Watchpoint Control Register"
bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select"
newline
bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both"
bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System,Reserved,User/System"
bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled"
else
group.long c14:(0x0700+0x60)++0x00
line.long 0x00 "DBGWCR6,Watchpoint Control Register"
bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select"
newline
bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both"
bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Supervisor,?..."
bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled"
endif
else
group.long c14:(0x0700+0x60)++0x00
line.long 0x00 "DBGWCR6,Watchpoint Control Register"
bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select"
newline
bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both"
bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System,User,User/System"
bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled"
endif
tree.end
tree "Watchpoint 7"
group.long c14:(0x0600+0x70)++0x00
line.long 0x00 "DBGWVR7,Watchpoint Value Register"
hexmask.long 0x00 2.--31. 0x4 "VA,Address value"
if ((per.l(c14:0x0700+0x70)&0x2000)==0x2000)
if ((per.l(c14:(0x0700+0x70))&0xC000)==(0x0000||0x4000))
group.long c14:(0x0700+0x70)++0x00
line.long 0x00 "DBGWCR7,Watchpoint Control Register"
bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select"
newline
bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both"
bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System/Supervisor,Reserved,User/System/Supervisor"
bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled"
elif ((per.l(c14:0x0700+0x70)&0xC000)==0x8000)
group.long c14:(0x0700+0x70)++0x00
line.long 0x00 "DBGWCR7,Watchpoint Control Register"
bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select"
newline
bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both"
bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System,Reserved,User/System"
bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled"
else
group.long c14:(0x0700+0x70)++0x00
line.long 0x00 "DBGWCR7,Watchpoint Control Register"
bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select"
newline
bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both"
bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Supervisor,?..."
bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled"
endif
else
group.long c14:(0x0700+0x70)++0x00
line.long 0x00 "DBGWCR7,Watchpoint Control Register"
bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select"
newline
bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both"
bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System,User,User/System"
bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled"
endif
tree.end
tree.end
AUTOINDENT.OFF
AUTOINDENT.POP
tree.end
endif
autoindent.on center tree
tree "REALTIME_CORE"
base ad:0xF0200000
group.long 0x00++0x03
line.long 0x00 "WBCTLR,WBCTLR is the register to enable the write buffer function"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "EN,Write Buffer Enable" "0: disable write buffer (default),1: enable write buffer"
group.long 0x200++0x03
line.long 0x00 "WBIMSKR,WBIMSKR is the register to enable interrupt when bus error is detected"
hexmask.long 0x00 2.--31. 1. "Reserved_2,Reserved These bits are always read as 0"
bitfld.long 0x00 1. "DECERR,DECERR interrupt mask" "0: enable interrupt (default),1: disable interrupt"
newline
bitfld.long 0x00 0. "SLVERR,SLVERR interrupt mask" "0: enable interrupt (default),1: disable interrupt"
group.long 0x204++0x03
line.long 0x00 "WBIMSKSTSR,WBIMSKSTSR is the register to hold the error status after being masked by WBIMSKR"
hexmask.long 0x00 2.--31. 1. "Reserved_2,Reserved These bits are always read as 0"
rbitfld.long 0x00 1. "DECERRSTS,DECERR interrupt status" "0: interrupt is not asserted or is being masked,1: interrupt is asserted"
newline
rbitfld.long 0x00 0. "SLVERRSTS,SLVERR interrupt status" "0: interrupt is not asserted or is being masked,1: interrupt is asserted"
group.long 0x208++0x03
line.long 0x00 "WBERRSTSR,WBERRSTSR is the register to hold the error status before being masked by WBIMSKR"
hexmask.long 0x00 2.--31. 1. "Reserved_2,Reserved These bits are always read as 0"
rbitfld.long 0x00 1. "DECERRSTS,DECERR status" "0: no DECERR happened,1: DECERR happened"
newline
rbitfld.long 0x00 0. "SLVERRSTS,SLVERR status" "0: no SLVERR happened,1: SLVERR happened"
group.long 0x20C++0x03
line.long 0x00 "WBICLRR,WBICLRR is the register to clear error status"
hexmask.long 0x00 2.--31. 1. "Reserved_2,Reserved These bits are always read as 0"
bitfld.long 0x00 1. "DECERR,Clear DECERR interrupt status Writing 0 to this bit is ignored Writing 1 to this bit clears DECERR interrupt status Read value is not guaranteed" "0,1"
newline
bitfld.long 0x00 0. "SLVERR,Clear SLVERR interrupt status Writing 0 to this bit is ignored Writing 1 to this bit clears SLVERR interrupt status Read value is not guaranteed" "0,1"
group.long 0x210++0x03
line.long 0x00 "WBSERRADDR,WBSERRADDR is the register to hold the address at which SLVERR is detected"
hexmask.long 0x00 7.--31. 1. "Slave_Error_Address,Error address"
hexmask.long.byte 0x00 0.--6. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x214++0x03
line.long 0x00 "WBDERRADDR,WBDERRADDR is the register to hold the address at which DECERR is detected"
hexmask.long 0x00 7.--31. 1. "Decode_Error_Address,Error address"
hexmask.long.byte 0x00 0.--6. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x730++0x03
line.long 0x00 "WBSYNCR,WBSYNCR is the register to execute memory barrier operation accompanied with the data eviction from write buffer"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "SYNC,Enable memory barrier Writing 0 to this bit is ignored Writing 1 to this bit enable memory barrier" "0,1"
group.long 0xF80++0x03
line.long 0x00 "WBPWRCTLR,WBPWRCTLR is the register to control the dynamic module stop function"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "DMSEN,Enable dynamic module stop" "0: disable (default),1: enable"
tree.end
tree "PFC_GPIO"
tree "PFC_GPIO_FOR_GP0"
base ad:0xE6050000
group.long 0x00++0x03
line.long 0x00 "PMMR0_B0A0,PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers"
hexmask.long 0x00 0.--31. 1. "PMMR_31_0,Multiplexed Pin Setting Mask Writing a value to any register from among the GPSR IPSR DRVCTRL TDSEL POC PUEN PUD MODSEL DMPR PSER PSSR PINV PIS registers is enabled by writing the inverse of the value to this register"
group.long 0x04++0x03
line.long 0x00 "PMMER0_B0A0,PMMERn / PMMERSYS performs enables / disables control of the PMMR"
abitfld.long 0x00 0.--31. "PMMER_31_0,Multiplexed Pin Setting Mask Enable" "0x00000000=0: PMMR function is disabled,0x00000001=1: PMMR function is enabled"
group.long 0x20++0x03
line.long 0x00 "DM0PR0_B0A0,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM0PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x24++0x03
line.long 0x00 "DM1PR0_B0A0,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM1PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x28++0x03
line.long 0x00 "DM2PR0_B0A0,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM2PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x2C++0x03
line.long 0x00 "DM3PR0_B0A0,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM3PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x40++0x03
line.long 0x00 "GPSR0_B0A0,GPSRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "GPSR_31_0,"
group.long 0x60++0x03
line.long 0x00 "IP0SR0_B0A0,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP0SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x64++0x03
line.long 0x00 "IP1SR0_B0A0,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP1SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x68++0x03
line.long 0x00 "IP2SR0_B0A0,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP2SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x80++0x03
line.long 0x00 "DRV0CTRL0_B0A0,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV0CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x84++0x03
line.long 0x00 "DRV1CTRL0_B0A0,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV1CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x88++0x03
line.long 0x00 "DRV2CTRL0_B0A0,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV2CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0xA0++0x03
line.long 0x00 "POC0_B0A0,Each bit in POCn / POCSYS must be set according to IO voltage level that is supplied to the pin"
abitfld.long 0x00 0.--31. "POC_31_0,- For 1.8V/3.3 V" "0x00000000=0: 2.5V,0x00000001=1: 3.3V"
group.long 0xC0++0x03
line.long 0x00 "PUEN0_B0A0,PUENn / PUENSYS performs on / off control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUEN_31_0,"
group.long 0xE0++0x03
line.long 0x00 "PUD0_B0A0,PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUD_31_0,"
group.long 0x160++0x03
line.long 0x00 "PSER0_B0A0,The register (PSERn) to enable / disable PSS Rregister"
hexmask.long 0x00 0.--31. 1. "PSER_31_0,"
group.long 0x164++0x03
line.long 0x00 "PS0SR0_B0A0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS0SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x168++0x03
line.long 0x00 "PS1SR0_B0A0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS1SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x180++0x03
line.long 0x00 "IOINTSEL0_B0A0,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group"
abitfld.long 0x00 0.--31. "IOINTSEL_31_0,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input/output mode,0x00000001=1: Interrupt input mode"
group.long 0x184++0x03
line.long 0x00 "INOUTSEL0_B0A0,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INOUTSEL_31_0,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input mode,0x00000001=1: General output mode"
group.long 0x188++0x03
line.long 0x00 "OUTDT0_B0A0,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDT_31_0,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL" "0x00000000=0: 0 is output,0x00000001=1: 1 is output"
group.long 0x18C++0x03
line.long 0x00 "INDT0_B0A0,INDTn is a register that can read the status of General-Purpose Input / Output Ports"
abitfld.long 0x00 0.--31. "INDT_31_0,Each bit reflects the value received through the corresponding port pin" "0x00000000=0: Input is 0,0x00000001=1: Input is 1"
group.long 0x190++0x03
line.long 0x00 "INTDT0_B0A0,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INTDT_31_0,Each bit indicates the input of an interrupt signal on the corresponding port pin" "0x00000000=0: No interrupt signal has been input,0x00000001=1: Interrupt signal has been input"
group.long 0x194++0x03
line.long 0x00 "INTCLR0_B0A0,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).."
abitfld.long 0x00 0.--31. "INTCLR_31_0,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register" "0x00000000=0: No effect,0x00000001=1: Interrupt display"
group.long 0x198++0x03
line.long 0x00 "INTMSK0_B0A0,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch"
abitfld.long 0x00 0.--31. "INTMSK_31_0,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block" "0x00000000=0: Interrupt is masked,0x00000001=1: Interrupt is not masked"
group.long 0x19C++0x03
line.long 0x00 "MSKCLR0_B0A0,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A"
abitfld.long 0x00 0.--31. "MSKCLR_31_0,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block" "0x00000000=0: No effect,0x00000001=1: Interrupt is not masked"
group.long 0x1A0++0x03
line.long 0x00 "POSNEG0_B0A0,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode general output mode or interrupt input mode"
abitfld.long 0x00 0.--31. "POSNEG_31_0,Selects the polarity (positive or negative logic) of each port pin" "0x00000000=0: Positive logic,0x00000001=1: Negative logic"
group.long 0x1A4++0x03
line.long 0x00 "EDGLEVEL0_B0A0,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "EDGLEVEL_31_0,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected" "0x00000000=0: Level,0x00000001=1: Edge"
group.long 0x1A8++0x03
line.long 0x00 "FILONOFF0_B0A0,FILONOFFn prevents chattering input to the port pins of each GPIO group"
abitfld.long 0x00 0.--31. "FILONOFF_31_0,Enables or disables the chattering prevention function" "0x00000000=0: Chattering prevention function is..,0x00000001=1: Chattering prevention function is.."
group.long 0x1AC++0x03
line.long 0x00 "FILCLKSEL0_B0A0,FILCLKSELn controls the division ratio of clock CP? for prevent chattering input to the port pin GPIO group"
hexmask.long 0x00 0.--31. 1. "FILCLKSEL_31_0,Set the division ratio of filter CLOCK"
group.long 0x1C0++0x03
line.long 0x00 "OUTDTSEL0_B0A0,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDTSEL_31_0,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn" "0x00000000=0: General output register is used to..,0x00000001=1: Output data high register and.."
group.long 0x1C4++0x03
line.long 0x00 "OUTDTH0_B0A0,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTH_31_0,Outputting high value data" "0x00000000=0: Invalid data,0x00000001=1: Valid data"
group.long 0x1C8++0x03
line.long 0x00 "OUTDTL0_B0A0,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTL_31_0,Outputting low value data" "0x00000000=0: Valid data,0x00000001=1: Invalid data"
group.long 0x1CC++0x03
line.long 0x00 "BOTHEDGE0_B0A0,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers"
abitfld.long 0x00 0.--31. "BOTHEDGE_31_0,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected" "0x00000000=0: One edge,0x00000001=1: Both edges"
group.long 0x1D0++0x03
line.long 0x00 "INEN0_B0A0,Create registers that can control IE in GPIO"
hexmask.long 0x00 0.--31. 1. "INEN_31_0,"
group.long 0x200++0x03
line.long 0x00 "PMMR0_B0A1,PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers"
hexmask.long 0x00 0.--31. 1. "PMMR_31_0,Multiplexed Pin Setting Mask Writing a value to any register from among the GPSR IPSR DRVCTRL TDSEL POC PUEN PUD MODSEL DMPR PSER PSSR PINV PIS registers is enabled by writing the inverse of the value to this register"
group.long 0x204++0x03
line.long 0x00 "PMMER0_B0A1,PMMERn / PMMERSYS performs enables / disables control of the PMMR"
abitfld.long 0x00 0.--31. "PMMER_31_0,Multiplexed Pin Setting Mask Enable" "0x00000000=0: PMMR function is disabled,0x00000001=1: PMMR function is enabled"
group.long 0x220++0x03
line.long 0x00 "DM0PR0_B0A1,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM0PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x224++0x03
line.long 0x00 "DM1PR0_B0A1,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM1PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x228++0x03
line.long 0x00 "DM2PR0_B0A1,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM2PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x22C++0x03
line.long 0x00 "DM3PR0_B0A1,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM3PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x240++0x03
line.long 0x00 "GPSR0_B0A1,GPSRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "GPSR_31_0,"
group.long 0x260++0x03
line.long 0x00 "IP0SR0_B0A1,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP0SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x264++0x03
line.long 0x00 "IP1SR0_B0A1,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP1SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x268++0x03
line.long 0x00 "IP2SR0_B0A1,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP2SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x280++0x03
line.long 0x00 "DRV0CTRL0_B0A1,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV0CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x284++0x03
line.long 0x00 "DRV1CTRL0_B0A1,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV1CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x288++0x03
line.long 0x00 "DRV2CTRL0_B0A1,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV2CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x2A0++0x03
line.long 0x00 "POC0_B0A1,Each bit in POCn / POCSYS must be set according to IO voltage level that is supplied to the pin"
abitfld.long 0x00 0.--31. "POC_31_0,- For 1.8V/3.3 V" "0x00000000=0: 2.5V,0x00000001=1: 3.3V"
group.long 0x2C0++0x03
line.long 0x00 "PUEN0_B0A1,PUENn / PUENSYS performs on / off control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUEN_31_0,"
group.long 0x2E0++0x03
line.long 0x00 "PUD0_B0A1,PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUD_31_0,"
group.long 0x360++0x03
line.long 0x00 "PSER0_B0A1,The register (PSERn) to enable / disable PSS Rregister"
hexmask.long 0x00 0.--31. 1. "PSER_31_0,"
group.long 0x364++0x03
line.long 0x00 "PS0SR0_B0A1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS0SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x368++0x03
line.long 0x00 "PS1SR0_B0A1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS1SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x380++0x03
line.long 0x00 "IOINTSEL0_B0A1,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group"
abitfld.long 0x00 0.--31. "IOINTSEL_31_0,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input/output mode,0x00000001=1: Interrupt input mode"
group.long 0x384++0x03
line.long 0x00 "INOUTSEL0_B0A1,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INOUTSEL_31_0,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input mode,0x00000001=1: General output mode"
group.long 0x388++0x03
line.long 0x00 "OUTDT0_B0A1,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDT_31_0,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL" "0x00000000=0: 0 is output,0x00000001=1: 1 is output"
group.long 0x38C++0x03
line.long 0x00 "INDT0_B0A1,INDTn is a register that can read the status of General-Purpose Input / Output Ports"
abitfld.long 0x00 0.--31. "INDT_31_0,Each bit reflects the value received through the corresponding port pin" "0x00000000=0: Input is 0,0x00000001=1: Input is 1"
group.long 0x390++0x03
line.long 0x00 "INTDT0_B0A1,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INTDT_31_0,Each bit indicates the input of an interrupt signal on the corresponding port pin" "0x00000000=0: No interrupt signal has been input,0x00000001=1: Interrupt signal has been input"
group.long 0x394++0x03
line.long 0x00 "INTCLR0_B0A1,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).."
abitfld.long 0x00 0.--31. "INTCLR_31_0,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register" "0x00000000=0: No effect,0x00000001=1: Interrupt display"
group.long 0x398++0x03
line.long 0x00 "INTMSK0_B0A1,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch"
abitfld.long 0x00 0.--31. "INTMSK_31_0,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block" "0x00000000=0: Interrupt is masked,0x00000001=1: Interrupt is not masked"
group.long 0x39C++0x03
line.long 0x00 "MSKCLR0_B0A1,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A"
abitfld.long 0x00 0.--31. "MSKCLR_31_0,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block" "0x00000000=0: No effect,0x00000001=1: Interrupt is not masked"
group.long 0x3A0++0x03
line.long 0x00 "POSNEG0_B0A1,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode general output mode or interrupt input mode"
abitfld.long 0x00 0.--31. "POSNEG_31_0,Selects the polarity (positive or negative logic) of each port pin" "0x00000000=0: Positive logic,0x00000001=1: Negative logic"
group.long 0x3A4++0x03
line.long 0x00 "EDGLEVEL0_B0A1,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "EDGLEVEL_31_0,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected" "0x00000000=0: Level,0x00000001=1: Edge"
group.long 0x3A8++0x03
line.long 0x00 "FILONOFF0_B0A1,FILONOFFn prevents chattering input to the port pins of each GPIO group"
abitfld.long 0x00 0.--31. "FILONOFF_31_0,Enables or disables the chattering prevention function" "0x00000000=0: Chattering prevention function is..,0x00000001=1: Chattering prevention function is.."
group.long 0x3AC++0x03
line.long 0x00 "FILCLKSEL0_B0A1,FILCLKSELn controls the division ratio of clock CP? for prevent chattering input to the port pin GPIO group"
hexmask.long 0x00 0.--31. 1. "FILCLKSEL_31_0,Set the division ratio of filter CLOCK"
group.long 0x3C0++0x03
line.long 0x00 "OUTDTSEL0_B0A1,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDTSEL_31_0,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn" "0x00000000=0: General output register is used to..,0x00000001=1: Output data high register and.."
group.long 0x3C4++0x03
line.long 0x00 "OUTDTH0_B0A1,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTH_31_0,Outputting high value data" "0x00000000=0: Invalid data,0x00000001=1: Valid data"
group.long 0x3C8++0x03
line.long 0x00 "OUTDTL0_B0A1,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTL_31_0,Outputting low value data" "0x00000000=0: Valid data,0x00000001=1: Invalid data"
group.long 0x3CC++0x03
line.long 0x00 "BOTHEDGE0_B0A1,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers"
abitfld.long 0x00 0.--31. "BOTHEDGE_31_0,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected" "0x00000000=0: One edge,0x00000001=1: Both edges"
group.long 0x3D0++0x03
line.long 0x00 "INEN0_B0A1,Create registers that can control IE in GPIO"
hexmask.long 0x00 0.--31. 1. "INEN_31_0,"
group.long 0x400++0x03
line.long 0x00 "PMMR0_B0A2,PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers"
hexmask.long 0x00 0.--31. 1. "PMMR_31_0,Multiplexed Pin Setting Mask Writing a value to any register from among the GPSR IPSR DRVCTRL TDSEL POC PUEN PUD MODSEL DMPR PSER PSSR PINV PIS registers is enabled by writing the inverse of the value to this register"
group.long 0x404++0x03
line.long 0x00 "PMMER0_B0A2,PMMERn / PMMERSYS performs enables / disables control of the PMMR"
abitfld.long 0x00 0.--31. "PMMER_31_0,Multiplexed Pin Setting Mask Enable" "0x00000000=0: PMMR function is disabled,0x00000001=1: PMMR function is enabled"
group.long 0x420++0x03
line.long 0x00 "DM0PR0_B0A2,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM0PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x424++0x03
line.long 0x00 "DM1PR0_B0A2,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM1PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x428++0x03
line.long 0x00 "DM2PR0_B0A2,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM2PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x42C++0x03
line.long 0x00 "DM3PR0_B0A2,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM3PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x440++0x03
line.long 0x00 "GPSR0_B0A2,GPSRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "GPSR_31_0,"
group.long 0x460++0x03
line.long 0x00 "IP0SR0_B0A2,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP0SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x464++0x03
line.long 0x00 "IP1SR0_B0A2,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP1SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x468++0x03
line.long 0x00 "IP2SR0_B0A2,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP2SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x480++0x03
line.long 0x00 "DRV0CTRL0_B0A2,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV0CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x484++0x03
line.long 0x00 "DRV1CTRL0_B0A2,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV1CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x488++0x03
line.long 0x00 "DRV2CTRL0_B0A2,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV2CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x4A0++0x03
line.long 0x00 "POC0_B0A2,Each bit in POCn / POCSYS must be set according to IO voltage level that is supplied to the pin"
abitfld.long 0x00 0.--31. "POC_31_0,- For 1.8V/3.3 V" "0x00000000=0: 2.5V,0x00000001=1: 3.3V"
group.long 0x4C0++0x03
line.long 0x00 "PUEN0_B0A2,PUENn / PUENSYS performs on / off control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUEN_31_0,"
group.long 0x4E0++0x03
line.long 0x00 "PUD0_B0A2,PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUD_31_0,"
group.long 0x560++0x03
line.long 0x00 "PSER0_B0A2,The register (PSERn) to enable / disable PSS Rregister"
hexmask.long 0x00 0.--31. 1. "PSER_31_0,"
group.long 0x564++0x03
line.long 0x00 "PS0SR0_B0A2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS0SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x568++0x03
line.long 0x00 "PS1SR0_B0A2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS1SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x580++0x03
line.long 0x00 "IOINTSEL0_B0A2,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group"
abitfld.long 0x00 0.--31. "IOINTSEL_31_0,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input/output mode,0x00000001=1: Interrupt input mode"
group.long 0x584++0x03
line.long 0x00 "INOUTSEL0_B0A2,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INOUTSEL_31_0,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input mode,0x00000001=1: General output mode"
group.long 0x588++0x03
line.long 0x00 "OUTDT0_B0A2,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDT_31_0,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL" "0x00000000=0: 0 is output,0x00000001=1: 1 is output"
group.long 0x58C++0x03
line.long 0x00 "INDT0_B0A2,INDTn is a register that can read the status of General-Purpose Input / Output Ports"
abitfld.long 0x00 0.--31. "INDT_31_0,Each bit reflects the value received through the corresponding port pin" "0x00000000=0: Input is 0,0x00000001=1: Input is 1"
group.long 0x590++0x03
line.long 0x00 "INTDT0_B0A2,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INTDT_31_0,Each bit indicates the input of an interrupt signal on the corresponding port pin" "0x00000000=0: No interrupt signal has been input,0x00000001=1: Interrupt signal has been input"
group.long 0x594++0x03
line.long 0x00 "INTCLR0_B0A2,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).."
abitfld.long 0x00 0.--31. "INTCLR_31_0,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register" "0x00000000=0: No effect,0x00000001=1: Interrupt display"
group.long 0x598++0x03
line.long 0x00 "INTMSK0_B0A2,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch"
abitfld.long 0x00 0.--31. "INTMSK_31_0,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block" "0x00000000=0: Interrupt is masked,0x00000001=1: Interrupt is not masked"
group.long 0x59C++0x03
line.long 0x00 "MSKCLR0_B0A2,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A"
abitfld.long 0x00 0.--31. "MSKCLR_31_0,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block" "0x00000000=0: No effect,0x00000001=1: Interrupt is not masked"
group.long 0x5A0++0x03
line.long 0x00 "POSNEG0_B0A2,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode general output mode or interrupt input mode"
abitfld.long 0x00 0.--31. "POSNEG_31_0,Selects the polarity (positive or negative logic) of each port pin" "0x00000000=0: Positive logic,0x00000001=1: Negative logic"
group.long 0x5A4++0x03
line.long 0x00 "EDGLEVEL0_B0A2,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "EDGLEVEL_31_0,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected" "0x00000000=0: Level,0x00000001=1: Edge"
group.long 0x5A8++0x03
line.long 0x00 "FILONOFF0_B0A2,FILONOFFn prevents chattering input to the port pins of each GPIO group"
abitfld.long 0x00 0.--31. "FILONOFF_31_0,Enables or disables the chattering prevention function" "0x00000000=0: Chattering prevention function is..,0x00000001=1: Chattering prevention function is.."
group.long 0x5AC++0x03
line.long 0x00 "FILCLKSEL0_B0A2,FILCLKSELn controls the division ratio of clock CP? for prevent chattering input to the port pin GPIO group"
hexmask.long 0x00 0.--31. 1. "FILCLKSEL_31_0,Set the division ratio of filter CLOCK"
group.long 0x5C0++0x03
line.long 0x00 "OUTDTSEL0_B0A2,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDTSEL_31_0,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn" "0x00000000=0: General output register is used to..,0x00000001=1: Output data high register and.."
group.long 0x5C4++0x03
line.long 0x00 "OUTDTH0_B0A2,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTH_31_0,Outputting high value data" "0x00000000=0: Invalid data,0x00000001=1: Valid data"
group.long 0x5C8++0x03
line.long 0x00 "OUTDTL0_B0A2,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTL_31_0,Outputting low value data" "0x00000000=0: Valid data,0x00000001=1: Invalid data"
group.long 0x5CC++0x03
line.long 0x00 "BOTHEDGE0_B0A2,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers"
abitfld.long 0x00 0.--31. "BOTHEDGE_31_0,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected" "0x00000000=0: One edge,0x00000001=1: Both edges"
group.long 0x5D0++0x03
line.long 0x00 "INEN0_B0A2,Create registers that can control IE in GPIO"
hexmask.long 0x00 0.--31. 1. "INEN_31_0,"
group.long 0x2000++0x03
line.long 0x00 "PMMR0_B1A0,PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers"
hexmask.long 0x00 0.--31. 1. "PMMR_31_0,Multiplexed Pin Setting Mask Writing a value to any register from among the GPSR IPSR DRVCTRL TDSEL POC PUEN PUD MODSEL DMPR PSER PSSR PINV PIS registers is enabled by writing the inverse of the value to this register"
group.long 0x2004++0x03
line.long 0x00 "PMMER0_B1A0,PMMERn / PMMERSYS performs enables / disables control of the PMMR"
abitfld.long 0x00 0.--31. "PMMER_31_0,Multiplexed Pin Setting Mask Enable" "0x00000000=0: PMMR function is disabled,0x00000001=1: PMMR function is enabled"
group.long 0x2020++0x03
line.long 0x00 "DM0PR0_B1A0,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM0PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x2024++0x03
line.long 0x00 "DM1PR0_B1A0,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM1PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x2028++0x03
line.long 0x00 "DM2PR0_B1A0,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM2PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x202C++0x03
line.long 0x00 "DM3PR0_B1A0,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM3PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x2040++0x03
line.long 0x00 "GPSR0_B1A0,GPSRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "GPSR_31_0,"
group.long 0x2060++0x03
line.long 0x00 "IP0SR0_B1A0,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP0SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x2064++0x03
line.long 0x00 "IP1SR0_B1A0,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP1SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x2068++0x03
line.long 0x00 "IP2SR0_B1A0,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP2SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x2080++0x03
line.long 0x00 "DRV0CTRL0_B1A0,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV0CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x2084++0x03
line.long 0x00 "DRV1CTRL0_B1A0,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV1CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x2088++0x03
line.long 0x00 "DRV2CTRL0_B1A0,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV2CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x20A0++0x03
line.long 0x00 "POC0_B1A0,Each bit in POCn / POCSYS must be set according to IO voltage level that is supplied to the pin"
abitfld.long 0x00 0.--31. "POC_31_0,- For 1.8V/3.3 V" "0x00000000=0: 2.5V,0x00000001=1: 3.3V"
group.long 0x20C0++0x03
line.long 0x00 "PUEN0_B1A0,PUENn / PUENSYS performs on / off control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUEN_31_0,"
group.long 0x20E0++0x03
line.long 0x00 "PUD0_B1A0,PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUD_31_0,"
group.long 0x2160++0x03
line.long 0x00 "PSER0_B1A0,The register (PSERn) to enable / disable PSS Rregister"
hexmask.long 0x00 0.--31. 1. "PSER_31_0,"
group.long 0x2164++0x03
line.long 0x00 "PS0SR0_B1A0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS0SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x2168++0x03
line.long 0x00 "PS1SR0_B1A0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS1SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x2180++0x03
line.long 0x00 "IOINTSEL0_B1A0,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group"
abitfld.long 0x00 0.--31. "IOINTSEL_31_0,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input/output mode,0x00000001=1: Interrupt input mode"
group.long 0x2184++0x03
line.long 0x00 "INOUTSEL0_B1A0,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INOUTSEL_31_0,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input mode,0x00000001=1: General output mode"
group.long 0x2188++0x03
line.long 0x00 "OUTDT0_B1A0,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDT_31_0,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL" "0x00000000=0: 0 is output,0x00000001=1: 1 is output"
group.long 0x218C++0x03
line.long 0x00 "INDT0_B1A0,INDTn is a register that can read the status of General-Purpose Input / Output Ports"
abitfld.long 0x00 0.--31. "INDT_31_0,Each bit reflects the value received through the corresponding port pin" "0x00000000=0: Input is 0,0x00000001=1: Input is 1"
group.long 0x2190++0x03
line.long 0x00 "INTDT0_B1A0,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INTDT_31_0,Each bit indicates the input of an interrupt signal on the corresponding port pin" "0x00000000=0: No interrupt signal has been input,0x00000001=1: Interrupt signal has been input"
group.long 0x2194++0x03
line.long 0x00 "INTCLR0_B1A0,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).."
abitfld.long 0x00 0.--31. "INTCLR_31_0,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register" "0x00000000=0: No effect,0x00000001=1: Interrupt display"
group.long 0x2198++0x03
line.long 0x00 "INTMSK0_B1A0,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch"
abitfld.long 0x00 0.--31. "INTMSK_31_0,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block" "0x00000000=0: Interrupt is masked,0x00000001=1: Interrupt is not masked"
group.long 0x219C++0x03
line.long 0x00 "MSKCLR0_B1A0,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A"
abitfld.long 0x00 0.--31. "MSKCLR_31_0,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block" "0x00000000=0: No effect,0x00000001=1: Interrupt is not masked"
group.long 0x21A0++0x03
line.long 0x00 "POSNEG0_B1A0,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode general output mode or interrupt input mode"
abitfld.long 0x00 0.--31. "POSNEG_31_0,Selects the polarity (positive or negative logic) of each port pin" "0x00000000=0: Positive logic,0x00000001=1: Negative logic"
group.long 0x21A4++0x03
line.long 0x00 "EDGLEVEL0_B1A0,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "EDGLEVEL_31_0,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected" "0x00000000=0: Level,0x00000001=1: Edge"
group.long 0x21A8++0x03
line.long 0x00 "FILONOFF0_B1A0,FILONOFFn prevents chattering input to the port pins of each GPIO group"
abitfld.long 0x00 0.--31. "FILONOFF_31_0,Enables or disables the chattering prevention function" "0x00000000=0: Chattering prevention function is..,0x00000001=1: Chattering prevention function is.."
group.long 0x21AC++0x03
line.long 0x00 "FILCLKSEL0_B1A0,FILCLKSELn controls the division ratio of clock CP? for prevent chattering input to the port pin GPIO group"
hexmask.long 0x00 0.--31. 1. "FILCLKSEL_31_0,Set the division ratio of filter CLOCK"
group.long 0x21C0++0x03
line.long 0x00 "OUTDTSEL0_B1A0,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDTSEL_31_0,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn" "0x00000000=0: General output register is used to..,0x00000001=1: Output data high register and.."
group.long 0x21C4++0x03
line.long 0x00 "OUTDTH0_B1A0,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTH_31_0,Outputting high value data" "0x00000000=0: Invalid data,0x00000001=1: Valid data"
group.long 0x21C8++0x03
line.long 0x00 "OUTDTL0_B1A0,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTL_31_0,Outputting low value data" "0x00000000=0: Valid data,0x00000001=1: Invalid data"
group.long 0x21CC++0x03
line.long 0x00 "BOTHEDGE0_B1A0,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers"
abitfld.long 0x00 0.--31. "BOTHEDGE_31_0,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected" "0x00000000=0: One edge,0x00000001=1: Both edges"
group.long 0x21D0++0x03
line.long 0x00 "INEN0_B1A0,Create registers that can control IE in GPIO"
hexmask.long 0x00 0.--31. 1. "INEN_31_0,"
group.long 0x2200++0x03
line.long 0x00 "PMMR0_B1A1,PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers"
hexmask.long 0x00 0.--31. 1. "PMMR_31_0,Multiplexed Pin Setting Mask Writing a value to any register from among the GPSR IPSR DRVCTRL TDSEL POC PUEN PUD MODSEL DMPR PSER PSSR PINV PIS registers is enabled by writing the inverse of the value to this register"
group.long 0x2204++0x03
line.long 0x00 "PMMER0_B1A1,PMMERn / PMMERSYS performs enables / disables control of the PMMR"
abitfld.long 0x00 0.--31. "PMMER_31_0,Multiplexed Pin Setting Mask Enable" "0x00000000=0: PMMR function is disabled,0x00000001=1: PMMR function is enabled"
group.long 0x2220++0x03
line.long 0x00 "DM0PR0_B1A1,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM0PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x2224++0x03
line.long 0x00 "DM1PR0_B1A1,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM1PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x2228++0x03
line.long 0x00 "DM2PR0_B1A1,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM2PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x222C++0x03
line.long 0x00 "DM3PR0_B1A1,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM3PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x2240++0x03
line.long 0x00 "GPSR0_B1A1,GPSRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "GPSR_31_0,"
group.long 0x2260++0x03
line.long 0x00 "IP0SR0_B1A1,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP0SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x2264++0x03
line.long 0x00 "IP1SR0_B1A1,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP1SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x2268++0x03
line.long 0x00 "IP2SR0_B1A1,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP2SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x2280++0x03
line.long 0x00 "DRV0CTRL0_B1A1,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV0CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x2284++0x03
line.long 0x00 "DRV1CTRL0_B1A1,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV1CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x2288++0x03
line.long 0x00 "DRV2CTRL0_B1A1,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV2CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x22A0++0x03
line.long 0x00 "POC0_B1A1,Each bit in POCn / POCSYS must be set according to IO voltage level that is supplied to the pin"
abitfld.long 0x00 0.--31. "POC_31_0,- For 1.8V/3.3 V" "0x00000000=0: 2.5V,0x00000001=1: 3.3V"
group.long 0x22C0++0x03
line.long 0x00 "PUEN0_B1A1,PUENn / PUENSYS performs on / off control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUEN_31_0,"
group.long 0x22E0++0x03
line.long 0x00 "PUD0_B1A1,PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUD_31_0,"
group.long 0x2360++0x03
line.long 0x00 "PSER0_B1A1,The register (PSERn) to enable / disable PSS Rregister"
hexmask.long 0x00 0.--31. 1. "PSER_31_0,"
group.long 0x2364++0x03
line.long 0x00 "PS0SR0_B1A1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS0SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x2368++0x03
line.long 0x00 "PS1SR0_B1A1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS1SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x2380++0x03
line.long 0x00 "IOINTSEL0_B1A1,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group"
abitfld.long 0x00 0.--31. "IOINTSEL_31_0,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input/output mode,0x00000001=1: Interrupt input mode"
group.long 0x2384++0x03
line.long 0x00 "INOUTSEL0_B1A1,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INOUTSEL_31_0,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input mode,0x00000001=1: General output mode"
group.long 0x2388++0x03
line.long 0x00 "OUTDT0_B1A1,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDT_31_0,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL" "0x00000000=0: 0 is output,0x00000001=1: 1 is output"
group.long 0x238C++0x03
line.long 0x00 "INDT0_B1A1,INDTn is a register that can read the status of General-Purpose Input / Output Ports"
abitfld.long 0x00 0.--31. "INDT_31_0,Each bit reflects the value received through the corresponding port pin" "0x00000000=0: Input is 0,0x00000001=1: Input is 1"
group.long 0x2390++0x03
line.long 0x00 "INTDT0_B1A1,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INTDT_31_0,Each bit indicates the input of an interrupt signal on the corresponding port pin" "0x00000000=0: No interrupt signal has been input,0x00000001=1: Interrupt signal has been input"
group.long 0x2394++0x03
line.long 0x00 "INTCLR0_B1A1,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).."
abitfld.long 0x00 0.--31. "INTCLR_31_0,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register" "0x00000000=0: No effect,0x00000001=1: Interrupt display"
group.long 0x2398++0x03
line.long 0x00 "INTMSK0_B1A1,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch"
abitfld.long 0x00 0.--31. "INTMSK_31_0,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block" "0x00000000=0: Interrupt is masked,0x00000001=1: Interrupt is not masked"
group.long 0x239C++0x03
line.long 0x00 "MSKCLR0_B1A1,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A"
abitfld.long 0x00 0.--31. "MSKCLR_31_0,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block" "0x00000000=0: No effect,0x00000001=1: Interrupt is not masked"
group.long 0x23A0++0x03
line.long 0x00 "POSNEG0_B1A1,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode general output mode or interrupt input mode"
abitfld.long 0x00 0.--31. "POSNEG_31_0,Selects the polarity (positive or negative logic) of each port pin" "0x00000000=0: Positive logic,0x00000001=1: Negative logic"
group.long 0x23A4++0x03
line.long 0x00 "EDGLEVEL0_B1A1,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "EDGLEVEL_31_0,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected" "0x00000000=0: Level,0x00000001=1: Edge"
group.long 0x23A8++0x03
line.long 0x00 "FILONOFF0_B1A1,FILONOFFn prevents chattering input to the port pins of each GPIO group"
abitfld.long 0x00 0.--31. "FILONOFF_31_0,Enables or disables the chattering prevention function" "0x00000000=0: Chattering prevention function is..,0x00000001=1: Chattering prevention function is.."
group.long 0x23AC++0x03
line.long 0x00 "FILCLKSEL0_B1A1,FILCLKSELn controls the division ratio of clock CP? for prevent chattering input to the port pin GPIO group"
hexmask.long 0x00 0.--31. 1. "FILCLKSEL_31_0,Set the division ratio of filter CLOCK"
group.long 0x23C0++0x03
line.long 0x00 "OUTDTSEL0_B1A1,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDTSEL_31_0,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn" "0x00000000=0: General output register is used to..,0x00000001=1: Output data high register and.."
group.long 0x23C4++0x03
line.long 0x00 "OUTDTH0_B1A1,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTH_31_0,Outputting high value data" "0x00000000=0: Invalid data,0x00000001=1: Valid data"
group.long 0x23C8++0x03
line.long 0x00 "OUTDTL0_B1A1,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTL_31_0,Outputting low value data" "0x00000000=0: Valid data,0x00000001=1: Invalid data"
group.long 0x23CC++0x03
line.long 0x00 "BOTHEDGE0_B1A1,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers"
abitfld.long 0x00 0.--31. "BOTHEDGE_31_0,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected" "0x00000000=0: One edge,0x00000001=1: Both edges"
group.long 0x23D0++0x03
line.long 0x00 "INEN0_B1A1,Create registers that can control IE in GPIO"
hexmask.long 0x00 0.--31. 1. "INEN_31_0,"
group.long 0x2400++0x03
line.long 0x00 "PMMR0_B1A2,PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers"
hexmask.long 0x00 0.--31. 1. "PMMR_31_0,Multiplexed Pin Setting Mask Writing a value to any register from among the GPSR IPSR DRVCTRL TDSEL POC PUEN PUD MODSEL DMPR PSER PSSR PINV PIS registers is enabled by writing the inverse of the value to this register"
group.long 0x2404++0x03
line.long 0x00 "PMMER0_B1A2,PMMERn / PMMERSYS performs enables / disables control of the PMMR"
abitfld.long 0x00 0.--31. "PMMER_31_0,Multiplexed Pin Setting Mask Enable" "0x00000000=0: PMMR function is disabled,0x00000001=1: PMMR function is enabled"
group.long 0x2420++0x03
line.long 0x00 "DM0PR0_B1A2,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM0PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x2424++0x03
line.long 0x00 "DM1PR0_B1A2,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM1PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x2428++0x03
line.long 0x00 "DM2PR0_B1A2,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM2PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x242C++0x03
line.long 0x00 "DM3PR0_B1A2,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM3PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x2440++0x03
line.long 0x00 "GPSR0_B1A2,GPSRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "GPSR_31_0,"
group.long 0x2460++0x03
line.long 0x00 "IP0SR0_B1A2,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP0SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x2464++0x03
line.long 0x00 "IP1SR0_B1A2,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP1SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x2468++0x03
line.long 0x00 "IP2SR0_B1A2,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP2SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x2480++0x03
line.long 0x00 "DRV0CTRL0_B1A2,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV0CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x2484++0x03
line.long 0x00 "DRV1CTRL0_B1A2,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV1CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x2488++0x03
line.long 0x00 "DRV2CTRL0_B1A2,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV2CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x24A0++0x03
line.long 0x00 "POC0_B1A2,Each bit in POCn / POCSYS must be set according to IO voltage level that is supplied to the pin"
abitfld.long 0x00 0.--31. "POC_31_0,- For 1.8V/3.3 V" "0x00000000=0: 2.5V,0x00000001=1: 3.3V"
group.long 0x24C0++0x03
line.long 0x00 "PUEN0_B1A2,PUENn / PUENSYS performs on / off control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUEN_31_0,"
group.long 0x24E0++0x03
line.long 0x00 "PUD0_B1A2,PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUD_31_0,"
group.long 0x2560++0x03
line.long 0x00 "PSER0_B1A2,The register (PSERn) to enable / disable PSS Rregister"
hexmask.long 0x00 0.--31. 1. "PSER_31_0,"
group.long 0x2564++0x03
line.long 0x00 "PS0SR0_B1A2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS0SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x2568++0x03
line.long 0x00 "PS1SR0_B1A2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS1SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x2580++0x03
line.long 0x00 "IOINTSEL0_B1A2,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group"
abitfld.long 0x00 0.--31. "IOINTSEL_31_0,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input/output mode,0x00000001=1: Interrupt input mode"
group.long 0x2584++0x03
line.long 0x00 "INOUTSEL0_B1A2,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INOUTSEL_31_0,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input mode,0x00000001=1: General output mode"
group.long 0x2588++0x03
line.long 0x00 "OUTDT0_B1A2,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDT_31_0,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL" "0x00000000=0: 0 is output,0x00000001=1: 1 is output"
group.long 0x258C++0x03
line.long 0x00 "INDT0_B1A2,INDTn is a register that can read the status of General-Purpose Input / Output Ports"
abitfld.long 0x00 0.--31. "INDT_31_0,Each bit reflects the value received through the corresponding port pin" "0x00000000=0: Input is 0,0x00000001=1: Input is 1"
group.long 0x2590++0x03
line.long 0x00 "INTDT0_B1A2,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INTDT_31_0,Each bit indicates the input of an interrupt signal on the corresponding port pin" "0x00000000=0: No interrupt signal has been input,0x00000001=1: Interrupt signal has been input"
group.long 0x2594++0x03
line.long 0x00 "INTCLR0_B1A2,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).."
abitfld.long 0x00 0.--31. "INTCLR_31_0,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register" "0x00000000=0: No effect,0x00000001=1: Interrupt display"
group.long 0x2598++0x03
line.long 0x00 "INTMSK0_B1A2,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch"
abitfld.long 0x00 0.--31. "INTMSK_31_0,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block" "0x00000000=0: Interrupt is masked,0x00000001=1: Interrupt is not masked"
group.long 0x259C++0x03
line.long 0x00 "MSKCLR0_B1A2,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A"
abitfld.long 0x00 0.--31. "MSKCLR_31_0,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block" "0x00000000=0: No effect,0x00000001=1: Interrupt is not masked"
group.long 0x25A0++0x03
line.long 0x00 "POSNEG0_B1A2,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode general output mode or interrupt input mode"
abitfld.long 0x00 0.--31. "POSNEG_31_0,Selects the polarity (positive or negative logic) of each port pin" "0x00000000=0: Positive logic,0x00000001=1: Negative logic"
group.long 0x25A4++0x03
line.long 0x00 "EDGLEVEL0_B1A2,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "EDGLEVEL_31_0,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected" "0x00000000=0: Level,0x00000001=1: Edge"
group.long 0x25A8++0x03
line.long 0x00 "FILONOFF0_B1A2,FILONOFFn prevents chattering input to the port pins of each GPIO group"
abitfld.long 0x00 0.--31. "FILONOFF_31_0,Enables or disables the chattering prevention function" "0x00000000=0: Chattering prevention function is..,0x00000001=1: Chattering prevention function is.."
group.long 0x25AC++0x03
line.long 0x00 "FILCLKSEL0_B1A2,FILCLKSELn controls the division ratio of clock CP? for prevent chattering input to the port pin GPIO group"
hexmask.long 0x00 0.--31. 1. "FILCLKSEL_31_0,Set the division ratio of filter CLOCK"
group.long 0x25C0++0x03
line.long 0x00 "OUTDTSEL0_B1A2,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDTSEL_31_0,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn" "0x00000000=0: General output register is used to..,0x00000001=1: Output data high register and.."
group.long 0x25C4++0x03
line.long 0x00 "OUTDTH0_B1A2,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTH_31_0,Outputting high value data" "0x00000000=0: Invalid data,0x00000001=1: Valid data"
group.long 0x25C8++0x03
line.long 0x00 "OUTDTL0_B1A2,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTL_31_0,Outputting low value data" "0x00000000=0: Valid data,0x00000001=1: Invalid data"
group.long 0x25CC++0x03
line.long 0x00 "BOTHEDGE0_B1A2,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers"
abitfld.long 0x00 0.--31. "BOTHEDGE_31_0,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected" "0x00000000=0: One edge,0x00000001=1: Both edges"
group.long 0x25D0++0x03
line.long 0x00 "INEN0_B1A2,Create registers that can control IE in GPIO"
hexmask.long 0x00 0.--31. 1. "INEN_31_0,"
group.long 0x4000++0x03
line.long 0x00 "PMMR0_B2A0,PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers"
hexmask.long 0x00 0.--31. 1. "PMMR_31_0,Multiplexed Pin Setting Mask Writing a value to any register from among the GPSR IPSR DRVCTRL TDSEL POC PUEN PUD MODSEL DMPR PSER PSSR PINV PIS registers is enabled by writing the inverse of the value to this register"
group.long 0x4004++0x03
line.long 0x00 "PMMER0_B2A0,PMMERn / PMMERSYS performs enables / disables control of the PMMR"
abitfld.long 0x00 0.--31. "PMMER_31_0,Multiplexed Pin Setting Mask Enable" "0x00000000=0: PMMR function is disabled,0x00000001=1: PMMR function is enabled"
group.long 0x4020++0x03
line.long 0x00 "DM0PR0_B2A0,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM0PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x4024++0x03
line.long 0x00 "DM1PR0_B2A0,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM1PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x4028++0x03
line.long 0x00 "DM2PR0_B2A0,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM2PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x402C++0x03
line.long 0x00 "DM3PR0_B2A0,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM3PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x4040++0x03
line.long 0x00 "GPSR0_B2A0,GPSRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "GPSR_31_0,"
group.long 0x4060++0x03
line.long 0x00 "IP0SR0_B2A0,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP0SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x4064++0x03
line.long 0x00 "IP1SR0_B2A0,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP1SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x4068++0x03
line.long 0x00 "IP2SR0_B2A0,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP2SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x4080++0x03
line.long 0x00 "DRV0CTRL0_B2A0,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV0CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x4084++0x03
line.long 0x00 "DRV1CTRL0_B2A0,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV1CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x4088++0x03
line.long 0x00 "DRV2CTRL0_B2A0,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV2CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x40A0++0x03
line.long 0x00 "POC0_B2A0,Each bit in POCn / POCSYS must be set according to IO voltage level that is supplied to the pin"
abitfld.long 0x00 0.--31. "POC_31_0,- For 1.8V/3.3 V" "0x00000000=0: 2.5V,0x00000001=1: 3.3V"
group.long 0x40C0++0x03
line.long 0x00 "PUEN0_B2A0,PUENn / PUENSYS performs on / off control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUEN_31_0,"
group.long 0x40E0++0x03
line.long 0x00 "PUD0_B2A0,PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUD_31_0,"
group.long 0x4160++0x03
line.long 0x00 "PSER0_B2A0,The register (PSERn) to enable / disable PSS Rregister"
hexmask.long 0x00 0.--31. 1. "PSER_31_0,"
group.long 0x4164++0x03
line.long 0x00 "PS0SR0_B2A0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS0SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x4168++0x03
line.long 0x00 "PS1SR0_B2A0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS1SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x4180++0x03
line.long 0x00 "IOINTSEL0_B2A0,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group"
abitfld.long 0x00 0.--31. "IOINTSEL_31_0,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input/output mode,0x00000001=1: Interrupt input mode"
group.long 0x4184++0x03
line.long 0x00 "INOUTSEL0_B2A0,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INOUTSEL_31_0,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input mode,0x00000001=1: General output mode"
group.long 0x4188++0x03
line.long 0x00 "OUTDT0_B2A0,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDT_31_0,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL" "0x00000000=0: 0 is output,0x00000001=1: 1 is output"
group.long 0x418C++0x03
line.long 0x00 "INDT0_B2A0,INDTn is a register that can read the status of General-Purpose Input / Output Ports"
abitfld.long 0x00 0.--31. "INDT_31_0,Each bit reflects the value received through the corresponding port pin" "0x00000000=0: Input is 0,0x00000001=1: Input is 1"
group.long 0x4190++0x03
line.long 0x00 "INTDT0_B2A0,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INTDT_31_0,Each bit indicates the input of an interrupt signal on the corresponding port pin" "0x00000000=0: No interrupt signal has been input,0x00000001=1: Interrupt signal has been input"
group.long 0x4194++0x03
line.long 0x00 "INTCLR0_B2A0,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).."
abitfld.long 0x00 0.--31. "INTCLR_31_0,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register" "0x00000000=0: No effect,0x00000001=1: Interrupt display"
group.long 0x4198++0x03
line.long 0x00 "INTMSK0_B2A0,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch"
abitfld.long 0x00 0.--31. "INTMSK_31_0,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block" "0x00000000=0: Interrupt is masked,0x00000001=1: Interrupt is not masked"
group.long 0x419C++0x03
line.long 0x00 "MSKCLR0_B2A0,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A"
abitfld.long 0x00 0.--31. "MSKCLR_31_0,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block" "0x00000000=0: No effect,0x00000001=1: Interrupt is not masked"
group.long 0x41A0++0x03
line.long 0x00 "POSNEG0_B2A0,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode general output mode or interrupt input mode"
abitfld.long 0x00 0.--31. "POSNEG_31_0,Selects the polarity (positive or negative logic) of each port pin" "0x00000000=0: Positive logic,0x00000001=1: Negative logic"
group.long 0x41A4++0x03
line.long 0x00 "EDGLEVEL0_B2A0,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "EDGLEVEL_31_0,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected" "0x00000000=0: Level,0x00000001=1: Edge"
group.long 0x41A8++0x03
line.long 0x00 "FILONOFF0_B2A0,FILONOFFn prevents chattering input to the port pins of each GPIO group"
abitfld.long 0x00 0.--31. "FILONOFF_31_0,Enables or disables the chattering prevention function" "0x00000000=0: Chattering prevention function is..,0x00000001=1: Chattering prevention function is.."
group.long 0x41AC++0x03
line.long 0x00 "FILCLKSEL0_B2A0,FILCLKSELn controls the division ratio of clock CP? for prevent chattering input to the port pin GPIO group"
hexmask.long 0x00 0.--31. 1. "FILCLKSEL_31_0,Set the division ratio of filter CLOCK"
group.long 0x41C0++0x03
line.long 0x00 "OUTDTSEL0_B2A0,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDTSEL_31_0,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn" "0x00000000=0: General output register is used to..,0x00000001=1: Output data high register and.."
group.long 0x41C4++0x03
line.long 0x00 "OUTDTH0_B2A0,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTH_31_0,Outputting high value data" "0x00000000=0: Invalid data,0x00000001=1: Valid data"
group.long 0x41C8++0x03
line.long 0x00 "OUTDTL0_B2A0,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTL_31_0,Outputting low value data" "0x00000000=0: Valid data,0x00000001=1: Invalid data"
group.long 0x41CC++0x03
line.long 0x00 "BOTHEDGE0_B2A0,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers"
abitfld.long 0x00 0.--31. "BOTHEDGE_31_0,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected" "0x00000000=0: One edge,0x00000001=1: Both edges"
group.long 0x41D0++0x03
line.long 0x00 "INEN0_B2A0,Create registers that can control IE in GPIO"
hexmask.long 0x00 0.--31. 1. "INEN_31_0,"
group.long 0x4200++0x03
line.long 0x00 "PMMR0_B2A1,PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers"
hexmask.long 0x00 0.--31. 1. "PMMR_31_0,Multiplexed Pin Setting Mask Writing a value to any register from among the GPSR IPSR DRVCTRL TDSEL POC PUEN PUD MODSEL DMPR PSER PSSR PINV PIS registers is enabled by writing the inverse of the value to this register"
group.long 0x4204++0x03
line.long 0x00 "PMMER0_B2A1,PMMERn / PMMERSYS performs enables / disables control of the PMMR"
abitfld.long 0x00 0.--31. "PMMER_31_0,Multiplexed Pin Setting Mask Enable" "0x00000000=0: PMMR function is disabled,0x00000001=1: PMMR function is enabled"
group.long 0x4220++0x03
line.long 0x00 "DM0PR0_B2A1,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM0PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x4224++0x03
line.long 0x00 "DM1PR0_B2A1,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM1PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x4228++0x03
line.long 0x00 "DM2PR0_B2A1,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM2PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x422C++0x03
line.long 0x00 "DM3PR0_B2A1,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM3PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x4240++0x03
line.long 0x00 "GPSR0_B2A1,GPSRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "GPSR_31_0,"
group.long 0x4260++0x03
line.long 0x00 "IP0SR0_B2A1,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP0SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x4264++0x03
line.long 0x00 "IP1SR0_B2A1,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP1SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x4268++0x03
line.long 0x00 "IP2SR0_B2A1,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP2SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x4280++0x03
line.long 0x00 "DRV0CTRL0_B2A1,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV0CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x4284++0x03
line.long 0x00 "DRV1CTRL0_B2A1,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV1CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x4288++0x03
line.long 0x00 "DRV2CTRL0_B2A1,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV2CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x42A0++0x03
line.long 0x00 "POC0_B2A1,Each bit in POCn / POCSYS must be set according to IO voltage level that is supplied to the pin"
abitfld.long 0x00 0.--31. "POC_31_0,- For 1.8V/3.3 V" "0x00000000=0: 2.5V,0x00000001=1: 3.3V"
group.long 0x42C0++0x03
line.long 0x00 "PUEN0_B2A1,PUENn / PUENSYS performs on / off control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUEN_31_0,"
group.long 0x42E0++0x03
line.long 0x00 "PUD0_B2A1,PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUD_31_0,"
group.long 0x4360++0x03
line.long 0x00 "PSER0_B2A1,The register (PSERn) to enable / disable PSS Rregister"
hexmask.long 0x00 0.--31. 1. "PSER_31_0,"
group.long 0x4364++0x03
line.long 0x00 "PS0SR0_B2A1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS0SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x4368++0x03
line.long 0x00 "PS1SR0_B2A1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS1SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x4380++0x03
line.long 0x00 "IOINTSEL0_B2A1,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group"
abitfld.long 0x00 0.--31. "IOINTSEL_31_0,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input/output mode,0x00000001=1: Interrupt input mode"
group.long 0x4384++0x03
line.long 0x00 "INOUTSEL0_B2A1,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INOUTSEL_31_0,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input mode,0x00000001=1: General output mode"
group.long 0x4388++0x03
line.long 0x00 "OUTDT0_B2A1,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDT_31_0,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL" "0x00000000=0: 0 is output,0x00000001=1: 1 is output"
group.long 0x438C++0x03
line.long 0x00 "INDT0_B2A1,INDTn is a register that can read the status of General-Purpose Input / Output Ports"
abitfld.long 0x00 0.--31. "INDT_31_0,Each bit reflects the value received through the corresponding port pin" "0x00000000=0: Input is 0,0x00000001=1: Input is 1"
group.long 0x4390++0x03
line.long 0x00 "INTDT0_B2A1,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INTDT_31_0,Each bit indicates the input of an interrupt signal on the corresponding port pin" "0x00000000=0: No interrupt signal has been input,0x00000001=1: Interrupt signal has been input"
group.long 0x4394++0x03
line.long 0x00 "INTCLR0_B2A1,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).."
abitfld.long 0x00 0.--31. "INTCLR_31_0,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register" "0x00000000=0: No effect,0x00000001=1: Interrupt display"
group.long 0x4398++0x03
line.long 0x00 "INTMSK0_B2A1,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch"
abitfld.long 0x00 0.--31. "INTMSK_31_0,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block" "0x00000000=0: Interrupt is masked,0x00000001=1: Interrupt is not masked"
group.long 0x439C++0x03
line.long 0x00 "MSKCLR0_B2A1,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A"
abitfld.long 0x00 0.--31. "MSKCLR_31_0,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block" "0x00000000=0: No effect,0x00000001=1: Interrupt is not masked"
group.long 0x43A0++0x03
line.long 0x00 "POSNEG0_B2A1,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode general output mode or interrupt input mode"
abitfld.long 0x00 0.--31. "POSNEG_31_0,Selects the polarity (positive or negative logic) of each port pin" "0x00000000=0: Positive logic,0x00000001=1: Negative logic"
group.long 0x43A4++0x03
line.long 0x00 "EDGLEVEL0_B2A1,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "EDGLEVEL_31_0,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected" "0x00000000=0: Level,0x00000001=1: Edge"
group.long 0x43A8++0x03
line.long 0x00 "FILONOFF0_B2A1,FILONOFFn prevents chattering input to the port pins of each GPIO group"
abitfld.long 0x00 0.--31. "FILONOFF_31_0,Enables or disables the chattering prevention function" "0x00000000=0: Chattering prevention function is..,0x00000001=1: Chattering prevention function is.."
group.long 0x43AC++0x03
line.long 0x00 "FILCLKSEL0_B2A1,FILCLKSELn controls the division ratio of clock CP? for prevent chattering input to the port pin GPIO group"
hexmask.long 0x00 0.--31. 1. "FILCLKSEL_31_0,Set the division ratio of filter CLOCK"
group.long 0x43C0++0x03
line.long 0x00 "OUTDTSEL0_B2A1,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDTSEL_31_0,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn" "0x00000000=0: General output register is used to..,0x00000001=1: Output data high register and.."
group.long 0x43C4++0x03
line.long 0x00 "OUTDTH0_B2A1,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTH_31_0,Outputting high value data" "0x00000000=0: Invalid data,0x00000001=1: Valid data"
group.long 0x43C8++0x03
line.long 0x00 "OUTDTL0_B2A1,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTL_31_0,Outputting low value data" "0x00000000=0: Valid data,0x00000001=1: Invalid data"
group.long 0x43CC++0x03
line.long 0x00 "BOTHEDGE0_B2A1,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers"
abitfld.long 0x00 0.--31. "BOTHEDGE_31_0,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected" "0x00000000=0: One edge,0x00000001=1: Both edges"
group.long 0x43D0++0x03
line.long 0x00 "INEN0_B2A1,Create registers that can control IE in GPIO"
hexmask.long 0x00 0.--31. 1. "INEN_31_0,"
group.long 0x4400++0x03
line.long 0x00 "PMMR0_B2A2,PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers"
hexmask.long 0x00 0.--31. 1. "PMMR_31_0,Multiplexed Pin Setting Mask Writing a value to any register from among the GPSR IPSR DRVCTRL TDSEL POC PUEN PUD MODSEL DMPR PSER PSSR PINV PIS registers is enabled by writing the inverse of the value to this register"
group.long 0x4404++0x03
line.long 0x00 "PMMER0_B2A2,PMMERn / PMMERSYS performs enables / disables control of the PMMR"
abitfld.long 0x00 0.--31. "PMMER_31_0,Multiplexed Pin Setting Mask Enable" "0x00000000=0: PMMR function is disabled,0x00000001=1: PMMR function is enabled"
group.long 0x4420++0x03
line.long 0x00 "DM0PR0_B2A2,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM0PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x4424++0x03
line.long 0x00 "DM1PR0_B2A2,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM1PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x4428++0x03
line.long 0x00 "DM2PR0_B2A2,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM2PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x442C++0x03
line.long 0x00 "DM3PR0_B2A2,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM3PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x4440++0x03
line.long 0x00 "GPSR0_B2A2,GPSRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "GPSR_31_0,"
group.long 0x4460++0x03
line.long 0x00 "IP0SR0_B2A2,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP0SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x4464++0x03
line.long 0x00 "IP1SR0_B2A2,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP1SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x4468++0x03
line.long 0x00 "IP2SR0_B2A2,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP2SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x4480++0x03
line.long 0x00 "DRV0CTRL0_B2A2,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV0CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x4484++0x03
line.long 0x00 "DRV1CTRL0_B2A2,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV1CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x4488++0x03
line.long 0x00 "DRV2CTRL0_B2A2,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV2CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x44A0++0x03
line.long 0x00 "POC0_B2A2,Each bit in POCn / POCSYS must be set according to IO voltage level that is supplied to the pin"
abitfld.long 0x00 0.--31. "POC_31_0,- For 1.8V/3.3 V" "0x00000000=0: 2.5V,0x00000001=1: 3.3V"
group.long 0x44C0++0x03
line.long 0x00 "PUEN0_B2A2,PUENn / PUENSYS performs on / off control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUEN_31_0,"
group.long 0x44E0++0x03
line.long 0x00 "PUD0_B2A2,PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUD_31_0,"
group.long 0x4560++0x03
line.long 0x00 "PSER0_B2A2,The register (PSERn) to enable / disable PSS Rregister"
hexmask.long 0x00 0.--31. 1. "PSER_31_0,"
group.long 0x4564++0x03
line.long 0x00 "PS0SR0_B2A2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS0SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x4568++0x03
line.long 0x00 "PS1SR0_B2A2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS1SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x4580++0x03
line.long 0x00 "IOINTSEL0_B2A2,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group"
abitfld.long 0x00 0.--31. "IOINTSEL_31_0,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input/output mode,0x00000001=1: Interrupt input mode"
group.long 0x4584++0x03
line.long 0x00 "INOUTSEL0_B2A2,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INOUTSEL_31_0,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input mode,0x00000001=1: General output mode"
group.long 0x4588++0x03
line.long 0x00 "OUTDT0_B2A2,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDT_31_0,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL" "0x00000000=0: 0 is output,0x00000001=1: 1 is output"
group.long 0x458C++0x03
line.long 0x00 "INDT0_B2A2,INDTn is a register that can read the status of General-Purpose Input / Output Ports"
abitfld.long 0x00 0.--31. "INDT_31_0,Each bit reflects the value received through the corresponding port pin" "0x00000000=0: Input is 0,0x00000001=1: Input is 1"
group.long 0x4590++0x03
line.long 0x00 "INTDT0_B2A2,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INTDT_31_0,Each bit indicates the input of an interrupt signal on the corresponding port pin" "0x00000000=0: No interrupt signal has been input,0x00000001=1: Interrupt signal has been input"
group.long 0x4594++0x03
line.long 0x00 "INTCLR0_B2A2,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).."
abitfld.long 0x00 0.--31. "INTCLR_31_0,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register" "0x00000000=0: No effect,0x00000001=1: Interrupt display"
group.long 0x4598++0x03
line.long 0x00 "INTMSK0_B2A2,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch"
abitfld.long 0x00 0.--31. "INTMSK_31_0,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block" "0x00000000=0: Interrupt is masked,0x00000001=1: Interrupt is not masked"
group.long 0x459C++0x03
line.long 0x00 "MSKCLR0_B2A2,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A"
abitfld.long 0x00 0.--31. "MSKCLR_31_0,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block" "0x00000000=0: No effect,0x00000001=1: Interrupt is not masked"
group.long 0x45A0++0x03
line.long 0x00 "POSNEG0_B2A2,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode general output mode or interrupt input mode"
abitfld.long 0x00 0.--31. "POSNEG_31_0,Selects the polarity (positive or negative logic) of each port pin" "0x00000000=0: Positive logic,0x00000001=1: Negative logic"
group.long 0x45A4++0x03
line.long 0x00 "EDGLEVEL0_B2A2,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "EDGLEVEL_31_0,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected" "0x00000000=0: Level,0x00000001=1: Edge"
group.long 0x45A8++0x03
line.long 0x00 "FILONOFF0_B2A2,FILONOFFn prevents chattering input to the port pins of each GPIO group"
abitfld.long 0x00 0.--31. "FILONOFF_31_0,Enables or disables the chattering prevention function" "0x00000000=0: Chattering prevention function is..,0x00000001=1: Chattering prevention function is.."
group.long 0x45AC++0x03
line.long 0x00 "FILCLKSEL0_B2A2,FILCLKSELn controls the division ratio of clock CP? for prevent chattering input to the port pin GPIO group"
hexmask.long 0x00 0.--31. 1. "FILCLKSEL_31_0,Set the division ratio of filter CLOCK"
group.long 0x45C0++0x03
line.long 0x00 "OUTDTSEL0_B2A2,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDTSEL_31_0,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn" "0x00000000=0: General output register is used to..,0x00000001=1: Output data high register and.."
group.long 0x45C4++0x03
line.long 0x00 "OUTDTH0_B2A2,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTH_31_0,Outputting high value data" "0x00000000=0: Invalid data,0x00000001=1: Valid data"
group.long 0x45C8++0x03
line.long 0x00 "OUTDTL0_B2A2,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTL_31_0,Outputting low value data" "0x00000000=0: Valid data,0x00000001=1: Invalid data"
group.long 0x45CC++0x03
line.long 0x00 "BOTHEDGE0_B2A2,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers"
abitfld.long 0x00 0.--31. "BOTHEDGE_31_0,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected" "0x00000000=0: One edge,0x00000001=1: Both edges"
group.long 0x45D0++0x03
line.long 0x00 "INEN0_B2A2,Create registers that can control IE in GPIO"
hexmask.long 0x00 0.--31. 1. "INEN_31_0,"
group.long 0x6000++0x03
line.long 0x00 "PMMR0_B3A0,PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers"
hexmask.long 0x00 0.--31. 1. "PMMR_31_0,Multiplexed Pin Setting Mask Writing a value to any register from among the GPSR IPSR DRVCTRL TDSEL POC PUEN PUD MODSEL DMPR PSER PSSR PINV PIS registers is enabled by writing the inverse of the value to this register"
group.long 0x6004++0x03
line.long 0x00 "PMMER0_B3A0,PMMERn / PMMERSYS performs enables / disables control of the PMMR"
abitfld.long 0x00 0.--31. "PMMER_31_0,Multiplexed Pin Setting Mask Enable" "0x00000000=0: PMMR function is disabled,0x00000001=1: PMMR function is enabled"
group.long 0x6020++0x03
line.long 0x00 "DM0PR0_B3A0,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM0PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x6024++0x03
line.long 0x00 "DM1PR0_B3A0,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM1PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x6028++0x03
line.long 0x00 "DM2PR0_B3A0,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM2PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x602C++0x03
line.long 0x00 "DM3PR0_B3A0,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM3PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x6040++0x03
line.long 0x00 "GPSR0_B3A0,GPSRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "GPSR_31_0,"
group.long 0x6060++0x03
line.long 0x00 "IP0SR0_B3A0,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP0SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x6064++0x03
line.long 0x00 "IP1SR0_B3A0,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP1SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x6068++0x03
line.long 0x00 "IP2SR0_B3A0,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP2SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x6080++0x03
line.long 0x00 "DRV0CTRL0_B3A0,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV0CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x6084++0x03
line.long 0x00 "DRV1CTRL0_B3A0,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV1CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x6088++0x03
line.long 0x00 "DRV2CTRL0_B3A0,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV2CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x60A0++0x03
line.long 0x00 "POC0_B3A0,Each bit in POCn / POCSYS must be set according to IO voltage level that is supplied to the pin"
abitfld.long 0x00 0.--31. "POC_31_0,- For 1.8V/3.3 V" "0x00000000=0: 2.5V,0x00000001=1: 3.3V"
group.long 0x60C0++0x03
line.long 0x00 "PUEN0_B3A0,PUENn / PUENSYS performs on / off control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUEN_31_0,"
group.long 0x60E0++0x03
line.long 0x00 "PUD0_B3A0,PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUD_31_0,"
group.long 0x6160++0x03
line.long 0x00 "PSER0_B3A0,The register (PSERn) to enable / disable PSS Rregister"
hexmask.long 0x00 0.--31. 1. "PSER_31_0,"
group.long 0x6164++0x03
line.long 0x00 "PS0SR0_B3A0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS0SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x6168++0x03
line.long 0x00 "PS1SR0_B3A0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS1SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x6180++0x03
line.long 0x00 "IOINTSEL0_B3A0,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group"
abitfld.long 0x00 0.--31. "IOINTSEL_31_0,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input/output mode,0x00000001=1: Interrupt input mode"
group.long 0x6184++0x03
line.long 0x00 "INOUTSEL0_B3A0,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INOUTSEL_31_0,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input mode,0x00000001=1: General output mode"
group.long 0x6188++0x03
line.long 0x00 "OUTDT0_B3A0,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDT_31_0,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL" "0x00000000=0: 0 is output,0x00000001=1: 1 is output"
group.long 0x618C++0x03
line.long 0x00 "INDT0_B3A0,INDTn is a register that can read the status of General-Purpose Input / Output Ports"
abitfld.long 0x00 0.--31. "INDT_31_0,Each bit reflects the value received through the corresponding port pin" "0x00000000=0: Input is 0,0x00000001=1: Input is 1"
group.long 0x6190++0x03
line.long 0x00 "INTDT0_B3A0,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INTDT_31_0,Each bit indicates the input of an interrupt signal on the corresponding port pin" "0x00000000=0: No interrupt signal has been input,0x00000001=1: Interrupt signal has been input"
group.long 0x6194++0x03
line.long 0x00 "INTCLR0_B3A0,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).."
abitfld.long 0x00 0.--31. "INTCLR_31_0,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register" "0x00000000=0: No effect,0x00000001=1: Interrupt display"
group.long 0x6198++0x03
line.long 0x00 "INTMSK0_B3A0,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch"
abitfld.long 0x00 0.--31. "INTMSK_31_0,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block" "0x00000000=0: Interrupt is masked,0x00000001=1: Interrupt is not masked"
group.long 0x619C++0x03
line.long 0x00 "MSKCLR0_B3A0,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A"
abitfld.long 0x00 0.--31. "MSKCLR_31_0,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block" "0x00000000=0: No effect,0x00000001=1: Interrupt is not masked"
group.long 0x61A0++0x03
line.long 0x00 "POSNEG0_B3A0,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode general output mode or interrupt input mode"
abitfld.long 0x00 0.--31. "POSNEG_31_0,Selects the polarity (positive or negative logic) of each port pin" "0x00000000=0: Positive logic,0x00000001=1: Negative logic"
group.long 0x61A4++0x03
line.long 0x00 "EDGLEVEL0_B3A0,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "EDGLEVEL_31_0,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected" "0x00000000=0: Level,0x00000001=1: Edge"
group.long 0x61A8++0x03
line.long 0x00 "FILONOFF0_B3A0,FILONOFFn prevents chattering input to the port pins of each GPIO group"
abitfld.long 0x00 0.--31. "FILONOFF_31_0,Enables or disables the chattering prevention function" "0x00000000=0: Chattering prevention function is..,0x00000001=1: Chattering prevention function is.."
group.long 0x61AC++0x03
line.long 0x00 "FILCLKSEL0_B3A0,FILCLKSELn controls the division ratio of clock CP? for prevent chattering input to the port pin GPIO group"
hexmask.long 0x00 0.--31. 1. "FILCLKSEL_31_0,Set the division ratio of filter CLOCK"
group.long 0x61C0++0x03
line.long 0x00 "OUTDTSEL0_B3A0,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDTSEL_31_0,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn" "0x00000000=0: General output register is used to..,0x00000001=1: Output data high register and.."
group.long 0x61C4++0x03
line.long 0x00 "OUTDTH0_B3A0,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTH_31_0,Outputting high value data" "0x00000000=0: Invalid data,0x00000001=1: Valid data"
group.long 0x61C8++0x03
line.long 0x00 "OUTDTL0_B3A0,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTL_31_0,Outputting low value data" "0x00000000=0: Valid data,0x00000001=1: Invalid data"
group.long 0x61CC++0x03
line.long 0x00 "BOTHEDGE0_B3A0,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers"
abitfld.long 0x00 0.--31. "BOTHEDGE_31_0,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected" "0x00000000=0: One edge,0x00000001=1: Both edges"
group.long 0x61D0++0x03
line.long 0x00 "INEN0_B3A0,Create registers that can control IE in GPIO"
hexmask.long 0x00 0.--31. 1. "INEN_31_0,"
group.long 0x6200++0x03
line.long 0x00 "PMMR0_B3A1,PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers"
hexmask.long 0x00 0.--31. 1. "PMMR_31_0,Multiplexed Pin Setting Mask Writing a value to any register from among the GPSR IPSR DRVCTRL TDSEL POC PUEN PUD MODSEL DMPR PSER PSSR PINV PIS registers is enabled by writing the inverse of the value to this register"
group.long 0x6204++0x03
line.long 0x00 "PMMER0_B3A1,PMMERn / PMMERSYS performs enables / disables control of the PMMR"
abitfld.long 0x00 0.--31. "PMMER_31_0,Multiplexed Pin Setting Mask Enable" "0x00000000=0: PMMR function is disabled,0x00000001=1: PMMR function is enabled"
group.long 0x6220++0x03
line.long 0x00 "DM0PR0_B3A1,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM0PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x6224++0x03
line.long 0x00 "DM1PR0_B3A1,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM1PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x6228++0x03
line.long 0x00 "DM2PR0_B3A1,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM2PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x622C++0x03
line.long 0x00 "DM3PR0_B3A1,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM3PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x6240++0x03
line.long 0x00 "GPSR0_B3A1,GPSRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "GPSR_31_0,"
group.long 0x6260++0x03
line.long 0x00 "IP0SR0_B3A1,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP0SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x6264++0x03
line.long 0x00 "IP1SR0_B3A1,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP1SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x6268++0x03
line.long 0x00 "IP2SR0_B3A1,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP2SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x6280++0x03
line.long 0x00 "DRV0CTRL0_B3A1,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV0CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x6284++0x03
line.long 0x00 "DRV1CTRL0_B3A1,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV1CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x6288++0x03
line.long 0x00 "DRV2CTRL0_B3A1,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV2CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x62A0++0x03
line.long 0x00 "POC0_B3A1,Each bit in POCn / POCSYS must be set according to IO voltage level that is supplied to the pin"
abitfld.long 0x00 0.--31. "POC_31_0,- For 1.8V/3.3 V" "0x00000000=0: 2.5V,0x00000001=1: 3.3V"
group.long 0x62C0++0x03
line.long 0x00 "PUEN0_B3A1,PUENn / PUENSYS performs on / off control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUEN_31_0,"
group.long 0x62E0++0x03
line.long 0x00 "PUD0_B3A1,PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUD_31_0,"
group.long 0x6360++0x03
line.long 0x00 "PSER0_B3A1,The register (PSERn) to enable / disable PSS Rregister"
hexmask.long 0x00 0.--31. 1. "PSER_31_0,"
group.long 0x6364++0x03
line.long 0x00 "PS0SR0_B3A1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS0SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x6368++0x03
line.long 0x00 "PS1SR0_B3A1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS1SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x6380++0x03
line.long 0x00 "IOINTSEL0_B3A1,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group"
abitfld.long 0x00 0.--31. "IOINTSEL_31_0,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input/output mode,0x00000001=1: Interrupt input mode"
group.long 0x6384++0x03
line.long 0x00 "INOUTSEL0_B3A1,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INOUTSEL_31_0,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input mode,0x00000001=1: General output mode"
group.long 0x6388++0x03
line.long 0x00 "OUTDT0_B3A1,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDT_31_0,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL" "0x00000000=0: 0 is output,0x00000001=1: 1 is output"
group.long 0x638C++0x03
line.long 0x00 "INDT0_B3A1,INDTn is a register that can read the status of General-Purpose Input / Output Ports"
abitfld.long 0x00 0.--31. "INDT_31_0,Each bit reflects the value received through the corresponding port pin" "0x00000000=0: Input is 0,0x00000001=1: Input is 1"
group.long 0x6390++0x03
line.long 0x00 "INTDT0_B3A1,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INTDT_31_0,Each bit indicates the input of an interrupt signal on the corresponding port pin" "0x00000000=0: No interrupt signal has been input,0x00000001=1: Interrupt signal has been input"
group.long 0x6394++0x03
line.long 0x00 "INTCLR0_B3A1,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).."
abitfld.long 0x00 0.--31. "INTCLR_31_0,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register" "0x00000000=0: No effect,0x00000001=1: Interrupt display"
group.long 0x6398++0x03
line.long 0x00 "INTMSK0_B3A1,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch"
abitfld.long 0x00 0.--31. "INTMSK_31_0,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block" "0x00000000=0: Interrupt is masked,0x00000001=1: Interrupt is not masked"
group.long 0x639C++0x03
line.long 0x00 "MSKCLR0_B3A1,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A"
abitfld.long 0x00 0.--31. "MSKCLR_31_0,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block" "0x00000000=0: No effect,0x00000001=1: Interrupt is not masked"
group.long 0x63A0++0x03
line.long 0x00 "POSNEG0_B3A1,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode general output mode or interrupt input mode"
abitfld.long 0x00 0.--31. "POSNEG_31_0,Selects the polarity (positive or negative logic) of each port pin" "0x00000000=0: Positive logic,0x00000001=1: Negative logic"
group.long 0x63A4++0x03
line.long 0x00 "EDGLEVEL0_B3A1,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "EDGLEVEL_31_0,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected" "0x00000000=0: Level,0x00000001=1: Edge"
group.long 0x63A8++0x03
line.long 0x00 "FILONOFF0_B3A1,FILONOFFn prevents chattering input to the port pins of each GPIO group"
abitfld.long 0x00 0.--31. "FILONOFF_31_0,Enables or disables the chattering prevention function" "0x00000000=0: Chattering prevention function is..,0x00000001=1: Chattering prevention function is.."
group.long 0x63AC++0x03
line.long 0x00 "FILCLKSEL0_B3A1,FILCLKSELn controls the division ratio of clock CP? for prevent chattering input to the port pin GPIO group"
hexmask.long 0x00 0.--31. 1. "FILCLKSEL_31_0,Set the division ratio of filter CLOCK"
group.long 0x63C0++0x03
line.long 0x00 "OUTDTSEL0_B3A1,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDTSEL_31_0,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn" "0x00000000=0: General output register is used to..,0x00000001=1: Output data high register and.."
group.long 0x63C4++0x03
line.long 0x00 "OUTDTH0_B3A1,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTH_31_0,Outputting high value data" "0x00000000=0: Invalid data,0x00000001=1: Valid data"
group.long 0x63C8++0x03
line.long 0x00 "OUTDTL0_B3A1,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTL_31_0,Outputting low value data" "0x00000000=0: Valid data,0x00000001=1: Invalid data"
group.long 0x63CC++0x03
line.long 0x00 "BOTHEDGE0_B3A1,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers"
abitfld.long 0x00 0.--31. "BOTHEDGE_31_0,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected" "0x00000000=0: One edge,0x00000001=1: Both edges"
group.long 0x63D0++0x03
line.long 0x00 "INEN0_B3A1,Create registers that can control IE in GPIO"
hexmask.long 0x00 0.--31. 1. "INEN_31_0,"
group.long 0x6400++0x03
line.long 0x00 "PMMR0_B3A2,PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers"
hexmask.long 0x00 0.--31. 1. "PMMR_31_0,Multiplexed Pin Setting Mask Writing a value to any register from among the GPSR IPSR DRVCTRL TDSEL POC PUEN PUD MODSEL DMPR PSER PSSR PINV PIS registers is enabled by writing the inverse of the value to this register"
group.long 0x6404++0x03
line.long 0x00 "PMMER0_B3A2,PMMERn / PMMERSYS performs enables / disables control of the PMMR"
abitfld.long 0x00 0.--31. "PMMER_31_0,Multiplexed Pin Setting Mask Enable" "0x00000000=0: PMMR function is disabled,0x00000001=1: PMMR function is enabled"
group.long 0x6420++0x03
line.long 0x00 "DM0PR0_B3A2,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM0PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x6424++0x03
line.long 0x00 "DM1PR0_B3A2,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM1PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x6428++0x03
line.long 0x00 "DM2PR0_B3A2,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM2PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x642C++0x03
line.long 0x00 "DM3PR0_B3A2,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM3PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x6440++0x03
line.long 0x00 "GPSR0_B3A2,GPSRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "GPSR_31_0,"
group.long 0x6460++0x03
line.long 0x00 "IP0SR0_B3A2,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP0SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x6464++0x03
line.long 0x00 "IP1SR0_B3A2,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP1SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x6468++0x03
line.long 0x00 "IP2SR0_B3A2,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP2SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x6480++0x03
line.long 0x00 "DRV0CTRL0_B3A2,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV0CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x6484++0x03
line.long 0x00 "DRV1CTRL0_B3A2,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV1CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x6488++0x03
line.long 0x00 "DRV2CTRL0_B3A2,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV2CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x64A0++0x03
line.long 0x00 "POC0_B3A2,Each bit in POCn / POCSYS must be set according to IO voltage level that is supplied to the pin"
abitfld.long 0x00 0.--31. "POC_31_0,- For 1.8V/3.3 V" "0x00000000=0: 2.5V,0x00000001=1: 3.3V"
group.long 0x64C0++0x03
line.long 0x00 "PUEN0_B3A2,PUENn / PUENSYS performs on / off control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUEN_31_0,"
group.long 0x64E0++0x03
line.long 0x00 "PUD0_B3A2,PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUD_31_0,"
group.long 0x6560++0x03
line.long 0x00 "PSER0_B3A2,The register (PSERn) to enable / disable PSS Rregister"
hexmask.long 0x00 0.--31. 1. "PSER_31_0,"
group.long 0x6564++0x03
line.long 0x00 "PS0SR0_B3A2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS0SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x6568++0x03
line.long 0x00 "PS1SR0_B3A2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS1SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x6580++0x03
line.long 0x00 "IOINTSEL0_B3A2,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group"
abitfld.long 0x00 0.--31. "IOINTSEL_31_0,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input/output mode,0x00000001=1: Interrupt input mode"
group.long 0x6584++0x03
line.long 0x00 "INOUTSEL0_B3A2,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INOUTSEL_31_0,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input mode,0x00000001=1: General output mode"
group.long 0x6588++0x03
line.long 0x00 "OUTDT0_B3A2,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDT_31_0,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL" "0x00000000=0: 0 is output,0x00000001=1: 1 is output"
group.long 0x658C++0x03
line.long 0x00 "INDT0_B3A2,INDTn is a register that can read the status of General-Purpose Input / Output Ports"
abitfld.long 0x00 0.--31. "INDT_31_0,Each bit reflects the value received through the corresponding port pin" "0x00000000=0: Input is 0,0x00000001=1: Input is 1"
group.long 0x6590++0x03
line.long 0x00 "INTDT0_B3A2,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INTDT_31_0,Each bit indicates the input of an interrupt signal on the corresponding port pin" "0x00000000=0: No interrupt signal has been input,0x00000001=1: Interrupt signal has been input"
group.long 0x6594++0x03
line.long 0x00 "INTCLR0_B3A2,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).."
abitfld.long 0x00 0.--31. "INTCLR_31_0,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register" "0x00000000=0: No effect,0x00000001=1: Interrupt display"
group.long 0x6598++0x03
line.long 0x00 "INTMSK0_B3A2,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch"
abitfld.long 0x00 0.--31. "INTMSK_31_0,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block" "0x00000000=0: Interrupt is masked,0x00000001=1: Interrupt is not masked"
group.long 0x659C++0x03
line.long 0x00 "MSKCLR0_B3A2,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A"
abitfld.long 0x00 0.--31. "MSKCLR_31_0,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block" "0x00000000=0: No effect,0x00000001=1: Interrupt is not masked"
group.long 0x65A0++0x03
line.long 0x00 "POSNEG0_B3A2,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode general output mode or interrupt input mode"
abitfld.long 0x00 0.--31. "POSNEG_31_0,Selects the polarity (positive or negative logic) of each port pin" "0x00000000=0: Positive logic,0x00000001=1: Negative logic"
group.long 0x65A4++0x03
line.long 0x00 "EDGLEVEL0_B3A2,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "EDGLEVEL_31_0,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected" "0x00000000=0: Level,0x00000001=1: Edge"
group.long 0x65A8++0x03
line.long 0x00 "FILONOFF0_B3A2,FILONOFFn prevents chattering input to the port pins of each GPIO group"
abitfld.long 0x00 0.--31. "FILONOFF_31_0,Enables or disables the chattering prevention function" "0x00000000=0: Chattering prevention function is..,0x00000001=1: Chattering prevention function is.."
group.long 0x65AC++0x03
line.long 0x00 "FILCLKSEL0_B3A2,FILCLKSELn controls the division ratio of clock CP? for prevent chattering input to the port pin GPIO group"
hexmask.long 0x00 0.--31. 1. "FILCLKSEL_31_0,Set the division ratio of filter CLOCK"
group.long 0x65C0++0x03
line.long 0x00 "OUTDTSEL0_B3A2,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDTSEL_31_0,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn" "0x00000000=0: General output register is used to..,0x00000001=1: Output data high register and.."
group.long 0x65C4++0x03
line.long 0x00 "OUTDTH0_B3A2,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTH_31_0,Outputting high value data" "0x00000000=0: Invalid data,0x00000001=1: Valid data"
group.long 0x65C8++0x03
line.long 0x00 "OUTDTL0_B3A2,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTL_31_0,Outputting low value data" "0x00000000=0: Valid data,0x00000001=1: Invalid data"
group.long 0x65CC++0x03
line.long 0x00 "BOTHEDGE0_B3A2,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers"
abitfld.long 0x00 0.--31. "BOTHEDGE_31_0,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected" "0x00000000=0: One edge,0x00000001=1: Both edges"
group.long 0x65D0++0x03
line.long 0x00 "INEN0_B3A2,Create registers that can control IE in GPIO"
hexmask.long 0x00 0.--31. 1. "INEN_31_0,"
tree.end
tree "PFC_GPIO_FOR_GP1"
base ad:0xE6050800
group.long 0x00++0x03
line.long 0x00 "PMMR1_B0A0,PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers"
hexmask.long 0x00 0.--31. 1. "PMMR_31_0,Multiplexed Pin Setting Mask Writing a value to any register from among the GPSR IPSR DRVCTRL TDSEL POC PUEN PUD MODSEL DMPR PSER PSSR PINV PIS registers is enabled by writing the inverse of the value to this register"
group.long 0x04++0x03
line.long 0x00 "PMMER1_B0A0,PMMERn / PMMERSYS performs enables / disables control of the PMMR"
abitfld.long 0x00 0.--31. "PMMER_31_0,Multiplexed Pin Setting Mask Enable" "0x00000000=0: PMMR function is disabled,0x00000001=1: PMMR function is enabled"
group.long 0x20++0x03
line.long 0x00 "DM0PR1_B0A0,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM0PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x24++0x03
line.long 0x00 "DM1PR1_B0A0,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM1PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x28++0x03
line.long 0x00 "DM2PR1_B0A0,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM2PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x2C++0x03
line.long 0x00 "DM3PR1_B0A0,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM3PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x40++0x03
line.long 0x00 "GPSR1_B0A0,GPSRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "GPSR_31_0,"
group.long 0x60++0x03
line.long 0x00 "IP0SR1_B0A0,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP0SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x80++0x03
line.long 0x00 "DRV0CTRL1_B0A0,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV0CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x84++0x03
line.long 0x00 "DRV1CTRL1_B0A0,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV1CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x88++0x03
line.long 0x00 "DRV2CTRL1_B0A0,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV2CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x8C++0x03
line.long 0x00 "DRV3CTRL1_B0A0,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV3CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0xA0++0x03
line.long 0x00 "POC1_B0A0,Each bit in POCn / POCSYS must be set according to IO voltage level that is supplied to the pin"
abitfld.long 0x00 0.--31. "POC_31_0,- For 1.8V/3.3 V" "0x00000000=0: 2.5V,0x00000001=1: 3.3V"
group.long 0xC0++0x03
line.long 0x00 "PUEN1_B0A0,PUENn / PUENSYS performs on / off control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUEN_31_0,"
group.long 0xE0++0x03
line.long 0x00 "PUD1_B0A0,PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUD_31_0,"
group.long 0x100++0x03
line.long 0x00 "MODSEL_B0A0,MODSELn selects the group for multiple LSI pins with multiplexed pin functions"
hexmask.long 0x00 0.--31. 1. "MODSEL_31_0,"
group.long 0x120++0x03
line.long 0x00 "TD0SEL_B0A0,TD*SELn / TD*SELSYS controls the driving abilities of pins in use for the SDHI"
hexmask.long 0x00 0.--31. 1. "TD0SEL_31_0,"
group.long 0x160++0x03
line.long 0x00 "PSER1_B0A0,The register (PSERn) to enable / disable PSS Rregister"
hexmask.long 0x00 0.--31. 1. "PSER_31_0,"
group.long 0x164++0x03
line.long 0x00 "PS0SR1_B0A0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS0SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x168++0x03
line.long 0x00 "PS1SR1_B0A0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS1SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x180++0x03
line.long 0x00 "IOINTSEL1_B0A0,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group"
abitfld.long 0x00 0.--31. "IOINTSEL_31_0,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input/output mode,0x00000001=1: Interrupt input mode"
group.long 0x184++0x03
line.long 0x00 "INOUTSEL1_B0A0,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INOUTSEL_31_0,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input mode,0x00000001=1: General output mode"
group.long 0x188++0x03
line.long 0x00 "OUTDT1_B0A0,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDT_31_0,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL" "0x00000000=0: 0 is output,0x00000001=1: 1 is output"
group.long 0x18C++0x03
line.long 0x00 "INDT1_B0A0,INDTn is a register that can read the status of General-Purpose Input / Output Ports"
abitfld.long 0x00 0.--31. "INDT_31_0,Each bit reflects the value received through the corresponding port pin" "0x00000000=0: Input is 0,0x00000001=1: Input is 1"
group.long 0x190++0x03
line.long 0x00 "INTDT1_B0A0,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INTDT_31_0,Each bit indicates the input of an interrupt signal on the corresponding port pin" "0x00000000=0: No interrupt signal has been input,0x00000001=1: Interrupt signal has been input"
group.long 0x194++0x03
line.long 0x00 "INTCLR1_B0A0,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).."
abitfld.long 0x00 0.--31. "INTCLR_31_0,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register" "0x00000000=0: No effect,0x00000001=1: Interrupt display"
group.long 0x198++0x03
line.long 0x00 "INTMSK1_B0A0,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch"
abitfld.long 0x00 0.--31. "INTMSK_31_0,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block" "0x00000000=0: Interrupt is masked,0x00000001=1: Interrupt is not masked"
group.long 0x19C++0x03
line.long 0x00 "MSKCLR1_B0A0,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A"
abitfld.long 0x00 0.--31. "MSKCLR_31_0,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block" "0x00000000=0: No effect,0x00000001=1: Interrupt is not masked"
group.long 0x1A0++0x03
line.long 0x00 "POSNEG1_B0A0,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode general output mode or interrupt input mode"
abitfld.long 0x00 0.--31. "POSNEG_31_0,Selects the polarity (positive or negative logic) of each port pin" "0x00000000=0: Positive logic,0x00000001=1: Negative logic"
group.long 0x1A4++0x03
line.long 0x00 "EDGLEVEL1_B0A0,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "EDGLEVEL_31_0,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected" "0x00000000=0: Level,0x00000001=1: Edge"
group.long 0x1A8++0x03
line.long 0x00 "FILONOFF1_B0A0,FILONOFFn prevents chattering input to the port pins of each GPIO group"
abitfld.long 0x00 0.--31. "FILONOFF_31_0,Enables or disables the chattering prevention function" "0x00000000=0: Chattering prevention function is..,0x00000001=1: Chattering prevention function is.."
group.long 0x1AC++0x03
line.long 0x00 "FILCLKSEL1_B0A0,FILCLKSELn controls the division ratio of clock CP? for prevent chattering input to the port pin GPIO group"
hexmask.long 0x00 0.--31. 1. "FILCLKSEL_31_0,Set the division ratio of filter CLOCK"
group.long 0x1C0++0x03
line.long 0x00 "OUTDTSEL1_B0A0,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDTSEL_31_0,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn" "0x00000000=0: General output register is used to..,0x00000001=1: Output data high register and.."
group.long 0x1C4++0x03
line.long 0x00 "OUTDTH1_B0A0,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTH_31_0,Outputting high value data" "0x00000000=0: Invalid data,0x00000001=1: Valid data"
group.long 0x1C8++0x03
line.long 0x00 "OUTDTL1_B0A0,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTL_31_0,Outputting low value data" "0x00000000=0: Valid data,0x00000001=1: Invalid data"
group.long 0x1CC++0x03
line.long 0x00 "BOTHEDGE1_B0A0,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers"
abitfld.long 0x00 0.--31. "BOTHEDGE_31_0,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected" "0x00000000=0: One edge,0x00000001=1: Both edges"
group.long 0x1D0++0x03
line.long 0x00 "INEN1_B0A0,Create registers that can control IE in GPIO"
hexmask.long 0x00 0.--31. 1. "INEN_31_0,"
group.long 0x200++0x03
line.long 0x00 "PMMR1_B0A1,PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers"
hexmask.long 0x00 0.--31. 1. "PMMR_31_0,Multiplexed Pin Setting Mask Writing a value to any register from among the GPSR IPSR DRVCTRL TDSEL POC PUEN PUD MODSEL DMPR PSER PSSR PINV PIS registers is enabled by writing the inverse of the value to this register"
group.long 0x204++0x03
line.long 0x00 "PMMER1_B0A1,PMMERn / PMMERSYS performs enables / disables control of the PMMR"
abitfld.long 0x00 0.--31. "PMMER_31_0,Multiplexed Pin Setting Mask Enable" "0x00000000=0: PMMR function is disabled,0x00000001=1: PMMR function is enabled"
group.long 0x220++0x03
line.long 0x00 "DM0PR1_B0A1,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM0PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x224++0x03
line.long 0x00 "DM1PR1_B0A1,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM1PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x228++0x03
line.long 0x00 "DM2PR1_B0A1,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM2PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x22C++0x03
line.long 0x00 "DM3PR1_B0A1,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM3PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x240++0x03
line.long 0x00 "GPSR1_B0A1,GPSRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "GPSR_31_0,"
group.long 0x260++0x03
line.long 0x00 "IP0SR1_B0A1,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP0SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x280++0x03
line.long 0x00 "DRV0CTRL1_B0A1,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV0CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x284++0x03
line.long 0x00 "DRV1CTRL1_B0A1,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV1CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x288++0x03
line.long 0x00 "DRV2CTRL1_B0A1,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV2CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x28C++0x03
line.long 0x00 "DRV3CTRL1_B0A1,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV3CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x2A0++0x03
line.long 0x00 "POC1_B0A1,Each bit in POCn / POCSYS must be set according to IO voltage level that is supplied to the pin"
abitfld.long 0x00 0.--31. "POC_31_0,- For 1.8V/3.3 V" "0x00000000=0: 2.5V,0x00000001=1: 3.3V"
group.long 0x2C0++0x03
line.long 0x00 "PUEN1_B0A1,PUENn / PUENSYS performs on / off control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUEN_31_0,"
group.long 0x2E0++0x03
line.long 0x00 "PUD1_B0A1,PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUD_31_0,"
group.long 0x300++0x03
line.long 0x00 "MODSEL_B0A1,MODSELn selects the group for multiple LSI pins with multiplexed pin functions"
hexmask.long 0x00 0.--31. 1. "MODSEL_31_0,"
group.long 0x320++0x03
line.long 0x00 "TD0SEL_B0A1,TD*SELn / TD*SELSYS controls the driving abilities of pins in use for the SDHI"
hexmask.long 0x00 0.--31. 1. "TD0SEL_31_0,"
group.long 0x360++0x03
line.long 0x00 "PSER1_B0A1,The register (PSERn) to enable / disable PSS Rregister"
hexmask.long 0x00 0.--31. 1. "PSER_31_0,"
group.long 0x364++0x03
line.long 0x00 "PS0SR1_B0A1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS0SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x368++0x03
line.long 0x00 "PS1SR1_B0A1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS1SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x380++0x03
line.long 0x00 "IOINTSEL1_B0A1,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group"
abitfld.long 0x00 0.--31. "IOINTSEL_31_0,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input/output mode,0x00000001=1: Interrupt input mode"
group.long 0x384++0x03
line.long 0x00 "INOUTSEL1_B0A1,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INOUTSEL_31_0,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input mode,0x00000001=1: General output mode"
group.long 0x388++0x03
line.long 0x00 "OUTDT1_B0A1,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDT_31_0,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL" "0x00000000=0: 0 is output,0x00000001=1: 1 is output"
group.long 0x38C++0x03
line.long 0x00 "INDT1_B0A1,INDTn is a register that can read the status of General-Purpose Input / Output Ports"
abitfld.long 0x00 0.--31. "INDT_31_0,Each bit reflects the value received through the corresponding port pin" "0x00000000=0: Input is 0,0x00000001=1: Input is 1"
group.long 0x390++0x03
line.long 0x00 "INTDT1_B0A1,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INTDT_31_0,Each bit indicates the input of an interrupt signal on the corresponding port pin" "0x00000000=0: No interrupt signal has been input,0x00000001=1: Interrupt signal has been input"
group.long 0x394++0x03
line.long 0x00 "INTCLR1_B0A1,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).."
abitfld.long 0x00 0.--31. "INTCLR_31_0,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register" "0x00000000=0: No effect,0x00000001=1: Interrupt display"
group.long 0x398++0x03
line.long 0x00 "INTMSK1_B0A1,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch"
abitfld.long 0x00 0.--31. "INTMSK_31_0,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block" "0x00000000=0: Interrupt is masked,0x00000001=1: Interrupt is not masked"
group.long 0x39C++0x03
line.long 0x00 "MSKCLR1_B0A1,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A"
abitfld.long 0x00 0.--31. "MSKCLR_31_0,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block" "0x00000000=0: No effect,0x00000001=1: Interrupt is not masked"
group.long 0x3A0++0x03
line.long 0x00 "POSNEG1_B0A1,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode general output mode or interrupt input mode"
abitfld.long 0x00 0.--31. "POSNEG_31_0,Selects the polarity (positive or negative logic) of each port pin" "0x00000000=0: Positive logic,0x00000001=1: Negative logic"
group.long 0x3A4++0x03
line.long 0x00 "EDGLEVEL1_B0A1,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "EDGLEVEL_31_0,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected" "0x00000000=0: Level,0x00000001=1: Edge"
group.long 0x3A8++0x03
line.long 0x00 "FILONOFF1_B0A1,FILONOFFn prevents chattering input to the port pins of each GPIO group"
abitfld.long 0x00 0.--31. "FILONOFF_31_0,Enables or disables the chattering prevention function" "0x00000000=0: Chattering prevention function is..,0x00000001=1: Chattering prevention function is.."
group.long 0x3AC++0x03
line.long 0x00 "FILCLKSEL1_B0A1,FILCLKSELn controls the division ratio of clock CP? for prevent chattering input to the port pin GPIO group"
hexmask.long 0x00 0.--31. 1. "FILCLKSEL_31_0,Set the division ratio of filter CLOCK"
group.long 0x3C0++0x03
line.long 0x00 "OUTDTSEL1_B0A1,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDTSEL_31_0,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn" "0x00000000=0: General output register is used to..,0x00000001=1: Output data high register and.."
group.long 0x3C4++0x03
line.long 0x00 "OUTDTH1_B0A1,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTH_31_0,Outputting high value data" "0x00000000=0: Invalid data,0x00000001=1: Valid data"
group.long 0x3C8++0x03
line.long 0x00 "OUTDTL1_B0A1,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTL_31_0,Outputting low value data" "0x00000000=0: Valid data,0x00000001=1: Invalid data"
group.long 0x3CC++0x03
line.long 0x00 "BOTHEDGE1_B0A1,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers"
abitfld.long 0x00 0.--31. "BOTHEDGE_31_0,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected" "0x00000000=0: One edge,0x00000001=1: Both edges"
group.long 0x3D0++0x03
line.long 0x00 "INEN1_B0A1,Create registers that can control IE in GPIO"
hexmask.long 0x00 0.--31. 1. "INEN_31_0,"
group.long 0x400++0x03
line.long 0x00 "PMMR1_B0A2,PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers"
hexmask.long 0x00 0.--31. 1. "PMMR_31_0,Multiplexed Pin Setting Mask Writing a value to any register from among the GPSR IPSR DRVCTRL TDSEL POC PUEN PUD MODSEL DMPR PSER PSSR PINV PIS registers is enabled by writing the inverse of the value to this register"
group.long 0x404++0x03
line.long 0x00 "PMMER1_B0A2,PMMERn / PMMERSYS performs enables / disables control of the PMMR"
abitfld.long 0x00 0.--31. "PMMER_31_0,Multiplexed Pin Setting Mask Enable" "0x00000000=0: PMMR function is disabled,0x00000001=1: PMMR function is enabled"
group.long 0x420++0x03
line.long 0x00 "DM0PR1_B0A2,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM0PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x424++0x03
line.long 0x00 "DM1PR1_B0A2,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM1PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x428++0x03
line.long 0x00 "DM2PR1_B0A2,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM2PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x42C++0x03
line.long 0x00 "DM3PR1_B0A2,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM3PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x440++0x03
line.long 0x00 "GPSR1_B0A2,GPSRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "GPSR_31_0,"
group.long 0x460++0x03
line.long 0x00 "IP0SR1_B0A2,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP0SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x480++0x03
line.long 0x00 "DRV0CTRL1_B0A2,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV0CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x484++0x03
line.long 0x00 "DRV1CTRL1_B0A2,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV1CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x488++0x03
line.long 0x00 "DRV2CTRL1_B0A2,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV2CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x48C++0x03
line.long 0x00 "DRV3CTRL1_B0A2,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV3CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x4A0++0x03
line.long 0x00 "POC1_B0A2,Each bit in POCn / POCSYS must be set according to IO voltage level that is supplied to the pin"
abitfld.long 0x00 0.--31. "POC_31_0,- For 1.8V/3.3 V" "0x00000000=0: 2.5V,0x00000001=1: 3.3V"
group.long 0x4C0++0x03
line.long 0x00 "PUEN1_B0A2,PUENn / PUENSYS performs on / off control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUEN_31_0,"
group.long 0x4E0++0x03
line.long 0x00 "PUD1_B0A2,PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUD_31_0,"
group.long 0x500++0x03
line.long 0x00 "MODSEL_B0A2,MODSELn selects the group for multiple LSI pins with multiplexed pin functions"
hexmask.long 0x00 0.--31. 1. "MODSEL_31_0,"
group.long 0x520++0x03
line.long 0x00 "TD0SEL_B0A2,TD*SELn / TD*SELSYS controls the driving abilities of pins in use for the SDHI"
hexmask.long 0x00 0.--31. 1. "TD0SEL_31_0,"
group.long 0x560++0x03
line.long 0x00 "PSER1_B0A2,The register (PSERn) to enable / disable PSS Rregister"
hexmask.long 0x00 0.--31. 1. "PSER_31_0,"
group.long 0x564++0x03
line.long 0x00 "PS0SR1_B0A2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS0SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x568++0x03
line.long 0x00 "PS1SR1_B0A2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS1SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x580++0x03
line.long 0x00 "IOINTSEL1_B0A2,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group"
abitfld.long 0x00 0.--31. "IOINTSEL_31_0,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input/output mode,0x00000001=1: Interrupt input mode"
group.long 0x584++0x03
line.long 0x00 "INOUTSEL1_B0A2,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INOUTSEL_31_0,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input mode,0x00000001=1: General output mode"
group.long 0x588++0x03
line.long 0x00 "OUTDT1_B0A2,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDT_31_0,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL" "0x00000000=0: 0 is output,0x00000001=1: 1 is output"
group.long 0x58C++0x03
line.long 0x00 "INDT1_B0A2,INDTn is a register that can read the status of General-Purpose Input / Output Ports"
abitfld.long 0x00 0.--31. "INDT_31_0,Each bit reflects the value received through the corresponding port pin" "0x00000000=0: Input is 0,0x00000001=1: Input is 1"
group.long 0x590++0x03
line.long 0x00 "INTDT1_B0A2,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INTDT_31_0,Each bit indicates the input of an interrupt signal on the corresponding port pin" "0x00000000=0: No interrupt signal has been input,0x00000001=1: Interrupt signal has been input"
group.long 0x594++0x03
line.long 0x00 "INTCLR1_B0A2,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).."
abitfld.long 0x00 0.--31. "INTCLR_31_0,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register" "0x00000000=0: No effect,0x00000001=1: Interrupt display"
group.long 0x598++0x03
line.long 0x00 "INTMSK1_B0A2,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch"
abitfld.long 0x00 0.--31. "INTMSK_31_0,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block" "0x00000000=0: Interrupt is masked,0x00000001=1: Interrupt is not masked"
group.long 0x59C++0x03
line.long 0x00 "MSKCLR1_B0A2,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A"
abitfld.long 0x00 0.--31. "MSKCLR_31_0,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block" "0x00000000=0: No effect,0x00000001=1: Interrupt is not masked"
group.long 0x5A0++0x03
line.long 0x00 "POSNEG1_B0A2,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode general output mode or interrupt input mode"
abitfld.long 0x00 0.--31. "POSNEG_31_0,Selects the polarity (positive or negative logic) of each port pin" "0x00000000=0: Positive logic,0x00000001=1: Negative logic"
group.long 0x5A4++0x03
line.long 0x00 "EDGLEVEL1_B0A2,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "EDGLEVEL_31_0,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected" "0x00000000=0: Level,0x00000001=1: Edge"
group.long 0x5A8++0x03
line.long 0x00 "FILONOFF1_B0A2,FILONOFFn prevents chattering input to the port pins of each GPIO group"
abitfld.long 0x00 0.--31. "FILONOFF_31_0,Enables or disables the chattering prevention function" "0x00000000=0: Chattering prevention function is..,0x00000001=1: Chattering prevention function is.."
group.long 0x5AC++0x03
line.long 0x00 "FILCLKSEL1_B0A2,FILCLKSELn controls the division ratio of clock CP? for prevent chattering input to the port pin GPIO group"
hexmask.long 0x00 0.--31. 1. "FILCLKSEL_31_0,Set the division ratio of filter CLOCK"
group.long 0x5C0++0x03
line.long 0x00 "OUTDTSEL1_B0A2,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDTSEL_31_0,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn" "0x00000000=0: General output register is used to..,0x00000001=1: Output data high register and.."
group.long 0x5C4++0x03
line.long 0x00 "OUTDTH1_B0A2,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTH_31_0,Outputting high value data" "0x00000000=0: Invalid data,0x00000001=1: Valid data"
group.long 0x5C8++0x03
line.long 0x00 "OUTDTL1_B0A2,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTL_31_0,Outputting low value data" "0x00000000=0: Valid data,0x00000001=1: Invalid data"
group.long 0x5CC++0x03
line.long 0x00 "BOTHEDGE1_B0A2,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers"
abitfld.long 0x00 0.--31. "BOTHEDGE_31_0,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected" "0x00000000=0: One edge,0x00000001=1: Both edges"
group.long 0x5D0++0x03
line.long 0x00 "INEN1_B0A2,Create registers that can control IE in GPIO"
hexmask.long 0x00 0.--31. 1. "INEN_31_0,"
group.long 0x2000++0x03
line.long 0x00 "PMMR1_B1A0,PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers"
hexmask.long 0x00 0.--31. 1. "PMMR_31_0,Multiplexed Pin Setting Mask Writing a value to any register from among the GPSR IPSR DRVCTRL TDSEL POC PUEN PUD MODSEL DMPR PSER PSSR PINV PIS registers is enabled by writing the inverse of the value to this register"
group.long 0x2004++0x03
line.long 0x00 "PMMER1_B1A0,PMMERn / PMMERSYS performs enables / disables control of the PMMR"
abitfld.long 0x00 0.--31. "PMMER_31_0,Multiplexed Pin Setting Mask Enable" "0x00000000=0: PMMR function is disabled,0x00000001=1: PMMR function is enabled"
group.long 0x2020++0x03
line.long 0x00 "DM0PR1_B1A0,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM0PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x2024++0x03
line.long 0x00 "DM1PR1_B1A0,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM1PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x2028++0x03
line.long 0x00 "DM2PR1_B1A0,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM2PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x202C++0x03
line.long 0x00 "DM3PR1_B1A0,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM3PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x2040++0x03
line.long 0x00 "GPSR1_B1A0,GPSRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "GPSR_31_0,"
group.long 0x2060++0x03
line.long 0x00 "IP0SR1_B1A0,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP0SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x2080++0x03
line.long 0x00 "DRV0CTRL1_B1A0,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV0CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x2084++0x03
line.long 0x00 "DRV1CTRL1_B1A0,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV1CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x2088++0x03
line.long 0x00 "DRV2CTRL1_B1A0,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV2CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x208C++0x03
line.long 0x00 "DRV3CTRL1_B1A0,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV3CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x20A0++0x03
line.long 0x00 "POC1_B1A0,Each bit in POCn / POCSYS must be set according to IO voltage level that is supplied to the pin"
abitfld.long 0x00 0.--31. "POC_31_0,- For 1.8V/3.3 V" "0x00000000=0: 2.5V,0x00000001=1: 3.3V"
group.long 0x20C0++0x03
line.long 0x00 "PUEN1_B1A0,PUENn / PUENSYS performs on / off control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUEN_31_0,"
group.long 0x20E0++0x03
line.long 0x00 "PUD1_B1A0,PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUD_31_0,"
group.long 0x2100++0x03
line.long 0x00 "MODSEL_B1A0,MODSELn selects the group for multiple LSI pins with multiplexed pin functions"
hexmask.long 0x00 0.--31. 1. "MODSEL_31_0,"
group.long 0x2120++0x03
line.long 0x00 "TD0SEL_B1A0,TD*SELn / TD*SELSYS controls the driving abilities of pins in use for the SDHI"
hexmask.long 0x00 0.--31. 1. "TD0SEL_31_0,"
group.long 0x2160++0x03
line.long 0x00 "PSER1_B1A0,The register (PSERn) to enable / disable PSS Rregister"
hexmask.long 0x00 0.--31. 1. "PSER_31_0,"
group.long 0x2164++0x03
line.long 0x00 "PS0SR1_B1A0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS0SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x2168++0x03
line.long 0x00 "PS1SR1_B1A0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS1SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x2180++0x03
line.long 0x00 "IOINTSEL1_B1A0,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group"
abitfld.long 0x00 0.--31. "IOINTSEL_31_0,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input/output mode,0x00000001=1: Interrupt input mode"
group.long 0x2184++0x03
line.long 0x00 "INOUTSEL1_B1A0,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INOUTSEL_31_0,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input mode,0x00000001=1: General output mode"
group.long 0x2188++0x03
line.long 0x00 "OUTDT1_B1A0,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDT_31_0,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL" "0x00000000=0: 0 is output,0x00000001=1: 1 is output"
group.long 0x218C++0x03
line.long 0x00 "INDT1_B1A0,INDTn is a register that can read the status of General-Purpose Input / Output Ports"
abitfld.long 0x00 0.--31. "INDT_31_0,Each bit reflects the value received through the corresponding port pin" "0x00000000=0: Input is 0,0x00000001=1: Input is 1"
group.long 0x2190++0x03
line.long 0x00 "INTDT1_B1A0,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INTDT_31_0,Each bit indicates the input of an interrupt signal on the corresponding port pin" "0x00000000=0: No interrupt signal has been input,0x00000001=1: Interrupt signal has been input"
group.long 0x2194++0x03
line.long 0x00 "INTCLR1_B1A0,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).."
abitfld.long 0x00 0.--31. "INTCLR_31_0,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register" "0x00000000=0: No effect,0x00000001=1: Interrupt display"
group.long 0x2198++0x03
line.long 0x00 "INTMSK1_B1A0,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch"
abitfld.long 0x00 0.--31. "INTMSK_31_0,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block" "0x00000000=0: Interrupt is masked,0x00000001=1: Interrupt is not masked"
group.long 0x219C++0x03
line.long 0x00 "MSKCLR1_B1A0,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A"
abitfld.long 0x00 0.--31. "MSKCLR_31_0,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block" "0x00000000=0: No effect,0x00000001=1: Interrupt is not masked"
group.long 0x21A0++0x03
line.long 0x00 "POSNEG1_B1A0,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode general output mode or interrupt input mode"
abitfld.long 0x00 0.--31. "POSNEG_31_0,Selects the polarity (positive or negative logic) of each port pin" "0x00000000=0: Positive logic,0x00000001=1: Negative logic"
group.long 0x21A4++0x03
line.long 0x00 "EDGLEVEL1_B1A0,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "EDGLEVEL_31_0,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected" "0x00000000=0: Level,0x00000001=1: Edge"
group.long 0x21A8++0x03
line.long 0x00 "FILONOFF1_B1A0,FILONOFFn prevents chattering input to the port pins of each GPIO group"
abitfld.long 0x00 0.--31. "FILONOFF_31_0,Enables or disables the chattering prevention function" "0x00000000=0: Chattering prevention function is..,0x00000001=1: Chattering prevention function is.."
group.long 0x21AC++0x03
line.long 0x00 "FILCLKSEL1_B1A0,FILCLKSELn controls the division ratio of clock CP? for prevent chattering input to the port pin GPIO group"
hexmask.long 0x00 0.--31. 1. "FILCLKSEL_31_0,Set the division ratio of filter CLOCK"
group.long 0x21C0++0x03
line.long 0x00 "OUTDTSEL1_B1A0,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDTSEL_31_0,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn" "0x00000000=0: General output register is used to..,0x00000001=1: Output data high register and.."
group.long 0x21C4++0x03
line.long 0x00 "OUTDTH1_B1A0,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTH_31_0,Outputting high value data" "0x00000000=0: Invalid data,0x00000001=1: Valid data"
group.long 0x21C8++0x03
line.long 0x00 "OUTDTL1_B1A0,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTL_31_0,Outputting low value data" "0x00000000=0: Valid data,0x00000001=1: Invalid data"
group.long 0x21CC++0x03
line.long 0x00 "BOTHEDGE1_B1A0,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers"
abitfld.long 0x00 0.--31. "BOTHEDGE_31_0,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected" "0x00000000=0: One edge,0x00000001=1: Both edges"
group.long 0x21D0++0x03
line.long 0x00 "INEN1_B1A0,Create registers that can control IE in GPIO"
hexmask.long 0x00 0.--31. 1. "INEN_31_0,"
group.long 0x2200++0x03
line.long 0x00 "PMMR1_B1A1,PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers"
hexmask.long 0x00 0.--31. 1. "PMMR_31_0,Multiplexed Pin Setting Mask Writing a value to any register from among the GPSR IPSR DRVCTRL TDSEL POC PUEN PUD MODSEL DMPR PSER PSSR PINV PIS registers is enabled by writing the inverse of the value to this register"
group.long 0x2204++0x03
line.long 0x00 "PMMER1_B1A1,PMMERn / PMMERSYS performs enables / disables control of the PMMR"
abitfld.long 0x00 0.--31. "PMMER_31_0,Multiplexed Pin Setting Mask Enable" "0x00000000=0: PMMR function is disabled,0x00000001=1: PMMR function is enabled"
group.long 0x2220++0x03
line.long 0x00 "DM0PR1_B1A1,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM0PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x2224++0x03
line.long 0x00 "DM1PR1_B1A1,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM1PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x2228++0x03
line.long 0x00 "DM2PR1_B1A1,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM2PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x222C++0x03
line.long 0x00 "DM3PR1_B1A1,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM3PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x2240++0x03
line.long 0x00 "GPSR1_B1A1,GPSRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "GPSR_31_0,"
group.long 0x2260++0x03
line.long 0x00 "IP0SR1_B1A1,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP0SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x2280++0x03
line.long 0x00 "DRV0CTRL1_B1A1,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV0CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x2284++0x03
line.long 0x00 "DRV1CTRL1_B1A1,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV1CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x2288++0x03
line.long 0x00 "DRV2CTRL1_B1A1,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV2CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x228C++0x03
line.long 0x00 "DRV3CTRL1_B1A1,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV3CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x22A0++0x03
line.long 0x00 "POC1_B1A1,Each bit in POCn / POCSYS must be set according to IO voltage level that is supplied to the pin"
abitfld.long 0x00 0.--31. "POC_31_0,- For 1.8V/3.3 V" "0x00000000=0: 2.5V,0x00000001=1: 3.3V"
group.long 0x22C0++0x03
line.long 0x00 "PUEN1_B1A1,PUENn / PUENSYS performs on / off control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUEN_31_0,"
group.long 0x22E0++0x03
line.long 0x00 "PUD1_B1A1,PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUD_31_0,"
group.long 0x2300++0x03
line.long 0x00 "MODSEL_B1A1,MODSELn selects the group for multiple LSI pins with multiplexed pin functions"
hexmask.long 0x00 0.--31. 1. "MODSEL_31_0,"
group.long 0x2320++0x03
line.long 0x00 "TD0SEL_B1A1,TD*SELn / TD*SELSYS controls the driving abilities of pins in use for the SDHI"
hexmask.long 0x00 0.--31. 1. "TD0SEL_31_0,"
group.long 0x2360++0x03
line.long 0x00 "PSER1_B1A1,The register (PSERn) to enable / disable PSS Rregister"
hexmask.long 0x00 0.--31. 1. "PSER_31_0,"
group.long 0x2364++0x03
line.long 0x00 "PS0SR1_B1A1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS0SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x2368++0x03
line.long 0x00 "PS1SR1_B1A1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS1SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x2380++0x03
line.long 0x00 "IOINTSEL1_B1A1,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group"
abitfld.long 0x00 0.--31. "IOINTSEL_31_0,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input/output mode,0x00000001=1: Interrupt input mode"
group.long 0x2384++0x03
line.long 0x00 "INOUTSEL1_B1A1,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INOUTSEL_31_0,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input mode,0x00000001=1: General output mode"
group.long 0x2388++0x03
line.long 0x00 "OUTDT1_B1A1,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDT_31_0,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL" "0x00000000=0: 0 is output,0x00000001=1: 1 is output"
group.long 0x238C++0x03
line.long 0x00 "INDT1_B1A1,INDTn is a register that can read the status of General-Purpose Input / Output Ports"
abitfld.long 0x00 0.--31. "INDT_31_0,Each bit reflects the value received through the corresponding port pin" "0x00000000=0: Input is 0,0x00000001=1: Input is 1"
group.long 0x2390++0x03
line.long 0x00 "INTDT1_B1A1,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INTDT_31_0,Each bit indicates the input of an interrupt signal on the corresponding port pin" "0x00000000=0: No interrupt signal has been input,0x00000001=1: Interrupt signal has been input"
group.long 0x2394++0x03
line.long 0x00 "INTCLR1_B1A1,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).."
abitfld.long 0x00 0.--31. "INTCLR_31_0,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register" "0x00000000=0: No effect,0x00000001=1: Interrupt display"
group.long 0x2398++0x03
line.long 0x00 "INTMSK1_B1A1,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch"
abitfld.long 0x00 0.--31. "INTMSK_31_0,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block" "0x00000000=0: Interrupt is masked,0x00000001=1: Interrupt is not masked"
group.long 0x239C++0x03
line.long 0x00 "MSKCLR1_B1A1,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A"
abitfld.long 0x00 0.--31. "MSKCLR_31_0,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block" "0x00000000=0: No effect,0x00000001=1: Interrupt is not masked"
group.long 0x23A0++0x03
line.long 0x00 "POSNEG1_B1A1,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode general output mode or interrupt input mode"
abitfld.long 0x00 0.--31. "POSNEG_31_0,Selects the polarity (positive or negative logic) of each port pin" "0x00000000=0: Positive logic,0x00000001=1: Negative logic"
group.long 0x23A4++0x03
line.long 0x00 "EDGLEVEL1_B1A1,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "EDGLEVEL_31_0,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected" "0x00000000=0: Level,0x00000001=1: Edge"
group.long 0x23A8++0x03
line.long 0x00 "FILONOFF1_B1A1,FILONOFFn prevents chattering input to the port pins of each GPIO group"
abitfld.long 0x00 0.--31. "FILONOFF_31_0,Enables or disables the chattering prevention function" "0x00000000=0: Chattering prevention function is..,0x00000001=1: Chattering prevention function is.."
group.long 0x23AC++0x03
line.long 0x00 "FILCLKSEL1_B1A1,FILCLKSELn controls the division ratio of clock CP? for prevent chattering input to the port pin GPIO group"
hexmask.long 0x00 0.--31. 1. "FILCLKSEL_31_0,Set the division ratio of filter CLOCK"
group.long 0x23C0++0x03
line.long 0x00 "OUTDTSEL1_B1A1,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDTSEL_31_0,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn" "0x00000000=0: General output register is used to..,0x00000001=1: Output data high register and.."
group.long 0x23C4++0x03
line.long 0x00 "OUTDTH1_B1A1,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTH_31_0,Outputting high value data" "0x00000000=0: Invalid data,0x00000001=1: Valid data"
group.long 0x23C8++0x03
line.long 0x00 "OUTDTL1_B1A1,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTL_31_0,Outputting low value data" "0x00000000=0: Valid data,0x00000001=1: Invalid data"
group.long 0x23CC++0x03
line.long 0x00 "BOTHEDGE1_B1A1,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers"
abitfld.long 0x00 0.--31. "BOTHEDGE_31_0,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected" "0x00000000=0: One edge,0x00000001=1: Both edges"
group.long 0x23D0++0x03
line.long 0x00 "INEN1_B1A1,Create registers that can control IE in GPIO"
hexmask.long 0x00 0.--31. 1. "INEN_31_0,"
group.long 0x2400++0x03
line.long 0x00 "PMMR1_B1A2,PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers"
hexmask.long 0x00 0.--31. 1. "PMMR_31_0,Multiplexed Pin Setting Mask Writing a value to any register from among the GPSR IPSR DRVCTRL TDSEL POC PUEN PUD MODSEL DMPR PSER PSSR PINV PIS registers is enabled by writing the inverse of the value to this register"
group.long 0x2404++0x03
line.long 0x00 "PMMER1_B1A2,PMMERn / PMMERSYS performs enables / disables control of the PMMR"
abitfld.long 0x00 0.--31. "PMMER_31_0,Multiplexed Pin Setting Mask Enable" "0x00000000=0: PMMR function is disabled,0x00000001=1: PMMR function is enabled"
group.long 0x2420++0x03
line.long 0x00 "DM0PR1_B1A2,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM0PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x2424++0x03
line.long 0x00 "DM1PR1_B1A2,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM1PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x2428++0x03
line.long 0x00 "DM2PR1_B1A2,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM2PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x242C++0x03
line.long 0x00 "DM3PR1_B1A2,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM3PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x2440++0x03
line.long 0x00 "GPSR1_B1A2,GPSRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "GPSR_31_0,"
group.long 0x2460++0x03
line.long 0x00 "IP0SR1_B1A2,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP0SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x2480++0x03
line.long 0x00 "DRV0CTRL1_B1A2,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV0CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x2484++0x03
line.long 0x00 "DRV1CTRL1_B1A2,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV1CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x2488++0x03
line.long 0x00 "DRV2CTRL1_B1A2,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV2CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x248C++0x03
line.long 0x00 "DRV3CTRL1_B1A2,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV3CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x24A0++0x03
line.long 0x00 "POC1_B1A2,Each bit in POCn / POCSYS must be set according to IO voltage level that is supplied to the pin"
abitfld.long 0x00 0.--31. "POC_31_0,- For 1.8V/3.3 V" "0x00000000=0: 2.5V,0x00000001=1: 3.3V"
group.long 0x24C0++0x03
line.long 0x00 "PUEN1_B1A2,PUENn / PUENSYS performs on / off control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUEN_31_0,"
group.long 0x24E0++0x03
line.long 0x00 "PUD1_B1A2,PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUD_31_0,"
group.long 0x2500++0x03
line.long 0x00 "MODSEL_B1A2,MODSELn selects the group for multiple LSI pins with multiplexed pin functions"
hexmask.long 0x00 0.--31. 1. "MODSEL_31_0,"
group.long 0x2520++0x03
line.long 0x00 "TD0SEL_B1A2,TD*SELn / TD*SELSYS controls the driving abilities of pins in use for the SDHI"
hexmask.long 0x00 0.--31. 1. "TD0SEL_31_0,"
group.long 0x2560++0x03
line.long 0x00 "PSER1_B1A2,The register (PSERn) to enable / disable PSS Rregister"
hexmask.long 0x00 0.--31. 1. "PSER_31_0,"
group.long 0x2564++0x03
line.long 0x00 "PS0SR1_B1A2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS0SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x2568++0x03
line.long 0x00 "PS1SR1_B1A2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS1SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x2580++0x03
line.long 0x00 "IOINTSEL1_B1A2,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group"
abitfld.long 0x00 0.--31. "IOINTSEL_31_0,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input/output mode,0x00000001=1: Interrupt input mode"
group.long 0x2584++0x03
line.long 0x00 "INOUTSEL1_B1A2,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INOUTSEL_31_0,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input mode,0x00000001=1: General output mode"
group.long 0x2588++0x03
line.long 0x00 "OUTDT1_B1A2,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDT_31_0,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL" "0x00000000=0: 0 is output,0x00000001=1: 1 is output"
group.long 0x258C++0x03
line.long 0x00 "INDT1_B1A2,INDTn is a register that can read the status of General-Purpose Input / Output Ports"
abitfld.long 0x00 0.--31. "INDT_31_0,Each bit reflects the value received through the corresponding port pin" "0x00000000=0: Input is 0,0x00000001=1: Input is 1"
group.long 0x2590++0x03
line.long 0x00 "INTDT1_B1A2,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INTDT_31_0,Each bit indicates the input of an interrupt signal on the corresponding port pin" "0x00000000=0: No interrupt signal has been input,0x00000001=1: Interrupt signal has been input"
group.long 0x2594++0x03
line.long 0x00 "INTCLR1_B1A2,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).."
abitfld.long 0x00 0.--31. "INTCLR_31_0,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register" "0x00000000=0: No effect,0x00000001=1: Interrupt display"
group.long 0x2598++0x03
line.long 0x00 "INTMSK1_B1A2,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch"
abitfld.long 0x00 0.--31. "INTMSK_31_0,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block" "0x00000000=0: Interrupt is masked,0x00000001=1: Interrupt is not masked"
group.long 0x259C++0x03
line.long 0x00 "MSKCLR1_B1A2,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A"
abitfld.long 0x00 0.--31. "MSKCLR_31_0,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block" "0x00000000=0: No effect,0x00000001=1: Interrupt is not masked"
group.long 0x25A0++0x03
line.long 0x00 "POSNEG1_B1A2,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode general output mode or interrupt input mode"
abitfld.long 0x00 0.--31. "POSNEG_31_0,Selects the polarity (positive or negative logic) of each port pin" "0x00000000=0: Positive logic,0x00000001=1: Negative logic"
group.long 0x25A4++0x03
line.long 0x00 "EDGLEVEL1_B1A2,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "EDGLEVEL_31_0,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected" "0x00000000=0: Level,0x00000001=1: Edge"
group.long 0x25A8++0x03
line.long 0x00 "FILONOFF1_B1A2,FILONOFFn prevents chattering input to the port pins of each GPIO group"
abitfld.long 0x00 0.--31. "FILONOFF_31_0,Enables or disables the chattering prevention function" "0x00000000=0: Chattering prevention function is..,0x00000001=1: Chattering prevention function is.."
group.long 0x25AC++0x03
line.long 0x00 "FILCLKSEL1_B1A2,FILCLKSELn controls the division ratio of clock CP? for prevent chattering input to the port pin GPIO group"
hexmask.long 0x00 0.--31. 1. "FILCLKSEL_31_0,Set the division ratio of filter CLOCK"
group.long 0x25C0++0x03
line.long 0x00 "OUTDTSEL1_B1A2,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDTSEL_31_0,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn" "0x00000000=0: General output register is used to..,0x00000001=1: Output data high register and.."
group.long 0x25C4++0x03
line.long 0x00 "OUTDTH1_B1A2,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTH_31_0,Outputting high value data" "0x00000000=0: Invalid data,0x00000001=1: Valid data"
group.long 0x25C8++0x03
line.long 0x00 "OUTDTL1_B1A2,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTL_31_0,Outputting low value data" "0x00000000=0: Valid data,0x00000001=1: Invalid data"
group.long 0x25CC++0x03
line.long 0x00 "BOTHEDGE1_B1A2,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers"
abitfld.long 0x00 0.--31. "BOTHEDGE_31_0,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected" "0x00000000=0: One edge,0x00000001=1: Both edges"
group.long 0x25D0++0x03
line.long 0x00 "INEN1_B1A2,Create registers that can control IE in GPIO"
hexmask.long 0x00 0.--31. 1. "INEN_31_0,"
group.long 0x4000++0x03
line.long 0x00 "PMMR1_B2A0,PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers"
hexmask.long 0x00 0.--31. 1. "PMMR_31_0,Multiplexed Pin Setting Mask Writing a value to any register from among the GPSR IPSR DRVCTRL TDSEL POC PUEN PUD MODSEL DMPR PSER PSSR PINV PIS registers is enabled by writing the inverse of the value to this register"
group.long 0x4004++0x03
line.long 0x00 "PMMER1_B2A0,PMMERn / PMMERSYS performs enables / disables control of the PMMR"
abitfld.long 0x00 0.--31. "PMMER_31_0,Multiplexed Pin Setting Mask Enable" "0x00000000=0: PMMR function is disabled,0x00000001=1: PMMR function is enabled"
group.long 0x4020++0x03
line.long 0x00 "DM0PR1_B2A0,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM0PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x4024++0x03
line.long 0x00 "DM1PR1_B2A0,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM1PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x4028++0x03
line.long 0x00 "DM2PR1_B2A0,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM2PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x402C++0x03
line.long 0x00 "DM3PR1_B2A0,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM3PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x4040++0x03
line.long 0x00 "GPSR1_B2A0,GPSRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "GPSR_31_0,"
group.long 0x4060++0x03
line.long 0x00 "IP0SR1_B2A0,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP0SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x4080++0x03
line.long 0x00 "DRV0CTRL1_B2A0,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV0CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x4084++0x03
line.long 0x00 "DRV1CTRL1_B2A0,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV1CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x4088++0x03
line.long 0x00 "DRV2CTRL1_B2A0,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV2CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x408C++0x03
line.long 0x00 "DRV3CTRL1_B2A0,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV3CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x40A0++0x03
line.long 0x00 "POC1_B2A0,Each bit in POCn / POCSYS must be set according to IO voltage level that is supplied to the pin"
abitfld.long 0x00 0.--31. "POC_31_0,- For 1.8V/3.3 V" "0x00000000=0: 2.5V,0x00000001=1: 3.3V"
group.long 0x40C0++0x03
line.long 0x00 "PUEN1_B2A0,PUENn / PUENSYS performs on / off control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUEN_31_0,"
group.long 0x40E0++0x03
line.long 0x00 "PUD1_B2A0,PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUD_31_0,"
group.long 0x4100++0x03
line.long 0x00 "MODSEL_B2A0,MODSELn selects the group for multiple LSI pins with multiplexed pin functions"
hexmask.long 0x00 0.--31. 1. "MODSEL_31_0,"
group.long 0x4120++0x03
line.long 0x00 "TD0SEL_B2A0,TD*SELn / TD*SELSYS controls the driving abilities of pins in use for the SDHI"
hexmask.long 0x00 0.--31. 1. "TD0SEL_31_0,"
group.long 0x4160++0x03
line.long 0x00 "PSER1_B2A0,The register (PSERn) to enable / disable PSS Rregister"
hexmask.long 0x00 0.--31. 1. "PSER_31_0,"
group.long 0x4164++0x03
line.long 0x00 "PS0SR1_B2A0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS0SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x4168++0x03
line.long 0x00 "PS1SR1_B2A0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS1SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x4180++0x03
line.long 0x00 "IOINTSEL1_B2A0,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group"
abitfld.long 0x00 0.--31. "IOINTSEL_31_0,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input/output mode,0x00000001=1: Interrupt input mode"
group.long 0x4184++0x03
line.long 0x00 "INOUTSEL1_B2A0,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INOUTSEL_31_0,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input mode,0x00000001=1: General output mode"
group.long 0x4188++0x03
line.long 0x00 "OUTDT1_B2A0,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDT_31_0,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL" "0x00000000=0: 0 is output,0x00000001=1: 1 is output"
group.long 0x418C++0x03
line.long 0x00 "INDT1_B2A0,INDTn is a register that can read the status of General-Purpose Input / Output Ports"
abitfld.long 0x00 0.--31. "INDT_31_0,Each bit reflects the value received through the corresponding port pin" "0x00000000=0: Input is 0,0x00000001=1: Input is 1"
group.long 0x4190++0x03
line.long 0x00 "INTDT1_B2A0,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INTDT_31_0,Each bit indicates the input of an interrupt signal on the corresponding port pin" "0x00000000=0: No interrupt signal has been input,0x00000001=1: Interrupt signal has been input"
group.long 0x4194++0x03
line.long 0x00 "INTCLR1_B2A0,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).."
abitfld.long 0x00 0.--31. "INTCLR_31_0,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register" "0x00000000=0: No effect,0x00000001=1: Interrupt display"
group.long 0x4198++0x03
line.long 0x00 "INTMSK1_B2A0,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch"
abitfld.long 0x00 0.--31. "INTMSK_31_0,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block" "0x00000000=0: Interrupt is masked,0x00000001=1: Interrupt is not masked"
group.long 0x419C++0x03
line.long 0x00 "MSKCLR1_B2A0,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A"
abitfld.long 0x00 0.--31. "MSKCLR_31_0,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block" "0x00000000=0: No effect,0x00000001=1: Interrupt is not masked"
group.long 0x41A0++0x03
line.long 0x00 "POSNEG1_B2A0,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode general output mode or interrupt input mode"
abitfld.long 0x00 0.--31. "POSNEG_31_0,Selects the polarity (positive or negative logic) of each port pin" "0x00000000=0: Positive logic,0x00000001=1: Negative logic"
group.long 0x41A4++0x03
line.long 0x00 "EDGLEVEL1_B2A0,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "EDGLEVEL_31_0,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected" "0x00000000=0: Level,0x00000001=1: Edge"
group.long 0x41A8++0x03
line.long 0x00 "FILONOFF1_B2A0,FILONOFFn prevents chattering input to the port pins of each GPIO group"
abitfld.long 0x00 0.--31. "FILONOFF_31_0,Enables or disables the chattering prevention function" "0x00000000=0: Chattering prevention function is..,0x00000001=1: Chattering prevention function is.."
group.long 0x41AC++0x03
line.long 0x00 "FILCLKSEL1_B2A0,FILCLKSELn controls the division ratio of clock CP? for prevent chattering input to the port pin GPIO group"
hexmask.long 0x00 0.--31. 1. "FILCLKSEL_31_0,Set the division ratio of filter CLOCK"
group.long 0x41C0++0x03
line.long 0x00 "OUTDTSEL1_B2A0,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDTSEL_31_0,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn" "0x00000000=0: General output register is used to..,0x00000001=1: Output data high register and.."
group.long 0x41C4++0x03
line.long 0x00 "OUTDTH1_B2A0,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTH_31_0,Outputting high value data" "0x00000000=0: Invalid data,0x00000001=1: Valid data"
group.long 0x41C8++0x03
line.long 0x00 "OUTDTL1_B2A0,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTL_31_0,Outputting low value data" "0x00000000=0: Valid data,0x00000001=1: Invalid data"
group.long 0x41CC++0x03
line.long 0x00 "BOTHEDGE1_B2A0,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers"
abitfld.long 0x00 0.--31. "BOTHEDGE_31_0,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected" "0x00000000=0: One edge,0x00000001=1: Both edges"
group.long 0x41D0++0x03
line.long 0x00 "INEN1_B2A0,Create registers that can control IE in GPIO"
hexmask.long 0x00 0.--31. 1. "INEN_31_0,"
group.long 0x4200++0x03
line.long 0x00 "PMMR1_B2A1,PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers"
hexmask.long 0x00 0.--31. 1. "PMMR_31_0,Multiplexed Pin Setting Mask Writing a value to any register from among the GPSR IPSR DRVCTRL TDSEL POC PUEN PUD MODSEL DMPR PSER PSSR PINV PIS registers is enabled by writing the inverse of the value to this register"
group.long 0x4204++0x03
line.long 0x00 "PMMER1_B2A1,PMMERn / PMMERSYS performs enables / disables control of the PMMR"
abitfld.long 0x00 0.--31. "PMMER_31_0,Multiplexed Pin Setting Mask Enable" "0x00000000=0: PMMR function is disabled,0x00000001=1: PMMR function is enabled"
group.long 0x4220++0x03
line.long 0x00 "DM0PR1_B2A1,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM0PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x4224++0x03
line.long 0x00 "DM1PR1_B2A1,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM1PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x4228++0x03
line.long 0x00 "DM2PR1_B2A1,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM2PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x422C++0x03
line.long 0x00 "DM3PR1_B2A1,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM3PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x4240++0x03
line.long 0x00 "GPSR1_B2A1,GPSRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "GPSR_31_0,"
group.long 0x4260++0x03
line.long 0x00 "IP0SR1_B2A1,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP0SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x4280++0x03
line.long 0x00 "DRV0CTRL1_B2A1,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV0CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x4284++0x03
line.long 0x00 "DRV1CTRL1_B2A1,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV1CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x4288++0x03
line.long 0x00 "DRV2CTRL1_B2A1,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV2CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x428C++0x03
line.long 0x00 "DRV3CTRL1_B2A1,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV3CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x42A0++0x03
line.long 0x00 "POC1_B2A1,Each bit in POCn / POCSYS must be set according to IO voltage level that is supplied to the pin"
abitfld.long 0x00 0.--31. "POC_31_0,- For 1.8V/3.3 V" "0x00000000=0: 2.5V,0x00000001=1: 3.3V"
group.long 0x42C0++0x03
line.long 0x00 "PUEN1_B2A1,PUENn / PUENSYS performs on / off control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUEN_31_0,"
group.long 0x42E0++0x03
line.long 0x00 "PUD1_B2A1,PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUD_31_0,"
group.long 0x4300++0x03
line.long 0x00 "MODSEL_B2A1,MODSELn selects the group for multiple LSI pins with multiplexed pin functions"
hexmask.long 0x00 0.--31. 1. "MODSEL_31_0,"
group.long 0x4320++0x03
line.long 0x00 "TD0SEL_B2A1,TD*SELn / TD*SELSYS controls the driving abilities of pins in use for the SDHI"
hexmask.long 0x00 0.--31. 1. "TD0SEL_31_0,"
group.long 0x4360++0x03
line.long 0x00 "PSER1_B2A1,The register (PSERn) to enable / disable PSS Rregister"
hexmask.long 0x00 0.--31. 1. "PSER_31_0,"
group.long 0x4364++0x03
line.long 0x00 "PS0SR1_B2A1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS0SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x4368++0x03
line.long 0x00 "PS1SR1_B2A1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS1SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x4380++0x03
line.long 0x00 "IOINTSEL1_B2A1,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group"
abitfld.long 0x00 0.--31. "IOINTSEL_31_0,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input/output mode,0x00000001=1: Interrupt input mode"
group.long 0x4384++0x03
line.long 0x00 "INOUTSEL1_B2A1,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INOUTSEL_31_0,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input mode,0x00000001=1: General output mode"
group.long 0x4388++0x03
line.long 0x00 "OUTDT1_B2A1,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDT_31_0,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL" "0x00000000=0: 0 is output,0x00000001=1: 1 is output"
group.long 0x438C++0x03
line.long 0x00 "INDT1_B2A1,INDTn is a register that can read the status of General-Purpose Input / Output Ports"
abitfld.long 0x00 0.--31. "INDT_31_0,Each bit reflects the value received through the corresponding port pin" "0x00000000=0: Input is 0,0x00000001=1: Input is 1"
group.long 0x4390++0x03
line.long 0x00 "INTDT1_B2A1,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INTDT_31_0,Each bit indicates the input of an interrupt signal on the corresponding port pin" "0x00000000=0: No interrupt signal has been input,0x00000001=1: Interrupt signal has been input"
group.long 0x4394++0x03
line.long 0x00 "INTCLR1_B2A1,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).."
abitfld.long 0x00 0.--31. "INTCLR_31_0,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register" "0x00000000=0: No effect,0x00000001=1: Interrupt display"
group.long 0x4398++0x03
line.long 0x00 "INTMSK1_B2A1,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch"
abitfld.long 0x00 0.--31. "INTMSK_31_0,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block" "0x00000000=0: Interrupt is masked,0x00000001=1: Interrupt is not masked"
group.long 0x439C++0x03
line.long 0x00 "MSKCLR1_B2A1,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A"
abitfld.long 0x00 0.--31. "MSKCLR_31_0,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block" "0x00000000=0: No effect,0x00000001=1: Interrupt is not masked"
group.long 0x43A0++0x03
line.long 0x00 "POSNEG1_B2A1,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode general output mode or interrupt input mode"
abitfld.long 0x00 0.--31. "POSNEG_31_0,Selects the polarity (positive or negative logic) of each port pin" "0x00000000=0: Positive logic,0x00000001=1: Negative logic"
group.long 0x43A4++0x03
line.long 0x00 "EDGLEVEL1_B2A1,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "EDGLEVEL_31_0,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected" "0x00000000=0: Level,0x00000001=1: Edge"
group.long 0x43A8++0x03
line.long 0x00 "FILONOFF1_B2A1,FILONOFFn prevents chattering input to the port pins of each GPIO group"
abitfld.long 0x00 0.--31. "FILONOFF_31_0,Enables or disables the chattering prevention function" "0x00000000=0: Chattering prevention function is..,0x00000001=1: Chattering prevention function is.."
group.long 0x43AC++0x03
line.long 0x00 "FILCLKSEL1_B2A1,FILCLKSELn controls the division ratio of clock CP? for prevent chattering input to the port pin GPIO group"
hexmask.long 0x00 0.--31. 1. "FILCLKSEL_31_0,Set the division ratio of filter CLOCK"
group.long 0x43C0++0x03
line.long 0x00 "OUTDTSEL1_B2A1,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDTSEL_31_0,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn" "0x00000000=0: General output register is used to..,0x00000001=1: Output data high register and.."
group.long 0x43C4++0x03
line.long 0x00 "OUTDTH1_B2A1,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTH_31_0,Outputting high value data" "0x00000000=0: Invalid data,0x00000001=1: Valid data"
group.long 0x43C8++0x03
line.long 0x00 "OUTDTL1_B2A1,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTL_31_0,Outputting low value data" "0x00000000=0: Valid data,0x00000001=1: Invalid data"
group.long 0x43CC++0x03
line.long 0x00 "BOTHEDGE1_B2A1,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers"
abitfld.long 0x00 0.--31. "BOTHEDGE_31_0,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected" "0x00000000=0: One edge,0x00000001=1: Both edges"
group.long 0x43D0++0x03
line.long 0x00 "INEN1_B2A1,Create registers that can control IE in GPIO"
hexmask.long 0x00 0.--31. 1. "INEN_31_0,"
group.long 0x4400++0x03
line.long 0x00 "PMMR1_B2A2,PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers"
hexmask.long 0x00 0.--31. 1. "PMMR_31_0,Multiplexed Pin Setting Mask Writing a value to any register from among the GPSR IPSR DRVCTRL TDSEL POC PUEN PUD MODSEL DMPR PSER PSSR PINV PIS registers is enabled by writing the inverse of the value to this register"
group.long 0x4404++0x03
line.long 0x00 "PMMER1_B2A2,PMMERn / PMMERSYS performs enables / disables control of the PMMR"
abitfld.long 0x00 0.--31. "PMMER_31_0,Multiplexed Pin Setting Mask Enable" "0x00000000=0: PMMR function is disabled,0x00000001=1: PMMR function is enabled"
group.long 0x4420++0x03
line.long 0x00 "DM0PR1_B2A2,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM0PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x4424++0x03
line.long 0x00 "DM1PR1_B2A2,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM1PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x4428++0x03
line.long 0x00 "DM2PR1_B2A2,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM2PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x442C++0x03
line.long 0x00 "DM3PR1_B2A2,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM3PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x4440++0x03
line.long 0x00 "GPSR1_B2A2,GPSRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "GPSR_31_0,"
group.long 0x4460++0x03
line.long 0x00 "IP0SR1_B2A2,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP0SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x4480++0x03
line.long 0x00 "DRV0CTRL1_B2A2,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV0CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x4484++0x03
line.long 0x00 "DRV1CTRL1_B2A2,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV1CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x4488++0x03
line.long 0x00 "DRV2CTRL1_B2A2,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV2CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x448C++0x03
line.long 0x00 "DRV3CTRL1_B2A2,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV3CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x44A0++0x03
line.long 0x00 "POC1_B2A2,Each bit in POCn / POCSYS must be set according to IO voltage level that is supplied to the pin"
abitfld.long 0x00 0.--31. "POC_31_0,- For 1.8V/3.3 V" "0x00000000=0: 2.5V,0x00000001=1: 3.3V"
group.long 0x44C0++0x03
line.long 0x00 "PUEN1_B2A2,PUENn / PUENSYS performs on / off control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUEN_31_0,"
group.long 0x44E0++0x03
line.long 0x00 "PUD1_B2A2,PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUD_31_0,"
group.long 0x4500++0x03
line.long 0x00 "MODSEL_B2A2,MODSELn selects the group for multiple LSI pins with multiplexed pin functions"
hexmask.long 0x00 0.--31. 1. "MODSEL_31_0,"
group.long 0x4520++0x03
line.long 0x00 "TD0SEL_B2A2,TD*SELn / TD*SELSYS controls the driving abilities of pins in use for the SDHI"
hexmask.long 0x00 0.--31. 1. "TD0SEL_31_0,"
group.long 0x4560++0x03
line.long 0x00 "PSER1_B2A2,The register (PSERn) to enable / disable PSS Rregister"
hexmask.long 0x00 0.--31. 1. "PSER_31_0,"
group.long 0x4564++0x03
line.long 0x00 "PS0SR1_B2A2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS0SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x4568++0x03
line.long 0x00 "PS1SR1_B2A2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS1SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x4580++0x03
line.long 0x00 "IOINTSEL1_B2A2,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group"
abitfld.long 0x00 0.--31. "IOINTSEL_31_0,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input/output mode,0x00000001=1: Interrupt input mode"
group.long 0x4584++0x03
line.long 0x00 "INOUTSEL1_B2A2,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INOUTSEL_31_0,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input mode,0x00000001=1: General output mode"
group.long 0x4588++0x03
line.long 0x00 "OUTDT1_B2A2,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDT_31_0,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL" "0x00000000=0: 0 is output,0x00000001=1: 1 is output"
group.long 0x458C++0x03
line.long 0x00 "INDT1_B2A2,INDTn is a register that can read the status of General-Purpose Input / Output Ports"
abitfld.long 0x00 0.--31. "INDT_31_0,Each bit reflects the value received through the corresponding port pin" "0x00000000=0: Input is 0,0x00000001=1: Input is 1"
group.long 0x4590++0x03
line.long 0x00 "INTDT1_B2A2,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INTDT_31_0,Each bit indicates the input of an interrupt signal on the corresponding port pin" "0x00000000=0: No interrupt signal has been input,0x00000001=1: Interrupt signal has been input"
group.long 0x4594++0x03
line.long 0x00 "INTCLR1_B2A2,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).."
abitfld.long 0x00 0.--31. "INTCLR_31_0,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register" "0x00000000=0: No effect,0x00000001=1: Interrupt display"
group.long 0x4598++0x03
line.long 0x00 "INTMSK1_B2A2,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch"
abitfld.long 0x00 0.--31. "INTMSK_31_0,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block" "0x00000000=0: Interrupt is masked,0x00000001=1: Interrupt is not masked"
group.long 0x459C++0x03
line.long 0x00 "MSKCLR1_B2A2,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A"
abitfld.long 0x00 0.--31. "MSKCLR_31_0,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block" "0x00000000=0: No effect,0x00000001=1: Interrupt is not masked"
group.long 0x45A0++0x03
line.long 0x00 "POSNEG1_B2A2,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode general output mode or interrupt input mode"
abitfld.long 0x00 0.--31. "POSNEG_31_0,Selects the polarity (positive or negative logic) of each port pin" "0x00000000=0: Positive logic,0x00000001=1: Negative logic"
group.long 0x45A4++0x03
line.long 0x00 "EDGLEVEL1_B2A2,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "EDGLEVEL_31_0,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected" "0x00000000=0: Level,0x00000001=1: Edge"
group.long 0x45A8++0x03
line.long 0x00 "FILONOFF1_B2A2,FILONOFFn prevents chattering input to the port pins of each GPIO group"
abitfld.long 0x00 0.--31. "FILONOFF_31_0,Enables or disables the chattering prevention function" "0x00000000=0: Chattering prevention function is..,0x00000001=1: Chattering prevention function is.."
group.long 0x45AC++0x03
line.long 0x00 "FILCLKSEL1_B2A2,FILCLKSELn controls the division ratio of clock CP? for prevent chattering input to the port pin GPIO group"
hexmask.long 0x00 0.--31. 1. "FILCLKSEL_31_0,Set the division ratio of filter CLOCK"
group.long 0x45C0++0x03
line.long 0x00 "OUTDTSEL1_B2A2,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDTSEL_31_0,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn" "0x00000000=0: General output register is used to..,0x00000001=1: Output data high register and.."
group.long 0x45C4++0x03
line.long 0x00 "OUTDTH1_B2A2,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTH_31_0,Outputting high value data" "0x00000000=0: Invalid data,0x00000001=1: Valid data"
group.long 0x45C8++0x03
line.long 0x00 "OUTDTL1_B2A2,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTL_31_0,Outputting low value data" "0x00000000=0: Valid data,0x00000001=1: Invalid data"
group.long 0x45CC++0x03
line.long 0x00 "BOTHEDGE1_B2A2,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers"
abitfld.long 0x00 0.--31. "BOTHEDGE_31_0,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected" "0x00000000=0: One edge,0x00000001=1: Both edges"
group.long 0x45D0++0x03
line.long 0x00 "INEN1_B2A2,Create registers that can control IE in GPIO"
hexmask.long 0x00 0.--31. 1. "INEN_31_0,"
group.long 0x6000++0x03
line.long 0x00 "PMMR1_B3A0,PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers"
hexmask.long 0x00 0.--31. 1. "PMMR_31_0,Multiplexed Pin Setting Mask Writing a value to any register from among the GPSR IPSR DRVCTRL TDSEL POC PUEN PUD MODSEL DMPR PSER PSSR PINV PIS registers is enabled by writing the inverse of the value to this register"
group.long 0x6004++0x03
line.long 0x00 "PMMER1_B3A0,PMMERn / PMMERSYS performs enables / disables control of the PMMR"
abitfld.long 0x00 0.--31. "PMMER_31_0,Multiplexed Pin Setting Mask Enable" "0x00000000=0: PMMR function is disabled,0x00000001=1: PMMR function is enabled"
group.long 0x6020++0x03
line.long 0x00 "DM0PR1_B3A0,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM0PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x6024++0x03
line.long 0x00 "DM1PR1_B3A0,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM1PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x6028++0x03
line.long 0x00 "DM2PR1_B3A0,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM2PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x602C++0x03
line.long 0x00 "DM3PR1_B3A0,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM3PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x6040++0x03
line.long 0x00 "GPSR1_B3A0,GPSRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "GPSR_31_0,"
group.long 0x6060++0x03
line.long 0x00 "IP0SR1_B3A0,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP0SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x6080++0x03
line.long 0x00 "DRV0CTRL1_B3A0,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV0CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x6084++0x03
line.long 0x00 "DRV1CTRL1_B3A0,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV1CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x6088++0x03
line.long 0x00 "DRV2CTRL1_B3A0,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV2CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x608C++0x03
line.long 0x00 "DRV3CTRL1_B3A0,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV3CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x60A0++0x03
line.long 0x00 "POC1_B3A0,Each bit in POCn / POCSYS must be set according to IO voltage level that is supplied to the pin"
abitfld.long 0x00 0.--31. "POC_31_0,- For 1.8V/3.3 V" "0x00000000=0: 2.5V,0x00000001=1: 3.3V"
group.long 0x60C0++0x03
line.long 0x00 "PUEN1_B3A0,PUENn / PUENSYS performs on / off control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUEN_31_0,"
group.long 0x60E0++0x03
line.long 0x00 "PUD1_B3A0,PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUD_31_0,"
group.long 0x6100++0x03
line.long 0x00 "MODSEL_B3A0,MODSELn selects the group for multiple LSI pins with multiplexed pin functions"
hexmask.long 0x00 0.--31. 1. "MODSEL_31_0,"
group.long 0x6120++0x03
line.long 0x00 "TD0SEL_B3A0,TD*SELn / TD*SELSYS controls the driving abilities of pins in use for the SDHI"
hexmask.long 0x00 0.--31. 1. "TD0SEL_31_0,"
group.long 0x6160++0x03
line.long 0x00 "PSER1_B3A0,The register (PSERn) to enable / disable PSS Rregister"
hexmask.long 0x00 0.--31. 1. "PSER_31_0,"
group.long 0x6164++0x03
line.long 0x00 "PS0SR1_B3A0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS0SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x6168++0x03
line.long 0x00 "PS1SR1_B3A0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS1SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x6180++0x03
line.long 0x00 "IOINTSEL1_B3A0,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group"
abitfld.long 0x00 0.--31. "IOINTSEL_31_0,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input/output mode,0x00000001=1: Interrupt input mode"
group.long 0x6184++0x03
line.long 0x00 "INOUTSEL1_B3A0,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INOUTSEL_31_0,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input mode,0x00000001=1: General output mode"
group.long 0x6188++0x03
line.long 0x00 "OUTDT1_B3A0,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDT_31_0,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL" "0x00000000=0: 0 is output,0x00000001=1: 1 is output"
group.long 0x618C++0x03
line.long 0x00 "INDT1_B3A0,INDTn is a register that can read the status of General-Purpose Input / Output Ports"
abitfld.long 0x00 0.--31. "INDT_31_0,Each bit reflects the value received through the corresponding port pin" "0x00000000=0: Input is 0,0x00000001=1: Input is 1"
group.long 0x6190++0x03
line.long 0x00 "INTDT1_B3A0,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INTDT_31_0,Each bit indicates the input of an interrupt signal on the corresponding port pin" "0x00000000=0: No interrupt signal has been input,0x00000001=1: Interrupt signal has been input"
group.long 0x6194++0x03
line.long 0x00 "INTCLR1_B3A0,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).."
abitfld.long 0x00 0.--31. "INTCLR_31_0,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register" "0x00000000=0: No effect,0x00000001=1: Interrupt display"
group.long 0x6198++0x03
line.long 0x00 "INTMSK1_B3A0,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch"
abitfld.long 0x00 0.--31. "INTMSK_31_0,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block" "0x00000000=0: Interrupt is masked,0x00000001=1: Interrupt is not masked"
group.long 0x619C++0x03
line.long 0x00 "MSKCLR1_B3A0,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A"
abitfld.long 0x00 0.--31. "MSKCLR_31_0,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block" "0x00000000=0: No effect,0x00000001=1: Interrupt is not masked"
group.long 0x61A0++0x03
line.long 0x00 "POSNEG1_B3A0,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode general output mode or interrupt input mode"
abitfld.long 0x00 0.--31. "POSNEG_31_0,Selects the polarity (positive or negative logic) of each port pin" "0x00000000=0: Positive logic,0x00000001=1: Negative logic"
group.long 0x61A4++0x03
line.long 0x00 "EDGLEVEL1_B3A0,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "EDGLEVEL_31_0,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected" "0x00000000=0: Level,0x00000001=1: Edge"
group.long 0x61A8++0x03
line.long 0x00 "FILONOFF1_B3A0,FILONOFFn prevents chattering input to the port pins of each GPIO group"
abitfld.long 0x00 0.--31. "FILONOFF_31_0,Enables or disables the chattering prevention function" "0x00000000=0: Chattering prevention function is..,0x00000001=1: Chattering prevention function is.."
group.long 0x61AC++0x03
line.long 0x00 "FILCLKSEL1_B3A0,FILCLKSELn controls the division ratio of clock CP? for prevent chattering input to the port pin GPIO group"
hexmask.long 0x00 0.--31. 1. "FILCLKSEL_31_0,Set the division ratio of filter CLOCK"
group.long 0x61C0++0x03
line.long 0x00 "OUTDTSEL1_B3A0,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDTSEL_31_0,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn" "0x00000000=0: General output register is used to..,0x00000001=1: Output data high register and.."
group.long 0x61C4++0x03
line.long 0x00 "OUTDTH1_B3A0,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTH_31_0,Outputting high value data" "0x00000000=0: Invalid data,0x00000001=1: Valid data"
group.long 0x61C8++0x03
line.long 0x00 "OUTDTL1_B3A0,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTL_31_0,Outputting low value data" "0x00000000=0: Valid data,0x00000001=1: Invalid data"
group.long 0x61CC++0x03
line.long 0x00 "BOTHEDGE1_B3A0,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers"
abitfld.long 0x00 0.--31. "BOTHEDGE_31_0,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected" "0x00000000=0: One edge,0x00000001=1: Both edges"
group.long 0x61D0++0x03
line.long 0x00 "INEN1_B3A0,Create registers that can control IE in GPIO"
hexmask.long 0x00 0.--31. 1. "INEN_31_0,"
group.long 0x6200++0x03
line.long 0x00 "PMMR1_B3A1,PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers"
hexmask.long 0x00 0.--31. 1. "PMMR_31_0,Multiplexed Pin Setting Mask Writing a value to any register from among the GPSR IPSR DRVCTRL TDSEL POC PUEN PUD MODSEL DMPR PSER PSSR PINV PIS registers is enabled by writing the inverse of the value to this register"
group.long 0x6204++0x03
line.long 0x00 "PMMER1_B3A1,PMMERn / PMMERSYS performs enables / disables control of the PMMR"
abitfld.long 0x00 0.--31. "PMMER_31_0,Multiplexed Pin Setting Mask Enable" "0x00000000=0: PMMR function is disabled,0x00000001=1: PMMR function is enabled"
group.long 0x6220++0x03
line.long 0x00 "DM0PR1_B3A1,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM0PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x6224++0x03
line.long 0x00 "DM1PR1_B3A1,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM1PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x6228++0x03
line.long 0x00 "DM2PR1_B3A1,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM2PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x622C++0x03
line.long 0x00 "DM3PR1_B3A1,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM3PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x6240++0x03
line.long 0x00 "GPSR1_B3A1,GPSRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "GPSR_31_0,"
group.long 0x6260++0x03
line.long 0x00 "IP0SR1_B3A1,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP0SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x6280++0x03
line.long 0x00 "DRV0CTRL1_B3A1,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV0CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x6284++0x03
line.long 0x00 "DRV1CTRL1_B3A1,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV1CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x6288++0x03
line.long 0x00 "DRV2CTRL1_B3A1,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV2CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x628C++0x03
line.long 0x00 "DRV3CTRL1_B3A1,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV3CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x62A0++0x03
line.long 0x00 "POC1_B3A1,Each bit in POCn / POCSYS must be set according to IO voltage level that is supplied to the pin"
abitfld.long 0x00 0.--31. "POC_31_0,- For 1.8V/3.3 V" "0x00000000=0: 2.5V,0x00000001=1: 3.3V"
group.long 0x62C0++0x03
line.long 0x00 "PUEN1_B3A1,PUENn / PUENSYS performs on / off control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUEN_31_0,"
group.long 0x62E0++0x03
line.long 0x00 "PUD1_B3A1,PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUD_31_0,"
group.long 0x6300++0x03
line.long 0x00 "MODSEL_B3A1,MODSELn selects the group for multiple LSI pins with multiplexed pin functions"
hexmask.long 0x00 0.--31. 1. "MODSEL_31_0,"
group.long 0x6320++0x03
line.long 0x00 "TD0SEL_B3A1,TD*SELn / TD*SELSYS controls the driving abilities of pins in use for the SDHI"
hexmask.long 0x00 0.--31. 1. "TD0SEL_31_0,"
group.long 0x6360++0x03
line.long 0x00 "PSER1_B3A1,The register (PSERn) to enable / disable PSS Rregister"
hexmask.long 0x00 0.--31. 1. "PSER_31_0,"
group.long 0x6364++0x03
line.long 0x00 "PS0SR1_B3A1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS0SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x6368++0x03
line.long 0x00 "PS1SR1_B3A1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS1SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x6380++0x03
line.long 0x00 "IOINTSEL1_B3A1,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group"
abitfld.long 0x00 0.--31. "IOINTSEL_31_0,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input/output mode,0x00000001=1: Interrupt input mode"
group.long 0x6384++0x03
line.long 0x00 "INOUTSEL1_B3A1,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INOUTSEL_31_0,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input mode,0x00000001=1: General output mode"
group.long 0x6388++0x03
line.long 0x00 "OUTDT1_B3A1,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDT_31_0,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL" "0x00000000=0: 0 is output,0x00000001=1: 1 is output"
group.long 0x638C++0x03
line.long 0x00 "INDT1_B3A1,INDTn is a register that can read the status of General-Purpose Input / Output Ports"
abitfld.long 0x00 0.--31. "INDT_31_0,Each bit reflects the value received through the corresponding port pin" "0x00000000=0: Input is 0,0x00000001=1: Input is 1"
group.long 0x6390++0x03
line.long 0x00 "INTDT1_B3A1,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INTDT_31_0,Each bit indicates the input of an interrupt signal on the corresponding port pin" "0x00000000=0: No interrupt signal has been input,0x00000001=1: Interrupt signal has been input"
group.long 0x6394++0x03
line.long 0x00 "INTCLR1_B3A1,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).."
abitfld.long 0x00 0.--31. "INTCLR_31_0,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register" "0x00000000=0: No effect,0x00000001=1: Interrupt display"
group.long 0x6398++0x03
line.long 0x00 "INTMSK1_B3A1,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch"
abitfld.long 0x00 0.--31. "INTMSK_31_0,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block" "0x00000000=0: Interrupt is masked,0x00000001=1: Interrupt is not masked"
group.long 0x639C++0x03
line.long 0x00 "MSKCLR1_B3A1,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A"
abitfld.long 0x00 0.--31. "MSKCLR_31_0,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block" "0x00000000=0: No effect,0x00000001=1: Interrupt is not masked"
group.long 0x63A0++0x03
line.long 0x00 "POSNEG1_B3A1,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode general output mode or interrupt input mode"
abitfld.long 0x00 0.--31. "POSNEG_31_0,Selects the polarity (positive or negative logic) of each port pin" "0x00000000=0: Positive logic,0x00000001=1: Negative logic"
group.long 0x63A4++0x03
line.long 0x00 "EDGLEVEL1_B3A1,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "EDGLEVEL_31_0,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected" "0x00000000=0: Level,0x00000001=1: Edge"
group.long 0x63A8++0x03
line.long 0x00 "FILONOFF1_B3A1,FILONOFFn prevents chattering input to the port pins of each GPIO group"
abitfld.long 0x00 0.--31. "FILONOFF_31_0,Enables or disables the chattering prevention function" "0x00000000=0: Chattering prevention function is..,0x00000001=1: Chattering prevention function is.."
group.long 0x63AC++0x03
line.long 0x00 "FILCLKSEL1_B3A1,FILCLKSELn controls the division ratio of clock CP? for prevent chattering input to the port pin GPIO group"
hexmask.long 0x00 0.--31. 1. "FILCLKSEL_31_0,Set the division ratio of filter CLOCK"
group.long 0x63C0++0x03
line.long 0x00 "OUTDTSEL1_B3A1,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDTSEL_31_0,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn" "0x00000000=0: General output register is used to..,0x00000001=1: Output data high register and.."
group.long 0x63C4++0x03
line.long 0x00 "OUTDTH1_B3A1,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTH_31_0,Outputting high value data" "0x00000000=0: Invalid data,0x00000001=1: Valid data"
group.long 0x63C8++0x03
line.long 0x00 "OUTDTL1_B3A1,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTL_31_0,Outputting low value data" "0x00000000=0: Valid data,0x00000001=1: Invalid data"
group.long 0x63CC++0x03
line.long 0x00 "BOTHEDGE1_B3A1,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers"
abitfld.long 0x00 0.--31. "BOTHEDGE_31_0,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected" "0x00000000=0: One edge,0x00000001=1: Both edges"
group.long 0x63D0++0x03
line.long 0x00 "INEN1_B3A1,Create registers that can control IE in GPIO"
hexmask.long 0x00 0.--31. 1. "INEN_31_0,"
group.long 0x6400++0x03
line.long 0x00 "PMMR1_B3A2,PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers"
hexmask.long 0x00 0.--31. 1. "PMMR_31_0,Multiplexed Pin Setting Mask Writing a value to any register from among the GPSR IPSR DRVCTRL TDSEL POC PUEN PUD MODSEL DMPR PSER PSSR PINV PIS registers is enabled by writing the inverse of the value to this register"
group.long 0x6404++0x03
line.long 0x00 "PMMER1_B3A2,PMMERn / PMMERSYS performs enables / disables control of the PMMR"
abitfld.long 0x00 0.--31. "PMMER_31_0,Multiplexed Pin Setting Mask Enable" "0x00000000=0: PMMR function is disabled,0x00000001=1: PMMR function is enabled"
group.long 0x6420++0x03
line.long 0x00 "DM0PR1_B3A2,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM0PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x6424++0x03
line.long 0x00 "DM1PR1_B3A2,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM1PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x6428++0x03
line.long 0x00 "DM2PR1_B3A2,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM2PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x642C++0x03
line.long 0x00 "DM3PR1_B3A2,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM3PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x6440++0x03
line.long 0x00 "GPSR1_B3A2,GPSRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "GPSR_31_0,"
group.long 0x6460++0x03
line.long 0x00 "IP0SR1_B3A2,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP0SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x6480++0x03
line.long 0x00 "DRV0CTRL1_B3A2,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV0CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x6484++0x03
line.long 0x00 "DRV1CTRL1_B3A2,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV1CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x6488++0x03
line.long 0x00 "DRV2CTRL1_B3A2,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV2CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x648C++0x03
line.long 0x00 "DRV3CTRL1_B3A2,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV3CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x64A0++0x03
line.long 0x00 "POC1_B3A2,Each bit in POCn / POCSYS must be set according to IO voltage level that is supplied to the pin"
abitfld.long 0x00 0.--31. "POC_31_0,- For 1.8V/3.3 V" "0x00000000=0: 2.5V,0x00000001=1: 3.3V"
group.long 0x64C0++0x03
line.long 0x00 "PUEN1_B3A2,PUENn / PUENSYS performs on / off control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUEN_31_0,"
group.long 0x64E0++0x03
line.long 0x00 "PUD1_B3A2,PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUD_31_0,"
group.long 0x6500++0x03
line.long 0x00 "MODSEL_B3A2,MODSELn selects the group for multiple LSI pins with multiplexed pin functions"
hexmask.long 0x00 0.--31. 1. "MODSEL_31_0,"
group.long 0x6520++0x03
line.long 0x00 "TD0SEL_B3A2,TD*SELn / TD*SELSYS controls the driving abilities of pins in use for the SDHI"
hexmask.long 0x00 0.--31. 1. "TD0SEL_31_0,"
group.long 0x6560++0x03
line.long 0x00 "PSER1_B3A2,The register (PSERn) to enable / disable PSS Rregister"
hexmask.long 0x00 0.--31. 1. "PSER_31_0,"
group.long 0x6564++0x03
line.long 0x00 "PS0SR1_B3A2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS0SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x6568++0x03
line.long 0x00 "PS1SR1_B3A2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS1SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x6580++0x03
line.long 0x00 "IOINTSEL1_B3A2,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group"
abitfld.long 0x00 0.--31. "IOINTSEL_31_0,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input/output mode,0x00000001=1: Interrupt input mode"
group.long 0x6584++0x03
line.long 0x00 "INOUTSEL1_B3A2,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INOUTSEL_31_0,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input mode,0x00000001=1: General output mode"
group.long 0x6588++0x03
line.long 0x00 "OUTDT1_B3A2,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDT_31_0,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL" "0x00000000=0: 0 is output,0x00000001=1: 1 is output"
group.long 0x658C++0x03
line.long 0x00 "INDT1_B3A2,INDTn is a register that can read the status of General-Purpose Input / Output Ports"
abitfld.long 0x00 0.--31. "INDT_31_0,Each bit reflects the value received through the corresponding port pin" "0x00000000=0: Input is 0,0x00000001=1: Input is 1"
group.long 0x6590++0x03
line.long 0x00 "INTDT1_B3A2,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INTDT_31_0,Each bit indicates the input of an interrupt signal on the corresponding port pin" "0x00000000=0: No interrupt signal has been input,0x00000001=1: Interrupt signal has been input"
group.long 0x6594++0x03
line.long 0x00 "INTCLR1_B3A2,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).."
abitfld.long 0x00 0.--31. "INTCLR_31_0,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register" "0x00000000=0: No effect,0x00000001=1: Interrupt display"
group.long 0x6598++0x03
line.long 0x00 "INTMSK1_B3A2,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch"
abitfld.long 0x00 0.--31. "INTMSK_31_0,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block" "0x00000000=0: Interrupt is masked,0x00000001=1: Interrupt is not masked"
group.long 0x659C++0x03
line.long 0x00 "MSKCLR1_B3A2,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A"
abitfld.long 0x00 0.--31. "MSKCLR_31_0,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block" "0x00000000=0: No effect,0x00000001=1: Interrupt is not masked"
group.long 0x65A0++0x03
line.long 0x00 "POSNEG1_B3A2,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode general output mode or interrupt input mode"
abitfld.long 0x00 0.--31. "POSNEG_31_0,Selects the polarity (positive or negative logic) of each port pin" "0x00000000=0: Positive logic,0x00000001=1: Negative logic"
group.long 0x65A4++0x03
line.long 0x00 "EDGLEVEL1_B3A2,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "EDGLEVEL_31_0,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected" "0x00000000=0: Level,0x00000001=1: Edge"
group.long 0x65A8++0x03
line.long 0x00 "FILONOFF1_B3A2,FILONOFFn prevents chattering input to the port pins of each GPIO group"
abitfld.long 0x00 0.--31. "FILONOFF_31_0,Enables or disables the chattering prevention function" "0x00000000=0: Chattering prevention function is..,0x00000001=1: Chattering prevention function is.."
group.long 0x65AC++0x03
line.long 0x00 "FILCLKSEL1_B3A2,FILCLKSELn controls the division ratio of clock CP? for prevent chattering input to the port pin GPIO group"
hexmask.long 0x00 0.--31. 1. "FILCLKSEL_31_0,Set the division ratio of filter CLOCK"
group.long 0x65C0++0x03
line.long 0x00 "OUTDTSEL1_B3A2,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDTSEL_31_0,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn" "0x00000000=0: General output register is used to..,0x00000001=1: Output data high register and.."
group.long 0x65C4++0x03
line.long 0x00 "OUTDTH1_B3A2,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTH_31_0,Outputting high value data" "0x00000000=0: Invalid data,0x00000001=1: Valid data"
group.long 0x65C8++0x03
line.long 0x00 "OUTDTL1_B3A2,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTL_31_0,Outputting low value data" "0x00000000=0: Valid data,0x00000001=1: Invalid data"
group.long 0x65CC++0x03
line.long 0x00 "BOTHEDGE1_B3A2,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers"
abitfld.long 0x00 0.--31. "BOTHEDGE_31_0,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected" "0x00000000=0: One edge,0x00000001=1: Both edges"
group.long 0x65D0++0x03
line.long 0x00 "INEN1_B3A2,Create registers that can control IE in GPIO"
hexmask.long 0x00 0.--31. 1. "INEN_31_0,"
tree.end
tree "PFC_GPIO_FOR_GP2"
base ad:0xE6051000
group.long 0x00++0x03
line.long 0x00 "PMMR2_B0A0,PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers"
hexmask.long 0x00 0.--31. 1. "PMMR_31_0,Multiplexed Pin Setting Mask Writing a value to any register from among the GPSR IPSR DRVCTRL TDSEL POC PUEN PUD MODSEL DMPR PSER PSSR PINV PIS registers is enabled by writing the inverse of the value to this register"
group.long 0x04++0x03
line.long 0x00 "PMMER2_B0A0,PMMERn / PMMERSYS performs enables / disables control of the PMMR"
abitfld.long 0x00 0.--31. "PMMER_31_0,Multiplexed Pin Setting Mask Enable" "0x00000000=0: PMMR function is disabled,0x00000001=1: PMMR function is enabled"
group.long 0x20++0x03
line.long 0x00 "DM0PR2_B0A0,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM0PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x24++0x03
line.long 0x00 "DM1PR2_B0A0,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM1PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x28++0x03
line.long 0x00 "DM2PR2_B0A0,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM2PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x2C++0x03
line.long 0x00 "DM3PR2_B0A0,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM3PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x40++0x03
line.long 0x00 "GPSR2_B0A0,GPSRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "GPSR_31_0,"
group.long 0x80++0x03
line.long 0x00 "DRV0CTRL2_B0A0,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV0CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x84++0x03
line.long 0x00 "DRV1CTRL2_B0A0,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV1CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x88++0x03
line.long 0x00 "DRV2CTRL2_B0A0,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV2CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0xC0++0x03
line.long 0x00 "PUEN2_B0A0,PUENn / PUENSYS performs on / off control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUEN_31_0,"
group.long 0xE0++0x03
line.long 0x00 "PUD2_B0A0,PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUD_31_0,"
group.long 0x160++0x03
line.long 0x00 "PSER2_B0A0,The register (PSERn) to enable / disable PSS Rregister"
hexmask.long 0x00 0.--31. 1. "PSER_31_0,"
group.long 0x164++0x03
line.long 0x00 "PS0SR2_B0A0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS0SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x168++0x03
line.long 0x00 "PS1SR2_B0A0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS1SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x180++0x03
line.long 0x00 "IOINTSEL2_B0A0,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group"
abitfld.long 0x00 0.--31. "IOINTSEL_31_0,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input/output mode,0x00000001=1: Interrupt input mode"
group.long 0x184++0x03
line.long 0x00 "INOUTSEL2_B0A0,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INOUTSEL_31_0,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input mode,0x00000001=1: General output mode"
group.long 0x188++0x03
line.long 0x00 "OUTDT2_B0A0,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDT_31_0,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL" "0x00000000=0: 0 is output,0x00000001=1: 1 is output"
group.long 0x18C++0x03
line.long 0x00 "INDT2_B0A0,INDTn is a register that can read the status of General-Purpose Input / Output Ports"
abitfld.long 0x00 0.--31. "INDT_31_0,Each bit reflects the value received through the corresponding port pin" "0x00000000=0: Input is 0,0x00000001=1: Input is 1"
group.long 0x190++0x03
line.long 0x00 "INTDT2_B0A0,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INTDT_31_0,Each bit indicates the input of an interrupt signal on the corresponding port pin" "0x00000000=0: No interrupt signal has been input,0x00000001=1: Interrupt signal has been input"
group.long 0x194++0x03
line.long 0x00 "INTCLR2_B0A0,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).."
abitfld.long 0x00 0.--31. "INTCLR_31_0,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register" "0x00000000=0: No effect,0x00000001=1: Interrupt display"
group.long 0x198++0x03
line.long 0x00 "INTMSK2_B0A0,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch"
abitfld.long 0x00 0.--31. "INTMSK_31_0,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block" "0x00000000=0: Interrupt is masked,0x00000001=1: Interrupt is not masked"
group.long 0x19C++0x03
line.long 0x00 "MSKCLR2_B0A0,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A"
abitfld.long 0x00 0.--31. "MSKCLR_31_0,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block" "0x00000000=0: No effect,0x00000001=1: Interrupt is not masked"
group.long 0x1A0++0x03
line.long 0x00 "POSNEG2_B0A0,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode general output mode or interrupt input mode"
abitfld.long 0x00 0.--31. "POSNEG_31_0,Selects the polarity (positive or negative logic) of each port pin" "0x00000000=0: Positive logic,0x00000001=1: Negative logic"
group.long 0x1A4++0x03
line.long 0x00 "EDGLEVEL2_B0A0,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "EDGLEVEL_31_0,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected" "0x00000000=0: Level,0x00000001=1: Edge"
group.long 0x1A8++0x03
line.long 0x00 "FILONOFF2_B0A0,FILONOFFn prevents chattering input to the port pins of each GPIO group"
abitfld.long 0x00 0.--31. "FILONOFF_31_0,Enables or disables the chattering prevention function" "0x00000000=0: Chattering prevention function is..,0x00000001=1: Chattering prevention function is.."
group.long 0x1AC++0x03
line.long 0x00 "FILCLKSEL2_B0A0,FILCLKSELn controls the division ratio of clock CP? for prevent chattering input to the port pin GPIO group"
hexmask.long 0x00 0.--31. 1. "FILCLKSEL_31_0,Set the division ratio of filter CLOCK"
group.long 0x1C0++0x03
line.long 0x00 "OUTDTSEL2_B0A0,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDTSEL_31_0,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn" "0x00000000=0: General output register is used to..,0x00000001=1: Output data high register and.."
group.long 0x1C4++0x03
line.long 0x00 "OUTDTH2_B0A0,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTH_31_0,Outputting high value data" "0x00000000=0: Invalid data,0x00000001=1: Valid data"
group.long 0x1C8++0x03
line.long 0x00 "OUTDTL2_B0A0,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTL_31_0,Outputting low value data" "0x00000000=0: Valid data,0x00000001=1: Invalid data"
group.long 0x1CC++0x03
line.long 0x00 "BOTHEDGE2_B0A0,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers"
abitfld.long 0x00 0.--31. "BOTHEDGE_31_0,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected" "0x00000000=0: One edge,0x00000001=1: Both edges"
group.long 0x1D0++0x03
line.long 0x00 "INEN2_B0A0,Create registers that can control IE in GPIO"
hexmask.long 0x00 0.--31. 1. "INEN_31_0,"
group.long 0x200++0x03
line.long 0x00 "PMMR2_B0A1,PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers"
hexmask.long 0x00 0.--31. 1. "PMMR_31_0,Multiplexed Pin Setting Mask Writing a value to any register from among the GPSR IPSR DRVCTRL TDSEL POC PUEN PUD MODSEL DMPR PSER PSSR PINV PIS registers is enabled by writing the inverse of the value to this register"
group.long 0x204++0x03
line.long 0x00 "PMMER2_B0A1,PMMERn / PMMERSYS performs enables / disables control of the PMMR"
abitfld.long 0x00 0.--31. "PMMER_31_0,Multiplexed Pin Setting Mask Enable" "0x00000000=0: PMMR function is disabled,0x00000001=1: PMMR function is enabled"
group.long 0x220++0x03
line.long 0x00 "DM0PR2_B0A1,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM0PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x224++0x03
line.long 0x00 "DM1PR2_B0A1,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM1PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x228++0x03
line.long 0x00 "DM2PR2_B0A1,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM2PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x22C++0x03
line.long 0x00 "DM3PR2_B0A1,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM3PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x240++0x03
line.long 0x00 "GPSR2_B0A1,GPSRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "GPSR_31_0,"
group.long 0x280++0x03
line.long 0x00 "DRV0CTRL2_B0A1,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV0CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x284++0x03
line.long 0x00 "DRV1CTRL2_B0A1,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV1CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x288++0x03
line.long 0x00 "DRV2CTRL2_B0A1,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV2CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x2C0++0x03
line.long 0x00 "PUEN2_B0A1,PUENn / PUENSYS performs on / off control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUEN_31_0,"
group.long 0x2E0++0x03
line.long 0x00 "PUD2_B0A1,PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUD_31_0,"
group.long 0x360++0x03
line.long 0x00 "PSER2_B0A1,The register (PSERn) to enable / disable PSS Rregister"
hexmask.long 0x00 0.--31. 1. "PSER_31_0,"
group.long 0x364++0x03
line.long 0x00 "PS0SR2_B0A1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS0SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x368++0x03
line.long 0x00 "PS1SR2_B0A1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS1SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x380++0x03
line.long 0x00 "IOINTSEL2_B0A1,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group"
abitfld.long 0x00 0.--31. "IOINTSEL_31_0,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input/output mode,0x00000001=1: Interrupt input mode"
group.long 0x384++0x03
line.long 0x00 "INOUTSEL2_B0A1,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INOUTSEL_31_0,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input mode,0x00000001=1: General output mode"
group.long 0x388++0x03
line.long 0x00 "OUTDT2_B0A1,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDT_31_0,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL" "0x00000000=0: 0 is output,0x00000001=1: 1 is output"
group.long 0x38C++0x03
line.long 0x00 "INDT2_B0A1,INDTn is a register that can read the status of General-Purpose Input / Output Ports"
abitfld.long 0x00 0.--31. "INDT_31_0,Each bit reflects the value received through the corresponding port pin" "0x00000000=0: Input is 0,0x00000001=1: Input is 1"
group.long 0x390++0x03
line.long 0x00 "INTDT2_B0A1,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INTDT_31_0,Each bit indicates the input of an interrupt signal on the corresponding port pin" "0x00000000=0: No interrupt signal has been input,0x00000001=1: Interrupt signal has been input"
group.long 0x394++0x03
line.long 0x00 "INTCLR2_B0A1,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).."
abitfld.long 0x00 0.--31. "INTCLR_31_0,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register" "0x00000000=0: No effect,0x00000001=1: Interrupt display"
group.long 0x398++0x03
line.long 0x00 "INTMSK2_B0A1,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch"
abitfld.long 0x00 0.--31. "INTMSK_31_0,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block" "0x00000000=0: Interrupt is masked,0x00000001=1: Interrupt is not masked"
group.long 0x39C++0x03
line.long 0x00 "MSKCLR2_B0A1,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A"
abitfld.long 0x00 0.--31. "MSKCLR_31_0,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block" "0x00000000=0: No effect,0x00000001=1: Interrupt is not masked"
group.long 0x3A0++0x03
line.long 0x00 "POSNEG2_B0A1,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode general output mode or interrupt input mode"
abitfld.long 0x00 0.--31. "POSNEG_31_0,Selects the polarity (positive or negative logic) of each port pin" "0x00000000=0: Positive logic,0x00000001=1: Negative logic"
group.long 0x3A4++0x03
line.long 0x00 "EDGLEVEL2_B0A1,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "EDGLEVEL_31_0,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected" "0x00000000=0: Level,0x00000001=1: Edge"
group.long 0x3A8++0x03
line.long 0x00 "FILONOFF2_B0A1,FILONOFFn prevents chattering input to the port pins of each GPIO group"
abitfld.long 0x00 0.--31. "FILONOFF_31_0,Enables or disables the chattering prevention function" "0x00000000=0: Chattering prevention function is..,0x00000001=1: Chattering prevention function is.."
group.long 0x3AC++0x03
line.long 0x00 "FILCLKSEL2_B0A1,FILCLKSELn controls the division ratio of clock CP? for prevent chattering input to the port pin GPIO group"
hexmask.long 0x00 0.--31. 1. "FILCLKSEL_31_0,Set the division ratio of filter CLOCK"
group.long 0x3C0++0x03
line.long 0x00 "OUTDTSEL2_B0A1,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDTSEL_31_0,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn" "0x00000000=0: General output register is used to..,0x00000001=1: Output data high register and.."
group.long 0x3C4++0x03
line.long 0x00 "OUTDTH2_B0A1,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTH_31_0,Outputting high value data" "0x00000000=0: Invalid data,0x00000001=1: Valid data"
group.long 0x3C8++0x03
line.long 0x00 "OUTDTL2_B0A1,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTL_31_0,Outputting low value data" "0x00000000=0: Valid data,0x00000001=1: Invalid data"
group.long 0x3CC++0x03
line.long 0x00 "BOTHEDGE2_B0A1,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers"
abitfld.long 0x00 0.--31. "BOTHEDGE_31_0,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected" "0x00000000=0: One edge,0x00000001=1: Both edges"
group.long 0x3D0++0x03
line.long 0x00 "INEN2_B0A1,Create registers that can control IE in GPIO"
hexmask.long 0x00 0.--31. 1. "INEN_31_0,"
group.long 0x400++0x03
line.long 0x00 "PMMR2_B0A2,PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers"
hexmask.long 0x00 0.--31. 1. "PMMR_31_0,Multiplexed Pin Setting Mask Writing a value to any register from among the GPSR IPSR DRVCTRL TDSEL POC PUEN PUD MODSEL DMPR PSER PSSR PINV PIS registers is enabled by writing the inverse of the value to this register"
group.long 0x404++0x03
line.long 0x00 "PMMER2_B0A2,PMMERn / PMMERSYS performs enables / disables control of the PMMR"
abitfld.long 0x00 0.--31. "PMMER_31_0,Multiplexed Pin Setting Mask Enable" "0x00000000=0: PMMR function is disabled,0x00000001=1: PMMR function is enabled"
group.long 0x420++0x03
line.long 0x00 "DM0PR2_B0A2,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM0PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x424++0x03
line.long 0x00 "DM1PR2_B0A2,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM1PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x428++0x03
line.long 0x00 "DM2PR2_B0A2,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM2PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x42C++0x03
line.long 0x00 "DM3PR2_B0A2,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM3PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x440++0x03
line.long 0x00 "GPSR2_B0A2,GPSRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "GPSR_31_0,"
group.long 0x480++0x03
line.long 0x00 "DRV0CTRL2_B0A2,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV0CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x484++0x03
line.long 0x00 "DRV1CTRL2_B0A2,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV1CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x488++0x03
line.long 0x00 "DRV2CTRL2_B0A2,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV2CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x4C0++0x03
line.long 0x00 "PUEN2_B0A2,PUENn / PUENSYS performs on / off control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUEN_31_0,"
group.long 0x4E0++0x03
line.long 0x00 "PUD2_B0A2,PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUD_31_0,"
group.long 0x560++0x03
line.long 0x00 "PSER2_B0A2,The register (PSERn) to enable / disable PSS Rregister"
hexmask.long 0x00 0.--31. 1. "PSER_31_0,"
group.long 0x564++0x03
line.long 0x00 "PS0SR2_B0A2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS0SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x568++0x03
line.long 0x00 "PS1SR2_B0A2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS1SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x580++0x03
line.long 0x00 "IOINTSEL2_B0A2,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group"
abitfld.long 0x00 0.--31. "IOINTSEL_31_0,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input/output mode,0x00000001=1: Interrupt input mode"
group.long 0x584++0x03
line.long 0x00 "INOUTSEL2_B0A2,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INOUTSEL_31_0,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input mode,0x00000001=1: General output mode"
group.long 0x588++0x03
line.long 0x00 "OUTDT2_B0A2,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDT_31_0,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL" "0x00000000=0: 0 is output,0x00000001=1: 1 is output"
group.long 0x58C++0x03
line.long 0x00 "INDT2_B0A2,INDTn is a register that can read the status of General-Purpose Input / Output Ports"
abitfld.long 0x00 0.--31. "INDT_31_0,Each bit reflects the value received through the corresponding port pin" "0x00000000=0: Input is 0,0x00000001=1: Input is 1"
group.long 0x590++0x03
line.long 0x00 "INTDT2_B0A2,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INTDT_31_0,Each bit indicates the input of an interrupt signal on the corresponding port pin" "0x00000000=0: No interrupt signal has been input,0x00000001=1: Interrupt signal has been input"
group.long 0x594++0x03
line.long 0x00 "INTCLR2_B0A2,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).."
abitfld.long 0x00 0.--31. "INTCLR_31_0,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register" "0x00000000=0: No effect,0x00000001=1: Interrupt display"
group.long 0x598++0x03
line.long 0x00 "INTMSK2_B0A2,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch"
abitfld.long 0x00 0.--31. "INTMSK_31_0,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block" "0x00000000=0: Interrupt is masked,0x00000001=1: Interrupt is not masked"
group.long 0x59C++0x03
line.long 0x00 "MSKCLR2_B0A2,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A"
abitfld.long 0x00 0.--31. "MSKCLR_31_0,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block" "0x00000000=0: No effect,0x00000001=1: Interrupt is not masked"
group.long 0x5A0++0x03
line.long 0x00 "POSNEG2_B0A2,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode general output mode or interrupt input mode"
abitfld.long 0x00 0.--31. "POSNEG_31_0,Selects the polarity (positive or negative logic) of each port pin" "0x00000000=0: Positive logic,0x00000001=1: Negative logic"
group.long 0x5A4++0x03
line.long 0x00 "EDGLEVEL2_B0A2,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "EDGLEVEL_31_0,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected" "0x00000000=0: Level,0x00000001=1: Edge"
group.long 0x5A8++0x03
line.long 0x00 "FILONOFF2_B0A2,FILONOFFn prevents chattering input to the port pins of each GPIO group"
abitfld.long 0x00 0.--31. "FILONOFF_31_0,Enables or disables the chattering prevention function" "0x00000000=0: Chattering prevention function is..,0x00000001=1: Chattering prevention function is.."
group.long 0x5AC++0x03
line.long 0x00 "FILCLKSEL2_B0A2,FILCLKSELn controls the division ratio of clock CP? for prevent chattering input to the port pin GPIO group"
hexmask.long 0x00 0.--31. 1. "FILCLKSEL_31_0,Set the division ratio of filter CLOCK"
group.long 0x5C0++0x03
line.long 0x00 "OUTDTSEL2_B0A2,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDTSEL_31_0,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn" "0x00000000=0: General output register is used to..,0x00000001=1: Output data high register and.."
group.long 0x5C4++0x03
line.long 0x00 "OUTDTH2_B0A2,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTH_31_0,Outputting high value data" "0x00000000=0: Invalid data,0x00000001=1: Valid data"
group.long 0x5C8++0x03
line.long 0x00 "OUTDTL2_B0A2,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTL_31_0,Outputting low value data" "0x00000000=0: Valid data,0x00000001=1: Invalid data"
group.long 0x5CC++0x03
line.long 0x00 "BOTHEDGE2_B0A2,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers"
abitfld.long 0x00 0.--31. "BOTHEDGE_31_0,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected" "0x00000000=0: One edge,0x00000001=1: Both edges"
group.long 0x5D0++0x03
line.long 0x00 "INEN2_B0A2,Create registers that can control IE in GPIO"
hexmask.long 0x00 0.--31. 1. "INEN_31_0,"
group.long 0x2000++0x03
line.long 0x00 "PMMR2_B1A0,PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers"
hexmask.long 0x00 0.--31. 1. "PMMR_31_0,Multiplexed Pin Setting Mask Writing a value to any register from among the GPSR IPSR DRVCTRL TDSEL POC PUEN PUD MODSEL DMPR PSER PSSR PINV PIS registers is enabled by writing the inverse of the value to this register"
group.long 0x2004++0x03
line.long 0x00 "PMMER2_B1A0,PMMERn / PMMERSYS performs enables / disables control of the PMMR"
abitfld.long 0x00 0.--31. "PMMER_31_0,Multiplexed Pin Setting Mask Enable" "0x00000000=0: PMMR function is disabled,0x00000001=1: PMMR function is enabled"
group.long 0x2020++0x03
line.long 0x00 "DM0PR2_B1A0,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM0PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x2024++0x03
line.long 0x00 "DM1PR2_B1A0,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM1PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x2028++0x03
line.long 0x00 "DM2PR2_B1A0,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM2PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x202C++0x03
line.long 0x00 "DM3PR2_B1A0,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM3PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x2040++0x03
line.long 0x00 "GPSR2_B1A0,GPSRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "GPSR_31_0,"
group.long 0x2080++0x03
line.long 0x00 "DRV0CTRL2_B1A0,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV0CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x2084++0x03
line.long 0x00 "DRV1CTRL2_B1A0,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV1CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x2088++0x03
line.long 0x00 "DRV2CTRL2_B1A0,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV2CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x20C0++0x03
line.long 0x00 "PUEN2_B1A0,PUENn / PUENSYS performs on / off control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUEN_31_0,"
group.long 0x20E0++0x03
line.long 0x00 "PUD2_B1A0,PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUD_31_0,"
group.long 0x2160++0x03
line.long 0x00 "PSER2_B1A0,The register (PSERn) to enable / disable PSS Rregister"
hexmask.long 0x00 0.--31. 1. "PSER_31_0,"
group.long 0x2164++0x03
line.long 0x00 "PS0SR2_B1A0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS0SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x2168++0x03
line.long 0x00 "PS1SR2_B1A0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS1SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x2180++0x03
line.long 0x00 "IOINTSEL2_B1A0,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group"
abitfld.long 0x00 0.--31. "IOINTSEL_31_0,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input/output mode,0x00000001=1: Interrupt input mode"
group.long 0x2184++0x03
line.long 0x00 "INOUTSEL2_B1A0,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INOUTSEL_31_0,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input mode,0x00000001=1: General output mode"
group.long 0x2188++0x03
line.long 0x00 "OUTDT2_B1A0,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDT_31_0,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL" "0x00000000=0: 0 is output,0x00000001=1: 1 is output"
group.long 0x218C++0x03
line.long 0x00 "INDT2_B1A0,INDTn is a register that can read the status of General-Purpose Input / Output Ports"
abitfld.long 0x00 0.--31. "INDT_31_0,Each bit reflects the value received through the corresponding port pin" "0x00000000=0: Input is 0,0x00000001=1: Input is 1"
group.long 0x2190++0x03
line.long 0x00 "INTDT2_B1A0,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INTDT_31_0,Each bit indicates the input of an interrupt signal on the corresponding port pin" "0x00000000=0: No interrupt signal has been input,0x00000001=1: Interrupt signal has been input"
group.long 0x2194++0x03
line.long 0x00 "INTCLR2_B1A0,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).."
abitfld.long 0x00 0.--31. "INTCLR_31_0,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register" "0x00000000=0: No effect,0x00000001=1: Interrupt display"
group.long 0x2198++0x03
line.long 0x00 "INTMSK2_B1A0,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch"
abitfld.long 0x00 0.--31. "INTMSK_31_0,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block" "0x00000000=0: Interrupt is masked,0x00000001=1: Interrupt is not masked"
group.long 0x219C++0x03
line.long 0x00 "MSKCLR2_B1A0,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A"
abitfld.long 0x00 0.--31. "MSKCLR_31_0,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block" "0x00000000=0: No effect,0x00000001=1: Interrupt is not masked"
group.long 0x21A0++0x03
line.long 0x00 "POSNEG2_B1A0,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode general output mode or interrupt input mode"
abitfld.long 0x00 0.--31. "POSNEG_31_0,Selects the polarity (positive or negative logic) of each port pin" "0x00000000=0: Positive logic,0x00000001=1: Negative logic"
group.long 0x21A4++0x03
line.long 0x00 "EDGLEVEL2_B1A0,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "EDGLEVEL_31_0,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected" "0x00000000=0: Level,0x00000001=1: Edge"
group.long 0x21A8++0x03
line.long 0x00 "FILONOFF2_B1A0,FILONOFFn prevents chattering input to the port pins of each GPIO group"
abitfld.long 0x00 0.--31. "FILONOFF_31_0,Enables or disables the chattering prevention function" "0x00000000=0: Chattering prevention function is..,0x00000001=1: Chattering prevention function is.."
group.long 0x21AC++0x03
line.long 0x00 "FILCLKSEL2_B1A0,FILCLKSELn controls the division ratio of clock CP? for prevent chattering input to the port pin GPIO group"
hexmask.long 0x00 0.--31. 1. "FILCLKSEL_31_0,Set the division ratio of filter CLOCK"
group.long 0x21C0++0x03
line.long 0x00 "OUTDTSEL2_B1A0,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDTSEL_31_0,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn" "0x00000000=0: General output register is used to..,0x00000001=1: Output data high register and.."
group.long 0x21C4++0x03
line.long 0x00 "OUTDTH2_B1A0,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTH_31_0,Outputting high value data" "0x00000000=0: Invalid data,0x00000001=1: Valid data"
group.long 0x21C8++0x03
line.long 0x00 "OUTDTL2_B1A0,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTL_31_0,Outputting low value data" "0x00000000=0: Valid data,0x00000001=1: Invalid data"
group.long 0x21CC++0x03
line.long 0x00 "BOTHEDGE2_B1A0,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers"
abitfld.long 0x00 0.--31. "BOTHEDGE_31_0,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected" "0x00000000=0: One edge,0x00000001=1: Both edges"
group.long 0x21D0++0x03
line.long 0x00 "INEN2_B1A0,Create registers that can control IE in GPIO"
hexmask.long 0x00 0.--31. 1. "INEN_31_0,"
group.long 0x2200++0x03
line.long 0x00 "PMMR2_B1A1,PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers"
hexmask.long 0x00 0.--31. 1. "PMMR_31_0,Multiplexed Pin Setting Mask Writing a value to any register from among the GPSR IPSR DRVCTRL TDSEL POC PUEN PUD MODSEL DMPR PSER PSSR PINV PIS registers is enabled by writing the inverse of the value to this register"
group.long 0x2204++0x03
line.long 0x00 "PMMER2_B1A1,PMMERn / PMMERSYS performs enables / disables control of the PMMR"
abitfld.long 0x00 0.--31. "PMMER_31_0,Multiplexed Pin Setting Mask Enable" "0x00000000=0: PMMR function is disabled,0x00000001=1: PMMR function is enabled"
group.long 0x2220++0x03
line.long 0x00 "DM0PR2_B1A1,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM0PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x2224++0x03
line.long 0x00 "DM1PR2_B1A1,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM1PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x2228++0x03
line.long 0x00 "DM2PR2_B1A1,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM2PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x222C++0x03
line.long 0x00 "DM3PR2_B1A1,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM3PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x2240++0x03
line.long 0x00 "GPSR2_B1A1,GPSRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "GPSR_31_0,"
group.long 0x2280++0x03
line.long 0x00 "DRV0CTRL2_B1A1,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV0CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x2284++0x03
line.long 0x00 "DRV1CTRL2_B1A1,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV1CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x2288++0x03
line.long 0x00 "DRV2CTRL2_B1A1,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV2CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x22C0++0x03
line.long 0x00 "PUEN2_B1A1,PUENn / PUENSYS performs on / off control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUEN_31_0,"
group.long 0x22E0++0x03
line.long 0x00 "PUD2_B1A1,PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUD_31_0,"
group.long 0x2360++0x03
line.long 0x00 "PSER2_B1A1,The register (PSERn) to enable / disable PSS Rregister"
hexmask.long 0x00 0.--31. 1. "PSER_31_0,"
group.long 0x2364++0x03
line.long 0x00 "PS0SR2_B1A1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS0SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x2368++0x03
line.long 0x00 "PS1SR2_B1A1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS1SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x2380++0x03
line.long 0x00 "IOINTSEL2_B1A1,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group"
abitfld.long 0x00 0.--31. "IOINTSEL_31_0,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input/output mode,0x00000001=1: Interrupt input mode"
group.long 0x2384++0x03
line.long 0x00 "INOUTSEL2_B1A1,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INOUTSEL_31_0,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input mode,0x00000001=1: General output mode"
group.long 0x2388++0x03
line.long 0x00 "OUTDT2_B1A1,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDT_31_0,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL" "0x00000000=0: 0 is output,0x00000001=1: 1 is output"
group.long 0x238C++0x03
line.long 0x00 "INDT2_B1A1,INDTn is a register that can read the status of General-Purpose Input / Output Ports"
abitfld.long 0x00 0.--31. "INDT_31_0,Each bit reflects the value received through the corresponding port pin" "0x00000000=0: Input is 0,0x00000001=1: Input is 1"
group.long 0x2390++0x03
line.long 0x00 "INTDT2_B1A1,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INTDT_31_0,Each bit indicates the input of an interrupt signal on the corresponding port pin" "0x00000000=0: No interrupt signal has been input,0x00000001=1: Interrupt signal has been input"
group.long 0x2394++0x03
line.long 0x00 "INTCLR2_B1A1,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).."
abitfld.long 0x00 0.--31. "INTCLR_31_0,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register" "0x00000000=0: No effect,0x00000001=1: Interrupt display"
group.long 0x2398++0x03
line.long 0x00 "INTMSK2_B1A1,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch"
abitfld.long 0x00 0.--31. "INTMSK_31_0,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block" "0x00000000=0: Interrupt is masked,0x00000001=1: Interrupt is not masked"
group.long 0x239C++0x03
line.long 0x00 "MSKCLR2_B1A1,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A"
abitfld.long 0x00 0.--31. "MSKCLR_31_0,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block" "0x00000000=0: No effect,0x00000001=1: Interrupt is not masked"
group.long 0x23A0++0x03
line.long 0x00 "POSNEG2_B1A1,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode general output mode or interrupt input mode"
abitfld.long 0x00 0.--31. "POSNEG_31_0,Selects the polarity (positive or negative logic) of each port pin" "0x00000000=0: Positive logic,0x00000001=1: Negative logic"
group.long 0x23A4++0x03
line.long 0x00 "EDGLEVEL2_B1A1,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "EDGLEVEL_31_0,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected" "0x00000000=0: Level,0x00000001=1: Edge"
group.long 0x23A8++0x03
line.long 0x00 "FILONOFF2_B1A1,FILONOFFn prevents chattering input to the port pins of each GPIO group"
abitfld.long 0x00 0.--31. "FILONOFF_31_0,Enables or disables the chattering prevention function" "0x00000000=0: Chattering prevention function is..,0x00000001=1: Chattering prevention function is.."
group.long 0x23AC++0x03
line.long 0x00 "FILCLKSEL2_B1A1,FILCLKSELn controls the division ratio of clock CP? for prevent chattering input to the port pin GPIO group"
hexmask.long 0x00 0.--31. 1. "FILCLKSEL_31_0,Set the division ratio of filter CLOCK"
group.long 0x23C0++0x03
line.long 0x00 "OUTDTSEL2_B1A1,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDTSEL_31_0,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn" "0x00000000=0: General output register is used to..,0x00000001=1: Output data high register and.."
group.long 0x23C4++0x03
line.long 0x00 "OUTDTH2_B1A1,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTH_31_0,Outputting high value data" "0x00000000=0: Invalid data,0x00000001=1: Valid data"
group.long 0x23C8++0x03
line.long 0x00 "OUTDTL2_B1A1,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTL_31_0,Outputting low value data" "0x00000000=0: Valid data,0x00000001=1: Invalid data"
group.long 0x23CC++0x03
line.long 0x00 "BOTHEDGE2_B1A1,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers"
abitfld.long 0x00 0.--31. "BOTHEDGE_31_0,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected" "0x00000000=0: One edge,0x00000001=1: Both edges"
group.long 0x23D0++0x03
line.long 0x00 "INEN2_B1A1,Create registers that can control IE in GPIO"
hexmask.long 0x00 0.--31. 1. "INEN_31_0,"
group.long 0x2400++0x03
line.long 0x00 "PMMR2_B1A2,PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers"
hexmask.long 0x00 0.--31. 1. "PMMR_31_0,Multiplexed Pin Setting Mask Writing a value to any register from among the GPSR IPSR DRVCTRL TDSEL POC PUEN PUD MODSEL DMPR PSER PSSR PINV PIS registers is enabled by writing the inverse of the value to this register"
group.long 0x2404++0x03
line.long 0x00 "PMMER2_B1A2,PMMERn / PMMERSYS performs enables / disables control of the PMMR"
abitfld.long 0x00 0.--31. "PMMER_31_0,Multiplexed Pin Setting Mask Enable" "0x00000000=0: PMMR function is disabled,0x00000001=1: PMMR function is enabled"
group.long 0x2420++0x03
line.long 0x00 "DM0PR2_B1A2,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM0PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x2424++0x03
line.long 0x00 "DM1PR2_B1A2,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM1PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x2428++0x03
line.long 0x00 "DM2PR2_B1A2,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM2PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x242C++0x03
line.long 0x00 "DM3PR2_B1A2,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM3PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x2440++0x03
line.long 0x00 "GPSR2_B1A2,GPSRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "GPSR_31_0,"
group.long 0x2480++0x03
line.long 0x00 "DRV0CTRL2_B1A2,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV0CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x2484++0x03
line.long 0x00 "DRV1CTRL2_B1A2,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV1CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x2488++0x03
line.long 0x00 "DRV2CTRL2_B1A2,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV2CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x24C0++0x03
line.long 0x00 "PUEN2_B1A2,PUENn / PUENSYS performs on / off control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUEN_31_0,"
group.long 0x24E0++0x03
line.long 0x00 "PUD2_B1A2,PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUD_31_0,"
group.long 0x2560++0x03
line.long 0x00 "PSER2_B1A2,The register (PSERn) to enable / disable PSS Rregister"
hexmask.long 0x00 0.--31. 1. "PSER_31_0,"
group.long 0x2564++0x03
line.long 0x00 "PS0SR2_B1A2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS0SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x2568++0x03
line.long 0x00 "PS1SR2_B1A2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS1SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x2580++0x03
line.long 0x00 "IOINTSEL2_B1A2,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group"
abitfld.long 0x00 0.--31. "IOINTSEL_31_0,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input/output mode,0x00000001=1: Interrupt input mode"
group.long 0x2584++0x03
line.long 0x00 "INOUTSEL2_B1A2,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INOUTSEL_31_0,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input mode,0x00000001=1: General output mode"
group.long 0x2588++0x03
line.long 0x00 "OUTDT2_B1A2,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDT_31_0,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL" "0x00000000=0: 0 is output,0x00000001=1: 1 is output"
group.long 0x258C++0x03
line.long 0x00 "INDT2_B1A2,INDTn is a register that can read the status of General-Purpose Input / Output Ports"
abitfld.long 0x00 0.--31. "INDT_31_0,Each bit reflects the value received through the corresponding port pin" "0x00000000=0: Input is 0,0x00000001=1: Input is 1"
group.long 0x2590++0x03
line.long 0x00 "INTDT2_B1A2,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INTDT_31_0,Each bit indicates the input of an interrupt signal on the corresponding port pin" "0x00000000=0: No interrupt signal has been input,0x00000001=1: Interrupt signal has been input"
group.long 0x2594++0x03
line.long 0x00 "INTCLR2_B1A2,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).."
abitfld.long 0x00 0.--31. "INTCLR_31_0,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register" "0x00000000=0: No effect,0x00000001=1: Interrupt display"
group.long 0x2598++0x03
line.long 0x00 "INTMSK2_B1A2,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch"
abitfld.long 0x00 0.--31. "INTMSK_31_0,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block" "0x00000000=0: Interrupt is masked,0x00000001=1: Interrupt is not masked"
group.long 0x259C++0x03
line.long 0x00 "MSKCLR2_B1A2,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A"
abitfld.long 0x00 0.--31. "MSKCLR_31_0,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block" "0x00000000=0: No effect,0x00000001=1: Interrupt is not masked"
group.long 0x25A0++0x03
line.long 0x00 "POSNEG2_B1A2,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode general output mode or interrupt input mode"
abitfld.long 0x00 0.--31. "POSNEG_31_0,Selects the polarity (positive or negative logic) of each port pin" "0x00000000=0: Positive logic,0x00000001=1: Negative logic"
group.long 0x25A4++0x03
line.long 0x00 "EDGLEVEL2_B1A2,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "EDGLEVEL_31_0,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected" "0x00000000=0: Level,0x00000001=1: Edge"
group.long 0x25A8++0x03
line.long 0x00 "FILONOFF2_B1A2,FILONOFFn prevents chattering input to the port pins of each GPIO group"
abitfld.long 0x00 0.--31. "FILONOFF_31_0,Enables or disables the chattering prevention function" "0x00000000=0: Chattering prevention function is..,0x00000001=1: Chattering prevention function is.."
group.long 0x25AC++0x03
line.long 0x00 "FILCLKSEL2_B1A2,FILCLKSELn controls the division ratio of clock CP? for prevent chattering input to the port pin GPIO group"
hexmask.long 0x00 0.--31. 1. "FILCLKSEL_31_0,Set the division ratio of filter CLOCK"
group.long 0x25C0++0x03
line.long 0x00 "OUTDTSEL2_B1A2,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDTSEL_31_0,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn" "0x00000000=0: General output register is used to..,0x00000001=1: Output data high register and.."
group.long 0x25C4++0x03
line.long 0x00 "OUTDTH2_B1A2,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTH_31_0,Outputting high value data" "0x00000000=0: Invalid data,0x00000001=1: Valid data"
group.long 0x25C8++0x03
line.long 0x00 "OUTDTL2_B1A2,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTL_31_0,Outputting low value data" "0x00000000=0: Valid data,0x00000001=1: Invalid data"
group.long 0x25CC++0x03
line.long 0x00 "BOTHEDGE2_B1A2,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers"
abitfld.long 0x00 0.--31. "BOTHEDGE_31_0,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected" "0x00000000=0: One edge,0x00000001=1: Both edges"
group.long 0x25D0++0x03
line.long 0x00 "INEN2_B1A2,Create registers that can control IE in GPIO"
hexmask.long 0x00 0.--31. 1. "INEN_31_0,"
group.long 0x4000++0x03
line.long 0x00 "PMMR2_B2A0,PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers"
hexmask.long 0x00 0.--31. 1. "PMMR_31_0,Multiplexed Pin Setting Mask Writing a value to any register from among the GPSR IPSR DRVCTRL TDSEL POC PUEN PUD MODSEL DMPR PSER PSSR PINV PIS registers is enabled by writing the inverse of the value to this register"
group.long 0x4004++0x03
line.long 0x00 "PMMER2_B2A0,PMMERn / PMMERSYS performs enables / disables control of the PMMR"
abitfld.long 0x00 0.--31. "PMMER_31_0,Multiplexed Pin Setting Mask Enable" "0x00000000=0: PMMR function is disabled,0x00000001=1: PMMR function is enabled"
group.long 0x4020++0x03
line.long 0x00 "DM0PR2_B2A0,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM0PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x4024++0x03
line.long 0x00 "DM1PR2_B2A0,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM1PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x4028++0x03
line.long 0x00 "DM2PR2_B2A0,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM2PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x402C++0x03
line.long 0x00 "DM3PR2_B2A0,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM3PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x4040++0x03
line.long 0x00 "GPSR2_B2A0,GPSRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "GPSR_31_0,"
group.long 0x4080++0x03
line.long 0x00 "DRV0CTRL2_B2A0,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV0CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x4084++0x03
line.long 0x00 "DRV1CTRL2_B2A0,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV1CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x4088++0x03
line.long 0x00 "DRV2CTRL2_B2A0,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV2CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x40C0++0x03
line.long 0x00 "PUEN2_B2A0,PUENn / PUENSYS performs on / off control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUEN_31_0,"
group.long 0x40E0++0x03
line.long 0x00 "PUD2_B2A0,PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUD_31_0,"
group.long 0x4160++0x03
line.long 0x00 "PSER2_B2A0,The register (PSERn) to enable / disable PSS Rregister"
hexmask.long 0x00 0.--31. 1. "PSER_31_0,"
group.long 0x4164++0x03
line.long 0x00 "PS0SR2_B2A0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS0SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x4168++0x03
line.long 0x00 "PS1SR2_B2A0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS1SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x4180++0x03
line.long 0x00 "IOINTSEL2_B2A0,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group"
abitfld.long 0x00 0.--31. "IOINTSEL_31_0,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input/output mode,0x00000001=1: Interrupt input mode"
group.long 0x4184++0x03
line.long 0x00 "INOUTSEL2_B2A0,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INOUTSEL_31_0,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input mode,0x00000001=1: General output mode"
group.long 0x4188++0x03
line.long 0x00 "OUTDT2_B2A0,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDT_31_0,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL" "0x00000000=0: 0 is output,0x00000001=1: 1 is output"
group.long 0x418C++0x03
line.long 0x00 "INDT2_B2A0,INDTn is a register that can read the status of General-Purpose Input / Output Ports"
abitfld.long 0x00 0.--31. "INDT_31_0,Each bit reflects the value received through the corresponding port pin" "0x00000000=0: Input is 0,0x00000001=1: Input is 1"
group.long 0x4190++0x03
line.long 0x00 "INTDT2_B2A0,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INTDT_31_0,Each bit indicates the input of an interrupt signal on the corresponding port pin" "0x00000000=0: No interrupt signal has been input,0x00000001=1: Interrupt signal has been input"
group.long 0x4194++0x03
line.long 0x00 "INTCLR2_B2A0,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).."
abitfld.long 0x00 0.--31. "INTCLR_31_0,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register" "0x00000000=0: No effect,0x00000001=1: Interrupt display"
group.long 0x4198++0x03
line.long 0x00 "INTMSK2_B2A0,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch"
abitfld.long 0x00 0.--31. "INTMSK_31_0,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block" "0x00000000=0: Interrupt is masked,0x00000001=1: Interrupt is not masked"
group.long 0x419C++0x03
line.long 0x00 "MSKCLR2_B2A0,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A"
abitfld.long 0x00 0.--31. "MSKCLR_31_0,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block" "0x00000000=0: No effect,0x00000001=1: Interrupt is not masked"
group.long 0x41A0++0x03
line.long 0x00 "POSNEG2_B2A0,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode general output mode or interrupt input mode"
abitfld.long 0x00 0.--31. "POSNEG_31_0,Selects the polarity (positive or negative logic) of each port pin" "0x00000000=0: Positive logic,0x00000001=1: Negative logic"
group.long 0x41A4++0x03
line.long 0x00 "EDGLEVEL2_B2A0,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "EDGLEVEL_31_0,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected" "0x00000000=0: Level,0x00000001=1: Edge"
group.long 0x41A8++0x03
line.long 0x00 "FILONOFF2_B2A0,FILONOFFn prevents chattering input to the port pins of each GPIO group"
abitfld.long 0x00 0.--31. "FILONOFF_31_0,Enables or disables the chattering prevention function" "0x00000000=0: Chattering prevention function is..,0x00000001=1: Chattering prevention function is.."
group.long 0x41AC++0x03
line.long 0x00 "FILCLKSEL2_B2A0,FILCLKSELn controls the division ratio of clock CP? for prevent chattering input to the port pin GPIO group"
hexmask.long 0x00 0.--31. 1. "FILCLKSEL_31_0,Set the division ratio of filter CLOCK"
group.long 0x41C0++0x03
line.long 0x00 "OUTDTSEL2_B2A0,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDTSEL_31_0,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn" "0x00000000=0: General output register is used to..,0x00000001=1: Output data high register and.."
group.long 0x41C4++0x03
line.long 0x00 "OUTDTH2_B2A0,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTH_31_0,Outputting high value data" "0x00000000=0: Invalid data,0x00000001=1: Valid data"
group.long 0x41C8++0x03
line.long 0x00 "OUTDTL2_B2A0,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTL_31_0,Outputting low value data" "0x00000000=0: Valid data,0x00000001=1: Invalid data"
group.long 0x41CC++0x03
line.long 0x00 "BOTHEDGE2_B2A0,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers"
abitfld.long 0x00 0.--31. "BOTHEDGE_31_0,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected" "0x00000000=0: One edge,0x00000001=1: Both edges"
group.long 0x41D0++0x03
line.long 0x00 "INEN2_B2A0,Create registers that can control IE in GPIO"
hexmask.long 0x00 0.--31. 1. "INEN_31_0,"
group.long 0x4200++0x03
line.long 0x00 "PMMR2_B2A1,PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers"
hexmask.long 0x00 0.--31. 1. "PMMR_31_0,Multiplexed Pin Setting Mask Writing a value to any register from among the GPSR IPSR DRVCTRL TDSEL POC PUEN PUD MODSEL DMPR PSER PSSR PINV PIS registers is enabled by writing the inverse of the value to this register"
group.long 0x4204++0x03
line.long 0x00 "PMMER2_B2A1,PMMERn / PMMERSYS performs enables / disables control of the PMMR"
abitfld.long 0x00 0.--31. "PMMER_31_0,Multiplexed Pin Setting Mask Enable" "0x00000000=0: PMMR function is disabled,0x00000001=1: PMMR function is enabled"
group.long 0x4220++0x03
line.long 0x00 "DM0PR2_B2A1,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM0PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x4224++0x03
line.long 0x00 "DM1PR2_B2A1,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM1PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x4228++0x03
line.long 0x00 "DM2PR2_B2A1,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM2PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x422C++0x03
line.long 0x00 "DM3PR2_B2A1,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM3PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x4240++0x03
line.long 0x00 "GPSR2_B2A1,GPSRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "GPSR_31_0,"
group.long 0x4280++0x03
line.long 0x00 "DRV0CTRL2_B2A1,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV0CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x4284++0x03
line.long 0x00 "DRV1CTRL2_B2A1,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV1CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x4288++0x03
line.long 0x00 "DRV2CTRL2_B2A1,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV2CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x42C0++0x03
line.long 0x00 "PUEN2_B2A1,PUENn / PUENSYS performs on / off control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUEN_31_0,"
group.long 0x42E0++0x03
line.long 0x00 "PUD2_B2A1,PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUD_31_0,"
group.long 0x4360++0x03
line.long 0x00 "PSER2_B2A1,The register (PSERn) to enable / disable PSS Rregister"
hexmask.long 0x00 0.--31. 1. "PSER_31_0,"
group.long 0x4364++0x03
line.long 0x00 "PS0SR2_B2A1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS0SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x4368++0x03
line.long 0x00 "PS1SR2_B2A1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS1SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x4380++0x03
line.long 0x00 "IOINTSEL2_B2A1,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group"
abitfld.long 0x00 0.--31. "IOINTSEL_31_0,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input/output mode,0x00000001=1: Interrupt input mode"
group.long 0x4384++0x03
line.long 0x00 "INOUTSEL2_B2A1,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INOUTSEL_31_0,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input mode,0x00000001=1: General output mode"
group.long 0x4388++0x03
line.long 0x00 "OUTDT2_B2A1,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDT_31_0,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL" "0x00000000=0: 0 is output,0x00000001=1: 1 is output"
group.long 0x438C++0x03
line.long 0x00 "INDT2_B2A1,INDTn is a register that can read the status of General-Purpose Input / Output Ports"
abitfld.long 0x00 0.--31. "INDT_31_0,Each bit reflects the value received through the corresponding port pin" "0x00000000=0: Input is 0,0x00000001=1: Input is 1"
group.long 0x4390++0x03
line.long 0x00 "INTDT2_B2A1,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INTDT_31_0,Each bit indicates the input of an interrupt signal on the corresponding port pin" "0x00000000=0: No interrupt signal has been input,0x00000001=1: Interrupt signal has been input"
group.long 0x4394++0x03
line.long 0x00 "INTCLR2_B2A1,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).."
abitfld.long 0x00 0.--31. "INTCLR_31_0,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register" "0x00000000=0: No effect,0x00000001=1: Interrupt display"
group.long 0x4398++0x03
line.long 0x00 "INTMSK2_B2A1,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch"
abitfld.long 0x00 0.--31. "INTMSK_31_0,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block" "0x00000000=0: Interrupt is masked,0x00000001=1: Interrupt is not masked"
group.long 0x439C++0x03
line.long 0x00 "MSKCLR2_B2A1,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A"
abitfld.long 0x00 0.--31. "MSKCLR_31_0,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block" "0x00000000=0: No effect,0x00000001=1: Interrupt is not masked"
group.long 0x43A0++0x03
line.long 0x00 "POSNEG2_B2A1,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode general output mode or interrupt input mode"
abitfld.long 0x00 0.--31. "POSNEG_31_0,Selects the polarity (positive or negative logic) of each port pin" "0x00000000=0: Positive logic,0x00000001=1: Negative logic"
group.long 0x43A4++0x03
line.long 0x00 "EDGLEVEL2_B2A1,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "EDGLEVEL_31_0,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected" "0x00000000=0: Level,0x00000001=1: Edge"
group.long 0x43A8++0x03
line.long 0x00 "FILONOFF2_B2A1,FILONOFFn prevents chattering input to the port pins of each GPIO group"
abitfld.long 0x00 0.--31. "FILONOFF_31_0,Enables or disables the chattering prevention function" "0x00000000=0: Chattering prevention function is..,0x00000001=1: Chattering prevention function is.."
group.long 0x43AC++0x03
line.long 0x00 "FILCLKSEL2_B2A1,FILCLKSELn controls the division ratio of clock CP? for prevent chattering input to the port pin GPIO group"
hexmask.long 0x00 0.--31. 1. "FILCLKSEL_31_0,Set the division ratio of filter CLOCK"
group.long 0x43C0++0x03
line.long 0x00 "OUTDTSEL2_B2A1,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDTSEL_31_0,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn" "0x00000000=0: General output register is used to..,0x00000001=1: Output data high register and.."
group.long 0x43C4++0x03
line.long 0x00 "OUTDTH2_B2A1,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTH_31_0,Outputting high value data" "0x00000000=0: Invalid data,0x00000001=1: Valid data"
group.long 0x43C8++0x03
line.long 0x00 "OUTDTL2_B2A1,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTL_31_0,Outputting low value data" "0x00000000=0: Valid data,0x00000001=1: Invalid data"
group.long 0x43CC++0x03
line.long 0x00 "BOTHEDGE2_B2A1,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers"
abitfld.long 0x00 0.--31. "BOTHEDGE_31_0,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected" "0x00000000=0: One edge,0x00000001=1: Both edges"
group.long 0x43D0++0x03
line.long 0x00 "INEN2_B2A1,Create registers that can control IE in GPIO"
hexmask.long 0x00 0.--31. 1. "INEN_31_0,"
group.long 0x4400++0x03
line.long 0x00 "PMMR2_B2A2,PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers"
hexmask.long 0x00 0.--31. 1. "PMMR_31_0,Multiplexed Pin Setting Mask Writing a value to any register from among the GPSR IPSR DRVCTRL TDSEL POC PUEN PUD MODSEL DMPR PSER PSSR PINV PIS registers is enabled by writing the inverse of the value to this register"
group.long 0x4404++0x03
line.long 0x00 "PMMER2_B2A2,PMMERn / PMMERSYS performs enables / disables control of the PMMR"
abitfld.long 0x00 0.--31. "PMMER_31_0,Multiplexed Pin Setting Mask Enable" "0x00000000=0: PMMR function is disabled,0x00000001=1: PMMR function is enabled"
group.long 0x4420++0x03
line.long 0x00 "DM0PR2_B2A2,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM0PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x4424++0x03
line.long 0x00 "DM1PR2_B2A2,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM1PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x4428++0x03
line.long 0x00 "DM2PR2_B2A2,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM2PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x442C++0x03
line.long 0x00 "DM3PR2_B2A2,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM3PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x4440++0x03
line.long 0x00 "GPSR2_B2A2,GPSRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "GPSR_31_0,"
group.long 0x4480++0x03
line.long 0x00 "DRV0CTRL2_B2A2,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV0CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x4484++0x03
line.long 0x00 "DRV1CTRL2_B2A2,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV1CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x4488++0x03
line.long 0x00 "DRV2CTRL2_B2A2,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV2CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x44C0++0x03
line.long 0x00 "PUEN2_B2A2,PUENn / PUENSYS performs on / off control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUEN_31_0,"
group.long 0x44E0++0x03
line.long 0x00 "PUD2_B2A2,PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUD_31_0,"
group.long 0x4560++0x03
line.long 0x00 "PSER2_B2A2,The register (PSERn) to enable / disable PSS Rregister"
hexmask.long 0x00 0.--31. 1. "PSER_31_0,"
group.long 0x4564++0x03
line.long 0x00 "PS0SR2_B2A2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS0SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x4568++0x03
line.long 0x00 "PS1SR2_B2A2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS1SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x4580++0x03
line.long 0x00 "IOINTSEL2_B2A2,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group"
abitfld.long 0x00 0.--31. "IOINTSEL_31_0,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input/output mode,0x00000001=1: Interrupt input mode"
group.long 0x4584++0x03
line.long 0x00 "INOUTSEL2_B2A2,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INOUTSEL_31_0,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input mode,0x00000001=1: General output mode"
group.long 0x4588++0x03
line.long 0x00 "OUTDT2_B2A2,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDT_31_0,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL" "0x00000000=0: 0 is output,0x00000001=1: 1 is output"
group.long 0x458C++0x03
line.long 0x00 "INDT2_B2A2,INDTn is a register that can read the status of General-Purpose Input / Output Ports"
abitfld.long 0x00 0.--31. "INDT_31_0,Each bit reflects the value received through the corresponding port pin" "0x00000000=0: Input is 0,0x00000001=1: Input is 1"
group.long 0x4590++0x03
line.long 0x00 "INTDT2_B2A2,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INTDT_31_0,Each bit indicates the input of an interrupt signal on the corresponding port pin" "0x00000000=0: No interrupt signal has been input,0x00000001=1: Interrupt signal has been input"
group.long 0x4594++0x03
line.long 0x00 "INTCLR2_B2A2,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).."
abitfld.long 0x00 0.--31. "INTCLR_31_0,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register" "0x00000000=0: No effect,0x00000001=1: Interrupt display"
group.long 0x4598++0x03
line.long 0x00 "INTMSK2_B2A2,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch"
abitfld.long 0x00 0.--31. "INTMSK_31_0,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block" "0x00000000=0: Interrupt is masked,0x00000001=1: Interrupt is not masked"
group.long 0x459C++0x03
line.long 0x00 "MSKCLR2_B2A2,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A"
abitfld.long 0x00 0.--31. "MSKCLR_31_0,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block" "0x00000000=0: No effect,0x00000001=1: Interrupt is not masked"
group.long 0x45A0++0x03
line.long 0x00 "POSNEG2_B2A2,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode general output mode or interrupt input mode"
abitfld.long 0x00 0.--31. "POSNEG_31_0,Selects the polarity (positive or negative logic) of each port pin" "0x00000000=0: Positive logic,0x00000001=1: Negative logic"
group.long 0x45A4++0x03
line.long 0x00 "EDGLEVEL2_B2A2,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "EDGLEVEL_31_0,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected" "0x00000000=0: Level,0x00000001=1: Edge"
group.long 0x45A8++0x03
line.long 0x00 "FILONOFF2_B2A2,FILONOFFn prevents chattering input to the port pins of each GPIO group"
abitfld.long 0x00 0.--31. "FILONOFF_31_0,Enables or disables the chattering prevention function" "0x00000000=0: Chattering prevention function is..,0x00000001=1: Chattering prevention function is.."
group.long 0x45AC++0x03
line.long 0x00 "FILCLKSEL2_B2A2,FILCLKSELn controls the division ratio of clock CP? for prevent chattering input to the port pin GPIO group"
hexmask.long 0x00 0.--31. 1. "FILCLKSEL_31_0,Set the division ratio of filter CLOCK"
group.long 0x45C0++0x03
line.long 0x00 "OUTDTSEL2_B2A2,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDTSEL_31_0,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn" "0x00000000=0: General output register is used to..,0x00000001=1: Output data high register and.."
group.long 0x45C4++0x03
line.long 0x00 "OUTDTH2_B2A2,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTH_31_0,Outputting high value data" "0x00000000=0: Invalid data,0x00000001=1: Valid data"
group.long 0x45C8++0x03
line.long 0x00 "OUTDTL2_B2A2,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTL_31_0,Outputting low value data" "0x00000000=0: Valid data,0x00000001=1: Invalid data"
group.long 0x45CC++0x03
line.long 0x00 "BOTHEDGE2_B2A2,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers"
abitfld.long 0x00 0.--31. "BOTHEDGE_31_0,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected" "0x00000000=0: One edge,0x00000001=1: Both edges"
group.long 0x45D0++0x03
line.long 0x00 "INEN2_B2A2,Create registers that can control IE in GPIO"
hexmask.long 0x00 0.--31. 1. "INEN_31_0,"
group.long 0x6000++0x03
line.long 0x00 "PMMR2_B3A0,PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers"
hexmask.long 0x00 0.--31. 1. "PMMR_31_0,Multiplexed Pin Setting Mask Writing a value to any register from among the GPSR IPSR DRVCTRL TDSEL POC PUEN PUD MODSEL DMPR PSER PSSR PINV PIS registers is enabled by writing the inverse of the value to this register"
group.long 0x6004++0x03
line.long 0x00 "PMMER2_B3A0,PMMERn / PMMERSYS performs enables / disables control of the PMMR"
abitfld.long 0x00 0.--31. "PMMER_31_0,Multiplexed Pin Setting Mask Enable" "0x00000000=0: PMMR function is disabled,0x00000001=1: PMMR function is enabled"
group.long 0x6020++0x03
line.long 0x00 "DM0PR2_B3A0,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM0PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x6024++0x03
line.long 0x00 "DM1PR2_B3A0,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM1PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x6028++0x03
line.long 0x00 "DM2PR2_B3A0,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM2PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x602C++0x03
line.long 0x00 "DM3PR2_B3A0,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM3PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x6040++0x03
line.long 0x00 "GPSR2_B3A0,GPSRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "GPSR_31_0,"
group.long 0x6080++0x03
line.long 0x00 "DRV0CTRL2_B3A0,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV0CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x6084++0x03
line.long 0x00 "DRV1CTRL2_B3A0,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV1CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x6088++0x03
line.long 0x00 "DRV2CTRL2_B3A0,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV2CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x60C0++0x03
line.long 0x00 "PUEN2_B3A0,PUENn / PUENSYS performs on / off control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUEN_31_0,"
group.long 0x60E0++0x03
line.long 0x00 "PUD2_B3A0,PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUD_31_0,"
group.long 0x6160++0x03
line.long 0x00 "PSER2_B3A0,The register (PSERn) to enable / disable PSS Rregister"
hexmask.long 0x00 0.--31. 1. "PSER_31_0,"
group.long 0x6164++0x03
line.long 0x00 "PS0SR2_B3A0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS0SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x6168++0x03
line.long 0x00 "PS1SR2_B3A0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS1SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x6180++0x03
line.long 0x00 "IOINTSEL2_B3A0,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group"
abitfld.long 0x00 0.--31. "IOINTSEL_31_0,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input/output mode,0x00000001=1: Interrupt input mode"
group.long 0x6184++0x03
line.long 0x00 "INOUTSEL2_B3A0,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INOUTSEL_31_0,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input mode,0x00000001=1: General output mode"
group.long 0x6188++0x03
line.long 0x00 "OUTDT2_B3A0,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDT_31_0,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL" "0x00000000=0: 0 is output,0x00000001=1: 1 is output"
group.long 0x618C++0x03
line.long 0x00 "INDT2_B3A0,INDTn is a register that can read the status of General-Purpose Input / Output Ports"
abitfld.long 0x00 0.--31. "INDT_31_0,Each bit reflects the value received through the corresponding port pin" "0x00000000=0: Input is 0,0x00000001=1: Input is 1"
group.long 0x6190++0x03
line.long 0x00 "INTDT2_B3A0,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INTDT_31_0,Each bit indicates the input of an interrupt signal on the corresponding port pin" "0x00000000=0: No interrupt signal has been input,0x00000001=1: Interrupt signal has been input"
group.long 0x6194++0x03
line.long 0x00 "INTCLR2_B3A0,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).."
abitfld.long 0x00 0.--31. "INTCLR_31_0,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register" "0x00000000=0: No effect,0x00000001=1: Interrupt display"
group.long 0x6198++0x03
line.long 0x00 "INTMSK2_B3A0,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch"
abitfld.long 0x00 0.--31. "INTMSK_31_0,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block" "0x00000000=0: Interrupt is masked,0x00000001=1: Interrupt is not masked"
group.long 0x619C++0x03
line.long 0x00 "MSKCLR2_B3A0,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A"
abitfld.long 0x00 0.--31. "MSKCLR_31_0,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block" "0x00000000=0: No effect,0x00000001=1: Interrupt is not masked"
group.long 0x61A0++0x03
line.long 0x00 "POSNEG2_B3A0,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode general output mode or interrupt input mode"
abitfld.long 0x00 0.--31. "POSNEG_31_0,Selects the polarity (positive or negative logic) of each port pin" "0x00000000=0: Positive logic,0x00000001=1: Negative logic"
group.long 0x61A4++0x03
line.long 0x00 "EDGLEVEL2_B3A0,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "EDGLEVEL_31_0,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected" "0x00000000=0: Level,0x00000001=1: Edge"
group.long 0x61A8++0x03
line.long 0x00 "FILONOFF2_B3A0,FILONOFFn prevents chattering input to the port pins of each GPIO group"
abitfld.long 0x00 0.--31. "FILONOFF_31_0,Enables or disables the chattering prevention function" "0x00000000=0: Chattering prevention function is..,0x00000001=1: Chattering prevention function is.."
group.long 0x61AC++0x03
line.long 0x00 "FILCLKSEL2_B3A0,FILCLKSELn controls the division ratio of clock CP? for prevent chattering input to the port pin GPIO group"
hexmask.long 0x00 0.--31. 1. "FILCLKSEL_31_0,Set the division ratio of filter CLOCK"
group.long 0x61C0++0x03
line.long 0x00 "OUTDTSEL2_B3A0,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDTSEL_31_0,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn" "0x00000000=0: General output register is used to..,0x00000001=1: Output data high register and.."
group.long 0x61C4++0x03
line.long 0x00 "OUTDTH2_B3A0,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTH_31_0,Outputting high value data" "0x00000000=0: Invalid data,0x00000001=1: Valid data"
group.long 0x61C8++0x03
line.long 0x00 "OUTDTL2_B3A0,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTL_31_0,Outputting low value data" "0x00000000=0: Valid data,0x00000001=1: Invalid data"
group.long 0x61CC++0x03
line.long 0x00 "BOTHEDGE2_B3A0,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers"
abitfld.long 0x00 0.--31. "BOTHEDGE_31_0,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected" "0x00000000=0: One edge,0x00000001=1: Both edges"
group.long 0x61D0++0x03
line.long 0x00 "INEN2_B3A0,Create registers that can control IE in GPIO"
hexmask.long 0x00 0.--31. 1. "INEN_31_0,"
group.long 0x6200++0x03
line.long 0x00 "PMMR2_B3A1,PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers"
hexmask.long 0x00 0.--31. 1. "PMMR_31_0,Multiplexed Pin Setting Mask Writing a value to any register from among the GPSR IPSR DRVCTRL TDSEL POC PUEN PUD MODSEL DMPR PSER PSSR PINV PIS registers is enabled by writing the inverse of the value to this register"
group.long 0x6204++0x03
line.long 0x00 "PMMER2_B3A1,PMMERn / PMMERSYS performs enables / disables control of the PMMR"
abitfld.long 0x00 0.--31. "PMMER_31_0,Multiplexed Pin Setting Mask Enable" "0x00000000=0: PMMR function is disabled,0x00000001=1: PMMR function is enabled"
group.long 0x6220++0x03
line.long 0x00 "DM0PR2_B3A1,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM0PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x6224++0x03
line.long 0x00 "DM1PR2_B3A1,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM1PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x6228++0x03
line.long 0x00 "DM2PR2_B3A1,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM2PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x622C++0x03
line.long 0x00 "DM3PR2_B3A1,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM3PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x6240++0x03
line.long 0x00 "GPSR2_B3A1,GPSRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "GPSR_31_0,"
group.long 0x6280++0x03
line.long 0x00 "DRV0CTRL2_B3A1,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV0CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x6284++0x03
line.long 0x00 "DRV1CTRL2_B3A1,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV1CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x6288++0x03
line.long 0x00 "DRV2CTRL2_B3A1,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV2CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x62C0++0x03
line.long 0x00 "PUEN2_B3A1,PUENn / PUENSYS performs on / off control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUEN_31_0,"
group.long 0x62E0++0x03
line.long 0x00 "PUD2_B3A1,PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUD_31_0,"
group.long 0x6360++0x03
line.long 0x00 "PSER2_B3A1,The register (PSERn) to enable / disable PSS Rregister"
hexmask.long 0x00 0.--31. 1. "PSER_31_0,"
group.long 0x6364++0x03
line.long 0x00 "PS0SR2_B3A1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS0SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x6368++0x03
line.long 0x00 "PS1SR2_B3A1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS1SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x6380++0x03
line.long 0x00 "IOINTSEL2_B3A1,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group"
abitfld.long 0x00 0.--31. "IOINTSEL_31_0,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input/output mode,0x00000001=1: Interrupt input mode"
group.long 0x6384++0x03
line.long 0x00 "INOUTSEL2_B3A1,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INOUTSEL_31_0,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input mode,0x00000001=1: General output mode"
group.long 0x6388++0x03
line.long 0x00 "OUTDT2_B3A1,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDT_31_0,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL" "0x00000000=0: 0 is output,0x00000001=1: 1 is output"
group.long 0x638C++0x03
line.long 0x00 "INDT2_B3A1,INDTn is a register that can read the status of General-Purpose Input / Output Ports"
abitfld.long 0x00 0.--31. "INDT_31_0,Each bit reflects the value received through the corresponding port pin" "0x00000000=0: Input is 0,0x00000001=1: Input is 1"
group.long 0x6390++0x03
line.long 0x00 "INTDT2_B3A1,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INTDT_31_0,Each bit indicates the input of an interrupt signal on the corresponding port pin" "0x00000000=0: No interrupt signal has been input,0x00000001=1: Interrupt signal has been input"
group.long 0x6394++0x03
line.long 0x00 "INTCLR2_B3A1,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).."
abitfld.long 0x00 0.--31. "INTCLR_31_0,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register" "0x00000000=0: No effect,0x00000001=1: Interrupt display"
group.long 0x6398++0x03
line.long 0x00 "INTMSK2_B3A1,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch"
abitfld.long 0x00 0.--31. "INTMSK_31_0,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block" "0x00000000=0: Interrupt is masked,0x00000001=1: Interrupt is not masked"
group.long 0x639C++0x03
line.long 0x00 "MSKCLR2_B3A1,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A"
abitfld.long 0x00 0.--31. "MSKCLR_31_0,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block" "0x00000000=0: No effect,0x00000001=1: Interrupt is not masked"
group.long 0x63A0++0x03
line.long 0x00 "POSNEG2_B3A1,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode general output mode or interrupt input mode"
abitfld.long 0x00 0.--31. "POSNEG_31_0,Selects the polarity (positive or negative logic) of each port pin" "0x00000000=0: Positive logic,0x00000001=1: Negative logic"
group.long 0x63A4++0x03
line.long 0x00 "EDGLEVEL2_B3A1,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "EDGLEVEL_31_0,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected" "0x00000000=0: Level,0x00000001=1: Edge"
group.long 0x63A8++0x03
line.long 0x00 "FILONOFF2_B3A1,FILONOFFn prevents chattering input to the port pins of each GPIO group"
abitfld.long 0x00 0.--31. "FILONOFF_31_0,Enables or disables the chattering prevention function" "0x00000000=0: Chattering prevention function is..,0x00000001=1: Chattering prevention function is.."
group.long 0x63AC++0x03
line.long 0x00 "FILCLKSEL2_B3A1,FILCLKSELn controls the division ratio of clock CP? for prevent chattering input to the port pin GPIO group"
hexmask.long 0x00 0.--31. 1. "FILCLKSEL_31_0,Set the division ratio of filter CLOCK"
group.long 0x63C0++0x03
line.long 0x00 "OUTDTSEL2_B3A1,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDTSEL_31_0,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn" "0x00000000=0: General output register is used to..,0x00000001=1: Output data high register and.."
group.long 0x63C4++0x03
line.long 0x00 "OUTDTH2_B3A1,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTH_31_0,Outputting high value data" "0x00000000=0: Invalid data,0x00000001=1: Valid data"
group.long 0x63C8++0x03
line.long 0x00 "OUTDTL2_B3A1,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTL_31_0,Outputting low value data" "0x00000000=0: Valid data,0x00000001=1: Invalid data"
group.long 0x63CC++0x03
line.long 0x00 "BOTHEDGE2_B3A1,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers"
abitfld.long 0x00 0.--31. "BOTHEDGE_31_0,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected" "0x00000000=0: One edge,0x00000001=1: Both edges"
group.long 0x63D0++0x03
line.long 0x00 "INEN2_B3A1,Create registers that can control IE in GPIO"
hexmask.long 0x00 0.--31. 1. "INEN_31_0,"
group.long 0x6400++0x03
line.long 0x00 "PMMR2_B3A2,PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers"
hexmask.long 0x00 0.--31. 1. "PMMR_31_0,Multiplexed Pin Setting Mask Writing a value to any register from among the GPSR IPSR DRVCTRL TDSEL POC PUEN PUD MODSEL DMPR PSER PSSR PINV PIS registers is enabled by writing the inverse of the value to this register"
group.long 0x6404++0x03
line.long 0x00 "PMMER2_B3A2,PMMERn / PMMERSYS performs enables / disables control of the PMMR"
abitfld.long 0x00 0.--31. "PMMER_31_0,Multiplexed Pin Setting Mask Enable" "0x00000000=0: PMMR function is disabled,0x00000001=1: PMMR function is enabled"
group.long 0x6420++0x03
line.long 0x00 "DM0PR2_B3A2,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM0PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x6424++0x03
line.long 0x00 "DM1PR2_B3A2,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM1PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x6428++0x03
line.long 0x00 "DM2PR2_B3A2,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM2PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x642C++0x03
line.long 0x00 "DM3PR2_B3A2,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM3PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x6440++0x03
line.long 0x00 "GPSR2_B3A2,GPSRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "GPSR_31_0,"
group.long 0x6480++0x03
line.long 0x00 "DRV0CTRL2_B3A2,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV0CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x6484++0x03
line.long 0x00 "DRV1CTRL2_B3A2,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV1CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x6488++0x03
line.long 0x00 "DRV2CTRL2_B3A2,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV2CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x64C0++0x03
line.long 0x00 "PUEN2_B3A2,PUENn / PUENSYS performs on / off control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUEN_31_0,"
group.long 0x64E0++0x03
line.long 0x00 "PUD2_B3A2,PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUD_31_0,"
group.long 0x6560++0x03
line.long 0x00 "PSER2_B3A2,The register (PSERn) to enable / disable PSS Rregister"
hexmask.long 0x00 0.--31. 1. "PSER_31_0,"
group.long 0x6564++0x03
line.long 0x00 "PS0SR2_B3A2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS0SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x6568++0x03
line.long 0x00 "PS1SR2_B3A2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS1SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x6580++0x03
line.long 0x00 "IOINTSEL2_B3A2,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group"
abitfld.long 0x00 0.--31. "IOINTSEL_31_0,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input/output mode,0x00000001=1: Interrupt input mode"
group.long 0x6584++0x03
line.long 0x00 "INOUTSEL2_B3A2,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INOUTSEL_31_0,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input mode,0x00000001=1: General output mode"
group.long 0x6588++0x03
line.long 0x00 "OUTDT2_B3A2,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDT_31_0,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL" "0x00000000=0: 0 is output,0x00000001=1: 1 is output"
group.long 0x658C++0x03
line.long 0x00 "INDT2_B3A2,INDTn is a register that can read the status of General-Purpose Input / Output Ports"
abitfld.long 0x00 0.--31. "INDT_31_0,Each bit reflects the value received through the corresponding port pin" "0x00000000=0: Input is 0,0x00000001=1: Input is 1"
group.long 0x6590++0x03
line.long 0x00 "INTDT2_B3A2,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INTDT_31_0,Each bit indicates the input of an interrupt signal on the corresponding port pin" "0x00000000=0: No interrupt signal has been input,0x00000001=1: Interrupt signal has been input"
group.long 0x6594++0x03
line.long 0x00 "INTCLR2_B3A2,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).."
abitfld.long 0x00 0.--31. "INTCLR_31_0,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register" "0x00000000=0: No effect,0x00000001=1: Interrupt display"
group.long 0x6598++0x03
line.long 0x00 "INTMSK2_B3A2,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch"
abitfld.long 0x00 0.--31. "INTMSK_31_0,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block" "0x00000000=0: Interrupt is masked,0x00000001=1: Interrupt is not masked"
group.long 0x659C++0x03
line.long 0x00 "MSKCLR2_B3A2,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A"
abitfld.long 0x00 0.--31. "MSKCLR_31_0,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block" "0x00000000=0: No effect,0x00000001=1: Interrupt is not masked"
group.long 0x65A0++0x03
line.long 0x00 "POSNEG2_B3A2,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode general output mode or interrupt input mode"
abitfld.long 0x00 0.--31. "POSNEG_31_0,Selects the polarity (positive or negative logic) of each port pin" "0x00000000=0: Positive logic,0x00000001=1: Negative logic"
group.long 0x65A4++0x03
line.long 0x00 "EDGLEVEL2_B3A2,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "EDGLEVEL_31_0,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected" "0x00000000=0: Level,0x00000001=1: Edge"
group.long 0x65A8++0x03
line.long 0x00 "FILONOFF2_B3A2,FILONOFFn prevents chattering input to the port pins of each GPIO group"
abitfld.long 0x00 0.--31. "FILONOFF_31_0,Enables or disables the chattering prevention function" "0x00000000=0: Chattering prevention function is..,0x00000001=1: Chattering prevention function is.."
group.long 0x65AC++0x03
line.long 0x00 "FILCLKSEL2_B3A2,FILCLKSELn controls the division ratio of clock CP? for prevent chattering input to the port pin GPIO group"
hexmask.long 0x00 0.--31. 1. "FILCLKSEL_31_0,Set the division ratio of filter CLOCK"
group.long 0x65C0++0x03
line.long 0x00 "OUTDTSEL2_B3A2,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDTSEL_31_0,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn" "0x00000000=0: General output register is used to..,0x00000001=1: Output data high register and.."
group.long 0x65C4++0x03
line.long 0x00 "OUTDTH2_B3A2,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTH_31_0,Outputting high value data" "0x00000000=0: Invalid data,0x00000001=1: Valid data"
group.long 0x65C8++0x03
line.long 0x00 "OUTDTL2_B3A2,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTL_31_0,Outputting low value data" "0x00000000=0: Valid data,0x00000001=1: Invalid data"
group.long 0x65CC++0x03
line.long 0x00 "BOTHEDGE2_B3A2,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers"
abitfld.long 0x00 0.--31. "BOTHEDGE_31_0,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected" "0x00000000=0: One edge,0x00000001=1: Both edges"
group.long 0x65D0++0x03
line.long 0x00 "INEN2_B3A2,Create registers that can control IE in GPIO"
hexmask.long 0x00 0.--31. 1. "INEN_31_0,"
tree.end
tree "PFC_GPIO_FOR_GP3"
base ad:0xE6051800
group.long 0x00++0x03
line.long 0x00 "PMMR3_B0A0,PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers"
hexmask.long 0x00 0.--31. 1. "PMMR_31_0,Multiplexed Pin Setting Mask Writing a value to any register from among the GPSR IPSR DRVCTRL TDSEL POC PUEN PUD MODSEL DMPR PSER PSSR PINV PIS registers is enabled by writing the inverse of the value to this register"
group.long 0x04++0x03
line.long 0x00 "PMMER3_B0A0,PMMERn / PMMERSYS performs enables / disables control of the PMMR"
abitfld.long 0x00 0.--31. "PMMER_31_0,Multiplexed Pin Setting Mask Enable" "0x00000000=0: PMMR function is disabled,0x00000001=1: PMMR function is enabled"
group.long 0x20++0x03
line.long 0x00 "DM0PR3_B0A0,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM0PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x24++0x03
line.long 0x00 "DM1PR3_B0A0,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM1PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x28++0x03
line.long 0x00 "DM2PR3_B0A0,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM2PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x2C++0x03
line.long 0x00 "DM3PR3_B0A0,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM3PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x40++0x03
line.long 0x00 "GPSR3_B0A0,GPSRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "GPSR_31_0,"
group.long 0x80++0x03
line.long 0x00 "DRV0CTRL3_B0A0,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV0CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x84++0x03
line.long 0x00 "DRV1CTRL3_B0A0,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV1CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x88++0x03
line.long 0x00 "DRV2CTRL3_B0A0,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV2CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0xA0++0x03
line.long 0x00 "POC3_B0A0,Each bit in POCn / POCSYS must be set according to IO voltage level that is supplied to the pin"
abitfld.long 0x00 0.--31. "POC_31_0,- For 1.8V/3.3 V" "0x00000000=0: 2.5V,0x00000001=1: 3.3V"
group.long 0xC0++0x03
line.long 0x00 "PUEN3_B0A0,PUENn / PUENSYS performs on / off control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUEN_31_0,"
group.long 0xE0++0x03
line.long 0x00 "PUD3_B0A0,PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUD_31_0,"
group.long 0x160++0x03
line.long 0x00 "PSER3_B0A0,The register (PSERn) to enable / disable PSS Rregister"
hexmask.long 0x00 0.--31. 1. "PSER_31_0,"
group.long 0x164++0x03
line.long 0x00 "PS0SR3_B0A0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS0SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x168++0x03
line.long 0x00 "PS1SR3_B0A0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS1SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x180++0x03
line.long 0x00 "IOINTSEL3_B0A0,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group"
abitfld.long 0x00 0.--31. "IOINTSEL_31_0,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input/output mode,0x00000001=1: Interrupt input mode"
group.long 0x184++0x03
line.long 0x00 "INOUTSEL3_B0A0,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INOUTSEL_31_0,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input mode,0x00000001=1: General output mode"
group.long 0x188++0x03
line.long 0x00 "OUTDT3_B0A0,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDT_31_0,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL" "0x00000000=0: 0 is output,0x00000001=1: 1 is output"
group.long 0x18C++0x03
line.long 0x00 "INDT3_B0A0,INDTn is a register that can read the status of General-Purpose Input / Output Ports"
abitfld.long 0x00 0.--31. "INDT_31_0,Each bit reflects the value received through the corresponding port pin" "0x00000000=0: Input is 0,0x00000001=1: Input is 1"
group.long 0x190++0x03
line.long 0x00 "INTDT3_B0A0,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INTDT_31_0,Each bit indicates the input of an interrupt signal on the corresponding port pin" "0x00000000=0: No interrupt signal has been input,0x00000001=1: Interrupt signal has been input"
group.long 0x194++0x03
line.long 0x00 "INTCLR3_B0A0,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).."
abitfld.long 0x00 0.--31. "INTCLR_31_0,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register" "0x00000000=0: No effect,0x00000001=1: Interrupt display"
group.long 0x198++0x03
line.long 0x00 "INTMSK3_B0A0,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch"
abitfld.long 0x00 0.--31. "INTMSK_31_0,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block" "0x00000000=0: Interrupt is masked,0x00000001=1: Interrupt is not masked"
group.long 0x19C++0x03
line.long 0x00 "MSKCLR3_B0A0,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A"
abitfld.long 0x00 0.--31. "MSKCLR_31_0,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block" "0x00000000=0: No effect,0x00000001=1: Interrupt is not masked"
group.long 0x1A0++0x03
line.long 0x00 "POSNEG3_B0A0,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode general output mode or interrupt input mode"
abitfld.long 0x00 0.--31. "POSNEG_31_0,Selects the polarity (positive or negative logic) of each port pin" "0x00000000=0: Positive logic,0x00000001=1: Negative logic"
group.long 0x1A4++0x03
line.long 0x00 "EDGLEVEL3_B0A0,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "EDGLEVEL_31_0,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected" "0x00000000=0: Level,0x00000001=1: Edge"
group.long 0x1A8++0x03
line.long 0x00 "FILONOFF3_B0A0,FILONOFFn prevents chattering input to the port pins of each GPIO group"
abitfld.long 0x00 0.--31. "FILONOFF_31_0,Enables or disables the chattering prevention function" "0x00000000=0: Chattering prevention function is..,0x00000001=1: Chattering prevention function is.."
group.long 0x1AC++0x03
line.long 0x00 "FILCLKSEL3_B0A0,FILCLKSELn controls the division ratio of clock CP? for prevent chattering input to the port pin GPIO group"
hexmask.long 0x00 0.--31. 1. "FILCLKSEL_31_0,Set the division ratio of filter CLOCK"
group.long 0x1C0++0x03
line.long 0x00 "OUTDTSEL3_B0A0,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDTSEL_31_0,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn" "0x00000000=0: General output register is used to..,0x00000001=1: Output data high register and.."
group.long 0x1C4++0x03
line.long 0x00 "OUTDTH3_B0A0,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTH_31_0,Outputting high value data" "0x00000000=0: Invalid data,0x00000001=1: Valid data"
group.long 0x1C8++0x03
line.long 0x00 "OUTDTL3_B0A0,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTL_31_0,Outputting low value data" "0x00000000=0: Valid data,0x00000001=1: Invalid data"
group.long 0x1CC++0x03
line.long 0x00 "BOTHEDGE3_B0A0,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers"
abitfld.long 0x00 0.--31. "BOTHEDGE_31_0,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected" "0x00000000=0: One edge,0x00000001=1: Both edges"
group.long 0x1D0++0x03
line.long 0x00 "INEN3_B0A0,Create registers that can control IE in GPIO"
hexmask.long 0x00 0.--31. 1. "INEN_31_0,"
group.long 0x200++0x03
line.long 0x00 "PMMR3_B0A1,PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers"
hexmask.long 0x00 0.--31. 1. "PMMR_31_0,Multiplexed Pin Setting Mask Writing a value to any register from among the GPSR IPSR DRVCTRL TDSEL POC PUEN PUD MODSEL DMPR PSER PSSR PINV PIS registers is enabled by writing the inverse of the value to this register"
group.long 0x204++0x03
line.long 0x00 "PMMER3_B0A1,PMMERn / PMMERSYS performs enables / disables control of the PMMR"
abitfld.long 0x00 0.--31. "PMMER_31_0,Multiplexed Pin Setting Mask Enable" "0x00000000=0: PMMR function is disabled,0x00000001=1: PMMR function is enabled"
group.long 0x220++0x03
line.long 0x00 "DM0PR3_B0A1,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM0PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x224++0x03
line.long 0x00 "DM1PR3_B0A1,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM1PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x228++0x03
line.long 0x00 "DM2PR3_B0A1,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM2PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x22C++0x03
line.long 0x00 "DM3PR3_B0A1,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM3PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x240++0x03
line.long 0x00 "GPSR3_B0A1,GPSRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "GPSR_31_0,"
group.long 0x280++0x03
line.long 0x00 "DRV0CTRL3_B0A1,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV0CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x284++0x03
line.long 0x00 "DRV1CTRL3_B0A1,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV1CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x288++0x03
line.long 0x00 "DRV2CTRL3_B0A1,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV2CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x2A0++0x03
line.long 0x00 "POC3_B0A1,Each bit in POCn / POCSYS must be set according to IO voltage level that is supplied to the pin"
abitfld.long 0x00 0.--31. "POC_31_0,- For 1.8V/3.3 V" "0x00000000=0: 2.5V,0x00000001=1: 3.3V"
group.long 0x2C0++0x03
line.long 0x00 "PUEN3_B0A1,PUENn / PUENSYS performs on / off control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUEN_31_0,"
group.long 0x2E0++0x03
line.long 0x00 "PUD3_B0A1,PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUD_31_0,"
group.long 0x360++0x03
line.long 0x00 "PSER3_B0A1,The register (PSERn) to enable / disable PSS Rregister"
hexmask.long 0x00 0.--31. 1. "PSER_31_0,"
group.long 0x364++0x03
line.long 0x00 "PS0SR3_B0A1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS0SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x368++0x03
line.long 0x00 "PS1SR3_B0A1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS1SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x380++0x03
line.long 0x00 "IOINTSEL3_B0A1,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group"
abitfld.long 0x00 0.--31. "IOINTSEL_31_0,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input/output mode,0x00000001=1: Interrupt input mode"
group.long 0x384++0x03
line.long 0x00 "INOUTSEL3_B0A1,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INOUTSEL_31_0,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input mode,0x00000001=1: General output mode"
group.long 0x388++0x03
line.long 0x00 "OUTDT3_B0A1,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDT_31_0,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL" "0x00000000=0: 0 is output,0x00000001=1: 1 is output"
group.long 0x38C++0x03
line.long 0x00 "INDT3_B0A1,INDTn is a register that can read the status of General-Purpose Input / Output Ports"
abitfld.long 0x00 0.--31. "INDT_31_0,Each bit reflects the value received through the corresponding port pin" "0x00000000=0: Input is 0,0x00000001=1: Input is 1"
group.long 0x390++0x03
line.long 0x00 "INTDT3_B0A1,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INTDT_31_0,Each bit indicates the input of an interrupt signal on the corresponding port pin" "0x00000000=0: No interrupt signal has been input,0x00000001=1: Interrupt signal has been input"
group.long 0x394++0x03
line.long 0x00 "INTCLR3_B0A1,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).."
abitfld.long 0x00 0.--31. "INTCLR_31_0,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register" "0x00000000=0: No effect,0x00000001=1: Interrupt display"
group.long 0x398++0x03
line.long 0x00 "INTMSK3_B0A1,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch"
abitfld.long 0x00 0.--31. "INTMSK_31_0,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block" "0x00000000=0: Interrupt is masked,0x00000001=1: Interrupt is not masked"
group.long 0x39C++0x03
line.long 0x00 "MSKCLR3_B0A1,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A"
abitfld.long 0x00 0.--31. "MSKCLR_31_0,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block" "0x00000000=0: No effect,0x00000001=1: Interrupt is not masked"
group.long 0x3A0++0x03
line.long 0x00 "POSNEG3_B0A1,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode general output mode or interrupt input mode"
abitfld.long 0x00 0.--31. "POSNEG_31_0,Selects the polarity (positive or negative logic) of each port pin" "0x00000000=0: Positive logic,0x00000001=1: Negative logic"
group.long 0x3A4++0x03
line.long 0x00 "EDGLEVEL3_B0A1,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "EDGLEVEL_31_0,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected" "0x00000000=0: Level,0x00000001=1: Edge"
group.long 0x3A8++0x03
line.long 0x00 "FILONOFF3_B0A1,FILONOFFn prevents chattering input to the port pins of each GPIO group"
abitfld.long 0x00 0.--31. "FILONOFF_31_0,Enables or disables the chattering prevention function" "0x00000000=0: Chattering prevention function is..,0x00000001=1: Chattering prevention function is.."
group.long 0x3AC++0x03
line.long 0x00 "FILCLKSEL3_B0A1,FILCLKSELn controls the division ratio of clock CP? for prevent chattering input to the port pin GPIO group"
hexmask.long 0x00 0.--31. 1. "FILCLKSEL_31_0,Set the division ratio of filter CLOCK"
group.long 0x3C0++0x03
line.long 0x00 "OUTDTSEL3_B0A1,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDTSEL_31_0,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn" "0x00000000=0: General output register is used to..,0x00000001=1: Output data high register and.."
group.long 0x3C4++0x03
line.long 0x00 "OUTDTH3_B0A1,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTH_31_0,Outputting high value data" "0x00000000=0: Invalid data,0x00000001=1: Valid data"
group.long 0x3C8++0x03
line.long 0x00 "OUTDTL3_B0A1,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTL_31_0,Outputting low value data" "0x00000000=0: Valid data,0x00000001=1: Invalid data"
group.long 0x3CC++0x03
line.long 0x00 "BOTHEDGE3_B0A1,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers"
abitfld.long 0x00 0.--31. "BOTHEDGE_31_0,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected" "0x00000000=0: One edge,0x00000001=1: Both edges"
group.long 0x3D0++0x03
line.long 0x00 "INEN3_B0A1,Create registers that can control IE in GPIO"
hexmask.long 0x00 0.--31. 1. "INEN_31_0,"
group.long 0x400++0x03
line.long 0x00 "PMMR3_B0A2,PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers"
hexmask.long 0x00 0.--31. 1. "PMMR_31_0,Multiplexed Pin Setting Mask Writing a value to any register from among the GPSR IPSR DRVCTRL TDSEL POC PUEN PUD MODSEL DMPR PSER PSSR PINV PIS registers is enabled by writing the inverse of the value to this register"
group.long 0x404++0x03
line.long 0x00 "PMMER3_B0A2,PMMERn / PMMERSYS performs enables / disables control of the PMMR"
abitfld.long 0x00 0.--31. "PMMER_31_0,Multiplexed Pin Setting Mask Enable" "0x00000000=0: PMMR function is disabled,0x00000001=1: PMMR function is enabled"
group.long 0x420++0x03
line.long 0x00 "DM0PR3_B0A2,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM0PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x424++0x03
line.long 0x00 "DM1PR3_B0A2,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM1PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x428++0x03
line.long 0x00 "DM2PR3_B0A2,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM2PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x42C++0x03
line.long 0x00 "DM3PR3_B0A2,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM3PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x440++0x03
line.long 0x00 "GPSR3_B0A2,GPSRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "GPSR_31_0,"
group.long 0x480++0x03
line.long 0x00 "DRV0CTRL3_B0A2,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV0CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x484++0x03
line.long 0x00 "DRV1CTRL3_B0A2,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV1CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x488++0x03
line.long 0x00 "DRV2CTRL3_B0A2,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV2CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x4A0++0x03
line.long 0x00 "POC3_B0A2,Each bit in POCn / POCSYS must be set according to IO voltage level that is supplied to the pin"
abitfld.long 0x00 0.--31. "POC_31_0,- For 1.8V/3.3 V" "0x00000000=0: 2.5V,0x00000001=1: 3.3V"
group.long 0x4C0++0x03
line.long 0x00 "PUEN3_B0A2,PUENn / PUENSYS performs on / off control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUEN_31_0,"
group.long 0x4E0++0x03
line.long 0x00 "PUD3_B0A2,PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUD_31_0,"
group.long 0x560++0x03
line.long 0x00 "PSER3_B0A2,The register (PSERn) to enable / disable PSS Rregister"
hexmask.long 0x00 0.--31. 1. "PSER_31_0,"
group.long 0x564++0x03
line.long 0x00 "PS0SR3_B0A2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS0SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x568++0x03
line.long 0x00 "PS1SR3_B0A2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS1SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x580++0x03
line.long 0x00 "IOINTSEL3_B0A2,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group"
abitfld.long 0x00 0.--31. "IOINTSEL_31_0,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input/output mode,0x00000001=1: Interrupt input mode"
group.long 0x584++0x03
line.long 0x00 "INOUTSEL3_B0A2,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INOUTSEL_31_0,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input mode,0x00000001=1: General output mode"
group.long 0x588++0x03
line.long 0x00 "OUTDT3_B0A2,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDT_31_0,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL" "0x00000000=0: 0 is output,0x00000001=1: 1 is output"
group.long 0x58C++0x03
line.long 0x00 "INDT3_B0A2,INDTn is a register that can read the status of General-Purpose Input / Output Ports"
abitfld.long 0x00 0.--31. "INDT_31_0,Each bit reflects the value received through the corresponding port pin" "0x00000000=0: Input is 0,0x00000001=1: Input is 1"
group.long 0x590++0x03
line.long 0x00 "INTDT3_B0A2,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INTDT_31_0,Each bit indicates the input of an interrupt signal on the corresponding port pin" "0x00000000=0: No interrupt signal has been input,0x00000001=1: Interrupt signal has been input"
group.long 0x594++0x03
line.long 0x00 "INTCLR3_B0A2,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).."
abitfld.long 0x00 0.--31. "INTCLR_31_0,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register" "0x00000000=0: No effect,0x00000001=1: Interrupt display"
group.long 0x598++0x03
line.long 0x00 "INTMSK3_B0A2,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch"
abitfld.long 0x00 0.--31. "INTMSK_31_0,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block" "0x00000000=0: Interrupt is masked,0x00000001=1: Interrupt is not masked"
group.long 0x59C++0x03
line.long 0x00 "MSKCLR3_B0A2,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A"
abitfld.long 0x00 0.--31. "MSKCLR_31_0,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block" "0x00000000=0: No effect,0x00000001=1: Interrupt is not masked"
group.long 0x5A0++0x03
line.long 0x00 "POSNEG3_B0A2,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode general output mode or interrupt input mode"
abitfld.long 0x00 0.--31. "POSNEG_31_0,Selects the polarity (positive or negative logic) of each port pin" "0x00000000=0: Positive logic,0x00000001=1: Negative logic"
group.long 0x5A4++0x03
line.long 0x00 "EDGLEVEL3_B0A2,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "EDGLEVEL_31_0,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected" "0x00000000=0: Level,0x00000001=1: Edge"
group.long 0x5A8++0x03
line.long 0x00 "FILONOFF3_B0A2,FILONOFFn prevents chattering input to the port pins of each GPIO group"
abitfld.long 0x00 0.--31. "FILONOFF_31_0,Enables or disables the chattering prevention function" "0x00000000=0: Chattering prevention function is..,0x00000001=1: Chattering prevention function is.."
group.long 0x5AC++0x03
line.long 0x00 "FILCLKSEL3_B0A2,FILCLKSELn controls the division ratio of clock CP? for prevent chattering input to the port pin GPIO group"
hexmask.long 0x00 0.--31. 1. "FILCLKSEL_31_0,Set the division ratio of filter CLOCK"
group.long 0x5C0++0x03
line.long 0x00 "OUTDTSEL3_B0A2,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDTSEL_31_0,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn" "0x00000000=0: General output register is used to..,0x00000001=1: Output data high register and.."
group.long 0x5C4++0x03
line.long 0x00 "OUTDTH3_B0A2,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTH_31_0,Outputting high value data" "0x00000000=0: Invalid data,0x00000001=1: Valid data"
group.long 0x5C8++0x03
line.long 0x00 "OUTDTL3_B0A2,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTL_31_0,Outputting low value data" "0x00000000=0: Valid data,0x00000001=1: Invalid data"
group.long 0x5CC++0x03
line.long 0x00 "BOTHEDGE3_B0A2,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers"
abitfld.long 0x00 0.--31. "BOTHEDGE_31_0,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected" "0x00000000=0: One edge,0x00000001=1: Both edges"
group.long 0x5D0++0x03
line.long 0x00 "INEN3_B0A2,Create registers that can control IE in GPIO"
hexmask.long 0x00 0.--31. 1. "INEN_31_0,"
group.long 0x2000++0x03
line.long 0x00 "PMMR3_B1A0,PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers"
hexmask.long 0x00 0.--31. 1. "PMMR_31_0,Multiplexed Pin Setting Mask Writing a value to any register from among the GPSR IPSR DRVCTRL TDSEL POC PUEN PUD MODSEL DMPR PSER PSSR PINV PIS registers is enabled by writing the inverse of the value to this register"
group.long 0x2004++0x03
line.long 0x00 "PMMER3_B1A0,PMMERn / PMMERSYS performs enables / disables control of the PMMR"
abitfld.long 0x00 0.--31. "PMMER_31_0,Multiplexed Pin Setting Mask Enable" "0x00000000=0: PMMR function is disabled,0x00000001=1: PMMR function is enabled"
group.long 0x2020++0x03
line.long 0x00 "DM0PR3_B1A0,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM0PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x2024++0x03
line.long 0x00 "DM1PR3_B1A0,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM1PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x2028++0x03
line.long 0x00 "DM2PR3_B1A0,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM2PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x202C++0x03
line.long 0x00 "DM3PR3_B1A0,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM3PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x2040++0x03
line.long 0x00 "GPSR3_B1A0,GPSRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "GPSR_31_0,"
group.long 0x2080++0x03
line.long 0x00 "DRV0CTRL3_B1A0,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV0CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x2084++0x03
line.long 0x00 "DRV1CTRL3_B1A0,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV1CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x2088++0x03
line.long 0x00 "DRV2CTRL3_B1A0,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV2CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x20A0++0x03
line.long 0x00 "POC3_B1A0,Each bit in POCn / POCSYS must be set according to IO voltage level that is supplied to the pin"
abitfld.long 0x00 0.--31. "POC_31_0,- For 1.8V/3.3 V" "0x00000000=0: 2.5V,0x00000001=1: 3.3V"
group.long 0x20C0++0x03
line.long 0x00 "PUEN3_B1A0,PUENn / PUENSYS performs on / off control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUEN_31_0,"
group.long 0x20E0++0x03
line.long 0x00 "PUD3_B1A0,PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUD_31_0,"
group.long 0x2160++0x03
line.long 0x00 "PSER3_B1A0,The register (PSERn) to enable / disable PSS Rregister"
hexmask.long 0x00 0.--31. 1. "PSER_31_0,"
group.long 0x2164++0x03
line.long 0x00 "PS0SR3_B1A0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS0SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x2168++0x03
line.long 0x00 "PS1SR3_B1A0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS1SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x2180++0x03
line.long 0x00 "IOINTSEL3_B1A0,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group"
abitfld.long 0x00 0.--31. "IOINTSEL_31_0,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input/output mode,0x00000001=1: Interrupt input mode"
group.long 0x2184++0x03
line.long 0x00 "INOUTSEL3_B1A0,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INOUTSEL_31_0,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input mode,0x00000001=1: General output mode"
group.long 0x2188++0x03
line.long 0x00 "OUTDT3_B1A0,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDT_31_0,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL" "0x00000000=0: 0 is output,0x00000001=1: 1 is output"
group.long 0x218C++0x03
line.long 0x00 "INDT3_B1A0,INDTn is a register that can read the status of General-Purpose Input / Output Ports"
abitfld.long 0x00 0.--31. "INDT_31_0,Each bit reflects the value received through the corresponding port pin" "0x00000000=0: Input is 0,0x00000001=1: Input is 1"
group.long 0x2190++0x03
line.long 0x00 "INTDT3_B1A0,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INTDT_31_0,Each bit indicates the input of an interrupt signal on the corresponding port pin" "0x00000000=0: No interrupt signal has been input,0x00000001=1: Interrupt signal has been input"
group.long 0x2194++0x03
line.long 0x00 "INTCLR3_B1A0,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).."
abitfld.long 0x00 0.--31. "INTCLR_31_0,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register" "0x00000000=0: No effect,0x00000001=1: Interrupt display"
group.long 0x2198++0x03
line.long 0x00 "INTMSK3_B1A0,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch"
abitfld.long 0x00 0.--31. "INTMSK_31_0,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block" "0x00000000=0: Interrupt is masked,0x00000001=1: Interrupt is not masked"
group.long 0x219C++0x03
line.long 0x00 "MSKCLR3_B1A0,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A"
abitfld.long 0x00 0.--31. "MSKCLR_31_0,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block" "0x00000000=0: No effect,0x00000001=1: Interrupt is not masked"
group.long 0x21A0++0x03
line.long 0x00 "POSNEG3_B1A0,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode general output mode or interrupt input mode"
abitfld.long 0x00 0.--31. "POSNEG_31_0,Selects the polarity (positive or negative logic) of each port pin" "0x00000000=0: Positive logic,0x00000001=1: Negative logic"
group.long 0x21A4++0x03
line.long 0x00 "EDGLEVEL3_B1A0,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "EDGLEVEL_31_0,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected" "0x00000000=0: Level,0x00000001=1: Edge"
group.long 0x21A8++0x03
line.long 0x00 "FILONOFF3_B1A0,FILONOFFn prevents chattering input to the port pins of each GPIO group"
abitfld.long 0x00 0.--31. "FILONOFF_31_0,Enables or disables the chattering prevention function" "0x00000000=0: Chattering prevention function is..,0x00000001=1: Chattering prevention function is.."
group.long 0x21AC++0x03
line.long 0x00 "FILCLKSEL3_B1A0,FILCLKSELn controls the division ratio of clock CP? for prevent chattering input to the port pin GPIO group"
hexmask.long 0x00 0.--31. 1. "FILCLKSEL_31_0,Set the division ratio of filter CLOCK"
group.long 0x21C0++0x03
line.long 0x00 "OUTDTSEL3_B1A0,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDTSEL_31_0,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn" "0x00000000=0: General output register is used to..,0x00000001=1: Output data high register and.."
group.long 0x21C4++0x03
line.long 0x00 "OUTDTH3_B1A0,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTH_31_0,Outputting high value data" "0x00000000=0: Invalid data,0x00000001=1: Valid data"
group.long 0x21C8++0x03
line.long 0x00 "OUTDTL3_B1A0,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTL_31_0,Outputting low value data" "0x00000000=0: Valid data,0x00000001=1: Invalid data"
group.long 0x21CC++0x03
line.long 0x00 "BOTHEDGE3_B1A0,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers"
abitfld.long 0x00 0.--31. "BOTHEDGE_31_0,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected" "0x00000000=0: One edge,0x00000001=1: Both edges"
group.long 0x21D0++0x03
line.long 0x00 "INEN3_B1A0,Create registers that can control IE in GPIO"
hexmask.long 0x00 0.--31. 1. "INEN_31_0,"
group.long 0x2200++0x03
line.long 0x00 "PMMR3_B1A1,PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers"
hexmask.long 0x00 0.--31. 1. "PMMR_31_0,Multiplexed Pin Setting Mask Writing a value to any register from among the GPSR IPSR DRVCTRL TDSEL POC PUEN PUD MODSEL DMPR PSER PSSR PINV PIS registers is enabled by writing the inverse of the value to this register"
group.long 0x2204++0x03
line.long 0x00 "PMMER3_B1A1,PMMERn / PMMERSYS performs enables / disables control of the PMMR"
abitfld.long 0x00 0.--31. "PMMER_31_0,Multiplexed Pin Setting Mask Enable" "0x00000000=0: PMMR function is disabled,0x00000001=1: PMMR function is enabled"
group.long 0x2220++0x03
line.long 0x00 "DM0PR3_B1A1,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM0PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x2224++0x03
line.long 0x00 "DM1PR3_B1A1,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM1PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x2228++0x03
line.long 0x00 "DM2PR3_B1A1,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM2PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x222C++0x03
line.long 0x00 "DM3PR3_B1A1,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM3PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x2240++0x03
line.long 0x00 "GPSR3_B1A1,GPSRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "GPSR_31_0,"
group.long 0x2280++0x03
line.long 0x00 "DRV0CTRL3_B1A1,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV0CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x2284++0x03
line.long 0x00 "DRV1CTRL3_B1A1,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV1CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x2288++0x03
line.long 0x00 "DRV2CTRL3_B1A1,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV2CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x22A0++0x03
line.long 0x00 "POC3_B1A1,Each bit in POCn / POCSYS must be set according to IO voltage level that is supplied to the pin"
abitfld.long 0x00 0.--31. "POC_31_0,- For 1.8V/3.3 V" "0x00000000=0: 2.5V,0x00000001=1: 3.3V"
group.long 0x22C0++0x03
line.long 0x00 "PUEN3_B1A1,PUENn / PUENSYS performs on / off control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUEN_31_0,"
group.long 0x22E0++0x03
line.long 0x00 "PUD3_B1A1,PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUD_31_0,"
group.long 0x2360++0x03
line.long 0x00 "PSER3_B1A1,The register (PSERn) to enable / disable PSS Rregister"
hexmask.long 0x00 0.--31. 1. "PSER_31_0,"
group.long 0x2364++0x03
line.long 0x00 "PS0SR3_B1A1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS0SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x2368++0x03
line.long 0x00 "PS1SR3_B1A1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS1SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x2380++0x03
line.long 0x00 "IOINTSEL3_B1A1,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group"
abitfld.long 0x00 0.--31. "IOINTSEL_31_0,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input/output mode,0x00000001=1: Interrupt input mode"
group.long 0x2384++0x03
line.long 0x00 "INOUTSEL3_B1A1,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INOUTSEL_31_0,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input mode,0x00000001=1: General output mode"
group.long 0x2388++0x03
line.long 0x00 "OUTDT3_B1A1,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDT_31_0,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL" "0x00000000=0: 0 is output,0x00000001=1: 1 is output"
group.long 0x238C++0x03
line.long 0x00 "INDT3_B1A1,INDTn is a register that can read the status of General-Purpose Input / Output Ports"
abitfld.long 0x00 0.--31. "INDT_31_0,Each bit reflects the value received through the corresponding port pin" "0x00000000=0: Input is 0,0x00000001=1: Input is 1"
group.long 0x2390++0x03
line.long 0x00 "INTDT3_B1A1,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INTDT_31_0,Each bit indicates the input of an interrupt signal on the corresponding port pin" "0x00000000=0: No interrupt signal has been input,0x00000001=1: Interrupt signal has been input"
group.long 0x2394++0x03
line.long 0x00 "INTCLR3_B1A1,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).."
abitfld.long 0x00 0.--31. "INTCLR_31_0,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register" "0x00000000=0: No effect,0x00000001=1: Interrupt display"
group.long 0x2398++0x03
line.long 0x00 "INTMSK3_B1A1,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch"
abitfld.long 0x00 0.--31. "INTMSK_31_0,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block" "0x00000000=0: Interrupt is masked,0x00000001=1: Interrupt is not masked"
group.long 0x239C++0x03
line.long 0x00 "MSKCLR3_B1A1,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A"
abitfld.long 0x00 0.--31. "MSKCLR_31_0,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block" "0x00000000=0: No effect,0x00000001=1: Interrupt is not masked"
group.long 0x23A0++0x03
line.long 0x00 "POSNEG3_B1A1,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode general output mode or interrupt input mode"
abitfld.long 0x00 0.--31. "POSNEG_31_0,Selects the polarity (positive or negative logic) of each port pin" "0x00000000=0: Positive logic,0x00000001=1: Negative logic"
group.long 0x23A4++0x03
line.long 0x00 "EDGLEVEL3_B1A1,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "EDGLEVEL_31_0,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected" "0x00000000=0: Level,0x00000001=1: Edge"
group.long 0x23A8++0x03
line.long 0x00 "FILONOFF3_B1A1,FILONOFFn prevents chattering input to the port pins of each GPIO group"
abitfld.long 0x00 0.--31. "FILONOFF_31_0,Enables or disables the chattering prevention function" "0x00000000=0: Chattering prevention function is..,0x00000001=1: Chattering prevention function is.."
group.long 0x23AC++0x03
line.long 0x00 "FILCLKSEL3_B1A1,FILCLKSELn controls the division ratio of clock CP? for prevent chattering input to the port pin GPIO group"
hexmask.long 0x00 0.--31. 1. "FILCLKSEL_31_0,Set the division ratio of filter CLOCK"
group.long 0x23C0++0x03
line.long 0x00 "OUTDTSEL3_B1A1,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDTSEL_31_0,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn" "0x00000000=0: General output register is used to..,0x00000001=1: Output data high register and.."
group.long 0x23C4++0x03
line.long 0x00 "OUTDTH3_B1A1,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTH_31_0,Outputting high value data" "0x00000000=0: Invalid data,0x00000001=1: Valid data"
group.long 0x23C8++0x03
line.long 0x00 "OUTDTL3_B1A1,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTL_31_0,Outputting low value data" "0x00000000=0: Valid data,0x00000001=1: Invalid data"
group.long 0x23CC++0x03
line.long 0x00 "BOTHEDGE3_B1A1,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers"
abitfld.long 0x00 0.--31. "BOTHEDGE_31_0,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected" "0x00000000=0: One edge,0x00000001=1: Both edges"
group.long 0x23D0++0x03
line.long 0x00 "INEN3_B1A1,Create registers that can control IE in GPIO"
hexmask.long 0x00 0.--31. 1. "INEN_31_0,"
group.long 0x2400++0x03
line.long 0x00 "PMMR3_B1A2,PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers"
hexmask.long 0x00 0.--31. 1. "PMMR_31_0,Multiplexed Pin Setting Mask Writing a value to any register from among the GPSR IPSR DRVCTRL TDSEL POC PUEN PUD MODSEL DMPR PSER PSSR PINV PIS registers is enabled by writing the inverse of the value to this register"
group.long 0x2404++0x03
line.long 0x00 "PMMER3_B1A2,PMMERn / PMMERSYS performs enables / disables control of the PMMR"
abitfld.long 0x00 0.--31. "PMMER_31_0,Multiplexed Pin Setting Mask Enable" "0x00000000=0: PMMR function is disabled,0x00000001=1: PMMR function is enabled"
group.long 0x2420++0x03
line.long 0x00 "DM0PR3_B1A2,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM0PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x2424++0x03
line.long 0x00 "DM1PR3_B1A2,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM1PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x2428++0x03
line.long 0x00 "DM2PR3_B1A2,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM2PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x242C++0x03
line.long 0x00 "DM3PR3_B1A2,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM3PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x2440++0x03
line.long 0x00 "GPSR3_B1A2,GPSRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "GPSR_31_0,"
group.long 0x2480++0x03
line.long 0x00 "DRV0CTRL3_B1A2,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV0CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x2484++0x03
line.long 0x00 "DRV1CTRL3_B1A2,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV1CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x2488++0x03
line.long 0x00 "DRV2CTRL3_B1A2,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV2CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x24A0++0x03
line.long 0x00 "POC3_B1A2,Each bit in POCn / POCSYS must be set according to IO voltage level that is supplied to the pin"
abitfld.long 0x00 0.--31. "POC_31_0,- For 1.8V/3.3 V" "0x00000000=0: 2.5V,0x00000001=1: 3.3V"
group.long 0x24C0++0x03
line.long 0x00 "PUEN3_B1A2,PUENn / PUENSYS performs on / off control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUEN_31_0,"
group.long 0x24E0++0x03
line.long 0x00 "PUD3_B1A2,PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUD_31_0,"
group.long 0x2560++0x03
line.long 0x00 "PSER3_B1A2,The register (PSERn) to enable / disable PSS Rregister"
hexmask.long 0x00 0.--31. 1. "PSER_31_0,"
group.long 0x2564++0x03
line.long 0x00 "PS0SR3_B1A2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS0SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x2568++0x03
line.long 0x00 "PS1SR3_B1A2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS1SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x2580++0x03
line.long 0x00 "IOINTSEL3_B1A2,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group"
abitfld.long 0x00 0.--31. "IOINTSEL_31_0,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input/output mode,0x00000001=1: Interrupt input mode"
group.long 0x2584++0x03
line.long 0x00 "INOUTSEL3_B1A2,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INOUTSEL_31_0,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input mode,0x00000001=1: General output mode"
group.long 0x2588++0x03
line.long 0x00 "OUTDT3_B1A2,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDT_31_0,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL" "0x00000000=0: 0 is output,0x00000001=1: 1 is output"
group.long 0x258C++0x03
line.long 0x00 "INDT3_B1A2,INDTn is a register that can read the status of General-Purpose Input / Output Ports"
abitfld.long 0x00 0.--31. "INDT_31_0,Each bit reflects the value received through the corresponding port pin" "0x00000000=0: Input is 0,0x00000001=1: Input is 1"
group.long 0x2590++0x03
line.long 0x00 "INTDT3_B1A2,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INTDT_31_0,Each bit indicates the input of an interrupt signal on the corresponding port pin" "0x00000000=0: No interrupt signal has been input,0x00000001=1: Interrupt signal has been input"
group.long 0x2594++0x03
line.long 0x00 "INTCLR3_B1A2,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).."
abitfld.long 0x00 0.--31. "INTCLR_31_0,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register" "0x00000000=0: No effect,0x00000001=1: Interrupt display"
group.long 0x2598++0x03
line.long 0x00 "INTMSK3_B1A2,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch"
abitfld.long 0x00 0.--31. "INTMSK_31_0,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block" "0x00000000=0: Interrupt is masked,0x00000001=1: Interrupt is not masked"
group.long 0x259C++0x03
line.long 0x00 "MSKCLR3_B1A2,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A"
abitfld.long 0x00 0.--31. "MSKCLR_31_0,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block" "0x00000000=0: No effect,0x00000001=1: Interrupt is not masked"
group.long 0x25A0++0x03
line.long 0x00 "POSNEG3_B1A2,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode general output mode or interrupt input mode"
abitfld.long 0x00 0.--31. "POSNEG_31_0,Selects the polarity (positive or negative logic) of each port pin" "0x00000000=0: Positive logic,0x00000001=1: Negative logic"
group.long 0x25A4++0x03
line.long 0x00 "EDGLEVEL3_B1A2,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "EDGLEVEL_31_0,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected" "0x00000000=0: Level,0x00000001=1: Edge"
group.long 0x25A8++0x03
line.long 0x00 "FILONOFF3_B1A2,FILONOFFn prevents chattering input to the port pins of each GPIO group"
abitfld.long 0x00 0.--31. "FILONOFF_31_0,Enables or disables the chattering prevention function" "0x00000000=0: Chattering prevention function is..,0x00000001=1: Chattering prevention function is.."
group.long 0x25AC++0x03
line.long 0x00 "FILCLKSEL3_B1A2,FILCLKSELn controls the division ratio of clock CP? for prevent chattering input to the port pin GPIO group"
hexmask.long 0x00 0.--31. 1. "FILCLKSEL_31_0,Set the division ratio of filter CLOCK"
group.long 0x25C0++0x03
line.long 0x00 "OUTDTSEL3_B1A2,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDTSEL_31_0,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn" "0x00000000=0: General output register is used to..,0x00000001=1: Output data high register and.."
group.long 0x25C4++0x03
line.long 0x00 "OUTDTH3_B1A2,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTH_31_0,Outputting high value data" "0x00000000=0: Invalid data,0x00000001=1: Valid data"
group.long 0x25C8++0x03
line.long 0x00 "OUTDTL3_B1A2,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTL_31_0,Outputting low value data" "0x00000000=0: Valid data,0x00000001=1: Invalid data"
group.long 0x25CC++0x03
line.long 0x00 "BOTHEDGE3_B1A2,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers"
abitfld.long 0x00 0.--31. "BOTHEDGE_31_0,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected" "0x00000000=0: One edge,0x00000001=1: Both edges"
group.long 0x25D0++0x03
line.long 0x00 "INEN3_B1A2,Create registers that can control IE in GPIO"
hexmask.long 0x00 0.--31. 1. "INEN_31_0,"
group.long 0x4000++0x03
line.long 0x00 "PMMR3_B2A0,PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers"
hexmask.long 0x00 0.--31. 1. "PMMR_31_0,Multiplexed Pin Setting Mask Writing a value to any register from among the GPSR IPSR DRVCTRL TDSEL POC PUEN PUD MODSEL DMPR PSER PSSR PINV PIS registers is enabled by writing the inverse of the value to this register"
group.long 0x4004++0x03
line.long 0x00 "PMMER3_B2A0,PMMERn / PMMERSYS performs enables / disables control of the PMMR"
abitfld.long 0x00 0.--31. "PMMER_31_0,Multiplexed Pin Setting Mask Enable" "0x00000000=0: PMMR function is disabled,0x00000001=1: PMMR function is enabled"
group.long 0x4020++0x03
line.long 0x00 "DM0PR3_B2A0,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM0PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x4024++0x03
line.long 0x00 "DM1PR3_B2A0,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM1PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x4028++0x03
line.long 0x00 "DM2PR3_B2A0,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM2PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x402C++0x03
line.long 0x00 "DM3PR3_B2A0,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM3PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x4040++0x03
line.long 0x00 "GPSR3_B2A0,GPSRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "GPSR_31_0,"
group.long 0x4080++0x03
line.long 0x00 "DRV0CTRL3_B2A0,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV0CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x4084++0x03
line.long 0x00 "DRV1CTRL3_B2A0,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV1CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x4088++0x03
line.long 0x00 "DRV2CTRL3_B2A0,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV2CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x40A0++0x03
line.long 0x00 "POC3_B2A0,Each bit in POCn / POCSYS must be set according to IO voltage level that is supplied to the pin"
abitfld.long 0x00 0.--31. "POC_31_0,- For 1.8V/3.3 V" "0x00000000=0: 2.5V,0x00000001=1: 3.3V"
group.long 0x40C0++0x03
line.long 0x00 "PUEN3_B2A0,PUENn / PUENSYS performs on / off control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUEN_31_0,"
group.long 0x40E0++0x03
line.long 0x00 "PUD3_B2A0,PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUD_31_0,"
group.long 0x4160++0x03
line.long 0x00 "PSER3_B2A0,The register (PSERn) to enable / disable PSS Rregister"
hexmask.long 0x00 0.--31. 1. "PSER_31_0,"
group.long 0x4164++0x03
line.long 0x00 "PS0SR3_B2A0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS0SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x4168++0x03
line.long 0x00 "PS1SR3_B2A0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS1SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x4180++0x03
line.long 0x00 "IOINTSEL3_B2A0,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group"
abitfld.long 0x00 0.--31. "IOINTSEL_31_0,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input/output mode,0x00000001=1: Interrupt input mode"
group.long 0x4184++0x03
line.long 0x00 "INOUTSEL3_B2A0,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INOUTSEL_31_0,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input mode,0x00000001=1: General output mode"
group.long 0x4188++0x03
line.long 0x00 "OUTDT3_B2A0,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDT_31_0,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL" "0x00000000=0: 0 is output,0x00000001=1: 1 is output"
group.long 0x418C++0x03
line.long 0x00 "INDT3_B2A0,INDTn is a register that can read the status of General-Purpose Input / Output Ports"
abitfld.long 0x00 0.--31. "INDT_31_0,Each bit reflects the value received through the corresponding port pin" "0x00000000=0: Input is 0,0x00000001=1: Input is 1"
group.long 0x4190++0x03
line.long 0x00 "INTDT3_B2A0,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INTDT_31_0,Each bit indicates the input of an interrupt signal on the corresponding port pin" "0x00000000=0: No interrupt signal has been input,0x00000001=1: Interrupt signal has been input"
group.long 0x4194++0x03
line.long 0x00 "INTCLR3_B2A0,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).."
abitfld.long 0x00 0.--31. "INTCLR_31_0,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register" "0x00000000=0: No effect,0x00000001=1: Interrupt display"
group.long 0x4198++0x03
line.long 0x00 "INTMSK3_B2A0,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch"
abitfld.long 0x00 0.--31. "INTMSK_31_0,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block" "0x00000000=0: Interrupt is masked,0x00000001=1: Interrupt is not masked"
group.long 0x419C++0x03
line.long 0x00 "MSKCLR3_B2A0,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A"
abitfld.long 0x00 0.--31. "MSKCLR_31_0,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block" "0x00000000=0: No effect,0x00000001=1: Interrupt is not masked"
group.long 0x41A0++0x03
line.long 0x00 "POSNEG3_B2A0,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode general output mode or interrupt input mode"
abitfld.long 0x00 0.--31. "POSNEG_31_0,Selects the polarity (positive or negative logic) of each port pin" "0x00000000=0: Positive logic,0x00000001=1: Negative logic"
group.long 0x41A4++0x03
line.long 0x00 "EDGLEVEL3_B2A0,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "EDGLEVEL_31_0,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected" "0x00000000=0: Level,0x00000001=1: Edge"
group.long 0x41A8++0x03
line.long 0x00 "FILONOFF3_B2A0,FILONOFFn prevents chattering input to the port pins of each GPIO group"
abitfld.long 0x00 0.--31. "FILONOFF_31_0,Enables or disables the chattering prevention function" "0x00000000=0: Chattering prevention function is..,0x00000001=1: Chattering prevention function is.."
group.long 0x41AC++0x03
line.long 0x00 "FILCLKSEL3_B2A0,FILCLKSELn controls the division ratio of clock CP? for prevent chattering input to the port pin GPIO group"
hexmask.long 0x00 0.--31. 1. "FILCLKSEL_31_0,Set the division ratio of filter CLOCK"
group.long 0x41C0++0x03
line.long 0x00 "OUTDTSEL3_B2A0,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDTSEL_31_0,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn" "0x00000000=0: General output register is used to..,0x00000001=1: Output data high register and.."
group.long 0x41C4++0x03
line.long 0x00 "OUTDTH3_B2A0,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTH_31_0,Outputting high value data" "0x00000000=0: Invalid data,0x00000001=1: Valid data"
group.long 0x41C8++0x03
line.long 0x00 "OUTDTL3_B2A0,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTL_31_0,Outputting low value data" "0x00000000=0: Valid data,0x00000001=1: Invalid data"
group.long 0x41CC++0x03
line.long 0x00 "BOTHEDGE3_B2A0,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers"
abitfld.long 0x00 0.--31. "BOTHEDGE_31_0,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected" "0x00000000=0: One edge,0x00000001=1: Both edges"
group.long 0x41D0++0x03
line.long 0x00 "INEN3_B2A0,Create registers that can control IE in GPIO"
hexmask.long 0x00 0.--31. 1. "INEN_31_0,"
group.long 0x4200++0x03
line.long 0x00 "PMMR3_B2A1,PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers"
hexmask.long 0x00 0.--31. 1. "PMMR_31_0,Multiplexed Pin Setting Mask Writing a value to any register from among the GPSR IPSR DRVCTRL TDSEL POC PUEN PUD MODSEL DMPR PSER PSSR PINV PIS registers is enabled by writing the inverse of the value to this register"
group.long 0x4204++0x03
line.long 0x00 "PMMER3_B2A1,PMMERn / PMMERSYS performs enables / disables control of the PMMR"
abitfld.long 0x00 0.--31. "PMMER_31_0,Multiplexed Pin Setting Mask Enable" "0x00000000=0: PMMR function is disabled,0x00000001=1: PMMR function is enabled"
group.long 0x4220++0x03
line.long 0x00 "DM0PR3_B2A1,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM0PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x4224++0x03
line.long 0x00 "DM1PR3_B2A1,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM1PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x4228++0x03
line.long 0x00 "DM2PR3_B2A1,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM2PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x422C++0x03
line.long 0x00 "DM3PR3_B2A1,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM3PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x4240++0x03
line.long 0x00 "GPSR3_B2A1,GPSRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "GPSR_31_0,"
group.long 0x4280++0x03
line.long 0x00 "DRV0CTRL3_B2A1,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV0CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x4284++0x03
line.long 0x00 "DRV1CTRL3_B2A1,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV1CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x4288++0x03
line.long 0x00 "DRV2CTRL3_B2A1,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV2CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x42A0++0x03
line.long 0x00 "POC3_B2A1,Each bit in POCn / POCSYS must be set according to IO voltage level that is supplied to the pin"
abitfld.long 0x00 0.--31. "POC_31_0,- For 1.8V/3.3 V" "0x00000000=0: 2.5V,0x00000001=1: 3.3V"
group.long 0x42C0++0x03
line.long 0x00 "PUEN3_B2A1,PUENn / PUENSYS performs on / off control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUEN_31_0,"
group.long 0x42E0++0x03
line.long 0x00 "PUD3_B2A1,PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUD_31_0,"
group.long 0x4360++0x03
line.long 0x00 "PSER3_B2A1,The register (PSERn) to enable / disable PSS Rregister"
hexmask.long 0x00 0.--31. 1. "PSER_31_0,"
group.long 0x4364++0x03
line.long 0x00 "PS0SR3_B2A1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS0SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x4368++0x03
line.long 0x00 "PS1SR3_B2A1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS1SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x4380++0x03
line.long 0x00 "IOINTSEL3_B2A1,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group"
abitfld.long 0x00 0.--31. "IOINTSEL_31_0,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input/output mode,0x00000001=1: Interrupt input mode"
group.long 0x4384++0x03
line.long 0x00 "INOUTSEL3_B2A1,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INOUTSEL_31_0,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input mode,0x00000001=1: General output mode"
group.long 0x4388++0x03
line.long 0x00 "OUTDT3_B2A1,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDT_31_0,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL" "0x00000000=0: 0 is output,0x00000001=1: 1 is output"
group.long 0x438C++0x03
line.long 0x00 "INDT3_B2A1,INDTn is a register that can read the status of General-Purpose Input / Output Ports"
abitfld.long 0x00 0.--31. "INDT_31_0,Each bit reflects the value received through the corresponding port pin" "0x00000000=0: Input is 0,0x00000001=1: Input is 1"
group.long 0x4390++0x03
line.long 0x00 "INTDT3_B2A1,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INTDT_31_0,Each bit indicates the input of an interrupt signal on the corresponding port pin" "0x00000000=0: No interrupt signal has been input,0x00000001=1: Interrupt signal has been input"
group.long 0x4394++0x03
line.long 0x00 "INTCLR3_B2A1,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).."
abitfld.long 0x00 0.--31. "INTCLR_31_0,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register" "0x00000000=0: No effect,0x00000001=1: Interrupt display"
group.long 0x4398++0x03
line.long 0x00 "INTMSK3_B2A1,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch"
abitfld.long 0x00 0.--31. "INTMSK_31_0,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block" "0x00000000=0: Interrupt is masked,0x00000001=1: Interrupt is not masked"
group.long 0x439C++0x03
line.long 0x00 "MSKCLR3_B2A1,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A"
abitfld.long 0x00 0.--31. "MSKCLR_31_0,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block" "0x00000000=0: No effect,0x00000001=1: Interrupt is not masked"
group.long 0x43A0++0x03
line.long 0x00 "POSNEG3_B2A1,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode general output mode or interrupt input mode"
abitfld.long 0x00 0.--31. "POSNEG_31_0,Selects the polarity (positive or negative logic) of each port pin" "0x00000000=0: Positive logic,0x00000001=1: Negative logic"
group.long 0x43A4++0x03
line.long 0x00 "EDGLEVEL3_B2A1,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "EDGLEVEL_31_0,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected" "0x00000000=0: Level,0x00000001=1: Edge"
group.long 0x43A8++0x03
line.long 0x00 "FILONOFF3_B2A1,FILONOFFn prevents chattering input to the port pins of each GPIO group"
abitfld.long 0x00 0.--31. "FILONOFF_31_0,Enables or disables the chattering prevention function" "0x00000000=0: Chattering prevention function is..,0x00000001=1: Chattering prevention function is.."
group.long 0x43AC++0x03
line.long 0x00 "FILCLKSEL3_B2A1,FILCLKSELn controls the division ratio of clock CP? for prevent chattering input to the port pin GPIO group"
hexmask.long 0x00 0.--31. 1. "FILCLKSEL_31_0,Set the division ratio of filter CLOCK"
group.long 0x43C0++0x03
line.long 0x00 "OUTDTSEL3_B2A1,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDTSEL_31_0,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn" "0x00000000=0: General output register is used to..,0x00000001=1: Output data high register and.."
group.long 0x43C4++0x03
line.long 0x00 "OUTDTH3_B2A1,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTH_31_0,Outputting high value data" "0x00000000=0: Invalid data,0x00000001=1: Valid data"
group.long 0x43C8++0x03
line.long 0x00 "OUTDTL3_B2A1,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTL_31_0,Outputting low value data" "0x00000000=0: Valid data,0x00000001=1: Invalid data"
group.long 0x43CC++0x03
line.long 0x00 "BOTHEDGE3_B2A1,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers"
abitfld.long 0x00 0.--31. "BOTHEDGE_31_0,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected" "0x00000000=0: One edge,0x00000001=1: Both edges"
group.long 0x43D0++0x03
line.long 0x00 "INEN3_B2A1,Create registers that can control IE in GPIO"
hexmask.long 0x00 0.--31. 1. "INEN_31_0,"
group.long 0x4400++0x03
line.long 0x00 "PMMR3_B2A2,PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers"
hexmask.long 0x00 0.--31. 1. "PMMR_31_0,Multiplexed Pin Setting Mask Writing a value to any register from among the GPSR IPSR DRVCTRL TDSEL POC PUEN PUD MODSEL DMPR PSER PSSR PINV PIS registers is enabled by writing the inverse of the value to this register"
group.long 0x4404++0x03
line.long 0x00 "PMMER3_B2A2,PMMERn / PMMERSYS performs enables / disables control of the PMMR"
abitfld.long 0x00 0.--31. "PMMER_31_0,Multiplexed Pin Setting Mask Enable" "0x00000000=0: PMMR function is disabled,0x00000001=1: PMMR function is enabled"
group.long 0x4420++0x03
line.long 0x00 "DM0PR3_B2A2,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM0PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x4424++0x03
line.long 0x00 "DM1PR3_B2A2,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM1PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x4428++0x03
line.long 0x00 "DM2PR3_B2A2,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM2PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x442C++0x03
line.long 0x00 "DM3PR3_B2A2,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM3PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x4440++0x03
line.long 0x00 "GPSR3_B2A2,GPSRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "GPSR_31_0,"
group.long 0x4480++0x03
line.long 0x00 "DRV0CTRL3_B2A2,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV0CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x4484++0x03
line.long 0x00 "DRV1CTRL3_B2A2,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV1CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x4488++0x03
line.long 0x00 "DRV2CTRL3_B2A2,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV2CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x44A0++0x03
line.long 0x00 "POC3_B2A2,Each bit in POCn / POCSYS must be set according to IO voltage level that is supplied to the pin"
abitfld.long 0x00 0.--31. "POC_31_0,- For 1.8V/3.3 V" "0x00000000=0: 2.5V,0x00000001=1: 3.3V"
group.long 0x44C0++0x03
line.long 0x00 "PUEN3_B2A2,PUENn / PUENSYS performs on / off control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUEN_31_0,"
group.long 0x44E0++0x03
line.long 0x00 "PUD3_B2A2,PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUD_31_0,"
group.long 0x4560++0x03
line.long 0x00 "PSER3_B2A2,The register (PSERn) to enable / disable PSS Rregister"
hexmask.long 0x00 0.--31. 1. "PSER_31_0,"
group.long 0x4564++0x03
line.long 0x00 "PS0SR3_B2A2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS0SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x4568++0x03
line.long 0x00 "PS1SR3_B2A2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS1SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x4580++0x03
line.long 0x00 "IOINTSEL3_B2A2,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group"
abitfld.long 0x00 0.--31. "IOINTSEL_31_0,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input/output mode,0x00000001=1: Interrupt input mode"
group.long 0x4584++0x03
line.long 0x00 "INOUTSEL3_B2A2,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INOUTSEL_31_0,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input mode,0x00000001=1: General output mode"
group.long 0x4588++0x03
line.long 0x00 "OUTDT3_B2A2,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDT_31_0,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL" "0x00000000=0: 0 is output,0x00000001=1: 1 is output"
group.long 0x458C++0x03
line.long 0x00 "INDT3_B2A2,INDTn is a register that can read the status of General-Purpose Input / Output Ports"
abitfld.long 0x00 0.--31. "INDT_31_0,Each bit reflects the value received through the corresponding port pin" "0x00000000=0: Input is 0,0x00000001=1: Input is 1"
group.long 0x4590++0x03
line.long 0x00 "INTDT3_B2A2,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INTDT_31_0,Each bit indicates the input of an interrupt signal on the corresponding port pin" "0x00000000=0: No interrupt signal has been input,0x00000001=1: Interrupt signal has been input"
group.long 0x4594++0x03
line.long 0x00 "INTCLR3_B2A2,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).."
abitfld.long 0x00 0.--31. "INTCLR_31_0,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register" "0x00000000=0: No effect,0x00000001=1: Interrupt display"
group.long 0x4598++0x03
line.long 0x00 "INTMSK3_B2A2,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch"
abitfld.long 0x00 0.--31. "INTMSK_31_0,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block" "0x00000000=0: Interrupt is masked,0x00000001=1: Interrupt is not masked"
group.long 0x459C++0x03
line.long 0x00 "MSKCLR3_B2A2,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A"
abitfld.long 0x00 0.--31. "MSKCLR_31_0,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block" "0x00000000=0: No effect,0x00000001=1: Interrupt is not masked"
group.long 0x45A0++0x03
line.long 0x00 "POSNEG3_B2A2,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode general output mode or interrupt input mode"
abitfld.long 0x00 0.--31. "POSNEG_31_0,Selects the polarity (positive or negative logic) of each port pin" "0x00000000=0: Positive logic,0x00000001=1: Negative logic"
group.long 0x45A4++0x03
line.long 0x00 "EDGLEVEL3_B2A2,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "EDGLEVEL_31_0,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected" "0x00000000=0: Level,0x00000001=1: Edge"
group.long 0x45A8++0x03
line.long 0x00 "FILONOFF3_B2A2,FILONOFFn prevents chattering input to the port pins of each GPIO group"
abitfld.long 0x00 0.--31. "FILONOFF_31_0,Enables or disables the chattering prevention function" "0x00000000=0: Chattering prevention function is..,0x00000001=1: Chattering prevention function is.."
group.long 0x45AC++0x03
line.long 0x00 "FILCLKSEL3_B2A2,FILCLKSELn controls the division ratio of clock CP? for prevent chattering input to the port pin GPIO group"
hexmask.long 0x00 0.--31. 1. "FILCLKSEL_31_0,Set the division ratio of filter CLOCK"
group.long 0x45C0++0x03
line.long 0x00 "OUTDTSEL3_B2A2,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDTSEL_31_0,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn" "0x00000000=0: General output register is used to..,0x00000001=1: Output data high register and.."
group.long 0x45C4++0x03
line.long 0x00 "OUTDTH3_B2A2,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTH_31_0,Outputting high value data" "0x00000000=0: Invalid data,0x00000001=1: Valid data"
group.long 0x45C8++0x03
line.long 0x00 "OUTDTL3_B2A2,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTL_31_0,Outputting low value data" "0x00000000=0: Valid data,0x00000001=1: Invalid data"
group.long 0x45CC++0x03
line.long 0x00 "BOTHEDGE3_B2A2,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers"
abitfld.long 0x00 0.--31. "BOTHEDGE_31_0,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected" "0x00000000=0: One edge,0x00000001=1: Both edges"
group.long 0x45D0++0x03
line.long 0x00 "INEN3_B2A2,Create registers that can control IE in GPIO"
hexmask.long 0x00 0.--31. 1. "INEN_31_0,"
group.long 0x6000++0x03
line.long 0x00 "PMMR3_B3A0,PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers"
hexmask.long 0x00 0.--31. 1. "PMMR_31_0,Multiplexed Pin Setting Mask Writing a value to any register from among the GPSR IPSR DRVCTRL TDSEL POC PUEN PUD MODSEL DMPR PSER PSSR PINV PIS registers is enabled by writing the inverse of the value to this register"
group.long 0x6004++0x03
line.long 0x00 "PMMER3_B3A0,PMMERn / PMMERSYS performs enables / disables control of the PMMR"
abitfld.long 0x00 0.--31. "PMMER_31_0,Multiplexed Pin Setting Mask Enable" "0x00000000=0: PMMR function is disabled,0x00000001=1: PMMR function is enabled"
group.long 0x6020++0x03
line.long 0x00 "DM0PR3_B3A0,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM0PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x6024++0x03
line.long 0x00 "DM1PR3_B3A0,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM1PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x6028++0x03
line.long 0x00 "DM2PR3_B3A0,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM2PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x602C++0x03
line.long 0x00 "DM3PR3_B3A0,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM3PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x6040++0x03
line.long 0x00 "GPSR3_B3A0,GPSRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "GPSR_31_0,"
group.long 0x6080++0x03
line.long 0x00 "DRV0CTRL3_B3A0,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV0CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x6084++0x03
line.long 0x00 "DRV1CTRL3_B3A0,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV1CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x6088++0x03
line.long 0x00 "DRV2CTRL3_B3A0,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV2CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x60A0++0x03
line.long 0x00 "POC3_B3A0,Each bit in POCn / POCSYS must be set according to IO voltage level that is supplied to the pin"
abitfld.long 0x00 0.--31. "POC_31_0,- For 1.8V/3.3 V" "0x00000000=0: 2.5V,0x00000001=1: 3.3V"
group.long 0x60C0++0x03
line.long 0x00 "PUEN3_B3A0,PUENn / PUENSYS performs on / off control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUEN_31_0,"
group.long 0x60E0++0x03
line.long 0x00 "PUD3_B3A0,PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUD_31_0,"
group.long 0x6160++0x03
line.long 0x00 "PSER3_B3A0,The register (PSERn) to enable / disable PSS Rregister"
hexmask.long 0x00 0.--31. 1. "PSER_31_0,"
group.long 0x6164++0x03
line.long 0x00 "PS0SR3_B3A0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS0SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x6168++0x03
line.long 0x00 "PS1SR3_B3A0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS1SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x6180++0x03
line.long 0x00 "IOINTSEL3_B3A0,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group"
abitfld.long 0x00 0.--31. "IOINTSEL_31_0,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input/output mode,0x00000001=1: Interrupt input mode"
group.long 0x6184++0x03
line.long 0x00 "INOUTSEL3_B3A0,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INOUTSEL_31_0,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input mode,0x00000001=1: General output mode"
group.long 0x6188++0x03
line.long 0x00 "OUTDT3_B3A0,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDT_31_0,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL" "0x00000000=0: 0 is output,0x00000001=1: 1 is output"
group.long 0x618C++0x03
line.long 0x00 "INDT3_B3A0,INDTn is a register that can read the status of General-Purpose Input / Output Ports"
abitfld.long 0x00 0.--31. "INDT_31_0,Each bit reflects the value received through the corresponding port pin" "0x00000000=0: Input is 0,0x00000001=1: Input is 1"
group.long 0x6190++0x03
line.long 0x00 "INTDT3_B3A0,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INTDT_31_0,Each bit indicates the input of an interrupt signal on the corresponding port pin" "0x00000000=0: No interrupt signal has been input,0x00000001=1: Interrupt signal has been input"
group.long 0x6194++0x03
line.long 0x00 "INTCLR3_B3A0,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).."
abitfld.long 0x00 0.--31. "INTCLR_31_0,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register" "0x00000000=0: No effect,0x00000001=1: Interrupt display"
group.long 0x6198++0x03
line.long 0x00 "INTMSK3_B3A0,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch"
abitfld.long 0x00 0.--31. "INTMSK_31_0,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block" "0x00000000=0: Interrupt is masked,0x00000001=1: Interrupt is not masked"
group.long 0x619C++0x03
line.long 0x00 "MSKCLR3_B3A0,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A"
abitfld.long 0x00 0.--31. "MSKCLR_31_0,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block" "0x00000000=0: No effect,0x00000001=1: Interrupt is not masked"
group.long 0x61A0++0x03
line.long 0x00 "POSNEG3_B3A0,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode general output mode or interrupt input mode"
abitfld.long 0x00 0.--31. "POSNEG_31_0,Selects the polarity (positive or negative logic) of each port pin" "0x00000000=0: Positive logic,0x00000001=1: Negative logic"
group.long 0x61A4++0x03
line.long 0x00 "EDGLEVEL3_B3A0,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "EDGLEVEL_31_0,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected" "0x00000000=0: Level,0x00000001=1: Edge"
group.long 0x61A8++0x03
line.long 0x00 "FILONOFF3_B3A0,FILONOFFn prevents chattering input to the port pins of each GPIO group"
abitfld.long 0x00 0.--31. "FILONOFF_31_0,Enables or disables the chattering prevention function" "0x00000000=0: Chattering prevention function is..,0x00000001=1: Chattering prevention function is.."
group.long 0x61AC++0x03
line.long 0x00 "FILCLKSEL3_B3A0,FILCLKSELn controls the division ratio of clock CP? for prevent chattering input to the port pin GPIO group"
hexmask.long 0x00 0.--31. 1. "FILCLKSEL_31_0,Set the division ratio of filter CLOCK"
group.long 0x61C0++0x03
line.long 0x00 "OUTDTSEL3_B3A0,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDTSEL_31_0,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn" "0x00000000=0: General output register is used to..,0x00000001=1: Output data high register and.."
group.long 0x61C4++0x03
line.long 0x00 "OUTDTH3_B3A0,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTH_31_0,Outputting high value data" "0x00000000=0: Invalid data,0x00000001=1: Valid data"
group.long 0x61C8++0x03
line.long 0x00 "OUTDTL3_B3A0,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTL_31_0,Outputting low value data" "0x00000000=0: Valid data,0x00000001=1: Invalid data"
group.long 0x61CC++0x03
line.long 0x00 "BOTHEDGE3_B3A0,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers"
abitfld.long 0x00 0.--31. "BOTHEDGE_31_0,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected" "0x00000000=0: One edge,0x00000001=1: Both edges"
group.long 0x61D0++0x03
line.long 0x00 "INEN3_B3A0,Create registers that can control IE in GPIO"
hexmask.long 0x00 0.--31. 1. "INEN_31_0,"
group.long 0x6200++0x03
line.long 0x00 "PMMR3_B3A1,PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers"
hexmask.long 0x00 0.--31. 1. "PMMR_31_0,Multiplexed Pin Setting Mask Writing a value to any register from among the GPSR IPSR DRVCTRL TDSEL POC PUEN PUD MODSEL DMPR PSER PSSR PINV PIS registers is enabled by writing the inverse of the value to this register"
group.long 0x6204++0x03
line.long 0x00 "PMMER3_B3A1,PMMERn / PMMERSYS performs enables / disables control of the PMMR"
abitfld.long 0x00 0.--31. "PMMER_31_0,Multiplexed Pin Setting Mask Enable" "0x00000000=0: PMMR function is disabled,0x00000001=1: PMMR function is enabled"
group.long 0x6220++0x03
line.long 0x00 "DM0PR3_B3A1,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM0PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x6224++0x03
line.long 0x00 "DM1PR3_B3A1,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM1PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x6228++0x03
line.long 0x00 "DM2PR3_B3A1,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM2PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x622C++0x03
line.long 0x00 "DM3PR3_B3A1,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM3PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x6240++0x03
line.long 0x00 "GPSR3_B3A1,GPSRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "GPSR_31_0,"
group.long 0x6280++0x03
line.long 0x00 "DRV0CTRL3_B3A1,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV0CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x6284++0x03
line.long 0x00 "DRV1CTRL3_B3A1,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV1CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x6288++0x03
line.long 0x00 "DRV2CTRL3_B3A1,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV2CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x62A0++0x03
line.long 0x00 "POC3_B3A1,Each bit in POCn / POCSYS must be set according to IO voltage level that is supplied to the pin"
abitfld.long 0x00 0.--31. "POC_31_0,- For 1.8V/3.3 V" "0x00000000=0: 2.5V,0x00000001=1: 3.3V"
group.long 0x62C0++0x03
line.long 0x00 "PUEN3_B3A1,PUENn / PUENSYS performs on / off control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUEN_31_0,"
group.long 0x62E0++0x03
line.long 0x00 "PUD3_B3A1,PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUD_31_0,"
group.long 0x6360++0x03
line.long 0x00 "PSER3_B3A1,The register (PSERn) to enable / disable PSS Rregister"
hexmask.long 0x00 0.--31. 1. "PSER_31_0,"
group.long 0x6364++0x03
line.long 0x00 "PS0SR3_B3A1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS0SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x6368++0x03
line.long 0x00 "PS1SR3_B3A1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS1SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x6380++0x03
line.long 0x00 "IOINTSEL3_B3A1,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group"
abitfld.long 0x00 0.--31. "IOINTSEL_31_0,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input/output mode,0x00000001=1: Interrupt input mode"
group.long 0x6384++0x03
line.long 0x00 "INOUTSEL3_B3A1,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INOUTSEL_31_0,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input mode,0x00000001=1: General output mode"
group.long 0x6388++0x03
line.long 0x00 "OUTDT3_B3A1,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDT_31_0,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL" "0x00000000=0: 0 is output,0x00000001=1: 1 is output"
group.long 0x638C++0x03
line.long 0x00 "INDT3_B3A1,INDTn is a register that can read the status of General-Purpose Input / Output Ports"
abitfld.long 0x00 0.--31. "INDT_31_0,Each bit reflects the value received through the corresponding port pin" "0x00000000=0: Input is 0,0x00000001=1: Input is 1"
group.long 0x6390++0x03
line.long 0x00 "INTDT3_B3A1,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INTDT_31_0,Each bit indicates the input of an interrupt signal on the corresponding port pin" "0x00000000=0: No interrupt signal has been input,0x00000001=1: Interrupt signal has been input"
group.long 0x6394++0x03
line.long 0x00 "INTCLR3_B3A1,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).."
abitfld.long 0x00 0.--31. "INTCLR_31_0,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register" "0x00000000=0: No effect,0x00000001=1: Interrupt display"
group.long 0x6398++0x03
line.long 0x00 "INTMSK3_B3A1,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch"
abitfld.long 0x00 0.--31. "INTMSK_31_0,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block" "0x00000000=0: Interrupt is masked,0x00000001=1: Interrupt is not masked"
group.long 0x639C++0x03
line.long 0x00 "MSKCLR3_B3A1,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A"
abitfld.long 0x00 0.--31. "MSKCLR_31_0,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block" "0x00000000=0: No effect,0x00000001=1: Interrupt is not masked"
group.long 0x63A0++0x03
line.long 0x00 "POSNEG3_B3A1,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode general output mode or interrupt input mode"
abitfld.long 0x00 0.--31. "POSNEG_31_0,Selects the polarity (positive or negative logic) of each port pin" "0x00000000=0: Positive logic,0x00000001=1: Negative logic"
group.long 0x63A4++0x03
line.long 0x00 "EDGLEVEL3_B3A1,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "EDGLEVEL_31_0,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected" "0x00000000=0: Level,0x00000001=1: Edge"
group.long 0x63A8++0x03
line.long 0x00 "FILONOFF3_B3A1,FILONOFFn prevents chattering input to the port pins of each GPIO group"
abitfld.long 0x00 0.--31. "FILONOFF_31_0,Enables or disables the chattering prevention function" "0x00000000=0: Chattering prevention function is..,0x00000001=1: Chattering prevention function is.."
group.long 0x63AC++0x03
line.long 0x00 "FILCLKSEL3_B3A1,FILCLKSELn controls the division ratio of clock CP? for prevent chattering input to the port pin GPIO group"
hexmask.long 0x00 0.--31. 1. "FILCLKSEL_31_0,Set the division ratio of filter CLOCK"
group.long 0x63C0++0x03
line.long 0x00 "OUTDTSEL3_B3A1,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDTSEL_31_0,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn" "0x00000000=0: General output register is used to..,0x00000001=1: Output data high register and.."
group.long 0x63C4++0x03
line.long 0x00 "OUTDTH3_B3A1,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTH_31_0,Outputting high value data" "0x00000000=0: Invalid data,0x00000001=1: Valid data"
group.long 0x63C8++0x03
line.long 0x00 "OUTDTL3_B3A1,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTL_31_0,Outputting low value data" "0x00000000=0: Valid data,0x00000001=1: Invalid data"
group.long 0x63CC++0x03
line.long 0x00 "BOTHEDGE3_B3A1,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers"
abitfld.long 0x00 0.--31. "BOTHEDGE_31_0,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected" "0x00000000=0: One edge,0x00000001=1: Both edges"
group.long 0x63D0++0x03
line.long 0x00 "INEN3_B3A1,Create registers that can control IE in GPIO"
hexmask.long 0x00 0.--31. 1. "INEN_31_0,"
group.long 0x6400++0x03
line.long 0x00 "PMMR3_B3A2,PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers"
hexmask.long 0x00 0.--31. 1. "PMMR_31_0,Multiplexed Pin Setting Mask Writing a value to any register from among the GPSR IPSR DRVCTRL TDSEL POC PUEN PUD MODSEL DMPR PSER PSSR PINV PIS registers is enabled by writing the inverse of the value to this register"
group.long 0x6404++0x03
line.long 0x00 "PMMER3_B3A2,PMMERn / PMMERSYS performs enables / disables control of the PMMR"
abitfld.long 0x00 0.--31. "PMMER_31_0,Multiplexed Pin Setting Mask Enable" "0x00000000=0: PMMR function is disabled,0x00000001=1: PMMR function is enabled"
group.long 0x6420++0x03
line.long 0x00 "DM0PR3_B3A2,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM0PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x6424++0x03
line.long 0x00 "DM1PR3_B3A2,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM1PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x6428++0x03
line.long 0x00 "DM2PR3_B3A2,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM2PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x642C++0x03
line.long 0x00 "DM3PR3_B3A2,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM3PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x6440++0x03
line.long 0x00 "GPSR3_B3A2,GPSRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "GPSR_31_0,"
group.long 0x6480++0x03
line.long 0x00 "DRV0CTRL3_B3A2,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV0CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x6484++0x03
line.long 0x00 "DRV1CTRL3_B3A2,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV1CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x6488++0x03
line.long 0x00 "DRV2CTRL3_B3A2,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV2CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x64A0++0x03
line.long 0x00 "POC3_B3A2,Each bit in POCn / POCSYS must be set according to IO voltage level that is supplied to the pin"
abitfld.long 0x00 0.--31. "POC_31_0,- For 1.8V/3.3 V" "0x00000000=0: 2.5V,0x00000001=1: 3.3V"
group.long 0x64C0++0x03
line.long 0x00 "PUEN3_B3A2,PUENn / PUENSYS performs on / off control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUEN_31_0,"
group.long 0x64E0++0x03
line.long 0x00 "PUD3_B3A2,PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUD_31_0,"
group.long 0x6560++0x03
line.long 0x00 "PSER3_B3A2,The register (PSERn) to enable / disable PSS Rregister"
hexmask.long 0x00 0.--31. 1. "PSER_31_0,"
group.long 0x6564++0x03
line.long 0x00 "PS0SR3_B3A2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS0SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x6568++0x03
line.long 0x00 "PS1SR3_B3A2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS1SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x6580++0x03
line.long 0x00 "IOINTSEL3_B3A2,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group"
abitfld.long 0x00 0.--31. "IOINTSEL_31_0,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input/output mode,0x00000001=1: Interrupt input mode"
group.long 0x6584++0x03
line.long 0x00 "INOUTSEL3_B3A2,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INOUTSEL_31_0,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input mode,0x00000001=1: General output mode"
group.long 0x6588++0x03
line.long 0x00 "OUTDT3_B3A2,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDT_31_0,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL" "0x00000000=0: 0 is output,0x00000001=1: 1 is output"
group.long 0x658C++0x03
line.long 0x00 "INDT3_B3A2,INDTn is a register that can read the status of General-Purpose Input / Output Ports"
abitfld.long 0x00 0.--31. "INDT_31_0,Each bit reflects the value received through the corresponding port pin" "0x00000000=0: Input is 0,0x00000001=1: Input is 1"
group.long 0x6590++0x03
line.long 0x00 "INTDT3_B3A2,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INTDT_31_0,Each bit indicates the input of an interrupt signal on the corresponding port pin" "0x00000000=0: No interrupt signal has been input,0x00000001=1: Interrupt signal has been input"
group.long 0x6594++0x03
line.long 0x00 "INTCLR3_B3A2,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).."
abitfld.long 0x00 0.--31. "INTCLR_31_0,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register" "0x00000000=0: No effect,0x00000001=1: Interrupt display"
group.long 0x6598++0x03
line.long 0x00 "INTMSK3_B3A2,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch"
abitfld.long 0x00 0.--31. "INTMSK_31_0,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block" "0x00000000=0: Interrupt is masked,0x00000001=1: Interrupt is not masked"
group.long 0x659C++0x03
line.long 0x00 "MSKCLR3_B3A2,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A"
abitfld.long 0x00 0.--31. "MSKCLR_31_0,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block" "0x00000000=0: No effect,0x00000001=1: Interrupt is not masked"
group.long 0x65A0++0x03
line.long 0x00 "POSNEG3_B3A2,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode general output mode or interrupt input mode"
abitfld.long 0x00 0.--31. "POSNEG_31_0,Selects the polarity (positive or negative logic) of each port pin" "0x00000000=0: Positive logic,0x00000001=1: Negative logic"
group.long 0x65A4++0x03
line.long 0x00 "EDGLEVEL3_B3A2,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "EDGLEVEL_31_0,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected" "0x00000000=0: Level,0x00000001=1: Edge"
group.long 0x65A8++0x03
line.long 0x00 "FILONOFF3_B3A2,FILONOFFn prevents chattering input to the port pins of each GPIO group"
abitfld.long 0x00 0.--31. "FILONOFF_31_0,Enables or disables the chattering prevention function" "0x00000000=0: Chattering prevention function is..,0x00000001=1: Chattering prevention function is.."
group.long 0x65AC++0x03
line.long 0x00 "FILCLKSEL3_B3A2,FILCLKSELn controls the division ratio of clock CP? for prevent chattering input to the port pin GPIO group"
hexmask.long 0x00 0.--31. 1. "FILCLKSEL_31_0,Set the division ratio of filter CLOCK"
group.long 0x65C0++0x03
line.long 0x00 "OUTDTSEL3_B3A2,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDTSEL_31_0,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn" "0x00000000=0: General output register is used to..,0x00000001=1: Output data high register and.."
group.long 0x65C4++0x03
line.long 0x00 "OUTDTH3_B3A2,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTH_31_0,Outputting high value data" "0x00000000=0: Invalid data,0x00000001=1: Valid data"
group.long 0x65C8++0x03
line.long 0x00 "OUTDTL3_B3A2,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTL_31_0,Outputting low value data" "0x00000000=0: Valid data,0x00000001=1: Invalid data"
group.long 0x65CC++0x03
line.long 0x00 "BOTHEDGE3_B3A2,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers"
abitfld.long 0x00 0.--31. "BOTHEDGE_31_0,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected" "0x00000000=0: One edge,0x00000001=1: Both edges"
group.long 0x65D0++0x03
line.long 0x00 "INEN3_B3A2,Create registers that can control IE in GPIO"
hexmask.long 0x00 0.--31. 1. "INEN_31_0,"
tree.end
tree "PFC_GPIO_FOR_GP4"
base ad:0xFFD90000
group.long 0x00++0x03
line.long 0x00 "PMMR4_A0,PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers"
hexmask.long 0x00 0.--31. 1. "PMMR_31_0,Multiplexed Pin Setting Mask Writing a value to any register from among the GPSR IPSR DRVCTRL TDSEL POC PUEN PUD MODSEL DMPR PSER PSSR PINV PIS registers is enabled by writing the inverse of the value to this register"
group.long 0x04++0x03
line.long 0x00 "PMMER4_A0,PMMERn / PMMERSYS performs enables / disables control of the PMMR"
abitfld.long 0x00 0.--31. "PMMER_31_0,Multiplexed Pin Setting Mask Enable" "0x00000000=0: PMMR function is disabled,0x00000001=1: PMMR function is enabled"
group.long 0x24++0x03
line.long 0x00 "DM1PR4_A0,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM1PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x28++0x03
line.long 0x00 "DM2PR4_A0,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM2PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x40++0x03
line.long 0x00 "GPSR4_A0,GPSRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "GPSR_31_0,"
group.long 0x60++0x03
line.long 0x00 "IP0SR4_A0,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP0SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x64++0x03
line.long 0x00 "IP1SR4_A0,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP1SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x68++0x03
line.long 0x00 "IP2SR4_A0,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP2SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x6C++0x03
line.long 0x00 "IP3SR4_A0,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP3SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x80++0x03
line.long 0x00 "DRV0CTRL4_A0,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV0CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x84++0x03
line.long 0x00 "DRV1CTRL4_A0,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV1CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x88++0x03
line.long 0x00 "DRV2CTRL4_A0,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV2CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x8C++0x03
line.long 0x00 "DRV3CTRL4_A0,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV3CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0xC0++0x03
line.long 0x00 "PUEN4_A0,PUENn / PUENSYS performs on / off control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUEN_31_0,"
group.long 0xE0++0x03
line.long 0x00 "PUD4_A0,PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUD_31_0,"
group.long 0x100++0x03
line.long 0x00 "MODSEL4_A0,MODSELn selects the group for multiple LSI pins with multiplexed pin functions"
hexmask.long 0x00 0.--31. 1. "MODSEL_31_0,"
group.long 0x160++0x03
line.long 0x00 "PSER4_A0,The register (PSERn) to enable / disable PSS Rregister"
hexmask.long 0x00 0.--31. 1. "PSER_31_0,"
group.long 0x164++0x03
line.long 0x00 "PS0SR4_A0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS0SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x168++0x03
line.long 0x00 "PS1SR4_A0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS1SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x16C++0x03
line.long 0x00 "PINV4_A0,This register(PINVn) inverts the output value of the port"
hexmask.long 0x00 0.--31. 1. "PINV_31_0,"
group.long 0x170++0x03
line.long 0x00 "PIS4_A0,This register specifies the input buffer characteristics"
hexmask.long 0x00 0.--31. 1. "PIS_31_0,"
group.long 0x180++0x03
line.long 0x00 "IOINTSEL4_A0,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group"
abitfld.long 0x00 0.--31. "IOINTSEL_31_0,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input/output mode,0x00000001=1: Interrupt input mode"
group.long 0x184++0x03
line.long 0x00 "INOUTSEL4_A0,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INOUTSEL_31_0,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input mode,0x00000001=1: General output mode"
group.long 0x188++0x03
line.long 0x00 "OUTDT4_A0,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDT_31_0,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL" "0x00000000=0: 0 is output,0x00000001=1: 1 is output"
group.long 0x18C++0x03
line.long 0x00 "INDT4_A0,INDTn is a register that can read the status of General-Purpose Input / Output Ports"
abitfld.long 0x00 0.--31. "INDT_31_0,Each bit reflects the value received through the corresponding port pin" "0x00000000=0: Input is 0,0x00000001=1: Input is 1"
group.long 0x190++0x03
line.long 0x00 "INTDT4_A0,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INTDT_31_0,Each bit indicates the input of an interrupt signal on the corresponding port pin" "0x00000000=0: No interrupt signal has been input,0x00000001=1: Interrupt signal has been input"
group.long 0x194++0x03
line.long 0x00 "INTCLR4_A0,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).."
abitfld.long 0x00 0.--31. "INTCLR_31_0,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register" "0x00000000=0: No effect,0x00000001=1: Interrupt display"
group.long 0x198++0x03
line.long 0x00 "INTMSK4_A0,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch"
abitfld.long 0x00 0.--31. "INTMSK_31_0,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block" "0x00000000=0: Interrupt is masked,0x00000001=1: Interrupt is not masked"
group.long 0x19C++0x03
line.long 0x00 "MSKCLR4_A0,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A"
abitfld.long 0x00 0.--31. "MSKCLR_31_0,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block" "0x00000000=0: No effect,0x00000001=1: Interrupt is not masked"
group.long 0x1A0++0x03
line.long 0x00 "POSNEG4_A0,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode general output mode or interrupt input mode"
abitfld.long 0x00 0.--31. "POSNEG_31_0,Selects the polarity (positive or negative logic) of each port pin" "0x00000000=0: Positive logic,0x00000001=1: Negative logic"
group.long 0x1A4++0x03
line.long 0x00 "EDGLEVEL4_A0,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "EDGLEVEL_31_0,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected" "0x00000000=0: Level,0x00000001=1: Edge"
group.long 0x1A8++0x03
line.long 0x00 "FILONOFF4_A0,FILONOFFn prevents chattering input to the port pins of each GPIO group"
abitfld.long 0x00 0.--31. "FILONOFF_31_0,Enables or disables the chattering prevention function" "0x00000000=0: Chattering prevention function is..,0x00000001=1: Chattering prevention function is.."
group.long 0x1AC++0x03
line.long 0x00 "FILCLKSEL4_A0,FILCLKSELn controls the division ratio of clock CP? for prevent chattering input to the port pin GPIO group"
hexmask.long 0x00 0.--31. 1. "FILCLKSEL_31_0,Set the division ratio of filter CLOCK"
group.long 0x1C0++0x03
line.long 0x00 "OUTDTSEL4_A0,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDTSEL_31_0,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn" "0x00000000=0: General output register is used to..,0x00000001=1: Output data high register and.."
group.long 0x1C4++0x03
line.long 0x00 "OUTDTH4_A0,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTH_31_0,Outputting high value data" "0x00000000=0: Invalid data,0x00000001=1: Valid data"
group.long 0x1C8++0x03
line.long 0x00 "OUTDTL4_A0,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTL_31_0,Outputting low value data" "0x00000000=0: Valid data,0x00000001=1: Invalid data"
group.long 0x1CC++0x03
line.long 0x00 "BOTHEDGE4_A0,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers"
abitfld.long 0x00 0.--31. "BOTHEDGE_31_0,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected" "0x00000000=0: One edge,0x00000001=1: Both edges"
group.long 0x1D0++0x03
line.long 0x00 "INEN4_A0,Create registers that can control IE in GPIO"
hexmask.long 0x00 0.--31. 1. "INEN_31_0,"
group.long 0x200++0x03
line.long 0x00 "PMMR4_A1,PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers"
hexmask.long 0x00 0.--31. 1. "PMMR_31_0,Multiplexed Pin Setting Mask Writing a value to any register from among the GPSR IPSR DRVCTRL TDSEL POC PUEN PUD MODSEL DMPR PSER PSSR PINV PIS registers is enabled by writing the inverse of the value to this register"
group.long 0x204++0x03
line.long 0x00 "PMMER4_A1,PMMERn / PMMERSYS performs enables / disables control of the PMMR"
abitfld.long 0x00 0.--31. "PMMER_31_0,Multiplexed Pin Setting Mask Enable" "0x00000000=0: PMMR function is disabled,0x00000001=1: PMMR function is enabled"
group.long 0x224++0x03
line.long 0x00 "DM1PR4_A1,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM1PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x228++0x03
line.long 0x00 "DM2PR4_A1,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM2PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x240++0x03
line.long 0x00 "GPSR4_A1,GPSRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "GPSR_31_0,"
group.long 0x260++0x03
line.long 0x00 "IP0SR4_A1,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP0SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x264++0x03
line.long 0x00 "IP1SR4_A1,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP1SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x268++0x03
line.long 0x00 "IP2SR4_A1,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP2SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x26C++0x03
line.long 0x00 "IP3SR4_A1,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP3SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x280++0x03
line.long 0x00 "DRV0CTRL4_A1,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV0CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x284++0x03
line.long 0x00 "DRV1CTRL4_A1,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV1CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x288++0x03
line.long 0x00 "DRV2CTRL4_A1,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV2CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x28C++0x03
line.long 0x00 "DRV3CTRL4_A1,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV3CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x2C0++0x03
line.long 0x00 "PUEN4_A1,PUENn / PUENSYS performs on / off control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUEN_31_0,"
group.long 0x2E0++0x03
line.long 0x00 "PUD4_A1,PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUD_31_0,"
group.long 0x300++0x03
line.long 0x00 "MODSEL4_A1,MODSELn selects the group for multiple LSI pins with multiplexed pin functions"
hexmask.long 0x00 0.--31. 1. "MODSEL_31_0,"
group.long 0x360++0x03
line.long 0x00 "PSER4_A1,The register (PSERn) to enable / disable PSS Rregister"
hexmask.long 0x00 0.--31. 1. "PSER_31_0,"
group.long 0x364++0x03
line.long 0x00 "PS0SR4_A1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS0SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x368++0x03
line.long 0x00 "PS1SR4_A1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS1SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x36C++0x03
line.long 0x00 "PINV4_A1,This register(PINVn) inverts the output value of the port"
hexmask.long 0x00 0.--31. 1. "PINV_31_0,"
group.long 0x370++0x03
line.long 0x00 "PIS4_A1,This register specifies the input buffer characteristics"
hexmask.long 0x00 0.--31. 1. "PIS_31_0,"
group.long 0x380++0x03
line.long 0x00 "IOINTSEL4_A1,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group"
abitfld.long 0x00 0.--31. "IOINTSEL_31_0,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input/output mode,0x00000001=1: Interrupt input mode"
group.long 0x384++0x03
line.long 0x00 "INOUTSEL4_A1,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INOUTSEL_31_0,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input mode,0x00000001=1: General output mode"
group.long 0x388++0x03
line.long 0x00 "OUTDT4_A1,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDT_31_0,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL" "0x00000000=0: 0 is output,0x00000001=1: 1 is output"
group.long 0x38C++0x03
line.long 0x00 "INDT4_A1,INDTn is a register that can read the status of General-Purpose Input / Output Ports"
abitfld.long 0x00 0.--31. "INDT_31_0,Each bit reflects the value received through the corresponding port pin" "0x00000000=0: Input is 0,0x00000001=1: Input is 1"
group.long 0x390++0x03
line.long 0x00 "INTDT4_A1,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INTDT_31_0,Each bit indicates the input of an interrupt signal on the corresponding port pin" "0x00000000=0: No interrupt signal has been input,0x00000001=1: Interrupt signal has been input"
group.long 0x394++0x03
line.long 0x00 "INTCLR4_A1,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).."
abitfld.long 0x00 0.--31. "INTCLR_31_0,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register" "0x00000000=0: No effect,0x00000001=1: Interrupt display"
group.long 0x398++0x03
line.long 0x00 "INTMSK4_A1,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch"
abitfld.long 0x00 0.--31. "INTMSK_31_0,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block" "0x00000000=0: Interrupt is masked,0x00000001=1: Interrupt is not masked"
group.long 0x39C++0x03
line.long 0x00 "MSKCLR4_A1,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A"
abitfld.long 0x00 0.--31. "MSKCLR_31_0,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block" "0x00000000=0: No effect,0x00000001=1: Interrupt is not masked"
group.long 0x3A0++0x03
line.long 0x00 "POSNEG4_A1,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode general output mode or interrupt input mode"
abitfld.long 0x00 0.--31. "POSNEG_31_0,Selects the polarity (positive or negative logic) of each port pin" "0x00000000=0: Positive logic,0x00000001=1: Negative logic"
group.long 0x3A4++0x03
line.long 0x00 "EDGLEVEL4_A1,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "EDGLEVEL_31_0,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected" "0x00000000=0: Level,0x00000001=1: Edge"
group.long 0x3A8++0x03
line.long 0x00 "FILONOFF4_A1,FILONOFFn prevents chattering input to the port pins of each GPIO group"
abitfld.long 0x00 0.--31. "FILONOFF_31_0,Enables or disables the chattering prevention function" "0x00000000=0: Chattering prevention function is..,0x00000001=1: Chattering prevention function is.."
group.long 0x3AC++0x03
line.long 0x00 "FILCLKSEL4_A1,FILCLKSELn controls the division ratio of clock CP? for prevent chattering input to the port pin GPIO group"
hexmask.long 0x00 0.--31. 1. "FILCLKSEL_31_0,Set the division ratio of filter CLOCK"
group.long 0x3C0++0x03
line.long 0x00 "OUTDTSEL4_A1,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDTSEL_31_0,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn" "0x00000000=0: General output register is used to..,0x00000001=1: Output data high register and.."
group.long 0x3C4++0x03
line.long 0x00 "OUTDTH4_A1,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTH_31_0,Outputting high value data" "0x00000000=0: Invalid data,0x00000001=1: Valid data"
group.long 0x3C8++0x03
line.long 0x00 "OUTDTL4_A1,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTL_31_0,Outputting low value data" "0x00000000=0: Valid data,0x00000001=1: Invalid data"
group.long 0x3CC++0x03
line.long 0x00 "BOTHEDGE4_A1,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers"
abitfld.long 0x00 0.--31. "BOTHEDGE_31_0,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected" "0x00000000=0: One edge,0x00000001=1: Both edges"
group.long 0x3D0++0x03
line.long 0x00 "INEN4_A1,Create registers that can control IE in GPIO"
hexmask.long 0x00 0.--31. 1. "INEN_31_0,"
group.long 0x400++0x03
line.long 0x00 "PMMR4_A2,PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers"
hexmask.long 0x00 0.--31. 1. "PMMR_31_0,Multiplexed Pin Setting Mask Writing a value to any register from among the GPSR IPSR DRVCTRL TDSEL POC PUEN PUD MODSEL DMPR PSER PSSR PINV PIS registers is enabled by writing the inverse of the value to this register"
group.long 0x404++0x03
line.long 0x00 "PMMER4_A2,PMMERn / PMMERSYS performs enables / disables control of the PMMR"
abitfld.long 0x00 0.--31. "PMMER_31_0,Multiplexed Pin Setting Mask Enable" "0x00000000=0: PMMR function is disabled,0x00000001=1: PMMR function is enabled"
group.long 0x424++0x03
line.long 0x00 "DM1PR4_A2,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM1PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x428++0x03
line.long 0x00 "DM2PR4_A2,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM2PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x440++0x03
line.long 0x00 "GPSR4_A2,GPSRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "GPSR_31_0,"
group.long 0x460++0x03
line.long 0x00 "IP0SR4_A2,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP0SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x464++0x03
line.long 0x00 "IP1SR4_A2,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP1SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x468++0x03
line.long 0x00 "IP2SR4_A2,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP2SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x46C++0x03
line.long 0x00 "IP3SR4_A2,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP3SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x480++0x03
line.long 0x00 "DRV0CTRL4_A2,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV0CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x484++0x03
line.long 0x00 "DRV1CTRL4_A2,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV1CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x488++0x03
line.long 0x00 "DRV2CTRL4_A2,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV2CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x48C++0x03
line.long 0x00 "DRV3CTRL4_A2,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV3CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x4C0++0x03
line.long 0x00 "PUEN4_A2,PUENn / PUENSYS performs on / off control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUEN_31_0,"
group.long 0x4E0++0x03
line.long 0x00 "PUD4_A2,PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUD_31_0,"
group.long 0x500++0x03
line.long 0x00 "MODSEL4_A2,MODSELn selects the group for multiple LSI pins with multiplexed pin functions"
hexmask.long 0x00 0.--31. 1. "MODSEL_31_0,"
group.long 0x560++0x03
line.long 0x00 "PSER4_A2,The register (PSERn) to enable / disable PSS Rregister"
hexmask.long 0x00 0.--31. 1. "PSER_31_0,"
group.long 0x564++0x03
line.long 0x00 "PS0SR4_A2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS0SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x568++0x03
line.long 0x00 "PS1SR4_A2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS1SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x56C++0x03
line.long 0x00 "PINV4_A2,This register(PINVn) inverts the output value of the port"
hexmask.long 0x00 0.--31. 1. "PINV_31_0,"
group.long 0x570++0x03
line.long 0x00 "PIS4_A2,This register specifies the input buffer characteristics"
hexmask.long 0x00 0.--31. 1. "PIS_31_0,"
group.long 0x580++0x03
line.long 0x00 "IOINTSEL4_A2,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group"
abitfld.long 0x00 0.--31. "IOINTSEL_31_0,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input/output mode,0x00000001=1: Interrupt input mode"
group.long 0x584++0x03
line.long 0x00 "INOUTSEL4_A2,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INOUTSEL_31_0,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input mode,0x00000001=1: General output mode"
group.long 0x588++0x03
line.long 0x00 "OUTDT4_A2,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDT_31_0,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL" "0x00000000=0: 0 is output,0x00000001=1: 1 is output"
group.long 0x58C++0x03
line.long 0x00 "INDT4_A2,INDTn is a register that can read the status of General-Purpose Input / Output Ports"
abitfld.long 0x00 0.--31. "INDT_31_0,Each bit reflects the value received through the corresponding port pin" "0x00000000=0: Input is 0,0x00000001=1: Input is 1"
group.long 0x590++0x03
line.long 0x00 "INTDT4_A2,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INTDT_31_0,Each bit indicates the input of an interrupt signal on the corresponding port pin" "0x00000000=0: No interrupt signal has been input,0x00000001=1: Interrupt signal has been input"
group.long 0x594++0x03
line.long 0x00 "INTCLR4_A2,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).."
abitfld.long 0x00 0.--31. "INTCLR_31_0,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register" "0x00000000=0: No effect,0x00000001=1: Interrupt display"
group.long 0x598++0x03
line.long 0x00 "INTMSK4_A2,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch"
abitfld.long 0x00 0.--31. "INTMSK_31_0,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block" "0x00000000=0: Interrupt is masked,0x00000001=1: Interrupt is not masked"
group.long 0x59C++0x03
line.long 0x00 "MSKCLR4_A2,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A"
abitfld.long 0x00 0.--31. "MSKCLR_31_0,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block" "0x00000000=0: No effect,0x00000001=1: Interrupt is not masked"
group.long 0x5A0++0x03
line.long 0x00 "POSNEG4_A2,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode general output mode or interrupt input mode"
abitfld.long 0x00 0.--31. "POSNEG_31_0,Selects the polarity (positive or negative logic) of each port pin" "0x00000000=0: Positive logic,0x00000001=1: Negative logic"
group.long 0x5A4++0x03
line.long 0x00 "EDGLEVEL4_A2,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "EDGLEVEL_31_0,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected" "0x00000000=0: Level,0x00000001=1: Edge"
group.long 0x5A8++0x03
line.long 0x00 "FILONOFF4_A2,FILONOFFn prevents chattering input to the port pins of each GPIO group"
abitfld.long 0x00 0.--31. "FILONOFF_31_0,Enables or disables the chattering prevention function" "0x00000000=0: Chattering prevention function is..,0x00000001=1: Chattering prevention function is.."
group.long 0x5AC++0x03
line.long 0x00 "FILCLKSEL4_A2,FILCLKSELn controls the division ratio of clock CP? for prevent chattering input to the port pin GPIO group"
hexmask.long 0x00 0.--31. 1. "FILCLKSEL_31_0,Set the division ratio of filter CLOCK"
group.long 0x5C0++0x03
line.long 0x00 "OUTDTSEL4_A2,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDTSEL_31_0,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn" "0x00000000=0: General output register is used to..,0x00000001=1: Output data high register and.."
group.long 0x5C4++0x03
line.long 0x00 "OUTDTH4_A2,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTH_31_0,Outputting high value data" "0x00000000=0: Invalid data,0x00000001=1: Valid data"
group.long 0x5C8++0x03
line.long 0x00 "OUTDTL4_A2,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTL_31_0,Outputting low value data" "0x00000000=0: Valid data,0x00000001=1: Invalid data"
group.long 0x5CC++0x03
line.long 0x00 "BOTHEDGE4_A2,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers"
abitfld.long 0x00 0.--31. "BOTHEDGE_31_0,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected" "0x00000000=0: One edge,0x00000001=1: Both edges"
group.long 0x5D0++0x03
line.long 0x00 "INEN4_A2,Create registers that can control IE in GPIO"
hexmask.long 0x00 0.--31. 1. "INEN_31_0,"
tree.end
tree "PFC_GPIO_FOR_GP5"
base ad:0xFFD90800
group.long 0x00++0x03
line.long 0x00 "PMMR5_A0,PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers"
hexmask.long 0x00 0.--31. 1. "PMMR_31_0,Multiplexed Pin Setting Mask Writing a value to any register from among the GPSR IPSR DRVCTRL TDSEL POC PUEN PUD MODSEL DMPR PSER PSSR PINV PIS registers is enabled by writing the inverse of the value to this register"
group.long 0x04++0x03
line.long 0x00 "PMMER5_A0,PMMERn / PMMERSYS performs enables / disables control of the PMMR"
abitfld.long 0x00 0.--31. "PMMER_31_0,Multiplexed Pin Setting Mask Enable" "0x00000000=0: PMMR function is disabled,0x00000001=1: PMMR function is enabled"
group.long 0x24++0x03
line.long 0x00 "DM1PR5_A0,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM1PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x28++0x03
line.long 0x00 "DM2PR5_A0,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM2PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x40++0x03
line.long 0x00 "GPSR5_A0,GPSRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "GPSR_31_0,"
group.long 0x60++0x03
line.long 0x00 "IP0SR5_A0,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP0SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x64++0x03
line.long 0x00 "IP1SR5_A0,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP1SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x68++0x03
line.long 0x00 "IP2SR5_A0,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP2SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x80++0x03
line.long 0x00 "DRV0CTRL5_A0,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV0CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x84++0x03
line.long 0x00 "DRV1CTRL5_A0,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV1CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x88++0x03
line.long 0x00 "DRV2CTRL5_A0,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV2CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0xC0++0x03
line.long 0x00 "PUEN5_A0,PUENn / PUENSYS performs on / off control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUEN_31_0,"
group.long 0xE0++0x03
line.long 0x00 "PUD5_A0,PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUD_31_0,"
group.long 0x100++0x03
line.long 0x00 "MODSEL5_A0,MODSELn selects the group for multiple LSI pins with multiplexed pin functions"
hexmask.long 0x00 0.--31. 1. "MODSEL_31_0,"
group.long 0x160++0x03
line.long 0x00 "PSER5_A0,The register (PSERn) to enable / disable PSS Rregister"
hexmask.long 0x00 0.--31. 1. "PSER_31_0,"
group.long 0x164++0x03
line.long 0x00 "PS0SR5_A0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS0SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x168++0x03
line.long 0x00 "PS1SR5_A0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS1SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x16C++0x03
line.long 0x00 "PINV5_A0,This register(PINVn) inverts the output value of the port"
hexmask.long 0x00 0.--31. 1. "PINV_31_0,"
group.long 0x170++0x03
line.long 0x00 "PIS5_A0,This register specifies the input buffer characteristics"
hexmask.long 0x00 0.--31. 1. "PIS_31_0,"
group.long 0x180++0x03
line.long 0x00 "IOINTSEL5_A0,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group"
abitfld.long 0x00 0.--31. "IOINTSEL_31_0,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input/output mode,0x00000001=1: Interrupt input mode"
group.long 0x184++0x03
line.long 0x00 "INOUTSEL5_A0,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INOUTSEL_31_0,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input mode,0x00000001=1: General output mode"
group.long 0x188++0x03
line.long 0x00 "OUTDT5_A0,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDT_31_0,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL" "0x00000000=0: 0 is output,0x00000001=1: 1 is output"
group.long 0x18C++0x03
line.long 0x00 "INDT5_A0,INDTn is a register that can read the status of General-Purpose Input / Output Ports"
abitfld.long 0x00 0.--31. "INDT_31_0,Each bit reflects the value received through the corresponding port pin" "0x00000000=0: Input is 0,0x00000001=1: Input is 1"
group.long 0x190++0x03
line.long 0x00 "INTDT5_A0,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INTDT_31_0,Each bit indicates the input of an interrupt signal on the corresponding port pin" "0x00000000=0: No interrupt signal has been input,0x00000001=1: Interrupt signal has been input"
group.long 0x194++0x03
line.long 0x00 "INTCLR5_A0,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).."
abitfld.long 0x00 0.--31. "INTCLR_31_0,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register" "0x00000000=0: No effect,0x00000001=1: Interrupt display"
group.long 0x198++0x03
line.long 0x00 "INTMSK5_A0,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch"
abitfld.long 0x00 0.--31. "INTMSK_31_0,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block" "0x00000000=0: Interrupt is masked,0x00000001=1: Interrupt is not masked"
group.long 0x19C++0x03
line.long 0x00 "MSKCLR5_A0,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A"
abitfld.long 0x00 0.--31. "MSKCLR_31_0,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block" "0x00000000=0: No effect,0x00000001=1: Interrupt is not masked"
group.long 0x1A0++0x03
line.long 0x00 "POSNEG5_A0,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode general output mode or interrupt input mode"
abitfld.long 0x00 0.--31. "POSNEG_31_0,Selects the polarity (positive or negative logic) of each port pin" "0x00000000=0: Positive logic,0x00000001=1: Negative logic"
group.long 0x1A4++0x03
line.long 0x00 "EDGLEVEL5_A0,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "EDGLEVEL_31_0,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected" "0x00000000=0: Level,0x00000001=1: Edge"
group.long 0x1A8++0x03
line.long 0x00 "FILONOFF5_A0,FILONOFFn prevents chattering input to the port pins of each GPIO group"
abitfld.long 0x00 0.--31. "FILONOFF_31_0,Enables or disables the chattering prevention function" "0x00000000=0: Chattering prevention function is..,0x00000001=1: Chattering prevention function is.."
group.long 0x1AC++0x03
line.long 0x00 "FILCLKSEL5_A0,FILCLKSELn controls the division ratio of clock CP? for prevent chattering input to the port pin GPIO group"
hexmask.long 0x00 0.--31. 1. "FILCLKSEL_31_0,Set the division ratio of filter CLOCK"
group.long 0x1C0++0x03
line.long 0x00 "OUTDTSEL5_A0,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDTSEL_31_0,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn" "0x00000000=0: General output register is used to..,0x00000001=1: Output data high register and.."
group.long 0x1C4++0x03
line.long 0x00 "OUTDTH5_A0,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTH_31_0,Outputting high value data" "0x00000000=0: Invalid data,0x00000001=1: Valid data"
group.long 0x1C8++0x03
line.long 0x00 "OUTDTL5_A0,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTL_31_0,Outputting low value data" "0x00000000=0: Valid data,0x00000001=1: Invalid data"
group.long 0x1CC++0x03
line.long 0x00 "BOTHEDGE5_A0,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers"
abitfld.long 0x00 0.--31. "BOTHEDGE_31_0,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected" "0x00000000=0: One edge,0x00000001=1: Both edges"
group.long 0x1D0++0x03
line.long 0x00 "INEN5_A0,Create registers that can control IE in GPIO"
hexmask.long 0x00 0.--31. 1. "INEN_31_0,"
group.long 0x200++0x03
line.long 0x00 "PMMR5_A1,PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers"
hexmask.long 0x00 0.--31. 1. "PMMR_31_0,Multiplexed Pin Setting Mask Writing a value to any register from among the GPSR IPSR DRVCTRL TDSEL POC PUEN PUD MODSEL DMPR PSER PSSR PINV PIS registers is enabled by writing the inverse of the value to this register"
group.long 0x204++0x03
line.long 0x00 "PMMER5_A1,PMMERn / PMMERSYS performs enables / disables control of the PMMR"
abitfld.long 0x00 0.--31. "PMMER_31_0,Multiplexed Pin Setting Mask Enable" "0x00000000=0: PMMR function is disabled,0x00000001=1: PMMR function is enabled"
group.long 0x224++0x03
line.long 0x00 "DM1PR5_A1,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM1PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x228++0x03
line.long 0x00 "DM2PR5_A1,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM2PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x240++0x03
line.long 0x00 "GPSR5_A1,GPSRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "GPSR_31_0,"
group.long 0x260++0x03
line.long 0x00 "IP0SR5_A1,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP0SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x264++0x03
line.long 0x00 "IP1SR5_A1,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP1SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x268++0x03
line.long 0x00 "IP2SR5_A1,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP2SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x280++0x03
line.long 0x00 "DRV0CTRL5_A1,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV0CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x284++0x03
line.long 0x00 "DRV1CTRL5_A1,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV1CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x288++0x03
line.long 0x00 "DRV2CTRL5_A1,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV2CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x2C0++0x03
line.long 0x00 "PUEN5_A1,PUENn / PUENSYS performs on / off control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUEN_31_0,"
group.long 0x2E0++0x03
line.long 0x00 "PUD5_A1,PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUD_31_0,"
group.long 0x300++0x03
line.long 0x00 "MODSEL5_A1,MODSELn selects the group for multiple LSI pins with multiplexed pin functions"
hexmask.long 0x00 0.--31. 1. "MODSEL_31_0,"
group.long 0x360++0x03
line.long 0x00 "PSER5_A1,The register (PSERn) to enable / disable PSS Rregister"
hexmask.long 0x00 0.--31. 1. "PSER_31_0,"
group.long 0x364++0x03
line.long 0x00 "PS0SR5_A1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS0SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x368++0x03
line.long 0x00 "PS1SR5_A1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS1SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x36C++0x03
line.long 0x00 "PINV5_A1,This register(PINVn) inverts the output value of the port"
hexmask.long 0x00 0.--31. 1. "PINV_31_0,"
group.long 0x370++0x03
line.long 0x00 "PIS5_A1,This register specifies the input buffer characteristics"
hexmask.long 0x00 0.--31. 1. "PIS_31_0,"
group.long 0x380++0x03
line.long 0x00 "IOINTSEL5_A1,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group"
abitfld.long 0x00 0.--31. "IOINTSEL_31_0,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input/output mode,0x00000001=1: Interrupt input mode"
group.long 0x384++0x03
line.long 0x00 "INOUTSEL5_A1,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INOUTSEL_31_0,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input mode,0x00000001=1: General output mode"
group.long 0x388++0x03
line.long 0x00 "OUTDT5_A1,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDT_31_0,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL" "0x00000000=0: 0 is output,0x00000001=1: 1 is output"
group.long 0x38C++0x03
line.long 0x00 "INDT5_A1,INDTn is a register that can read the status of General-Purpose Input / Output Ports"
abitfld.long 0x00 0.--31. "INDT_31_0,Each bit reflects the value received through the corresponding port pin" "0x00000000=0: Input is 0,0x00000001=1: Input is 1"
group.long 0x390++0x03
line.long 0x00 "INTDT5_A1,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INTDT_31_0,Each bit indicates the input of an interrupt signal on the corresponding port pin" "0x00000000=0: No interrupt signal has been input,0x00000001=1: Interrupt signal has been input"
group.long 0x394++0x03
line.long 0x00 "INTCLR5_A1,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).."
abitfld.long 0x00 0.--31. "INTCLR_31_0,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register" "0x00000000=0: No effect,0x00000001=1: Interrupt display"
group.long 0x398++0x03
line.long 0x00 "INTMSK5_A1,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch"
abitfld.long 0x00 0.--31. "INTMSK_31_0,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block" "0x00000000=0: Interrupt is masked,0x00000001=1: Interrupt is not masked"
group.long 0x39C++0x03
line.long 0x00 "MSKCLR5_A1,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A"
abitfld.long 0x00 0.--31. "MSKCLR_31_0,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block" "0x00000000=0: No effect,0x00000001=1: Interrupt is not masked"
group.long 0x3A0++0x03
line.long 0x00 "POSNEG5_A1,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode general output mode or interrupt input mode"
abitfld.long 0x00 0.--31. "POSNEG_31_0,Selects the polarity (positive or negative logic) of each port pin" "0x00000000=0: Positive logic,0x00000001=1: Negative logic"
group.long 0x3A4++0x03
line.long 0x00 "EDGLEVEL5_A1,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "EDGLEVEL_31_0,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected" "0x00000000=0: Level,0x00000001=1: Edge"
group.long 0x3A8++0x03
line.long 0x00 "FILONOFF5_A1,FILONOFFn prevents chattering input to the port pins of each GPIO group"
abitfld.long 0x00 0.--31. "FILONOFF_31_0,Enables or disables the chattering prevention function" "0x00000000=0: Chattering prevention function is..,0x00000001=1: Chattering prevention function is.."
group.long 0x3AC++0x03
line.long 0x00 "FILCLKSEL5_A1,FILCLKSELn controls the division ratio of clock CP? for prevent chattering input to the port pin GPIO group"
hexmask.long 0x00 0.--31. 1. "FILCLKSEL_31_0,Set the division ratio of filter CLOCK"
group.long 0x3C0++0x03
line.long 0x00 "OUTDTSEL5_A1,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDTSEL_31_0,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn" "0x00000000=0: General output register is used to..,0x00000001=1: Output data high register and.."
group.long 0x3C4++0x03
line.long 0x00 "OUTDTH5_A1,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTH_31_0,Outputting high value data" "0x00000000=0: Invalid data,0x00000001=1: Valid data"
group.long 0x3C8++0x03
line.long 0x00 "OUTDTL5_A1,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTL_31_0,Outputting low value data" "0x00000000=0: Valid data,0x00000001=1: Invalid data"
group.long 0x3CC++0x03
line.long 0x00 "BOTHEDGE5_A1,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers"
abitfld.long 0x00 0.--31. "BOTHEDGE_31_0,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected" "0x00000000=0: One edge,0x00000001=1: Both edges"
group.long 0x3D0++0x03
line.long 0x00 "INEN5_A1,Create registers that can control IE in GPIO"
hexmask.long 0x00 0.--31. 1. "INEN_31_0,"
group.long 0x400++0x03
line.long 0x00 "PMMR5_A2,PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers"
hexmask.long 0x00 0.--31. 1. "PMMR_31_0,Multiplexed Pin Setting Mask Writing a value to any register from among the GPSR IPSR DRVCTRL TDSEL POC PUEN PUD MODSEL DMPR PSER PSSR PINV PIS registers is enabled by writing the inverse of the value to this register"
group.long 0x404++0x03
line.long 0x00 "PMMER5_A2,PMMERn / PMMERSYS performs enables / disables control of the PMMR"
abitfld.long 0x00 0.--31. "PMMER_31_0,Multiplexed Pin Setting Mask Enable" "0x00000000=0: PMMR function is disabled,0x00000001=1: PMMR function is enabled"
group.long 0x424++0x03
line.long 0x00 "DM1PR5_A2,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM1PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x428++0x03
line.long 0x00 "DM2PR5_A2,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM2PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x440++0x03
line.long 0x00 "GPSR5_A2,GPSRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "GPSR_31_0,"
group.long 0x460++0x03
line.long 0x00 "IP0SR5_A2,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP0SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x464++0x03
line.long 0x00 "IP1SR5_A2,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP1SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x468++0x03
line.long 0x00 "IP2SR5_A2,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP2SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x480++0x03
line.long 0x00 "DRV0CTRL5_A2,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV0CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x484++0x03
line.long 0x00 "DRV1CTRL5_A2,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV1CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x488++0x03
line.long 0x00 "DRV2CTRL5_A2,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV2CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x4C0++0x03
line.long 0x00 "PUEN5_A2,PUENn / PUENSYS performs on / off control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUEN_31_0,"
group.long 0x4E0++0x03
line.long 0x00 "PUD5_A2,PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUD_31_0,"
group.long 0x500++0x03
line.long 0x00 "MODSEL5_A2,MODSELn selects the group for multiple LSI pins with multiplexed pin functions"
hexmask.long 0x00 0.--31. 1. "MODSEL_31_0,"
group.long 0x560++0x03
line.long 0x00 "PSER5_A2,The register (PSERn) to enable / disable PSS Rregister"
hexmask.long 0x00 0.--31. 1. "PSER_31_0,"
group.long 0x564++0x03
line.long 0x00 "PS0SR5_A2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS0SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x568++0x03
line.long 0x00 "PS1SR5_A2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS1SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x56C++0x03
line.long 0x00 "PINV5_A2,This register(PINVn) inverts the output value of the port"
hexmask.long 0x00 0.--31. 1. "PINV_31_0,"
group.long 0x570++0x03
line.long 0x00 "PIS5_A2,This register specifies the input buffer characteristics"
hexmask.long 0x00 0.--31. 1. "PIS_31_0,"
group.long 0x580++0x03
line.long 0x00 "IOINTSEL5_A2,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group"
abitfld.long 0x00 0.--31. "IOINTSEL_31_0,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input/output mode,0x00000001=1: Interrupt input mode"
group.long 0x584++0x03
line.long 0x00 "INOUTSEL5_A2,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INOUTSEL_31_0,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input mode,0x00000001=1: General output mode"
group.long 0x588++0x03
line.long 0x00 "OUTDT5_A2,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDT_31_0,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL" "0x00000000=0: 0 is output,0x00000001=1: 1 is output"
group.long 0x58C++0x03
line.long 0x00 "INDT5_A2,INDTn is a register that can read the status of General-Purpose Input / Output Ports"
abitfld.long 0x00 0.--31. "INDT_31_0,Each bit reflects the value received through the corresponding port pin" "0x00000000=0: Input is 0,0x00000001=1: Input is 1"
group.long 0x590++0x03
line.long 0x00 "INTDT5_A2,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INTDT_31_0,Each bit indicates the input of an interrupt signal on the corresponding port pin" "0x00000000=0: No interrupt signal has been input,0x00000001=1: Interrupt signal has been input"
group.long 0x594++0x03
line.long 0x00 "INTCLR5_A2,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).."
abitfld.long 0x00 0.--31. "INTCLR_31_0,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register" "0x00000000=0: No effect,0x00000001=1: Interrupt display"
group.long 0x598++0x03
line.long 0x00 "INTMSK5_A2,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch"
abitfld.long 0x00 0.--31. "INTMSK_31_0,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block" "0x00000000=0: Interrupt is masked,0x00000001=1: Interrupt is not masked"
group.long 0x59C++0x03
line.long 0x00 "MSKCLR5_A2,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A"
abitfld.long 0x00 0.--31. "MSKCLR_31_0,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block" "0x00000000=0: No effect,0x00000001=1: Interrupt is not masked"
group.long 0x5A0++0x03
line.long 0x00 "POSNEG5_A2,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode general output mode or interrupt input mode"
abitfld.long 0x00 0.--31. "POSNEG_31_0,Selects the polarity (positive or negative logic) of each port pin" "0x00000000=0: Positive logic,0x00000001=1: Negative logic"
group.long 0x5A4++0x03
line.long 0x00 "EDGLEVEL5_A2,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "EDGLEVEL_31_0,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected" "0x00000000=0: Level,0x00000001=1: Edge"
group.long 0x5A8++0x03
line.long 0x00 "FILONOFF5_A2,FILONOFFn prevents chattering input to the port pins of each GPIO group"
abitfld.long 0x00 0.--31. "FILONOFF_31_0,Enables or disables the chattering prevention function" "0x00000000=0: Chattering prevention function is..,0x00000001=1: Chattering prevention function is.."
group.long 0x5AC++0x03
line.long 0x00 "FILCLKSEL5_A2,FILCLKSELn controls the division ratio of clock CP? for prevent chattering input to the port pin GPIO group"
hexmask.long 0x00 0.--31. 1. "FILCLKSEL_31_0,Set the division ratio of filter CLOCK"
group.long 0x5C0++0x03
line.long 0x00 "OUTDTSEL5_A2,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDTSEL_31_0,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn" "0x00000000=0: General output register is used to..,0x00000001=1: Output data high register and.."
group.long 0x5C4++0x03
line.long 0x00 "OUTDTH5_A2,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTH_31_0,Outputting high value data" "0x00000000=0: Invalid data,0x00000001=1: Valid data"
group.long 0x5C8++0x03
line.long 0x00 "OUTDTL5_A2,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTL_31_0,Outputting low value data" "0x00000000=0: Valid data,0x00000001=1: Invalid data"
group.long 0x5CC++0x03
line.long 0x00 "BOTHEDGE5_A2,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers"
abitfld.long 0x00 0.--31. "BOTHEDGE_31_0,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected" "0x00000000=0: One edge,0x00000001=1: Both edges"
group.long 0x5D0++0x03
line.long 0x00 "INEN5_A2,Create registers that can control IE in GPIO"
hexmask.long 0x00 0.--31. 1. "INEN_31_0,"
tree.end
tree "PFC_GPIO_FOR_GP6"
base ad:0xFFD91000
group.long 0x00++0x03
line.long 0x00 "PMMR6_A0,PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers"
hexmask.long 0x00 0.--31. 1. "PMMR_31_0,Multiplexed Pin Setting Mask Writing a value to any register from among the GPSR IPSR DRVCTRL TDSEL POC PUEN PUD MODSEL DMPR PSER PSSR PINV PIS registers is enabled by writing the inverse of the value to this register"
group.long 0x04++0x03
line.long 0x00 "PMMER6_A0,PMMERn / PMMERSYS performs enables / disables control of the PMMR"
abitfld.long 0x00 0.--31. "PMMER_31_0,Multiplexed Pin Setting Mask Enable" "0x00000000=0: PMMR function is disabled,0x00000001=1: PMMR function is enabled"
group.long 0x24++0x03
line.long 0x00 "DM1PR6_A0,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM1PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x28++0x03
line.long 0x00 "DM2PR6_A0,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM2PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x40++0x03
line.long 0x00 "GPSR6_A0,GPSRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "GPSR_31_0,"
group.long 0x60++0x03
line.long 0x00 "IP0SR6_A0,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP0SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x64++0x03
line.long 0x00 "IP1SR6_A0,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP1SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x68++0x03
line.long 0x00 "IP2SR6_A0,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP2SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x80++0x03
line.long 0x00 "DRV0CTRL6_A0,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV0CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x84++0x03
line.long 0x00 "DRV1CTRL6_A0,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV1CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x88++0x03
line.long 0x00 "DRV2CTRL6_A0,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV2CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x8C++0x03
line.long 0x00 "DRV3CTRL6_A0,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV3CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0xC0++0x03
line.long 0x00 "PUEN6_A0,PUENn / PUENSYS performs on / off control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUEN_31_0,"
group.long 0xE0++0x03
line.long 0x00 "PUD6_A0,PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUD_31_0,"
group.long 0x100++0x03
line.long 0x00 "MODSEL6_A0,MODSELn selects the group for multiple LSI pins with multiplexed pin functions"
hexmask.long 0x00 0.--31. 1. "MODSEL_31_0,"
group.long 0x160++0x03
line.long 0x00 "PSER6_A0,The register (PSERn) to enable / disable PSS Rregister"
hexmask.long 0x00 0.--31. 1. "PSER_31_0,"
group.long 0x164++0x03
line.long 0x00 "PS0SR6_A0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS0SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x168++0x03
line.long 0x00 "PS1SR6_A0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS1SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x16C++0x03
line.long 0x00 "PINV6_A0,This register(PINVn) inverts the output value of the port"
hexmask.long 0x00 0.--31. 1. "PINV_31_0,"
group.long 0x170++0x03
line.long 0x00 "PIS6_A0,This register specifies the input buffer characteristics"
hexmask.long 0x00 0.--31. 1. "PIS_31_0,"
group.long 0x180++0x03
line.long 0x00 "IOINTSEL6_A0,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group"
abitfld.long 0x00 0.--31. "IOINTSEL_31_0,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input/output mode,0x00000001=1: Interrupt input mode"
group.long 0x184++0x03
line.long 0x00 "INOUTSEL6_A0,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INOUTSEL_31_0,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input mode,0x00000001=1: General output mode"
group.long 0x188++0x03
line.long 0x00 "OUTDT6_A0,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDT_31_0,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL" "0x00000000=0: 0 is output,0x00000001=1: 1 is output"
group.long 0x18C++0x03
line.long 0x00 "INDT6_A0,INDTn is a register that can read the status of General-Purpose Input / Output Ports"
abitfld.long 0x00 0.--31. "INDT_31_0,Each bit reflects the value received through the corresponding port pin" "0x00000000=0: Input is 0,0x00000001=1: Input is 1"
group.long 0x190++0x03
line.long 0x00 "INTDT6_A0,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INTDT_31_0,Each bit indicates the input of an interrupt signal on the corresponding port pin" "0x00000000=0: No interrupt signal has been input,0x00000001=1: Interrupt signal has been input"
group.long 0x194++0x03
line.long 0x00 "INTCLR6_A0,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).."
abitfld.long 0x00 0.--31. "INTCLR_31_0,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register" "0x00000000=0: No effect,0x00000001=1: Interrupt display"
group.long 0x198++0x03
line.long 0x00 "INTMSK6_A0,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch"
abitfld.long 0x00 0.--31. "INTMSK_31_0,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block" "0x00000000=0: Interrupt is masked,0x00000001=1: Interrupt is not masked"
group.long 0x19C++0x03
line.long 0x00 "MSKCLR6_A0,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A"
abitfld.long 0x00 0.--31. "MSKCLR_31_0,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block" "0x00000000=0: No effect,0x00000001=1: Interrupt is not masked"
group.long 0x1A0++0x03
line.long 0x00 "POSNEG6_A0,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode general output mode or interrupt input mode"
abitfld.long 0x00 0.--31. "POSNEG_31_0,Selects the polarity (positive or negative logic) of each port pin" "0x00000000=0: Positive logic,0x00000001=1: Negative logic"
group.long 0x1A4++0x03
line.long 0x00 "EDGLEVEL6_A0,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "EDGLEVEL_31_0,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected" "0x00000000=0: Level,0x00000001=1: Edge"
group.long 0x1A8++0x03
line.long 0x00 "FILONOFF6_A0,FILONOFFn prevents chattering input to the port pins of each GPIO group"
abitfld.long 0x00 0.--31. "FILONOFF_31_0,Enables or disables the chattering prevention function" "0x00000000=0: Chattering prevention function is..,0x00000001=1: Chattering prevention function is.."
group.long 0x1AC++0x03
line.long 0x00 "FILCLKSEL6_A0,FILCLKSELn controls the division ratio of clock CP? for prevent chattering input to the port pin GPIO group"
hexmask.long 0x00 0.--31. 1. "FILCLKSEL_31_0,Set the division ratio of filter CLOCK"
group.long 0x1C0++0x03
line.long 0x00 "OUTDTSEL6_A0,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDTSEL_31_0,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn" "0x00000000=0: General output register is used to..,0x00000001=1: Output data high register and.."
group.long 0x1C4++0x03
line.long 0x00 "OUTDTH6_A0,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTH_31_0,Outputting high value data" "0x00000000=0: Invalid data,0x00000001=1: Valid data"
group.long 0x1C8++0x03
line.long 0x00 "OUTDTL6_A0,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTL_31_0,Outputting low value data" "0x00000000=0: Valid data,0x00000001=1: Invalid data"
group.long 0x1CC++0x03
line.long 0x00 "BOTHEDGE6_A0,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers"
abitfld.long 0x00 0.--31. "BOTHEDGE_31_0,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected" "0x00000000=0: One edge,0x00000001=1: Both edges"
group.long 0x1D0++0x03
line.long 0x00 "INEN6_A0,Create registers that can control IE in GPIO"
hexmask.long 0x00 0.--31. 1. "INEN_31_0,"
group.long 0x200++0x03
line.long 0x00 "PMMR6_A1,PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers"
hexmask.long 0x00 0.--31. 1. "PMMR_31_0,Multiplexed Pin Setting Mask Writing a value to any register from among the GPSR IPSR DRVCTRL TDSEL POC PUEN PUD MODSEL DMPR PSER PSSR PINV PIS registers is enabled by writing the inverse of the value to this register"
group.long 0x204++0x03
line.long 0x00 "PMMER6_A1,PMMERn / PMMERSYS performs enables / disables control of the PMMR"
abitfld.long 0x00 0.--31. "PMMER_31_0,Multiplexed Pin Setting Mask Enable" "0x00000000=0: PMMR function is disabled,0x00000001=1: PMMR function is enabled"
group.long 0x224++0x03
line.long 0x00 "DM1PR6_A1,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM1PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x228++0x03
line.long 0x00 "DM2PR6_A1,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM2PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x240++0x03
line.long 0x00 "GPSR6_A1,GPSRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "GPSR_31_0,"
group.long 0x260++0x03
line.long 0x00 "IP0SR6_A1,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP0SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x264++0x03
line.long 0x00 "IP1SR6_A1,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP1SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x268++0x03
line.long 0x00 "IP2SR6_A1,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP2SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x280++0x03
line.long 0x00 "DRV0CTRL6_A1,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV0CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x284++0x03
line.long 0x00 "DRV1CTRL6_A1,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV1CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x288++0x03
line.long 0x00 "DRV2CTRL6_A1,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV2CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x28C++0x03
line.long 0x00 "DRV3CTRL6_A1,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV3CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x2C0++0x03
line.long 0x00 "PUEN6_A1,PUENn / PUENSYS performs on / off control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUEN_31_0,"
group.long 0x2E0++0x03
line.long 0x00 "PUD6_A1,PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUD_31_0,"
group.long 0x300++0x03
line.long 0x00 "MODSEL6_A1,MODSELn selects the group for multiple LSI pins with multiplexed pin functions"
hexmask.long 0x00 0.--31. 1. "MODSEL_31_0,"
group.long 0x360++0x03
line.long 0x00 "PSER6_A1,The register (PSERn) to enable / disable PSS Rregister"
hexmask.long 0x00 0.--31. 1. "PSER_31_0,"
group.long 0x364++0x03
line.long 0x00 "PS0SR6_A1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS0SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x368++0x03
line.long 0x00 "PS1SR6_A1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS1SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x36C++0x03
line.long 0x00 "PINV6_A1,This register(PINVn) inverts the output value of the port"
hexmask.long 0x00 0.--31. 1. "PINV_31_0,"
group.long 0x370++0x03
line.long 0x00 "PIS6_A1,This register specifies the input buffer characteristics"
hexmask.long 0x00 0.--31. 1. "PIS_31_0,"
group.long 0x380++0x03
line.long 0x00 "IOINTSEL6_A1,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group"
abitfld.long 0x00 0.--31. "IOINTSEL_31_0,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input/output mode,0x00000001=1: Interrupt input mode"
group.long 0x384++0x03
line.long 0x00 "INOUTSEL6_A1,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INOUTSEL_31_0,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input mode,0x00000001=1: General output mode"
group.long 0x388++0x03
line.long 0x00 "OUTDT6_A1,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDT_31_0,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL" "0x00000000=0: 0 is output,0x00000001=1: 1 is output"
group.long 0x38C++0x03
line.long 0x00 "INDT6_A1,INDTn is a register that can read the status of General-Purpose Input / Output Ports"
abitfld.long 0x00 0.--31. "INDT_31_0,Each bit reflects the value received through the corresponding port pin" "0x00000000=0: Input is 0,0x00000001=1: Input is 1"
group.long 0x390++0x03
line.long 0x00 "INTDT6_A1,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INTDT_31_0,Each bit indicates the input of an interrupt signal on the corresponding port pin" "0x00000000=0: No interrupt signal has been input,0x00000001=1: Interrupt signal has been input"
group.long 0x394++0x03
line.long 0x00 "INTCLR6_A1,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).."
abitfld.long 0x00 0.--31. "INTCLR_31_0,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register" "0x00000000=0: No effect,0x00000001=1: Interrupt display"
group.long 0x398++0x03
line.long 0x00 "INTMSK6_A1,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch"
abitfld.long 0x00 0.--31. "INTMSK_31_0,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block" "0x00000000=0: Interrupt is masked,0x00000001=1: Interrupt is not masked"
group.long 0x39C++0x03
line.long 0x00 "MSKCLR6_A1,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A"
abitfld.long 0x00 0.--31. "MSKCLR_31_0,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block" "0x00000000=0: No effect,0x00000001=1: Interrupt is not masked"
group.long 0x3A0++0x03
line.long 0x00 "POSNEG6_A1,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode general output mode or interrupt input mode"
abitfld.long 0x00 0.--31. "POSNEG_31_0,Selects the polarity (positive or negative logic) of each port pin" "0x00000000=0: Positive logic,0x00000001=1: Negative logic"
group.long 0x3A4++0x03
line.long 0x00 "EDGLEVEL6_A1,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "EDGLEVEL_31_0,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected" "0x00000000=0: Level,0x00000001=1: Edge"
group.long 0x3A8++0x03
line.long 0x00 "FILONOFF6_A1,FILONOFFn prevents chattering input to the port pins of each GPIO group"
abitfld.long 0x00 0.--31. "FILONOFF_31_0,Enables or disables the chattering prevention function" "0x00000000=0: Chattering prevention function is..,0x00000001=1: Chattering prevention function is.."
group.long 0x3AC++0x03
line.long 0x00 "FILCLKSEL6_A1,FILCLKSELn controls the division ratio of clock CP? for prevent chattering input to the port pin GPIO group"
hexmask.long 0x00 0.--31. 1. "FILCLKSEL_31_0,Set the division ratio of filter CLOCK"
group.long 0x3C0++0x03
line.long 0x00 "OUTDTSEL6_A1,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDTSEL_31_0,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn" "0x00000000=0: General output register is used to..,0x00000001=1: Output data high register and.."
group.long 0x3C4++0x03
line.long 0x00 "OUTDTH6_A1,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTH_31_0,Outputting high value data" "0x00000000=0: Invalid data,0x00000001=1: Valid data"
group.long 0x3C8++0x03
line.long 0x00 "OUTDTL6_A1,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTL_31_0,Outputting low value data" "0x00000000=0: Valid data,0x00000001=1: Invalid data"
group.long 0x3CC++0x03
line.long 0x00 "BOTHEDGE6_A1,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers"
abitfld.long 0x00 0.--31. "BOTHEDGE_31_0,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected" "0x00000000=0: One edge,0x00000001=1: Both edges"
group.long 0x3D0++0x03
line.long 0x00 "INEN6_A1,Create registers that can control IE in GPIO"
hexmask.long 0x00 0.--31. 1. "INEN_31_0,"
group.long 0x400++0x03
line.long 0x00 "PMMR6_A2,PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers"
hexmask.long 0x00 0.--31. 1. "PMMR_31_0,Multiplexed Pin Setting Mask Writing a value to any register from among the GPSR IPSR DRVCTRL TDSEL POC PUEN PUD MODSEL DMPR PSER PSSR PINV PIS registers is enabled by writing the inverse of the value to this register"
group.long 0x404++0x03
line.long 0x00 "PMMER6_A2,PMMERn / PMMERSYS performs enables / disables control of the PMMR"
abitfld.long 0x00 0.--31. "PMMER_31_0,Multiplexed Pin Setting Mask Enable" "0x00000000=0: PMMR function is disabled,0x00000001=1: PMMR function is enabled"
group.long 0x424++0x03
line.long 0x00 "DM1PR6_A2,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM1PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x428++0x03
line.long 0x00 "DM2PR6_A2,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM2PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x440++0x03
line.long 0x00 "GPSR6_A2,GPSRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "GPSR_31_0,"
group.long 0x460++0x03
line.long 0x00 "IP0SR6_A2,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP0SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x464++0x03
line.long 0x00 "IP1SR6_A2,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP1SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x468++0x03
line.long 0x00 "IP2SR6_A2,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP2SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x480++0x03
line.long 0x00 "DRV0CTRL6_A2,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV0CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x484++0x03
line.long 0x00 "DRV1CTRL6_A2,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV1CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x488++0x03
line.long 0x00 "DRV2CTRL6_A2,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV2CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x48C++0x03
line.long 0x00 "DRV3CTRL6_A2,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV3CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x4C0++0x03
line.long 0x00 "PUEN6_A2,PUENn / PUENSYS performs on / off control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUEN_31_0,"
group.long 0x4E0++0x03
line.long 0x00 "PUD6_A2,PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUD_31_0,"
group.long 0x500++0x03
line.long 0x00 "MODSEL6_A2,MODSELn selects the group for multiple LSI pins with multiplexed pin functions"
hexmask.long 0x00 0.--31. 1. "MODSEL_31_0,"
group.long 0x560++0x03
line.long 0x00 "PSER6_A2,The register (PSERn) to enable / disable PSS Rregister"
hexmask.long 0x00 0.--31. 1. "PSER_31_0,"
group.long 0x564++0x03
line.long 0x00 "PS0SR6_A2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS0SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x568++0x03
line.long 0x00 "PS1SR6_A2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS1SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x56C++0x03
line.long 0x00 "PINV6_A2,This register(PINVn) inverts the output value of the port"
hexmask.long 0x00 0.--31. 1. "PINV_31_0,"
group.long 0x570++0x03
line.long 0x00 "PIS6_A2,This register specifies the input buffer characteristics"
hexmask.long 0x00 0.--31. 1. "PIS_31_0,"
group.long 0x580++0x03
line.long 0x00 "IOINTSEL6_A2,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group"
abitfld.long 0x00 0.--31. "IOINTSEL_31_0,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input/output mode,0x00000001=1: Interrupt input mode"
group.long 0x584++0x03
line.long 0x00 "INOUTSEL6_A2,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INOUTSEL_31_0,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input mode,0x00000001=1: General output mode"
group.long 0x588++0x03
line.long 0x00 "OUTDT6_A2,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDT_31_0,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL" "0x00000000=0: 0 is output,0x00000001=1: 1 is output"
group.long 0x58C++0x03
line.long 0x00 "INDT6_A2,INDTn is a register that can read the status of General-Purpose Input / Output Ports"
abitfld.long 0x00 0.--31. "INDT_31_0,Each bit reflects the value received through the corresponding port pin" "0x00000000=0: Input is 0,0x00000001=1: Input is 1"
group.long 0x590++0x03
line.long 0x00 "INTDT6_A2,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INTDT_31_0,Each bit indicates the input of an interrupt signal on the corresponding port pin" "0x00000000=0: No interrupt signal has been input,0x00000001=1: Interrupt signal has been input"
group.long 0x594++0x03
line.long 0x00 "INTCLR6_A2,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).."
abitfld.long 0x00 0.--31. "INTCLR_31_0,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register" "0x00000000=0: No effect,0x00000001=1: Interrupt display"
group.long 0x598++0x03
line.long 0x00 "INTMSK6_A2,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch"
abitfld.long 0x00 0.--31. "INTMSK_31_0,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block" "0x00000000=0: Interrupt is masked,0x00000001=1: Interrupt is not masked"
group.long 0x59C++0x03
line.long 0x00 "MSKCLR6_A2,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A"
abitfld.long 0x00 0.--31. "MSKCLR_31_0,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block" "0x00000000=0: No effect,0x00000001=1: Interrupt is not masked"
group.long 0x5A0++0x03
line.long 0x00 "POSNEG6_A2,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode general output mode or interrupt input mode"
abitfld.long 0x00 0.--31. "POSNEG_31_0,Selects the polarity (positive or negative logic) of each port pin" "0x00000000=0: Positive logic,0x00000001=1: Negative logic"
group.long 0x5A4++0x03
line.long 0x00 "EDGLEVEL6_A2,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "EDGLEVEL_31_0,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected" "0x00000000=0: Level,0x00000001=1: Edge"
group.long 0x5A8++0x03
line.long 0x00 "FILONOFF6_A2,FILONOFFn prevents chattering input to the port pins of each GPIO group"
abitfld.long 0x00 0.--31. "FILONOFF_31_0,Enables or disables the chattering prevention function" "0x00000000=0: Chattering prevention function is..,0x00000001=1: Chattering prevention function is.."
group.long 0x5AC++0x03
line.long 0x00 "FILCLKSEL6_A2,FILCLKSELn controls the division ratio of clock CP? for prevent chattering input to the port pin GPIO group"
hexmask.long 0x00 0.--31. 1. "FILCLKSEL_31_0,Set the division ratio of filter CLOCK"
group.long 0x5C0++0x03
line.long 0x00 "OUTDTSEL6_A2,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDTSEL_31_0,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn" "0x00000000=0: General output register is used to..,0x00000001=1: Output data high register and.."
group.long 0x5C4++0x03
line.long 0x00 "OUTDTH6_A2,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTH_31_0,Outputting high value data" "0x00000000=0: Invalid data,0x00000001=1: Valid data"
group.long 0x5C8++0x03
line.long 0x00 "OUTDTL6_A2,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTL_31_0,Outputting low value data" "0x00000000=0: Valid data,0x00000001=1: Invalid data"
group.long 0x5CC++0x03
line.long 0x00 "BOTHEDGE6_A2,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers"
abitfld.long 0x00 0.--31. "BOTHEDGE_31_0,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected" "0x00000000=0: One edge,0x00000001=1: Both edges"
group.long 0x5D0++0x03
line.long 0x00 "INEN6_A2,Create registers that can control IE in GPIO"
hexmask.long 0x00 0.--31. 1. "INEN_31_0,"
tree.end
tree "PFC_GPIO_FOR_GP7"
base ad:0xFFD91800
group.long 0x00++0x03
line.long 0x00 "PMMR7_A0,PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers"
hexmask.long 0x00 0.--31. 1. "PMMR_31_0,Multiplexed Pin Setting Mask Writing a value to any register from among the GPSR IPSR DRVCTRL TDSEL POC PUEN PUD MODSEL DMPR PSER PSSR PINV PIS registers is enabled by writing the inverse of the value to this register"
group.long 0x04++0x03
line.long 0x00 "PMMER7_A0,PMMERn / PMMERSYS performs enables / disables control of the PMMR"
abitfld.long 0x00 0.--31. "PMMER_31_0,Multiplexed Pin Setting Mask Enable" "0x00000000=0: PMMR function is disabled,0x00000001=1: PMMR function is enabled"
group.long 0x24++0x03
line.long 0x00 "DM1PR7_A0,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM1PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x28++0x03
line.long 0x00 "DM2PR7_A0,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM2PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x40++0x03
line.long 0x00 "GPSR7_A0,GPSRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "GPSR_31_0,"
group.long 0x60++0x03
line.long 0x00 "IP_0_SR7_A0,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP0SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x64++0x03
line.long 0x00 "IP1SR7_A0,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP1SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x68++0x03
line.long 0x00 "IP2SR7_A0,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP2SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x6C++0x03
line.long 0x00 "IP3SR7_A0,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP3SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x80++0x03
line.long 0x00 "DRV0CTRL7_A0,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV0CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x84++0x03
line.long 0x00 "DRV1CTRL7_A0,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV1CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x88++0x03
line.long 0x00 "DRV2CTRL7_A0,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV2CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x8C++0x03
line.long 0x00 "DRV3CTRL7_A0,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV3CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0xC0++0x03
line.long 0x00 "PUEN7_A0,PUENn / PUENSYS performs on / off control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUEN_31_0,"
group.long 0xE0++0x03
line.long 0x00 "PUD7_A0,PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUD_31_0,"
group.long 0x100++0x03
line.long 0x00 "MODSEL7_A0,MODSELn selects the group for multiple LSI pins with multiplexed pin functions"
hexmask.long 0x00 0.--31. 1. "MODSEL_31_0,"
group.long 0x160++0x03
line.long 0x00 "PSER7_A0,The register (PSERn) to enable / disable PSS Rregister"
hexmask.long 0x00 0.--31. 1. "PSER_31_0,"
group.long 0x164++0x03
line.long 0x00 "PS0SR7_A0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS0SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x168++0x03
line.long 0x00 "PS1SR7_A0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS1SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x16C++0x03
line.long 0x00 "PINV7_A0,This register(PINVn) inverts the output value of the port"
hexmask.long 0x00 0.--31. 1. "PINV_31_0,"
group.long 0x170++0x03
line.long 0x00 "PIS7_A0,This register specifies the input buffer characteristics"
hexmask.long 0x00 0.--31. 1. "PIS_31_0,"
group.long 0x180++0x03
line.long 0x00 "IOINTSEL7_A0,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group"
abitfld.long 0x00 0.--31. "IOINTSEL_31_0,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input/output mode,0x00000001=1: Interrupt input mode"
group.long 0x184++0x03
line.long 0x00 "INOUTSEL7_A0,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INOUTSEL_31_0,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input mode,0x00000001=1: General output mode"
group.long 0x188++0x03
line.long 0x00 "OUTDT7_A0,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDT_31_0,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL" "0x00000000=0: 0 is output,0x00000001=1: 1 is output"
group.long 0x18C++0x03
line.long 0x00 "INDT7_A0,INDTn is a register that can read the status of General-Purpose Input / Output Ports"
abitfld.long 0x00 0.--31. "INDT_31_0,Each bit reflects the value received through the corresponding port pin" "0x00000000=0: Input is 0,0x00000001=1: Input is 1"
group.long 0x190++0x03
line.long 0x00 "INTDT7_A0,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INTDT_31_0,Each bit indicates the input of an interrupt signal on the corresponding port pin" "0x00000000=0: No interrupt signal has been input,0x00000001=1: Interrupt signal has been input"
group.long 0x194++0x03
line.long 0x00 "INTCLR7_A0,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).."
abitfld.long 0x00 0.--31. "INTCLR_31_0,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register" "0x00000000=0: No effect,0x00000001=1: Interrupt display"
group.long 0x198++0x03
line.long 0x00 "INTMSK7_A0,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch"
abitfld.long 0x00 0.--31. "INTMSK_31_0,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block" "0x00000000=0: Interrupt is masked,0x00000001=1: Interrupt is not masked"
group.long 0x19C++0x03
line.long 0x00 "MSKCLR7_A0,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A"
abitfld.long 0x00 0.--31. "MSKCLR_31_0,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block" "0x00000000=0: No effect,0x00000001=1: Interrupt is not masked"
group.long 0x1A0++0x03
line.long 0x00 "POSNEG7_A0,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode general output mode or interrupt input mode"
abitfld.long 0x00 0.--31. "POSNEG_31_0,Selects the polarity (positive or negative logic) of each port pin" "0x00000000=0: Positive logic,0x00000001=1: Negative logic"
group.long 0x1A4++0x03
line.long 0x00 "EDGLEVEL7_A0,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "EDGLEVEL_31_0,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected" "0x00000000=0: Level,0x00000001=1: Edge"
group.long 0x1A8++0x03
line.long 0x00 "FILONOFF7_A0,FILONOFFn prevents chattering input to the port pins of each GPIO group"
abitfld.long 0x00 0.--31. "FILONOFF_31_0,Enables or disables the chattering prevention function" "0x00000000=0: Chattering prevention function is..,0x00000001=1: Chattering prevention function is.."
group.long 0x1AC++0x03
line.long 0x00 "FILCLKSEL7_A0,FILCLKSELn controls the division ratio of clock CP? for prevent chattering input to the port pin GPIO group"
hexmask.long 0x00 0.--31. 1. "FILCLKSEL_31_0,Set the division ratio of filter CLOCK"
group.long 0x1C0++0x03
line.long 0x00 "OUTDTSEL7_A0,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDTSEL_31_0,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn" "0x00000000=0: General output register is used to..,0x00000001=1: Output data high register and.."
group.long 0x1C4++0x03
line.long 0x00 "OUTDTH7_A0,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTH_31_0,Outputting high value data" "0x00000000=0: Invalid data,0x00000001=1: Valid data"
group.long 0x1C8++0x03
line.long 0x00 "OUTDTL7_A0,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTL_31_0,Outputting low value data" "0x00000000=0: Valid data,0x00000001=1: Invalid data"
group.long 0x1CC++0x03
line.long 0x00 "BOTHEDGE7_A0,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers"
abitfld.long 0x00 0.--31. "BOTHEDGE_31_0,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected" "0x00000000=0: One edge,0x00000001=1: Both edges"
group.long 0x1D0++0x03
line.long 0x00 "INEN7_A0,Create registers that can control IE in GPIO"
hexmask.long 0x00 0.--31. 1. "INEN_31_0,"
group.long 0x200++0x03
line.long 0x00 "PMMR7_A1,PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers"
hexmask.long 0x00 0.--31. 1. "PMMR_31_0,Multiplexed Pin Setting Mask Writing a value to any register from among the GPSR IPSR DRVCTRL TDSEL POC PUEN PUD MODSEL DMPR PSER PSSR PINV PIS registers is enabled by writing the inverse of the value to this register"
group.long 0x204++0x03
line.long 0x00 "PMMER7_A1,PMMERn / PMMERSYS performs enables / disables control of the PMMR"
abitfld.long 0x00 0.--31. "PMMER_31_0,Multiplexed Pin Setting Mask Enable" "0x00000000=0: PMMR function is disabled,0x00000001=1: PMMR function is enabled"
group.long 0x224++0x03
line.long 0x00 "DM1PR7_A1,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM1PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x228++0x03
line.long 0x00 "DM2PR7_A1,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM2PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x240++0x03
line.long 0x00 "GPSR7_A1,GPSRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "GPSR_31_0,"
group.long 0x260++0x03
line.long 0x00 "IP_0_SR7_A1,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP0SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x264++0x03
line.long 0x00 "IP1SR7_A1,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP1SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x268++0x03
line.long 0x00 "IP2SR7_A1,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP2SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x26C++0x03
line.long 0x00 "IP3SR7_A1,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP3SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x280++0x03
line.long 0x00 "DRV0CTRL7_A1,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV0CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x284++0x03
line.long 0x00 "DRV1CTRL7_A1,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV1CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x288++0x03
line.long 0x00 "DRV2CTRL7_A1,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV2CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x28C++0x03
line.long 0x00 "DRV3CTRL7_A1,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV3CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x2C0++0x03
line.long 0x00 "PUEN7_A1,PUENn / PUENSYS performs on / off control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUEN_31_0,"
group.long 0x2E0++0x03
line.long 0x00 "PUD7_A1,PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUD_31_0,"
group.long 0x300++0x03
line.long 0x00 "MODSEL7_A1,MODSELn selects the group for multiple LSI pins with multiplexed pin functions"
hexmask.long 0x00 0.--31. 1. "MODSEL_31_0,"
group.long 0x360++0x03
line.long 0x00 "PSER7_A1,The register (PSERn) to enable / disable PSS Rregister"
hexmask.long 0x00 0.--31. 1. "PSER_31_0,"
group.long 0x364++0x03
line.long 0x00 "PS0SR7_A1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS0SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x368++0x03
line.long 0x00 "PS1SR7_A1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS1SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x36C++0x03
line.long 0x00 "PINV7_A1,This register(PINVn) inverts the output value of the port"
hexmask.long 0x00 0.--31. 1. "PINV_31_0,"
group.long 0x370++0x03
line.long 0x00 "PIS7_A1,This register specifies the input buffer characteristics"
hexmask.long 0x00 0.--31. 1. "PIS_31_0,"
group.long 0x380++0x03
line.long 0x00 "IOINTSEL7_A1,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group"
abitfld.long 0x00 0.--31. "IOINTSEL_31_0,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input/output mode,0x00000001=1: Interrupt input mode"
group.long 0x384++0x03
line.long 0x00 "INOUTSEL7_A1,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INOUTSEL_31_0,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input mode,0x00000001=1: General output mode"
group.long 0x388++0x03
line.long 0x00 "OUTDT7_A1,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDT_31_0,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL" "0x00000000=0: 0 is output,0x00000001=1: 1 is output"
group.long 0x38C++0x03
line.long 0x00 "INDT7_A1,INDTn is a register that can read the status of General-Purpose Input / Output Ports"
abitfld.long 0x00 0.--31. "INDT_31_0,Each bit reflects the value received through the corresponding port pin" "0x00000000=0: Input is 0,0x00000001=1: Input is 1"
group.long 0x390++0x03
line.long 0x00 "INTDT7_A1,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INTDT_31_0,Each bit indicates the input of an interrupt signal on the corresponding port pin" "0x00000000=0: No interrupt signal has been input,0x00000001=1: Interrupt signal has been input"
group.long 0x394++0x03
line.long 0x00 "INTCLR7_A1,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).."
abitfld.long 0x00 0.--31. "INTCLR_31_0,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register" "0x00000000=0: No effect,0x00000001=1: Interrupt display"
group.long 0x398++0x03
line.long 0x00 "INTMSK7_A1,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch"
abitfld.long 0x00 0.--31. "INTMSK_31_0,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block" "0x00000000=0: Interrupt is masked,0x00000001=1: Interrupt is not masked"
group.long 0x39C++0x03
line.long 0x00 "MSKCLR7_A1,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A"
abitfld.long 0x00 0.--31. "MSKCLR_31_0,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block" "0x00000000=0: No effect,0x00000001=1: Interrupt is not masked"
group.long 0x3A0++0x03
line.long 0x00 "POSNEG7_A1,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode general output mode or interrupt input mode"
abitfld.long 0x00 0.--31. "POSNEG_31_0,Selects the polarity (positive or negative logic) of each port pin" "0x00000000=0: Positive logic,0x00000001=1: Negative logic"
group.long 0x3A4++0x03
line.long 0x00 "EDGLEVEL7_A1,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "EDGLEVEL_31_0,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected" "0x00000000=0: Level,0x00000001=1: Edge"
group.long 0x3A8++0x03
line.long 0x00 "FILONOFF7_A1,FILONOFFn prevents chattering input to the port pins of each GPIO group"
abitfld.long 0x00 0.--31. "FILONOFF_31_0,Enables or disables the chattering prevention function" "0x00000000=0: Chattering prevention function is..,0x00000001=1: Chattering prevention function is.."
group.long 0x3AC++0x03
line.long 0x00 "FILCLKSEL7_A1,FILCLKSELn controls the division ratio of clock CP? for prevent chattering input to the port pin GPIO group"
hexmask.long 0x00 0.--31. 1. "FILCLKSEL_31_0,Set the division ratio of filter CLOCK"
group.long 0x3C0++0x03
line.long 0x00 "OUTDTSEL7_A1,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDTSEL_31_0,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn" "0x00000000=0: General output register is used to..,0x00000001=1: Output data high register and.."
group.long 0x3C4++0x03
line.long 0x00 "OUTDTH7_A1,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTH_31_0,Outputting high value data" "0x00000000=0: Invalid data,0x00000001=1: Valid data"
group.long 0x3C8++0x03
line.long 0x00 "OUTDTL7_A1,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTL_31_0,Outputting low value data" "0x00000000=0: Valid data,0x00000001=1: Invalid data"
group.long 0x3CC++0x03
line.long 0x00 "BOTHEDGE7_A1,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers"
abitfld.long 0x00 0.--31. "BOTHEDGE_31_0,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected" "0x00000000=0: One edge,0x00000001=1: Both edges"
group.long 0x3D0++0x03
line.long 0x00 "INEN7_A1,Create registers that can control IE in GPIO"
hexmask.long 0x00 0.--31. 1. "INEN_31_0,"
group.long 0x400++0x03
line.long 0x00 "PMMR7_A2,PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers"
hexmask.long 0x00 0.--31. 1. "PMMR_31_0,Multiplexed Pin Setting Mask Writing a value to any register from among the GPSR IPSR DRVCTRL TDSEL POC PUEN PUD MODSEL DMPR PSER PSSR PINV PIS registers is enabled by writing the inverse of the value to this register"
group.long 0x404++0x03
line.long 0x00 "PMMER7_A2,PMMERn / PMMERSYS performs enables / disables control of the PMMR"
abitfld.long 0x00 0.--31. "PMMER_31_0,Multiplexed Pin Setting Mask Enable" "0x00000000=0: PMMR function is disabled,0x00000001=1: PMMR function is enabled"
group.long 0x424++0x03
line.long 0x00 "DM1PR7_A2,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM1PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x428++0x03
line.long 0x00 "DM2PR7_A2,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM2PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x440++0x03
line.long 0x00 "GPSR7_A2,GPSRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "GPSR_31_0,"
group.long 0x460++0x03
line.long 0x00 "IP_0_SR7_A2,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP0SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x464++0x03
line.long 0x00 "IP1SR7_A2,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP1SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x468++0x03
line.long 0x00 "IP2SR7_A2,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP2SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x46C++0x03
line.long 0x00 "IP3SR7_A2,IP*SRn selects the functions of the multiplexed LSI pins"
hexmask.long 0x00 0.--31. 1. "IP3SR_31_0,The functions of the LSI pins are selected according to the table below"
group.long 0x480++0x03
line.long 0x00 "DRV0CTRL7_A2,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV0CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x484++0x03
line.long 0x00 "DRV1CTRL7_A2,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV1CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x488++0x03
line.long 0x00 "DRV2CTRL7_A2,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV2CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x48C++0x03
line.long 0x00 "DRV3CTRL7_A2,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV3CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x4C0++0x03
line.long 0x00 "PUEN7_A2,PUENn / PUENSYS performs on / off control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUEN_31_0,"
group.long 0x4E0++0x03
line.long 0x00 "PUD7_A2,PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUD_31_0,"
group.long 0x500++0x03
line.long 0x00 "MODSEL7_A2,MODSELn selects the group for multiple LSI pins with multiplexed pin functions"
hexmask.long 0x00 0.--31. 1. "MODSEL_31_0,"
group.long 0x560++0x03
line.long 0x00 "PSER7_A2,The register (PSERn) to enable / disable PSS Rregister"
hexmask.long 0x00 0.--31. 1. "PSER_31_0,"
group.long 0x564++0x03
line.long 0x00 "PS0SR7_A2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS0SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x568++0x03
line.long 0x00 "PS1SR7_A2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits"
hexmask.long 0x00 0.--31. 1. "PS1SR_31_0,b'00=initial state b'01=HiZ b'10=Pull-Down b'11=Pull-Up"
group.long 0x56C++0x03
line.long 0x00 "PINV7_A2,This register(PINVn) inverts the output value of the port"
hexmask.long 0x00 0.--31. 1. "PINV_31_0,"
group.long 0x570++0x03
line.long 0x00 "PIS7_A2,This register specifies the input buffer characteristics"
hexmask.long 0x00 0.--31. 1. "PIS_31_0,"
group.long 0x580++0x03
line.long 0x00 "IOINTSEL7_A2,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group"
abitfld.long 0x00 0.--31. "IOINTSEL_31_0,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input/output mode,0x00000001=1: Interrupt input mode"
group.long 0x584++0x03
line.long 0x00 "INOUTSEL7_A2,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INOUTSEL_31_0,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers" "0x00000000=0: General input mode,0x00000001=1: General output mode"
group.long 0x588++0x03
line.long 0x00 "OUTDT7_A2,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDT_31_0,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL" "0x00000000=0: 0 is output,0x00000001=1: 1 is output"
group.long 0x58C++0x03
line.long 0x00 "INDT7_A2,INDTn is a register that can read the status of General-Purpose Input / Output Ports"
abitfld.long 0x00 0.--31. "INDT_31_0,Each bit reflects the value received through the corresponding port pin" "0x00000000=0: Input is 0,0x00000001=1: Input is 1"
group.long 0x590++0x03
line.long 0x00 "INTDT7_A2,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "INTDT_31_0,Each bit indicates the input of an interrupt signal on the corresponding port pin" "0x00000000=0: No interrupt signal has been input,0x00000001=1: Interrupt signal has been input"
group.long 0x594++0x03
line.long 0x00 "INTCLR7_A2,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).."
abitfld.long 0x00 0.--31. "INTCLR_31_0,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register" "0x00000000=0: No effect,0x00000001=1: Interrupt display"
group.long 0x598++0x03
line.long 0x00 "INTMSK7_A2,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch"
abitfld.long 0x00 0.--31. "INTMSK_31_0,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block" "0x00000000=0: Interrupt is masked,0x00000001=1: Interrupt is not masked"
group.long 0x59C++0x03
line.long 0x00 "MSKCLR7_A2,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A"
abitfld.long 0x00 0.--31. "MSKCLR_31_0,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block" "0x00000000=0: No effect,0x00000001=1: Interrupt is not masked"
group.long 0x5A0++0x03
line.long 0x00 "POSNEG7_A2,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode general output mode or interrupt input mode"
abitfld.long 0x00 0.--31. "POSNEG_31_0,Selects the polarity (positive or negative logic) of each port pin" "0x00000000=0: Positive logic,0x00000001=1: Negative logic"
group.long 0x5A4++0x03
line.long 0x00 "EDGLEVEL7_A2,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register"
abitfld.long 0x00 0.--31. "EDGLEVEL_31_0,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected" "0x00000000=0: Level,0x00000001=1: Edge"
group.long 0x5A8++0x03
line.long 0x00 "FILONOFF7_A2,FILONOFFn prevents chattering input to the port pins of each GPIO group"
abitfld.long 0x00 0.--31. "FILONOFF_31_0,Enables or disables the chattering prevention function" "0x00000000=0: Chattering prevention function is..,0x00000001=1: Chattering prevention function is.."
group.long 0x5AC++0x03
line.long 0x00 "FILCLKSEL7_A2,FILCLKSELn controls the division ratio of clock CP? for prevent chattering input to the port pin GPIO group"
hexmask.long 0x00 0.--31. 1. "FILCLKSEL_31_0,Set the division ratio of filter CLOCK"
group.long 0x5C0++0x03
line.long 0x00 "OUTDTSEL7_A2,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register"
abitfld.long 0x00 0.--31. "OUTDTSEL_31_0,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn" "0x00000000=0: General output register is used to..,0x00000001=1: Output data high register and.."
group.long 0x5C4++0x03
line.long 0x00 "OUTDTH7_A2,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTH_31_0,Outputting high value data" "0x00000000=0: Invalid data,0x00000001=1: Valid data"
group.long 0x5C8++0x03
line.long 0x00 "OUTDTL7_A2,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register and the output data.."
abitfld.long 0x00 0.--31. "OUTDTL_31_0,Outputting low value data" "0x00000000=0: Valid data,0x00000001=1: Invalid data"
group.long 0x5CC++0x03
line.long 0x00 "BOTHEDGE7_A2,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers"
abitfld.long 0x00 0.--31. "BOTHEDGE_31_0,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected" "0x00000000=0: One edge,0x00000001=1: Both edges"
group.long 0x5D0++0x03
line.long 0x00 "INEN7_A2,Create registers that can control IE in GPIO"
hexmask.long 0x00 0.--31. 1. "INEN_31_0,"
tree.end
tree "PFC_GPIO_FOR_SYS0"
base ad:0xE6078000
group.long 0x00++0x03
line.long 0x00 "PMMRSYS0_A0,PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers"
hexmask.long 0x00 0.--31. 1. "PMMR_31_0,Multiplexed Pin Setting Mask Writing a value to any register from among the GPSR IPSR DRVCTRL TDSEL POC PUEN PUD MODSEL DMPR PSER PSSR PINV PIS registers is enabled by writing the inverse of the value to this register"
group.long 0x04++0x03
line.long 0x00 "PMMERSYS0_A0,PMMERn / PMMERSYS performs enables / disables control of the PMMR"
abitfld.long 0x00 0.--31. "PMMER_31_0,Multiplexed Pin Setting Mask Enable" "0x00000000=0: PMMR function is disabled,0x00000001=1: PMMR function is enabled"
group.long 0x20++0x03
line.long 0x00 "DM0PRSYS0_A0,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM0PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x80++0x03
line.long 0x00 "DRV0CTRLSYS0_A0,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV0CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0xC0++0x03
line.long 0x00 "PUENSYS0_A0,PUENn / PUENSYS performs on / off control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUEN_31_0,"
group.long 0xE0++0x03
line.long 0x00 "PUDSYS0_A0,PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUD_31_0,"
group.long 0x200++0x03
line.long 0x00 "PMMRSYS0_A1,PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers"
hexmask.long 0x00 0.--31. 1. "PMMR_31_0,Multiplexed Pin Setting Mask Writing a value to any register from among the GPSR IPSR DRVCTRL TDSEL POC PUEN PUD MODSEL DMPR PSER PSSR PINV PIS registers is enabled by writing the inverse of the value to this register"
group.long 0x204++0x03
line.long 0x00 "PMMERSYS0_A1,PMMERn / PMMERSYS performs enables / disables control of the PMMR"
abitfld.long 0x00 0.--31. "PMMER_31_0,Multiplexed Pin Setting Mask Enable" "0x00000000=0: PMMR function is disabled,0x00000001=1: PMMR function is enabled"
group.long 0x220++0x03
line.long 0x00 "DM0PRSYS0_A1,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM0PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x280++0x03
line.long 0x00 "DRV0CTRLSYS0_A1,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV0CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x2C0++0x03
line.long 0x00 "PUENSYS0_A1,PUENn / PUENSYS performs on / off control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUEN_31_0,"
group.long 0x2E0++0x03
line.long 0x00 "PUDSYS0_A1,PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUD_31_0,"
group.long 0x400++0x03
line.long 0x00 "PMMRSYS0_A2,PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers"
hexmask.long 0x00 0.--31. 1. "PMMR_31_0,Multiplexed Pin Setting Mask Writing a value to any register from among the GPSR IPSR DRVCTRL TDSEL POC PUEN PUD MODSEL DMPR PSER PSSR PINV PIS registers is enabled by writing the inverse of the value to this register"
group.long 0x404++0x03
line.long 0x00 "PMMERSYS0_A2,PMMERn / PMMERSYS performs enables / disables control of the PMMR"
abitfld.long 0x00 0.--31. "PMMER_31_0,Multiplexed Pin Setting Mask Enable" "0x00000000=0: PMMR function is disabled,0x00000001=1: PMMR function is enabled"
group.long 0x420++0x03
line.long 0x00 "DM0PRSYS0_A2,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM0PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x480++0x03
line.long 0x00 "DRV0CTRLSYS0_A2,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV0CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x4C0++0x03
line.long 0x00 "PUENSYS0_A2,PUENn / PUENSYS performs on / off control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUEN_31_0,"
group.long 0x4E0++0x03
line.long 0x00 "PUDSYS0_A2,PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUD_31_0,"
tree.end
tree "PFC_GPIO_FOR_SYS1"
base ad:0xFFD98000
group.long 0x00++0x03
line.long 0x00 "PMMRSYS1_A0,PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers"
hexmask.long 0x00 0.--31. 1. "PMMR_31_0,Multiplexed Pin Setting Mask Writing a value to any register from among the GPSR IPSR DRVCTRL TDSEL POC PUEN PUD MODSEL DMPR PSER PSSR PINV PIS registers is enabled by writing the inverse of the value to this register"
group.long 0x04++0x03
line.long 0x00 "PMMERSYS1_A0,PMMERn / PMMERSYS performs enables / disables control of the PMMR"
abitfld.long 0x00 0.--31. "PMMER_31_0,Multiplexed Pin Setting Mask Enable" "0x00000000=0: PMMR function is disabled,0x00000001=1: PMMR function is enabled"
group.long 0x20++0x03
line.long 0x00 "DM0PRSYS1_A0,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM0PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x24++0x03
line.long 0x00 "DM1PRSYS1_A0,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM1PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x28++0x03
line.long 0x00 "DM2PRSYS1_A0,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM2PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x2C++0x03
line.long 0x00 "DM3PRSYS1_A0,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM3PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x84++0x03
line.long 0x00 "DRV1CTRLSYS1_A0,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV1CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x88++0x03
line.long 0x00 "DRV2CTRLSYS1_A0,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV2CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0xC0++0x03
line.long 0x00 "PUENSYS1_A0,PUENn / PUENSYS performs on / off control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUEN_31_0,"
group.long 0xC8++0x03
line.long 0x00 "PMMRSYS1_A1,PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers"
hexmask.long 0x00 0.--31. 1. "PMMR_31_0,Multiplexed Pin Setting Mask Writing a value to any register from among the GPSR IPSR DRVCTRL TDSEL POC PUEN PUD MODSEL DMPR PSER PSSR PINV PIS registers is enabled by writing the inverse of the value to this register"
group.long 0xCC++0x03
line.long 0x00 "PMMERSYS1_A1,PMMERn / PMMERSYS performs enables / disables control of the PMMR"
abitfld.long 0x00 0.--31. "PMMER_31_0,Multiplexed Pin Setting Mask Enable" "0x00000000=0: PMMR function is disabled,0x00000001=1: PMMR function is enabled"
group.long 0xE0++0x03
line.long 0x00 "PUDSYS1_A0,PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUD_31_0,"
group.long 0xE8++0x03
line.long 0x00 "DM0PRSYS1_A1,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM0PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0xEC++0x03
line.long 0x00 "DM1PRSYS1_A1,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM1PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0xF0++0x03
line.long 0x00 "DM2PRSYS1_A1,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM2PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0xF4++0x03
line.long 0x00 "DM3PRSYS1_A1,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM3PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x14C++0x03
line.long 0x00 "DRV1CTRLSYS1_A1,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV1CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x150++0x03
line.long 0x00 "DRV2CTRLSYS1_A1,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV2CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x188++0x03
line.long 0x00 "PUENSYS1_A1,PUENn / PUENSYS performs on / off control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUEN_31_0,"
group.long 0x190++0x03
line.long 0x00 "PMMRSYS1_A2,PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers"
hexmask.long 0x00 0.--31. 1. "PMMR_31_0,Multiplexed Pin Setting Mask Writing a value to any register from among the GPSR IPSR DRVCTRL TDSEL POC PUEN PUD MODSEL DMPR PSER PSSR PINV PIS registers is enabled by writing the inverse of the value to this register"
group.long 0x194++0x03
line.long 0x00 "PMMERSYS1_A2,PMMERn / PMMERSYS performs enables / disables control of the PMMR"
abitfld.long 0x00 0.--31. "PMMER_31_0,Multiplexed Pin Setting Mask Enable" "0x00000000=0: PMMR function is disabled,0x00000001=1: PMMR function is enabled"
group.long 0x1A8++0x03
line.long 0x00 "PUDSYS1_A1,PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUD_31_0,"
group.long 0x1B0++0x03
line.long 0x00 "DM0PRSYS1_A2,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM0PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x1B4++0x03
line.long 0x00 "DM1PRSYS1_A2,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM1PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x1B8++0x03
line.long 0x00 "DM2PRSYS1_A2,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM2PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x1BC++0x03
line.long 0x00 "DM3PRSYS1_A2,DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain"
abitfld.long 0x00 0.--31. "DM3PR_31_0,Bus Domain Protection" "0x00000000=0: Disable write to register,0x00000001=1: Enable write to register DMiPRn /.."
group.long 0x214++0x03
line.long 0x00 "DRV1CTRLSYS1_A2,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV1CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x218++0x03
line.long 0x00 "DRV2CTRLSYS1_A2,DRV*CTRLn / DRV**CTRLSYS controls the driving abilities of pins"
abitfld.long 0x00 0.--31. "DRV2CTRL_31_0,- Drive capability of pins with voltage type 1.8V/3.3V 2.5V/3.3V 3.3V based on value of DRV3/DRV2/DRV1 as below" "0x00000000=0: 1/4,0x00000001=1: 2/4,0x00000002=2: 3/4,0x00000003=3: Full,0x00000004=4: 5/8,0x00000005=5: 6/8,0x00000006=6: 7/8,0x00000007=7: Full"
group.long 0x250++0x03
line.long 0x00 "PUENSYS1_A2,PUENn / PUENSYS performs on / off control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUEN_31_0,"
group.long 0x270++0x03
line.long 0x00 "PUDSYS1_A2,PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors"
hexmask.long 0x00 0.--31. 1. "PUD_31_0,"
tree.end
tree.end
tree "CLOCK_PULSE_GENERATOR"
tree "CLOCK_PULSE_GENERATOR_CPG_INST_0"
base ad:0xE6150000
group.long 0x00++0x03
line.long 0x00 "CPGWPR,CPGWPR is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "WPRTCT_31_0,Writing a value to CPG registers is enabled by writing the inverse of the value to this register"
group.long 0x04++0x03
line.long 0x00 "CPGWPCR,CPGWPCR is a 32-bit readable/writable register"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Code value (H'A5A5)"
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved"
newline
bitfld.long 0x00 0. "WPE,Write protect enable" "0: Disable the write protect,1: Enable the write protect"
group.long 0x280++0x03
line.long 0x00 "BKBAPR,BKBAPR is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
bitfld.long 0x00 0. "BKBAPR,Enables or disables protection of the data storage in the Backup Buffer" "0: Enables protection of the data storage in the,1: Disables protection of the data storage in the"
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x400)++0x03
line.long 0x00 "FSRCHKRA$1,The usage method is described in 9.5.2"
hexmask.long 0x00 0.--31. 1. "RCHK_31_0,[Set Condition] This bit is set by writing 1 to corresponding bit of RSET field of FSRCHKSETRn"
repeat.end
repeat 12. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C )
group.long ($2+0x440)++0x03
line.long 0x00 "FSRCHKRA$1,The usage method is described in 9.5.2"
hexmask.long 0x00 0.--31. 1. "RCHK_31_0,[Set Condition] This bit is set by writing 1 to corresponding bit of RSET field of FSRCHKSETRn"
repeat.end
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x480)++0x03
line.long 0x00 "FSRCHKRB$1,The usage method is described in 9.5.2"
hexmask.long 0x00 0.--31. 1. "RCHK_31_0,[Set Condition] This bit is set by writing 1 to corresponding bit of RSET field of FSRCHKSETRn"
repeat.end
repeat 12. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C )
group.long ($2+0x4C0)++0x03
line.long 0x00 "FSRCHKRB$1,The usage method is described in 9.5.2"
hexmask.long 0x00 0.--31. 1. "RCHK_31_0,[Set Condition] This bit is set by writing 1 to corresponding bit of RSET field of FSRCHKSETRn"
repeat.end
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x500)++0x03
line.long 0x00 "FSRCHKSETR$1,The usage method is described in 9.5.2"
hexmask.long 0x00 0.--31. 1. "RSET_31_0,When writing 1 to bits of RSET field of FSRCHKSETRn corresponding bits of RCHK field of both FSRCHKRAn and FSRCHKRBn are set to 1"
repeat.end
repeat 12. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C )
group.long ($2+0x540)++0x03
line.long 0x00 "FSRCHKSETR$1,The usage method is described in 9.5.2"
hexmask.long 0x00 0.--31. 1. "RSET_31_0,When writing 1 to bits of RSET field of FSRCHKSETRn corresponding bits of RCHK field of both FSRCHKRAn and FSRCHKRBn are set to 1"
repeat.end
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x580)++0x03
line.long 0x00 "FSRCHKCLRR$1,FSRCHKCLRRn is a 32-bit writable register"
hexmask.long 0x00 0.--31. 1. "RCLR_31_0,When writing 1 to bits of RCLRm of FSRCHKCLRRn corresponding bits of RCHK field of both FSRCHKRAn and FSRCHKRBn are cleared to 0"
repeat.end
repeat 12. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C )
group.long ($2+0x5C0)++0x03
line.long 0x00 "FSRCHKCLRR$1,FSRCHKCLRRn is a 32-bit writable register"
hexmask.long 0x00 0.--31. 1. "RCLR_31_0,When writing 1 to bits of RCLRm of FSRCHKCLRRn corresponding bits of RCHK field of both FSRCHKRAn and FSRCHKRBn are cleared to 0"
repeat.end
group.long 0x804++0x03
line.long 0x00 "FRQCRB,FRQCRB is a 32-bit readable/writable register"
bitfld.long 0x00 31. "KICK,KICK bit" "0: Does not activate the FRQCRB and FRQCRC..,1: Activates the FRQCRB and FRQCRC settings"
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved"
newline
bitfld.long 0x00 20.--23. "ZTRFC_3_0,Debug Trace port clock (ZTR?) Frequency division ratio" "0: ZTR? frequency = (PLL1VCO x 1/2) x 1/2,1: ZTR? frequency = (PLL1VCO x 1/2) x 1/3,2: ZTR? frequency = (PLL1VCO x 1/2) x 1/4,3: ZTR? frequency = (PLL1VCO x 1/2) x 1/6,4: ZTR? frequency = (PLL1VCO x 1/2) x 1/8,5: ZTR? frequency = (PLL1VCO x 1/2) x 1/12,6: ZTR? frequency = (PLL1VCO x 1/2) x 1/16 Other,?..."
bitfld.long 0x00 16.--19. "ZTFC_3_0,Debug Trace port clock (ZT?) Frequency division ratio" "0: ZT? frequency = (PLL1VCO x 1/2) x 1/2..,1: ZT? frequency = (PLL1VCO x 1/2) x 1/3..,2: ZT? frequency = (PLL1VCO x 1/2) x 1/4..,3: ZT? frequency = (PLL1VCO x 1/2) x 1/6..,4: ZT? frequency = (PLL1VCO x 1/2) x 1/8..,5: ZT? frequency = (PLL1VCO x 1/2) x 1/12..,6: ZT? frequency = (PLL1VCO x 1/2) x 1/16 Other,?..."
newline
bitfld.long 0x00 12.--15. "ZSFC_3_0,Debug Trace port clock (ZS?) Frequency division ratio" "0: ZS? frequency = (PLL1VCO x 1/2) x 1/2..,1: ZS? frequency = (PLL1VCO x 1/2) x 1/3..,2: ZS? frequency = (PLL1VCO x 1/2) x 1/4..,3: ZS? frequency = (PLL1VCO x 1/2) x 1/6..,4: ZS? frequency = (PLL1VCO x 1/2) x 1/8..,5: ZS? frequency = (PLL1VCO x 1/2) x 1/12..,6: ZS? frequency = (PLL1VCO x 1/2) x 1/16 Other,?..."
hexmask.long.word 0x00 0.--11. 1. "Reserved_0,Reserved"
group.long 0x808++0x03
line.long 0x00 "FRQCRC,FRQCRC0 is a 32-bit readable/writable register"
hexmask.long.word 0x00 21.--31. 1. "Reserved_21,Reserved"
bitfld.long 0x00 16.--20. "ZRFC_4_0,CR52 clock (ZR?) Frequency division ratio" "0: (PLL6VCO x 1/2) x 32/32,1: (PLL6VCO x 1/2) x 31/32,?,?,?,?,?,?,?,?,?,?,?,?,?,?,16: (PLL6VCO x 1/2) x 16/32,?,?,?,?,?,?,?,?,?,?,?,?,?,30: (PLL6VCO x 1/2) x 2/32,31: (PLL6VCO x 1/2) x 1/32"
newline
rbitfld.long 0x00 13.--15. "Reserved_13,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--12. "Z1FC_4_0,CA55 clock (Z1?) Frequency division ratio" "0: (PLL2VCO x 1/2) x 32/32,1: (PLL2VCO x 1/2) x 31/32,?,?,?,?,?,?,?,?,?,?,?,?,?,?,16: (PLL2VCO x 1/2) x 16/32,?,?,?,?,?,?,?,?,?,?,?,?,?,30: (PLL2VCO x 1/2) x 2/32,31: (PLL2VCO x 1/2) x 1/32"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "Z0FC_4_0,CA55 clock (Z0?) Frequency division ratio" "0: (PLL2VCO x 1/2) x 32/32,1: (PLL2VCO x 1/2) x 31/32,?,?,?,?,?,?,?,?,?,?,?,?,?,?,16: (PLL2VCO x 1/2) x 16/32,?,?,?,?,?,?,?,?,?,?,?,?,?,30: (PLL2VCO x 1/2) x 2/32,31: (PLL2VCO x 1/2) x 1/32"
group.long 0x80C++0x03
line.long 0x00 "FRQCRD,FRQCRD0 is a 32-bit readable/writable register"
bitfld.long 0x00 31. "KICK,KICK bit" "0: Does not activate the FRQCRD settings,1: Activates the FRQCRD settings"
hexmask.long 0x00 4.--30. 1. "Reserved_4,Reserved"
newline
bitfld.long 0x00 0.--3. "ZB3FC,ZB3? ZB3D2? ZB3D4? clock for DDR/DBSC frequency division ratio is set" "?,?,2: ZB3? = (PLL3VCO) x 1/4 x 1/1 ZB3D2? = (PLL3VCO),?,4: ZB3? = (PLL3VCO) x 1/4 x 1/2 ZB3D2? = (PLL3VCO),?,6: ZB3? = (PLL3VCO) x 1/4 x 1/4 ZB3D2? = (PLL3VCO),?,?,9: ZB3? = (PLL3VCO) x 1/4 x 1/8 ZB3D2? = (PLL3VCO),?..."
group.long 0x820++0x03
line.long 0x00 "PLLECR,PLLECR is a 32-bit readable/writable register"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved"
rbitfld.long 0x00 15. "PLL6ST,PLL circuit 6 status" "0: PLL circuit 6 is turned off,1: PLL circuit 6 is turned on"
newline
rbitfld.long 0x00 14. "Reserved_14,Reserved" "0,1"
rbitfld.long 0x00 12.--13. "Reserved_12,Reserved" "0,1,2,3"
newline
rbitfld.long 0x00 11. "PLL3ST,PLL circuit 3 status" "0: PLL circuit 3 is turned off,1: PLL circuit 3 is turned on"
rbitfld.long 0x00 10. "Reserved_10,Reserved" "0,1"
newline
rbitfld.long 0x00 9. "PLL2ST,PLL circuit 2 status" "0: PLL circuit 2 is turned off,1: PLL circuit 2 is turned on"
rbitfld.long 0x00 8. "PLL1ST,PLL circuit 1 status" "0: PLL circuit 1 is turned off,1: PLL circuit 1 is turned on"
newline
bitfld.long 0x00 7. "PLL6E,PLL circuit 6 enable" "0: Turns off PLL circuit 6,1: Turns on PLL circuit 6"
rbitfld.long 0x00 6. "Reserved_6,Reserved" "0,1"
newline
rbitfld.long 0x00 4.--5. "Reserved_4,Reserved" "0,1,2,3"
bitfld.long 0x00 3. "PLL3E,PLL circuit 3 enable" "0: Turns off PLL circuit 3,1: Turns on PLL circuit 3"
newline
rbitfld.long 0x00 2. "Reserved_2,Reserved" "0,1"
bitfld.long 0x00 1. "PLL2E,PLL circuit 2 enable" "0: Turns off PLL circuit 2,1: Turns on PLL circuit 2"
newline
bitfld.long 0x00 0. "PLL1E,PLL circuit 1 enable" "0: Turns off PLL circuit 1,1: Turns on PLL circuit 1"
group.long 0x830++0x03
line.long 0x00 "PLL1CR0,PLL1CR0 is a 32-bit readable/writable register"
rbitfld.long 0x00 29.--31. "Reserved_29,Reserved" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 20.--28. 1. "NI_8_0,PLL1 multiplication ratio control parameter"
newline
rbitfld.long 0x00 19. "Reserved_19,Reserved" "0,1"
rbitfld.long 0x00 16.--18. "SSMODE_2_0,PLL mode and output frequency dither mode are shown in the value of SSMODE[2:0]" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 15. "Reserved_15,Reserved" "0,1"
hexmask.long.byte 0x00 8.--14. 1. "SSFREQ_6_0,The parameter shows the SSCG modulation frequency (Fmod) defined in Figure 8.1.1"
newline
rbitfld.long 0x00 7. "Reserved_7,Reserved" "0,1"
hexmask.long.byte 0x00 0.--6. 1. "SSDEPT_6_0,The parameter shows the modulation depth defined in Figure 8.1.1"
group.long 0x834++0x03
line.long 0x00 "PLL2CR0,PLL2CR0 is a 32-bit readable/writable register"
bitfld.long 0x00 31. "KICK,KICK bit" "0: Does not activate the PLL2CRn (n = 0 1)..,1: Activate the PLL0CRn (n = 0 1) settings"
rbitfld.long 0x00 29.--30. "Reserved_29,Reserved" "0,1,2,3"
newline
hexmask.long.word 0x00 20.--28. 1. "NI_8_0,PLL2 multiplication ratio control parameter"
rbitfld.long 0x00 19. "Reserved_19,Reserved" "0,1"
newline
bitfld.long 0x00 16.--18. "SSMODE_2_0,PLL mode and output frequency dither mode are shown in the value of SSMODE[2:0]" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 15. "Reserved_15,Reserved" "0,1"
newline
hexmask.long.byte 0x00 8.--14. 1. "SSFREQ_6_0,The parameter shows the SSCG modulation frequency (Fmod) defined in Figure 8.1.1"
rbitfld.long 0x00 7. "Reserved_7,Reserved" "0,1"
newline
hexmask.long.byte 0x00 0.--6. 1. "SSDEPT_6_0,The parameter shows the modulation depth defined in Figure 8.1.1"
group.long 0x83C++0x03
line.long 0x00 "PLL3CR0,PLL3CR0 is a 32-bit readable/writable register"
bitfld.long 0x00 31. "KICK,KICK bit" "0: Does not activate the PLL3CRn (n = 0 1)..,1: Activate the PLL0CRn (n = 0 1) settings"
rbitfld.long 0x00 29.--30. "Reserved_29,Reserved" "0,1,2,3"
newline
hexmask.long.word 0x00 20.--28. 1. "NI_8_0,PLL3 multiplication ratio control parameter"
rbitfld.long 0x00 19. "Reserved_19,Reserved" "0,1"
newline
bitfld.long 0x00 16.--18. "SSMODE_2_0,As described in 8.1.5.3 DDR operation can be guaranteed only during the integer multiplication PLL mode" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 0.--15. 1. "Reserved_0,Reserved"
group.long 0x84C++0x03
line.long 0x00 "PLL6CR0,PLL6CR0 is a 32-bit readable/writable register"
bitfld.long 0x00 31. "KICK,KICK bit" "0: Does not activate the PLL6CRn (n = 0 1)..,1: Activate the PLL0CRn (n = 0 1) settings"
rbitfld.long 0x00 29.--30. "Reserved_29,Reserved" "0,1,2,3"
newline
hexmask.long.word 0x00 20.--28. 1. "NI_8_0,PLL6 multiplication ratio control parameter"
rbitfld.long 0x00 19. "Reserved_19,Reserved" "0,1"
newline
bitfld.long 0x00 16.--18. "SSMODE_2_0,PLL mode and output frequency dither mode are shown in the value of SSMODE[2:0]" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 15. "Reserved_15,Reserved" "0,1"
newline
hexmask.long.byte 0x00 8.--14. 1. "SSFREQ_6_0,The parameter shows the SSCG modulation frequency (Fmod) defined in Figure 8.1.1"
rbitfld.long 0x00 7. "Reserved_7,Reserved" "0,1"
newline
hexmask.long.byte 0x00 0.--6. 1. "SSDEPT_6_0,The parameter shows the modulation depth defined in Figure 8.1.1"
group.long 0x850++0x03
line.long 0x00 "PLL1STPCR,PLLnSTPCR is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 10.--31. 1. "Reserved_10,Reserved"
bitfld.long 0x00 9. "A2E1D1STP,PLLn circuit Stop Condition by CA55SS1 cluster 1 domain (A2E1D1) Power Status" "0: PLL circuit is not turned off when the power,1: PLL circuit is turned off when the power supply"
newline
bitfld.long 0x00 8. "A2E1D0STP,PLLn circuit Stop Condition by CA55SS1 cluster 0 domain (A2E1D0) Power Status" "0: PLL circuit is not turned off when the power,1: PLL circuit is turned off when the power supply"
bitfld.long 0x00 7. "A2E0D1STP,PLLn circuit Stop Condition by CA55SS0 cluster 1 domain (A2E0D1) Power Status" "0: PLL circuit is not turned off when the power,1: PLL circuit is turned off when the power supply"
newline
bitfld.long 0x00 6. "A2E0D0STP,PLLn circuit Stop Condition by CA55SS0 cluster 0 domain (A2E0D0) Power Status" "0: PLL circuit is not turned off when the power,1: PLL circuit is turned off when the power supply"
rbitfld.long 0x00 0.--5. "Reserved_0,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x85C++0x03
line.long 0x00 "PLL3STPCR,PLLnSTPCR is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 10.--31. 1. "Reserved_10,Reserved"
bitfld.long 0x00 9. "A2E1D1STP,PLLn circuit Stop Condition by CA55SS1 cluster 1 domain (A2E1D1) Power Status" "0: PLL circuit is not turned off when the power,1: PLL circuit is turned off when the power supply"
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bitfld.long 0x00 8. "A2E1D0STP,PLLn circuit Stop Condition by CA55SS1 cluster 0 domain (A2E1D0) Power Status" "0: PLL circuit is not turned off when the power,1: PLL circuit is turned off when the power supply"
bitfld.long 0x00 7. "A2E0D1STP,PLLn circuit Stop Condition by CA55SS0 cluster 1 domain (A2E0D1) Power Status" "0: PLL circuit is not turned off when the power,1: PLL circuit is turned off when the power supply"
newline
bitfld.long 0x00 6. "A2E0D0STP,PLLn circuit Stop Condition by CA55SS0 cluster 0 domain (A2E0D0) Power Status" "0: PLL circuit is not turned off when the power,1: PLL circuit is turned off when the power supply"
rbitfld.long 0x00 0.--5. "Reserved_0,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x86C++0x03
line.long 0x00 "PLL6STPCR,PLLnSTPCR is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 10.--31. 1. "Reserved_10,Reserved"
bitfld.long 0x00 9. "A2E1D1STP,PLLn circuit Stop Condition by CA55SS1 cluster 1 domain (A2E1D1) Power Status" "0: PLL circuit is not turned off when the power,1: PLL circuit is turned off when the power supply"
newline
bitfld.long 0x00 8. "A2E1D0STP,PLLn circuit Stop Condition by CA55SS1 cluster 0 domain (A2E1D0) Power Status" "0: PLL circuit is not turned off when the power,1: PLL circuit is turned off when the power supply"
bitfld.long 0x00 7. "A2E0D1STP,PLLn circuit Stop Condition by CA55SS0 cluster 1 domain (A2E0D1) Power Status" "0: PLL circuit is not turned off when the power,1: PLL circuit is turned off when the power supply"
newline
bitfld.long 0x00 6. "A2E0D0STP,PLLn circuit Stop Condition by CA55SS0 cluster 0 domain (A2E0D0) Power Status" "0: PLL circuit is not turned off when the power,1: PLL circuit is turned off when the power supply"
rbitfld.long 0x00 0.--5. "Reserved_0,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x870++0x03
line.long 0x00 "SD0CKCR0,This register should be set before SD-IF0 module (SDHI) is operated"
hexmask.long.tbyte 0x00 10.--31. 1. "Reserved_10,Reserved"
bitfld.long 0x00 9. "STP0HCK,Clock Stop" "0: Supplies SDnH clock,1: Stops SDnH clock"
newline
bitfld.long 0x00 8. "STP0CK,Clock Stop" "0: Supplies SDn clock,1: Stops SDn clock"
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 2.--4. "SDSRCFC_2_0,SD0H? clock Frequency Division Ratio SD0CKCR1.SDSRCSEL[1:0] =" "0: SD0H? = SDSRC? ? 1/1 SD0? = SD0SRC? ? 1/4 (when,1: SD0H? = SDSRC? ? 1/2 SD0? = SDSRC? ? 1/8 (when,2: SD0H? = SDSRC? ? 1/4 (should be stopped by,3: Setting prohibited,4: SD0H? = should be stopped (should be stopped by,5: Setting prohibited,6: Setting prohibited,7: Setting prohibited SD0CKCR1.SDSRCSEL[1:0] ="
bitfld.long 0x00 0.--1. "SD0FC_1_0,Select SD0? division Ratio" "0: SD0? = SD0H? ? 1/2,1: SD0? = SD0H? ? 1/4,2: Setting prohibited,3: Setting prohibited Example 1"
group.long 0x874++0x03
line.long 0x00 "RPCCKCR,RPCCKCR is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 10.--31. 1. "Reserved_10,Reserved"
bitfld.long 0x00 9. "CKSTP2,RPCD2? Clock" "0: Supplies clock to RPC,1: Stops clock to RPC"
newline
bitfld.long 0x00 8. "CKSTP,RPC? Clock Stop" "0: Supplies clock to RPC,1: Stops clock to RPC"
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0.--4. "RPCFC_4_0,RPC clock (RPC? RPCD2?) Frequency Division Ratio.When PLL5 is turned off RPC clock can't be oscillated (set CKSTP1 and CKSTP2 before turning off PLL5)" "0: (PLL5VCO) x 1/2 x 1/2,1: (PLL5VCO) x 1/2 x 1/3,2: (PLL5VCO) x 1/5,3: (PLL5VCO) x 1/6 RPCFC[2:0],?..."
group.long 0x87C++0x03
line.long 0x00 "MSOCKCR,MSOCKCR is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 9.--31. 1. "Reserved_9,Reserved"
bitfld.long 0x00 8. "CKSTP,Clock Stop" "0: Supplies clock to MSIOF module,1: Stops clock to MSIOF module"
newline
rbitfld.long 0x00 6.--7. "Reserved_6,Reserved" "0,1,2,3"
bitfld.long 0x00 0.--5. "DIV_5_0,Division Ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x8A4++0x03
line.long 0x00 "SD0CKCR1,This register should be set before SD-IF0 module (SDHI) is operated"
rbitfld.long 0x00 31. "Reserved_31,Reserved" "0,1"
bitfld.long 0x00 29.--30. "SDSRCSEL_1_0,SDSRC? clock frequency select" "0: 800.00 MHz,1: 640.00 MHz,2: 533.33 MHz,3: Setting prohibited"
newline
rbitfld.long 0x00 28. "Reserved_28,Reserved" "0,1"
hexmask.long.byte 0x00 20.--27. 1. "Reserved_20,Reserved"
newline
rbitfld.long 0x00 16.--19. "Reserved_16,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 4.--15. 1. "Reserved_4,Reserved"
newline
rbitfld.long 0x00 0.--3. "Reserved_0,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8B0++0x03
line.long 0x00 "PLL1CR1,PLL1CR1 is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "NF_23_0,PLL1 multiplication ratio control parameter"
group.long 0x8B8++0x03
line.long 0x00 "PLL2CR1,PLL2CR1 is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "NF_23_0,PLL2 multiplication ratio control parameter"
group.long 0x8C0++0x03
line.long 0x00 "PLL3CR1,PLL3CR1 is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "NF_23_0,Before SSMODE[2:0] is changed from 3B100 (fractional multiplication mode) to 3B000 (integer multiplication mode) write 24H000 to NF[23:0]"
group.long 0x8D8++0x03
line.long 0x00 "PLL6CR1,PLL6CR1 is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "NF_23_0,PLL6 multiplication ratio control parameter"
group.long 0x8E8++0x03
line.long 0x00 "RSW2CKCR,RSW2CKCR is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 9.--31. 1. "Reserved_9,Reserved"
bitfld.long 0x00 8. "CKSTP,Clock Stop" "0: Supplies the clock,1: Stops the clock"
newline
hexmask.long.byte 0x00 0.--7. 1. "Reserved_0,Reserved"
group.long 0xC00++0x03
line.long 0x00 "PLL1FBCKMCSR,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "CHKRES,Check result" "0: Clock oscillates normally,1: Detect unexpected clock oscillation"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 24. "CLRMON,Reference for clear command signal - PLL1FBCKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued"
rbitfld.long 0x00 19.--23. "Reserved_19,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 18. "RSTMMON,Reset status for monitor clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
rbitfld.long 0x00 17. "RSTMSMP,Reset status for sampling clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
newline
rbitfld.long 0x00 16. "ENMON,Operating status" "0: Clock monitor is stopped,1: Clock monitor is operating"
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved"
newline
bitfld.long 0x00 1. "INTEN,Interrupt mask bit" "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor"
bitfld.long 0x00 0. "CHKEN,Enable for checking clock oscillation" "0: Stop clock monitor checking,1: Run clock monitor checking"
group.long 0xC04++0x03
line.long 0x00 "PLL1FBCKMECR,It is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "CLRRES,Reference for clear command signal - PLL1FBCKMECR.CLRRES" "0: Release clear signal,1: Issue clear signal to clock monitor when clock"
group.long 0xC08++0x03
line.long 0x00 "PLL1FBCKMLCH,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPH_23_0,The upper limit to judge as expected oscillation"
group.long 0xC0C++0x03
line.long 0x00 "PLL1FBCKMLCL,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPL_23_0,The lower limit to judge as expected oscillation"
group.long 0xC10++0x03
line.long 0x00 "PLL1FBCKMCNT,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNT_6_0,Monitoring PLL1FBCKMCNT.UPDCNT value"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,Monitoring PLL1FBCKMCNT.MONCNT value"
group.long 0xC14++0x03
line.long 0x00 "PLL1FBCKMCNTE,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "VLD,Valid bit" "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNTE_6_0,PLL1FBCKMCNT.UPDCNT value when the first error occurred"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,The counter value of clock monitor when the first error occurred"
group.long 0xC20++0x03
line.long 0x00 "PLL2FBCKMCSR,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "CHKRES,Check result" "0: Clock oscillates normally,1: Detect unexpected clock oscillation"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 24. "CLRMON,Reference for clear command signal - PLL2FBCKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued"
rbitfld.long 0x00 19.--23. "Reserved_19,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 18. "RSTMMON,Reset status for monitor clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
rbitfld.long 0x00 17. "RSTMSMP,Reset status for sampling clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
newline
rbitfld.long 0x00 16. "ENMON,Operating status" "0: Clock monitor is stopped,1: Clock monitor is operating"
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved"
newline
bitfld.long 0x00 1. "INTEN,Interrupt mask bit" "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor"
bitfld.long 0x00 0. "CHKEN,Enable for checking clock oscillation" "0: Stop clock monitor checking,1: Run clock monitor checking"
group.long 0xC24++0x03
line.long 0x00 "PLL2FBCKMECR,It is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "CLRRES,Reference for clear command signal - PLL2FBCKMECR.CLRRES" "0: Release clear signal,1: Issue clear signal to clock monitor when clock"
group.long 0xC28++0x03
line.long 0x00 "PLL2FBCKMLCH,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPH_23_0,The upper limit to judge as expected oscillation"
group.long 0xC2C++0x03
line.long 0x00 "PLL2FBCKMLCL,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPL_23_0,The lower limit to judge as expected oscillation"
group.long 0xC30++0x03
line.long 0x00 "PLL2FBCKMCNT,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNT_6_0,Monitoring PLL2FBCKMCNT.UPDCNT value"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,Monitoring PLL2FBCKMCNT.MONCNT value"
group.long 0xC34++0x03
line.long 0x00 "PLL2FBCKMCNTE,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "VLD,Valid bit" "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNTE_6_0,PLL2FBCKMCNT.UPDCNT value when the first error occurred"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,The counter value of clock monitor when the first error occurred"
group.long 0xC60++0x03
line.long 0x00 "PLL3FBCKMCSR,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "CHKRES,Check result" "0: Clock oscillates normally,1: Detect unexpected clock oscillation"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 24. "CLRMON,Reference for clear command signal - PLL3FBCKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued"
rbitfld.long 0x00 19.--23. "Reserved_19,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 18. "RSTMMON,Reset status for monitor clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
rbitfld.long 0x00 17. "RSTMSMP,Reset status for sampling clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
newline
rbitfld.long 0x00 16. "ENMON,Operating status" "0: Clock monitor is stopped,1: Clock monitor is operating"
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved"
newline
bitfld.long 0x00 1. "INTEN,Interrupt mask bit" "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor"
bitfld.long 0x00 0. "CHKEN,Enable for checking clock oscillation" "0: Stop clock monitor checking,1: Run clock monitor checking"
group.long 0xC64++0x03
line.long 0x00 "PLL3FBCKMECR,It is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "CLRRES,Reference for clear command signal - PLL3FBCKMECR.CLRRES" "0: Release clear signal,1: Issue clear signal to clock monitor when clock"
group.long 0xC68++0x03
line.long 0x00 "PLL3FBCKMLCH,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPH_23_0,The upper limit to judge as expected oscillation"
group.long 0xC6C++0x03
line.long 0x00 "PLL3FBCKMLCL,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPL_23_0,The lower limit to judge as expected oscillation"
group.long 0xC70++0x03
line.long 0x00 "PLL3FBCKMCNT,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNT_6_0,Monitoring PLL3FBCKMCNT.UPDCNT value"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,Monitoring PLL3FBCKMCNT.MONCNT value"
group.long 0xC74++0x03
line.long 0x00 "PLL3FBCKMCNTE,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "VLD,Valid bit" "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNTE_6_0,PLL3FBCKMCNT.UPDCNT value when the first error occurred"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,The counter value of clock monitor when the first error occurred"
group.long 0xCC0++0x03
line.long 0x00 "PLL5FBCKMCSR,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "CHKRES,Check result" "0: Clock oscillates normally,1: Detect unexpected clock oscillation"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 24. "CLRMON,Reference for clear command signal - PLL5FBCKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued"
rbitfld.long 0x00 19.--23. "Reserved_19,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 18. "RSTMMON,Reset status for monitor clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
rbitfld.long 0x00 17. "RSTMSMP,Reset status for sampling clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
newline
rbitfld.long 0x00 16. "ENMON,Operating status" "0: Clock monitor is stopped,1: Clock monitor is operating"
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved"
newline
bitfld.long 0x00 1. "INTEN,Interrupt mask bit" "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor"
bitfld.long 0x00 0. "CHKEN,Enable for checking clock oscillation" "0: Stop clock monitor checking,1: Run clock monitor checking"
group.long 0xCC4++0x03
line.long 0x00 "PLL5FBCKMECR,It is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "CLRRES,Reference for clear command signal - PLL5FBCKMECR.CLRRES" "0: Release clear signal,1: Issue clear signal to clock monitor when clock"
group.long 0xCC8++0x03
line.long 0x00 "PLL5FBCKMLCH,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPH_23_0,The upper limit to judge as expected oscillation"
group.long 0xCCC++0x03
line.long 0x00 "PLL5FBCKMLCL,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPL_23_0,The lower limit to judge as expected oscillation"
group.long 0xCD0++0x03
line.long 0x00 "PLL5FBCKMCNT,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNT_6_0,Monitoring PLL5FBCKMCNT.UPDCNT value"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,Monitoring PLL5FBCKMCNT.MONCNT value"
group.long 0xCD4++0x03
line.long 0x00 "PLL5FBCKMCNTE,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "VLD,Valid bit" "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNTE_6_0,PLL5FBCKMCNT.UPDCNT value when the first error occurred"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,The counter value of clock monitor when the first error occurred"
group.long 0xD00++0x03
line.long 0x00 "CBFUSACKMCSR,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "CHKRES,Check result" "0: Clock oscillates normally,1: Detect unexpected clock oscillation"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 24. "CLRMON,Reference for clear command signal - CBFUSACKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued"
rbitfld.long 0x00 19.--23. "Reserved_19,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 18. "RSTMMON,Reset status for monitor clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
rbitfld.long 0x00 17. "RSTMSMP,Reset status for sampling clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
newline
rbitfld.long 0x00 16. "ENMON,Operating status" "0: Clock monitor is stopped,1: Clock monitor is operating"
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved"
newline
bitfld.long 0x00 1. "INTEN,Interrupt mask bit" "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor"
bitfld.long 0x00 0. "CHKEN,Enable for checking clock oscillation" "0: Stop clock monitor checking,1: Run clock monitor checking"
group.long 0xD04++0x03
line.long 0x00 "CBFUSACKMECR,It is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "CLRRES,Reference for clear command signal - CBFUSACKMECR.CLRRES" "0: Release clear signal,1: Issue clear signal to clock monitor when clock"
group.long 0xD08++0x03
line.long 0x00 "CBFUSACKMLCH,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPH_23_0,The upper limit to judge as expected oscillation"
group.long 0xD0C++0x03
line.long 0x00 "CBFUSACKMLCL,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPL_23_0,The lower limit to judge as expected oscillation"
group.long 0xD10++0x03
line.long 0x00 "CBFUSACKMCNT,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNT_6_0,Monitoring CBFUSACKMCNT.UPDCNT value"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,Monitoring CBFUSACKMCNT.MONCNT value"
group.long 0xD14++0x03
line.long 0x00 "CBFUSACKMCNTE,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "VLD,Valid bit" "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNTE_6_0,CBFUSACKMCNT.UPDCNT value when the first error occurred"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,The counter value of clock monitor when the first error occurred"
group.long 0xD1C++0x03
line.long 0x00 "CPGACKMSR,It is a 32-bit readable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved" "0,1"
rbitfld.long 0x00 30. "Reserved_30,Reserved" "0,1"
newline
rbitfld.long 0x00 29. "Reserved_29,Reserved" "0,1"
rbitfld.long 0x00 28. "Reserved_28,Reserved" "0,1"
newline
rbitfld.long 0x00 27. "Reserved_27,Reserved" "0,1"
rbitfld.long 0x00 26. "Reserved_26,Reserved" "0,1"
newline
rbitfld.long 0x00 25. "Reserved_25,Reserved" "0,1"
rbitfld.long 0x00 24. "Reserved_24,Reserved" "0,1"
newline
rbitfld.long 0x00 23. "Reserved_23,Reserved" "0,1"
rbitfld.long 0x00 22. "Reserved_22,Reserved" "0,1"
newline
rbitfld.long 0x00 21. "Reserved_21,Reserved" "0,1"
rbitfld.long 0x00 20. "Reserved_20,Reserved" "0,1"
newline
rbitfld.long 0x00 19. "Reserved_19,Reserved" "0,1"
rbitfld.long 0x00 18. "Reserved_18,Reserved" "0,1"
newline
rbitfld.long 0x00 17. "Reserved_17,Reserved" "0,1"
rbitfld.long 0x00 16. "Reserved_16,Reserved" "0,1"
newline
rbitfld.long 0x00 15. "Reserved_15,Reserved" "0,1"
rbitfld.long 0x00 14. "Reserved_14,Reserved" "0,1"
newline
rbitfld.long 0x00 13. "Reserved_13,Reserved" "0,1"
rbitfld.long 0x00 12. "Reserved_12,Reserved" "0,1"
newline
rbitfld.long 0x00 11. "Reserved_11,Reserved" "0,1"
rbitfld.long 0x00 10. "CHKRES010,RCLK" "0,1"
newline
rbitfld.long 0x00 9. "CHKRES009,PLL6FBCK" "0,1"
rbitfld.long 0x00 8. "CHKRES008,CBFUSA" "0,1"
newline
rbitfld.long 0x00 7. "Reserved_7,Reserved" "0,1"
rbitfld.long 0x00 6. "CHKRES007,PLL5FBCK" "0,1"
newline
rbitfld.long 0x00 5. "Reserved_5,Reserved" "0,1"
rbitfld.long 0x00 4. "Reserved_4,Reserved" "0,1"
newline
rbitfld.long 0x00 3. "CHKRES003,PLL3FBCK" "0,1"
rbitfld.long 0x00 2. "Reserved_2,Reserved" "0,1"
newline
rbitfld.long 0x00 1. "CHKRES001,PLL2FBCK" "0,1"
rbitfld.long 0x00 0. "CHKRES000,PLL1FBCK" "0,1"
group.long 0xE60++0x03
line.long 0x00 "PLL6FBCKMCSR,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "CHKRES,Check result" "0: Clock oscillates normally,1: Detect unexpected clock oscillation"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 24. "CLRMON,Reference for clear command signal - PLL6FBCKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued"
rbitfld.long 0x00 19.--23. "Reserved_19,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 18. "RSTMMON,Reset status for monitor clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
rbitfld.long 0x00 17. "RSTMSMP,Reset status for sampling clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
newline
rbitfld.long 0x00 16. "ENMON,Operating status" "0: Clock monitor is stopped,1: Clock monitor is operating"
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved"
newline
bitfld.long 0x00 1. "INTEN,Interrupt mask bit" "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor"
bitfld.long 0x00 0. "CHKEN,Enable for checking clock oscillation" "0: Stop clock monitor checking,1: Run clock monitor checking"
group.long 0xE64++0x03
line.long 0x00 "PLL6FBCKMECR,It is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "CLRRES,Reference for clear command signal - PLL6FBCKMECR.CLRRES" "0: Release clear signal,1: Issue clear signal to clock monitor when clock"
group.long 0xE68++0x03
line.long 0x00 "PLL6FBCKMLCH,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPH_23_0,The upper limit to judge as expected oscillation"
group.long 0xE6C++0x03
line.long 0x00 "PLL6FBCKMLCL,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPL_23_0,The lower limit to judge as expected oscillation"
group.long 0xE70++0x03
line.long 0x00 "PLL6FBCKMCNT,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNT_6_0,Monitoring PLL6FBCKMCNT.UPDCNT value"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,Monitoring PLL6FBCKMCNT.MONCNT value"
group.long 0xE74++0x03
line.long 0x00 "PLL6FBCKMCNTE,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "VLD,Valid bit" "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNTE_6_0,PLL6FBCKMCNT.UPDCNT value when the first error occurred"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,The counter value of clock monitor when the first error occurred"
group.long 0xE80++0x03
line.long 0x00 "RCLKCKMCSR,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "CHKRES,Check result" "0: Clock oscillates normally,1: Detect unexpected clock oscillation"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 24. "CLRMON,Reference for clear command signal - RCLKCKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued"
rbitfld.long 0x00 19.--23. "Reserved_19,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 18. "RSTMMON,Reset status for monitor clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
rbitfld.long 0x00 17. "RSTMSMP,Reset status for sampling clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
newline
rbitfld.long 0x00 16. "ENMON,Operating status" "0: Clock monitor is stopped,1: Clock monitor is operating"
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved"
newline
bitfld.long 0x00 1. "INTEN,Interrupt mask bit" "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor"
bitfld.long 0x00 0. "CHKEN,Enable for checking clock oscillation" "0: Stop clock monitor checking,1: Run clock monitor checking"
group.long 0xE84++0x03
line.long 0x00 "RCLKCKMECR,It is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "CLRRES,Reference for clear command signal - RCLKCKMECR.CLRRES" "0: Release clear signal,1: Issue clear signal to clock monitor when clock"
group.long 0xE88++0x03
line.long 0x00 "RCLKCKMLCH,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPH_23_0,The upper limit to judge as expected oscillation"
group.long 0xE8C++0x03
line.long 0x00 "RCLKCKMLCL,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPL_23_0,The lower limit to judge as expected oscillation"
group.long 0xE90++0x03
line.long 0x00 "RCLKCKMCNT,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNT_6_0,Monitoring RCLKCKMCNT.UPDCNT value"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,Monitoring RCLKCKMCNT.MONCNT value"
group.long 0xE94++0x03
line.long 0x00 "RCLKCKMCNTE,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "VLD,Valid bit" "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNTE_6_0,RCLKCKMCNT.UPDCNT value when the first error occurred"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,The counter value of clock monitor when the first error occurred"
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x3800)++0x03
line.long 0x00 "D0WACRA$1,D0WACRAn (n = 0 to 63) is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "D0WACRA_n_31_0,The register specification is described in Sec"
repeat.end
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x3840)++0x03
line.long 0x00 "D0WACRA$1,D0WACRAn (n = 0 to 63) is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "D0WACRA_n_31_0,The register specification is described in Sec"
repeat.end
repeat 16. (strings "32" "33" "34" "35" "36" "37" "38" "39" "40" "41" "42" "43" "44" "45" "46" "47" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x3880)++0x03
line.long 0x00 "D0WACRA$1,D0WACRAn (n = 0 to 63) is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "D0WACRA_n_31_0,The register specification is described in Sec"
repeat.end
repeat 16. (strings "48" "49" "50" "51" "52" "53" "54" "55" "56" "57" "58" "59" "60" "61" "62" "63" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x38C0)++0x03
line.long 0x00 "D0WACRA$1,D0WACRAn (n = 0 to 63) is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "D0WACRA_n_31_0,The register specification is described in Sec"
repeat.end
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x3900)++0x03
line.long 0x00 "D1WACRA$1,D1WACRAn (n = 0 to 63) is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "D1WACRA_n_31_0,The register specification is described in Sec"
repeat.end
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x3940)++0x03
line.long 0x00 "D1WACRA$1,D1WACRAn (n = 0 to 63) is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "D1WACRA_n_31_0,The register specification is described in Sec"
repeat.end
repeat 16. (strings "32" "33" "34" "35" "36" "37" "38" "39" "40" "41" "42" "43" "44" "45" "46" "47" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x3980)++0x03
line.long 0x00 "D1WACRA$1,D1WACRAn (n = 0 to 63) is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "D1WACRA_n_31_0,The register specification is described in Sec"
repeat.end
repeat 16. (strings "48" "49" "50" "51" "52" "53" "54" "55" "56" "57" "58" "59" "60" "61" "62" "63" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x39C0)++0x03
line.long 0x00 "D1WACRA$1,D1WACRAn (n = 0 to 63) is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "D1WACRA_n_31_0,The register specification is described in Sec"
repeat.end
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x3A00)++0x03
line.long 0x00 "D2WACRA$1,D2WACRAn (n = 0 to 63) is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "D2WACRA_n_31_0,The register specification is described in Sec"
repeat.end
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x3A40)++0x03
line.long 0x00 "D2WACRA$1,D2WACRAn (n = 0 to 63) is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "D2WACRA_n_31_0,The register specification is described in Sec"
repeat.end
repeat 16. (strings "32" "33" "34" "35" "36" "37" "38" "39" "40" "41" "42" "43" "44" "45" "46" "47" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x3A80)++0x03
line.long 0x00 "D2WACRA$1,D2WACRAn (n = 0 to 63) is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "D2WACRA_n_31_0,The register specification is described in Sec"
repeat.end
repeat 16. (strings "48" "49" "50" "51" "52" "53" "54" "55" "56" "57" "58" "59" "60" "61" "62" "63" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x3AC0)++0x03
line.long 0x00 "D2WACRA$1,D2WACRAn (n = 0 to 63) is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "D2WACRA_n_31_0,The register specification is described in Sec"
repeat.end
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x3B00)++0x03
line.long 0x00 "D3WACRA$1,D3WACRAn (n = 0 to 63) is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "D3WACRA_n_31_0,The register specification is described in Sec"
repeat.end
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x3B40)++0x03
line.long 0x00 "D3WACRA$1,D3WACRAn (n = 0 to 63) is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "D3WACRA_n_31_0,The register specification is described in Sec"
repeat.end
repeat 16. (strings "32" "33" "34" "35" "36" "37" "38" "39" "40" "41" "42" "43" "44" "45" "46" "47" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x3B80)++0x03
line.long 0x00 "D3WACRA$1,D3WACRAn (n = 0 to 63) is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "D3WACRA_n_31_0,The register specification is described in Sec"
repeat.end
repeat 16. (strings "48" "49" "50" "51" "52" "53" "54" "55" "56" "57" "58" "59" "60" "61" "62" "63" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x3BC0)++0x03
line.long 0x00 "D3WACRA$1,D3WACRAn (n = 0 to 63) is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "D3WACRA_n_31_0,The register specification is described in Sec"
repeat.end
tree.end
tree "CLOCK_PULSE_GENERATOR_CPG_INST_1"
base ad:0xE677E000
group.long 0x00++0x03
line.long 0x00 "PERCKMWPR,It is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "WPRTCT_31_0,The specification is same as 8.2.1 CPG Write Protect Register (CPGWPR)"
group.long 0x04++0x03
line.long 0x00 "PERCKMWPCR,It is a 32-bit readable/writable register"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,The specification is same as 8.2.2 CPG Write Protect Register (CPGWPCR)"
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,The specification is same as 8.2.2 CPG Write Protect Register (CPGWPCR)"
newline
bitfld.long 0x00 0. "WPE,The specification is same as 8.2.2 CPG Write Protect Register (CPGWPCR)" "0,1"
group.long 0x90++0x03
line.long 0x00 "SD0HCKMCSR,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "CHKRES,Check result" "0: Clock oscillates normally,1: Detect unexpected clock oscillation"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 24. "CLRMON,Reference for clear command signal - SD0HCKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued"
rbitfld.long 0x00 19.--23. "Reserved_19,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 18. "RSTMMON,Reset status for monitor clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
rbitfld.long 0x00 17. "RSTMSMP,Reset status for sampling clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
newline
rbitfld.long 0x00 16. "ENMON,Operating status" "0: Clock monitor is stopped,1: Clock monitor is operating"
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved"
newline
bitfld.long 0x00 1. "INTEN,Interrupt mask bit" "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor"
bitfld.long 0x00 0. "CHKEN,Enable for checking clock oscillation" "0: Stop clock monitor checking,1: Run clock monitor checking"
group.long 0x94++0x03
line.long 0x00 "SD0HCKMECR,It is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "CLRRES,Reference for clear command signal - SD0HCKMECR.CLRRES" "0: Release clear signal,1: Issue clear signal to clock monitor when clock"
group.long 0x98++0x03
line.long 0x00 "SD0HCKMLCH,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPH_23_0,The upper limit to judge as expected oscillation"
group.long 0x9C++0x03
line.long 0x00 "SD0HCKMLCL,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPL_23_0,The lower limit to judge as expected oscillation"
group.long 0xA0++0x03
line.long 0x00 "SD0HCKMCNT,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNT_6_0,Monitoring SD0HCKMCNT.UPDCNT value"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,Monitoring SD0HCKMCNT.MONCNT value"
group.long 0xA4++0x03
line.long 0x00 "SD0HCKMCNTE,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "VLD,Valid bit" "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNTE_6_0,SD0HCKMCNT.UPDCNT value when the first error occurred"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,The counter value of clock monitor when the first error occurred"
group.long 0xB0++0x03
line.long 0x00 "SD0CKMCSR,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "CHKRES,Check result" "0: Clock oscillates normally,1: Detect unexpected clock oscillation"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 24. "CLRMON,Reference for clear command signal - SD0CKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued"
rbitfld.long 0x00 19.--23. "Reserved_19,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 18. "RSTMMON,Reset status for monitor clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
rbitfld.long 0x00 17. "RSTMSMP,Reset status for sampling clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
newline
rbitfld.long 0x00 16. "ENMON,Operating status" "0: Clock monitor is stopped,1: Clock monitor is operating"
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved"
newline
bitfld.long 0x00 1. "INTEN,Interrupt mask bit" "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor"
bitfld.long 0x00 0. "CHKEN,Enable for checking clock oscillation" "0: Stop clock monitor checking,1: Run clock monitor checking"
group.long 0xB4++0x03
line.long 0x00 "SD0CKMECR,It is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "CLRRES,Reference for clear command signal - SD0CKMECR.CLRRES" "0: Release clear signal,1: Issue clear signal to clock monitor when clock"
group.long 0xB8++0x03
line.long 0x00 "SD0CKMLCH,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPH_23_0,The upper limit to judge as expected oscillation"
group.long 0xBC++0x03
line.long 0x00 "SD0CKMLCL,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPL_23_0,The lower limit to judge as expected oscillation"
group.long 0xC0++0x03
line.long 0x00 "SD0CKMCNT,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNT_6_0,Monitoring SD0CKMCNT.UPDCNT value"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,Monitoring SD0CKMCNT.MONCNT value"
group.long 0xC4++0x03
line.long 0x00 "SD0CKMCNTE,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "VLD,Valid bit" "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNTE_6_0,SD0CKMCNT.UPDCNT value when the first error occurred"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,The counter value of clock monitor when the first error occurred"
group.long 0x130++0x03
line.long 0x00 "MSOCKMCSR,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "CHKRES,Check result" "0: Clock oscillates normally,1: Detect unexpected clock oscillation"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 24. "CLRMON,Reference for clear command signal - MSOCKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued"
rbitfld.long 0x00 19.--23. "Reserved_19,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 18. "RSTMMON,Reset status for monitor clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
rbitfld.long 0x00 17. "RSTMSMP,Reset status for sampling clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
newline
rbitfld.long 0x00 16. "ENMON,Operating status" "0: Clock monitor is stopped,1: Clock monitor is operating"
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved"
newline
bitfld.long 0x00 1. "INTEN,Interrupt mask bit" "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor"
bitfld.long 0x00 0. "CHKEN,Enable for checking clock oscillation" "0: Stop clock monitor checking,1: Run clock monitor checking"
group.long 0x134++0x03
line.long 0x00 "MSOCKMECR,It is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "CLRRES,Reference for clear command signal - MSOCKMECR.CLRRES" "0: Release clear signal,1: Issue clear signal to clock monitor when clock"
group.long 0x138++0x03
line.long 0x00 "MSOCKMLCH,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPH_23_0,The upper limit to judge as expected oscillation"
group.long 0x13C++0x03
line.long 0x00 "MSOCKMLCL,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPL_23_0,The lower limit to judge as expected oscillation"
group.long 0x140++0x03
line.long 0x00 "MSOCKMCNT,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNT_6_0,Monitoring MSOCKMCNT.UPDCNT value"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,Monitoring MSOCKMCNT.MONCNT value"
group.long 0x144++0x03
line.long 0x00 "MSOCKMCNTE,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "VLD,Valid bit" "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNTE_6_0,MSOCKMCNT.UPDCNT value when the first error occurred"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,The counter value of clock monitor when the first error occurred"
group.long 0x150++0x03
line.long 0x00 "RCLKPERCKMCSR,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "CHKRES,Check result" "0: Clock oscillates normally,1: Detect unexpected clock oscillation"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 24. "CLRMON,Reference for clear command signal - RCLKPERCKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued"
rbitfld.long 0x00 19.--23. "Reserved_19,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 18. "RSTMMON,Reset status for monitor clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
rbitfld.long 0x00 17. "RSTMSMP,Reset status for sampling clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
newline
rbitfld.long 0x00 16. "ENMON,Operating status" "0: Clock monitor is stopped,1: Clock monitor is operating"
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved"
newline
bitfld.long 0x00 1. "INTEN,Interrupt mask bit" "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor"
bitfld.long 0x00 0. "CHKEN,Enable for checking clock oscillation" "0: Stop clock monitor checking,1: Run clock monitor checking"
group.long 0x154++0x03
line.long 0x00 "RCLKPERCKMECR,It is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "CLRRES,Reference for clear command signal - RCLKPERCKMECR.CLRRES" "0: Release clear signal,1: Issue clear signal to clock monitor when clock"
group.long 0x158++0x03
line.long 0x00 "RCLKPERCKMLCH,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPH_23_0,The upper limit to judge as expected oscillation"
group.long 0x15C++0x03
line.long 0x00 "RCLKPERCKMLCL,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPL_23_0,The lower limit to judge as expected oscillation"
group.long 0x160++0x03
line.long 0x00 "RCLKPERCKMCNT,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNT_6_0,Monitoring RCLKPERCKMCNT.UPDCNT value"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,Monitoring RCLKPERCKMCNT.MONCNT value"
group.long 0x164++0x03
line.long 0x00 "RCLKPERCKMCNTE,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "VLD,Valid bit" "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNTE_6_0,RCLKPERCKMCNT.UPDCNT value when the first error occurred"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,The counter value of clock monitor when the first error occurred"
group.long 0x1B0++0x03
line.long 0x00 "CL16MPERCKMCSR,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "CHKRES,Check result" "0: Clock oscillates normally,1: Detect unexpected clock oscillation"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 24. "CLRMON,Reference for clear command signal - CL16MPERCKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued"
rbitfld.long 0x00 19.--23. "Reserved_19,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 18. "RSTMMON,Reset status for monitor clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
rbitfld.long 0x00 17. "RSTMSMP,Reset status for sampling clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
newline
rbitfld.long 0x00 16. "ENMON,Operating status" "0: Clock monitor is stopped,1: Clock monitor is operating"
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved"
newline
bitfld.long 0x00 1. "INTEN,Interrupt mask bit" "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor"
bitfld.long 0x00 0. "CHKEN,Enable for checking clock oscillation" "0: Stop clock monitor checking,1: Run clock monitor checking"
group.long 0x1B4++0x03
line.long 0x00 "CL16MPERCKMECR,It is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "CLRRES,Reference for clear command signal - CL16MPERCKMECR.CLRRES" "0: Release clear signal,1: Issue clear signal to clock monitor when clock"
group.long 0x1B8++0x03
line.long 0x00 "CL16MPERCKMLCH,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPH_23_0,The upper limit to judge as expected oscillation"
group.long 0x1BC++0x03
line.long 0x00 "CL16MPERCKMLCL,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPL_23_0,The lower limit to judge as expected oscillation"
group.long 0x1C0++0x03
line.long 0x00 "CL16MPERCKMCNT,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNT_6_0,Monitoring CL16MPERCKMCNT.UPDCNT value"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,Monitoring CL16MPERCKMCNT.MONCNT value"
group.long 0x1C4++0x03
line.long 0x00 "CL16MPERCKMCNTE,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "VLD,Valid bit" "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNTE_6_0,CL16MPERCKMCNT.UPDCNT value when the first error occurred"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,The counter value of clock monitor when the first error occurred"
group.long 0x1F0++0x03
line.long 0x00 "RPCCKMCSR,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "CHKRES,Check result" "0: Clock oscillates normally,1: Detect unexpected clock oscillation"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 24. "CLRMON,Reference for clear command signal - RPCCKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued"
rbitfld.long 0x00 19.--23. "Reserved_19,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 18. "RSTMMON,Reset status for monitor clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
rbitfld.long 0x00 17. "RSTMSMP,Reset status for sampling clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
newline
rbitfld.long 0x00 16. "ENMON,Operating status" "0: Clock monitor is stopped,1: Clock monitor is operating"
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved"
newline
bitfld.long 0x00 1. "INTEN,Interrupt mask bit" "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor"
bitfld.long 0x00 0. "CHKEN,Enable for checking clock oscillation" "0: Stop clock monitor checking,1: Run clock monitor checking"
group.long 0x1F4++0x03
line.long 0x00 "RPCCKMECR,It is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "CLRRES,Reference for clear command signal - RPCCKMECR.CLRRES" "0: Release clear signal,1: Issue clear signal to clock monitor when clock"
group.long 0x1F8++0x03
line.long 0x00 "RPCCKMLCH,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPH_23_0,The upper limit to judge as expected oscillation"
group.long 0x1FC++0x03
line.long 0x00 "RPCCKMLCL,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPL_23_0,The lower limit to judge as expected oscillation"
group.long 0x200++0x03
line.long 0x00 "RPCCKMCNT,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNT_6_0,Monitoring RPCCKMCNT.UPDCNT value"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,Monitoring RPCCKMCNT.MONCNT value"
group.long 0x204++0x03
line.long 0x00 "RPCCKMCNTE,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "VLD,Valid bit" "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNTE_6_0,RPCCKMCNT.UPDCNT value when the first error occurred"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,The counter value of clock monitor when the first error occurred"
group.long 0x210++0x03
line.long 0x00 "RPCD2CKMCSR,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "CHKRES,Check result" "0: Clock oscillates normally,1: Detect unexpected clock oscillation"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 24. "CLRMON,Reference for clear command signal - RPCD2CKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued"
rbitfld.long 0x00 19.--23. "Reserved_19,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 18. "RSTMMON,Reset status for monitor clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
rbitfld.long 0x00 17. "RSTMSMP,Reset status for sampling clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
newline
rbitfld.long 0x00 16. "ENMON,Operating status" "0: Clock monitor is stopped,1: Clock monitor is operating"
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved"
newline
bitfld.long 0x00 1. "INTEN,Interrupt mask bit" "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor"
bitfld.long 0x00 0. "CHKEN,Enable for checking clock oscillation" "0: Stop clock monitor checking,1: Run clock monitor checking"
group.long 0x214++0x03
line.long 0x00 "RPCD2CKMECR,It is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "CLRRES,Reference for clear command signal - RPCD2CKMECR.CLRRES" "0: Release clear signal,1: Issue clear signal to clock monitor when clock"
group.long 0x218++0x03
line.long 0x00 "RPCD2CKMLCH,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPH_23_0,The upper limit to judge as expected oscillation"
group.long 0x21C++0x03
line.long 0x00 "RPCD2CKMLCL,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPL_23_0,The lower limit to judge as expected oscillation"
group.long 0x220++0x03
line.long 0x00 "RPCD2CKMCNT,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNT_6_0,Monitoring RPCD2CKMCNT.UPDCNT value"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,Monitoring RPCD2CKMCNT.MONCNT value"
group.long 0x224++0x03
line.long 0x00 "RPCD2CKMCNTE,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "VLD,Valid bit" "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNTE_6_0,RPCD2CKMCNT.UPDCNT value when the first error occurred"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,The counter value of clock monitor when the first error occurred"
group.long 0x250++0x03
line.long 0x00 "PERACKMSR,It is a 32-bit readable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved" "0,1"
rbitfld.long 0x00 30. "CHKRES030,SASYNCPERD4" "0,1"
newline
rbitfld.long 0x00 29. "CHKRES029,SASYNCPERD2" "0,1"
rbitfld.long 0x00 28. "CHKRES028,SASYNCPERD1" "0,1"
newline
rbitfld.long 0x00 27. "CHKRES027,CBFUSA" "0,1"
rbitfld.long 0x00 26. "Reserved_26,Reserved" "0,1"
newline
rbitfld.long 0x00 25. "CHKRES025,S0D24_PER" "0,1"
rbitfld.long 0x00 24. "Reserved_24,Reserved" "0,1"
newline
rbitfld.long 0x00 23. "CHKRES023,S0D12_PER" "0,1"
rbitfld.long 0x00 22. "CHKRES022,S0D6_PER" "0,1"
newline
rbitfld.long 0x00 21. "Reserved_21,Reserved" "0,1"
rbitfld.long 0x00 20. "CHKRES020,S0D3_PER" "0,1"
newline
rbitfld.long 0x00 19. "Reserved_19,Reserved" "0,1"
rbitfld.long 0x00 18. "Reserved_18,Reserved" "0,1"
newline
rbitfld.long 0x00 17. "Reserved_17,Reserved" "0,1"
rbitfld.long 0x00 16. "CHKRES016,RPCD2" "0,1"
newline
rbitfld.long 0x00 15. "CHKRES015,RPC" "0,1"
rbitfld.long 0x00 14. "Reserved_14,Reserved" "0,1"
newline
rbitfld.long 0x00 13. "CHKRES013,CL16M_PER" "0,1"
rbitfld.long 0x00 12. "Reserved_12,Reserved" "0,1"
newline
rbitfld.long 0x00 11. "Reserved_11,Reserved" "0,1"
rbitfld.long 0x00 10. "CHKRES010,RCLK" "0,1"
newline
rbitfld.long 0x00 9. "CHKRES009,MSO" "0,1"
rbitfld.long 0x00 8. "Reserved_8,Reserved" "0,1"
newline
rbitfld.long 0x00 7. "Reserved_7,Reserved" "0,1"
rbitfld.long 0x00 6. "Reserved_6,Reserved" "0,1"
newline
rbitfld.long 0x00 5. "CHKRES005,SD0" "0,1"
rbitfld.long 0x00 4. "CHKRES004,SD0H" "0,1"
newline
rbitfld.long 0x00 3. "Reserved_3,Reserved" "0,1"
rbitfld.long 0x00 2. "Reserved_2,Reserved" "0,1"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved" "0,1"
rbitfld.long 0x00 0. "Reserved_0,Reserved" "0,1"
group.long 0x280++0x03
line.long 0x00 "S0D2PERCKMCSR,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "CHKRES,Check result" "0: Clock oscillates normally,1: Detect unexpected clock oscillation"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 24. "CLRMON,Reference for clear command signal - S0D2PERCKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued"
rbitfld.long 0x00 19.--23. "Reserved_19,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 18. "RSTMMON,Reset status for monitor clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
rbitfld.long 0x00 17. "RSTMSMP,Reset status for sampling clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
newline
rbitfld.long 0x00 16. "ENMON,Operating status" "0: Clock monitor is stopped,1: Clock monitor is operating"
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved"
newline
bitfld.long 0x00 1. "INTEN,Interrupt mask bit" "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor"
bitfld.long 0x00 0. "CHKEN,Enable for checking clock oscillation" "0: Stop clock monitor checking,1: Run clock monitor checking"
group.long 0x284++0x03
line.long 0x00 "S0D2PERCKMECR,It is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "CLRRES,Reference for clear command signal - S0D2PERCKMECR.CLRRES" "0: Release clear signal,1: Issue clear signal to clock monitor when clock"
group.long 0x288++0x03
line.long 0x00 "S0D2PERCKMLCH,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPH_23_0,The upper limit to judge as expected oscillation"
group.long 0x28C++0x03
line.long 0x00 "S0D2PERCKMLCL,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPL_23_0,The lower limit to judge as expected oscillation"
group.long 0x290++0x03
line.long 0x00 "S0D2PERCKMCNT,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNT_6_0,Monitoring S0D2PERCKMCNT.UPDCNT value"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,Monitoring S0D2PERCKMCNT.MONCNT value"
group.long 0x294++0x03
line.long 0x00 "S0D2PERCKMCNTE,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "VLD,Valid bit" "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNTE_6_0,S0D2PERCKMCNT.UPDCNT value when the first error occurred"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,The counter value of clock monitor when the first error occurred"
group.long 0x2A0++0x03
line.long 0x00 "S0D3PERCKMCSR,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "CHKRES,Check result" "0: Clock oscillates normally,1: Detect unexpected clock oscillation"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 24. "CLRMON,Reference for clear command signal - S0D3PERCKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued"
rbitfld.long 0x00 19.--23. "Reserved_19,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 18. "RSTMMON,Reset status for monitor clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
rbitfld.long 0x00 17. "RSTMSMP,Reset status for sampling clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
newline
rbitfld.long 0x00 16. "ENMON,Operating status" "0: Clock monitor is stopped,1: Clock monitor is operating"
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved"
newline
bitfld.long 0x00 1. "INTEN,Interrupt mask bit" "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor"
bitfld.long 0x00 0. "CHKEN,Enable for checking clock oscillation" "0: Stop clock monitor checking,1: Run clock monitor checking"
group.long 0x2A4++0x03
line.long 0x00 "S0D3PERCKMECR,It is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "CLRRES,Reference for clear command signal - S0D3PERCKMECR.CLRRES" "0: Release clear signal,1: Issue clear signal to clock monitor when clock"
group.long 0x2A8++0x03
line.long 0x00 "S0D3PERCKMLCH,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPH_23_0,The upper limit to judge as expected oscillation"
group.long 0x2AC++0x03
line.long 0x00 "S0D3PERCKMLCL,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPL_23_0,The lower limit to judge as expected oscillation"
group.long 0x2B0++0x03
line.long 0x00 "S0D3PERCKMCNT,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNT_6_0,Monitoring S0D3PERCKMCNT.UPDCNT value"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,Monitoring S0D3PERCKMCNT.MONCNT value"
group.long 0x2B4++0x03
line.long 0x00 "S0D3PERCKMCNTE,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "VLD,Valid bit" "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNTE_6_0,S0D3PERCKMCNT.UPDCNT value when the first error occurred"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,The counter value of clock monitor when the first error occurred"
group.long 0x2C0++0x03
line.long 0x00 "S0D4PERCKMCSR,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "CHKRES,Check result" "0: Clock oscillates normally,1: Detect unexpected clock oscillation"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 24. "CLRMON,Reference for clear command signal - S0D4PERCKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued"
rbitfld.long 0x00 19.--23. "Reserved_19,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 18. "RSTMMON,Reset status for monitor clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
rbitfld.long 0x00 17. "RSTMSMP,Reset status for sampling clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
newline
rbitfld.long 0x00 16. "ENMON,Operating status" "0: Clock monitor is stopped,1: Clock monitor is operating"
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved"
newline
bitfld.long 0x00 1. "INTEN,Interrupt mask bit" "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor"
bitfld.long 0x00 0. "CHKEN,Enable for checking clock oscillation" "0: Stop clock monitor checking,1: Run clock monitor checking"
group.long 0x2C4++0x03
line.long 0x00 "S0D4PERCKMECR,It is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "CLRRES,Reference for clear command signal - S0D4PERCKMECR.CLRRES" "0: Release clear signal,1: Issue clear signal to clock monitor when clock"
group.long 0x2C8++0x03
line.long 0x00 "S0D4PERCKMLCH,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPH_23_0,The upper limit to judge as expected oscillation"
group.long 0x2CC++0x03
line.long 0x00 "S0D4PERCKMLCL,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPL_23_0,The lower limit to judge as expected oscillation"
group.long 0x2D0++0x03
line.long 0x00 "S0D4PERCKMCNT,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNT_6_0,Monitoring S0D4PERCKMCNT.UPDCNT value"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,Monitoring S0D4PERCKMCNT.MONCNT value"
group.long 0x2D4++0x03
line.long 0x00 "S0D4PERCKMCNTE,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "VLD,Valid bit" "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNTE_6_0,S0D4PERCKMCNT.UPDCNT value when the first error occurred"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,The counter value of clock monitor when the first error occurred"
group.long 0x2E0++0x03
line.long 0x00 "S0D6PERCKMCSR,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "CHKRES,Check result" "0: Clock oscillates normally,1: Detect unexpected clock oscillation"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 24. "CLRMON,Reference for clear command signal - S0D6PERCKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued"
rbitfld.long 0x00 19.--23. "Reserved_19,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 18. "RSTMMON,Reset status for monitor clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
rbitfld.long 0x00 17. "RSTMSMP,Reset status for sampling clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
newline
rbitfld.long 0x00 16. "ENMON,Operating status" "0: Clock monitor is stopped,1: Clock monitor is operating"
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved"
newline
bitfld.long 0x00 1. "INTEN,Interrupt mask bit" "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor"
bitfld.long 0x00 0. "CHKEN,Enable for checking clock oscillation" "0: Stop clock monitor checking,1: Run clock monitor checking"
group.long 0x2E4++0x03
line.long 0x00 "S0D6PERCKMECR,It is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "CLRRES,Reference for clear command signal - S0D6PERCKMECR.CLRRES" "0: Release clear signal,1: Issue clear signal to clock monitor when clock"
group.long 0x2E8++0x03
line.long 0x00 "S0D6PERCKMLCH,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPH_23_0,The upper limit to judge as expected oscillation"
group.long 0x2EC++0x03
line.long 0x00 "S0D6PERCKMLCL,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPL_23_0,The lower limit to judge as expected oscillation"
group.long 0x2F0++0x03
line.long 0x00 "S0D6PERCKMCNT,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNT_6_0,Monitoring S0D6PERCKMCNT.UPDCNT value"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,Monitoring S0D6PERCKMCNT.MONCNT value"
group.long 0x2F4++0x03
line.long 0x00 "S0D6PERCKMCNTE,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "VLD,Valid bit" "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNTE_6_0,S0D6PERCKMCNT.UPDCNT value when the first error occurred"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,The counter value of clock monitor when the first error occurred"
group.long 0x300++0x03
line.long 0x00 "S0D12PERCKMCSR,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "CHKRES,Check result" "0: Clock oscillates normally,1: Detect unexpected clock oscillation"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 24. "CLRMON,Reference for clear command signal - S0D12PERCKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued"
rbitfld.long 0x00 19.--23. "Reserved_19,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 18. "RSTMMON,Reset status for monitor clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
rbitfld.long 0x00 17. "RSTMSMP,Reset status for sampling clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
newline
rbitfld.long 0x00 16. "ENMON,Operating status" "0: Clock monitor is stopped,1: Clock monitor is operating"
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved"
newline
bitfld.long 0x00 1. "INTEN,Interrupt mask bit" "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor"
bitfld.long 0x00 0. "CHKEN,Enable for checking clock oscillation" "0: Stop clock monitor checking,1: Run clock monitor checking"
group.long 0x304++0x03
line.long 0x00 "S0D12PERCKMECR,It is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "CLRRES,Reference for clear command signal - S0D12PERCKMECR.CLRRES" "0: Release clear signal,1: Issue clear signal to clock monitor when clock"
group.long 0x308++0x03
line.long 0x00 "S0D12PERCKMLCH,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPH_23_0,The upper limit to judge as expected oscillation"
group.long 0x30C++0x03
line.long 0x00 "S0D12PERCKMLCL,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPL_23_0,The lower limit to judge as expected oscillation"
group.long 0x310++0x03
line.long 0x00 "S0D12PERCKMCNT,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNT_6_0,Monitoring S0D12PERCKMCNT.UPDCNT value"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,Monitoring S0D12PERCKMCNT.MONCNT value"
group.long 0x314++0x03
line.long 0x00 "S0D12PERCKMCNTE,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "VLD,Valid bit" "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNTE_6_0,S0D12PERCKMCNT.UPDCNT value when the first error occurred"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,The counter value of clock monitor when the first error occurred"
group.long 0x340++0x03
line.long 0x00 "S0D24PERCKMCSR,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "CHKRES,Check result" "0: Clock oscillates normally,1: Detect unexpected clock oscillation"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 24. "CLRMON,Reference for clear command signal - S0D24PERCKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued"
rbitfld.long 0x00 19.--23. "Reserved_19,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 18. "RSTMMON,Reset status for monitor clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
rbitfld.long 0x00 17. "RSTMSMP,Reset status for sampling clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
newline
rbitfld.long 0x00 16. "ENMON,Operating status" "0: Clock monitor is stopped,1: Clock monitor is operating"
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved"
newline
bitfld.long 0x00 1. "INTEN,Interrupt mask bit" "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor"
bitfld.long 0x00 0. "CHKEN,Enable for checking clock oscillation" "0: Stop clock monitor checking,1: Run clock monitor checking"
group.long 0x344++0x03
line.long 0x00 "S0D24PERCKMECR,It is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "CLRRES,Reference for clear command signal - S0D24PERCKMECR.CLRRES" "0: Release clear signal,1: Issue clear signal to clock monitor when clock"
group.long 0x348++0x03
line.long 0x00 "S0D24PERCKMLCH,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPH_23_0,The upper limit to judge as expected oscillation"
group.long 0x34C++0x03
line.long 0x00 "S0D24PERCKMLCL,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPL_23_0,The lower limit to judge as expected oscillation"
group.long 0x350++0x03
line.long 0x00 "S0D24PERCKMCNT,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNT_6_0,Monitoring S0D24PERCKMCNT.UPDCNT value"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,Monitoring S0D24PERCKMCNT.MONCNT value"
group.long 0x354++0x03
line.long 0x00 "S0D24PERCKMCNTE,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "VLD,Valid bit" "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNTE_6_0,S0D24PERCKMCNT.UPDCNT value when the first error occurred"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,The counter value of clock monitor when the first error occurred"
group.long 0x380++0x03
line.long 0x00 "CBFUSAPERCKMCSR,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "CHKRES,Check result" "0: Clock oscillates normally,1: Detect unexpected clock oscillation"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 24. "CLRMON,Reference for clear command signal - CBFUSAPERCKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued"
rbitfld.long 0x00 19.--23. "Reserved_19,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 18. "RSTMMON,Reset status for monitor clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
rbitfld.long 0x00 17. "RSTMSMP,Reset status for sampling clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
newline
rbitfld.long 0x00 16. "ENMON,Operating status" "0: Clock monitor is stopped,1: Clock monitor is operating"
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved"
newline
bitfld.long 0x00 1. "INTEN,Interrupt mask bit" "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor"
bitfld.long 0x00 0. "CHKEN,Enable for checking clock oscillation" "0: Stop clock monitor checking,1: Run clock monitor checking"
group.long 0x384++0x03
line.long 0x00 "CBFUSAPERCKMECR,It is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "CLRRES,Reference for clear command signal - CBFUSAPERCKMECR.CLRRES" "0: Release clear signal,1: Issue clear signal to clock monitor when clock"
group.long 0x388++0x03
line.long 0x00 "CBFUSAPERCKMLCH,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPH_23_0,The upper limit to judge as expected oscillation"
group.long 0x38C++0x03
line.long 0x00 "CBFUSAPERCKMLCL,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPL_23_0,The lower limit to judge as expected oscillation"
group.long 0x390++0x03
line.long 0x00 "CBFUSAPERCKMCNT,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNT_6_0,Monitoring CBFUSAPERCKMCNT.UPDCNT value"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,Monitoring CBFUSAPERCKMCNT.MONCNT value"
group.long 0x394++0x03
line.long 0x00 "CBFUSAPERCKMCNTE,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "VLD,Valid bit" "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNTE_6_0,CBFUSAPERCKMCNT.UPDCNT value when the first error occurred"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,The counter value of clock monitor when the first error occurred"
group.long 0x3A0++0x03
line.long 0x00 "SASYNCPERD1CKMCSR,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "CHKRES,Check result" "0: Clock oscillates normally,1: Detect unexpected clock oscillation"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 24. "CLRMON,Reference for clear command signal - SASYNCPERD1CKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued"
rbitfld.long 0x00 19.--23. "Reserved_19,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 18. "RSTMMON,Reset status for monitor clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
rbitfld.long 0x00 17. "RSTMSMP,Reset status for sampling clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
newline
rbitfld.long 0x00 16. "ENMON,Operating status" "0: Clock monitor is stopped,1: Clock monitor is operating"
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved"
newline
bitfld.long 0x00 1. "INTEN,Interrupt mask bit" "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor"
bitfld.long 0x00 0. "CHKEN,Enable for checking clock oscillation" "0: Stop clock monitor checking,1: Run clock monitor checking"
group.long 0x3A4++0x03
line.long 0x00 "SASYNCPERD1CKMECR,It is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "CLRRES,Reference for clear command signal - SASYNCPERD1CKMECR.CLRRES" "0: Release clear signal,1: Issue clear signal to clock monitor when clock"
group.long 0x3A8++0x03
line.long 0x00 "SASYNCPERD1CKMLCH,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPH_23_0,The upper limit to judge as expected oscillation"
group.long 0x3AC++0x03
line.long 0x00 "SASYNCPERD1CKMLCL,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPL_23_0,The lower limit to judge as expected oscillation"
group.long 0x3B0++0x03
line.long 0x00 "SASYNCPERD1CKMCNT,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNT_6_0,Monitoring SASYNCPERD1CKMCNT.UPDCNT value"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,Monitoring SASYNCPERD1CKMCNT.MONCNT value"
group.long 0x3B4++0x03
line.long 0x00 "SASYNCPERD1CKMCNTE,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "VLD,Valid bit" "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNTE_6_0,SASYNCPERD1CKMCNT.UPDCNT value when the first error occurred"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,The counter value of clock monitor when the first error occurred"
group.long 0x3C0++0x03
line.long 0x00 "SASYNCPERD2CKMCSR,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "CHKRES,Check result" "0: Clock oscillates normally,1: Detect unexpected clock oscillation"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 24. "CLRMON,Reference for clear command signal - SASYNCPERD2CKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued"
rbitfld.long 0x00 19.--23. "Reserved_19,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 18. "RSTMMON,Reset status for monitor clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
rbitfld.long 0x00 17. "RSTMSMP,Reset status for sampling clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
newline
rbitfld.long 0x00 16. "ENMON,Operating status" "0: Clock monitor is stopped,1: Clock monitor is operating"
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved"
newline
bitfld.long 0x00 1. "INTEN,Interrupt mask bit" "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor"
bitfld.long 0x00 0. "CHKEN,Enable for checking clock oscillation" "0: Stop clock monitor checking,1: Run clock monitor checking"
group.long 0x3C4++0x03
line.long 0x00 "SASYNCPERD2CKMECR,It is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "CLRRES,Reference for clear command signal - SASYNCPERD2CKMECR.CLRRES" "0: Release clear signal,1: Issue clear signal to clock monitor when clock"
group.long 0x3C8++0x03
line.long 0x00 "SASYNCPERD2CKMLCH,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPH_23_0,The upper limit to judge as expected oscillation"
group.long 0x3CC++0x03
line.long 0x00 "SASYNCPERD2CKMLCL,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPL_23_0,The lower limit to judge as expected oscillation"
group.long 0x3D0++0x03
line.long 0x00 "SASYNCPERD2CKMCNT,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNT_6_0,Monitoring SASYNCPERD2CKMCNT.UPDCNT value"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,Monitoring SASYNCPERD2CKMCNT.MONCNT value"
group.long 0x3D4++0x03
line.long 0x00 "SASYNCPERD2CKMCNTE,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "VLD,Valid bit" "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNTE_6_0,SASYNCPERD2CKMCNT.UPDCNT value when the first error occurred"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,The counter value of clock monitor when the first error occurred"
group.long 0x3E0++0x03
line.long 0x00 "SASYNCPERD4CKMCSR,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "CHKRES,Check result" "0: Clock oscillates normally,1: Detect unexpected clock oscillation"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 24. "CLRMON,Reference for clear command signal - SASYNCPERD4CKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued"
rbitfld.long 0x00 19.--23. "Reserved_19,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 18. "RSTMMON,Reset status for monitor clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
rbitfld.long 0x00 17. "RSTMSMP,Reset status for sampling clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
newline
rbitfld.long 0x00 16. "ENMON,Operating status" "0: Clock monitor is stopped,1: Clock monitor is operating"
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved"
newline
bitfld.long 0x00 1. "INTEN,Interrupt mask bit" "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor"
bitfld.long 0x00 0. "CHKEN,Enable for checking clock oscillation" "0: Stop clock monitor checking,1: Run clock monitor checking"
group.long 0x3E4++0x03
line.long 0x00 "SASYNCPERD4CKMECR,It is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "CLRRES,Reference for clear command signal - SASYNCPERD4CKMECR.CLRRES" "0: Release clear signal,1: Issue clear signal to clock monitor when clock"
group.long 0x3E8++0x03
line.long 0x00 "SASYNCPERD4CKMLCH,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPH_23_0,The upper limit to judge as expected oscillation"
group.long 0x3EC++0x03
line.long 0x00 "SASYNCPERD4CKMLCL,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPL_23_0,The lower limit to judge as expected oscillation"
group.long 0x3F0++0x03
line.long 0x00 "SASYNCPERD4CKMCNT,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNT_6_0,Monitoring SASYNCPERD4CKMCNT.UPDCNT value"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,Monitoring SASYNCPERD4CKMCNT.MONCNT value"
group.long 0x3F4++0x03
line.long 0x00 "SASYNCPERD4CKMCNTE,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "VLD,Valid bit" "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNTE_6_0,SASYNCPERD4CKMCNT.UPDCNT value when the first error occurred"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,The counter value of clock monitor when the first error occurred"
tree.end
tree "CLOCK_PULSE_GENERATOR_CPG_INST_2"
base ad:0xE644E000
group.long 0x00++0x03
line.long 0x00 "HSCCKMWPR,It is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "WPRTCT_31_0,The specification is same as 8.2.1 CPG Write Protect Register (CPGWPR)"
group.long 0x04++0x03
line.long 0x00 "HSCCKMWPCR,It is a 32-bit readable/writable register"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,The specification is same as 8.2.2 CPG Write Protect Register (CPGWPCR)"
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,The specification is same as 8.2.2 CPG Write Protect Register (CPGWPCR)"
newline
bitfld.long 0x00 0. "WPE,The specification is same as 8.2.2 CPG Write Protect Register (CPGWPCR)" "0,1"
group.long 0xB0++0x03
line.long 0x00 "RCLKHSCCKMCSR,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "CHKRES,Check result" "0: Clock oscillates normally,1: Detect unexpected clock oscillation"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 24. "CLRMON,Reference for clear command signal - RCLKHSCCKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued"
rbitfld.long 0x00 19.--23. "Reserved_19,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 18. "RSTMMON,Reset status for monitor clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
rbitfld.long 0x00 17. "RSTMSMP,Reset status for sampling clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
newline
rbitfld.long 0x00 16. "ENMON,Operating status" "0: Clock monitor is stopped,1: Clock monitor is operating"
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved"
newline
bitfld.long 0x00 1. "INTEN,Interrupt mask bit" "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor"
bitfld.long 0x00 0. "CHKEN,Enable for checking clock oscillation" "0: Stop clock monitor checking,1: Run clock monitor checking"
group.long 0xB4++0x03
line.long 0x00 "RCLKHSCCKMECR,It is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "CLRRES,Reference for clear command signal - RCLKHSCCKMECR.CLRRES" "0: Release clear signal,1: Issue clear signal to clock monitor when clock"
group.long 0xB8++0x03
line.long 0x00 "RCLKHSCCKMLCH,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPH_23_0,The upper limit to judge as expected oscillation"
group.long 0xBC++0x03
line.long 0x00 "RCLKHSCCKMLCL,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPL_23_0,The lower limit to judge as expected oscillation"
group.long 0xC0++0x03
line.long 0x00 "RCLKHSCCKMCNT,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNT_6_0,Monitoring RCLKHSCCKMCNT.UPDCNT value"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,Monitoring RCLKHSCCKMCNT.MONCNT value"
group.long 0xC4++0x03
line.long 0x00 "RCLKHSCCKMCNTE,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "VLD,Valid bit" "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNTE_6_0,RCLKHSCCKMCNT.UPDCNT value when the first error occurred"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,The counter value of clock monitor when the first error occurred"
group.long 0x130++0x03
line.long 0x00 "CL16MHSCCKMCSR,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "CHKRES,Check result" "0: Clock oscillates normally,1: Detect unexpected clock oscillation"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 24. "CLRMON,Reference for clear command signal - CL16MHSCCKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued"
rbitfld.long 0x00 19.--23. "Reserved_19,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 18. "RSTMMON,Reset status for monitor clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
rbitfld.long 0x00 17. "RSTMSMP,Reset status for sampling clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
newline
rbitfld.long 0x00 16. "ENMON,Operating status" "0: Clock monitor is stopped,1: Clock monitor is operating"
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved"
newline
bitfld.long 0x00 1. "INTEN,Interrupt mask bit" "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor"
bitfld.long 0x00 0. "CHKEN,Enable for checking clock oscillation" "0: Stop clock monitor checking,1: Run clock monitor checking"
group.long 0x134++0x03
line.long 0x00 "CL16MHSCCKMECR,It is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "CLRRES,Reference for clear command signal - CL16MHSCCKMECR.CLRRES" "0: Release clear signal,1: Issue clear signal to clock monitor when clock"
group.long 0x138++0x03
line.long 0x00 "CL16MHSCCKMLCH,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPH_23_0,The upper limit to judge as expected oscillation"
group.long 0x13C++0x03
line.long 0x00 "CL16MHSCCKMLCL,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPL_23_0,The lower limit to judge as expected oscillation"
group.long 0x140++0x03
line.long 0x00 "CL16MHSCCKMCNT,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNT_6_0,Monitoring CL16MHSCCKMCNT.UPDCNT value"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,Monitoring CL16MHSCCKMCNT.MONCNT value"
group.long 0x144++0x03
line.long 0x00 "CL16MHSCCKMCNTE,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "VLD,Valid bit" "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNTE_6_0,CL16MHSCCKMCNT.UPDCNT value when the first error occurred"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,The counter value of clock monitor when the first error occurred"
group.long 0x14C++0x03
line.long 0x00 "HSCACKMSR,HSCACKMSR is a 32-bit readable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved" "0,1"
rbitfld.long 0x00 30. "Reserved_30,Reserved" "0,1"
newline
rbitfld.long 0x00 29. "Reserved_29,Reserved" "0,1"
rbitfld.long 0x00 28. "Reserved_28,Reserved" "0,1"
newline
rbitfld.long 0x00 27. "Reserved_27,Reserved" "0,1"
rbitfld.long 0x00 26. "Reserved_26,Reserved" "0,1"
newline
rbitfld.long 0x00 25. "Reserved_25,Reserved" "0,1"
rbitfld.long 0x00 24. "Reserved_24,Reserved" "0,1"
newline
rbitfld.long 0x00 23. "Reserved_23,Reserved" "0,1"
rbitfld.long 0x00 22. "CHKRES022,DBGSOC_HSC" "0,1"
newline
rbitfld.long 0x00 21. "CHKRES021,CBFUSA" "0,1"
rbitfld.long 0x00 20. "CHKRES020,RSW2" "0,1"
newline
rbitfld.long 0x00 19. "Reserved_19,Reserved" "0,1"
rbitfld.long 0x00 18. "Reserved_18,Reserved" "0,1"
newline
rbitfld.long 0x00 17. "Reserved_17,Reserved" "0,1"
rbitfld.long 0x00 16. "Reserved_16,Reserved" "0,1"
newline
rbitfld.long 0x00 15. "CHKRES015,S0D12_HSC" "0,1"
rbitfld.long 0x00 14. "CHKRES014,S0D6_HSC" "0,1"
newline
rbitfld.long 0x00 13. "Reserved_13,Reserved" "0,1"
rbitfld.long 0x00 12. "Reserved_12,Reserved" "0,1"
newline
rbitfld.long 0x00 11. "CHKRES011,S0D4_HSC" "0,1"
rbitfld.long 0x00 10. "CHKRES010,S0D3_HSC" "0,1"
newline
rbitfld.long 0x00 9. "CHKRES009,S0D2_HSC" "0,1"
rbitfld.long 0x00 8. "Reserved_8,Reserved" "0,1"
newline
rbitfld.long 0x00 7. "CHKRES007,CL16M_HSC" "0,1"
rbitfld.long 0x00 6. "Reserved_6,Reserved" "0,1"
newline
rbitfld.long 0x00 5. "CHKRES005,RCLK" "0,1"
rbitfld.long 0x00 4. "Reserved_4,Reserved" "0,1"
newline
rbitfld.long 0x00 3. "Reserved_3,Reserved" "0,1"
rbitfld.long 0x00 2. "Reserved_2,Reserved" "0,1"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved" "0,1"
rbitfld.long 0x00 0. "Reserved_0,Reserved" "0,1"
group.long 0x170++0x03
line.long 0x00 "S0D2HSCCKMCSR,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "CHKRES,Check result" "0: Clock oscillates normally,1: Detect unexpected clock oscillation"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 24. "CLRMON,Reference for clear command signal - S0D2HSCCKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued"
rbitfld.long 0x00 19.--23. "Reserved_19,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 18. "RSTMMON,Reset status for monitor clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
rbitfld.long 0x00 17. "RSTMSMP,Reset status for sampling clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
newline
rbitfld.long 0x00 16. "ENMON,Operating status" "0: Clock monitor is stopped,1: Clock monitor is operating"
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved"
newline
bitfld.long 0x00 1. "INTEN,Interrupt mask bit" "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor"
bitfld.long 0x00 0. "CHKEN,Enable for checking clock oscillation" "0: Stop clock monitor checking,1: Run clock monitor checking"
group.long 0x174++0x03
line.long 0x00 "S0D2HSCCKMECR,It is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "CLRRES,Reference for clear command signal - S0D2HSCCKMECR.CLRRES" "0: Release clear signal,1: Issue clear signal to clock monitor when clock"
group.long 0x178++0x03
line.long 0x00 "S0D2HSCCKMLCH,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPH_23_0,The upper limit to judge as expected oscillation"
group.long 0x17C++0x03
line.long 0x00 "S0D2HSCCKMLCL,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPL_23_0,The lower limit to judge as expected oscillation"
group.long 0x180++0x03
line.long 0x00 "S0D2HSCCKMCNT,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNT_6_0,Monitoring S0D2HSCCKMCNT.UPDCNT value"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,Monitoring S0D2HSCCKMCNT.MONCNT value"
group.long 0x184++0x03
line.long 0x00 "S0D2HSCCKMCNTE,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "VLD,Valid bit" "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNTE_6_0,S0D2HSCCKMCNT.UPDCNT value when the first error occurred"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,The counter value of clock monitor when the first error occurred"
group.long 0x190++0x03
line.long 0x00 "S0D3HSCCKMCSR,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "CHKRES,Check result" "0: Clock oscillates normally,1: Detect unexpected clock oscillation"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 24. "CLRMON,Reference for clear command signal - S0D3HSCCKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued"
rbitfld.long 0x00 19.--23. "Reserved_19,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 18. "RSTMMON,Reset status for monitor clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
rbitfld.long 0x00 17. "RSTMSMP,Reset status for sampling clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
newline
rbitfld.long 0x00 16. "ENMON,Operating status" "0: Clock monitor is stopped,1: Clock monitor is operating"
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved"
newline
bitfld.long 0x00 1. "INTEN,Interrupt mask bit" "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor"
bitfld.long 0x00 0. "CHKEN,Enable for checking clock oscillation" "0: Stop clock monitor checking,1: Run clock monitor checking"
group.long 0x194++0x03
line.long 0x00 "S0D3HSCCKMECR,It is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
bitfld.long 0x00 0. "CLRRES,Clear command signal for check result" "0: Release clear signal,1: Issue clear signal to clock monitor"
group.long 0x198++0x03
line.long 0x00 "S0D3HSCCKMLCH,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPH_23_0,The upper limit to judge as expected oscillation"
group.long 0x19C++0x03
line.long 0x00 "S0D3HSCCKMLCL,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPL_23_0,The lower limit to judge as expected oscillation"
group.long 0x1A0++0x03
line.long 0x00 "S0D3HSCCKMCNT,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNT_6_0,The number of times of updating MONCNT"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNT_23_0,The counter value of clock monitor in the latest sampling period"
group.long 0x1A4++0x03
line.long 0x00 "S0D3HSCCKMCNTE,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "VLD,Valid bit" "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNTE_6_0,S0D3HSCCKMCNT.UPDCNT value when the first error occurred"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,The counter value of clock monitor when the first error occurred"
group.long 0x1B0++0x03
line.long 0x00 "S0D4HSCCKMCSR,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "CHKRES,Check result" "0: Clock oscillates normally,1: Detect unexpected clock oscillation"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 24. "CLRMON,Reference for clear command signal - S0D4HSCCKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued"
rbitfld.long 0x00 19.--23. "Reserved_19,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 18. "RSTMMON,Reset status for monitor clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
rbitfld.long 0x00 17. "RSTMSMP,Reset status for sampling clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
newline
rbitfld.long 0x00 16. "ENMON,Operating status" "0: Clock monitor is stopped,1: Clock monitor is operating"
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved"
newline
bitfld.long 0x00 1. "INTEN,Interrupt mask bit" "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor"
bitfld.long 0x00 0. "CHKEN,Enable for checking clock oscillation" "0: Stop clock monitor checking,1: Run clock monitor checking"
group.long 0x1B4++0x03
line.long 0x00 "S0D4HSCCKMECR,It is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "CLRRES,Reference for clear command signal - S0D4HSCCKMECR.CLRRES" "0: Release clear signal,1: Issue clear signal to clock monitor when clock"
group.long 0x1B8++0x03
line.long 0x00 "S0D4HSCCKMLCH,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPH_23_0,The upper limit to judge as expected oscillation"
group.long 0x1BC++0x03
line.long 0x00 "S0D4HSCCKMLCL,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPL_23_0,The lower limit to judge as expected oscillation"
group.long 0x1C0++0x03
line.long 0x00 "S0D4HSCCKMCNT,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNT_6_0,Monitoring S0D4HSCCKMCNT.UPDCNT value"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,Monitoring S0D4HSCCKMCNT.MONCNT value"
group.long 0x1C4++0x03
line.long 0x00 "S0D4HSCCKMCNTE,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "VLD,Valid bit" "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNTE_6_0,S0D4HSCCKMCNT.UPDCNT value when the first error occurred"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,The counter value of clock monitor when the first error occurred"
group.long 0x210++0x03
line.long 0x00 "S0D6HSCCKMCSR,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "CHKRES,Check result" "0: Clock oscillates normally,1: Detect unexpected clock oscillation"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 24. "CLRMON,Reference for clear command signal - S0D6HSCCKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued"
rbitfld.long 0x00 19.--23. "Reserved_19,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 18. "RSTMMON,Reset status for monitor clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
rbitfld.long 0x00 17. "RSTMSMP,Reset status for sampling clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
newline
rbitfld.long 0x00 16. "ENMON,Operating status" "0: Clock monitor is stopped,1: Clock monitor is operating"
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved"
newline
bitfld.long 0x00 1. "INTEN,Interrupt mask bit" "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor"
bitfld.long 0x00 0. "CHKEN,Enable for checking clock oscillation" "0: Stop clock monitor checking,1: Run clock monitor checking"
group.long 0x214++0x03
line.long 0x00 "S0D6HSCCKMECR,It is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
bitfld.long 0x00 0. "CLRRES,Clear command signal for check result" "0: Release clear signal,1: Issue clear signal to clock monitor"
group.long 0x218++0x03
line.long 0x00 "S0D6HSCCKMLCH,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPH_23_0,The upper limit to judge as expected oscillation"
group.long 0x21C++0x03
line.long 0x00 "S0D6HSCCKMLCL,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPL_23_0,The lower limit to judge as expected oscillation"
group.long 0x220++0x03
line.long 0x00 "S0D6HSCCKMCNT,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNT_6_0,The number of times of updating MONCNT"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNT_23_0,The counter value of clock monitor in the latest sampling period"
group.long 0x224++0x03
line.long 0x00 "S0D6HSCCKMCNTE,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "VLD,Valid bit" "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNTE_6_0,S0D6HSCCKMCNT.UPDCNT value when the first error occurred"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,The counter value of clock monitor when the first error occurred"
group.long 0x230++0x03
line.long 0x00 "S0D12HSCCKMCSR,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "CHKRES,Check result" "0: Clock oscillates normally,1: Detect unexpected clock oscillation"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 24. "CLRMON,Reference for clear command signal - S0D12HSCCKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued"
rbitfld.long 0x00 19.--23. "Reserved_19,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 18. "RSTMMON,Reset status for monitor clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
rbitfld.long 0x00 17. "RSTMSMP,Reset status for sampling clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
newline
rbitfld.long 0x00 16. "ENMON,Operating status" "0: Clock monitor is stopped,1: Clock monitor is operating"
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved"
newline
bitfld.long 0x00 1. "INTEN,Interrupt mask bit" "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor"
bitfld.long 0x00 0. "CHKEN,Enable for checking clock oscillation" "0: Stop clock monitor checking,1: Run clock monitor checking"
group.long 0x234++0x03
line.long 0x00 "S0D12HSCCKMECR,It is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
bitfld.long 0x00 0. "CLRRES,Clear command signal for check result" "0: Release clear signal,1: Issue clear signal to clock monitor"
group.long 0x238++0x03
line.long 0x00 "S0D12HSCCKMLCH,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPH_23_0,The upper limit to judge as expected oscillation"
group.long 0x23C++0x03
line.long 0x00 "S0D12HSCCKMLCL,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPL_23_0,The lower limit to judge as expected oscillation"
group.long 0x240++0x03
line.long 0x00 "S0D12HSCCKMCNT,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNT_6_0,The number of times of updating MONCNT"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNT_23_0,The counter value of clock monitor in the latest sampling period"
group.long 0x244++0x03
line.long 0x00 "S0D12HSCCKMCNTE,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "VLD,Valid bit" "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNTE_6_0,S0D12HSCCKMCNT.UPDCNT value when the first error occurred"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,The counter value of clock monitor when the first error occurred"
group.long 0x2D0++0x03
line.long 0x00 "RSW2CKMCSR,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "CHKRES,Check result" "0: Clock oscillates normally,1: Detect unexpected clock oscillation"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 24. "CLRMON,Reference for clear command signal - RSW2CKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued"
rbitfld.long 0x00 19.--23. "Reserved_19,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 18. "RSTMMON,Reset status for monitor clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
rbitfld.long 0x00 17. "RSTMSMP,Reset status for sampling clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
newline
rbitfld.long 0x00 16. "ENMON,Operating status" "0: Clock monitor is stopped,1: Clock monitor is operating"
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved"
newline
bitfld.long 0x00 1. "INTEN,Interrupt mask bit" "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor"
bitfld.long 0x00 0. "CHKEN,Enable for checking clock oscillation" "0: Stop clock monitor checking,1: Run clock monitor checking"
group.long 0x2D4++0x03
line.long 0x00 "RSW2CKMECR,It is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
bitfld.long 0x00 0. "CLRRES,Clear command signal for check result" "0: Release clear signal,1: Issue clear signal to clock monitor"
group.long 0x2D8++0x03
line.long 0x00 "RSW2CKMLCH,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPH_23_0,The upper limit to judge as expected oscillation"
group.long 0x2DC++0x03
line.long 0x00 "RSW2CKMLCL,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPL_23_0,The lower limit to judge as expected oscillation"
group.long 0x2E0++0x03
line.long 0x00 "RSW2CKMCNT,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNT_6_0,The number of times of updating MONCNT"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNT_23_0,The counter value of clock monitor in the latest sampling period"
group.long 0x2E4++0x03
line.long 0x00 "RSW2CKMCNTE,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "VLD,Valid bit" "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNTE_6_0,RSW2CKMCNT.UPDCNT value when the first error occurred"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,The counter value of clock monitor when the first error occurred"
group.long 0x2F0++0x03
line.long 0x00 "CBFUSAHSCCKMCSR,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "CHKRES,Check result" "0: Clock oscillates normally,1: Detect unexpected clock oscillation"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 24. "CLRMON,Reference for clear command signal - CBFUSAHSCCKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued"
rbitfld.long 0x00 19.--23. "Reserved_19,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 18. "RSTMMON,Reset status for monitor clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
rbitfld.long 0x00 17. "RSTMSMP,Reset status for sampling clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
newline
rbitfld.long 0x00 16. "ENMON,Operating status" "0: Clock monitor is stopped,1: Clock monitor is operating"
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved"
newline
bitfld.long 0x00 1. "INTEN,Interrupt mask bit" "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor"
bitfld.long 0x00 0. "CHKEN,Enable for checking clock oscillation" "0: Stop clock monitor checking,1: Run clock monitor checking"
group.long 0x2F4++0x03
line.long 0x00 "CBFUSAHSCCKMECR,It is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "CLRRES,Reference for clear command signal - CBFUSAHSCCKMECR.CLRRES" "0: Release clear signal,1: Issue clear signal to clock monitor when clock"
group.long 0x2F8++0x03
line.long 0x00 "CBFUSAHSCCKMLCH,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPH_23_0,The upper limit to judge as expected oscillation"
group.long 0x2FC++0x03
line.long 0x00 "CBFUSAHSCCKMLCL,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPL_23_0,The lower limit to judge as expected oscillation"
group.long 0x300++0x03
line.long 0x00 "CBFUSAHSCCKMCNT,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNT_6_0,Monitoring CBFUSAHSCCKMCNT.UPDCNT value"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,Monitoring CBFUSAHSCCKMCNT.MONCNT value"
group.long 0x304++0x03
line.long 0x00 "CBFUSAHSCCKMCNTE,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "VLD,Valid bit" "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNTE_6_0,CBFUSAHSCCKMCNT.UPDCNT value when the first error occurred"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,The counter value of clock monitor when the first error occurred"
group.long 0x310++0x03
line.long 0x00 "DBGSOCHSCCKMCSR,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "CHKRES,Check result" "0: Clock oscillates normally,1: Detect unexpected clock oscillation"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 24. "CLRMON,Reference for clear command signal - DBGSOCHSCCKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued"
rbitfld.long 0x00 19.--23. "Reserved_19,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 18. "RSTMMON,Reset status for monitor clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
rbitfld.long 0x00 17. "RSTMSMP,Reset status for sampling clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
newline
rbitfld.long 0x00 16. "ENMON,Operating status" "0: Clock monitor is stopped,1: Clock monitor is operating"
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved"
newline
bitfld.long 0x00 1. "INTEN,Interrupt mask bit" "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor"
bitfld.long 0x00 0. "CHKEN,Enable for checking clock oscillation" "0: Stop clock monitor checking,1: Run clock monitor checking"
group.long 0x314++0x03
line.long 0x00 "DBGSOCHSCCKMECR,It is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
bitfld.long 0x00 0. "CLRRES,Clear command signal for check result" "0: Release clear signal,1: Issue clear signal to clock monitor"
group.long 0x318++0x03
line.long 0x00 "DBGSOCHSCCKMLCH,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPH_23_0,The upper limit to judge as expected oscillation"
group.long 0x31C++0x03
line.long 0x00 "DBGSOCHSCCKMLCL,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPL_23_0,The lower limit to judge as expected oscillation"
group.long 0x320++0x03
line.long 0x00 "DBGSOCHSCCKMCNT,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNT_6_0,The number of times of updating MONCNT"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNT_23_0,The counter value of clock monitor in the latest sampling period"
group.long 0x324++0x03
line.long 0x00 "DBGSOCHSCCKMCNTE,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "VLD,Valid bit" "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNTE_6_0,DBGSOCHSCCKMCNT.UPDCNT value when the first error occurred"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,The counter value of clock monitor when the first error occurred"
tree.end
tree "CLOCK_PULSE_GENERATOR_CPG_INST_3"
base ad:0xE61F0000
group.long 0x00++0x03
line.long 0x00 "RTCKMWPR,It is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "WPRTCT_31_0,The specification is same as 8.2.1 CPG Write Protect Register (CPGWPR)"
group.long 0x04++0x03
line.long 0x00 "RTCKMWPCR,It is a 32-bit readable/writable register"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,The specification is same as 8.2.2 CPG Write Protect Register (CPGWPCR)"
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,The specification is same as 8.2.2 CPG Write Protect Register (CPGWPCR)"
newline
bitfld.long 0x00 0. "WPE,The specification is same as 8.2.2 CPG Write Protect Register (CPGWPCR)" "0,1"
group.long 0x170++0x03
line.long 0x00 "RCLKRTCKMCSR,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "CHKRES,Check result" "0: Clock oscillates normally,1: Detect unexpected clock oscillation"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 24. "CLRMON,Reference for clear command signal - RCLKRTCKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued"
rbitfld.long 0x00 19.--23. "Reserved_19,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 18. "RSTMMON,Reset status for monitor clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
rbitfld.long 0x00 17. "RSTMSMP,Reset status for sampling clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
newline
rbitfld.long 0x00 16. "ENMON,Operating status" "0: Clock monitor is stopped,1: Clock monitor is operating"
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved"
newline
bitfld.long 0x00 1. "INTEN,Interrupt mask bit" "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor"
bitfld.long 0x00 0. "CHKEN,Enable for checking clock oscillation" "0: Stop clock monitor checking,1: Run clock monitor checking"
group.long 0x174++0x03
line.long 0x00 "RCLKRTCKMECR,It is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "CLRRES,Reference for clear command signal - RCLKRTCKMECR.CLRRES" "0: Release clear signal,1: Issue clear signal to clock monitor when clock"
group.long 0x178++0x03
line.long 0x00 "RCLKRTCKMLCH,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPH_23_0,The upper limit to judge as expected oscillation"
group.long 0x17C++0x03
line.long 0x00 "RCLKRTCKMLCL,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPL_23_0,The lower limit to judge as expected oscillation"
group.long 0x180++0x03
line.long 0x00 "RCLKRTCKMCNT,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNT_6_0,Monitoring RCLKRTCKMCNT.UPDCNT value"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,Monitoring RCLKRTCKMCNT.MONCNT value"
group.long 0x184++0x03
line.long 0x00 "RCLKRTCKMCNTE,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "VLD,Valid bit" "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNTE_6_0,RCLKRTCKMCNT.UPDCNT value when the first error occurred"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,The counter value of clock monitor when the first error occurred"
group.long 0x190++0x03
line.long 0x00 "CL16MRTCKMCSR,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "CHKRES,Check result" "0: Clock oscillates normally,1: Detect unexpected clock oscillation"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 24. "CLRMON,Reference for clear command signal - CL16MRTCKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued"
rbitfld.long 0x00 19.--23. "Reserved_19,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 18. "RSTMMON,Reset status for monitor clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
rbitfld.long 0x00 17. "RSTMSMP,Reset status for sampling clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
newline
rbitfld.long 0x00 16. "ENMON,Operating status" "0: Clock monitor is stopped,1: Clock monitor is operating"
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved"
newline
bitfld.long 0x00 1. "INTEN,Interrupt mask bit" "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor"
bitfld.long 0x00 0. "CHKEN,Enable for checking clock oscillation" "0: Stop clock monitor checking,1: Run clock monitor checking"
group.long 0x194++0x03
line.long 0x00 "CL16MRTCKMECR,It is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "CLRRES,Reference for clear command signal - CL16MRTCKMECR.CLRRES" "0: Release clear signal,1: Issue clear signal to clock monitor when clock"
group.long 0x198++0x03
line.long 0x00 "CL16MRTCKMLCH,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPH_23_0,The upper limit to judge as expected oscillation"
group.long 0x19C++0x03
line.long 0x00 "CL16MRTCKMLCL,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPL_23_0,The lower limit to judge as expected oscillation"
group.long 0x1A0++0x03
line.long 0x00 "CL16MRTCKMCNT,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNT_6_0,Monitoring CL16MRTCKMCNT.UPDCNT value"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,Monitoring CL16MRTCKMCNT.MONCNT value"
group.long 0x1A4++0x03
line.long 0x00 "CL16MRTCKMCNTE,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "VLD,Valid bit" "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNTE_6_0,CL16MRTCKMCNT.UPDCNT value when the first error occurred"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,The counter value of clock monitor when the first error occurred"
group.long 0x1AC++0x03
line.long 0x00 "RTACKMSR,It is a 32-bit readable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved" "0,1"
rbitfld.long 0x00 30. "Reserved_30,Reserved" "0,1"
newline
rbitfld.long 0x00 29. "Reserved_29,Reserved" "0,1"
rbitfld.long 0x00 28. "Reserved_28,Reserved" "0,1"
newline
rbitfld.long 0x00 27. "Reserved_27,Reserved" "0,1"
rbitfld.long 0x00 26. "Reserved_26,Reserved" "0,1"
newline
rbitfld.long 0x00 25. "Reserved_25,Reserved" "0,1"
rbitfld.long 0x00 24. "Reserved_24,Reserved" "0,1"
newline
rbitfld.long 0x00 23. "Reserved_23,Reserved" "0,1"
rbitfld.long 0x00 22. "Reserved_22,Reserved" "0,1"
newline
rbitfld.long 0x00 21. "CHKRES021,SASYNCRT" "0,1"
rbitfld.long 0x00 20. "CHKRES020,CBFUSA" "0,1"
newline
rbitfld.long 0x00 19. "Reserved_19,Reserved" "0,1"
rbitfld.long 0x00 18. "CHKRES018,S0D24_RT" "0,1"
newline
rbitfld.long 0x00 17. "Reserved_17,Reserved" "0,1"
rbitfld.long 0x00 16. "CHKRES016,S0D6_RT" "0,1"
newline
rbitfld.long 0x00 15. "CHKRES015,S0D4_RT" "0,1"
rbitfld.long 0x00 14. "CHKRES014,S0D3_RT" "0,1"
newline
rbitfld.long 0x00 13. "CHKRES013,S0D2_RT" "0,1"
rbitfld.long 0x00 12. "Reserved_12,Reserved" "0,1"
newline
rbitfld.long 0x00 11. "CHKRES011,CL16M_RT" "0,1"
rbitfld.long 0x00 10. "CHKRES010,RCLK" "0,1"
newline
rbitfld.long 0x00 9. "Reserved_9,Reserved" "0,1"
rbitfld.long 0x00 8. "Reserved_8,Reserved" "0,1"
newline
rbitfld.long 0x00 7. "Reserved_7,Reserved" "0,1"
rbitfld.long 0x00 6. "Reserved_6,Reserved" "0,1"
newline
rbitfld.long 0x00 5. "Reserved_5,Reserved" "0,1"
rbitfld.long 0x00 4. "Reserved_4,Reserved" "0,1"
newline
rbitfld.long 0x00 3. "Reserved_3,Reserved" "0,1"
rbitfld.long 0x00 2. "Reserved_2,Reserved" "0,1"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved" "0,1"
rbitfld.long 0x00 0. "Reserved_0,Reserved" "0,1"
group.long 0x1D0++0x03
line.long 0x00 "S0D2RTCKMCSR,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "CHKRES,Check result" "0: Clock oscillates normally,1: Detect unexpected clock oscillation"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 24. "CLRMON,Reference for clear command signal - S0D2RTCKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued"
rbitfld.long 0x00 19.--23. "Reserved_19,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 18. "RSTMMON,Reset status for monitor clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
rbitfld.long 0x00 17. "RSTMSMP,Reset status for sampling clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
newline
rbitfld.long 0x00 16. "ENMON,Operating status" "0: Clock monitor is stopped,1: Clock monitor is operating"
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved"
newline
bitfld.long 0x00 1. "INTEN,Interrupt mask bit" "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor"
bitfld.long 0x00 0. "CHKEN,Enable for checking clock oscillation" "0: Stop clock monitor checking,1: Run clock monitor checking"
group.long 0x1D4++0x03
line.long 0x00 "S0D2RTCKMECR,It is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "CLRRES,Reference for clear command signal - S0D2RTCKMECR.CLRRES" "0: Release clear signal,1: Issue clear signal to clock monitor when clock"
group.long 0x1D8++0x03
line.long 0x00 "S0D2RTCKMLCH,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPH_23_0,The upper limit to judge as expected oscillation"
group.long 0x1DC++0x03
line.long 0x00 "S0D2RTCKMLCL,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPL_23_0,The lower limit to judge as expected oscillation"
group.long 0x1E0++0x03
line.long 0x00 "S0D2RTCKMCNT,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNT_6_0,Monitoring S0D2RTCKMCNT.UPDCNT value"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,Monitoring S0D2RTCKMCNT.MONCNT value"
group.long 0x1E4++0x03
line.long 0x00 "S0D2RTCKMCNTE,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "VLD,Valid bit" "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNTE_6_0,S0D2RTCKMCNT.UPDCNT value when the first error occurred"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,The counter value of clock monitor when the first error occurred"
group.long 0x1F0++0x03
line.long 0x00 "S0D3RTCKMCSR,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "CHKRES,Check result" "0: Clock oscillates normally,1: Detect unexpected clock oscillation"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 24. "CLRMON,Reference for clear command signal - S0D3RTCKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued"
rbitfld.long 0x00 19.--23. "Reserved_19,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 18. "RSTMMON,Reset status for monitor clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
rbitfld.long 0x00 17. "RSTMSMP,Reset status for sampling clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
newline
rbitfld.long 0x00 16. "ENMON,Operating status" "0: Clock monitor is stopped,1: Clock monitor is operating"
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved"
newline
bitfld.long 0x00 1. "INTEN,Interrupt mask bit" "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor"
bitfld.long 0x00 0. "CHKEN,Enable for checking clock oscillation" "0: Stop clock monitor checking,1: Run clock monitor checking"
group.long 0x1F4++0x03
line.long 0x00 "S0D3RTCKMECR,It is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "CLRRES,Reference for clear command signal - S0D3RTCKMECR.CLRRES" "0: Release clear signal,1: Issue clear signal to clock monitor when clock"
group.long 0x1F8++0x03
line.long 0x00 "S0D3RTCKMLCH,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPH_23_0,The upper limit to judge as expected oscillation"
group.long 0x1FC++0x03
line.long 0x00 "S0D3RTCKMLCL,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPL_23_0,The lower limit to judge as expected oscillation"
group.long 0x200++0x03
line.long 0x00 "S0D3RTCKMCNT,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNT_6_0,Monitoring S0D3RTCKMCNT.UPDCNT value"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,Monitoring S0D3RTCKMCNT.MONCNT value"
group.long 0x204++0x03
line.long 0x00 "S0D3RTCKMCNTE,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "VLD,Valid bit" "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNTE_6_0,S0D3RTCKMCNT.UPDCNT value when the first error occurred"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,The counter value of clock monitor when the first error occurred"
group.long 0x210++0x03
line.long 0x00 "S0D4RTCKMCSR,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "CHKRES,Check result" "0: Clock oscillates normally,1: Detect unexpected clock oscillation"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 24. "CLRMON,Reference for clear command signal - S0D4RTCKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued"
rbitfld.long 0x00 19.--23. "Reserved_19,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 18. "RSTMMON,Reset status for monitor clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
rbitfld.long 0x00 17. "RSTMSMP,Reset status for sampling clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
newline
rbitfld.long 0x00 16. "ENMON,Operating status" "0: Clock monitor is stopped,1: Clock monitor is operating"
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved"
newline
bitfld.long 0x00 1. "INTEN,Interrupt mask bit" "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor"
bitfld.long 0x00 0. "CHKEN,Enable for checking clock oscillation" "0: Stop clock monitor checking,1: Run clock monitor checking"
group.long 0x214++0x03
line.long 0x00 "S0D4RTCKMECR,It is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "CLRRES,Reference for clear command signal - S0D4RTCKMECR.CLRRES" "0: Release clear signal,1: Issue clear signal to clock monitor when clock"
group.long 0x218++0x03
line.long 0x00 "S0D4RTCKMLCH,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPH_23_0,The upper limit to judge as expected oscillation"
group.long 0x21C++0x03
line.long 0x00 "S0D4RTCKMLCL,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPL_23_0,The lower limit to judge as expected oscillation"
group.long 0x220++0x03
line.long 0x00 "S0D4RTCKMCNT,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNT_6_0,Monitoring S0D4RTCKMCNT.UPDCNT value"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,Monitoring S0D4RTCKMCNT.MONCNT value"
group.long 0x224++0x03
line.long 0x00 "S0D4RTCKMCNTE,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "VLD,Valid bit" "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNTE_6_0,S0D4RTCKMCNT.UPDCNT value when the first error occurred"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,The counter value of clock monitor when the first error occurred"
group.long 0x230++0x03
line.long 0x00 "S0D6RTCKMCSR,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "CHKRES,Check result" "0: Clock oscillates normally,1: Detect unexpected clock oscillation"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 24. "CLRMON,Reference for clear command signal - S0D6RTCKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued"
rbitfld.long 0x00 19.--23. "Reserved_19,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 18. "RSTMMON,Reset status for monitor clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
rbitfld.long 0x00 17. "RSTMSMP,Reset status for sampling clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
newline
rbitfld.long 0x00 16. "ENMON,Operating status" "0: Clock monitor is stopped,1: Clock monitor is operating"
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved"
newline
bitfld.long 0x00 1. "INTEN,Interrupt mask bit" "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor"
bitfld.long 0x00 0. "CHKEN,Enable for checking clock oscillation" "0: Stop clock monitor checking,1: Run clock monitor checking"
group.long 0x234++0x03
line.long 0x00 "S0D6RTCKMECR,It is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "CLRRES,Reference for clear command signal - S0D6RTCKMECR.CLRRES" "0: Release clear signal,1: Issue clear signal to clock monitor when clock"
group.long 0x238++0x03
line.long 0x00 "S0D6RTCKMLCH,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPH_23_0,The upper limit to judge as expected oscillation"
group.long 0x23C++0x03
line.long 0x00 "S0D6RTCKMLCL,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPL_23_0,The lower limit to judge as expected oscillation"
group.long 0x240++0x03
line.long 0x00 "S0D6RTCKMCNT,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNT_6_0,Monitoring S0D6RTCKMCNT.UPDCNT value"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,Monitoring S0D6RTCKMCNT.MONCNT value"
group.long 0x244++0x03
line.long 0x00 "S0D6RTCKMCNTE,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "VLD,Valid bit" "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNTE_6_0,S0D6RTCKMCNT.UPDCNT value when the first error occurred"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,The counter value of clock monitor when the first error occurred"
group.long 0x2B0++0x03
line.long 0x00 "CBFUSARTCKMCSR,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "CHKRES,Check result" "0: Clock oscillates normally,1: Detect unexpected clock oscillation"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 24. "CLRMON,Reference for clear command signal - CBFUSARTCKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued"
rbitfld.long 0x00 19.--23. "Reserved_19,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 18. "RSTMMON,Reset status for monitor clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
rbitfld.long 0x00 17. "RSTMSMP,Reset status for sampling clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
newline
rbitfld.long 0x00 16. "ENMON,Operating status" "0: Clock monitor is stopped,1: Clock monitor is operating"
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved"
newline
bitfld.long 0x00 1. "INTEN,Interrupt mask bit" "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor"
bitfld.long 0x00 0. "CHKEN,Enable for checking clock oscillation" "0: Stop clock monitor checking,1: Run clock monitor checking"
group.long 0x2B4++0x03
line.long 0x00 "CBFUSARTCKMECR,It is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "CLRRES,Reference for clear command signal - CBFUSARTCKMECR.CLRRES" "0: Release clear signal,1: Issue clear signal to clock monitor when clock"
group.long 0x2B8++0x03
line.long 0x00 "CBFUSARTCKMLCH,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPH_23_0,The upper limit to judge as expected oscillation"
group.long 0x2BC++0x03
line.long 0x00 "CBFUSARTCKMLCL,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPL_23_0,The lower limit to judge as expected oscillation"
group.long 0x2C0++0x03
line.long 0x00 "CBFUSARTCKMCNT,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNT_6_0,Monitoring CBFUSARTCKMCNT.UPDCNT value"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,Monitoring CBFUSARTCKMCNT.MONCNT value"
group.long 0x2C4++0x03
line.long 0x00 "CBFUSARTCKMCNTE,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "VLD,Valid bit" "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNTE_6_0,CBFUSARTCKMCNT.UPDCNT value when the first error occurred"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,The counter value of clock monitor when the first error occurred"
group.long 0x2D0++0x03
line.long 0x00 "SASYNCRTCKMCSR,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "CHKRES,Check result" "0: Clock oscillates normally,1: Detect unexpected clock oscillation"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 24. "CLRMON,Reference for clear command signal - SASYNCRTCKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued"
rbitfld.long 0x00 19.--23. "Reserved_19,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 18. "RSTMMON,Reset status for monitor clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
rbitfld.long 0x00 17. "RSTMSMP,Reset status for sampling clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
newline
rbitfld.long 0x00 16. "ENMON,Operating status" "0: Clock monitor is stopped,1: Clock monitor is operating"
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved"
newline
bitfld.long 0x00 1. "INTEN,Interrupt mask bit" "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor"
bitfld.long 0x00 0. "CHKEN,Enable for checking clock oscillation" "0: Stop clock monitor checking,1: Run clock monitor checking"
group.long 0x2D4++0x03
line.long 0x00 "SASYNCRTCKMECR,It is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "CLRRES,Reference for clear command signal - SASYNCRTCKMECR.CLRRES" "0: Release clear signal,1: Issue clear signal to clock monitor when clock"
group.long 0x2D8++0x03
line.long 0x00 "SASYNCRTCKMLCH,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPH_23_0,The upper limit to judge as expected oscillation"
group.long 0x2DC++0x03
line.long 0x00 "SASYNCRTCKMLCL,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPL_23_0,The lower limit to judge as expected oscillation"
group.long 0x2E0++0x03
line.long 0x00 "SASYNCRTCKMCNT,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNT_6_0,Monitoring SASYNCRTCKMCNT.UPDCNT value"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,Monitoring SASYNCRTCKMCNT.MONCNT value"
group.long 0x2E4++0x03
line.long 0x00 "SASYNCRTCKMCNTE,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "VLD,Valid bit" "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNTE_6_0,SASYNCRTCKMCNT.UPDCNT value when the first error occurred"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,The counter value of clock monitor when the first error occurred"
group.long 0x2000++0x03
line.long 0x00 "RTCR52CKMWPR,It is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "WPRTCT_31_0,The specification is same as 8.2.1 CPG Write Protect Register (CPGWPR)"
group.long 0x2004++0x03
line.long 0x00 "RTCR52CKMWPCR,It is a 32-bit readable/writable register"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,The specification is same as 8.2.2 CPG Write Protect Register (CPGWPCR)"
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,The specification is same as 8.2.2 CPG Write Protect Register (CPGWPCR)"
newline
bitfld.long 0x00 0. "WPE,The specification is same as 8.2.2 CPG Write Protect Register (CPGWPCR)" "0,1"
group.long 0x2010++0x03
line.long 0x00 "ZRCR52CKMCSR,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "CHKRES,Check result" "0: Clock oscillates normally,1: Detect unexpected clock oscillation"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 24. "CLRMON,Reference for clear command signal - ZR0CR52CKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued"
rbitfld.long 0x00 19.--23. "Reserved_19,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 18. "RSTMMON,Reset status for monitor clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
rbitfld.long 0x00 17. "RSTMSMP,Reset status for sampling clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
newline
rbitfld.long 0x00 16. "ENMON,Operating status" "0: Clock monitor is stopped,1: Clock monitor is operating"
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved"
newline
bitfld.long 0x00 1. "INTEN,Interrupt mask bit" "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor"
bitfld.long 0x00 0. "CHKEN,Enable for checking clock oscillation" "0: Stop clock monitor checking,1: Run clock monitor checking"
group.long 0x2014++0x03
line.long 0x00 "ZRCR52CKMECR,It is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "CLRRES,Reference for clear command signal - ZR0CR52CKMECR.CLRRES" "0: Release clear signal,1: Issue clear signal to clock monitor when clock"
group.long 0x2018++0x03
line.long 0x00 "ZRCR52CKMLCH,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPH_23_0,The upper limit to judge as expected oscillation"
group.long 0x201C++0x03
line.long 0x00 "ZRCR52CKMLCL,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPL_23_0,The lower limit to judge as expected oscillation"
group.long 0x2020++0x03
line.long 0x00 "ZRCR52CKMCNT,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNT_6_0,Monitoring ZR0CR52CKMCNT.UPDCNT value"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,Monitoring ZR0CR52CKMCNT.MONCNT value"
group.long 0x2024++0x03
line.long 0x00 "ZRCR52CKMCNTE,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "VLD,Valid bit" "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNTE_6_0,ZR0CR52CKMCNT.UPDCNT value when the first error occurred"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,The counter value of clock monitor when the first error occurred"
group.long 0x2070++0x03
line.long 0x00 "RCLKRTCR52CKMCSR,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "CHKRES,Check result" "0: Clock oscillates normally,1: Detect unexpected clock oscillation"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 24. "CLRMON,Reference for clear command signal - RCLKRTCR52CKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued"
rbitfld.long 0x00 19.--23. "Reserved_19,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 18. "RSTMMON,Reset status for monitor clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
rbitfld.long 0x00 17. "RSTMSMP,Reset status for sampling clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
newline
rbitfld.long 0x00 16. "ENMON,Operating status" "0: Clock monitor is stopped,1: Clock monitor is operating"
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved"
newline
bitfld.long 0x00 1. "INTEN,Interrupt mask bit" "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor"
bitfld.long 0x00 0. "CHKEN,Enable for checking clock oscillation" "0: Stop clock monitor checking,1: Run clock monitor checking"
group.long 0x2074++0x03
line.long 0x00 "RCLKRTCR52CKMECR,It is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "CLRRES,Reference for clear command signal - RCLKRTCR52CKMECR.CLRRES" "0: Release clear signal,1: Issue clear signal to clock monitor when clock"
group.long 0x2078++0x03
line.long 0x00 "RCLKRTCR52CKMLCH,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPH_23_0,The upper limit to judge as expected oscillation"
group.long 0x207C++0x03
line.long 0x00 "RCLKRTCR52CKMLCL,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPL_23_0,The lower limit to judge as expected oscillation"
group.long 0x2080++0x03
line.long 0x00 "RCLKRTCR52CKMCNT,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNT_6_0,Monitoring RCLKRTCR52CKMCNT.UPDCNT value"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,Monitoring RCLKRTCR52CKMCNT.MONCNT value"
group.long 0x2084++0x03
line.long 0x00 "RCLKRTCR52CKMCNTE,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "VLD,Valid bit" "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNTE_6_0,RCLKRTCR52CKMCNT.UPDCNT value when the first error occurred"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,The counter value of clock monitor when the first error occurred"
group.long 0x2090++0x03
line.long 0x00 "CBFUSARTCR52CKMCSR,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "CHKRES,Check result" "0: Clock oscillates normally,1: Detect unexpected clock oscillation"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 24. "CLRMON,Reference for clear command signal - CBFUSARTCR52CKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued"
rbitfld.long 0x00 19.--23. "Reserved_19,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 18. "RSTMMON,Reset status for monitor clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
rbitfld.long 0x00 17. "RSTMSMP,Reset status for sampling clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
newline
rbitfld.long 0x00 16. "ENMON,Operating status" "0: Clock monitor is stopped,1: Clock monitor is operating"
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved"
newline
bitfld.long 0x00 1. "INTEN,Interrupt mask bit" "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor"
bitfld.long 0x00 0. "CHKEN,Enable for checking clock oscillation" "0: Stop clock monitor checking,1: Run clock monitor checking"
group.long 0x2094++0x03
line.long 0x00 "CBFUSARTCR52CKMECR,It is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "CLRRES,Reference for clear command signal - CBFUSARTCR52CKMECR.CLRRES" "0: Release clear signal,1: Issue clear signal to clock monitor when clock"
group.long 0x2098++0x03
line.long 0x00 "CBFUSARTCR52CKMLCH,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPH_23_0,The upper limit to judge as expected oscillation"
group.long 0x209C++0x03
line.long 0x00 "CBFUSARTCR52CKMLCL,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPL_23_0,The lower limit to judge as expected oscillation"
group.long 0x20A0++0x03
line.long 0x00 "CBFUSARTCR52CKMCNT,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNT_6_0,Monitoring CBFUSARTCR52CKMCNT.UPDCNT value"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,Monitoring CBFUSARTCR52CKMCNT.MONCNT value"
group.long 0x20A4++0x03
line.long 0x00 "CBFUSARTCR52CKMCNTE,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "VLD,Valid bit" "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNTE_6_0,CBFUSARTCR52CKMCNT.UPDCNT value when the first error occurred"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,The counter value of clock monitor when the first error occurred"
group.long 0x20B0++0x03
line.long 0x00 "RTCR52ACKMSR,It is a 32-bit readable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved" "0,1"
rbitfld.long 0x00 30. "Reserved_30,Reserved" "0,1"
newline
rbitfld.long 0x00 29. "Reserved_29,Reserved" "0,1"
rbitfld.long 0x00 28. "Reserved_28,Reserved" "0,1"
newline
rbitfld.long 0x00 27. "Reserved_27,Reserved" "0,1"
rbitfld.long 0x00 26. "Reserved_26,Reserved" "0,1"
newline
rbitfld.long 0x00 25. "Reserved_25,Reserved" "0,1"
rbitfld.long 0x00 24. "Reserved_24,Reserved" "0,1"
newline
rbitfld.long 0x00 23. "Reserved_23,Reserved" "0,1"
rbitfld.long 0x00 22. "Reserved_22,Reserved" "0,1"
newline
rbitfld.long 0x00 21. "Reserved_21,Reserved" "0,1"
rbitfld.long 0x00 20. "Reserved_20,Reserved" "0,1"
newline
rbitfld.long 0x00 19. "Reserved_19,Reserved" "0,1"
rbitfld.long 0x00 18. "Reserved_18,Reserved" "0,1"
newline
rbitfld.long 0x00 17. "Reserved_17,Reserved" "0,1"
rbitfld.long 0x00 16. "Reserved_16,Reserved" "0,1"
newline
rbitfld.long 0x00 15. "Reserved_15,Reserved" "0,1"
rbitfld.long 0x00 14. "Reserved_14,Reserved" "0,1"
newline
rbitfld.long 0x00 13. "Reserved_13,Reserved" "0,1"
rbitfld.long 0x00 12. "Reserved_12,Reserved" "0,1"
newline
rbitfld.long 0x00 11. "Reserved_11,Reserved" "0,1"
rbitfld.long 0x00 10. "Reserved_10,Reserved" "0,1"
newline
rbitfld.long 0x00 9. "Reserved_9,Reserved" "0,1"
rbitfld.long 0x00 8. "Reserved_8,Reserved" "0,1"
newline
rbitfld.long 0x00 7. "Reserved_7,Reserved" "0,1"
rbitfld.long 0x00 6. "Reserved_6,Reserved" "0,1"
newline
rbitfld.long 0x00 5. "CHKRES005,S0D2_RT" "0,1"
rbitfld.long 0x00 4. "CHKRES004,CBFUSA" "0,1"
newline
rbitfld.long 0x00 3. "CHKRES003,RCLK" "0,1"
rbitfld.long 0x00 2. "Reserved_2,Reserved" "0,1"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved" "0,1"
rbitfld.long 0x00 0. "CHKRES000,ZR" "0,1"
group.long 0x20C0++0x03
line.long 0x00 "S0D2RTCR52CKMCSR,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "CHKRES,Check result" "0: Clock oscillates normally,1: Detect unexpected clock oscillation"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 24. "CLRMON,Reference for clear command signal - S0D2RTCR52CKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued"
rbitfld.long 0x00 19.--23. "Reserved_19,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 18. "RSTMMON,Reset status for monitor clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
rbitfld.long 0x00 17. "RSTMSMP,Reset status for sampling clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
newline
rbitfld.long 0x00 16. "ENMON,Operating status" "0: Clock monitor is stopped,1: Clock monitor is operating"
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved"
newline
bitfld.long 0x00 1. "INTEN,Interrupt mask bit" "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor"
bitfld.long 0x00 0. "CHKEN,Enable for checking clock oscillation" "0: Stop clock monitor checking,1: Run clock monitor checking"
group.long 0x20C4++0x03
line.long 0x00 "S0D2RTCR52CKMECR,It is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "CLRRES,Reference for clear command signal - S0D2RTCR52CKMECR.CLRRES" "0: Release clear signal,1: Issue clear signal to clock monitor when clock"
group.long 0x20C8++0x03
line.long 0x00 "S0D2RTCR52CKMLCH,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPH_23_0,The upper limit to judge as expected oscillation"
group.long 0x20CC++0x03
line.long 0x00 "S0D2RTCR52CKMLCL,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPL_23_0,The lower limit to judge as expected oscillation"
group.long 0x20D0++0x03
line.long 0x00 "S0D2RTCR52CKMCNT,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNT_6_0,Monitoring S0D2RTCR52CKMCNT.UPDCNT value"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,Monitoring S0D2RTCR52CKMCNT.MONCNT value"
group.long 0x20D4++0x03
line.long 0x00 "S0D2RTCR52CKMCNTE,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "VLD,Valid bit" "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNTE_6_0,S0D2RTCR52CKMCNT.UPDCNT value when the first error occurred"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,The counter value of clock monitor when the first error occurred"
tree.end
tree "CLOCK_PULSE_GENERATOR_CPG_INST_4"
base ad:0xE67FA000
group.long 0x00++0x03
line.long 0x00 "MMCKMWPR,It is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "WPRTCT_31_0,The specification is same as 8.2.1 CPG Write Protect Register (CPGWPR)"
group.long 0x04++0x03
line.long 0x00 "MMCKMWPCR,It is a 32-bit readable/writable register"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,The specification is same as 8.2.2 CPG Write Protect Register (CPGWPCR)"
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,The specification is same as 8.2.2 CPG Write Protect Register (CPGWPCR)"
newline
bitfld.long 0x00 0. "WPE,The specification is same as 8.2.2 CPG Write Protect Register (CPGWPCR)" "0,1"
group.long 0x70++0x03
line.long 0x00 "ZB3D2CKMCSR,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "CHKRES,Check result" "0: Clock oscillates normally,1: Detect unexpected clock oscillation"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 24. "CLRMON,Reference for clear command signal - ZB3D2CKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued"
rbitfld.long 0x00 19.--23. "Reserved_19,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 18. "RSTMMON,Reset status for monitor clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
rbitfld.long 0x00 17. "RSTMSMP,Reset status for sampling clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
newline
rbitfld.long 0x00 16. "ENMON,Operating status" "0: Clock monitor is stopped,1: Clock monitor is operating"
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved"
newline
bitfld.long 0x00 1. "INTEN,Interrupt mask bit" "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor"
bitfld.long 0x00 0. "CHKEN,Enable for checking clock oscillation" "0: Stop clock monitor checking,1: Run clock monitor checking"
group.long 0x74++0x03
line.long 0x00 "ZB3D2CKMECR,It is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "CLRRES,Reference for clear command signal - ZB3D2CKMECR.CLRRES" "0: Release clear signal,1: Issue clear signal to clock monitor when clock"
group.long 0x78++0x03
line.long 0x00 "ZB3D2CKMLCH,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPH_23_0,The upper limit to judge as expected oscillation"
group.long 0x7C++0x03
line.long 0x00 "ZB3D2CKMLCL,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPL_23_0,The lower limit to judge as expected oscillation"
group.long 0x80++0x03
line.long 0x00 "ZB3D2CKMCNT,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNT_6_0,Monitoring ZB3D2CKMCNT.UPDCNT value"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,Monitoring ZB3D2CKMCNT.MONCNT value"
group.long 0x84++0x03
line.long 0x00 "ZB3D2CKMCNTE,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "VLD,Valid bit" "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNTE_6_0,ZB3D2CKMCNT.UPDCNT value when the first error occurred"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,The counter value of clock monitor when the first error occurred"
group.long 0x90++0x03
line.long 0x00 "CL16MMMCKMCSR,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "CHKRES,Check result" "0: Clock oscillates normally,1: Detect unexpected clock oscillation"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 24. "CLRMON,Reference for clear command signal - CL16MMMCKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued"
rbitfld.long 0x00 19.--23. "Reserved_19,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 18. "RSTMMON,Reset status for monitor clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
rbitfld.long 0x00 17. "RSTMSMP,Reset status for sampling clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
newline
rbitfld.long 0x00 16. "ENMON,Operating status" "0: Clock monitor is stopped,1: Clock monitor is operating"
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved"
newline
bitfld.long 0x00 1. "INTEN,Interrupt mask bit" "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor"
bitfld.long 0x00 0. "CHKEN,Enable for checking clock oscillation" "0: Stop clock monitor checking,1: Run clock monitor checking"
group.long 0x94++0x03
line.long 0x00 "CL16MMMCKMECR,It is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "CLRRES,Reference for clear command signal - CL16MMMCKMECR.CLRRES" "0: Release clear signal,1: Issue clear signal to clock monitor when clock"
group.long 0x98++0x03
line.long 0x00 "CL16MMMCKMLCH,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPH_23_0,The upper limit to judge as expected oscillation"
group.long 0x9C++0x03
line.long 0x00 "CL16MMMCKMLCL,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPL_23_0,The lower limit to judge as expected oscillation"
group.long 0xA0++0x03
line.long 0x00 "CL16MMMCKMCNT,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNT_6_0,Monitoring CL16MMMCKMCNT.UPDCNT value"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,Monitoring CL16MMMCKMCNT.MONCNT value"
group.long 0xA4++0x03
line.long 0x00 "CL16MMMCKMCNTE,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "VLD,Valid bit" "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNTE_6_0,CL16MMMCKMCNT.UPDCNT value when the first error occurred"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,The counter value of clock monitor when the first error occurred"
group.long 0xAC++0x03
line.long 0x00 "MMACKMSR,It is a 32-bit readable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved" "0,1"
rbitfld.long 0x00 30. "Reserved_30,Reserved" "0,1"
newline
rbitfld.long 0x00 29. "Reserved_29,Reserved" "0,1"
rbitfld.long 0x00 28. "Reserved_28,Reserved" "0,1"
newline
rbitfld.long 0x00 27. "Reserved_27,Reserved" "0,1"
rbitfld.long 0x00 26. "Reserved_26,Reserved" "0,1"
newline
rbitfld.long 0x00 25. "Reserved_25,Reserved" "0,1"
rbitfld.long 0x00 24. "Reserved_24,Reserved" "0,1"
newline
rbitfld.long 0x00 23. "Reserved_23,Reserved" "0,1"
rbitfld.long 0x00 22. "Reserved_22,Reserved" "0,1"
newline
rbitfld.long 0x00 21. "Reserved_21,Reserved" "0,1"
rbitfld.long 0x00 20. "Reserved_20,Reserved" "0,1"
newline
rbitfld.long 0x00 19. "Reserved_19,Reserved" "0,1"
rbitfld.long 0x00 18. "Reserved_18,Reserved" "0,1"
newline
rbitfld.long 0x00 17. "Reserved_17,Reserved" "0,1"
rbitfld.long 0x00 16. "Reserved_16,Reserved" "0,1"
newline
rbitfld.long 0x00 15. "Reserved_15,Reserved" "0,1"
rbitfld.long 0x00 14. "Reserved_14,Reserved" "0,1"
newline
rbitfld.long 0x00 13. "CHKRES013,RCLK" "0,1"
rbitfld.long 0x00 12. "CHKRES012,CBFUSA" "0,1"
newline
rbitfld.long 0x00 11. "CHKRES011,ZB3D4" "0,1"
rbitfld.long 0x00 10. "CHKRES010,ZB3D1" "0,1"
newline
rbitfld.long 0x00 9. "CHKRES009,S0D4_MM" "0,1"
rbitfld.long 0x00 8. "CHKRES008,S0D3_MM" "0,1"
newline
rbitfld.long 0x00 7. "CHKRES007,S0D2_MM" "0,1"
rbitfld.long 0x00 6. "Reserved_6,Reserved" "0,1"
newline
rbitfld.long 0x00 5. "CHKRES005,CL16M_MM" "0,1"
rbitfld.long 0x00 4. "CHKRES004,ZB3D2" "0,1"
newline
rbitfld.long 0x00 3. "Reserved_3,Reserved" "0,1"
rbitfld.long 0x00 2. "Reserved_2,Reserved" "0,1"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved" "0,1"
rbitfld.long 0x00 0. "Reserved_0,Reserved" "0,1"
group.long 0xD0++0x03
line.long 0x00 "S0D2MMCKMCSR,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "CHKRES,Check result" "0: Clock oscillates normally,1: Detect unexpected clock oscillation"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 24. "CLRMON,Reference for clear command signal - S0D2MMCKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued"
rbitfld.long 0x00 19.--23. "Reserved_19,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 18. "RSTMMON,Reset status for monitor clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
rbitfld.long 0x00 17. "RSTMSMP,Reset status for sampling clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
newline
rbitfld.long 0x00 16. "ENMON,Operating status" "0: Clock monitor is stopped,1: Clock monitor is operating"
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved"
newline
bitfld.long 0x00 1. "INTEN,Interrupt mask bit" "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor"
bitfld.long 0x00 0. "CHKEN,Enable for checking clock oscillation" "0: Stop clock monitor checking,1: Run clock monitor checking"
group.long 0xD4++0x03
line.long 0x00 "S0D2MMCKMECR,It is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "CLRRES,Reference for clear command signal - S0D2MMCKMECR.CLRRES" "0: Release clear signal,1: Issue clear signal to clock monitor when clock"
group.long 0xD8++0x03
line.long 0x00 "S0D2MMCKMLCH,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPH_23_0,The upper limit to judge as expected oscillation"
group.long 0xDC++0x03
line.long 0x00 "S0D2MMCKMLCL,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPL_23_0,The lower limit to judge as expected oscillation"
group.long 0xE0++0x03
line.long 0x00 "S0D2MMCKMCNT,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNT_6_0,Monitoring S0D2MMCKMCNT.UPDCNT value"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,Monitoring S0D2MMCKMCNT.MONCNT value"
group.long 0xE4++0x03
line.long 0x00 "S0D2MMCKMCNTE,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "VLD,Valid bit" "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNTE_6_0,S0D2MMCKMCNT.UPDCNT value when the first error occurred"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,The counter value of clock monitor when the first error occurred"
group.long 0xF0++0x03
line.long 0x00 "S0D3MMCKMCSR,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "CHKRES,Check result" "0: Clock oscillates normally,1: Detect unexpected clock oscillation"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 24. "CLRMON,Reference for clear command signal - S0D3MMCKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued"
rbitfld.long 0x00 19.--23. "Reserved_19,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 18. "RSTMMON,Reset status for monitor clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
rbitfld.long 0x00 17. "RSTMSMP,Reset status for sampling clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
newline
rbitfld.long 0x00 16. "ENMON,Operating status" "0: Clock monitor is stopped,1: Clock monitor is operating"
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved"
newline
bitfld.long 0x00 1. "INTEN,Interrupt mask bit" "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor"
bitfld.long 0x00 0. "CHKEN,Enable for checking clock oscillation" "0: Stop clock monitor checking,1: Run clock monitor checking"
group.long 0xF4++0x03
line.long 0x00 "S0D3MMCKMECR,It is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "CLRRES,Reference for clear command signal - S0D3MMCKMECR.CLRRES" "0: Release clear signal,1: Issue clear signal to clock monitor when clock"
group.long 0xF8++0x03
line.long 0x00 "S0D3MMCKMLCH,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPH_23_0,The upper limit to judge as expected oscillation"
group.long 0xFC++0x03
line.long 0x00 "S0D3MMCKMLCL,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPL_23_0,The lower limit to judge as expected oscillation"
group.long 0x100++0x03
line.long 0x00 "S0D3MMCKMCNT,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNT_6_0,Monitoring S0D3MMCKMCNT.UPDCNT value"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,Monitoring S0D3MMCKMCNT.MONCNT value"
group.long 0x104++0x03
line.long 0x00 "S0D3MMCKMCNTE,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "VLD,Valid bit" "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNTE_6_0,S0D3MMCKMCNT.UPDCNT value when the first error occurred"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,The counter value of clock monitor when the first error occurred"
group.long 0x110++0x03
line.long 0x00 "S0D4MMCKMCSR,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "CHKRES,Check result" "0: Clock oscillates normally,1: Detect unexpected clock oscillation"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 24. "CLRMON,Reference for clear command signal - S0D4MMCKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued"
rbitfld.long 0x00 19.--23. "Reserved_19,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 18. "RSTMMON,Reset status for monitor clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
rbitfld.long 0x00 17. "RSTMSMP,Reset status for sampling clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
newline
rbitfld.long 0x00 16. "ENMON,Operating status" "0: Clock monitor is stopped,1: Clock monitor is operating"
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved"
newline
bitfld.long 0x00 1. "INTEN,Interrupt mask bit" "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor"
bitfld.long 0x00 0. "CHKEN,Enable for checking clock oscillation" "0: Stop clock monitor checking,1: Run clock monitor checking"
group.long 0x114++0x03
line.long 0x00 "S0D4MMCKMECR,It is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "CLRRES,Reference for clear command signal - S0D4MMCKMECR.CLRRES" "0: Release clear signal,1: Issue clear signal to clock monitor when clock"
group.long 0x118++0x03
line.long 0x00 "S0D4MMCKMLCH,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPH_23_0,The upper limit to judge as expected oscillation"
group.long 0x11C++0x03
line.long 0x00 "S0D4MMCKMLCL,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPL_23_0,The lower limit to judge as expected oscillation"
group.long 0x120++0x03
line.long 0x00 "S0D4MMCKMCNT,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNT_6_0,Monitoring S0D4MMCKMCNT.UPDCNT value"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,Monitoring S0D4MMCKMCNT.MONCNT value"
group.long 0x124++0x03
line.long 0x00 "S0D4MMCKMCNTE,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "VLD,Valid bit" "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNTE_6_0,S0D4MMCKMCNT.UPDCNT value when the first error occurred"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,The counter value of clock monitor when the first error occurred"
group.long 0x130++0x03
line.long 0x00 "ZB3CKMCSR,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "CHKRES,Check result" "0: Clock oscillates normally,1: Detect unexpected clock oscillation"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 24. "CLRMON,Reference for clear command signal - ZB3CKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued"
rbitfld.long 0x00 19.--23. "Reserved_19,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 18. "RSTMMON,Reset status for monitor clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
rbitfld.long 0x00 17. "RSTMSMP,Reset status for sampling clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
newline
rbitfld.long 0x00 16. "ENMON,Operating status" "0: Clock monitor is stopped,1: Clock monitor is operating"
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved"
newline
bitfld.long 0x00 1. "INTEN,Interrupt mask bit" "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor"
bitfld.long 0x00 0. "CHKEN,Enable for checking clock oscillation" "0: Stop clock monitor checking,1: Run clock monitor checking"
group.long 0x134++0x03
line.long 0x00 "ZB3CKMECR,It is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "CLRRES,Reference for clear command signal - ZB3CKMECR.CLRRES" "0: Release clear signal,1: Issue clear signal to clock monitor when clock"
group.long 0x138++0x03
line.long 0x00 "ZB3CKMLCH,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPH_23_0,The upper limit to judge as expected oscillation"
group.long 0x13C++0x03
line.long 0x00 "ZB3CKMLCL,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPL_23_0,The lower limit to judge as expected oscillation"
group.long 0x140++0x03
line.long 0x00 "ZB3CKMCNT,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNT_6_0,Monitoring ZB3CKMCNT.UPDCNT value"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,Monitoring ZB3CKMCNT.MONCNT value"
group.long 0x144++0x03
line.long 0x00 "ZB3CKMCNTE,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "VLD,Valid bit" "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNTE_6_0,ZB3CKMCNT.UPDCNT value when the first error occurred"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,The counter value of clock monitor when the first error occurred"
group.long 0x150++0x03
line.long 0x00 "ZB3D4CKMCSR,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "CHKRES,Check result" "0: Clock oscillates normally,1: Detect unexpected clock oscillation"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 24. "CLRMON,Reference for clear command signal - ZB3D4CKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued"
rbitfld.long 0x00 19.--23. "Reserved_19,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 18. "RSTMMON,Reset status for monitor clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
rbitfld.long 0x00 17. "RSTMSMP,Reset status for sampling clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
newline
rbitfld.long 0x00 16. "ENMON,Operating status" "0: Clock monitor is stopped,1: Clock monitor is operating"
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved"
newline
bitfld.long 0x00 1. "INTEN,Interrupt mask bit" "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor"
bitfld.long 0x00 0. "CHKEN,Enable for checking clock oscillation" "0: Stop clock monitor checking,1: Run clock monitor checking"
group.long 0x154++0x03
line.long 0x00 "ZB3D4CKMECR,It is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "CLRRES,Reference for clear command signal - ZB3D4CKMECR.CLRRES" "0: Release clear signal,1: Issue clear signal to clock monitor when clock"
group.long 0x158++0x03
line.long 0x00 "ZB3D4CKMLCH,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPH_23_0,The upper limit to judge as expected oscillation"
group.long 0x15C++0x03
line.long 0x00 "ZB3D4CKMLCL,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPL_23_0,The lower limit to judge as expected oscillation"
group.long 0x160++0x03
line.long 0x00 "ZB3D4CKMCNT,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNT_6_0,Monitoring ZB3D4CKMCNT.UPDCNT value"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,Monitoring ZB3D4CKMCNT.MONCNT value"
group.long 0x164++0x03
line.long 0x00 "ZB3D4CKMCNTE,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "VLD,Valid bit" "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNTE_6_0,ZB3D4CKMCNT.UPDCNT value when the first error occurred"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,The counter value of clock monitor when the first error occurred"
group.long 0x170++0x03
line.long 0x00 "CBFUSAMMCKMCSR,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "CHKRES,Check result" "0: Clock oscillates normally,1: Detect unexpected clock oscillation"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 24. "CLRMON,Reference for clear command signal - CBFUSAMMCKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued"
rbitfld.long 0x00 19.--23. "Reserved_19,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 18. "RSTMMON,Reset status for monitor clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
rbitfld.long 0x00 17. "RSTMSMP,Reset status for sampling clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
newline
rbitfld.long 0x00 16. "ENMON,Operating status" "0: Clock monitor is stopped,1: Clock monitor is operating"
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved"
newline
bitfld.long 0x00 1. "INTEN,Interrupt mask bit" "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor"
bitfld.long 0x00 0. "CHKEN,Enable for checking clock oscillation" "0: Stop clock monitor checking,1: Run clock monitor checking"
group.long 0x174++0x03
line.long 0x00 "CBFUSAMMCKMECR,It is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "CLRRES,Reference for clear command signal - CBFUSAMMCKMECR.CLRRES" "0: Release clear signal,1: Issue clear signal to clock monitor when clock"
group.long 0x178++0x03
line.long 0x00 "CBFUSAMMCKMLCH,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPH_23_0,The upper limit to judge as expected oscillation"
group.long 0x17C++0x03
line.long 0x00 "CBFUSAMMCKMLCL,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPL_23_0,The lower limit to judge as expected oscillation"
group.long 0x180++0x03
line.long 0x00 "CBFUSAMMCKMCNT,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNT_6_0,Monitoring CBFUSAMMCKMCNT.UPDCNT value"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,Monitoring CBFUSAMMCKMCNT.MONCNT value"
group.long 0x184++0x03
line.long 0x00 "CBFUSAMMCKMCNTE,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "VLD,Valid bit" "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNTE_6_0,CBFUSAMMCKMCNT.UPDCNT value when the first error occurred"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,The counter value of clock monitor when the first error occurred"
group.long 0x190++0x03
line.long 0x00 "RCLKMMCKMCSR,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "CHKRES,Check result" "0: Clock oscillates normally,1: Detect unexpected clock oscillation"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 24. "CLRMON,Reference for clear command signal - RCLKMMCKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued"
rbitfld.long 0x00 19.--23. "Reserved_19,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 18. "RSTMMON,Reset status for monitor clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
rbitfld.long 0x00 17. "RSTMSMP,Reset status for sampling clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
newline
rbitfld.long 0x00 16. "ENMON,Operating status" "0: Clock monitor is stopped,1: Clock monitor is operating"
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved"
newline
bitfld.long 0x00 1. "INTEN,Interrupt mask bit" "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor"
bitfld.long 0x00 0. "CHKEN,Enable for checking clock oscillation" "0: Stop clock monitor checking,1: Run clock monitor checking"
group.long 0x194++0x03
line.long 0x00 "RCLKMMCKMECR,It is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "CLRRES,Reference for clear command signal - RCLKMMCKMECR.CLRRES" "0: Release clear signal,1: Issue clear signal to clock monitor when clock"
group.long 0x198++0x03
line.long 0x00 "RCLKMMCKMLCH,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPH_23_0,The upper limit to judge as expected oscillation"
group.long 0x19C++0x03
line.long 0x00 "RCLKMMCKMLCL,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPL_23_0,The lower limit to judge as expected oscillation"
group.long 0x1A0++0x03
line.long 0x00 "RCLKMMCKMCNT,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNT_6_0,Monitoring RCLKMMCKMCNT.UPDCNT value"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,Monitoring RCLKMMCKMCNT.MONCNT value"
group.long 0x1A4++0x03
line.long 0x00 "RCLKMMCKMCNTE,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "VLD,Valid bit" "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNTE_6_0,RCLKMMCKMCNT.UPDCNT value when the first error occurred"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,The counter value of clock monitor when the first error occurred"
tree.end
tree "CLOCK_PULSE_GENERATOR_CPG_INST_5"
base ad:0xE6070000
group.long 0x00++0x03
line.long 0x00 "TOPCKMWPR,It is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "WPRTCT_31_0,The specification is same as 8.2.1 CPG Write Protect Register (CPGWPR)"
group.long 0x04++0x03
line.long 0x00 "TOPCKMWPCR,It is a 32-bit readable/writable register"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,The specification is same as 8.2.2 CPG Write Protect Register (CPGWPCR)"
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,The specification is same as 8.2.2 CPG Write Protect Register (CPGWPCR)"
newline
bitfld.long 0x00 0. "WPE,The specification is same as 8.2.2 CPG Write Protect Register (CPGWPCR)" "0,1"
group.long 0xF0++0x03
line.long 0x00 "CLCKMCSR,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "CHKRES,Check result" "0: Clock oscillates normally,1: Detect unexpected clock oscillation"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 24. "CLRMON,Reference for clear command signal - CLCKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued"
rbitfld.long 0x00 19.--23. "Reserved_19,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 18. "RSTMMON,Reset status for monitor clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
rbitfld.long 0x00 17. "RSTMSMP,Reset status for sampling clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
newline
rbitfld.long 0x00 16. "ENMON,Operating status" "0: Clock monitor is stopped,1: Clock monitor is operating"
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved"
newline
bitfld.long 0x00 1. "INTEN,Interrupt mask bit" "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor"
bitfld.long 0x00 0. "CHKEN,Enable for checking clock oscillation" "0: Stop clock monitor checking,1: Run clock monitor checking"
group.long 0xF4++0x03
line.long 0x00 "CLCKMECR,It is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "CLRRES,Reference for clear command signal - CLCKMECR.CLRRES" "0: Release clear signal,1: Issue clear signal to clock monitor when clock"
group.long 0xF8++0x03
line.long 0x00 "CLCKMLCH,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPH_23_0,The upper limit to judge as expected oscillation"
group.long 0xFC++0x03
line.long 0x00 "CLCKMLCL,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPL_23_0,The lower limit to judge as expected oscillation"
group.long 0x100++0x03
line.long 0x00 "CLCKMCNT,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNT_6_0,Monitoring CLCKMCNT.UPDCNT value"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,Monitoring CLCKMCNT.MONCNT value"
group.long 0x104++0x03
line.long 0x00 "CLCKMCNTE,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "VLD,Valid bit" "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNTE_6_0,CLCKMCNT.UPDCNT value when the first error occurred"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,The counter value of clock monitor when the first error occurred"
group.long 0x1B0++0x03
line.long 0x00 "RCLKTOPCKMCSR,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "CHKRES,Check result" "0: Clock oscillates normally,1: Detect unexpected clock oscillation"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 24. "CLRMON,Reference for clear command signal - RCLKTOPCKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued"
rbitfld.long 0x00 19.--23. "Reserved_19,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 18. "RSTMMON,Reset status for monitor clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
rbitfld.long 0x00 17. "RSTMSMP,Reset status for sampling clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
newline
rbitfld.long 0x00 16. "ENMON,Operating status" "0: Clock monitor is stopped,1: Clock monitor is operating"
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved"
newline
bitfld.long 0x00 1. "INTEN,Interrupt mask bit" "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor"
bitfld.long 0x00 0. "CHKEN,Enable for checking clock oscillation" "0: Stop clock monitor checking,1: Run clock monitor checking"
group.long 0x1B4++0x03
line.long 0x00 "RCLKTOPCKMECR,It is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "CLRRES,Reference for clear command signal - RCLKTOPCKMECR.CLRRES" "0: Release clear signal,1: Issue clear signal to clock monitor when clock"
group.long 0x1B8++0x03
line.long 0x00 "RCLKTOPCKMLCH,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPH_23_0,The upper limit to judge as expected oscillation"
group.long 0x1BC++0x03
line.long 0x00 "RCLKTOPCKMLCL,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPL_23_0,The lower limit to judge as expected oscillation"
group.long 0x1C0++0x03
line.long 0x00 "RCLKTOPCKMCNT,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNT_6_0,Monitoring RCLKTOPCKMCNT.UPDCNT value"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,Monitoring RCLKTOPCKMCNT.MONCNT value"
group.long 0x1C4++0x03
line.long 0x00 "RCLKTOPCKMCNTE,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "VLD,Valid bit" "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNTE_6_0,RCLKTOPCKMCNT.UPDCNT value when the first error occurred"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,The counter value of clock monitor when the first error occurred"
group.long 0x1D0++0x03
line.long 0x00 "CPEXCKMCSR,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "CHKRES,Check result" "0: Clock oscillates normally,1: Detect unexpected clock oscillation"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 24. "CLRMON,Reference for clear command signal - CPEXCKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued"
rbitfld.long 0x00 19.--23. "Reserved_19,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 18. "RSTMMON,Reset status for monitor clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
rbitfld.long 0x00 17. "RSTMSMP,Reset status for sampling clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
newline
rbitfld.long 0x00 16. "ENMON,Operating status" "0: Clock monitor is stopped,1: Clock monitor is operating"
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved"
newline
bitfld.long 0x00 1. "INTEN,Interrupt mask bit" "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor"
bitfld.long 0x00 0. "CHKEN,Enable for checking clock oscillation" "0: Stop clock monitor checking,1: Run clock monitor checking"
group.long 0x1D4++0x03
line.long 0x00 "CPEXCKMECR,It is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "CLRRES,Reference for clear command signal - CPEXCKMECR.CLRRES" "0: Release clear signal,1: Issue clear signal to clock monitor when clock"
group.long 0x1D8++0x03
line.long 0x00 "CPEXCKMLCH,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPH_23_0,The upper limit to judge as expected oscillation"
group.long 0x1DC++0x03
line.long 0x00 "CPEXCKMLCL,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPL_23_0,The lower limit to judge as expected oscillation"
group.long 0x1E0++0x03
line.long 0x00 "CPEXCKMCNT,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNT_6_0,Monitoring CPEXCKMCNT.UPDCNT value"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,Monitoring CPEXCKMCNT.MONCNT value"
group.long 0x1E4++0x03
line.long 0x00 "CPEXCKMCNTE,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "VLD,Valid bit" "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNTE_6_0,CPEXCKMCNT.UPDCNT value when the first error occurred"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,The counter value of clock monitor when the first error occurred"
group.long 0x1F0++0x03
line.long 0x00 "CBFUSATOPCKMCSR,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "CHKRES,Check result" "0: Clock oscillates normally,1: Detect unexpected clock oscillation"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 24. "CLRMON,Reference for clear command signal - CBFUSATOPCKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued"
rbitfld.long 0x00 19.--23. "Reserved_19,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 18. "RSTMMON,Reset status for monitor clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
rbitfld.long 0x00 17. "RSTMSMP,Reset status for sampling clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
newline
rbitfld.long 0x00 16. "ENMON,Operating status" "0: Clock monitor is stopped,1: Clock monitor is operating"
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved"
newline
bitfld.long 0x00 1. "INTEN,Interrupt mask bit" "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor"
bitfld.long 0x00 0. "CHKEN,Enable for checking clock oscillation" "0: Stop clock monitor checking,1: Run clock monitor checking"
group.long 0x1F4++0x03
line.long 0x00 "CBFUSATOPCKMECR,It is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "CLRRES,Reference for clear command signal - CBFUSATOPCKMECR.CLRRES" "0: Release clear signal,1: Issue clear signal to clock monitor when clock"
group.long 0x1F8++0x03
line.long 0x00 "CBFUSATOPCKMLCH,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPH_23_0,The upper limit to judge as expected oscillation"
group.long 0x1FC++0x03
line.long 0x00 "CBFUSATOPCKMLCL,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPL_23_0,The lower limit to judge as expected oscillation"
group.long 0x200++0x03
line.long 0x00 "CBFUSATOPCKMCNT,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNT_6_0,Monitoring CBFUSATOPCKMCNT.UPDCNT value"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,Monitoring CBFUSATOPCKMCNT.MONCNT value"
group.long 0x204++0x03
line.long 0x00 "CBFUSATOPCKMCNTE,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "VLD,Valid bit" "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNTE_6_0,CBFUSATOPCKMCNT.UPDCNT value when the first error occurred"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,The counter value of clock monitor when the first error occurred"
group.long 0x210++0x03
line.long 0x00 "TOPACKMSR,It is a 32-bit readable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved" "0,1"
rbitfld.long 0x00 30. "Reserved_30,Reserved" "0,1"
newline
rbitfld.long 0x00 29. "Reserved_29,Reserved" "0,1"
rbitfld.long 0x00 28. "Reserved_28,Reserved" "0,1"
newline
rbitfld.long 0x00 27. "Reserved_27,Reserved" "0,1"
rbitfld.long 0x00 26. "Reserved_26,Reserved" "0,1"
newline
rbitfld.long 0x00 25. "Reserved_25,Reserved" "0,1"
rbitfld.long 0x00 24. "CHKRES024,CL16M" "0,1"
newline
rbitfld.long 0x00 23. "CHKRES023,ZX" "0,1"
rbitfld.long 0x00 22. "Reserved_22,Reserved" "0,1"
newline
rbitfld.long 0x00 21. "Reserved_21,Reserved" "0,1"
rbitfld.long 0x00 20. "Reserved_20,Reserved" "0,1"
newline
rbitfld.long 0x00 19. "CHKRES019,S0D4" "0,1"
rbitfld.long 0x00 18. "CHKRES018,S0D3" "0,1"
newline
rbitfld.long 0x00 17. "CHKRES017,S0D2" "0,1"
rbitfld.long 0x00 16. "Reserved_16,Reserved" "0,1"
newline
rbitfld.long 0x00 15. "CHKRES015,CBFUSA" "0,1"
rbitfld.long 0x00 14. "CHKRES014,CPEX" "0,1"
newline
rbitfld.long 0x00 13. "CHKRES013,RCLK" "0,1"
rbitfld.long 0x00 12. "CHKRES012,Reserved" "0,1"
newline
rbitfld.long 0x00 11. "Reserved_11,Reserved" "0,1"
rbitfld.long 0x00 10. "Reserved_10,Reserved" "0,1"
newline
rbitfld.long 0x00 9. "Reserved_9,Reserved" "0,1"
rbitfld.long 0x00 8. "Reserved_8,Reserved" "0,1"
newline
rbitfld.long 0x00 7. "CHKRES007,CL" "0,1"
rbitfld.long 0x00 6. "Reserved_6,Reserved" "0,1"
newline
rbitfld.long 0x00 5. "Reserved_5,Reserved" "0,1"
rbitfld.long 0x00 4. "Reserved_4,Reserved" "0,1"
newline
rbitfld.long 0x00 3. "Reserved_3,Reserved" "0,1"
rbitfld.long 0x00 2. "Reserved_2,Reserved" "0,1"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved" "0,1"
rbitfld.long 0x00 0. "Reserved_0,Reserved" "0,1"
group.long 0x240++0x03
line.long 0x00 "S0D2CKMCSR,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "CHKRES,Check result" "0: Clock oscillates normally,1: Detect unexpected clock oscillation"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 24. "CLRMON,Reference for clear command signal - S0D2CKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued"
rbitfld.long 0x00 19.--23. "Reserved_19,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 18. "RSTMMON,Reset status for monitor clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
rbitfld.long 0x00 17. "RSTMSMP,Reset status for sampling clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
newline
rbitfld.long 0x00 16. "ENMON,Operating status" "0: Clock monitor is stopped,1: Clock monitor is operating"
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved"
newline
bitfld.long 0x00 1. "INTEN,Interrupt mask bit" "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor"
bitfld.long 0x00 0. "CHKEN,Enable for checking clock oscillation" "0: Stop clock monitor checking,1: Run clock monitor checking"
group.long 0x244++0x03
line.long 0x00 "S0D2CKMECR,It is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "CLRRES,Reference for clear command signal - S0D2CKMECR.CLRRES" "0: Release clear signal,1: Issue clear signal to clock monitor when clock"
group.long 0x248++0x03
line.long 0x00 "S0D2CKMLCH,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPH_23_0,The upper limit to judge as expected oscillation"
group.long 0x24C++0x03
line.long 0x00 "S0D2CKMLCL,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPL_23_0,The lower limit to judge as expected oscillation"
group.long 0x250++0x03
line.long 0x00 "S0D2CKMCNT,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNT_6_0,Monitoring S0D2CKMCNT.UPDCNT value"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,Monitoring S0D2CKMCNT.MONCNT value"
group.long 0x254++0x03
line.long 0x00 "S0D2CKMCNTE,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "VLD,Valid bit" "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNTE_6_0,S0D2CKMCNT.UPDCNT value when the first error occurred"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,The counter value of clock monitor when the first error occurred"
group.long 0x260++0x03
line.long 0x00 "S0D3CKMCSR,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "CHKRES,Check result" "0: Clock oscillates normally,1: Detect unexpected clock oscillation"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 24. "CLRMON,Reference for clear command signal - S0D3CKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued"
rbitfld.long 0x00 19.--23. "Reserved_19,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 18. "RSTMMON,Reset status for monitor clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
rbitfld.long 0x00 17. "RSTMSMP,Reset status for sampling clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
newline
rbitfld.long 0x00 16. "ENMON,Operating status" "0: Clock monitor is stopped,1: Clock monitor is operating"
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved"
newline
bitfld.long 0x00 1. "INTEN,Interrupt mask bit" "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor"
bitfld.long 0x00 0. "CHKEN,Enable for checking clock oscillation" "0: Stop clock monitor checking,1: Run clock monitor checking"
group.long 0x264++0x03
line.long 0x00 "S0D3CKMECR,It is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "CLRRES,Reference for clear command signal - S0D3CKMECR.CLRRES" "0: Release clear signal,1: Issue clear signal to clock monitor when clock"
group.long 0x268++0x03
line.long 0x00 "S0D3CKMLCH,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPH_23_0,The upper limit to judge as expected oscillation"
group.long 0x26C++0x03
line.long 0x00 "S0D3CKMLCL,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPL_23_0,The lower limit to judge as expected oscillation"
group.long 0x270++0x03
line.long 0x00 "S0D3CKMCNT,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNT_6_0,Monitoring S0D3CKMCNT.UPDCNT value"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,Monitoring S0D3CKMCNT.MONCNT value"
group.long 0x274++0x03
line.long 0x00 "S0D3CKMCNTE,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "VLD,Valid bit" "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNTE_6_0,S0D3CKMCNT.UPDCNT value when the first error occurred"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,The counter value of clock monitor when the first error occurred"
group.long 0x280++0x03
line.long 0x00 "S0D4CKMCSR,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "CHKRES,Check result" "0: Clock oscillates normally,1: Detect unexpected clock oscillation"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 24. "CLRMON,Reference for clear command signal - S0D4CKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued"
rbitfld.long 0x00 19.--23. "Reserved_19,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 18. "RSTMMON,Reset status for monitor clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
rbitfld.long 0x00 17. "RSTMSMP,Reset status for sampling clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
newline
rbitfld.long 0x00 16. "ENMON,Operating status" "0: Clock monitor is stopped,1: Clock monitor is operating"
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved"
newline
bitfld.long 0x00 1. "INTEN,Interrupt mask bit" "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor"
bitfld.long 0x00 0. "CHKEN,Enable for checking clock oscillation" "0: Stop clock monitor checking,1: Run clock monitor checking"
group.long 0x284++0x03
line.long 0x00 "S0D4CKMECR,It is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "CLRRES,Reference for clear command signal - S0D4CKMECR.CLRRES" "0: Release clear signal,1: Issue clear signal to clock monitor when clock"
group.long 0x288++0x03
line.long 0x00 "S0D4CKMLCH,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPH_23_0,The upper limit to judge as expected oscillation"
group.long 0x28C++0x03
line.long 0x00 "S0D4CKMLCL,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPL_23_0,The lower limit to judge as expected oscillation"
group.long 0x290++0x03
line.long 0x00 "S0D4CKMCNT,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNT_6_0,Monitoring S0D4CKMCNT.UPDCNT value"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,Monitoring S0D4CKMCNT.MONCNT value"
group.long 0x294++0x03
line.long 0x00 "S0D4CKMCNTE,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "VLD,Valid bit" "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNTE_6_0,S0D4CKMCNT.UPDCNT value when the first error occurred"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,The counter value of clock monitor when the first error occurred"
group.long 0x300++0x03
line.long 0x00 "ZXCKMCSR,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "CHKRES,Check result" "0: Clock oscillates normally,1: Detect unexpected clock oscillation"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 24. "CLRMON,Reference for clear command signal - ZXCKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued"
rbitfld.long 0x00 19.--23. "Reserved_19,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 18. "RSTMMON,Reset status for monitor clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
rbitfld.long 0x00 17. "RSTMSMP,Reset status for sampling clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
newline
rbitfld.long 0x00 16. "ENMON,Operating status" "0: Clock monitor is stopped,1: Clock monitor is operating"
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved"
newline
bitfld.long 0x00 1. "INTEN,Interrupt mask bit" "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor"
bitfld.long 0x00 0. "CHKEN,Enable for checking clock oscillation" "0: Stop clock monitor checking,1: Run clock monitor checking"
group.long 0x304++0x03
line.long 0x00 "ZXCKMECR,It is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "CLRRES,Reference for clear command signal - ZXCKMECR.CLRRES" "0: Release clear signal,1: Issue clear signal to clock monitor when clock"
group.long 0x308++0x03
line.long 0x00 "ZXCKMLCH,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPH_23_0,The upper limit to judge as expected oscillation"
group.long 0x30C++0x03
line.long 0x00 "ZXCKMLCL,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPL_23_0,The lower limit to judge as expected oscillation"
group.long 0x310++0x03
line.long 0x00 "ZXCKMCNT,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNT_6_0,Monitoring ZXCKMCNT.UPDCNT value"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,Monitoring ZXCKMCNT.MONCNT value"
group.long 0x314++0x03
line.long 0x00 "ZXCKMCNTE,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "VLD,Valid bit" "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNTE_6_0,ZXCKMCNT.UPDCNT value when the first error occurred"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,The counter value of clock monitor when the first error occurred"
group.long 0x320++0x03
line.long 0x00 "CL16MCKMCSR,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "CHKRES,Check result" "0: Clock oscillates normally,1: Detect unexpected clock oscillation"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 24. "CLRMON,Reference for clear command signal - CL16MCKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued"
rbitfld.long 0x00 19.--23. "Reserved_19,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 18. "RSTMMON,Reset status for monitor clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
rbitfld.long 0x00 17. "RSTMSMP,Reset status for sampling clock domain of clock monitor module" "0: Reset signal is issued,1: Reset signal is released"
newline
rbitfld.long 0x00 16. "ENMON,Operating status" "0: Clock monitor is stopped,1: Clock monitor is operating"
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved"
newline
bitfld.long 0x00 1. "INTEN,Interrupt mask bit" "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor"
bitfld.long 0x00 0. "CHKEN,Enable for checking clock oscillation" "0: Stop clock monitor checking,1: Run clock monitor checking"
group.long 0x324++0x03
line.long 0x00 "CL16MCKMECR,It is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "CLRRES,Reference for clear command signal - CL16MCKMECR.CLRRES" "0: Release clear signal,1: Issue clear signal to clock monitor when clock"
group.long 0x328++0x03
line.long 0x00 "CL16MCKMLCH,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPH_23_0,The upper limit to judge as expected oscillation"
group.long 0x32C++0x03
line.long 0x00 "CL16MCKMLCL,It is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPL_23_0,The lower limit to judge as expected oscillation"
group.long 0x330++0x03
line.long 0x00 "CL16MCKMCNT,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNT_6_0,Monitoring CL16MCKMCNT.UPDCNT value"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,Monitoring CL16MCKMCNT.MONCNT value"
group.long 0x334++0x03
line.long 0x00 "CL16MCKMCNTE,It is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "VLD,Valid bit" "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value"
hexmask.long.byte 0x00 24.--30. 1. "UPDCNTE_6_0,CL16MCKMCNT.UPDCNT value when the first error occurred"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MONCNTE_23_0,The counter value of clock monitor when the first error occurred"
tree.end
tree.end
tree "MODULE_STANDBY_SOFTWARE_RESET"
base ad:0xE6152C00
group.long 0x00++0x03
line.long 0x00 "SRCR0,SRCRn is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "Reserved_0,Reserved"
group.long 0x04++0x03
line.long 0x00 "SRCR1,SRCRn is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
bitfld.long 0x00 23. "SRT023,ADVFS Controller (K-Sensor)" "0,1"
hexmask.long.tbyte 0x00 0.--22. 1. "Reserved_0,Reserved"
group.long 0x08++0x03
line.long 0x00 "SRCR2,SRCRn is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "Reserved_0,Reserved"
group.long 0x0C++0x03
line.long 0x00 "SRCR3,SRCRn is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved" "0,1"
bitfld.long 0x00 30. "SRT030,CoreSight Debug Block" "0,1"
bitfld.long 0x00 29. "SRT029,Crypto Engine" "0,1"
hexmask.long 0x00 0.--28. 1. "Reserved_0,Reserved"
group.long 0x10++0x03
line.long 0x00 "SRCR4,SRCRn is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 10.--31. 1. "Reserved_10,Reserved"
bitfld.long 0x00 9. "SRT009,LPDDR4X / LPDDR4" "0,1"
hexmask.long.word 0x00 0.--8. 1. "Reserved_0,Reserved"
group.long 0x14++0x03
line.long 0x00 "SRCR5,SRCRn is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
bitfld.long 0x00 23. "SRT023,I2C channel 5" "0,1"
bitfld.long 0x00 22. "SRT022,I2C channel 4" "0,1"
bitfld.long 0x00 21. "SRT021,I2C channel 3" "0,1"
bitfld.long 0x00 20. "SRT020,I2C channel 2" "0,1"
bitfld.long 0x00 19. "SRT019,I2C channel 1" "0,1"
bitfld.long 0x00 18. "SRT018,I2C channel 0" "0,1"
newline
bitfld.long 0x00 17. "SRT017,HSCIF channel 3" "0,1"
bitfld.long 0x00 16. "SRT016,HSCIF channel 2" "0,1"
bitfld.long 0x00 15. "SRT015,HSCIF channel 1" "0,1"
bitfld.long 0x00 14. "SRT014,HSCIF channel 0" "0,1"
hexmask.long.word 0x00 0.--13. 1. "Reserved_0,Reserved"
group.long 0x18++0x03
line.long 0x00 "SRCR6,SRCRn is a 32-bit readable/writable register"
bitfld.long 0x00 31. "SRT031,RT-DMAC channel 1" "0,1"
bitfld.long 0x00 30. "SRT030,RT-DMAC channel 1" "0,1"
bitfld.long 0x00 29. "SRT029,RPC" "0,1"
rbitfld.long 0x00 26.--28. "Reserved_26,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 25. "SRT025,PCIEC ch0 Application/Local register reset" "0,1"
bitfld.long 0x00 24. "SRT024,PCIEC ch0 Cold-reset" "0,1"
rbitfld.long 0x00 22.--23. "Reserved_22,Reserved" "0,1,2,3"
newline
bitfld.long 0x00 21. "SRT021,MSIOF channel 3 (MSIOF3)" "0,1"
bitfld.long 0x00 20. "SRT020,MSIOF channel 2 (MSIOF2)" "0,1"
bitfld.long 0x00 19. "SRT019,MSIOF channel 1 (MSIOF1)" "0,1"
bitfld.long 0x00 18. "SRT018,MSIOF channel 0 (MSIOF0)" "0,1"
hexmask.long.tbyte 0x00 0.--17. 1. "Reserved_0,Reserved"
group.long 0x1C++0x03
line.long 0x00 "SRCR7,SRCRn is a 32-bit readable/writable register"
hexmask.long.word 0x00 18.--31. 1. "Reserved_18,Reserved"
bitfld.long 0x00 17. "SRT017,TMU channel 4" "0,1"
bitfld.long 0x00 16. "SRT016,TMU channel 3" "0,1"
bitfld.long 0x00 15. "SRT015,TMU channel 2" "0,1"
bitfld.long 0x00 14. "SRT014,TMU channel 1" "0,1"
bitfld.long 0x00 13. "SRT013,TMU channel 0" "0,1"
rbitfld.long 0x00 11.--12. "Reserved_11,Reserved" "0,1,2,3"
newline
bitfld.long 0x00 10. "SRT010,SYS-DMAC1" "0,1"
bitfld.long 0x00 9. "SRT009,SYS-DMAC0" "0,1"
rbitfld.long 0x00 8. "Reserved_8,Reserved" "0,1"
bitfld.long 0x00 7. "SRT007,Secure ROM" "0,1"
bitfld.long 0x00 6. "SRT006,SDHI" "0,1"
bitfld.long 0x00 5. "SRT005,SCIF-4" "0,1"
bitfld.long 0x00 4. "SRT004,SCIF-3" "0,1"
newline
bitfld.long 0x00 3. "SRT003,SCIF-1" "0,1"
bitfld.long 0x00 2. "SRT002,SCIF-0" "0,1"
bitfld.long 0x00 1. "SRT001,RT-DMAC3" "0,1"
bitfld.long 0x00 0. "SRT000,RT-DMAC2" "0,1"
group.long 0x20++0x03
line.long 0x00 "SRCR8,SRCRn is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "Reserved_0,Reserved"
group.long 0x24++0x03
line.long 0x00 "SRCR9,SRCRn is a 32-bit readable/writable register"
hexmask.long.word 0x00 21.--31. 1. "Reserved_21,Reserved"
bitfld.long 0x00 20. "SRT020,SUCMT" "0,1"
bitfld.long 0x00 19. "SRT019,TSC4 TSC3 TSC2 TSC1" "0,1"
rbitfld.long 0x00 16.--18. "Reserved_16,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 15. "SRT015,PFC0" "0,1"
rbitfld.long 0x00 14. "Reserved_14,Reserved" "0,1"
bitfld.long 0x00 13. "SRT013,CMT3" "0,1"
newline
bitfld.long 0x00 12. "SRT012,CMT2" "0,1"
bitfld.long 0x00 11. "SRT011,CMT1" "0,1"
bitfld.long 0x00 10. "SRT010,CMT0" "0,1"
rbitfld.long 0x00 8.--9. "Reserved_8,Reserved" "0,1,2,3"
bitfld.long 0x00 7. "SRT007,WDT" "0,1"
bitfld.long 0x00 6. "SRT006,WCRC3" "0,1"
bitfld.long 0x00 5. "SRT005,WCRC2" "0,1"
newline
bitfld.long 0x00 4. "SRT004,WCRC1" "0,1"
bitfld.long 0x00 3. "SRT003,WCRC0" "0,1"
rbitfld.long 0x00 0.--2. "Reserved_0,Reserved" "0,1,2,3,4,5,6,7"
group.long 0x28++0x03
line.long 0x00 "SRCR10,SRCRn is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "Reserved_0,Reserved"
group.long 0x2C++0x03
line.long 0x00 "SRCR11,SRCRn is a 32-bit readable/writable register"
rbitfld.long 0x00 29.--31. "Reserved_29,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 28. "SRT028,SWDT" "0,1"
rbitfld.long 0x00 23.--27. "Reserved_23,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 22. "SRT022,PCIEC ch1 Application/Local register reset" "0,1"
bitfld.long 0x00 21. "SRT021,PCIEC ch1 Cold-reset" "0,1"
hexmask.long.word 0x00 7.--20. 1. "Reserved_7,Reserved"
bitfld.long 0x00 6. "SRT006,Aurora links (using 2-lane PCIE physical unit)" "0,1"
newline
rbitfld.long 0x00 0.--5. "Reserved_0,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x30++0x03
line.long 0x00 "SRCR12,SRCRn is a 32-bit readable/writable register"
hexmask.long.word 0x00 23.--31. 1. "Reserved_23,Reserved"
bitfld.long 0x00 22. "SRT022,SCMT" "0,1"
hexmask.long.word 0x00 13.--21. 1. "Reserved_13,Reserved"
bitfld.long 0x00 12. "SRT012,PFC Bus Domain3 (GPIO Group 0 1 2 3 shown in Table 7.2)" "0,1"
bitfld.long 0x00 11. "SRT011,PFC Bus Domain2 (GPIO Group 0 1 2 3 shown in Table 7.2)" "0,1"
bitfld.long 0x00 10. "SRT010,PFC Bus Domain1 (GPIO Group 0 1 2 3 shown in Table 7.2)" "0,1"
bitfld.long 0x00 9. "SRT009,WWDT9 for circuits with RCLK" "0,1"
newline
bitfld.long 0x00 8. "SRT008,WWDT8 for circuits with RCLK" "0,1"
bitfld.long 0x00 7. "SRT007,WWDT7 for circuits with RCLK" "0,1"
bitfld.long 0x00 6. "SRT006,WWDT6 for circuits with RCLK" "0,1"
bitfld.long 0x00 5. "SRT005,WWDT5 for circuits with RCLK" "0,1"
bitfld.long 0x00 4. "SRT004,WWDT4 for circuits with RCLK" "0,1"
bitfld.long 0x00 3. "SRT003,WWDT3 for circuits with RCLK" "0,1"
bitfld.long 0x00 2. "SRT002,WWDT2 for circuits with RCLK" "0,1"
newline
bitfld.long 0x00 1. "SRT001,WWDT1 for circuits with RCLK" "0,1"
bitfld.long 0x00 0. "SRT000,WWDT0 for circuits with RCLK" "0,1"
group.long 0x34++0x03
line.long 0x00 "SRCR13,SRCRn is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "Reserved_0,Reserved"
group.long 0x38++0x03
line.long 0x00 "SRCR14,SRCRn is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved"
bitfld.long 0x00 12. "SRT012,Clock Monitor in Main Memory domain shown in 8.5.2.5" "0,1"
rbitfld.long 0x00 7.--11. "Reserved_7,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 6. "SRT006,Clock Monitor in Peripheral (PeriE/PeriW) domain shown in 8.5.2.2" "0,1"
bitfld.long 0x00 5. "SRT005,Clock Monitor in RT (Real Time) domain shown in 8.5.2.4" "0,1"
rbitfld.long 0x00 0.--4. "Reserved_0,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x3C++0x03
line.long 0x00 "SRCR15,SRCRn is a 32-bit readable/writable register"
hexmask.long.word 0x00 18.--31. 1. "Reserved_18,Reserved"
bitfld.long 0x00 17. "SRT017,Clock Monitor in Slave Access Bus domain" "0,1"
bitfld.long 0x00 16. "SRT016,Clock Monitor in HC (High speed Communication) domain bus" "0,1"
bitfld.long 0x00 15. "SRT015,Clock Monitor in RT (Real Time) domain shown in 8.5.2.4" "0,1"
bitfld.long 0x00 14. "SRT014,UFS" "0,1"
hexmask.long.byte 0x00 7.--13. 1. "Reserved_7,Reserved"
bitfld.long 0x00 6. "SRT006,EtherTSN-IF" "0,1"
newline
bitfld.long 0x00 5. "SRT005,RSwitch2" "0,1"
rbitfld.long 0x00 0.--4. "Reserved_0,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
repeat 12. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C )
group.long ($2+0x40)++0x03
line.long 0x00 "SRCR$1,SRCRn is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "Reserved_0,Reserved"
repeat.end
group.long 0x80++0x03
line.long 0x00 "SRSTCLR0,Each SRSTCLRn is a 32-bit writable register"
hexmask.long 0x00 0.--31. 1. "Reserved_0,Reserved"
group.long 0x84++0x03
line.long 0x00 "SRSTCLR1,Each SRSTCLRn is a 32-bit writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
bitfld.long 0x00 23. "SRT023,ADVFS Controller (K-Sensor)" "0,1"
hexmask.long.tbyte 0x00 0.--22. 1. "Reserved_0,Reserved"
group.long 0x88++0x03
line.long 0x00 "SRSTCLR2,Each SRSTCLRn is a 32-bit writable register"
hexmask.long 0x00 0.--31. 1. "Reserved_0,Reserved"
group.long 0x8C++0x03
line.long 0x00 "SRSTCLR3,Each SRSTCLRn is a 32-bit writable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved" "0,1"
bitfld.long 0x00 30. "SRT030,CoreSight Debug Block" "0,1"
bitfld.long 0x00 29. "SRT029,Crypto Engine" "0,1"
hexmask.long 0x00 0.--28. 1. "Reserved_0,Reserved"
group.long 0x90++0x03
line.long 0x00 "SRSTCLR4,Each SRSTCLRn is a 32-bit writable register"
hexmask.long.tbyte 0x00 10.--31. 1. "Reserved_10,Reserved"
bitfld.long 0x00 9. "SRT009,LPDDR4X / LPDDR4" "0,1"
hexmask.long.word 0x00 0.--8. 1. "Reserved_0,Reserved"
group.long 0x94++0x03
line.long 0x00 "SRSTCLR5,Each SRSTCLRn is a 32-bit writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
bitfld.long 0x00 23. "SRT023,I2C channel 5" "0,1"
bitfld.long 0x00 22. "SRT022,I2C channel 4" "0,1"
bitfld.long 0x00 21. "SRT021,I2C channel 3" "0,1"
bitfld.long 0x00 20. "SRT020,I2C channel 2" "0,1"
bitfld.long 0x00 19. "SRT019,I2C channel 1" "0,1"
bitfld.long 0x00 18. "SRT018,I2C channel 0" "0,1"
newline
bitfld.long 0x00 17. "SRT017,HSCIF channel 3" "0,1"
bitfld.long 0x00 16. "SRT016,HSCIF channel 2" "0,1"
bitfld.long 0x00 15. "SRT015,HSCIF channel 1" "0,1"
bitfld.long 0x00 14. "SRT014,HSCIF channel 0" "0,1"
hexmask.long.word 0x00 0.--13. 1. "Reserved_0,Reserved"
group.long 0x98++0x03
line.long 0x00 "SRSTCLR6,Each SRSTCLRn is a 32-bit writable register"
bitfld.long 0x00 31. "SRT031,RT-DMAC channel 1" "0,1"
bitfld.long 0x00 30. "SRT030,RT-DMAC channel 1" "0,1"
bitfld.long 0x00 29. "SRT029,RPC" "0,1"
rbitfld.long 0x00 26.--28. "Reserved_26,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 25. "SRT025,PCIEC ch0 Application/Local register reset" "0,1"
bitfld.long 0x00 24. "SRT024,PCIEC ch0 Cold-reset" "0,1"
rbitfld.long 0x00 22.--23. "Reserved_22,Reserved" "0,1,2,3"
newline
bitfld.long 0x00 21. "SRT021,MSIOF channel 3 (MSIOF3)" "0,1"
bitfld.long 0x00 20. "SRT020,MSIOF channel 2 (MSIOF2)" "0,1"
bitfld.long 0x00 19. "SRT019,MSIOF channel 1 (MSIOF1)" "0,1"
bitfld.long 0x00 18. "SRT018,MSIOF channel 0 (MSIOF0)" "0,1"
hexmask.long.tbyte 0x00 0.--17. 1. "Reserved_0,Reserved"
group.long 0x9C++0x03
line.long 0x00 "SRSTCLR7,Each SRSTCLRn is a 32-bit writable register"
hexmask.long.word 0x00 18.--31. 1. "Reserved_18,Reserved"
bitfld.long 0x00 17. "SRT017,TMU channel 4" "0,1"
bitfld.long 0x00 16. "SRT016,TMU channel 3" "0,1"
bitfld.long 0x00 15. "SRT015,TMU channel 2" "0,1"
bitfld.long 0x00 14. "SRT014,TMU channel 1" "0,1"
bitfld.long 0x00 13. "SRT013,TMU channel 0" "0,1"
rbitfld.long 0x00 11.--12. "Reserved_11,Reserved" "0,1,2,3"
newline
bitfld.long 0x00 10. "SRT010,SYS-DMAC1" "0,1"
bitfld.long 0x00 9. "SRT009,SYS-DMAC0" "0,1"
rbitfld.long 0x00 8. "Reserved_8,Reserved" "0,1"
bitfld.long 0x00 7. "SRT007,Secure ROM" "0,1"
bitfld.long 0x00 6. "SRT006,SDHI" "0,1"
bitfld.long 0x00 5. "SRT005,SCIF-4" "0,1"
bitfld.long 0x00 4. "SRT004,SCIF-3" "0,1"
newline
bitfld.long 0x00 3. "SRT003,SCIF-1" "0,1"
bitfld.long 0x00 2. "SRT002,SCIF-0" "0,1"
bitfld.long 0x00 1. "SRT001,RT-DMAC3" "0,1"
bitfld.long 0x00 0. "SRT000,RT-DMAC2" "0,1"
group.long 0xA0++0x03
line.long 0x00 "SRSTCLR8,Each SRSTCLRn is a 32-bit writable register"
hexmask.long 0x00 0.--31. 1. "Reserved_0,Reserved"
group.long 0xA4++0x03
line.long 0x00 "SRSTCLR9,Each SRSTCLRn is a 32-bit writable register"
hexmask.long.word 0x00 21.--31. 1. "Reserved_21,Reserved"
bitfld.long 0x00 20. "SRT020,SUCMT" "0,1"
bitfld.long 0x00 19. "SRT019,TSC4 TSC3 TSC2 TSC1" "0,1"
rbitfld.long 0x00 16.--18. "Reserved_16,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 15. "SRT015,PFC0" "0,1"
rbitfld.long 0x00 14. "Reserved_14,Reserved" "0,1"
bitfld.long 0x00 13. "SRT013,CMT3" "0,1"
newline
bitfld.long 0x00 12. "SRT012,CMT2" "0,1"
bitfld.long 0x00 11. "SRT011,CMT1" "0,1"
bitfld.long 0x00 10. "SRT010,CMT0" "0,1"
rbitfld.long 0x00 8.--9. "Reserved_8,Reserved" "0,1,2,3"
bitfld.long 0x00 7. "SRT007,WDT" "0,1"
bitfld.long 0x00 6. "SRT006,WCRC3" "0,1"
bitfld.long 0x00 5. "SRT005,WCRC2" "0,1"
newline
bitfld.long 0x00 4. "SRT004,WCRC1" "0,1"
bitfld.long 0x00 3. "SRT003,WCRC0" "0,1"
rbitfld.long 0x00 0.--2. "Reserved_0,Reserved" "0,1,2,3,4,5,6,7"
group.long 0xA8++0x03
line.long 0x00 "SRSTCLR10,Each SRSTCLRn is a 32-bit writable register"
hexmask.long 0x00 0.--31. 1. "Reserved_0,Reserved"
group.long 0xAC++0x03
line.long 0x00 "SRSTCLR11,Each SRSTCLRn is a 32-bit writable register"
rbitfld.long 0x00 29.--31. "Reserved_29,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 28. "SRT028,SWDT" "0,1"
rbitfld.long 0x00 23.--27. "Reserved_23,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 22. "SRT022,PCIEC ch1 Application/Local register reset" "0,1"
bitfld.long 0x00 21. "SRT021,PCIEC ch1 Cold-reset" "0,1"
hexmask.long.word 0x00 7.--20. 1. "Reserved_7,Reserved"
bitfld.long 0x00 6. "SRT006,Aurora links (using 2-lane PCIE physical unit)" "0,1"
newline
rbitfld.long 0x00 0.--5. "Reserved_0,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xB0++0x03
line.long 0x00 "SRSTCLR12,Each SRSTCLRn is a 32-bit writable register"
hexmask.long.word 0x00 23.--31. 1. "Reserved_23,Reserved"
bitfld.long 0x00 22. "SRT022,SCMT" "0,1"
hexmask.long.word 0x00 13.--21. 1. "Reserved_13,Reserved"
bitfld.long 0x00 12. "SRT012,PFC Bus Domain3 (GPIO Group 0 1 2 3 shown in Table 7.2)" "0,1"
bitfld.long 0x00 11. "SRT011,PFC Bus Domain2 (GPIO Group 0 1 2 3 shown in Table 7.2)" "0,1"
bitfld.long 0x00 10. "SRT010,PFC Bus Domain1 (GPIO Group 0 1 2 3 shown in Table 7.2)" "0,1"
bitfld.long 0x00 9. "SRT009,WWDT9 for circuits with RCLK" "0,1"
newline
bitfld.long 0x00 8. "SRT008,WWDT8 for circuits with RCLK" "0,1"
bitfld.long 0x00 7. "SRT007,WWDT7 for circuits with RCLK" "0,1"
bitfld.long 0x00 6. "SRT006,WWDT6 for circuits with RCLK" "0,1"
bitfld.long 0x00 5. "SRT005,WWDT5 for circuits with RCLK" "0,1"
bitfld.long 0x00 4. "SRT004,WWDT4 for circuits with RCLK" "0,1"
bitfld.long 0x00 3. "SRT003,WWDT3 for circuits with RCLK" "0,1"
bitfld.long 0x00 2. "SRT002,WWDT2 for circuits with RCLK" "0,1"
newline
bitfld.long 0x00 1. "SRT001,WWDT1 for circuits with RCLK" "0,1"
bitfld.long 0x00 0. "SRT000,WWDT0 for circuits with RCLK" "0,1"
group.long 0xB4++0x03
line.long 0x00 "SRSTCLR13,Each SRSTCLRn is a 32-bit writable register"
hexmask.long 0x00 0.--31. 1. "Reserved_0,Reserved"
group.long 0xB8++0x03
line.long 0x00 "SRSTCLR14,Each SRSTCLRn is a 32-bit writable register"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved"
bitfld.long 0x00 12. "SRT012,Clock Monitor in Main Memory domain shown in 8.5.2.5" "0,1"
rbitfld.long 0x00 7.--11. "Reserved_7,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 6. "SRT006,Clock Monitor in Peripheral (PeriE/PeriW) domain shown in 8.5.2.2" "0,1"
bitfld.long 0x00 5. "SRT005,Clock Monitor in RT (Real Time) domain shown in 8.5.2.4" "0,1"
rbitfld.long 0x00 0.--4. "Reserved_0,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xBC++0x03
line.long 0x00 "SRSTCLR15,Each SRSTCLRn is a 32-bit writable register"
hexmask.long.word 0x00 18.--31. 1. "Reserved_18,Reserved"
bitfld.long 0x00 17. "SRT017,Clock Monitor in Slave Access Bus domain" "0,1"
bitfld.long 0x00 16. "SRT016,Clock Monitor in HC (High speed Communication) domain bus" "0,1"
bitfld.long 0x00 15. "SRT015,Clock Monitor in RT (Real Time) domain shown in 8.5.2.4" "0,1"
bitfld.long 0x00 14. "SRT014,UFS" "0,1"
hexmask.long.byte 0x00 7.--13. 1. "Reserved_7,Reserved"
bitfld.long 0x00 6. "SRT006,EtherTSN-IF" "0,1"
newline
bitfld.long 0x00 5. "SRT005,RSwitch2" "0,1"
rbitfld.long 0x00 0.--4. "Reserved_0,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
repeat 12. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C )
group.long ($2+0xC0)++0x03
line.long 0x00 "SRSTCLR$1,Each SRSTCLRn is a 32-bit writable register"
hexmask.long 0x00 0.--31. 1. "Reserved_0,Reserved"
repeat.end
group.long 0x100++0x03
line.long 0x00 "MSTPCR0,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits"
hexmask.long 0x00 0.--31. 1. "Reserved_0,Reserved"
group.long 0x104++0x03
line.long 0x00 "MSTPCR1,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
bitfld.long 0x00 23. "MSTP023,ADVFS Controller (K-Sensor)" "0,1"
hexmask.long.tbyte 0x00 0.--22. 1. "Reserved_0,Reserved"
group.long 0x108++0x03
line.long 0x00 "MSTPCR2,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits"
hexmask.long 0x00 0.--31. 1. "Reserved_0,Reserved"
group.long 0x10C++0x03
line.long 0x00 "MSTPCR3,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits"
rbitfld.long 0x00 31. "Reserved_31,Reserved" "0,1"
bitfld.long 0x00 30. "MSTP030,CoreSight Debug Block" "0,1"
bitfld.long 0x00 29. "MSTP029,Crypto Engine" "0,1"
hexmask.long 0x00 0.--28. 1. "Reserved_0,Reserved"
group.long 0x110++0x03
line.long 0x00 "MSTPCR4,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits"
hexmask.long 0x00 0.--31. 1. "Reserved_0,Reserved"
group.long 0x114++0x03
line.long 0x00 "MSTPCR5,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
bitfld.long 0x00 23. "MSTP023,I2C channel 5" "0,1"
bitfld.long 0x00 22. "MSTP022,I2C channel 4" "0,1"
bitfld.long 0x00 21. "MSTP021,I2C channel 3" "0,1"
bitfld.long 0x00 20. "MSTP020,I2C channel 2" "0,1"
bitfld.long 0x00 19. "MSTP019,I2C channel 1" "0,1"
bitfld.long 0x00 18. "MSTP018,I2C channel 0" "0,1"
newline
bitfld.long 0x00 17. "MSTP017,HSCIF channel 3" "0,1"
bitfld.long 0x00 16. "MSTP016,HSCIF channel 2" "0,1"
bitfld.long 0x00 15. "MSTP015,HSCIF channel 1" "0,1"
bitfld.long 0x00 14. "MSTP014,HSCIF channel 0" "0,1"
hexmask.long.word 0x00 0.--13. 1. "Reserved_0,Reserved"
group.long 0x118++0x03
line.long 0x00 "MSTPCR6,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits"
bitfld.long 0x00 31. "MSTP031,RT-DMAC channel 1" "0,1"
bitfld.long 0x00 30. "MSTP030,RT-DMAC channel 1" "0,1"
bitfld.long 0x00 29. "MSTP029,RPC" "0,1"
rbitfld.long 0x00 26.--28. "Reserved_26,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 25. "MSTP025,PCIEC ch0 Application/Local register reset" "0,1"
bitfld.long 0x00 24. "MSTP024,PCIEC ch0 Cold-reset" "0,1"
rbitfld.long 0x00 22.--23. "Reserved_22,Reserved" "0,1,2,3"
newline
bitfld.long 0x00 21. "MSTP021,MSIOF channel 3 (MSIOF3)" "0,1"
bitfld.long 0x00 20. "MSTP020,MSIOF channel 2 (MSIOF2)" "0,1"
bitfld.long 0x00 19. "MSTP019,MSIOF channel 1 (MSIOF1)" "0,1"
bitfld.long 0x00 18. "MSTP018,MSIOF channel 0 (MSIOF0)" "0,1"
hexmask.long.tbyte 0x00 0.--17. 1. "Reserved_0,Reserved"
group.long 0x11C++0x03
line.long 0x00 "MSTPCR7,"
rbitfld.long 0x00 29.--31. "Reserved_29,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 28. "MSTP028,AES-ACC Ch7" "0,1"
bitfld.long 0x00 27. "MSTP027,AES-ACC Ch6" "0,1"
bitfld.long 0x00 26. "MSTP026,AES-ACC Ch5" "0,1"
bitfld.long 0x00 25. "MSTP025,AES-ACC Ch4" "0,1"
bitfld.long 0x00 24. "MSTP024,AES-ACC Ch3" "0,1"
bitfld.long 0x00 23. "MSTP023,AES-ACC Ch2" "0,1"
newline
bitfld.long 0x00 22. "MSTP022,AES-ACC Ch1" "0,1"
bitfld.long 0x00 21. "MSTP021,AES-ACC Ch0" "0,1"
bitfld.long 0x00 20. "MSTP020,AES-ACC Wrapper" "0,1"
bitfld.long 0x00 19. "MSTP019,SHIP-S0" "0,1"
rbitfld.long 0x00 18. "Reserved_18,Reserved" "0,1"
bitfld.long 0x00 17. "MSTP017,TMU channel 4" "0,1"
bitfld.long 0x00 16. "MSTP016,TMU channel 3" "0,1"
newline
bitfld.long 0x00 15. "MSTP015,TMU channel 2" "0,1"
bitfld.long 0x00 14. "MSTP014,TMU channel 1" "0,1"
bitfld.long 0x00 13. "MSTP013,TMU channel 0" "0,1"
rbitfld.long 0x00 12. "Reserved_12,Reserved" "0,1"
rbitfld.long 0x00 11. "Reserved_11,Reserved" "0,1"
bitfld.long 0x00 10. "MSTP010,SYS-DMAC1" "0,1"
bitfld.long 0x00 9. "MSTP009,SYS-DMAC0" "0,1"
newline
rbitfld.long 0x00 8. "Reserved_8,Reserved" "0,1"
bitfld.long 0x00 7. "MSTP007,Secure ROM" "0,1"
bitfld.long 0x00 6. "MSTP006,SDHI" "0,1"
bitfld.long 0x00 5. "MSTP005,SCIF-4" "0,1"
bitfld.long 0x00 4. "MSTP004,SCIF-3" "0,1"
bitfld.long 0x00 3. "MSTP003,SCIF-1" "0,1"
bitfld.long 0x00 2. "MSTP002,SCIF-0" "0,1"
newline
bitfld.long 0x00 1. "MSTP001,RT-DMAC3" "0,1"
bitfld.long 0x00 0. "MSTP000,RT-DMAC2" "0,1"
group.long 0x120++0x03
line.long 0x00 "MSTPCR8,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits"
hexmask.long 0x00 0.--31. 1. "Reserved_0,Reserved"
group.long 0x124++0x03
line.long 0x00 "MSTPCR9,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits"
hexmask.long.word 0x00 21.--31. 1. "Reserved_21,Reserved"
rbitfld.long 0x00 20. "MSTP020,SCUMT" "0,1"
bitfld.long 0x00 19. "MSTP019,TSC4 TSC3 TSC2 TSC1" "0,1"
rbitfld.long 0x00 16.--18. "Reserved_16,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 15. "MSTP015,PFC0" "0,1"
rbitfld.long 0x00 14. "Reserved_14,Reserved" "0,1"
bitfld.long 0x00 13. "MSTP013,CMT3" "0,1"
newline
bitfld.long 0x00 12. "MSTP012,CMT2" "0,1"
bitfld.long 0x00 11. "MSTP011,CMT1" "0,1"
bitfld.long 0x00 10. "MSTP010,CMT0" "0,1"
rbitfld.long 0x00 8.--9. "Reserved_8,Reserved" "0,1,2,3"
bitfld.long 0x00 7. "MSTP007,WDT" "0,1"
bitfld.long 0x00 6. "MSTP006,WCRC3" "0,1"
bitfld.long 0x00 5. "MSTP005,WCRC2" "0,1"
newline
bitfld.long 0x00 4. "MSTP004,WCRC1" "0,1"
bitfld.long 0x00 3. "MSTP003,WCRC0" "0,1"
rbitfld.long 0x00 0.--2. "Reserved_0,Reserved" "0,1,2,3,4,5,6,7"
repeat 2. (strings "10" "11" )(list 0x00 0x04 )
group.long ($2+0x128)++0x03
line.long 0x00 "MSTPCR$1,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits"
hexmask.long 0x00 0.--31. 1. "Reserved_0,Reserved"
repeat.end
group.long 0x130++0x03
line.long 0x00 "MSTPCR12,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits"
bitfld.long 0x00 31. "MSTP031,KCRC4" "0,1"
rbitfld.long 0x00 29.--30. "Reserved_29,Reserved" "0,1,2,3"
bitfld.long 0x00 28. "MSTP028,CRC3" "0,1"
bitfld.long 0x00 27. "MSTP027,CRC2" "0,1"
bitfld.long 0x00 26. "MSTP026,CRC1" "0,1"
bitfld.long 0x00 25. "MSTP025,CRC0" "0,1"
rbitfld.long 0x00 24. "Reserved_24,Reserved" "0,1"
newline
bitfld.long 0x00 23. "MSTP023,ADVFS Controller (K-Sensor)" "0,1"
hexmask.long.tbyte 0x00 0.--22. 1. "Reserved_0,Reserved"
group.long 0x134++0x03
line.long 0x00 "MSTPCR13,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits"
hexmask.long 0x00 3.--31. 1. "Reserved_3,Reserved"
bitfld.long 0x00 2. "MSTP002,KCRC7" "0,1"
bitfld.long 0x00 1. "MSTP001,KCRC6" "0,1"
bitfld.long 0x00 0. "MSTP000,KCRC5" "0,1"
group.long 0x138++0x03
line.long 0x00 "MSTPCR14,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits"
hexmask.long 0x00 0.--31. 1. "Reserved_0,Reserved"
group.long 0x13C++0x03
line.long 0x00 "MSTPCR15,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits"
hexmask.long.tbyte 0x00 15.--31. 1. "Reserved_15,Reserved"
bitfld.long 0x00 14. "MSTP014,UFS" "0,1"
rbitfld.long 0x00 13. "Reserved_13,Reserved" "0,1"
bitfld.long 0x00 12. "MSTP012,SHIP-S2" "0,1"
bitfld.long 0x00 11. "MSTP011,SHIP-S1" "0,1"
rbitfld.long 0x00 7.--10. "Reserved_7,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 6. "MSTP006,EtherTSN-IF" "0,1"
newline
bitfld.long 0x00 5. "MSTP005,RSwitch2" "0,1"
rbitfld.long 0x00 0.--4. "Reserved_0,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
repeat 12. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C )
group.long ($2+0x140)++0x03
line.long 0x00 "MSTPCR$1,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits"
hexmask.long 0x00 0.--31. 1. "Reserved_0,Reserved"
repeat.end
group.long 0x180++0x03
line.long 0x00 "RAHSR0,RAHSRn (n = 0 to 27) is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "Reserved_0,Reserved"
group.long 0x184++0x03
line.long 0x00 "RAHSR1,RAHSRn (n = 0 to 27) is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
bitfld.long 0x00 23. "SRT023,ADVFS Controller (K-Sensor)" "0,1"
hexmask.long.tbyte 0x00 0.--22. 1. "Reserved_0,Reserved"
group.long 0x188++0x03
line.long 0x00 "RAHSR2,RAHSRn (n = 0 to 27) is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "Reserved_0,Reserved"
group.long 0x18C++0x03
line.long 0x00 "RAHSR3,RAHSRn (n = 0 to 27) is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved" "0,1"
bitfld.long 0x00 30. "SRT030,CoreSight Debug Block" "0,1"
bitfld.long 0x00 29. "SRT029,Crypto Engine" "0,1"
hexmask.long 0x00 0.--28. 1. "Reserved_0,Reserved"
group.long 0x190++0x03
line.long 0x00 "RAHSR4,RAHSRn (n = 0 to 27) is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 10.--31. 1. "Reserved_10,Reserved"
bitfld.long 0x00 9. "SRT009,LPDDR4X / LPDDR4" "0,1"
hexmask.long.word 0x00 0.--8. 1. "Reserved_0,Reserved"
group.long 0x194++0x03
line.long 0x00 "RAHSR5,RAHSRn (n = 0 to 27) is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
bitfld.long 0x00 23. "SRT023,I2C channel 5" "0,1"
bitfld.long 0x00 22. "SRT022,I2C channel 4" "0,1"
bitfld.long 0x00 21. "SRT021,I2C channel 3" "0,1"
bitfld.long 0x00 20. "SRT020,I2C channel 2" "0,1"
bitfld.long 0x00 19. "SRT019,I2C channel 1" "0,1"
bitfld.long 0x00 18. "SRT018,I2C channel 0" "0,1"
newline
bitfld.long 0x00 17. "SRT017,HSCIF channel 3" "0,1"
bitfld.long 0x00 16. "SRT016,HSCIF channel 2" "0,1"
bitfld.long 0x00 15. "SRT015,HSCIF channel 1" "0,1"
bitfld.long 0x00 14. "SRT014,HSCIF channel 0" "0,1"
hexmask.long.word 0x00 0.--13. 1. "Reserved_0,Reserved"
group.long 0x198++0x03
line.long 0x00 "RAHSR6,RAHSRn (n = 0 to 27) is a 32-bit readable/writable register"
bitfld.long 0x00 31. "SRT031,RT-DMAC channel 1" "0,1"
bitfld.long 0x00 30. "SRT030,RT-DMAC channel 1" "0,1"
bitfld.long 0x00 29. "SRT029,RPC" "0,1"
rbitfld.long 0x00 26.--28. "Reserved_26,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 25. "SRT025,PCIEC ch0 Application/Local register reset" "0,1"
bitfld.long 0x00 24. "SRT024,PCIEC ch0 Cold-reset" "0,1"
rbitfld.long 0x00 22.--23. "Reserved_22,Reserved" "0,1,2,3"
newline
bitfld.long 0x00 21. "SRT021,MSIOF channel 3 (MSIOF3)" "0,1"
bitfld.long 0x00 20. "SRT020,MSIOF channel 2 (MSIOF2)" "0,1"
bitfld.long 0x00 19. "SRT019,MSIOF channel 1 (MSIOF1)" "0,1"
bitfld.long 0x00 18. "SRT018,MSIOF channel 0 (MSIOF0)" "0,1"
hexmask.long.tbyte 0x00 0.--17. 1. "Reserved_0,Reserved"
group.long 0x19C++0x03
line.long 0x00 "RAHSR7,RAHSRn (n = 0 to 27) is a 32-bit readable/writable register"
hexmask.long.word 0x00 18.--31. 1. "Reserved_18,Reserved"
bitfld.long 0x00 17. "SRT017,TMU channel 4" "0,1"
bitfld.long 0x00 16. "SRT016,TMU channel 3" "0,1"
bitfld.long 0x00 15. "SRT015,TMU channel 2" "0,1"
bitfld.long 0x00 14. "SRT014,TMU channel 1" "0,1"
bitfld.long 0x00 13. "SRT013,TMU channel 0" "0,1"
rbitfld.long 0x00 11.--12. "Reserved_11,Reserved" "0,1,2,3"
newline
bitfld.long 0x00 10. "SRT010,SYS-DMAC1" "0,1"
bitfld.long 0x00 9. "SRT009,SYS-DMAC0" "0,1"
rbitfld.long 0x00 8. "Reserved_8,Reserved" "0,1"
bitfld.long 0x00 7. "SRT007,Secure ROM" "0,1"
bitfld.long 0x00 6. "SRT006,SDHI" "0,1"
bitfld.long 0x00 5. "SRT005,SCIF-4" "0,1"
bitfld.long 0x00 4. "SRT004,SCIF-3" "0,1"
newline
bitfld.long 0x00 3. "SRT003,SCIF-1" "0,1"
bitfld.long 0x00 2. "SRT002,SCIF-0" "0,1"
bitfld.long 0x00 1. "SRT001,RT-DMAC3" "0,1"
bitfld.long 0x00 0. "SRT000,RT-DMAC2" "0,1"
group.long 0x1A0++0x03
line.long 0x00 "RAHSR8,RAHSRn (n = 0 to 27) is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "Reserved_0,Reserved"
group.long 0x1A4++0x03
line.long 0x00 "RAHSR9,RAHSRn (n = 0 to 27) is a 32-bit readable/writable register"
hexmask.long.word 0x00 21.--31. 1. "Reserved_21,Reserved"
bitfld.long 0x00 20. "SRT020,SUCMT" "0,1"
bitfld.long 0x00 19. "SRT019,TSC4 TSC3 TSC2 TSC1" "0,1"
rbitfld.long 0x00 16.--18. "Reserved_16,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 15. "SRT015,PFC0" "0,1"
rbitfld.long 0x00 14. "Reserved_14,Reserved" "0,1"
bitfld.long 0x00 13. "SRT013,CMT3" "0,1"
newline
bitfld.long 0x00 12. "SRT012,CMT2" "0,1"
bitfld.long 0x00 11. "SRT011,CMT1" "0,1"
bitfld.long 0x00 10. "SRT010,CMT0" "0,1"
rbitfld.long 0x00 8.--9. "Reserved_8,Reserved" "0,1,2,3"
bitfld.long 0x00 7. "SRT007,WDT" "0,1"
bitfld.long 0x00 6. "SRT006,WCRC3" "0,1"
bitfld.long 0x00 5. "SRT005,WCRC2" "0,1"
newline
bitfld.long 0x00 4. "SRT004,WCRC1" "0,1"
bitfld.long 0x00 3. "SRT003,WCRC0" "0,1"
rbitfld.long 0x00 0.--2. "Reserved_0,Reserved" "0,1,2,3,4,5,6,7"
group.long 0x1A8++0x03
line.long 0x00 "RAHSR10,RAHSRn (n = 0 to 27) is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "Reserved_0,Reserved"
group.long 0x1AC++0x03
line.long 0x00 "RAHSR11,RAHSRn (n = 0 to 27) is a 32-bit readable/writable register"
rbitfld.long 0x00 29.--31. "Reserved_29,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 28. "SRT028,SWDT" "0,1"
rbitfld.long 0x00 23.--27. "Reserved_23,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 22. "SRT022,PCIEC ch1 Application/Local register reset" "0,1"
bitfld.long 0x00 21. "SRT021,PCIEC ch1 Cold-reset" "0,1"
hexmask.long.word 0x00 7.--20. 1. "Reserved_7,Reserved"
bitfld.long 0x00 6. "SRT006,Aurora links (using 2-lane PCIE physical unit)" "0,1"
newline
rbitfld.long 0x00 0.--5. "Reserved_0,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x1B0++0x03
line.long 0x00 "RAHSR12,RAHSRn (n = 0 to 27) is a 32-bit readable/writable register"
hexmask.long.word 0x00 23.--31. 1. "Reserved_23,Reserved"
bitfld.long 0x00 22. "SRT022,SCMT" "0,1"
hexmask.long.word 0x00 13.--21. 1. "Reserved_13,Reserved"
bitfld.long 0x00 12. "SRT012,PFC Bus Domain3 (GPIO Group 0 1 2 3 shown in Table 7.2)" "0,1"
bitfld.long 0x00 11. "SRT011,PFC Bus Domain2 (GPIO Group 0 1 2 3 shown in Table 7.2)" "0,1"
bitfld.long 0x00 10. "SRT010,PFC Bus Domain1 (GPIO Group 0 1 2 3 shown in Table 7.2)" "0,1"
bitfld.long 0x00 9. "SRT009,WWDT9 for circuits with RCLK" "0,1"
newline
bitfld.long 0x00 8. "SRT008,WWDT8 for circuits with RCLK" "0,1"
bitfld.long 0x00 7. "SRT007,WWDT7 for circuits with RCLK" "0,1"
bitfld.long 0x00 6. "SRT006,WWDT6 for circuits with RCLK" "0,1"
bitfld.long 0x00 5. "SRT005,WWDT5 for circuits with RCLK" "0,1"
bitfld.long 0x00 4. "SRT004,WWDT4 for circuits with RCLK" "0,1"
bitfld.long 0x00 3. "SRT003,WWDT3 for circuits with RCLK" "0,1"
bitfld.long 0x00 2. "SRT002,WWDT2 for circuits with RCLK" "0,1"
newline
bitfld.long 0x00 1. "SRT001,WWDT1 for circuits with RCLK" "0,1"
bitfld.long 0x00 0. "SRT000,WWDT0 for circuits with RCLK" "0,1"
group.long 0x1B4++0x03
line.long 0x00 "RAHSR13,RAHSRn (n = 0 to 27) is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "Reserved_0,Reserved"
group.long 0x1B8++0x03
line.long 0x00 "RAHSR14,RAHSRn (n = 0 to 27) is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved"
bitfld.long 0x00 12. "SRT012,Clock Monitor in Main Memory domain shown in 8.5.2.5" "0,1"
rbitfld.long 0x00 7.--11. "Reserved_7,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 6. "SRT006,Clock Monitor in Peripheral (PeriE/PeriW) domain shown in 8.5.2.2" "0,1"
bitfld.long 0x00 5. "SRT005,Clock Monitor in RT (Real Time) domain shown in 8.5.2.4" "0,1"
rbitfld.long 0x00 0.--4. "Reserved_0,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x1BC++0x03
line.long 0x00 "RAHSR15,RAHSRn (n = 0 to 27) is a 32-bit readable/writable register"
hexmask.long.word 0x00 18.--31. 1. "Reserved_18,Reserved"
bitfld.long 0x00 17. "SRT017,Clock Monitor in Slave Access Bus domain" "0,1"
bitfld.long 0x00 16. "SRT016,Clock Monitor in HC (High speed Communication) domain bus" "0,1"
bitfld.long 0x00 15. "SRT015,Clock Monitor in RT (Real Time) domain shown in 8.5.2.4" "0,1"
bitfld.long 0x00 14. "SRT014,UFS" "0,1"
hexmask.long.byte 0x00 7.--13. 1. "Reserved_7,Reserved"
bitfld.long 0x00 6. "SRT006,EtherTSN-IF" "0,1"
newline
bitfld.long 0x00 5. "SRT005,RSwitch2" "0,1"
rbitfld.long 0x00 0.--4. "Reserved_0,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
repeat 12. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C )
group.long ($2+0x1C0)++0x03
line.long 0x00 "RAHSR$1,RAHSRn (n = 0 to 27) is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "Reserved_0,Reserved"
repeat.end
group.long 0x200++0x03
line.long 0x00 "MSTPSR0,MSTPSRn (n = 0 to 27) is 32-bit readable register that indicates whether the on-chip modules are in the module standby state"
hexmask.long 0x00 0.--31. 1. "Reserved_0,Reserved"
group.long 0x204++0x03
line.long 0x00 "MSTPSR1,MSTPSRn (n = 0 to 27) is 32-bit readable register that indicates whether the on-chip modules are in the module standby state"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
bitfld.long 0x00 23. "MSTP023,ADVFS Controller (K-Sensor)" "0,1"
hexmask.long.tbyte 0x00 0.--22. 1. "Reserved_0,Reserved"
group.long 0x208++0x03
line.long 0x00 "MSTPSR2,MSTPSRn (n = 0 to 27) is 32-bit readable register that indicates whether the on-chip modules are in the module standby state"
hexmask.long 0x00 0.--31. 1. "Reserved_0,Reserved"
group.long 0x20C++0x03
line.long 0x00 "MSTPSR3,MSTPSRn (n = 0 to 27) is 32-bit readable register that indicates whether the on-chip modules are in the module standby state"
rbitfld.long 0x00 31. "Reserved_31,Reserved" "0,1"
bitfld.long 0x00 30. "MSTP030,CoreSight Debug Block" "0,1"
bitfld.long 0x00 29. "MSTP029,Crypto Engine" "0,1"
hexmask.long 0x00 0.--28. 1. "Reserved_0,Reserved"
group.long 0x210++0x03
line.long 0x00 "MSTPSR4,MSTPSRn (n = 0 to 27) is 32-bit readable register that indicates whether the on-chip modules are in the module standby state"
hexmask.long 0x00 0.--31. 1. "Reserved_0,Reserved"
group.long 0x214++0x03
line.long 0x00 "MSTPSR5,MSTPSRn (n = 0 to 27) is 32-bit readable register that indicates whether the on-chip modules are in the module standby state"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
bitfld.long 0x00 23. "MSTP023,I2C channel 5" "0,1"
bitfld.long 0x00 22. "MSTP022,I2C channel 4" "0,1"
bitfld.long 0x00 21. "MSTP021,I2C channel 3" "0,1"
bitfld.long 0x00 20. "MSTP020,I2C channel 2" "0,1"
bitfld.long 0x00 19. "MSTP019,I2C channel 1" "0,1"
bitfld.long 0x00 18. "MSTP018,I2C channel 0" "0,1"
newline
bitfld.long 0x00 17. "MSTP017,HSCIF channel 3" "0,1"
bitfld.long 0x00 16. "MSTP016,HSCIF channel 2" "0,1"
bitfld.long 0x00 15. "MSTP015,HSCIF channel 1" "0,1"
bitfld.long 0x00 14. "MSTP014,HSCIF channel 0" "0,1"
hexmask.long.word 0x00 0.--13. 1. "Reserved_0,Reserved"
group.long 0x218++0x03
line.long 0x00 "MSTPSR6,MSTPSRn (n = 0 to 27) is 32-bit readable register that indicates whether the on-chip modules are in the module standby state"
bitfld.long 0x00 31. "MSTP031,RT-DMAC channel 1" "0,1"
bitfld.long 0x00 30. "MSTP030,RT-DMAC channel 1" "0,1"
bitfld.long 0x00 29. "MSTP029,RPC" "0,1"
rbitfld.long 0x00 26.--28. "Reserved_26,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 25. "MSTP025,PCIEC ch0 Application/Local register reset" "0,1"
bitfld.long 0x00 24. "MSTP024,PCIEC ch0 Cold-reset" "0,1"
rbitfld.long 0x00 22.--23. "Reserved_22,Reserved" "0,1,2,3"
newline
bitfld.long 0x00 21. "MSTP021,MSIOF channel 3 (MSIOF3)" "0,1"
bitfld.long 0x00 20. "MSTP020,MSIOF channel 2 (MSIOF2)" "0,1"
bitfld.long 0x00 19. "MSTP019,MSIOF channel 1 (MSIOF1)" "0,1"
bitfld.long 0x00 18. "MSTP018,MSIOF channel 0 (MSIOF0)" "0,1"
hexmask.long.tbyte 0x00 0.--17. 1. "Reserved_0,Reserved"
group.long 0x21C++0x03
line.long 0x00 "MSTPSR7,"
hexmask.long.word 0x00 18.--31. 1. "Reserved_18,Reserved"
bitfld.long 0x00 17. "MSTP017,TMU channel 4" "0,1"
bitfld.long 0x00 16. "MSTP016,TMU channel 3" "0,1"
bitfld.long 0x00 15. "MSTP015,TMU channel 2" "0,1"
bitfld.long 0x00 14. "MSTP014,TMU channel 1" "0,1"
bitfld.long 0x00 13. "MSTP013,TMU channel 0" "0,1"
rbitfld.long 0x00 12. "Reserved_12,Reserved" "0,1"
newline
rbitfld.long 0x00 11. "Reserved_11,Reserved" "0,1"
bitfld.long 0x00 10. "MSTP010,SYS-DMAC1" "0,1"
bitfld.long 0x00 9. "MSTP009,SYS-DMAC0" "0,1"
rbitfld.long 0x00 8. "Reserved_8,Reserved" "0,1"
bitfld.long 0x00 7. "MSTP007,Secure ROM" "0,1"
bitfld.long 0x00 6. "MSTP006,SDHI" "0,1"
bitfld.long 0x00 5. "MSTP005,SCIF-4" "0,1"
newline
bitfld.long 0x00 4. "MSTP004,SCIF-3" "0,1"
bitfld.long 0x00 3. "MSTP003,SCIF-1" "0,1"
bitfld.long 0x00 2. "MSTP002,SCIF-0" "0,1"
bitfld.long 0x00 1. "MSTP001,RT-DMAC3" "0,1"
bitfld.long 0x00 0. "MSTP000,RT-DMAC2" "0,1"
group.long 0x220++0x03
line.long 0x00 "MSTPSR8,MSTPSRn (n = 0 to 27) is 32-bit readable register that indicates whether the on-chip modules are in the module standby state"
hexmask.long 0x00 0.--31. 1. "Reserved_0,Reserved"
group.long 0x224++0x03
line.long 0x00 "MSTPSR9,MSTPSRn (n = 0 to 27) is 32-bit readable register that indicates whether the on-chip modules are in the module standby state"
hexmask.long.word 0x00 21.--31. 1. "Reserved_21,Reserved"
rbitfld.long 0x00 20. "MSTP020,SCUMT" "0,1"
bitfld.long 0x00 19. "MSTP019,TSC4 TSC3 TSC2 TSC1" "0,1"
rbitfld.long 0x00 16.--18. "Reserved_16,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 15. "MSTP015,PFC0" "0,1"
rbitfld.long 0x00 14. "Reserved_14,Reserved" "0,1"
bitfld.long 0x00 13. "MSTP013,CMT3" "0,1"
newline
bitfld.long 0x00 12. "MSTP012,CMT2" "0,1"
bitfld.long 0x00 11. "MSTP011,CMT1" "0,1"
bitfld.long 0x00 10. "MSTP010,CMT0" "0,1"
rbitfld.long 0x00 8.--9. "Reserved_8,Reserved" "0,1,2,3"
bitfld.long 0x00 7. "MSTP007,WDT" "0,1"
bitfld.long 0x00 6. "MSTP006,WCRC3" "0,1"
bitfld.long 0x00 5. "MSTP005,WCRC2" "0,1"
newline
bitfld.long 0x00 4. "MSTP004,WCRC1" "0,1"
bitfld.long 0x00 3. "MSTP003,WCRC0" "0,1"
rbitfld.long 0x00 0.--2. "Reserved_0,Reserved" "0,1,2,3,4,5,6,7"
repeat 2. (strings "10" "11" )(list 0x00 0x04 )
group.long ($2+0x228)++0x03
line.long 0x00 "MSTPSR$1,MSTPSRn (n = 0 to 27) is 32-bit readable register that indicates whether the on-chip modules are in the module standby state"
hexmask.long 0x00 0.--31. 1. "Reserved_0,Reserved"
repeat.end
group.long 0x230++0x03
line.long 0x00 "MSTPSR12,MSTPSRn (n = 0 to 27) is 32-bit readable register that indicates whether the on-chip modules are in the module standby state"
bitfld.long 0x00 31. "MSTP031,KCRC4" "0,1"
rbitfld.long 0x00 29.--30. "Reserved_29,Reserved" "0,1,2,3"
bitfld.long 0x00 28. "MSTP028,CRC3" "0,1"
bitfld.long 0x00 27. "MSTP027,CRC2" "0,1"
bitfld.long 0x00 26. "MSTP026,CRC1" "0,1"
bitfld.long 0x00 25. "MSTP025,CRC0" "0,1"
rbitfld.long 0x00 24. "Reserved_24,Reserved" "0,1"
newline
bitfld.long 0x00 23. "MSTP023,ADVFS Controller (K-Sensor)" "0,1"
hexmask.long.tbyte 0x00 0.--22. 1. "Reserved_0,Reserved"
group.long 0x234++0x03
line.long 0x00 "MSTPSR13,MSTPSRn (n = 0 to 27) is 32-bit readable register that indicates whether the on-chip modules are in the module standby state"
hexmask.long 0x00 3.--31. 1. "Reserved_3,Reserved"
bitfld.long 0x00 2. "MSTP002,KCRC7" "0,1"
bitfld.long 0x00 1. "MSTP001,KCRC6" "0,1"
bitfld.long 0x00 0. "MSTP000,KCRC5" "0,1"
group.long 0x238++0x03
line.long 0x00 "MSTPSR14,MSTPSRn (n = 0 to 27) is 32-bit readable register that indicates whether the on-chip modules are in the module standby state"
hexmask.long 0x00 0.--31. 1. "Reserved_0,Reserved"
group.long 0x23C++0x03
line.long 0x00 "MSTPSR15,MSTPSRn (n = 0 to 27) is 32-bit readable register that indicates whether the on-chip modules are in the module standby state"
hexmask.long.tbyte 0x00 15.--31. 1. "Reserved_15,Reserved"
bitfld.long 0x00 14. "MSTP014,UFS" "0,1"
hexmask.long.byte 0x00 7.--13. 1. "Reserved_7,Reserved"
bitfld.long 0x00 6. "MSTP006,EtherTSN-IF" "0,1"
bitfld.long 0x00 5. "MSTP005,RSwitch2" "0,1"
rbitfld.long 0x00 0.--4. "Reserved_0,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
repeat 12. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C )
group.long ($2+0x240)++0x03
line.long 0x00 "MSTPSR$1,MSTPSRn (n = 0 to 27) is 32-bit readable register that indicates whether the on-chip modules are in the module standby state"
hexmask.long 0x00 0.--31. 1. "Reserved_0,Reserved"
repeat.end
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x400)++0x03
line.long 0x00 "D0WACR_MSTPCR$1,The register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "D0WACR_31_0,The register specification is described in Sec"
repeat.end
repeat 12. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C )
group.long ($2+0x440)++0x03
line.long 0x00 "D0WACR_MSTPCR$1,The register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "D0WACR_31_0,The register specification is described in Sec"
repeat.end
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x480)++0x03
line.long 0x00 "D0WACR_RAHSR$1,The register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "D0WACR_31_0,The register specification is described in Sec"
repeat.end
repeat 12. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C )
group.long ($2+0x4C0)++0x03
line.long 0x00 "D0WACR_RAHSR$1,The register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "D0WACR_31_0,The register specification is described in Sec"
repeat.end
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0xFFFFD404 0xFFFFD408 0xFFFFD40C 0xFFFFD410 0xFFFFD414 0xFFFFD418 0xFFFFD41C 0xFFFFD420 0xFFFFD424 0xFFFFD428 0xFFFFD42C 0xFFFFD430 0xFFFFD434 0xFFFFD438 0xFFFFD43C )
group.long ($2+0x3100)++0x03
line.long 0x00 "D1WACR_MSTPCR$1,The register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "D1WACR_31_0,The register specification is described in Sec"
repeat.end
repeat 12. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C )
group.long ($2+0x540)++0x03
line.long 0x00 "D1WACR_MSTPCR$1,The register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "D1WACR_31_0,The register specification is described in Sec"
repeat.end
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x580)++0x03
line.long 0x00 "D1WACR_RAHSR$1,The register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "D1WACR_31_0,The register specification is described in Sec"
repeat.end
repeat 12. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C )
group.long ($2+0x5C0)++0x03
line.long 0x00 "D1WACR_RAHSR$1,The register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "D1WACR_31_0,The register specification is described in Sec"
repeat.end
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x600)++0x03
line.long 0x00 "D2WACR_MSTPCR$1,The register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "D2WACR_31_0,The register specification is described in Sec"
repeat.end
repeat 12. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C )
group.long ($2+0x640)++0x03
line.long 0x00 "D2WACR_MSTPCR$1,The register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "D2WACR_31_0,The register specification is described in Sec"
repeat.end
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x680)++0x03
line.long 0x00 "D2WACR_RAHSR$1,The register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "D2WACR_31_0,The register specification is described in Sec"
repeat.end
repeat 12. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C )
group.long ($2+0x6C0)++0x03
line.long 0x00 "D2WACR_RAHSR$1,The register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "D2WACR_31_0,The register specification is described in Sec"
repeat.end
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x700)++0x03
line.long 0x00 "D3WACR_MSTPCR$1,The register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "D3WACR_31_0,The register specification is described in Sec"
repeat.end
repeat 12. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C )
group.long ($2+0x740)++0x03
line.long 0x00 "D3WACR_MSTPCR$1,The register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "D3WACR_31_0,The register specification is described in Sec"
repeat.end
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x780)++0x03
line.long 0x00 "D3WACR_RAHSR$1,The register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "D3WACR_31_0,The register specification is described in Sec"
repeat.end
repeat 12. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C )
group.long ($2+0x7C0)++0x03
line.long 0x00 "D3WACR_RAHSR$1,The register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "D3WACR_31_0,The register specification is described in Sec"
repeat.end
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x800)++0x03
line.long 0x00 "D0WACR_SRCR$1,The register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "D0WACR_31_0,The register specification is described in Sec"
repeat.end
repeat 12. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C )
group.long ($2+0x840)++0x03
line.long 0x00 "D0WACR_SRCR$1,The register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "D0WACR_31_0,The register specification is described in Sec"
repeat.end
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x880)++0x03
line.long 0x00 "D0WACR_SRSTCLR$1,The register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "D0WACR_31_0,The register specification is described in Sec"
repeat.end
repeat 12. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C )
group.long ($2+0x8C0)++0x03
line.long 0x00 "D0WACR_SRSTCLR$1,The register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "D0WACR_31_0,The register specification is described in Sec"
repeat.end
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x900)++0x03
line.long 0x00 "D1WACR_SRCR$1,The register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "D1WACR_31_0,The register specification is described in Sec"
repeat.end
repeat 12. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C )
group.long ($2+0x940)++0x03
line.long 0x00 "D1WACR_SRCR$1,The register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "D1WACR_31_0,The register specification is described in Sec"
repeat.end
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x980)++0x03
line.long 0x00 "D1WACR_SRSTCLR$1,The register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "D1WACR_31_0,The register specification is described in Sec"
repeat.end
repeat 12. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C )
group.long ($2+0x9C0)++0x03
line.long 0x00 "D1WACR_SRSTCLR$1,The register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "D1WACR_31_0,The register specification is described in Sec"
repeat.end
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0xA00)++0x03
line.long 0x00 "D2WACR_SRCR$1,The register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "D2WACR_31_0,The register specification is described in Sec"
repeat.end
repeat 12. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C )
group.long ($2+0xA40)++0x03
line.long 0x00 "D2WACR_SRCR$1,The register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "D2WACR_31_0,The register specification is described in Sec"
repeat.end
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0xA80)++0x03
line.long 0x00 "D2WACR_SRSTCLR$1,The register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "D2WACR_31_0,The register specification is described in Sec"
repeat.end
repeat 12. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C )
group.long ($2+0xAC0)++0x03
line.long 0x00 "D2WACR_SRSTCLR$1,The register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "D2WACR_31_0,The register specification is described in Sec"
repeat.end
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0xB00)++0x03
line.long 0x00 "D3WACR_SRCR$1,The register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "D3WACR_31_0,The register specification is described in Sec"
repeat.end
repeat 12. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C )
group.long ($2+0xB40)++0x03
line.long 0x00 "D3WACR_SRCR$1,The register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "D3WACR_31_0,The register specification is described in Sec"
repeat.end
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0xB80)++0x03
line.long 0x00 "D3WACR_SRSTCLR$1,The register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "D3WACR_31_0,The register specification is described in Sec"
repeat.end
repeat 12. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C )
group.long ($2+0xBC0)++0x03
line.long 0x00 "D3WACR_SRSTCLR$1,The register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "D3WACR_31_0,The register specification is described in Sec"
repeat.end
tree.end
tree "APMU"
tree "APMU_INST_0"
base ad:0xE6170000
group.long 0x00++0x03
line.long 0x00 "WPCR0,This register is 32-bit readable/writable register"
hexmask.long.word 0x00 16.--31. 1. "Code_value,Code Value Code value (H'5AA5) needs to be set to this field when some values are set to this register"
newline
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 0. "WPE,Write Protect Enable" "0: Write protect is disabled,1: Write protect is enabled"
group.long 0x04++0x03
line.long 0x00 "WPR0,These registers are 32-bit readable/writable registers"
hexmask.long 0x00 0.--31. 1. "WPRTCT_31_0,If Write Protect is enabled inverted values need to be set to this field before write access"
group.long 0x10++0x03
line.long 0x00 "D0ACCENR,This register is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 23. "ADMNGRP3,Register protection for Group3 of admin registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 22. "ADMNGRP2,Register protection for Group2 of admin registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 21. "ADMNGRP1,Register protection for Group1 of admin registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 20. "ADMNGRP0,Register protection for Group0 of admin registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 19. "RTGRP3,Register protection for Group3 of CR52's registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 18. "RTGRP2,Register protection for Group2 of CR52's registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 17. "RTGRP1,Register protection for Group1 of CR52's registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 16. "RTGRP0,Register protection for Group0 of CR52's registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 15. "CL3GRP3,Register protection for Group3 of Cortex-A55 cluster 3's registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 14. "CL3GRP2,Register protection for Group2 of Cortex-A55 cluster 3's registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 13. "CL3GRP1,Register protection for Group1 of Cortex-A55 cluster 3's registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 12. "CL3GRP0,Register protection for Group0 of Cortex-A55 cluster 3's registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 11. "CL2GRP3,Register protection for Group3 of Cortex-A55 cluster 2's registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 10. "CL2GRP2,Register protection for Group2 of Cortex-A55 cluster 2's registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 9. "CL2GRP1,Register protection for Group1 of Cortex-A55 cluster 2's registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 8. "CL2GRP0,Register protection for Group0 of Cortex-A55 cluster 2's registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 7. "CL1GRP3,Register protection for Group3 of Cortex-A55 cluster 1's registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 6. "CL1GRP2,Register protection for Group2 of Cortex-A55 cluster 1's registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 5. "CL1GRP1,Register protection for Group1 of Cortex-A55 cluster 1's registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 4. "CL1GRP0,Register protection for Group0 of Cortex-A55 cluster 1's registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 3. "CL0GRP3,Register protection for Group3 of Cortex-A55 cluster 0's registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 2. "CL0GRP2,Register protection for Group2 of Cortex-A55 cluster 0's registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 1. "CL0GRP1,Register protection for Group1 of Cortex-A55 cluster 0's registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 0. "CL0GRP0,Register protection for Group0 of Cortex-A55 cluster 0's registers" "0: Access disabled,1: Access enabled"
group.long 0x14++0x03
line.long 0x00 "D1ACCENR,This register is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 23. "ADMNGRP3,Register protection for Group3 of admin registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 22. "ADMNGRP2,Register protection for Group2 of admin registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 21. "ADMNGRP1,Register protection for Group1 of admin registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 20. "ADMNGRP0,Register protection for Group0 of admin registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 19. "RTGRP3,Register protection for Group3 of CR52's registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 18. "RTGRP2,Register protection for Group2 of CR52's registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 17. "RTGRP1,Register protection for Group1 of CR52's registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 16. "RTGRP0,Register protection for Group0 of CR52's registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 15. "CL3GRP3,Register protection for Group3 of Cortex-A55 cluster 3's registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 14. "CL3GRP2,Register protection for Group2 of Cortex-A55 cluster 3's registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 13. "CL3GRP1,Register protection for Group1 of Cortex-A55 cluster 3's registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 12. "CL3GRP0,Register protection for Group0 of Cortex-A55 cluster 3's registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 11. "CL2GRP3,Register protection for Group3 of Cortex-A55 cluster 2's registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 10. "CL2GRP2,Register protection for Group2 of Cortex-A55 cluster 2's registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 9. "CL2GRP1,Register protection for Group1 of Cortex-A55 cluster 2's registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 8. "CL2GRP0,Register protection for Group0 of Cortex-A55 cluster 2's registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 7. "CL1GRP3,Register protection for Group3 of Cortex-A55 cluster 1's registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 6. "CL1GRP2,Register protection for Group2 of Cortex-A55 cluster 1's registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 5. "CL1GRP1,Register protection for Group1 of Cortex-A55 cluster 1's registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 4. "CL1GRP0,Register protection for Group0 of Cortex-A55 cluster 1's registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 3. "CL0GRP3,Register protection for Group3 of Cortex-A55 cluster 0's registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 2. "CL0GRP2,Register protection for Group2 of Cortex-A55 cluster 0's registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 1. "CL0GRP1,Register protection for Group1 of Cortex-A55 cluster 0's registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 0. "CL0GRP0,Register protection for Group0 of Cortex-A55 cluster 0's registers" "0: Access disabled,1: Access enabled"
group.long 0x18++0x03
line.long 0x00 "D2ACCENR,This register is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 23. "ADMNGRP3,Register protection for Group3 of admin registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 22. "ADMNGRP2,Register protection for Group2 of admin registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 21. "ADMNGRP1,Register protection for Group1 of admin registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 20. "ADMNGRP0,Register protection for Group0 of admin registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 19. "RTGRP3,Register protection for Group3 of CR52's registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 18. "RTGRP2,Register protection for Group2 of CR52's registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 17. "RTGRP1,Register protection for Group1 of CR52's registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 16. "RTGRP0,Register protection for Group0 of CR52's registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 15. "CL3GRP3,Register protection for Group3 of Cortex-A55 cluster 3's registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 14. "CL3GRP2,Register protection for Group2 of Cortex-A55 cluster 3's registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 13. "CL3GRP1,Register protection for Group1 of Cortex-A55 cluster 3's registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 12. "CL3GRP0,Register protection for Group0 of Cortex-A55 cluster 3's registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 11. "CL2GRP3,Register protection for Group3 of Cortex-A55 cluster 2's registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 10. "CL2GRP2,Register protection for Group2 of Cortex-A55 cluster 2's registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 9. "CL2GRP1,Register protection for Group1 of Cortex-A55 cluster 2's registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 8. "CL2GRP0,Register protection for Group0 of Cortex-A55 cluster 2's registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 7. "CL1GRP3,Register protection for Group3 of Cortex-A55 cluster 1's registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 6. "CL1GRP2,Register protection for Group2 of Cortex-A55 cluster 1's registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 5. "CL1GRP1,Register protection for Group1 of Cortex-A55 cluster 1's registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 4. "CL1GRP0,Register protection for Group0 of Cortex-A55 cluster 1's registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 3. "CL0GRP3,Register protection for Group3 of Cortex-A55 cluster 0's registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 2. "CL0GRP2,Register protection for Group2 of Cortex-A55 cluster 0's registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 1. "CL0GRP1,Register protection for Group1 of Cortex-A55 cluster 0's registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 0. "CL0GRP0,Register protection for Group0 of Cortex-A55 cluster 0's registers" "0: Access disabled,1: Access enabled"
group.long 0x1C++0x03
line.long 0x00 "D3ACCENR,This register is a 32-bit readable/writable register"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 23. "ADMNGRP3,Register protection for Group3 of admin registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 22. "ADMNGRP2,Register protection for Group2 of admin registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 21. "ADMNGRP1,Register protection for Group1 of admin registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 20. "ADMNGRP0,Register protection for Group0 of admin registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 19. "RTGRP3,Register protection for Group3 of CR52's registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 18. "RTGRP2,Register protection for Group2 of CR52's registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 17. "RTGRP1,Register protection for Group1 of CR52's registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 16. "RTGRP0,Register protection for Group0 of CR52's registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 15. "CL3GRP3,Register protection for Group3 of Cortex-A55 cluster 3's registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 14. "CL3GRP2,Register protection for Group2 of Cortex-A55 cluster 3's registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 13. "CL3GRP1,Register protection for Group1 of Cortex-A55 cluster 3's registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 12. "CL3GRP0,Register protection for Group0 of Cortex-A55 cluster 3's registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 11. "CL2GRP3,Register protection for Group3 of Cortex-A55 cluster 2's registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 10. "CL2GRP2,Register protection for Group2 of Cortex-A55 cluster 2's registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 9. "CL2GRP1,Register protection for Group1 of Cortex-A55 cluster 2's registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 8. "CL2GRP0,Register protection for Group0 of Cortex-A55 cluster 2's registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 7. "CL1GRP3,Register protection for Group3 of Cortex-A55 cluster 1's registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 6. "CL1GRP2,Register protection for Group2 of Cortex-A55 cluster 1's registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 5. "CL1GRP1,Register protection for Group1 of Cortex-A55 cluster 1's registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 4. "CL1GRP0,Register protection for Group0 of Cortex-A55 cluster 1's registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 3. "CL0GRP3,Register protection for Group3 of Cortex-A55 cluster 0's registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 2. "CL0GRP2,Register protection for Group2 of Cortex-A55 cluster 0's registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 1. "CL0GRP1,Register protection for Group1 of Cortex-A55 cluster 0's registers" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 0. "CL0GRP0,Register protection for Group0 of Cortex-A55 cluster 0's registers" "0: Access disabled,1: Access enabled"
group.long 0x20++0x03
line.long 0x00 "PTCSR0,This register is a 32-bit readable/writable register"
hexmask.long 0x00 2.--31. 1. "Reserved_2,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "ERR,Indicates whether access error has occurred" "0: error has not occurred,1: error has occurred"
group.long 0x24++0x03
line.long 0x00 "PTERADR0,This register is a 32-bit readable register"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--15. 1. "ADDR_15_0,Indicate address causing access error"
group.long 0x28++0x03
line.long 0x00 "DCLSEIJTR0,This register is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 0. "EIJT,Error Injection enable" "0: error injection is not active,1: error injection is active"
repeat 2. (strings "00" "10" )(list 0x0 0x4 )
group.long ($2+0x40)++0x03
line.long 0x00 "A3PWRCTRL$1,This register is a 32-bit readable/writable register"
hexmask.long 0x00 5.--31. 1. "Reserved_5,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4. "A3_PDN_EN,Power down enable for A3 power domain" "0: A3 power domain cannot be powered down,1: A3 power domain is powered down if all A1 and.."
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
repeat.end
repeat 2. (strings "00" "10" )(list 0x0 0x4 )
group.long ($2+0x48)++0x03
line.long 0x00 "A3FSMSTSR$1,This register is a 32-bit readable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "STATE_7_0,Indicate current state of A3 FSM"
repeat.end
repeat 2. (strings "00" "10" )(list 0x0 0x4 )
group.long ($2+0x50)++0x03
line.long 0x00 "A3FSMLOCKR$1,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 16.--31. 1. "CNT_VALUE_15_0,Indicates count value for FSM deadlock error"
newline
rbitfld.long 0x00 13.--15. "Reserved_13,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred" "0: FSM dead lock has not occurred,1: FSM dead lock has occurred"
newline
bitfld.long 0x00 11. "LOCK_EN,FSM deadlock error enable" "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled"
newline
rbitfld.long 0x00 5.--10. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 4. "LOCK_EIJT,FSM deadlock error injection" "0,1"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "LOCK_CLR,FSM deadlock error clear" "0,1"
repeat.end
group.long 0x58++0x03
line.long 0x00 "INTSTSR0,This register is a 32-bit readable register"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 16.--19. "A2Cx_INT,Indicate whether each A2 domain FSM issues interrupt request" "0: FSM doesn't issue interrupt request,1: FSM issues interrupt request,?..."
newline
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
abitfld.long 0x00 0.--7. "A1Cx_INT,Indicate whether each A2 domain FSM issues interrupt request" "0x00=0: FSM doesn't issue interrupt request,0x01=1: FSM issues interrupt request"
group.long 0x5C++0x03
line.long 0x00 "ERRSTSR0,This register is a 32-bit readable register"
rbitfld.long 0x00 29.--31. "Reserved_29,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 28. "CR52_ERR,Indicates whether error flag is set in FSMLOCKRCR52" "0: Error is not detected,1: Error is detected and flag is set in.."
newline
rbitfld.long 0x00 26.--27. "Reserved_26,Reserved These bits are always read as 0" "0,1,2,3"
newline
rbitfld.long 0x00 24.--25. "A3Sx_ERR,Indicates whether error flag is set in A3FSMLOCKRx" "0: Error is not detected,1: Error is detected and flag is set in..,?..."
newline
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 16.--19. "A2Cx_ERR,Indicates whether error flag is set in FSMLOCKRCLx" "0: Error is not detected,1: Error is detected and flag is set in..,?..."
newline
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
abitfld.long 0x00 0.--7. "A1Cx_ERR,Indicates whether error flag is set in FSMLOCKRCx" "0x00=0: Error is not detected,0x01=1: Error is detected and flag is set in.."
group.long 0x60++0x03
line.long 0x00 "FRSTR0,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 16.--19. "FRSTRCLx,Forced reset request for each Cortex-A55 cluster" "0: Forced reset is not requested,1: Forced reset is requested,?..."
newline
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
abitfld.long 0x00 0.--7. "FRSTRCx,Forced reset request for each Cortex-A55 core" "0x00=0: Forced reset is not requested,0x01=1: Forced reset is requested"
group.long 0x68++0x03
line.long 0x00 "FRSTCTRL0,This register is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved These bits are always read as 1" "0,1"
newline
bitfld.long 0x00 30. "FRST_MOD_DBG,Forced reset modification in debug mode" "0: All reset signals are asserted by forced reset,1: Only warm reset of Cortex-A55 is asserted by"
newline
rbitfld.long 0x00 29. "Reserved_29,Reserved These bits are always read as 1" "0,1"
newline
rbitfld.long 0x00 28. "Reserved_28,Reserved These bits are always read as 1" "0,1"
newline
rbitfld.long 0x00 27. "Reserved_27,Reserved These bits are always read as 1" "0,1"
newline
hexmask.long 0x00 0.--26. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x80++0x03
line.long 0x00 "PADDCHKSTSR0,This register is a 32-bit readable/writable register"
bitfld.long 0x00 31. "PADD_CHK_SID_CLR,PADD_CHK_SID clear bit" "0,1"
newline
hexmask.long.tbyte 0x00 8.--30. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "PADD_CHK_SID_7_0,Indicates Source ID of fault transaction detected PADD_CHK mechanism"
group.long 0x84++0x03
line.long 0x00 "PWDATACHKSTSR0,This register is a 32-bit readable/writable register"
bitfld.long 0x00 31. "PWDATA_CHK_SID_CLR,PWDATA_CHK_SID clear bit" "0,1"
newline
hexmask.long.tbyte 0x00 8.--30. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "PWDATA_CHK_SID_7_0,Indicates Source ID of fault transaction detected PWDATA_CHK mechanism"
group.long 0xA4++0x03
line.long 0x00 "AA64nAA32CR0,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 13. "AA64nAA32_c7,AA64nAA32 control bit of Core 7" "0: AA32 mode,1: AA64 mode"
newline
bitfld.long 0x00 12. "AA64nAA32_c6,AA64nAA32 control bit of Core 6" "0: AA32 mode,1: AA64 mode"
newline
rbitfld.long 0x00 10.--11. "Reserved_10,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 9. "AA64nAA32_c5,AA64nAA32 control bit of Core 5" "0: AA32 mode,1: AA64 mode"
newline
bitfld.long 0x00 8. "AA64nAA32_c4,AA64nAA32 control bit of Core 4" "0: AA32 mode,1: AA64 mode"
newline
rbitfld.long 0x00 6.--7. "Reserved_6,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 5. "AA64nAA32_c3,AA64nAA32 control bit of Core 3" "0: AA32 mode,1: AA64 mode"
newline
bitfld.long 0x00 4. "AA64nAA32_c2,AA64nAA32 control bit of Core 2" "0: AA32 mode,1: AA64 mode"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "AA64nAA32_c1,AA64nAA32 control bit of Core 1" "0: AA32 mode,1: AA64 mode"
newline
bitfld.long 0x00 0. "AA64nAA32_c0,AA64nAA32 control bit of Core 0" "0: AA32 mode,1: AA64 mode"
group.long 0x300++0x03
line.long 0x00 "CR52CR0,This register is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 30. "NCPUHALT,NCPUHALT means inverted value of CPUHALT defined in Cortex-R52 TRM" "0: Processor halt after reset,1: No processor halt after reset"
newline
bitfld.long 0x00 29. "CFGRAMPROTEN,CFGRAMPROTEN defined in Cortex-R52 TRM" "0: RAM memory protection is disabled out of reset,1: RAM memory protection is enabled out of reset"
newline
bitfld.long 0x00 28. "CFGTCMBOOT,CFGTCMBOOT defined in Cortex-R52 TRM" "0: ATCM is disabled out of reset,1: ATCM is enabled and at address 0x0 out of reset"
newline
bitfld.long 0x00 27. "CFGINITREG,CFGINITREG defined in Cortex-R52 TRM" "0: Program-visible registers are not initialized..,1: Program-visible registers are initialized to"
newline
bitfld.long 0x00 26. "CFGL1CACHEINVDIS0,CFGL1CACHEINVDIS defined in Cortex-R52 TRM" "0: Automatic post-reset L1 cache invalidate is,1: Automatic post-reset L1 cache invalidate is"
newline
hexmask.long 0x00 0.--25. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x304++0x03
line.long 0x00 "CR52RSTCTRL0,This register is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 0. "CR52RST,Cortex-R52 reset" "0: All Cortex-R52 resets are negated,1: All Cortex-R52 resets are asserted"
group.long 0x30C++0x03
line.long 0x00 "FSMLOCKRCR520,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 16.--31. 1. "CNT_VALUE_15_0,Indicates count value for FSM deadlock error"
newline
rbitfld.long 0x00 13.--15. "Reserved_13,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred" "0: FSM dead lock has not occurred,1: FSM dead lock has occurred"
newline
bitfld.long 0x00 11. "LOCK_EN,FSM deadlock error enable" "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled"
newline
rbitfld.long 0x00 5.--10. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 4. "LOCK_EIJT,FSM deadlock error injection" "0,1"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "LOCK_CLR,FSM deadlock error clear" "0,1"
group.long 0x318++0x03
line.long 0x00 "FSMSTSRCR520,This register is a 32-bit readable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "STATE_7_0,Indicate current state of Cortex-R52 FSM"
group.long 0x31C++0x03
line.long 0x00 "G2GPRCR520,This register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "GPR_31_0,This fields are allowed to write any values and they don't affect module operation"
group.long 0x328++0x03
line.long 0x00 "CR52CMPEN0,This register is a 32-bit readable/writable register"
hexmask.long 0x00 2.--31. 1. "Reserved_2,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 1. "NSRCMPEN,Non-safety- related comparator enable" "0: Comparator for Non-safety-related signals is,1: Comparator for Non-safety-related signals is"
newline
bitfld.long 0x00 0. "CMPEN,Comparator enables" "0: Comparator is disabled,1: Comparator is enabled"
group.long 0x32C++0x03
line.long 0x00 "GCNTERRENCR520,This register is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 0. "GCNTERREN,Generic Counter error detection enable" "0: Error detection is disabled,1: Error detection is enabled"
group.long 0x330++0x03
line.long 0x00 "CR52RVBAR0,This register is a 32-bit readable/writable register"
hexmask.long 0x00 5.--31. 1. "CFGVECTABLE_31_5,CFGVECTABLE defined in Cortex-R52 TRM"
newline
rbitfld.long 0x00 0.--4. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x334++0x03
line.long 0x00 "CR52BAR0,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 18.--31. 1. "RBAR_31_18,Real time CPU (Cortex-R52) Boot Address"
newline
hexmask.long.word 0x00 5.--17. 1. "Reserved_5,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4. "BAREN,BAR enables" "0,1"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
rbitfld.long 0x00 0.--1. "BTMD_1_0,Boot Mode" "0: RBAR is assigned for boot address,?,2: Boot from BootROM,?..."
group.long 0x338++0x03
line.long 0x00 "CR52RVBARP0,This register is a 32-bit readable/writable register"
hexmask.long 0x00 5.--31. 1. "CFGVECTABLE_31_5,CFGVECTABLE defined in Cortex-R52 TRM"
newline
rbitfld.long 0x00 1.--4. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0. "VLD,CR52RVBARP valid" "0: CR52RVBAR is used to define CFGVECTABLE for,1: CR52RVBARP is used to define CFGVECTABLE for"
group.long 0x33C++0x03
line.long 0x00 "CR52BARP0,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 18.--31. 1. "RBAR_31_18,Real time CPU (Cortex-R52) Boot Address"
newline
hexmask.long.word 0x00 5.--17. 1. "Reserved_5,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4. "BAREN,BAR enables" "0: RBAR is not valid,1: RBAR is valid"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "VLD,CR52BARP valid" "0: CR52BAR is used to define Boot Address of,1: CR52BARP is used to define Boot Address of"
group.long 0x400++0x03
line.long 0x00 "PWRCTRLCL0_CLUSTER0,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 22.--31. 1. "Reserved_22,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 21. "PCHMRETEN,MEM_RET mode transition enable by P-channel protocol" "0,1"
newline
bitfld.long 0x00 20. "PCHFRETEN,FUNC_RET mode transition enable by P-channel protocol" "0: Power mode transition to FUNC_RET mode is..,1: Power mode transition to FUNC_RET mode is.."
newline
rbitfld.long 0x00 18.--19. "Reserved_18,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 17. "PCHPDNEN,OFF mode transition enable by P-channel protocol" "0,1"
newline
bitfld.long 0x00 16. "PCHWUPEN,ON mode transition enable by P-channel protocol" "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled"
newline
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0x404++0x03
line.long 0x00 "L3CTRLCL0_CLUSTER0,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 19.--31. 1. "Reserved_19,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 16.--18. "L3STS_2_0,Indicates current L3 cache partial power down/up status" "?,1: 1/4 of L3 cache is powered on,2: 1/2 of L3 cache is powered on,3: 3/4 of L3 cache is powered on,4: All L3 cache is powered on,?..."
newline
rbitfld.long 0x00 10.--15. "Reserved_10,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 9. "L3DENY,Indicates whether L3 cache partial power down/up request is denied" "0: request is not denied,1: request is denied"
newline
bitfld.long 0x00 8. "L3ACCEPT,Indicates whether L3 cache partial power down/up request is accepted" "0: request is not accepted,1: request is accepted"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4. "L3REQ,L3 cache partial power down/up request" "0: L3 cache partial power down/up is not requested,1: L3 cache partial power down/up is requested"
newline
rbitfld.long 0x00 3. "Reserved_3,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0.--2. "L3CTRL_2_0,L3 cache partial power down/up control" "0: All L3 cache is power-off or Cluster's power,1: 1/4 of L3 cache is power-on,2: 1/2 of L3 cache is power-on,3: 3/4 of L3 cache is power-on,4: All L3 cache is power-on,?..."
group.long 0x40C++0x03
line.long 0x00 "FSMLOCKRCL0_CLUSTER0,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 16.--31. 1. "CNT_VALUE_15_0,Indicates count value for FSM deadlock error"
newline
rbitfld.long 0x00 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred" "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred"
newline
rbitfld.long 0x00 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred" "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred"
newline
rbitfld.long 0x00 13. "Reserved_13,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred" "0: FSM dead lock has not occurred,1: FSM dead lock has occurred"
newline
bitfld.long 0x00 11. "LOCK_EN,FSM deadlock error enable" "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled"
newline
bitfld.long 0x00 10. "PRTCL_EN,P-channel protocol error enable" "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled"
newline
bitfld.long 0x00 9. "CRPT_EN,P-channel corruption error enable" "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled"
newline
rbitfld.long 0x00 8. "Reserved_8,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 7. "PRTCL_EIJT,P-channel protocol error injection" "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active"
newline
bitfld.long 0x00 6. "CRPT_EIJT,P-channel corruption error injection" "0,1"
newline
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 4. "LOCK_EIJT,FSM deadlock error injection" "0,1"
newline
bitfld.long 0x00 3. "PRTCL_CLR,P-channel protocol error clear" "0,1"
newline
bitfld.long 0x00 2. "CRPT_CLR,P-channel corruption error clear" "0,1"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "LOCK_CLR,FSM deadlock error clear" "0,1"
group.long 0x410++0x03
line.long 0x00 "PDENYSTSRCL0_CLUSTER0,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 23.--31. 1. "Reserved_23,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 22. "DNY_OFF_ON,Indicates whether a denied state transition has occurred by power mode transition from OFF mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 21. "DNY_ON_OFF,Indicates whether a denied state transition has occurred by power mode transition from ON mode to OFF mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 20. "DNY_ON_FUNC,Indicates whether a denied state transition has occurred by power mode transition from ON mode to FUNC_RET mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 19. "DNY_FUNC_ON,Indicates whether a denied state transition has occurred by power mode transition from FUNC_RET mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 18. "DNY_ON_MEM,Indicates whether a denied state transition has occurred by power mode transition from ON mode to MEM_RET mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 17. "DNY_MEM_ON,Indicates whether a denied state transition has occurred by power mode transition from MEM_RET mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 16. "DNY_ON_L3CHG,Indicates whether a denied state transition has occurred by L3 cache partial power mode control" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
hexmask.long.word 0x00 0.--15. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x414++0x03
line.long 0x00 "PDENYINTRCL0_CLUSTER0,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 23.--31. 1. "Reserved_23,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 22. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 21. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 20. "INT_ON_FUNC,Issuing interrupt enable by DNY_ON_FUNC" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 19. "INT_FUNC_ON,Issuing interrupt enable by DNY_FUNC_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 18. "INT_ON_MEM,Issuing interrupt enable by DNY_ON_MEM" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 17. "INT_MEM_ON,Issuing interrupt enable by DNY_MEM_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 16. "INT_ON_L3CHG,Issuing interrupt enable by DNY_ON_L3CHG" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
hexmask.long.word 0x00 0.--15. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x418++0x03
line.long 0x00 "FSMSTSRCL0_CLUSTER0,This register is a 32-bit readable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "STATE_7_0,Indicate current state of Cortex-A55 cluster FSM"
group.long 0x41C++0x03
line.long 0x00 "G2GPRCL0_CLUSTER0,This register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "GPR0_31_0,This fields are allowed to write any values and they don't affect module operation"
group.long 0x420++0x03
line.long 0x00 "SAFECTRLCL0_CLUSTER0,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as H'0000 2"
newline
rbitfld.long 0x00 11. "Reserved_11,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 10. "A2_RTT_MRET,A2 RuntimeTEST using MEM_RET mode enable" "0: A2 RuntimeTEST using MEM_RET mode is disabled,1: A2 RuntimeTEST using MEM_RET mode is enabled"
newline
bitfld.long 0x00 9. "A2_RTT_POFF,A2 RuntimeTEST using Pseudo OFF mode enable" "0: A2 RuntimeTEST using Pseudo OFF mode is..,1: A2 RuntimeTEST using Pseudo OFF mode is enabled"
newline
hexmask.long.byte 0x00 2.--8. 1. "Reserved_2,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A55 clusters are booted" "0: RuntimeTEST is disabled before Cortex-A55,1: RuntimeTEST is enabled before Cortex-A55"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0x424++0x03
line.long 0x00 "DCLSENCL0_CLUSTER0,This register is a 32-bit readable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 0. "DCLSEN,Indicates Cortex-A55 cluster is DCLS mode" "0: Cortex-A55 cluster is not in DCLS mode,1: Cortex-A55 cluster is in DCLS mode"
group.long 0x428++0x03
line.long 0x00 "DCLSCMPENCL0_CLUSTER0,This register is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 0. "DCLSCMPEN,DCLS comparator enable" "0: DCLS comparator is disabled,1: DCLS comparator is enabled"
group.long 0x42C++0x03
line.long 0x00 "GCNTERRENCL0_CLUSTER0,This register is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 0. "GCNTERREN,Generic Counter error detection enable" "0: Error detection is disabled,1: Error detection is enabled"
group.long 0x430++0x03
line.long 0x00 "CA55BAR0_CLUSTER0,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 10.--31. 1. "BAR_39_18,Cortex-A55 Boot Address for AA32 mode"
newline
rbitfld.long 0x00 5.--9. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 4. "BAREN,BAR enables" "0,1"
newline
rbitfld.long 0x00 0.--3. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x438++0x03
line.long 0x00 "CA55BARP0_CLUSTER0,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 10.--31. 1. "BAR_39_18,Cortex-A55 Boot Address for AA32 mode"
newline
rbitfld.long 0x00 5.--9. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 4. "BAREN,BAR enables" "0,1"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "VLD,CA55BARP valid" "0: CA55BAR is used to define Cortex-A55's Boot,1: CA55BARP is used to define Cortex-A55's Boot"
group.long 0x440++0x03
line.long 0x00 "PWRCTRLCL0_CLUSTER1,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 22.--31. 1. "Reserved_22,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 21. "PCHMRETEN,MEM_RET mode transition enable by P-channel protocol" "0,1"
newline
bitfld.long 0x00 20. "PCHFRETEN,FUNC_RET mode transition enable by P-channel protocol" "0: Power mode transition to FUNC_RET mode is..,1: Power mode transition to FUNC_RET mode is.."
newline
rbitfld.long 0x00 18.--19. "Reserved_18,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 17. "PCHPDNEN,OFF mode transition enable by P-channel protocol" "0,1"
newline
bitfld.long 0x00 16. "PCHWUPEN,ON mode transition enable by P-channel protocol" "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled"
newline
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0x444++0x03
line.long 0x00 "L3CTRLCL0_CLUSTER1,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 19.--31. 1. "Reserved_19,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 16.--18. "L3STS_2_0,Indicates current L3 cache partial power down/up status" "?,1: 1/4 of L3 cache is powered on,2: 1/2 of L3 cache is powered on,3: 3/4 of L3 cache is powered on,4: All L3 cache is powered on,?..."
newline
rbitfld.long 0x00 10.--15. "Reserved_10,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 9. "L3DENY,Indicates whether L3 cache partial power down/up request is denied" "0: request is not denied,1: request is denied"
newline
bitfld.long 0x00 8. "L3ACCEPT,Indicates whether L3 cache partial power down/up request is accepted" "0: request is not accepted,1: request is accepted"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4. "L3REQ,L3 cache partial power down/up request" "0: L3 cache partial power down/up is not requested,1: L3 cache partial power down/up is requested"
newline
rbitfld.long 0x00 3. "Reserved_3,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0.--2. "L3CTRL_2_0,L3 cache partial power down/up control" "0: All L3 cache is power-off or Cluster's power,1: 1/4 of L3 cache is power-on,2: 1/2 of L3 cache is power-on,3: 3/4 of L3 cache is power-on,4: All L3 cache is power-on,?..."
group.long 0x44C++0x03
line.long 0x00 "FSMLOCKRCL0_CLUSTER1,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 16.--31. 1. "CNT_VALUE_15_0,Indicates count value for FSM deadlock error"
newline
rbitfld.long 0x00 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred" "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred"
newline
rbitfld.long 0x00 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred" "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred"
newline
rbitfld.long 0x00 13. "Reserved_13,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred" "0: FSM dead lock has not occurred,1: FSM dead lock has occurred"
newline
bitfld.long 0x00 11. "LOCK_EN,FSM deadlock error enable" "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled"
newline
bitfld.long 0x00 10. "PRTCL_EN,P-channel protocol error enable" "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled"
newline
bitfld.long 0x00 9. "CRPT_EN,P-channel corruption error enable" "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled"
newline
rbitfld.long 0x00 8. "Reserved_8,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 7. "PRTCL_EIJT,P-channel protocol error injection" "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active"
newline
bitfld.long 0x00 6. "CRPT_EIJT,P-channel corruption error injection" "0,1"
newline
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 4. "LOCK_EIJT,FSM deadlock error injection" "0,1"
newline
bitfld.long 0x00 3. "PRTCL_CLR,P-channel protocol error clear" "0,1"
newline
bitfld.long 0x00 2. "CRPT_CLR,P-channel corruption error clear" "0,1"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "LOCK_CLR,FSM deadlock error clear" "0,1"
group.long 0x450++0x03
line.long 0x00 "PDENYSTSRCL0_CLUSTER1,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 23.--31. 1. "Reserved_23,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 22. "DNY_OFF_ON,Indicates whether a denied state transition has occurred by power mode transition from OFF mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 21. "DNY_ON_OFF,Indicates whether a denied state transition has occurred by power mode transition from ON mode to OFF mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 20. "DNY_ON_FUNC,Indicates whether a denied state transition has occurred by power mode transition from ON mode to FUNC_RET mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 19. "DNY_FUNC_ON,Indicates whether a denied state transition has occurred by power mode transition from FUNC_RET mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 18. "DNY_ON_MEM,Indicates whether a denied state transition has occurred by power mode transition from ON mode to MEM_RET mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 17. "DNY_MEM_ON,Indicates whether a denied state transition has occurred by power mode transition from MEM_RET mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 16. "DNY_ON_L3CHG,Indicates whether a denied state transition has occurred by L3 cache partial power mode control" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
hexmask.long.word 0x00 0.--15. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x454++0x03
line.long 0x00 "PDENYINTRCL0_CLUSTER1,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 23.--31. 1. "Reserved_23,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 22. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 21. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 20. "INT_ON_FUNC,Issuing interrupt enable by DNY_ON_FUNC" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 19. "INT_FUNC_ON,Issuing interrupt enable by DNY_FUNC_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 18. "INT_ON_MEM,Issuing interrupt enable by DNY_ON_MEM" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 17. "INT_MEM_ON,Issuing interrupt enable by DNY_MEM_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 16. "INT_ON_L3CHG,Issuing interrupt enable by DNY_ON_L3CHG" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
hexmask.long.word 0x00 0.--15. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x458++0x03
line.long 0x00 "FSMSTSRCL0_CLUSTER1,This register is a 32-bit readable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "STATE_7_0,Indicate current state of Cortex-A55 cluster FSM"
group.long 0x45C++0x03
line.long 0x00 "G2GPRCL0_CLUSTER1,This register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "GPR0_31_0,This fields are allowed to write any values and they don't affect module operation"
group.long 0x460++0x03
line.long 0x00 "SAFECTRLCL0_CLUSTER1,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as H'0000 2"
newline
rbitfld.long 0x00 11. "Reserved_11,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 10. "A2_RTT_MRET,A2 RuntimeTEST using MEM_RET mode enable" "0: A2 RuntimeTEST using MEM_RET mode is disabled,1: A2 RuntimeTEST using MEM_RET mode is enabled"
newline
bitfld.long 0x00 9. "A2_RTT_POFF,A2 RuntimeTEST using Pseudo OFF mode enable" "0: A2 RuntimeTEST using Pseudo OFF mode is..,1: A2 RuntimeTEST using Pseudo OFF mode is enabled"
newline
hexmask.long.byte 0x00 2.--8. 1. "Reserved_2,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A55 clusters are booted" "0: RuntimeTEST is disabled before Cortex-A55,1: RuntimeTEST is enabled before Cortex-A55"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0x464++0x03
line.long 0x00 "DCLSENCL0_CLUSTER1,This register is a 32-bit readable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 0. "DCLSEN,Indicates Cortex-A55 cluster is DCLS mode" "0: Cortex-A55 cluster is not in DCLS mode,1: Cortex-A55 cluster is in DCLS mode"
group.long 0x468++0x03
line.long 0x00 "DCLSCMPENCL0_CLUSTER1,This register is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 0. "DCLSCMPEN,DCLS comparator enable" "0: DCLS comparator is disabled,1: DCLS comparator is enabled"
group.long 0x46C++0x03
line.long 0x00 "GCNTERRENCL0_CLUSTER1,This register is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 0. "GCNTERREN,Generic Counter error detection enable" "0: Error detection is disabled,1: Error detection is enabled"
group.long 0x470++0x03
line.long 0x00 "CA55BAR0_CLUSTER1,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 10.--31. 1. "BAR_39_18,Cortex-A55 Boot Address for AA32 mode"
newline
rbitfld.long 0x00 5.--9. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 4. "BAREN,BAR enables" "0,1"
newline
rbitfld.long 0x00 0.--3. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x478++0x03
line.long 0x00 "CA55BARP0_CLUSTER1,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 10.--31. 1. "BAR_39_18,Cortex-A55 Boot Address for AA32 mode"
newline
rbitfld.long 0x00 5.--9. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 4. "BAREN,BAR enables" "0,1"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "VLD,CA55BARP valid" "0: CA55BAR is used to define Cortex-A55's Boot,1: CA55BARP is used to define Cortex-A55's Boot"
group.long 0x480++0x03
line.long 0x00 "PWRCTRLCL0_CLUSTER2,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 22.--31. 1. "Reserved_22,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 21. "PCHMRETEN,MEM_RET mode transition enable by P-channel protocol" "0,1"
newline
bitfld.long 0x00 20. "PCHFRETEN,FUNC_RET mode transition enable by P-channel protocol" "0: Power mode transition to FUNC_RET mode is..,1: Power mode transition to FUNC_RET mode is.."
newline
rbitfld.long 0x00 18.--19. "Reserved_18,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 17. "PCHPDNEN,OFF mode transition enable by P-channel protocol" "0,1"
newline
bitfld.long 0x00 16. "PCHWUPEN,ON mode transition enable by P-channel protocol" "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled"
newline
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0x484++0x03
line.long 0x00 "L3CTRLCL0_CLUSTER2,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 19.--31. 1. "Reserved_19,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 16.--18. "L3STS_2_0,Indicates current L3 cache partial power down/up status" "?,1: 1/4 of L3 cache is powered on,2: 1/2 of L3 cache is powered on,3: 3/4 of L3 cache is powered on,4: All L3 cache is powered on,?..."
newline
rbitfld.long 0x00 10.--15. "Reserved_10,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 9. "L3DENY,Indicates whether L3 cache partial power down/up request is denied" "0: request is not denied,1: request is denied"
newline
bitfld.long 0x00 8. "L3ACCEPT,Indicates whether L3 cache partial power down/up request is accepted" "0: request is not accepted,1: request is accepted"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4. "L3REQ,L3 cache partial power down/up request" "0: L3 cache partial power down/up is not requested,1: L3 cache partial power down/up is requested"
newline
rbitfld.long 0x00 3. "Reserved_3,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0.--2. "L3CTRL_2_0,L3 cache partial power down/up control" "0: All L3 cache is power-off or Cluster's power,1: 1/4 of L3 cache is power-on,2: 1/2 of L3 cache is power-on,3: 3/4 of L3 cache is power-on,4: All L3 cache is power-on,?..."
group.long 0x48C++0x03
line.long 0x00 "FSMLOCKRCL0_CLUSTER2,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 16.--31. 1. "CNT_VALUE_15_0,Indicates count value for FSM deadlock error"
newline
rbitfld.long 0x00 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred" "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred"
newline
rbitfld.long 0x00 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred" "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred"
newline
rbitfld.long 0x00 13. "Reserved_13,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred" "0: FSM dead lock has not occurred,1: FSM dead lock has occurred"
newline
bitfld.long 0x00 11. "LOCK_EN,FSM deadlock error enable" "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled"
newline
bitfld.long 0x00 10. "PRTCL_EN,P-channel protocol error enable" "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled"
newline
bitfld.long 0x00 9. "CRPT_EN,P-channel corruption error enable" "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled"
newline
rbitfld.long 0x00 8. "Reserved_8,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 7. "PRTCL_EIJT,P-channel protocol error injection" "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active"
newline
bitfld.long 0x00 6. "CRPT_EIJT,P-channel corruption error injection" "0,1"
newline
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 4. "LOCK_EIJT,FSM deadlock error injection" "0,1"
newline
bitfld.long 0x00 3. "PRTCL_CLR,P-channel protocol error clear" "0,1"
newline
bitfld.long 0x00 2. "CRPT_CLR,P-channel corruption error clear" "0,1"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "LOCK_CLR,FSM deadlock error clear" "0,1"
group.long 0x490++0x03
line.long 0x00 "PDENYSTSRCL0_CLUSTER2,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 23.--31. 1. "Reserved_23,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 22. "DNY_OFF_ON,Indicates whether a denied state transition has occurred by power mode transition from OFF mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 21. "DNY_ON_OFF,Indicates whether a denied state transition has occurred by power mode transition from ON mode to OFF mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 20. "DNY_ON_FUNC,Indicates whether a denied state transition has occurred by power mode transition from ON mode to FUNC_RET mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 19. "DNY_FUNC_ON,Indicates whether a denied state transition has occurred by power mode transition from FUNC_RET mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 18. "DNY_ON_MEM,Indicates whether a denied state transition has occurred by power mode transition from ON mode to MEM_RET mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 17. "DNY_MEM_ON,Indicates whether a denied state transition has occurred by power mode transition from MEM_RET mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 16. "DNY_ON_L3CHG,Indicates whether a denied state transition has occurred by L3 cache partial power mode control" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
hexmask.long.word 0x00 0.--15. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x494++0x03
line.long 0x00 "PDENYINTRCL0_CLUSTER2,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 23.--31. 1. "Reserved_23,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 22. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 21. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 20. "INT_ON_FUNC,Issuing interrupt enable by DNY_ON_FUNC" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 19. "INT_FUNC_ON,Issuing interrupt enable by DNY_FUNC_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 18. "INT_ON_MEM,Issuing interrupt enable by DNY_ON_MEM" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 17. "INT_MEM_ON,Issuing interrupt enable by DNY_MEM_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 16. "INT_ON_L3CHG,Issuing interrupt enable by DNY_ON_L3CHG" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
hexmask.long.word 0x00 0.--15. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x498++0x03
line.long 0x00 "FSMSTSRCL0_CLUSTER2,This register is a 32-bit readable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "STATE_7_0,Indicate current state of Cortex-A55 cluster FSM"
group.long 0x49C++0x03
line.long 0x00 "G2GPRCL0_CLUSTER2,This register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "GPR0_31_0,This fields are allowed to write any values and they don't affect module operation"
group.long 0x4A0++0x03
line.long 0x00 "SAFECTRLCL0_CLUSTER2,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as H'0000 2"
newline
rbitfld.long 0x00 11. "Reserved_11,Reserved These bits are always read as 0" "0,1"
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bitfld.long 0x00 10. "A2_RTT_MRET,A2 RuntimeTEST using MEM_RET mode enable" "0: A2 RuntimeTEST using MEM_RET mode is disabled,1: A2 RuntimeTEST using MEM_RET mode is enabled"
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bitfld.long 0x00 9. "A2_RTT_POFF,A2 RuntimeTEST using Pseudo OFF mode enable" "0: A2 RuntimeTEST using Pseudo OFF mode is..,1: A2 RuntimeTEST using Pseudo OFF mode is enabled"
newline
hexmask.long.byte 0x00 2.--8. 1. "Reserved_2,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A55 clusters are booted" "0: RuntimeTEST is disabled before Cortex-A55,1: RuntimeTEST is enabled before Cortex-A55"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0x4A4++0x03
line.long 0x00 "DCLSENCL0_CLUSTER2,This register is a 32-bit readable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 0. "DCLSEN,Indicates Cortex-A55 cluster is DCLS mode" "0: Cortex-A55 cluster is not in DCLS mode,1: Cortex-A55 cluster is in DCLS mode"
group.long 0x4A8++0x03
line.long 0x00 "DCLSCMPENCL0_CLUSTER2,This register is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 0. "DCLSCMPEN,DCLS comparator enable" "0: DCLS comparator is disabled,1: DCLS comparator is enabled"
group.long 0x4AC++0x03
line.long 0x00 "GCNTERRENCL0_CLUSTER2,This register is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 0. "GCNTERREN,Generic Counter error detection enable" "0: Error detection is disabled,1: Error detection is enabled"
group.long 0x4B0++0x03
line.long 0x00 "CA55BAR0_CLUSTER2,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 10.--31. 1. "BAR_39_18,Cortex-A55 Boot Address for AA32 mode"
newline
rbitfld.long 0x00 5.--9. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 4. "BAREN,BAR enables" "0,1"
newline
rbitfld.long 0x00 0.--3. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4B8++0x03
line.long 0x00 "CA55BARP0_CLUSTER2,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 10.--31. 1. "BAR_39_18,Cortex-A55 Boot Address for AA32 mode"
newline
rbitfld.long 0x00 5.--9. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 4. "BAREN,BAR enables" "0,1"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "VLD,CA55BARP valid" "0: CA55BAR is used to define Cortex-A55's Boot,1: CA55BARP is used to define Cortex-A55's Boot"
group.long 0x4C0++0x03
line.long 0x00 "PWRCTRLCL0_CLUSTER3,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 22.--31. 1. "Reserved_22,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 21. "PCHMRETEN,MEM_RET mode transition enable by P-channel protocol" "0,1"
newline
bitfld.long 0x00 20. "PCHFRETEN,FUNC_RET mode transition enable by P-channel protocol" "0: Power mode transition to FUNC_RET mode is..,1: Power mode transition to FUNC_RET mode is.."
newline
rbitfld.long 0x00 18.--19. "Reserved_18,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 17. "PCHPDNEN,OFF mode transition enable by P-channel protocol" "0,1"
newline
bitfld.long 0x00 16. "PCHWUPEN,ON mode transition enable by P-channel protocol" "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled"
newline
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0x4C4++0x03
line.long 0x00 "L3CTRLCL0_CLUSTER3,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 19.--31. 1. "Reserved_19,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 16.--18. "L3STS_2_0,Indicates current L3 cache partial power down/up status" "?,1: 1/4 of L3 cache is powered on,2: 1/2 of L3 cache is powered on,3: 3/4 of L3 cache is powered on,4: All L3 cache is powered on,?..."
newline
rbitfld.long 0x00 10.--15. "Reserved_10,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 9. "L3DENY,Indicates whether L3 cache partial power down/up request is denied" "0: request is not denied,1: request is denied"
newline
bitfld.long 0x00 8. "L3ACCEPT,Indicates whether L3 cache partial power down/up request is accepted" "0: request is not accepted,1: request is accepted"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4. "L3REQ,L3 cache partial power down/up request" "0: L3 cache partial power down/up is not requested,1: L3 cache partial power down/up is requested"
newline
rbitfld.long 0x00 3. "Reserved_3,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0.--2. "L3CTRL_2_0,L3 cache partial power down/up control" "0: All L3 cache is power-off or Cluster's power,1: 1/4 of L3 cache is power-on,2: 1/2 of L3 cache is power-on,3: 3/4 of L3 cache is power-on,4: All L3 cache is power-on,?..."
group.long 0x4CC++0x03
line.long 0x00 "FSMLOCKRCL0_CLUSTER3,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 16.--31. 1. "CNT_VALUE_15_0,Indicates count value for FSM deadlock error"
newline
rbitfld.long 0x00 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred" "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred"
newline
rbitfld.long 0x00 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred" "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred"
newline
rbitfld.long 0x00 13. "Reserved_13,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred" "0: FSM dead lock has not occurred,1: FSM dead lock has occurred"
newline
bitfld.long 0x00 11. "LOCK_EN,FSM deadlock error enable" "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled"
newline
bitfld.long 0x00 10. "PRTCL_EN,P-channel protocol error enable" "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled"
newline
bitfld.long 0x00 9. "CRPT_EN,P-channel corruption error enable" "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled"
newline
rbitfld.long 0x00 8. "Reserved_8,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 7. "PRTCL_EIJT,P-channel protocol error injection" "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active"
newline
bitfld.long 0x00 6. "CRPT_EIJT,P-channel corruption error injection" "0,1"
newline
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 4. "LOCK_EIJT,FSM deadlock error injection" "0,1"
newline
bitfld.long 0x00 3. "PRTCL_CLR,P-channel protocol error clear" "0,1"
newline
bitfld.long 0x00 2. "CRPT_CLR,P-channel corruption error clear" "0,1"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "LOCK_CLR,FSM deadlock error clear" "0,1"
group.long 0x4D0++0x03
line.long 0x00 "PDENYSTSRCL0_CLUSTER3,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 23.--31. 1. "Reserved_23,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 22. "DNY_OFF_ON,Indicates whether a denied state transition has occurred by power mode transition from OFF mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 21. "DNY_ON_OFF,Indicates whether a denied state transition has occurred by power mode transition from ON mode to OFF mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 20. "DNY_ON_FUNC,Indicates whether a denied state transition has occurred by power mode transition from ON mode to FUNC_RET mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 19. "DNY_FUNC_ON,Indicates whether a denied state transition has occurred by power mode transition from FUNC_RET mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 18. "DNY_ON_MEM,Indicates whether a denied state transition has occurred by power mode transition from ON mode to MEM_RET mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 17. "DNY_MEM_ON,Indicates whether a denied state transition has occurred by power mode transition from MEM_RET mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 16. "DNY_ON_L3CHG,Indicates whether a denied state transition has occurred by L3 cache partial power mode control" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
hexmask.long.word 0x00 0.--15. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x4D4++0x03
line.long 0x00 "PDENYINTRCL0_CLUSTER3,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 23.--31. 1. "Reserved_23,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 22. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 21. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 20. "INT_ON_FUNC,Issuing interrupt enable by DNY_ON_FUNC" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 19. "INT_FUNC_ON,Issuing interrupt enable by DNY_FUNC_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 18. "INT_ON_MEM,Issuing interrupt enable by DNY_ON_MEM" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 17. "INT_MEM_ON,Issuing interrupt enable by DNY_MEM_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 16. "INT_ON_L3CHG,Issuing interrupt enable by DNY_ON_L3CHG" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
hexmask.long.word 0x00 0.--15. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x4D8++0x03
line.long 0x00 "FSMSTSRCL0_CLUSTER3,This register is a 32-bit readable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "STATE_7_0,Indicate current state of Cortex-A55 cluster FSM"
group.long 0x4DC++0x03
line.long 0x00 "G2GPRCL0_CLUSTER3,This register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "GPR0_31_0,This fields are allowed to write any values and they don't affect module operation"
group.long 0x4E0++0x03
line.long 0x00 "SAFECTRLCL0_CLUSTER3,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as H'0000 2"
newline
rbitfld.long 0x00 11. "Reserved_11,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 10. "A2_RTT_MRET,A2 RuntimeTEST using MEM_RET mode enable" "0: A2 RuntimeTEST using MEM_RET mode is disabled,1: A2 RuntimeTEST using MEM_RET mode is enabled"
newline
bitfld.long 0x00 9. "A2_RTT_POFF,A2 RuntimeTEST using Pseudo OFF mode enable" "0: A2 RuntimeTEST using Pseudo OFF mode is..,1: A2 RuntimeTEST using Pseudo OFF mode is enabled"
newline
hexmask.long.byte 0x00 2.--8. 1. "Reserved_2,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A55 clusters are booted" "0: RuntimeTEST is disabled before Cortex-A55,1: RuntimeTEST is enabled before Cortex-A55"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0x4E4++0x03
line.long 0x00 "DCLSENCL0_CLUSTER3,This register is a 32-bit readable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 0. "DCLSEN,Indicates Cortex-A55 cluster is DCLS mode" "0: Cortex-A55 cluster is not in DCLS mode,1: Cortex-A55 cluster is in DCLS mode"
group.long 0x4E8++0x03
line.long 0x00 "DCLSCMPENCL0_CLUSTER3,This register is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 0. "DCLSCMPEN,DCLS comparator enable" "0: DCLS comparator is disabled,1: DCLS comparator is enabled"
group.long 0x4EC++0x03
line.long 0x00 "GCNTERRENCL0_CLUSTER3,This register is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 0. "GCNTERREN,Generic Counter error detection enable" "0: Error detection is disabled,1: Error detection is enabled"
group.long 0x4F0++0x03
line.long 0x00 "CA55BAR0_CLUSTER3,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 10.--31. 1. "BAR_39_18,Cortex-A55 Boot Address for AA32 mode"
newline
rbitfld.long 0x00 5.--9. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 4. "BAREN,BAR enables" "0,1"
newline
rbitfld.long 0x00 0.--3. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4F8++0x03
line.long 0x00 "CA55BARP0_CLUSTER3,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 10.--31. 1. "BAR_39_18,Cortex-A55 Boot Address for AA32 mode"
newline
rbitfld.long 0x00 5.--9. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 4. "BAREN,BAR enables" "0,1"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "VLD,CA55BARP valid" "0: CA55BAR is used to define Cortex-A55's Boot,1: CA55BARP is used to define Cortex-A55's Boot"
group.long 0x800++0x03
line.long 0x00 "PWRCTRLC0_CORE0,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 19.--31. 1. "Reserved_19,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol" "0: Power mode transition to OFF_EMU mode is..,1: Power mode transition to OFF_EMU mode is.."
newline
bitfld.long 0x00 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled"
newline
bitfld.long 0x00 16. "PCHWUPEN,ON mode transition enable by P-channel protocol" "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled"
newline
hexmask.long.word 0x00 6.--15. 1. "Reserved_6,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 5. "DWUP_EN,This bit enables wakeup request from Debugger" "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled"
newline
bitfld.long 0x00 4. "IWUP_EN,This bit enables wakeup request from INTC-AP" "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "WUP_REQ,Wake up request" "0: Power on is not requested,1: Power on is requested"
group.long 0x80C++0x03
line.long 0x00 "FSMLOCKRC0_CORE0,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 16.--31. 1. "CNT_VALUE_15_0,Indicates count value for FSM deadlock error"
newline
rbitfld.long 0x00 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred" "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred"
newline
rbitfld.long 0x00 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred" "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred"
newline
rbitfld.long 0x00 13. "Reserved_13,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred" "0: FSM dead lock has not occurred,1: FSM dead lock has occurred"
newline
bitfld.long 0x00 11. "LOCK_EN,FSM deadlock error enable" "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled"
newline
bitfld.long 0x00 10. "PRTCL_EN,P-channel protocol error enable" "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled"
newline
bitfld.long 0x00 9. "CRPT_EN,P-channel corruption error enable" "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled"
newline
rbitfld.long 0x00 8. "Reserved_8,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 7. "PRTCL_EIJT,P-channel protocol error injection" "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active"
newline
bitfld.long 0x00 6. "CRPT_EIJT,P-channel corruption error injection" "0,1"
newline
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 4. "LOCK_EIJT,FSM deadlock error injection" "0,1"
newline
bitfld.long 0x00 3. "PRTCL_CLR,P-channel protocol error clear" "0,1"
newline
bitfld.long 0x00 2. "CRPT_CLR,P-channel corruption error clear" "0,1"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "LOCK_CLR,FSM deadlock error clear" "0,1"
group.long 0x810++0x03
line.long 0x00 "PDENYSTSRC0_CORE0,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
rbitfld.long 0x00 4.--5. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0x814++0x03
line.long 0x00 "PDENYINTRC0_CORE0,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
rbitfld.long 0x00 4.--5. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0x818++0x03
line.long 0x00 "FSMSTSRC0_CORE0,This register is a 32-bit readable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "STATE_7_0,Indicate current state of A3 FSM"
group.long 0x81C++0x03
line.long 0x00 "G2GPRC0_CORE0,This register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "GPR0_31_0,This fields are allowed to write any values and they don't affect module operation"
group.long 0x820++0x03
line.long 0x00 "SAFECTRLC0_CORE0,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are always read as H'0000 0"
newline
bitfld.long 0x00 13. "DBGEN_PPDN,When Cortex-A55 is in debug mode Cortex-A55 core is goes to OFF_EMU mode instead of OFF mode" "0: Cortex-A55 goes to OFF mode,1: Cortex-A55 goes to OFF_EMU mode"
newline
hexmask.long.byte 0x00 5.--12. 1. "Reserved_5,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4. "A1_RTT,A1 RuntimeTEST enable" "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A55 cores are booted" "0: RuntimeTEST is disabled before Cortex-A55 cores,1: RuntimeTEST is enabled before Cortex-A55 cores"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0x830++0x03
line.long 0x00 "RVBARLC0_CORE0,This register is a 32-bit readable/writable register"
hexmask.long 0x00 2.--31. 1. "RVBAR_31_2,These bits indicate RVBARADDR[31:2]"
newline
rbitfld.long 0x00 0.--1. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3"
group.long 0x834++0x03
line.long 0x00 "RVBARHC0_CORE0,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--11. 1. "RVBAR_43_32,These bits indicate RVBARADDR[43:32]"
group.long 0x838++0x03
line.long 0x00 "RVBARPLC0_CORE0,This register is a 32-bit readable/writable register"
hexmask.long 0x00 2.--31. 1. "RVBARP_31_2,These bits indicate RVBARADDR[31:2]"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "VLD,RVBARP valid" "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR"
group.long 0x83C++0x03
line.long 0x00 "RVBARPHC0_CORE0,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--11. 1. "RVBARP_43_32,These bits indicate RVBARADDR[43:32]"
group.long 0x840++0x03
line.long 0x00 "PWRCTRLC0_CORE1,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 19.--31. 1. "Reserved_19,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol" "0: Power mode transition to OFF_EMU mode is..,1: Power mode transition to OFF_EMU mode is.."
newline
bitfld.long 0x00 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled"
newline
bitfld.long 0x00 16. "PCHWUPEN,ON mode transition enable by P-channel protocol" "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled"
newline
hexmask.long.word 0x00 6.--15. 1. "Reserved_6,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 5. "DWUP_EN,This bit enables wakeup request from Debugger" "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled"
newline
bitfld.long 0x00 4. "IWUP_EN,This bit enables wakeup request from INTC-AP" "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "WUP_REQ,Wake up request" "0: Power on is not requested,1: Power on is requested"
group.long 0x84C++0x03
line.long 0x00 "FSMLOCKRC0_CORE1,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 16.--31. 1. "CNT_VALUE_15_0,Indicates count value for FSM deadlock error"
newline
rbitfld.long 0x00 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred" "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred"
newline
rbitfld.long 0x00 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred" "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred"
newline
rbitfld.long 0x00 13. "Reserved_13,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred" "0: FSM dead lock has not occurred,1: FSM dead lock has occurred"
newline
bitfld.long 0x00 11. "LOCK_EN,FSM deadlock error enable" "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled"
newline
bitfld.long 0x00 10. "PRTCL_EN,P-channel protocol error enable" "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled"
newline
bitfld.long 0x00 9. "CRPT_EN,P-channel corruption error enable" "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled"
newline
rbitfld.long 0x00 8. "Reserved_8,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 7. "PRTCL_EIJT,P-channel protocol error injection" "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active"
newline
bitfld.long 0x00 6. "CRPT_EIJT,P-channel corruption error injection" "0,1"
newline
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 4. "LOCK_EIJT,FSM deadlock error injection" "0,1"
newline
bitfld.long 0x00 3. "PRTCL_CLR,P-channel protocol error clear" "0,1"
newline
bitfld.long 0x00 2. "CRPT_CLR,P-channel corruption error clear" "0,1"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "LOCK_CLR,FSM deadlock error clear" "0,1"
group.long 0x850++0x03
line.long 0x00 "PDENYSTSRC0_CORE1,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
rbitfld.long 0x00 4.--5. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0x854++0x03
line.long 0x00 "PDENYINTRC0_CORE1,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
rbitfld.long 0x00 4.--5. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0x858++0x03
line.long 0x00 "FSMSTSRC0_CORE1,This register is a 32-bit readable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "STATE_7_0,Indicate current state of A3 FSM"
group.long 0x85C++0x03
line.long 0x00 "G2GPRC0_CORE1,This register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "GPR0_31_0,This fields are allowed to write any values and they don't affect module operation"
group.long 0x860++0x03
line.long 0x00 "SAFECTRLC0_CORE1,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are always read as H'0000 0"
newline
bitfld.long 0x00 13. "DBGEN_PPDN,When Cortex-A55 is in debug mode Cortex-A55 core is goes to OFF_EMU mode instead of OFF mode" "0: Cortex-A55 goes to OFF mode,1: Cortex-A55 goes to OFF_EMU mode"
newline
hexmask.long.byte 0x00 5.--12. 1. "Reserved_5,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4. "A1_RTT,A1 RuntimeTEST enable" "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A55 cores are booted" "0: RuntimeTEST is disabled before Cortex-A55 cores,1: RuntimeTEST is enabled before Cortex-A55 cores"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0x870++0x03
line.long 0x00 "RVBARLC0_CORE1,This register is a 32-bit readable/writable register"
hexmask.long 0x00 2.--31. 1. "RVBAR_31_2,These bits indicate RVBARADDR[31:2]"
newline
rbitfld.long 0x00 0.--1. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3"
group.long 0x874++0x03
line.long 0x00 "RVBARHC0_CORE1,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--11. 1. "RVBAR_43_32,These bits indicate RVBARADDR[43:32]"
group.long 0x878++0x03
line.long 0x00 "RVBARPLC0_CORE1,This register is a 32-bit readable/writable register"
hexmask.long 0x00 2.--31. 1. "RVBARP_31_2,These bits indicate RVBARADDR[31:2]"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "VLD,RVBARP valid" "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR"
group.long 0x87C++0x03
line.long 0x00 "RVBARPHC0_CORE1,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--11. 1. "RVBARP_43_32,These bits indicate RVBARADDR[43:32]"
group.long 0xA00++0x03
line.long 0x00 "PWRCTRLC0_CORE2,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 19.--31. 1. "Reserved_19,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol" "0: Power mode transition to OFF_EMU mode is..,1: Power mode transition to OFF_EMU mode is.."
newline
bitfld.long 0x00 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled"
newline
bitfld.long 0x00 16. "PCHWUPEN,ON mode transition enable by P-channel protocol" "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled"
newline
hexmask.long.word 0x00 6.--15. 1. "Reserved_6,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 5. "DWUP_EN,This bit enables wakeup request from Debugger" "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled"
newline
bitfld.long 0x00 4. "IWUP_EN,This bit enables wakeup request from INTC-AP" "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "WUP_REQ,Wake up request" "0: Power on is not requested,1: Power on is requested"
group.long 0xA0C++0x03
line.long 0x00 "FSMLOCKRC0_CORE2,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 16.--31. 1. "CNT_VALUE_15_0,Indicates count value for FSM deadlock error"
newline
rbitfld.long 0x00 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred" "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred"
newline
rbitfld.long 0x00 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred" "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred"
newline
rbitfld.long 0x00 13. "Reserved_13,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred" "0: FSM dead lock has not occurred,1: FSM dead lock has occurred"
newline
bitfld.long 0x00 11. "LOCK_EN,FSM deadlock error enable" "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled"
newline
bitfld.long 0x00 10. "PRTCL_EN,P-channel protocol error enable" "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled"
newline
bitfld.long 0x00 9. "CRPT_EN,P-channel corruption error enable" "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled"
newline
rbitfld.long 0x00 8. "Reserved_8,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 7. "PRTCL_EIJT,P-channel protocol error injection" "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active"
newline
bitfld.long 0x00 6. "CRPT_EIJT,P-channel corruption error injection" "0,1"
newline
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 4. "LOCK_EIJT,FSM deadlock error injection" "0,1"
newline
bitfld.long 0x00 3. "PRTCL_CLR,P-channel protocol error clear" "0,1"
newline
bitfld.long 0x00 2. "CRPT_CLR,P-channel corruption error clear" "0,1"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "LOCK_CLR,FSM deadlock error clear" "0,1"
group.long 0xA10++0x03
line.long 0x00 "PDENYSTSRC0_CORE2,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
rbitfld.long 0x00 4.--5. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0xA14++0x03
line.long 0x00 "PDENYINTRC0_CORE2,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
rbitfld.long 0x00 4.--5. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0xA18++0x03
line.long 0x00 "FSMSTSRC0_CORE2,This register is a 32-bit readable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "STATE_7_0,Indicate current state of A3 FSM"
group.long 0xA1C++0x03
line.long 0x00 "G2GPRC0_CORE2,This register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "GPR0_31_0,This fields are allowed to write any values and they don't affect module operation"
group.long 0xA20++0x03
line.long 0x00 "SAFECTRLC0_CORE2,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are always read as H'0000 0"
newline
bitfld.long 0x00 13. "DBGEN_PPDN,When Cortex-A55 is in debug mode Cortex-A55 core is goes to OFF_EMU mode instead of OFF mode" "0: Cortex-A55 goes to OFF mode,1: Cortex-A55 goes to OFF_EMU mode"
newline
hexmask.long.byte 0x00 5.--12. 1. "Reserved_5,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4. "A1_RTT,A1 RuntimeTEST enable" "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A55 cores are booted" "0: RuntimeTEST is disabled before Cortex-A55 cores,1: RuntimeTEST is enabled before Cortex-A55 cores"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0xA30++0x03
line.long 0x00 "RVBARLC0_CORE2,This register is a 32-bit readable/writable register"
hexmask.long 0x00 2.--31. 1. "RVBAR_31_2,These bits indicate RVBARADDR[31:2]"
newline
rbitfld.long 0x00 0.--1. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3"
group.long 0xA34++0x03
line.long 0x00 "RVBARHC0_CORE2,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--11. 1. "RVBAR_43_32,These bits indicate RVBARADDR[43:32]"
group.long 0xA38++0x03
line.long 0x00 "RVBARPLC0_CORE2,This register is a 32-bit readable/writable register"
hexmask.long 0x00 2.--31. 1. "RVBARP_31_2,These bits indicate RVBARADDR[31:2]"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "VLD,RVBARP valid" "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR"
group.long 0xA3C++0x03
line.long 0x00 "RVBARPHC0_CORE2,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--11. 1. "RVBARP_43_32,These bits indicate RVBARADDR[43:32]"
group.long 0xA40++0x03
line.long 0x00 "PWRCTRLC0_CORE3,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 19.--31. 1. "Reserved_19,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol" "0: Power mode transition to OFF_EMU mode is..,1: Power mode transition to OFF_EMU mode is.."
newline
bitfld.long 0x00 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled"
newline
bitfld.long 0x00 16. "PCHWUPEN,ON mode transition enable by P-channel protocol" "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled"
newline
hexmask.long.word 0x00 6.--15. 1. "Reserved_6,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 5. "DWUP_EN,This bit enables wakeup request from Debugger" "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled"
newline
bitfld.long 0x00 4. "IWUP_EN,This bit enables wakeup request from INTC-AP" "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "WUP_REQ,Wake up request" "0: Power on is not requested,1: Power on is requested"
group.long 0xA4C++0x03
line.long 0x00 "FSMLOCKRC0_CORE3,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 16.--31. 1. "CNT_VALUE_15_0,Indicates count value for FSM deadlock error"
newline
rbitfld.long 0x00 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred" "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred"
newline
rbitfld.long 0x00 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred" "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred"
newline
rbitfld.long 0x00 13. "Reserved_13,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred" "0: FSM dead lock has not occurred,1: FSM dead lock has occurred"
newline
bitfld.long 0x00 11. "LOCK_EN,FSM deadlock error enable" "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled"
newline
bitfld.long 0x00 10. "PRTCL_EN,P-channel protocol error enable" "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled"
newline
bitfld.long 0x00 9. "CRPT_EN,P-channel corruption error enable" "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled"
newline
rbitfld.long 0x00 8. "Reserved_8,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 7. "PRTCL_EIJT,P-channel protocol error injection" "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active"
newline
bitfld.long 0x00 6. "CRPT_EIJT,P-channel corruption error injection" "0,1"
newline
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 4. "LOCK_EIJT,FSM deadlock error injection" "0,1"
newline
bitfld.long 0x00 3. "PRTCL_CLR,P-channel protocol error clear" "0,1"
newline
bitfld.long 0x00 2. "CRPT_CLR,P-channel corruption error clear" "0,1"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "LOCK_CLR,FSM deadlock error clear" "0,1"
group.long 0xA50++0x03
line.long 0x00 "PDENYSTSRC0_CORE3,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
rbitfld.long 0x00 4.--5. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0xA54++0x03
line.long 0x00 "PDENYINTRC0_CORE3,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
rbitfld.long 0x00 4.--5. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0xA58++0x03
line.long 0x00 "FSMSTSRC0_CORE3,This register is a 32-bit readable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "STATE_7_0,Indicate current state of A3 FSM"
group.long 0xA5C++0x03
line.long 0x00 "G2GPRC0_CORE3,This register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "GPR0_31_0,This fields are allowed to write any values and they don't affect module operation"
group.long 0xA60++0x03
line.long 0x00 "SAFECTRLC0_CORE3,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are always read as H'0000 0"
newline
bitfld.long 0x00 13. "DBGEN_PPDN,When Cortex-A55 is in debug mode Cortex-A55 core is goes to OFF_EMU mode instead of OFF mode" "0: Cortex-A55 goes to OFF mode,1: Cortex-A55 goes to OFF_EMU mode"
newline
hexmask.long.byte 0x00 5.--12. 1. "Reserved_5,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4. "A1_RTT,A1 RuntimeTEST enable" "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A55 cores are booted" "0: RuntimeTEST is disabled before Cortex-A55 cores,1: RuntimeTEST is enabled before Cortex-A55 cores"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0xA70++0x03
line.long 0x00 "RVBARLC0_CORE3,This register is a 32-bit readable/writable register"
hexmask.long 0x00 2.--31. 1. "RVBAR_31_2,These bits indicate RVBARADDR[31:2]"
newline
rbitfld.long 0x00 0.--1. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3"
group.long 0xA74++0x03
line.long 0x00 "RVBARHC0_CORE3,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--11. 1. "RVBAR_43_32,These bits indicate RVBARADDR[43:32]"
group.long 0xA78++0x03
line.long 0x00 "RVBARPLC0_CORE3,This register is a 32-bit readable/writable register"
hexmask.long 0x00 2.--31. 1. "RVBARP_31_2,These bits indicate RVBARADDR[31:2]"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "VLD,RVBARP valid" "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR"
group.long 0xA7C++0x03
line.long 0x00 "RVBARPHC0_CORE3,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--11. 1. "RVBARP_43_32,These bits indicate RVBARADDR[43:32]"
group.long 0xC00++0x03
line.long 0x00 "PWRCTRLC0_CORE4,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 19.--31. 1. "Reserved_19,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol" "0: Power mode transition to OFF_EMU mode is..,1: Power mode transition to OFF_EMU mode is.."
newline
bitfld.long 0x00 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled"
newline
bitfld.long 0x00 16. "PCHWUPEN,ON mode transition enable by P-channel protocol" "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled"
newline
hexmask.long.word 0x00 6.--15. 1. "Reserved_6,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 5. "DWUP_EN,This bit enables wakeup request from Debugger" "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled"
newline
bitfld.long 0x00 4. "IWUP_EN,This bit enables wakeup request from INTC-AP" "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "WUP_REQ,Wake up request" "0: Power on is not requested,1: Power on is requested"
group.long 0xC0C++0x03
line.long 0x00 "FSMLOCKRC0_CORE4,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 16.--31. 1. "CNT_VALUE_15_0,Indicates count value for FSM deadlock error"
newline
rbitfld.long 0x00 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred" "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred"
newline
rbitfld.long 0x00 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred" "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred"
newline
rbitfld.long 0x00 13. "Reserved_13,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred" "0: FSM dead lock has not occurred,1: FSM dead lock has occurred"
newline
bitfld.long 0x00 11. "LOCK_EN,FSM deadlock error enable" "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled"
newline
bitfld.long 0x00 10. "PRTCL_EN,P-channel protocol error enable" "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled"
newline
bitfld.long 0x00 9. "CRPT_EN,P-channel corruption error enable" "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled"
newline
rbitfld.long 0x00 8. "Reserved_8,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 7. "PRTCL_EIJT,P-channel protocol error injection" "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active"
newline
bitfld.long 0x00 6. "CRPT_EIJT,P-channel corruption error injection" "0,1"
newline
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 4. "LOCK_EIJT,FSM deadlock error injection" "0,1"
newline
bitfld.long 0x00 3. "PRTCL_CLR,P-channel protocol error clear" "0,1"
newline
bitfld.long 0x00 2. "CRPT_CLR,P-channel corruption error clear" "0,1"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "LOCK_CLR,FSM deadlock error clear" "0,1"
group.long 0xC10++0x03
line.long 0x00 "PDENYSTSRC0_CORE4,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
rbitfld.long 0x00 4.--5. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0xC14++0x03
line.long 0x00 "PDENYINTRC0_CORE4,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
rbitfld.long 0x00 4.--5. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0xC18++0x03
line.long 0x00 "FSMSTSRC0_CORE4,This register is a 32-bit readable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "STATE_7_0,Indicate current state of A3 FSM"
group.long 0xC1C++0x03
line.long 0x00 "G2GPRC0_CORE4,This register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "GPR0_31_0,This fields are allowed to write any values and they don't affect module operation"
group.long 0xC20++0x03
line.long 0x00 "SAFECTRLC0_CORE4,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are always read as H'0000 0"
newline
bitfld.long 0x00 13. "DBGEN_PPDN,When Cortex-A55 is in debug mode Cortex-A55 core is goes to OFF_EMU mode instead of OFF mode" "0: Cortex-A55 goes to OFF mode,1: Cortex-A55 goes to OFF_EMU mode"
newline
hexmask.long.byte 0x00 5.--12. 1. "Reserved_5,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4. "A1_RTT,A1 RuntimeTEST enable" "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A55 cores are booted" "0: RuntimeTEST is disabled before Cortex-A55 cores,1: RuntimeTEST is enabled before Cortex-A55 cores"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0xC30++0x03
line.long 0x00 "RVBARLC0_CORE4,This register is a 32-bit readable/writable register"
hexmask.long 0x00 2.--31. 1. "RVBAR_31_2,These bits indicate RVBARADDR[31:2]"
newline
rbitfld.long 0x00 0.--1. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3"
group.long 0xC34++0x03
line.long 0x00 "RVBARHC0_CORE4,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--11. 1. "RVBAR_43_32,These bits indicate RVBARADDR[43:32]"
group.long 0xC38++0x03
line.long 0x00 "RVBARPLC0_CORE4,This register is a 32-bit readable/writable register"
hexmask.long 0x00 2.--31. 1. "RVBARP_31_2,These bits indicate RVBARADDR[31:2]"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "VLD,RVBARP valid" "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR"
group.long 0xC3C++0x03
line.long 0x00 "RVBARPHC0_CORE4,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--11. 1. "RVBARP_43_32,These bits indicate RVBARADDR[43:32]"
group.long 0xC40++0x03
line.long 0x00 "PWRCTRLC0_CORE5,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 19.--31. 1. "Reserved_19,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol" "0: Power mode transition to OFF_EMU mode is..,1: Power mode transition to OFF_EMU mode is.."
newline
bitfld.long 0x00 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled"
newline
bitfld.long 0x00 16. "PCHWUPEN,ON mode transition enable by P-channel protocol" "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled"
newline
hexmask.long.word 0x00 6.--15. 1. "Reserved_6,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 5. "DWUP_EN,This bit enables wakeup request from Debugger" "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled"
newline
bitfld.long 0x00 4. "IWUP_EN,This bit enables wakeup request from INTC-AP" "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "WUP_REQ,Wake up request" "0: Power on is not requested,1: Power on is requested"
group.long 0xC4C++0x03
line.long 0x00 "FSMLOCKRC0_CORE5,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 16.--31. 1. "CNT_VALUE_15_0,Indicates count value for FSM deadlock error"
newline
rbitfld.long 0x00 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred" "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred"
newline
rbitfld.long 0x00 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred" "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred"
newline
rbitfld.long 0x00 13. "Reserved_13,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred" "0: FSM dead lock has not occurred,1: FSM dead lock has occurred"
newline
bitfld.long 0x00 11. "LOCK_EN,FSM deadlock error enable" "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled"
newline
bitfld.long 0x00 10. "PRTCL_EN,P-channel protocol error enable" "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled"
newline
bitfld.long 0x00 9. "CRPT_EN,P-channel corruption error enable" "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled"
newline
rbitfld.long 0x00 8. "Reserved_8,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 7. "PRTCL_EIJT,P-channel protocol error injection" "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active"
newline
bitfld.long 0x00 6. "CRPT_EIJT,P-channel corruption error injection" "0,1"
newline
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 4. "LOCK_EIJT,FSM deadlock error injection" "0,1"
newline
bitfld.long 0x00 3. "PRTCL_CLR,P-channel protocol error clear" "0,1"
newline
bitfld.long 0x00 2. "CRPT_CLR,P-channel corruption error clear" "0,1"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "LOCK_CLR,FSM deadlock error clear" "0,1"
group.long 0xC50++0x03
line.long 0x00 "PDENYSTSRC0_CORE5,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
rbitfld.long 0x00 4.--5. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0xC54++0x03
line.long 0x00 "PDENYINTRC0_CORE5,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
rbitfld.long 0x00 4.--5. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0xC58++0x03
line.long 0x00 "FSMSTSRC0_CORE5,This register is a 32-bit readable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "STATE_7_0,Indicate current state of A3 FSM"
group.long 0xC5C++0x03
line.long 0x00 "G2GPRC0_CORE5,This register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "GPR0_31_0,This fields are allowed to write any values and they don't affect module operation"
group.long 0xC60++0x03
line.long 0x00 "SAFECTRLC0_CORE5,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are always read as H'0000 0"
newline
bitfld.long 0x00 13. "DBGEN_PPDN,When Cortex-A55 is in debug mode Cortex-A55 core is goes to OFF_EMU mode instead of OFF mode" "0: Cortex-A55 goes to OFF mode,1: Cortex-A55 goes to OFF_EMU mode"
newline
hexmask.long.byte 0x00 5.--12. 1. "Reserved_5,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4. "A1_RTT,A1 RuntimeTEST enable" "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A55 cores are booted" "0: RuntimeTEST is disabled before Cortex-A55 cores,1: RuntimeTEST is enabled before Cortex-A55 cores"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0xC70++0x03
line.long 0x00 "RVBARLC0_CORE5,This register is a 32-bit readable/writable register"
hexmask.long 0x00 2.--31. 1. "RVBAR_31_2,These bits indicate RVBARADDR[31:2]"
newline
rbitfld.long 0x00 0.--1. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3"
group.long 0xC74++0x03
line.long 0x00 "RVBARHC0_CORE5,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--11. 1. "RVBAR_43_32,These bits indicate RVBARADDR[43:32]"
group.long 0xC78++0x03
line.long 0x00 "RVBARPLC0_CORE5,This register is a 32-bit readable/writable register"
hexmask.long 0x00 2.--31. 1. "RVBARP_31_2,These bits indicate RVBARADDR[31:2]"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "VLD,RVBARP valid" "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR"
group.long 0xC7C++0x03
line.long 0x00 "RVBARPHC0_CORE5,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--11. 1. "RVBARP_43_32,These bits indicate RVBARADDR[43:32]"
group.long 0xE00++0x03
line.long 0x00 "PWRCTRLC0_CORE6,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 19.--31. 1. "Reserved_19,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol" "0: Power mode transition to OFF_EMU mode is..,1: Power mode transition to OFF_EMU mode is.."
newline
bitfld.long 0x00 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled"
newline
bitfld.long 0x00 16. "PCHWUPEN,ON mode transition enable by P-channel protocol" "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled"
newline
hexmask.long.word 0x00 6.--15. 1. "Reserved_6,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 5. "DWUP_EN,This bit enables wakeup request from Debugger" "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled"
newline
bitfld.long 0x00 4. "IWUP_EN,This bit enables wakeup request from INTC-AP" "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "WUP_REQ,Wake up request" "0: Power on is not requested,1: Power on is requested"
group.long 0xE0C++0x03
line.long 0x00 "FSMLOCKRC0_CORE6,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 16.--31. 1. "CNT_VALUE_15_0,Indicates count value for FSM deadlock error"
newline
rbitfld.long 0x00 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred" "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred"
newline
rbitfld.long 0x00 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred" "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred"
newline
rbitfld.long 0x00 13. "Reserved_13,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred" "0: FSM dead lock has not occurred,1: FSM dead lock has occurred"
newline
bitfld.long 0x00 11. "LOCK_EN,FSM deadlock error enable" "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled"
newline
bitfld.long 0x00 10. "PRTCL_EN,P-channel protocol error enable" "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled"
newline
bitfld.long 0x00 9. "CRPT_EN,P-channel corruption error enable" "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled"
newline
rbitfld.long 0x00 8. "Reserved_8,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 7. "PRTCL_EIJT,P-channel protocol error injection" "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active"
newline
bitfld.long 0x00 6. "CRPT_EIJT,P-channel corruption error injection" "0,1"
newline
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 4. "LOCK_EIJT,FSM deadlock error injection" "0,1"
newline
bitfld.long 0x00 3. "PRTCL_CLR,P-channel protocol error clear" "0,1"
newline
bitfld.long 0x00 2. "CRPT_CLR,P-channel corruption error clear" "0,1"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "LOCK_CLR,FSM deadlock error clear" "0,1"
group.long 0xE10++0x03
line.long 0x00 "PDENYSTSRC0_CORE6,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
rbitfld.long 0x00 4.--5. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0xE14++0x03
line.long 0x00 "PDENYINTRC0_CORE6,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
rbitfld.long 0x00 4.--5. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0xE18++0x03
line.long 0x00 "FSMSTSRC0_CORE6,This register is a 32-bit readable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "STATE_7_0,Indicate current state of A3 FSM"
group.long 0xE1C++0x03
line.long 0x00 "G2GPRC0_CORE6,This register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "GPR0_31_0,This fields are allowed to write any values and they don't affect module operation"
group.long 0xE20++0x03
line.long 0x00 "SAFECTRLC0_CORE6,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are always read as H'0000 0"
newline
bitfld.long 0x00 13. "DBGEN_PPDN,When Cortex-A55 is in debug mode Cortex-A55 core is goes to OFF_EMU mode instead of OFF mode" "0: Cortex-A55 goes to OFF mode,1: Cortex-A55 goes to OFF_EMU mode"
newline
hexmask.long.byte 0x00 5.--12. 1. "Reserved_5,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4. "A1_RTT,A1 RuntimeTEST enable" "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A55 cores are booted" "0: RuntimeTEST is disabled before Cortex-A55 cores,1: RuntimeTEST is enabled before Cortex-A55 cores"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0xE30++0x03
line.long 0x00 "RVBARLC0_CORE6,This register is a 32-bit readable/writable register"
hexmask.long 0x00 2.--31. 1. "RVBAR_31_2,These bits indicate RVBARADDR[31:2]"
newline
rbitfld.long 0x00 0.--1. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3"
group.long 0xE34++0x03
line.long 0x00 "RVBARHC0_CORE6,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--11. 1. "RVBAR_43_32,These bits indicate RVBARADDR[43:32]"
group.long 0xE38++0x03
line.long 0x00 "RVBARPLC0_CORE6,This register is a 32-bit readable/writable register"
hexmask.long 0x00 2.--31. 1. "RVBARP_31_2,These bits indicate RVBARADDR[31:2]"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "VLD,RVBARP valid" "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR"
group.long 0xE3C++0x03
line.long 0x00 "RVBARPHC0_CORE6,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--11. 1. "RVBARP_43_32,These bits indicate RVBARADDR[43:32]"
group.long 0xE40++0x03
line.long 0x00 "PWRCTRLC0_CORE7,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 19.--31. 1. "Reserved_19,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol" "0: Power mode transition to OFF_EMU mode is..,1: Power mode transition to OFF_EMU mode is.."
newline
bitfld.long 0x00 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled"
newline
bitfld.long 0x00 16. "PCHWUPEN,ON mode transition enable by P-channel protocol" "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled"
newline
hexmask.long.word 0x00 6.--15. 1. "Reserved_6,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 5. "DWUP_EN,This bit enables wakeup request from Debugger" "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled"
newline
bitfld.long 0x00 4. "IWUP_EN,This bit enables wakeup request from INTC-AP" "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "WUP_REQ,Wake up request" "0: Power on is not requested,1: Power on is requested"
group.long 0xE4C++0x03
line.long 0x00 "FSMLOCKRC0_CORE7,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 16.--31. 1. "CNT_VALUE_15_0,Indicates count value for FSM deadlock error"
newline
rbitfld.long 0x00 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred" "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred"
newline
rbitfld.long 0x00 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred" "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred"
newline
rbitfld.long 0x00 13. "Reserved_13,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred" "0: FSM dead lock has not occurred,1: FSM dead lock has occurred"
newline
bitfld.long 0x00 11. "LOCK_EN,FSM deadlock error enable" "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled"
newline
bitfld.long 0x00 10. "PRTCL_EN,P-channel protocol error enable" "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled"
newline
bitfld.long 0x00 9. "CRPT_EN,P-channel corruption error enable" "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled"
newline
rbitfld.long 0x00 8. "Reserved_8,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 7. "PRTCL_EIJT,P-channel protocol error injection" "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active"
newline
bitfld.long 0x00 6. "CRPT_EIJT,P-channel corruption error injection" "0,1"
newline
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 4. "LOCK_EIJT,FSM deadlock error injection" "0,1"
newline
bitfld.long 0x00 3. "PRTCL_CLR,P-channel protocol error clear" "0,1"
newline
bitfld.long 0x00 2. "CRPT_CLR,P-channel corruption error clear" "0,1"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "LOCK_CLR,FSM deadlock error clear" "0,1"
group.long 0xE50++0x03
line.long 0x00 "PDENYSTSRC0_CORE7,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
rbitfld.long 0x00 4.--5. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0xE54++0x03
line.long 0x00 "PDENYINTRC0_CORE7,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
rbitfld.long 0x00 4.--5. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0xE58++0x03
line.long 0x00 "FSMSTSRC0_CORE7,This register is a 32-bit readable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "STATE_7_0,Indicate current state of A3 FSM"
group.long 0xE5C++0x03
line.long 0x00 "G2GPRC0_CORE7,This register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "GPR0_31_0,This fields are allowed to write any values and they don't affect module operation"
group.long 0xE60++0x03
line.long 0x00 "SAFECTRLC0_CORE7,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are always read as H'0000 0"
newline
bitfld.long 0x00 13. "DBGEN_PPDN,When Cortex-A55 is in debug mode Cortex-A55 core is goes to OFF_EMU mode instead of OFF mode" "0: Cortex-A55 goes to OFF mode,1: Cortex-A55 goes to OFF_EMU mode"
newline
hexmask.long.byte 0x00 5.--12. 1. "Reserved_5,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4. "A1_RTT,A1 RuntimeTEST enable" "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A55 cores are booted" "0: RuntimeTEST is disabled before Cortex-A55 cores,1: RuntimeTEST is enabled before Cortex-A55 cores"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0xE70++0x03
line.long 0x00 "RVBARLC0_CORE7,This register is a 32-bit readable/writable register"
hexmask.long 0x00 2.--31. 1. "RVBAR_31_2,These bits indicate RVBARADDR[31:2]"
newline
rbitfld.long 0x00 0.--1. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3"
group.long 0xE74++0x03
line.long 0x00 "RVBARHC0_CORE7,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--11. 1. "RVBAR_43_32,These bits indicate RVBARADDR[43:32]"
group.long 0xE78++0x03
line.long 0x00 "RVBARPLC0_CORE7,This register is a 32-bit readable/writable register"
hexmask.long 0x00 2.--31. 1. "RVBARP_31_2,These bits indicate RVBARADDR[31:2]"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "VLD,RVBARP valid" "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR"
group.long 0xE7C++0x03
line.long 0x00 "RVBARPHC0_CORE7,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--11. 1. "RVBARP_43_32,These bits indicate RVBARADDR[43:32]"
tree.end
tree "APMU_INST_1"
base ad:0xE6171000
group.long 0x00++0x03
line.long 0x00 "WPCR1,This register is 32-bit readable/writable register"
hexmask.long.word 0x00 16.--31. 1. "Code_value,Code Value Code value (H'5AA5) needs to be set to this field when some values are set to this register"
newline
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 0. "WPE,Write Protect Enable" "0: Write protect is disabled,1: Write protect is enabled"
group.long 0x04++0x03
line.long 0x00 "WPR1,These registers are 32-bit readable/writable registers"
hexmask.long 0x00 0.--31. 1. "WPRTCT_31_0,If Write Protect is enabled inverted values need to be set to this field before write access"
group.long 0x20++0x03
line.long 0x00 "PTCSR1,This register is a 32-bit readable/writable register"
hexmask.long 0x00 2.--31. 1. "Reserved_2,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "ERR,Indicates whether access error has occurred" "0: error has not occurred,1: error has occurred"
group.long 0x24++0x03
line.long 0x00 "PTERADR1,This register is a 32-bit readable register"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--15. 1. "ADDR_15_0,Indicate address causing access error"
group.long 0x28++0x03
line.long 0x00 "DCLSEIJTR1,This register is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 0. "EIJT,Error Injection enable" "0: error injection is not active,1: error injection is active"
repeat 2. (strings "01" "11" )(list 0x0 0x4 )
group.long ($2+0x40)++0x03
line.long 0x00 "A3PWRCTRL$1,This register is a 32-bit readable/writable register"
hexmask.long 0x00 5.--31. 1. "Reserved_5,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4. "A3_PDN_EN,Power down enable for A3 power domain" "0: A3 power domain cannot be powered down,1: A3 power domain is powered down if all A1 and.."
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
repeat.end
repeat 2. (strings "01" "11" )(list 0x0 0x4 )
group.long ($2+0x48)++0x03
line.long 0x00 "A3FSMSTSR$1,This register is a 32-bit readable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "STATE_7_0,Indicate current state of A3 FSM"
repeat.end
repeat 2. (strings "01" "11" )(list 0x0 0x4 )
group.long ($2+0x50)++0x03
line.long 0x00 "A3FSMLOCKR$1,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 16.--31. 1. "CNT_VALUE_15_0,Indicates count value for FSM deadlock error"
newline
rbitfld.long 0x00 13.--15. "Reserved_13,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred" "0: FSM dead lock has not occurred,1: FSM dead lock has occurred"
newline
bitfld.long 0x00 11. "LOCK_EN,FSM deadlock error enable" "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled"
newline
rbitfld.long 0x00 5.--10. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 4. "LOCK_EIJT,FSM deadlock error injection" "0,1"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "LOCK_CLR,FSM deadlock error clear" "0,1"
repeat.end
group.long 0x58++0x03
line.long 0x00 "INTSTSR1,This register is a 32-bit readable register"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 16.--19. "A2Cx_INT,Indicate whether each A2 domain FSM issues interrupt request" "0: FSM doesn't issue interrupt request,1: FSM issues interrupt request,?..."
newline
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
abitfld.long 0x00 0.--7. "A1Cx_INT,Indicate whether each A2 domain FSM issues interrupt request" "0x00=0: FSM doesn't issue interrupt request,0x01=1: FSM issues interrupt request"
group.long 0x5C++0x03
line.long 0x00 "ERRSTSR1,This register is a 32-bit readable register"
rbitfld.long 0x00 29.--31. "Reserved_29,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 28. "CR52_ERR,Indicates whether error flag is set in FSMLOCKRCR52" "0: Error is not detected,1: Error is detected and flag is set in.."
newline
rbitfld.long 0x00 26.--27. "Reserved_26,Reserved These bits are always read as 0" "0,1,2,3"
newline
rbitfld.long 0x00 24.--25. "A3Sx_ERR,Indicates whether error flag is set in A3FSMLOCKRx" "0: Error is not detected,1: Error is detected and flag is set in..,?..."
newline
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 16.--19. "A2Cx_ERR,Indicates whether error flag is set in FSMLOCKRCLx" "0: Error is not detected,1: Error is detected and flag is set in..,?..."
newline
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
abitfld.long 0x00 0.--7. "A1Cx_ERR,Indicates whether error flag is set in FSMLOCKRCx" "0x00=0: Error is not detected,0x01=1: Error is detected and flag is set in.."
group.long 0x60++0x03
line.long 0x00 "FRSTR1,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 16.--19. "FRSTRCLx,Forced reset request for each Cortex-A55 cluster" "0: Forced reset is not requested,1: Forced reset is requested,?..."
newline
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
abitfld.long 0x00 0.--7. "FRSTRCx,Forced reset request for each Cortex-A55 core" "0x00=0: Forced reset is not requested,0x01=1: Forced reset is requested"
group.long 0x68++0x03
line.long 0x00 "FRSTCTRL1,This register is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved These bits are always read as 1" "0,1"
newline
bitfld.long 0x00 30. "FRST_MOD_DBG,Forced reset modification in debug mode" "0: All reset signals are asserted by forced reset,1: Only warm reset of Cortex-A55 is asserted by"
newline
rbitfld.long 0x00 29. "Reserved_29,Reserved These bits are always read as 1" "0,1"
newline
rbitfld.long 0x00 28. "Reserved_28,Reserved These bits are always read as 1" "0,1"
newline
rbitfld.long 0x00 27. "Reserved_27,Reserved These bits are always read as 1" "0,1"
newline
hexmask.long 0x00 0.--26. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x80++0x03
line.long 0x00 "PADDCHKSTSR1,This register is a 32-bit readable/writable register"
bitfld.long 0x00 31. "PADD_CHK_SID_CLR,PADD_CHK_SID clear bit" "0,1"
newline
hexmask.long.tbyte 0x00 8.--30. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "PADD_CHK_SID_7_0,Indicates Source ID of fault transaction detected PADD_CHK mechanism"
group.long 0x84++0x03
line.long 0x00 "PWDATACHKSTSR1,This register is a 32-bit readable/writable register"
bitfld.long 0x00 31. "PWDATA_CHK_SID_CLR,PWDATA_CHK_SID clear bit" "0,1"
newline
hexmask.long.tbyte 0x00 8.--30. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "PWDATA_CHK_SID_7_0,Indicates Source ID of fault transaction detected PWDATA_CHK mechanism"
group.long 0xA4++0x03
line.long 0x00 "AA64nAA32CR1,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 13. "AA64nAA32_c7,AA64nAA32 control bit of Core 7" "0: AA32 mode,1: AA64 mode"
newline
bitfld.long 0x00 12. "AA64nAA32_c6,AA64nAA32 control bit of Core 6" "0: AA32 mode,1: AA64 mode"
newline
rbitfld.long 0x00 10.--11. "Reserved_10,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 9. "AA64nAA32_c5,AA64nAA32 control bit of Core 5" "0: AA32 mode,1: AA64 mode"
newline
bitfld.long 0x00 8. "AA64nAA32_c4,AA64nAA32 control bit of Core 4" "0: AA32 mode,1: AA64 mode"
newline
rbitfld.long 0x00 6.--7. "Reserved_6,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 5. "AA64nAA32_c3,AA64nAA32 control bit of Core 3" "0: AA32 mode,1: AA64 mode"
newline
bitfld.long 0x00 4. "AA64nAA32_c2,AA64nAA32 control bit of Core 2" "0: AA32 mode,1: AA64 mode"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "AA64nAA32_c1,AA64nAA32 control bit of Core 1" "0: AA32 mode,1: AA64 mode"
newline
bitfld.long 0x00 0. "AA64nAA32_c0,AA64nAA32 control bit of Core 0" "0: AA32 mode,1: AA64 mode"
group.long 0x300++0x03
line.long 0x00 "CR52CR1,This register is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 30. "NCPUHALT,NCPUHALT means inverted value of CPUHALT defined in Cortex-R52 TRM" "0: Processor halt after reset,1: No processor halt after reset"
newline
bitfld.long 0x00 29. "CFGRAMPROTEN,CFGRAMPROTEN defined in Cortex-R52 TRM" "0: RAM memory protection is disabled out of reset,1: RAM memory protection is enabled out of reset"
newline
bitfld.long 0x00 28. "CFGTCMBOOT,CFGTCMBOOT defined in Cortex-R52 TRM" "0: ATCM is disabled out of reset,1: ATCM is enabled and at address 0x0 out of reset"
newline
bitfld.long 0x00 27. "CFGINITREG,CFGINITREG defined in Cortex-R52 TRM" "0: Program-visible registers are not initialized..,1: Program-visible registers are initialized to"
newline
bitfld.long 0x00 26. "CFGL1CACHEINVDIS0,CFGL1CACHEINVDIS defined in Cortex-R52 TRM" "0: Automatic post-reset L1 cache invalidate is,1: Automatic post-reset L1 cache invalidate is"
newline
hexmask.long 0x00 0.--25. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x304++0x03
line.long 0x00 "CR52RSTCTRL1,This register is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 0. "CR52RST,Cortex-R52 reset" "0: All Cortex-R52 resets are negated,1: All Cortex-R52 resets are asserted"
group.long 0x30C++0x03
line.long 0x00 "FSMLOCKRCR521,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 16.--31. 1. "CNT_VALUE_15_0,Indicates count value for FSM deadlock error"
newline
rbitfld.long 0x00 13.--15. "Reserved_13,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred" "0: FSM dead lock has not occurred,1: FSM dead lock has occurred"
newline
bitfld.long 0x00 11. "LOCK_EN,FSM deadlock error enable" "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled"
newline
rbitfld.long 0x00 5.--10. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 4. "LOCK_EIJT,FSM deadlock error injection" "0,1"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "LOCK_CLR,FSM deadlock error clear" "0,1"
group.long 0x318++0x03
line.long 0x00 "FSMSTSRCR521,This register is a 32-bit readable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "STATE_7_0,Indicate current state of Cortex-R52 FSM"
group.long 0x31C++0x03
line.long 0x00 "G2GPRCR521,This register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "GPR_31_0,This fields are allowed to write any values and they don't affect module operation"
group.long 0x328++0x03
line.long 0x00 "CR52CMPEN1,This register is a 32-bit readable/writable register"
hexmask.long 0x00 2.--31. 1. "Reserved_2,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 1. "NSRCMPEN,Non-safety- related comparator enable" "0: Comparator for Non-safety-related signals is,1: Comparator for Non-safety-related signals is"
newline
bitfld.long 0x00 0. "CMPEN,Comparator enables" "0: Comparator is disabled,1: Comparator is enabled"
group.long 0x32C++0x03
line.long 0x00 "GCNTERRENCR521,This register is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 0. "GCNTERREN,Generic Counter error detection enable" "0: Error detection is disabled,1: Error detection is enabled"
group.long 0x330++0x03
line.long 0x00 "CR52RVBAR1,This register is a 32-bit readable/writable register"
hexmask.long 0x00 5.--31. 1. "CFGVECTABLE_31_5,CFGVECTABLE defined in Cortex-R52 TRM"
newline
rbitfld.long 0x00 0.--4. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x334++0x03
line.long 0x00 "CR52BAR1,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 18.--31. 1. "RBAR_31_18,Real time CPU (Cortex-R52) Boot Address"
newline
hexmask.long.word 0x00 5.--17. 1. "Reserved_5,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4. "BAREN,BAR enables" "0,1"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
rbitfld.long 0x00 0.--1. "BTMD_1_0,Boot Mode" "0: RBAR is assigned for boot address,?,2: Boot from BootROM,?..."
group.long 0x338++0x03
line.long 0x00 "CR52RVBARP1,This register is a 32-bit readable/writable register"
hexmask.long 0x00 5.--31. 1. "CFGVECTABLE_31_5,CFGVECTABLE defined in Cortex-R52 TRM"
newline
rbitfld.long 0x00 1.--4. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0. "VLD,CR52RVBARP valid" "0: CR52RVBAR is used to define CFGVECTABLE for,1: CR52RVBARP is used to define CFGVECTABLE for"
group.long 0x33C++0x03
line.long 0x00 "CR52BARP1,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 18.--31. 1. "RBAR_31_18,Real time CPU (Cortex-R52) Boot Address"
newline
hexmask.long.word 0x00 5.--17. 1. "Reserved_5,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4. "BAREN,BAR enables" "0: RBAR is not valid,1: RBAR is valid"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "VLD,CR52BARP valid" "0: CR52BAR is used to define Boot Address of,1: CR52BARP is used to define Boot Address of"
group.long 0x400++0x03
line.long 0x00 "PWRCTRLCL1_CLUSTER0,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 22.--31. 1. "Reserved_22,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 21. "PCHMRETEN,MEM_RET mode transition enable by P-channel protocol" "0,1"
newline
bitfld.long 0x00 20. "PCHFRETEN,FUNC_RET mode transition enable by P-channel protocol" "0: Power mode transition to FUNC_RET mode is..,1: Power mode transition to FUNC_RET mode is.."
newline
rbitfld.long 0x00 18.--19. "Reserved_18,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 17. "PCHPDNEN,OFF mode transition enable by P-channel protocol" "0,1"
newline
bitfld.long 0x00 16. "PCHWUPEN,ON mode transition enable by P-channel protocol" "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled"
newline
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0x404++0x03
line.long 0x00 "L3CTRLCL1_CLUSTER0,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 19.--31. 1. "Reserved_19,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 16.--18. "L3STS_2_0,Indicates current L3 cache partial power down/up status" "?,1: 1/4 of L3 cache is powered on,2: 1/2 of L3 cache is powered on,3: 3/4 of L3 cache is powered on,4: All L3 cache is powered on,?..."
newline
rbitfld.long 0x00 10.--15. "Reserved_10,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 9. "L3DENY,Indicates whether L3 cache partial power down/up request is denied" "0: request is not denied,1: request is denied"
newline
bitfld.long 0x00 8. "L3ACCEPT,Indicates whether L3 cache partial power down/up request is accepted" "0: request is not accepted,1: request is accepted"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4. "L3REQ,L3 cache partial power down/up request" "0: L3 cache partial power down/up is not requested,1: L3 cache partial power down/up is requested"
newline
rbitfld.long 0x00 3. "Reserved_3,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0.--2. "L3CTRL_2_0,L3 cache partial power down/up control" "0: All L3 cache is power-off or Cluster's power,1: 1/4 of L3 cache is power-on,2: 1/2 of L3 cache is power-on,3: 3/4 of L3 cache is power-on,4: All L3 cache is power-on,?..."
group.long 0x40C++0x03
line.long 0x00 "FSMLOCKRCL1_CLUSTER0,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 16.--31. 1. "CNT_VALUE_15_0,Indicates count value for FSM deadlock error"
newline
rbitfld.long 0x00 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred" "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred"
newline
rbitfld.long 0x00 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred" "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred"
newline
rbitfld.long 0x00 13. "Reserved_13,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred" "0: FSM dead lock has not occurred,1: FSM dead lock has occurred"
newline
bitfld.long 0x00 11. "LOCK_EN,FSM deadlock error enable" "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled"
newline
bitfld.long 0x00 10. "PRTCL_EN,P-channel protocol error enable" "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled"
newline
bitfld.long 0x00 9. "CRPT_EN,P-channel corruption error enable" "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled"
newline
rbitfld.long 0x00 8. "Reserved_8,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 7. "PRTCL_EIJT,P-channel protocol error injection" "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active"
newline
bitfld.long 0x00 6. "CRPT_EIJT,P-channel corruption error injection" "0,1"
newline
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 4. "LOCK_EIJT,FSM deadlock error injection" "0,1"
newline
bitfld.long 0x00 3. "PRTCL_CLR,P-channel protocol error clear" "0,1"
newline
bitfld.long 0x00 2. "CRPT_CLR,P-channel corruption error clear" "0,1"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "LOCK_CLR,FSM deadlock error clear" "0,1"
group.long 0x410++0x03
line.long 0x00 "PDENYSTSRCL1_CLUSTER0,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 23.--31. 1. "Reserved_23,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 22. "DNY_OFF_ON,Indicates whether a denied state transition has occurred by power mode transition from OFF mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 21. "DNY_ON_OFF,Indicates whether a denied state transition has occurred by power mode transition from ON mode to OFF mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 20. "DNY_ON_FUNC,Indicates whether a denied state transition has occurred by power mode transition from ON mode to FUNC_RET mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 19. "DNY_FUNC_ON,Indicates whether a denied state transition has occurred by power mode transition from FUNC_RET mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 18. "DNY_ON_MEM,Indicates whether a denied state transition has occurred by power mode transition from ON mode to MEM_RET mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 17. "DNY_MEM_ON,Indicates whether a denied state transition has occurred by power mode transition from MEM_RET mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 16. "DNY_ON_L3CHG,Indicates whether a denied state transition has occurred by L3 cache partial power mode control" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
hexmask.long.word 0x00 0.--15. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x414++0x03
line.long 0x00 "PDENYINTRCL1_CLUSTER0,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 23.--31. 1. "Reserved_23,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 22. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 21. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 20. "INT_ON_FUNC,Issuing interrupt enable by DNY_ON_FUNC" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 19. "INT_FUNC_ON,Issuing interrupt enable by DNY_FUNC_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 18. "INT_ON_MEM,Issuing interrupt enable by DNY_ON_MEM" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 17. "INT_MEM_ON,Issuing interrupt enable by DNY_MEM_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 16. "INT_ON_L3CHG,Issuing interrupt enable by DNY_ON_L3CHG" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
hexmask.long.word 0x00 0.--15. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x418++0x03
line.long 0x00 "FSMSTSRCL1_CLUSTER0,This register is a 32-bit readable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "STATE_7_0,Indicate current state of Cortex-A55 cluster FSM"
group.long 0x41C++0x03
line.long 0x00 "G2GPRCL1_CLUSTER0,This register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "GPR0_31_0,This fields are allowed to write any values and they don't affect module operation"
group.long 0x420++0x03
line.long 0x00 "SAFECTRLCL1_CLUSTER0,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as H'0000 2"
newline
rbitfld.long 0x00 11. "Reserved_11,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 10. "A2_RTT_MRET,A2 RuntimeTEST using MEM_RET mode enable" "0: A2 RuntimeTEST using MEM_RET mode is disabled,1: A2 RuntimeTEST using MEM_RET mode is enabled"
newline
bitfld.long 0x00 9. "A2_RTT_POFF,A2 RuntimeTEST using Pseudo OFF mode enable" "0: A2 RuntimeTEST using Pseudo OFF mode is..,1: A2 RuntimeTEST using Pseudo OFF mode is enabled"
newline
hexmask.long.byte 0x00 2.--8. 1. "Reserved_2,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A55 clusters are booted" "0: RuntimeTEST is disabled before Cortex-A55,1: RuntimeTEST is enabled before Cortex-A55"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0x42C++0x03
line.long 0x00 "GCNTERRENCL1_CLUSTER0,This register is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 0. "GCNTERREN,Generic Counter error detection enable" "0: Error detection is disabled,1: Error detection is enabled"
group.long 0x430++0x03
line.long 0x00 "CA55BAR1_CLUSTER0,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 10.--31. 1. "BAR_39_18,Cortex-A55 Boot Address for AA32 mode"
newline
rbitfld.long 0x00 5.--9. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 4. "BAREN,BAR enables" "0,1"
newline
rbitfld.long 0x00 0.--3. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x438++0x03
line.long 0x00 "CA55BARP1_CLUSTER0,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 10.--31. 1. "BAR_39_18,Cortex-A55 Boot Address for AA32 mode"
newline
rbitfld.long 0x00 5.--9. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 4. "BAREN,BAR enables" "0,1"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "VLD,CA55BARP valid" "0: CA55BAR is used to define Cortex-A55's Boot,1: CA55BARP is used to define Cortex-A55's Boot"
group.long 0x440++0x03
line.long 0x00 "PWRCTRLCL1_CLUSTER1,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 22.--31. 1. "Reserved_22,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 21. "PCHMRETEN,MEM_RET mode transition enable by P-channel protocol" "0,1"
newline
bitfld.long 0x00 20. "PCHFRETEN,FUNC_RET mode transition enable by P-channel protocol" "0: Power mode transition to FUNC_RET mode is..,1: Power mode transition to FUNC_RET mode is.."
newline
rbitfld.long 0x00 18.--19. "Reserved_18,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 17. "PCHPDNEN,OFF mode transition enable by P-channel protocol" "0,1"
newline
bitfld.long 0x00 16. "PCHWUPEN,ON mode transition enable by P-channel protocol" "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled"
newline
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0x444++0x03
line.long 0x00 "L3CTRLCL1_CLUSTER1,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 19.--31. 1. "Reserved_19,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 16.--18. "L3STS_2_0,Indicates current L3 cache partial power down/up status" "?,1: 1/4 of L3 cache is powered on,2: 1/2 of L3 cache is powered on,3: 3/4 of L3 cache is powered on,4: All L3 cache is powered on,?..."
newline
rbitfld.long 0x00 10.--15. "Reserved_10,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 9. "L3DENY,Indicates whether L3 cache partial power down/up request is denied" "0: request is not denied,1: request is denied"
newline
bitfld.long 0x00 8. "L3ACCEPT,Indicates whether L3 cache partial power down/up request is accepted" "0: request is not accepted,1: request is accepted"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4. "L3REQ,L3 cache partial power down/up request" "0: L3 cache partial power down/up is not requested,1: L3 cache partial power down/up is requested"
newline
rbitfld.long 0x00 3. "Reserved_3,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0.--2. "L3CTRL_2_0,L3 cache partial power down/up control" "0: All L3 cache is power-off or Cluster's power,1: 1/4 of L3 cache is power-on,2: 1/2 of L3 cache is power-on,3: 3/4 of L3 cache is power-on,4: All L3 cache is power-on,?..."
group.long 0x44C++0x03
line.long 0x00 "FSMLOCKRCL1_CLUSTER1,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 16.--31. 1. "CNT_VALUE_15_0,Indicates count value for FSM deadlock error"
newline
rbitfld.long 0x00 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred" "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred"
newline
rbitfld.long 0x00 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred" "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred"
newline
rbitfld.long 0x00 13. "Reserved_13,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred" "0: FSM dead lock has not occurred,1: FSM dead lock has occurred"
newline
bitfld.long 0x00 11. "LOCK_EN,FSM deadlock error enable" "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled"
newline
bitfld.long 0x00 10. "PRTCL_EN,P-channel protocol error enable" "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled"
newline
bitfld.long 0x00 9. "CRPT_EN,P-channel corruption error enable" "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled"
newline
rbitfld.long 0x00 8. "Reserved_8,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 7. "PRTCL_EIJT,P-channel protocol error injection" "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active"
newline
bitfld.long 0x00 6. "CRPT_EIJT,P-channel corruption error injection" "0,1"
newline
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 4. "LOCK_EIJT,FSM deadlock error injection" "0,1"
newline
bitfld.long 0x00 3. "PRTCL_CLR,P-channel protocol error clear" "0,1"
newline
bitfld.long 0x00 2. "CRPT_CLR,P-channel corruption error clear" "0,1"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "LOCK_CLR,FSM deadlock error clear" "0,1"
group.long 0x450++0x03
line.long 0x00 "PDENYSTSRCL1_CLUSTER1,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 23.--31. 1. "Reserved_23,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 22. "DNY_OFF_ON,Indicates whether a denied state transition has occurred by power mode transition from OFF mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 21. "DNY_ON_OFF,Indicates whether a denied state transition has occurred by power mode transition from ON mode to OFF mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 20. "DNY_ON_FUNC,Indicates whether a denied state transition has occurred by power mode transition from ON mode to FUNC_RET mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 19. "DNY_FUNC_ON,Indicates whether a denied state transition has occurred by power mode transition from FUNC_RET mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 18. "DNY_ON_MEM,Indicates whether a denied state transition has occurred by power mode transition from ON mode to MEM_RET mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 17. "DNY_MEM_ON,Indicates whether a denied state transition has occurred by power mode transition from MEM_RET mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 16. "DNY_ON_L3CHG,Indicates whether a denied state transition has occurred by L3 cache partial power mode control" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
hexmask.long.word 0x00 0.--15. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x454++0x03
line.long 0x00 "PDENYINTRCL1_CLUSTER1,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 23.--31. 1. "Reserved_23,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 22. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 21. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 20. "INT_ON_FUNC,Issuing interrupt enable by DNY_ON_FUNC" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 19. "INT_FUNC_ON,Issuing interrupt enable by DNY_FUNC_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 18. "INT_ON_MEM,Issuing interrupt enable by DNY_ON_MEM" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 17. "INT_MEM_ON,Issuing interrupt enable by DNY_MEM_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 16. "INT_ON_L3CHG,Issuing interrupt enable by DNY_ON_L3CHG" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
hexmask.long.word 0x00 0.--15. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x458++0x03
line.long 0x00 "FSMSTSRCL1_CLUSTER1,This register is a 32-bit readable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "STATE_7_0,Indicate current state of Cortex-A55 cluster FSM"
group.long 0x45C++0x03
line.long 0x00 "G2GPRCL1_CLUSTER1,This register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "GPR0_31_0,This fields are allowed to write any values and they don't affect module operation"
group.long 0x460++0x03
line.long 0x00 "SAFECTRLCL1_CLUSTER1,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as H'0000 2"
newline
rbitfld.long 0x00 11. "Reserved_11,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 10. "A2_RTT_MRET,A2 RuntimeTEST using MEM_RET mode enable" "0: A2 RuntimeTEST using MEM_RET mode is disabled,1: A2 RuntimeTEST using MEM_RET mode is enabled"
newline
bitfld.long 0x00 9. "A2_RTT_POFF,A2 RuntimeTEST using Pseudo OFF mode enable" "0: A2 RuntimeTEST using Pseudo OFF mode is..,1: A2 RuntimeTEST using Pseudo OFF mode is enabled"
newline
hexmask.long.byte 0x00 2.--8. 1. "Reserved_2,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A55 clusters are booted" "0: RuntimeTEST is disabled before Cortex-A55,1: RuntimeTEST is enabled before Cortex-A55"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0x46C++0x03
line.long 0x00 "GCNTERRENCL1_CLUSTER1,This register is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 0. "GCNTERREN,Generic Counter error detection enable" "0: Error detection is disabled,1: Error detection is enabled"
group.long 0x470++0x03
line.long 0x00 "CA55BAR1_CLUSTER1,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 10.--31. 1. "BAR_39_18,Cortex-A55 Boot Address for AA32 mode"
newline
rbitfld.long 0x00 5.--9. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 4. "BAREN,BAR enables" "0,1"
newline
rbitfld.long 0x00 0.--3. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x478++0x03
line.long 0x00 "CA55BARP1_CLUSTER1,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 10.--31. 1. "BAR_39_18,Cortex-A55 Boot Address for AA32 mode"
newline
rbitfld.long 0x00 5.--9. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 4. "BAREN,BAR enables" "0,1"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "VLD,CA55BARP valid" "0: CA55BAR is used to define Cortex-A55's Boot,1: CA55BARP is used to define Cortex-A55's Boot"
group.long 0x480++0x03
line.long 0x00 "PWRCTRLCL1_CLUSTER2,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 22.--31. 1. "Reserved_22,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 21. "PCHMRETEN,MEM_RET mode transition enable by P-channel protocol" "0,1"
newline
bitfld.long 0x00 20. "PCHFRETEN,FUNC_RET mode transition enable by P-channel protocol" "0: Power mode transition to FUNC_RET mode is..,1: Power mode transition to FUNC_RET mode is.."
newline
rbitfld.long 0x00 18.--19. "Reserved_18,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 17. "PCHPDNEN,OFF mode transition enable by P-channel protocol" "0,1"
newline
bitfld.long 0x00 16. "PCHWUPEN,ON mode transition enable by P-channel protocol" "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled"
newline
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0x484++0x03
line.long 0x00 "L3CTRLCL1_CLUSTER2,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 19.--31. 1. "Reserved_19,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 16.--18. "L3STS_2_0,Indicates current L3 cache partial power down/up status" "?,1: 1/4 of L3 cache is powered on,2: 1/2 of L3 cache is powered on,3: 3/4 of L3 cache is powered on,4: All L3 cache is powered on,?..."
newline
rbitfld.long 0x00 10.--15. "Reserved_10,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 9. "L3DENY,Indicates whether L3 cache partial power down/up request is denied" "0: request is not denied,1: request is denied"
newline
bitfld.long 0x00 8. "L3ACCEPT,Indicates whether L3 cache partial power down/up request is accepted" "0: request is not accepted,1: request is accepted"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4. "L3REQ,L3 cache partial power down/up request" "0: L3 cache partial power down/up is not requested,1: L3 cache partial power down/up is requested"
newline
rbitfld.long 0x00 3. "Reserved_3,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0.--2. "L3CTRL_2_0,L3 cache partial power down/up control" "0: All L3 cache is power-off or Cluster's power,1: 1/4 of L3 cache is power-on,2: 1/2 of L3 cache is power-on,3: 3/4 of L3 cache is power-on,4: All L3 cache is power-on,?..."
group.long 0x48C++0x03
line.long 0x00 "FSMLOCKRCL1_CLUSTER2,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 16.--31. 1. "CNT_VALUE_15_0,Indicates count value for FSM deadlock error"
newline
rbitfld.long 0x00 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred" "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred"
newline
rbitfld.long 0x00 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred" "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred"
newline
rbitfld.long 0x00 13. "Reserved_13,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred" "0: FSM dead lock has not occurred,1: FSM dead lock has occurred"
newline
bitfld.long 0x00 11. "LOCK_EN,FSM deadlock error enable" "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled"
newline
bitfld.long 0x00 10. "PRTCL_EN,P-channel protocol error enable" "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled"
newline
bitfld.long 0x00 9. "CRPT_EN,P-channel corruption error enable" "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled"
newline
rbitfld.long 0x00 8. "Reserved_8,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 7. "PRTCL_EIJT,P-channel protocol error injection" "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active"
newline
bitfld.long 0x00 6. "CRPT_EIJT,P-channel corruption error injection" "0,1"
newline
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 4. "LOCK_EIJT,FSM deadlock error injection" "0,1"
newline
bitfld.long 0x00 3. "PRTCL_CLR,P-channel protocol error clear" "0,1"
newline
bitfld.long 0x00 2. "CRPT_CLR,P-channel corruption error clear" "0,1"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "LOCK_CLR,FSM deadlock error clear" "0,1"
group.long 0x490++0x03
line.long 0x00 "PDENYSTSRCL1_CLUSTER2,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 23.--31. 1. "Reserved_23,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 22. "DNY_OFF_ON,Indicates whether a denied state transition has occurred by power mode transition from OFF mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 21. "DNY_ON_OFF,Indicates whether a denied state transition has occurred by power mode transition from ON mode to OFF mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 20. "DNY_ON_FUNC,Indicates whether a denied state transition has occurred by power mode transition from ON mode to FUNC_RET mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 19. "DNY_FUNC_ON,Indicates whether a denied state transition has occurred by power mode transition from FUNC_RET mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 18. "DNY_ON_MEM,Indicates whether a denied state transition has occurred by power mode transition from ON mode to MEM_RET mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 17. "DNY_MEM_ON,Indicates whether a denied state transition has occurred by power mode transition from MEM_RET mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 16. "DNY_ON_L3CHG,Indicates whether a denied state transition has occurred by L3 cache partial power mode control" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
hexmask.long.word 0x00 0.--15. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x494++0x03
line.long 0x00 "PDENYINTRCL1_CLUSTER2,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 23.--31. 1. "Reserved_23,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 22. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 21. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 20. "INT_ON_FUNC,Issuing interrupt enable by DNY_ON_FUNC" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 19. "INT_FUNC_ON,Issuing interrupt enable by DNY_FUNC_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 18. "INT_ON_MEM,Issuing interrupt enable by DNY_ON_MEM" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 17. "INT_MEM_ON,Issuing interrupt enable by DNY_MEM_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 16. "INT_ON_L3CHG,Issuing interrupt enable by DNY_ON_L3CHG" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
hexmask.long.word 0x00 0.--15. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x498++0x03
line.long 0x00 "FSMSTSRCL1_CLUSTER2,This register is a 32-bit readable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "STATE_7_0,Indicate current state of Cortex-A55 cluster FSM"
group.long 0x49C++0x03
line.long 0x00 "G2GPRCL1_CLUSTER2,This register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "GPR0_31_0,This fields are allowed to write any values and they don't affect module operation"
group.long 0x4A0++0x03
line.long 0x00 "SAFECTRLCL1_CLUSTER2,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as H'0000 2"
newline
rbitfld.long 0x00 11. "Reserved_11,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 10. "A2_RTT_MRET,A2 RuntimeTEST using MEM_RET mode enable" "0: A2 RuntimeTEST using MEM_RET mode is disabled,1: A2 RuntimeTEST using MEM_RET mode is enabled"
newline
bitfld.long 0x00 9. "A2_RTT_POFF,A2 RuntimeTEST using Pseudo OFF mode enable" "0: A2 RuntimeTEST using Pseudo OFF mode is..,1: A2 RuntimeTEST using Pseudo OFF mode is enabled"
newline
hexmask.long.byte 0x00 2.--8. 1. "Reserved_2,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A55 clusters are booted" "0: RuntimeTEST is disabled before Cortex-A55,1: RuntimeTEST is enabled before Cortex-A55"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0x4AC++0x03
line.long 0x00 "GCNTERRENCL1_CLUSTER2,This register is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 0. "GCNTERREN,Generic Counter error detection enable" "0: Error detection is disabled,1: Error detection is enabled"
group.long 0x4B0++0x03
line.long 0x00 "CA55BAR1_CLUSTER2,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 10.--31. 1. "BAR_39_18,Cortex-A55 Boot Address for AA32 mode"
newline
rbitfld.long 0x00 5.--9. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 4. "BAREN,BAR enables" "0,1"
newline
rbitfld.long 0x00 0.--3. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4B8++0x03
line.long 0x00 "CA55BARP1_CLUSTER2,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 10.--31. 1. "BAR_39_18,Cortex-A55 Boot Address for AA32 mode"
newline
rbitfld.long 0x00 5.--9. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 4. "BAREN,BAR enables" "0,1"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "VLD,CA55BARP valid" "0: CA55BAR is used to define Cortex-A55's Boot,1: CA55BARP is used to define Cortex-A55's Boot"
group.long 0x4C0++0x03
line.long 0x00 "PWRCTRLCL1_CLUSTER3,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 22.--31. 1. "Reserved_22,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 21. "PCHMRETEN,MEM_RET mode transition enable by P-channel protocol" "0,1"
newline
bitfld.long 0x00 20. "PCHFRETEN,FUNC_RET mode transition enable by P-channel protocol" "0: Power mode transition to FUNC_RET mode is..,1: Power mode transition to FUNC_RET mode is.."
newline
rbitfld.long 0x00 18.--19. "Reserved_18,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 17. "PCHPDNEN,OFF mode transition enable by P-channel protocol" "0,1"
newline
bitfld.long 0x00 16. "PCHWUPEN,ON mode transition enable by P-channel protocol" "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled"
newline
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0x4C4++0x03
line.long 0x00 "L3CTRLCL1_CLUSTER3,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 19.--31. 1. "Reserved_19,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 16.--18. "L3STS_2_0,Indicates current L3 cache partial power down/up status" "?,1: 1/4 of L3 cache is powered on,2: 1/2 of L3 cache is powered on,3: 3/4 of L3 cache is powered on,4: All L3 cache is powered on,?..."
newline
rbitfld.long 0x00 10.--15. "Reserved_10,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 9. "L3DENY,Indicates whether L3 cache partial power down/up request is denied" "0: request is not denied,1: request is denied"
newline
bitfld.long 0x00 8. "L3ACCEPT,Indicates whether L3 cache partial power down/up request is accepted" "0: request is not accepted,1: request is accepted"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4. "L3REQ,L3 cache partial power down/up request" "0: L3 cache partial power down/up is not requested,1: L3 cache partial power down/up is requested"
newline
rbitfld.long 0x00 3. "Reserved_3,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0.--2. "L3CTRL_2_0,L3 cache partial power down/up control" "0: All L3 cache is power-off or Cluster's power,1: 1/4 of L3 cache is power-on,2: 1/2 of L3 cache is power-on,3: 3/4 of L3 cache is power-on,4: All L3 cache is power-on,?..."
group.long 0x4CC++0x03
line.long 0x00 "FSMLOCKRCL1_CLUSTER3,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 16.--31. 1. "CNT_VALUE_15_0,Indicates count value for FSM deadlock error"
newline
rbitfld.long 0x00 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred" "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred"
newline
rbitfld.long 0x00 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred" "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred"
newline
rbitfld.long 0x00 13. "Reserved_13,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred" "0: FSM dead lock has not occurred,1: FSM dead lock has occurred"
newline
bitfld.long 0x00 11. "LOCK_EN,FSM deadlock error enable" "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled"
newline
bitfld.long 0x00 10. "PRTCL_EN,P-channel protocol error enable" "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled"
newline
bitfld.long 0x00 9. "CRPT_EN,P-channel corruption error enable" "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled"
newline
rbitfld.long 0x00 8. "Reserved_8,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 7. "PRTCL_EIJT,P-channel protocol error injection" "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active"
newline
bitfld.long 0x00 6. "CRPT_EIJT,P-channel corruption error injection" "0,1"
newline
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 4. "LOCK_EIJT,FSM deadlock error injection" "0,1"
newline
bitfld.long 0x00 3. "PRTCL_CLR,P-channel protocol error clear" "0,1"
newline
bitfld.long 0x00 2. "CRPT_CLR,P-channel corruption error clear" "0,1"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "LOCK_CLR,FSM deadlock error clear" "0,1"
group.long 0x4D0++0x03
line.long 0x00 "PDENYSTSRCL1_CLUSTER3,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 23.--31. 1. "Reserved_23,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 22. "DNY_OFF_ON,Indicates whether a denied state transition has occurred by power mode transition from OFF mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 21. "DNY_ON_OFF,Indicates whether a denied state transition has occurred by power mode transition from ON mode to OFF mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 20. "DNY_ON_FUNC,Indicates whether a denied state transition has occurred by power mode transition from ON mode to FUNC_RET mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 19. "DNY_FUNC_ON,Indicates whether a denied state transition has occurred by power mode transition from FUNC_RET mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 18. "DNY_ON_MEM,Indicates whether a denied state transition has occurred by power mode transition from ON mode to MEM_RET mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 17. "DNY_MEM_ON,Indicates whether a denied state transition has occurred by power mode transition from MEM_RET mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 16. "DNY_ON_L3CHG,Indicates whether a denied state transition has occurred by L3 cache partial power mode control" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
hexmask.long.word 0x00 0.--15. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x4D4++0x03
line.long 0x00 "PDENYINTRCL1_CLUSTER3,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 23.--31. 1. "Reserved_23,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 22. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 21. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 20. "INT_ON_FUNC,Issuing interrupt enable by DNY_ON_FUNC" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 19. "INT_FUNC_ON,Issuing interrupt enable by DNY_FUNC_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 18. "INT_ON_MEM,Issuing interrupt enable by DNY_ON_MEM" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 17. "INT_MEM_ON,Issuing interrupt enable by DNY_MEM_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 16. "INT_ON_L3CHG,Issuing interrupt enable by DNY_ON_L3CHG" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
hexmask.long.word 0x00 0.--15. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x4D8++0x03
line.long 0x00 "FSMSTSRCL1_CLUSTER3,This register is a 32-bit readable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "STATE_7_0,Indicate current state of Cortex-A55 cluster FSM"
group.long 0x4DC++0x03
line.long 0x00 "G2GPRCL1_CLUSTER3,This register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "GPR0_31_0,This fields are allowed to write any values and they don't affect module operation"
group.long 0x4E0++0x03
line.long 0x00 "SAFECTRLCL1_CLUSTER3,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as H'0000 2"
newline
rbitfld.long 0x00 11. "Reserved_11,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 10. "A2_RTT_MRET,A2 RuntimeTEST using MEM_RET mode enable" "0: A2 RuntimeTEST using MEM_RET mode is disabled,1: A2 RuntimeTEST using MEM_RET mode is enabled"
newline
bitfld.long 0x00 9. "A2_RTT_POFF,A2 RuntimeTEST using Pseudo OFF mode enable" "0: A2 RuntimeTEST using Pseudo OFF mode is..,1: A2 RuntimeTEST using Pseudo OFF mode is enabled"
newline
hexmask.long.byte 0x00 2.--8. 1. "Reserved_2,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A55 clusters are booted" "0: RuntimeTEST is disabled before Cortex-A55,1: RuntimeTEST is enabled before Cortex-A55"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0x4EC++0x03
line.long 0x00 "GCNTERRENCL1_CLUSTER3,This register is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 0. "GCNTERREN,Generic Counter error detection enable" "0: Error detection is disabled,1: Error detection is enabled"
group.long 0x4F0++0x03
line.long 0x00 "CA55BAR1_CLUSTER3,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 10.--31. 1. "BAR_39_18,Cortex-A55 Boot Address for AA32 mode"
newline
rbitfld.long 0x00 5.--9. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 4. "BAREN,BAR enables" "0,1"
newline
rbitfld.long 0x00 0.--3. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4F8++0x03
line.long 0x00 "CA55BARP1_CLUSTER3,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 10.--31. 1. "BAR_39_18,Cortex-A55 Boot Address for AA32 mode"
newline
rbitfld.long 0x00 5.--9. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 4. "BAREN,BAR enables" "0,1"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "VLD,CA55BARP valid" "0: CA55BAR is used to define Cortex-A55's Boot,1: CA55BARP is used to define Cortex-A55's Boot"
group.long 0x800++0x03
line.long 0x00 "PWRCTRLC1_CORE0,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 19.--31. 1. "Reserved_19,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol" "0: Power mode transition to OFF_EMU mode is..,1: Power mode transition to OFF_EMU mode is.."
newline
bitfld.long 0x00 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled"
newline
bitfld.long 0x00 16. "PCHWUPEN,ON mode transition enable by P-channel protocol" "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled"
newline
hexmask.long.word 0x00 6.--15. 1. "Reserved_6,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 5. "DWUP_EN,This bit enables wakeup request from Debugger" "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled"
newline
bitfld.long 0x00 4. "IWUP_EN,This bit enables wakeup request from INTC-AP" "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "WUP_REQ,Wake up request" "0: Power on is not requested,1: Power on is requested"
group.long 0x80C++0x03
line.long 0x00 "FSMLOCKRC1_CORE0,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 16.--31. 1. "CNT_VALUE_15_0,Indicates count value for FSM deadlock error"
newline
rbitfld.long 0x00 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred" "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred"
newline
rbitfld.long 0x00 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred" "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred"
newline
rbitfld.long 0x00 13. "Reserved_13,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred" "0: FSM dead lock has not occurred,1: FSM dead lock has occurred"
newline
bitfld.long 0x00 11. "LOCK_EN,FSM deadlock error enable" "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled"
newline
bitfld.long 0x00 10. "PRTCL_EN,P-channel protocol error enable" "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled"
newline
bitfld.long 0x00 9. "CRPT_EN,P-channel corruption error enable" "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled"
newline
rbitfld.long 0x00 8. "Reserved_8,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 7. "PRTCL_EIJT,P-channel protocol error injection" "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active"
newline
bitfld.long 0x00 6. "CRPT_EIJT,P-channel corruption error injection" "0,1"
newline
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 4. "LOCK_EIJT,FSM deadlock error injection" "0,1"
newline
bitfld.long 0x00 3. "PRTCL_CLR,P-channel protocol error clear" "0,1"
newline
bitfld.long 0x00 2. "CRPT_CLR,P-channel corruption error clear" "0,1"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "LOCK_CLR,FSM deadlock error clear" "0,1"
group.long 0x810++0x03
line.long 0x00 "PDENYSTSRC1_CORE0,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
rbitfld.long 0x00 4.--5. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0x814++0x03
line.long 0x00 "PDENYINTRC1_CORE0,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
rbitfld.long 0x00 4.--5. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0x818++0x03
line.long 0x00 "FSMSTSRC1_CORE0,This register is a 32-bit readable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "STATE_7_0,Indicate current state of A3 FSM"
group.long 0x81C++0x03
line.long 0x00 "G2GPRC1_CORE0,This register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "GPR0_31_0,This fields are allowed to write any values and they don't affect module operation"
group.long 0x820++0x03
line.long 0x00 "SAFECTRLC1_CORE0,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are always read as H'0000 0"
newline
bitfld.long 0x00 13. "DBGEN_PPDN,When Cortex-A55 is in debug mode Cortex-A55 core is goes to OFF_EMU mode instead of OFF mode" "0: Cortex-A55 goes to OFF mode,1: Cortex-A55 goes to OFF_EMU mode"
newline
hexmask.long.byte 0x00 5.--12. 1. "Reserved_5,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4. "A1_RTT,A1 RuntimeTEST enable" "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A55 cores are booted" "0: RuntimeTEST is disabled before Cortex-A55 cores,1: RuntimeTEST is enabled before Cortex-A55 cores"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0x830++0x03
line.long 0x00 "RVBARLC1_CORE0,This register is a 32-bit readable/writable register"
hexmask.long 0x00 2.--31. 1. "RVBAR_31_2,These bits indicate RVBARADDR[31:2]"
newline
rbitfld.long 0x00 0.--1. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3"
group.long 0x834++0x03
line.long 0x00 "RVBARHC1_CORE0,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--11. 1. "RVBAR_43_32,These bits indicate RVBARADDR[43:32]"
group.long 0x838++0x03
line.long 0x00 "RVBARPLC1_CORE0,This register is a 32-bit readable/writable register"
hexmask.long 0x00 2.--31. 1. "RVBARP_31_2,These bits indicate RVBARADDR[31:2]"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "VLD,RVBARP valid" "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR"
group.long 0x83C++0x03
line.long 0x00 "RVBARPHC1_CORE0,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--11. 1. "RVBARP_43_32,These bits indicate RVBARADDR[43:32]"
group.long 0x840++0x03
line.long 0x00 "PWRCTRLC1_CORE1,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 19.--31. 1. "Reserved_19,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol" "0: Power mode transition to OFF_EMU mode is..,1: Power mode transition to OFF_EMU mode is.."
newline
bitfld.long 0x00 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled"
newline
bitfld.long 0x00 16. "PCHWUPEN,ON mode transition enable by P-channel protocol" "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled"
newline
hexmask.long.word 0x00 6.--15. 1. "Reserved_6,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 5. "DWUP_EN,This bit enables wakeup request from Debugger" "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled"
newline
bitfld.long 0x00 4. "IWUP_EN,This bit enables wakeup request from INTC-AP" "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "WUP_REQ,Wake up request" "0: Power on is not requested,1: Power on is requested"
group.long 0x84C++0x03
line.long 0x00 "FSMLOCKRC1_CORE1,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 16.--31. 1. "CNT_VALUE_15_0,Indicates count value for FSM deadlock error"
newline
rbitfld.long 0x00 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred" "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred"
newline
rbitfld.long 0x00 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred" "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred"
newline
rbitfld.long 0x00 13. "Reserved_13,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred" "0: FSM dead lock has not occurred,1: FSM dead lock has occurred"
newline
bitfld.long 0x00 11. "LOCK_EN,FSM deadlock error enable" "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled"
newline
bitfld.long 0x00 10. "PRTCL_EN,P-channel protocol error enable" "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled"
newline
bitfld.long 0x00 9. "CRPT_EN,P-channel corruption error enable" "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled"
newline
rbitfld.long 0x00 8. "Reserved_8,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 7. "PRTCL_EIJT,P-channel protocol error injection" "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active"
newline
bitfld.long 0x00 6. "CRPT_EIJT,P-channel corruption error injection" "0,1"
newline
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 4. "LOCK_EIJT,FSM deadlock error injection" "0,1"
newline
bitfld.long 0x00 3. "PRTCL_CLR,P-channel protocol error clear" "0,1"
newline
bitfld.long 0x00 2. "CRPT_CLR,P-channel corruption error clear" "0,1"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "LOCK_CLR,FSM deadlock error clear" "0,1"
group.long 0x850++0x03
line.long 0x00 "PDENYSTSRC1_CORE1,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
rbitfld.long 0x00 4.--5. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0x854++0x03
line.long 0x00 "PDENYINTRC1_CORE1,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
rbitfld.long 0x00 4.--5. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0x858++0x03
line.long 0x00 "FSMSTSRC1_CORE1,This register is a 32-bit readable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "STATE_7_0,Indicate current state of A3 FSM"
group.long 0x85C++0x03
line.long 0x00 "G2GPRC1_CORE1,This register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "GPR0_31_0,This fields are allowed to write any values and they don't affect module operation"
group.long 0x860++0x03
line.long 0x00 "SAFECTRLC1_CORE1,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are always read as H'0000 0"
newline
bitfld.long 0x00 13. "DBGEN_PPDN,When Cortex-A55 is in debug mode Cortex-A55 core is goes to OFF_EMU mode instead of OFF mode" "0: Cortex-A55 goes to OFF mode,1: Cortex-A55 goes to OFF_EMU mode"
newline
hexmask.long.byte 0x00 5.--12. 1. "Reserved_5,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4. "A1_RTT,A1 RuntimeTEST enable" "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A55 cores are booted" "0: RuntimeTEST is disabled before Cortex-A55 cores,1: RuntimeTEST is enabled before Cortex-A55 cores"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0x870++0x03
line.long 0x00 "RVBARLC1_CORE1,This register is a 32-bit readable/writable register"
hexmask.long 0x00 2.--31. 1. "RVBAR_31_2,These bits indicate RVBARADDR[31:2]"
newline
rbitfld.long 0x00 0.--1. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3"
group.long 0x874++0x03
line.long 0x00 "RVBARHC1_CORE1,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--11. 1. "RVBAR_43_32,These bits indicate RVBARADDR[43:32]"
group.long 0x878++0x03
line.long 0x00 "RVBARPLC1_CORE1,This register is a 32-bit readable/writable register"
hexmask.long 0x00 2.--31. 1. "RVBARP_31_2,These bits indicate RVBARADDR[31:2]"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "VLD,RVBARP valid" "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR"
group.long 0x87C++0x03
line.long 0x00 "RVBARPHC1_CORE1,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--11. 1. "RVBARP_43_32,These bits indicate RVBARADDR[43:32]"
group.long 0xA00++0x03
line.long 0x00 "PWRCTRLC1_CORE2,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 19.--31. 1. "Reserved_19,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol" "0: Power mode transition to OFF_EMU mode is..,1: Power mode transition to OFF_EMU mode is.."
newline
bitfld.long 0x00 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled"
newline
bitfld.long 0x00 16. "PCHWUPEN,ON mode transition enable by P-channel protocol" "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled"
newline
hexmask.long.word 0x00 6.--15. 1. "Reserved_6,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 5. "DWUP_EN,This bit enables wakeup request from Debugger" "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled"
newline
bitfld.long 0x00 4. "IWUP_EN,This bit enables wakeup request from INTC-AP" "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "WUP_REQ,Wake up request" "0: Power on is not requested,1: Power on is requested"
group.long 0xA0C++0x03
line.long 0x00 "FSMLOCKRC1_CORE2,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 16.--31. 1. "CNT_VALUE_15_0,Indicates count value for FSM deadlock error"
newline
rbitfld.long 0x00 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred" "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred"
newline
rbitfld.long 0x00 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred" "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred"
newline
rbitfld.long 0x00 13. "Reserved_13,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred" "0: FSM dead lock has not occurred,1: FSM dead lock has occurred"
newline
bitfld.long 0x00 11. "LOCK_EN,FSM deadlock error enable" "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled"
newline
bitfld.long 0x00 10. "PRTCL_EN,P-channel protocol error enable" "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled"
newline
bitfld.long 0x00 9. "CRPT_EN,P-channel corruption error enable" "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled"
newline
rbitfld.long 0x00 8. "Reserved_8,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 7. "PRTCL_EIJT,P-channel protocol error injection" "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active"
newline
bitfld.long 0x00 6. "CRPT_EIJT,P-channel corruption error injection" "0,1"
newline
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 4. "LOCK_EIJT,FSM deadlock error injection" "0,1"
newline
bitfld.long 0x00 3. "PRTCL_CLR,P-channel protocol error clear" "0,1"
newline
bitfld.long 0x00 2. "CRPT_CLR,P-channel corruption error clear" "0,1"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "LOCK_CLR,FSM deadlock error clear" "0,1"
group.long 0xA10++0x03
line.long 0x00 "PDENYSTSRC1_CORE2,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
rbitfld.long 0x00 4.--5. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0xA14++0x03
line.long 0x00 "PDENYINTRC1_CORE2,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
rbitfld.long 0x00 4.--5. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0xA18++0x03
line.long 0x00 "FSMSTSRC1_CORE2,This register is a 32-bit readable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "STATE_7_0,Indicate current state of A3 FSM"
group.long 0xA1C++0x03
line.long 0x00 "G2GPRC1_CORE2,This register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "GPR0_31_0,This fields are allowed to write any values and they don't affect module operation"
group.long 0xA20++0x03
line.long 0x00 "SAFECTRLC1_CORE2,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are always read as H'0000 0"
newline
bitfld.long 0x00 13. "DBGEN_PPDN,When Cortex-A55 is in debug mode Cortex-A55 core is goes to OFF_EMU mode instead of OFF mode" "0: Cortex-A55 goes to OFF mode,1: Cortex-A55 goes to OFF_EMU mode"
newline
hexmask.long.byte 0x00 5.--12. 1. "Reserved_5,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4. "A1_RTT,A1 RuntimeTEST enable" "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A55 cores are booted" "0: RuntimeTEST is disabled before Cortex-A55 cores,1: RuntimeTEST is enabled before Cortex-A55 cores"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0xA30++0x03
line.long 0x00 "RVBARLC1_CORE2,This register is a 32-bit readable/writable register"
hexmask.long 0x00 2.--31. 1. "RVBAR_31_2,These bits indicate RVBARADDR[31:2]"
newline
rbitfld.long 0x00 0.--1. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3"
group.long 0xA34++0x03
line.long 0x00 "RVBARHC1_CORE2,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--11. 1. "RVBAR_43_32,These bits indicate RVBARADDR[43:32]"
group.long 0xA38++0x03
line.long 0x00 "RVBARPLC1_CORE2,This register is a 32-bit readable/writable register"
hexmask.long 0x00 2.--31. 1. "RVBARP_31_2,These bits indicate RVBARADDR[31:2]"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "VLD,RVBARP valid" "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR"
group.long 0xA3C++0x03
line.long 0x00 "RVBARPHC1_CORE2,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--11. 1. "RVBARP_43_32,These bits indicate RVBARADDR[43:32]"
group.long 0xA40++0x03
line.long 0x00 "PWRCTRLC1_CORE3,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 19.--31. 1. "Reserved_19,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol" "0: Power mode transition to OFF_EMU mode is..,1: Power mode transition to OFF_EMU mode is.."
newline
bitfld.long 0x00 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled"
newline
bitfld.long 0x00 16. "PCHWUPEN,ON mode transition enable by P-channel protocol" "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled"
newline
hexmask.long.word 0x00 6.--15. 1. "Reserved_6,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 5. "DWUP_EN,This bit enables wakeup request from Debugger" "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled"
newline
bitfld.long 0x00 4. "IWUP_EN,This bit enables wakeup request from INTC-AP" "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "WUP_REQ,Wake up request" "0: Power on is not requested,1: Power on is requested"
group.long 0xA4C++0x03
line.long 0x00 "FSMLOCKRC1_CORE3,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 16.--31. 1. "CNT_VALUE_15_0,Indicates count value for FSM deadlock error"
newline
rbitfld.long 0x00 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred" "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred"
newline
rbitfld.long 0x00 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred" "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred"
newline
rbitfld.long 0x00 13. "Reserved_13,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred" "0: FSM dead lock has not occurred,1: FSM dead lock has occurred"
newline
bitfld.long 0x00 11. "LOCK_EN,FSM deadlock error enable" "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled"
newline
bitfld.long 0x00 10. "PRTCL_EN,P-channel protocol error enable" "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled"
newline
bitfld.long 0x00 9. "CRPT_EN,P-channel corruption error enable" "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled"
newline
rbitfld.long 0x00 8. "Reserved_8,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 7. "PRTCL_EIJT,P-channel protocol error injection" "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active"
newline
bitfld.long 0x00 6. "CRPT_EIJT,P-channel corruption error injection" "0,1"
newline
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 4. "LOCK_EIJT,FSM deadlock error injection" "0,1"
newline
bitfld.long 0x00 3. "PRTCL_CLR,P-channel protocol error clear" "0,1"
newline
bitfld.long 0x00 2. "CRPT_CLR,P-channel corruption error clear" "0,1"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "LOCK_CLR,FSM deadlock error clear" "0,1"
group.long 0xA50++0x03
line.long 0x00 "PDENYSTSRC1_CORE3,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
rbitfld.long 0x00 4.--5. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0xA54++0x03
line.long 0x00 "PDENYINTRC1_CORE3,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
rbitfld.long 0x00 4.--5. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0xA58++0x03
line.long 0x00 "FSMSTSRC1_CORE3,This register is a 32-bit readable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "STATE_7_0,Indicate current state of A3 FSM"
group.long 0xA5C++0x03
line.long 0x00 "G2GPRC1_CORE3,This register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "GPR0_31_0,This fields are allowed to write any values and they don't affect module operation"
group.long 0xA60++0x03
line.long 0x00 "SAFECTRLC1_CORE3,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are always read as H'0000 0"
newline
bitfld.long 0x00 13. "DBGEN_PPDN,When Cortex-A55 is in debug mode Cortex-A55 core is goes to OFF_EMU mode instead of OFF mode" "0: Cortex-A55 goes to OFF mode,1: Cortex-A55 goes to OFF_EMU mode"
newline
hexmask.long.byte 0x00 5.--12. 1. "Reserved_5,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4. "A1_RTT,A1 RuntimeTEST enable" "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A55 cores are booted" "0: RuntimeTEST is disabled before Cortex-A55 cores,1: RuntimeTEST is enabled before Cortex-A55 cores"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0xA70++0x03
line.long 0x00 "RVBARLC1_CORE3,This register is a 32-bit readable/writable register"
hexmask.long 0x00 2.--31. 1. "RVBAR_31_2,These bits indicate RVBARADDR[31:2]"
newline
rbitfld.long 0x00 0.--1. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3"
group.long 0xA74++0x03
line.long 0x00 "RVBARHC1_CORE3,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--11. 1. "RVBAR_43_32,These bits indicate RVBARADDR[43:32]"
group.long 0xA78++0x03
line.long 0x00 "RVBARPLC1_CORE3,This register is a 32-bit readable/writable register"
hexmask.long 0x00 2.--31. 1. "RVBARP_31_2,These bits indicate RVBARADDR[31:2]"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "VLD,RVBARP valid" "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR"
group.long 0xA7C++0x03
line.long 0x00 "RVBARPHC1_CORE3,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--11. 1. "RVBARP_43_32,These bits indicate RVBARADDR[43:32]"
group.long 0xC00++0x03
line.long 0x00 "PWRCTRLC1_CORE4,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 19.--31. 1. "Reserved_19,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol" "0: Power mode transition to OFF_EMU mode is..,1: Power mode transition to OFF_EMU mode is.."
newline
bitfld.long 0x00 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled"
newline
bitfld.long 0x00 16. "PCHWUPEN,ON mode transition enable by P-channel protocol" "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled"
newline
hexmask.long.word 0x00 6.--15. 1. "Reserved_6,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 5. "DWUP_EN,This bit enables wakeup request from Debugger" "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled"
newline
bitfld.long 0x00 4. "IWUP_EN,This bit enables wakeup request from INTC-AP" "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "WUP_REQ,Wake up request" "0: Power on is not requested,1: Power on is requested"
group.long 0xC0C++0x03
line.long 0x00 "FSMLOCKRC1_CORE4,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 16.--31. 1. "CNT_VALUE_15_0,Indicates count value for FSM deadlock error"
newline
rbitfld.long 0x00 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred" "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred"
newline
rbitfld.long 0x00 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred" "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred"
newline
rbitfld.long 0x00 13. "Reserved_13,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred" "0: FSM dead lock has not occurred,1: FSM dead lock has occurred"
newline
bitfld.long 0x00 11. "LOCK_EN,FSM deadlock error enable" "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled"
newline
bitfld.long 0x00 10. "PRTCL_EN,P-channel protocol error enable" "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled"
newline
bitfld.long 0x00 9. "CRPT_EN,P-channel corruption error enable" "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled"
newline
rbitfld.long 0x00 8. "Reserved_8,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 7. "PRTCL_EIJT,P-channel protocol error injection" "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active"
newline
bitfld.long 0x00 6. "CRPT_EIJT,P-channel corruption error injection" "0,1"
newline
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 4. "LOCK_EIJT,FSM deadlock error injection" "0,1"
newline
bitfld.long 0x00 3. "PRTCL_CLR,P-channel protocol error clear" "0,1"
newline
bitfld.long 0x00 2. "CRPT_CLR,P-channel corruption error clear" "0,1"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "LOCK_CLR,FSM deadlock error clear" "0,1"
group.long 0xC10++0x03
line.long 0x00 "PDENYSTSRC1_CORE4,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
rbitfld.long 0x00 4.--5. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0xC14++0x03
line.long 0x00 "PDENYINTRC1_CORE4,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
rbitfld.long 0x00 4.--5. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0xC18++0x03
line.long 0x00 "FSMSTSRC1_CORE4,This register is a 32-bit readable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "STATE_7_0,Indicate current state of A3 FSM"
group.long 0xC1C++0x03
line.long 0x00 "G2GPRC1_CORE4,This register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "GPR0_31_0,This fields are allowed to write any values and they don't affect module operation"
group.long 0xC20++0x03
line.long 0x00 "SAFECTRLC1_CORE4,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are always read as H'0000 0"
newline
bitfld.long 0x00 13. "DBGEN_PPDN,When Cortex-A55 is in debug mode Cortex-A55 core is goes to OFF_EMU mode instead of OFF mode" "0: Cortex-A55 goes to OFF mode,1: Cortex-A55 goes to OFF_EMU mode"
newline
hexmask.long.byte 0x00 5.--12. 1. "Reserved_5,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4. "A1_RTT,A1 RuntimeTEST enable" "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A55 cores are booted" "0: RuntimeTEST is disabled before Cortex-A55 cores,1: RuntimeTEST is enabled before Cortex-A55 cores"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0xC30++0x03
line.long 0x00 "RVBARLC1_CORE4,This register is a 32-bit readable/writable register"
hexmask.long 0x00 2.--31. 1. "RVBAR_31_2,These bits indicate RVBARADDR[31:2]"
newline
rbitfld.long 0x00 0.--1. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3"
group.long 0xC34++0x03
line.long 0x00 "RVBARHC1_CORE4,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--11. 1. "RVBAR_43_32,These bits indicate RVBARADDR[43:32]"
group.long 0xC38++0x03
line.long 0x00 "RVBARPLC1_CORE4,This register is a 32-bit readable/writable register"
hexmask.long 0x00 2.--31. 1. "RVBARP_31_2,These bits indicate RVBARADDR[31:2]"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "VLD,RVBARP valid" "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR"
group.long 0xC3C++0x03
line.long 0x00 "RVBARPHC1_CORE4,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--11. 1. "RVBARP_43_32,These bits indicate RVBARADDR[43:32]"
group.long 0xC40++0x03
line.long 0x00 "PWRCTRLC1_CORE5,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 19.--31. 1. "Reserved_19,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol" "0: Power mode transition to OFF_EMU mode is..,1: Power mode transition to OFF_EMU mode is.."
newline
bitfld.long 0x00 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled"
newline
bitfld.long 0x00 16. "PCHWUPEN,ON mode transition enable by P-channel protocol" "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled"
newline
hexmask.long.word 0x00 6.--15. 1. "Reserved_6,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 5. "DWUP_EN,This bit enables wakeup request from Debugger" "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled"
newline
bitfld.long 0x00 4. "IWUP_EN,This bit enables wakeup request from INTC-AP" "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "WUP_REQ,Wake up request" "0: Power on is not requested,1: Power on is requested"
group.long 0xC4C++0x03
line.long 0x00 "FSMLOCKRC1_CORE5,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 16.--31. 1. "CNT_VALUE_15_0,Indicates count value for FSM deadlock error"
newline
rbitfld.long 0x00 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred" "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred"
newline
rbitfld.long 0x00 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred" "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred"
newline
rbitfld.long 0x00 13. "Reserved_13,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred" "0: FSM dead lock has not occurred,1: FSM dead lock has occurred"
newline
bitfld.long 0x00 11. "LOCK_EN,FSM deadlock error enable" "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled"
newline
bitfld.long 0x00 10. "PRTCL_EN,P-channel protocol error enable" "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled"
newline
bitfld.long 0x00 9. "CRPT_EN,P-channel corruption error enable" "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled"
newline
rbitfld.long 0x00 8. "Reserved_8,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 7. "PRTCL_EIJT,P-channel protocol error injection" "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active"
newline
bitfld.long 0x00 6. "CRPT_EIJT,P-channel corruption error injection" "0,1"
newline
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 4. "LOCK_EIJT,FSM deadlock error injection" "0,1"
newline
bitfld.long 0x00 3. "PRTCL_CLR,P-channel protocol error clear" "0,1"
newline
bitfld.long 0x00 2. "CRPT_CLR,P-channel corruption error clear" "0,1"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "LOCK_CLR,FSM deadlock error clear" "0,1"
group.long 0xC50++0x03
line.long 0x00 "PDENYSTSRC1_CORE5,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
rbitfld.long 0x00 4.--5. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0xC54++0x03
line.long 0x00 "PDENYINTRC1_CORE5,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
rbitfld.long 0x00 4.--5. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0xC58++0x03
line.long 0x00 "FSMSTSRC1_CORE5,This register is a 32-bit readable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "STATE_7_0,Indicate current state of A3 FSM"
group.long 0xC5C++0x03
line.long 0x00 "G2GPRC1_CORE5,This register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "GPR0_31_0,This fields are allowed to write any values and they don't affect module operation"
group.long 0xC60++0x03
line.long 0x00 "SAFECTRLC1_CORE5,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are always read as H'0000 0"
newline
bitfld.long 0x00 13. "DBGEN_PPDN,When Cortex-A55 is in debug mode Cortex-A55 core is goes to OFF_EMU mode instead of OFF mode" "0: Cortex-A55 goes to OFF mode,1: Cortex-A55 goes to OFF_EMU mode"
newline
hexmask.long.byte 0x00 5.--12. 1. "Reserved_5,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4. "A1_RTT,A1 RuntimeTEST enable" "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A55 cores are booted" "0: RuntimeTEST is disabled before Cortex-A55 cores,1: RuntimeTEST is enabled before Cortex-A55 cores"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0xC70++0x03
line.long 0x00 "RVBARLC1_CORE5,This register is a 32-bit readable/writable register"
hexmask.long 0x00 2.--31. 1. "RVBAR_31_2,These bits indicate RVBARADDR[31:2]"
newline
rbitfld.long 0x00 0.--1. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3"
group.long 0xC74++0x03
line.long 0x00 "RVBARHC1_CORE5,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--11. 1. "RVBAR_43_32,These bits indicate RVBARADDR[43:32]"
group.long 0xC78++0x03
line.long 0x00 "RVBARPLC1_CORE5,This register is a 32-bit readable/writable register"
hexmask.long 0x00 2.--31. 1. "RVBARP_31_2,These bits indicate RVBARADDR[31:2]"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "VLD,RVBARP valid" "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR"
group.long 0xC7C++0x03
line.long 0x00 "RVBARPHC1_CORE5,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--11. 1. "RVBARP_43_32,These bits indicate RVBARADDR[43:32]"
group.long 0xE00++0x03
line.long 0x00 "PWRCTRLC1_CORE6,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 19.--31. 1. "Reserved_19,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol" "0: Power mode transition to OFF_EMU mode is..,1: Power mode transition to OFF_EMU mode is.."
newline
bitfld.long 0x00 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled"
newline
bitfld.long 0x00 16. "PCHWUPEN,ON mode transition enable by P-channel protocol" "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled"
newline
hexmask.long.word 0x00 6.--15. 1. "Reserved_6,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 5. "DWUP_EN,This bit enables wakeup request from Debugger" "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled"
newline
bitfld.long 0x00 4. "IWUP_EN,This bit enables wakeup request from INTC-AP" "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "WUP_REQ,Wake up request" "0: Power on is not requested,1: Power on is requested"
group.long 0xE0C++0x03
line.long 0x00 "FSMLOCKRC1_CORE6,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 16.--31. 1. "CNT_VALUE_15_0,Indicates count value for FSM deadlock error"
newline
rbitfld.long 0x00 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred" "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred"
newline
rbitfld.long 0x00 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred" "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred"
newline
rbitfld.long 0x00 13. "Reserved_13,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred" "0: FSM dead lock has not occurred,1: FSM dead lock has occurred"
newline
bitfld.long 0x00 11. "LOCK_EN,FSM deadlock error enable" "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled"
newline
bitfld.long 0x00 10. "PRTCL_EN,P-channel protocol error enable" "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled"
newline
bitfld.long 0x00 9. "CRPT_EN,P-channel corruption error enable" "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled"
newline
rbitfld.long 0x00 8. "Reserved_8,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 7. "PRTCL_EIJT,P-channel protocol error injection" "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active"
newline
bitfld.long 0x00 6. "CRPT_EIJT,P-channel corruption error injection" "0,1"
newline
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 4. "LOCK_EIJT,FSM deadlock error injection" "0,1"
newline
bitfld.long 0x00 3. "PRTCL_CLR,P-channel protocol error clear" "0,1"
newline
bitfld.long 0x00 2. "CRPT_CLR,P-channel corruption error clear" "0,1"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "LOCK_CLR,FSM deadlock error clear" "0,1"
group.long 0xE10++0x03
line.long 0x00 "PDENYSTSRC1_CORE6,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
rbitfld.long 0x00 4.--5. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0xE14++0x03
line.long 0x00 "PDENYINTRC1_CORE6,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
rbitfld.long 0x00 4.--5. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0xE18++0x03
line.long 0x00 "FSMSTSRC1_CORE6,This register is a 32-bit readable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "STATE_7_0,Indicate current state of A3 FSM"
group.long 0xE1C++0x03
line.long 0x00 "G2GPRC1_CORE6,This register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "GPR0_31_0,This fields are allowed to write any values and they don't affect module operation"
group.long 0xE20++0x03
line.long 0x00 "SAFECTRLC1_CORE6,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are always read as H'0000 0"
newline
bitfld.long 0x00 13. "DBGEN_PPDN,When Cortex-A55 is in debug mode Cortex-A55 core is goes to OFF_EMU mode instead of OFF mode" "0: Cortex-A55 goes to OFF mode,1: Cortex-A55 goes to OFF_EMU mode"
newline
hexmask.long.byte 0x00 5.--12. 1. "Reserved_5,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4. "A1_RTT,A1 RuntimeTEST enable" "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A55 cores are booted" "0: RuntimeTEST is disabled before Cortex-A55 cores,1: RuntimeTEST is enabled before Cortex-A55 cores"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0xE30++0x03
line.long 0x00 "RVBARLC1_CORE6,This register is a 32-bit readable/writable register"
hexmask.long 0x00 2.--31. 1. "RVBAR_31_2,These bits indicate RVBARADDR[31:2]"
newline
rbitfld.long 0x00 0.--1. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3"
group.long 0xE34++0x03
line.long 0x00 "RVBARHC1_CORE6,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--11. 1. "RVBAR_43_32,These bits indicate RVBARADDR[43:32]"
group.long 0xE38++0x03
line.long 0x00 "RVBARPLC1_CORE6,This register is a 32-bit readable/writable register"
hexmask.long 0x00 2.--31. 1. "RVBARP_31_2,These bits indicate RVBARADDR[31:2]"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "VLD,RVBARP valid" "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR"
group.long 0xE3C++0x03
line.long 0x00 "RVBARPHC1_CORE6,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--11. 1. "RVBARP_43_32,These bits indicate RVBARADDR[43:32]"
group.long 0xE40++0x03
line.long 0x00 "PWRCTRLC1_CORE7,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 19.--31. 1. "Reserved_19,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol" "0: Power mode transition to OFF_EMU mode is..,1: Power mode transition to OFF_EMU mode is.."
newline
bitfld.long 0x00 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled"
newline
bitfld.long 0x00 16. "PCHWUPEN,ON mode transition enable by P-channel protocol" "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled"
newline
hexmask.long.word 0x00 6.--15. 1. "Reserved_6,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 5. "DWUP_EN,This bit enables wakeup request from Debugger" "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled"
newline
bitfld.long 0x00 4. "IWUP_EN,This bit enables wakeup request from INTC-AP" "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "WUP_REQ,Wake up request" "0: Power on is not requested,1: Power on is requested"
group.long 0xE4C++0x03
line.long 0x00 "FSMLOCKRC1_CORE7,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 16.--31. 1. "CNT_VALUE_15_0,Indicates count value for FSM deadlock error"
newline
rbitfld.long 0x00 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred" "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred"
newline
rbitfld.long 0x00 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred" "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred"
newline
rbitfld.long 0x00 13. "Reserved_13,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred" "0: FSM dead lock has not occurred,1: FSM dead lock has occurred"
newline
bitfld.long 0x00 11. "LOCK_EN,FSM deadlock error enable" "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled"
newline
bitfld.long 0x00 10. "PRTCL_EN,P-channel protocol error enable" "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled"
newline
bitfld.long 0x00 9. "CRPT_EN,P-channel corruption error enable" "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled"
newline
rbitfld.long 0x00 8. "Reserved_8,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 7. "PRTCL_EIJT,P-channel protocol error injection" "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active"
newline
bitfld.long 0x00 6. "CRPT_EIJT,P-channel corruption error injection" "0,1"
newline
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 4. "LOCK_EIJT,FSM deadlock error injection" "0,1"
newline
bitfld.long 0x00 3. "PRTCL_CLR,P-channel protocol error clear" "0,1"
newline
bitfld.long 0x00 2. "CRPT_CLR,P-channel corruption error clear" "0,1"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "LOCK_CLR,FSM deadlock error clear" "0,1"
group.long 0xE50++0x03
line.long 0x00 "PDENYSTSRC1_CORE7,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
rbitfld.long 0x00 4.--5. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0xE54++0x03
line.long 0x00 "PDENYINTRC1_CORE7,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
rbitfld.long 0x00 4.--5. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0xE58++0x03
line.long 0x00 "FSMSTSRC1_CORE7,This register is a 32-bit readable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "STATE_7_0,Indicate current state of A3 FSM"
group.long 0xE5C++0x03
line.long 0x00 "G2GPRC1_CORE7,This register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "GPR0_31_0,This fields are allowed to write any values and they don't affect module operation"
group.long 0xE60++0x03
line.long 0x00 "SAFECTRLC1_CORE7,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are always read as H'0000 0"
newline
bitfld.long 0x00 13. "DBGEN_PPDN,When Cortex-A55 is in debug mode Cortex-A55 core is goes to OFF_EMU mode instead of OFF mode" "0: Cortex-A55 goes to OFF mode,1: Cortex-A55 goes to OFF_EMU mode"
newline
hexmask.long.byte 0x00 5.--12. 1. "Reserved_5,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4. "A1_RTT,A1 RuntimeTEST enable" "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A55 cores are booted" "0: RuntimeTEST is disabled before Cortex-A55 cores,1: RuntimeTEST is enabled before Cortex-A55 cores"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0xE70++0x03
line.long 0x00 "RVBARLC1_CORE7,This register is a 32-bit readable/writable register"
hexmask.long 0x00 2.--31. 1. "RVBAR_31_2,These bits indicate RVBARADDR[31:2]"
newline
rbitfld.long 0x00 0.--1. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3"
group.long 0xE74++0x03
line.long 0x00 "RVBARHC1_CORE7,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--11. 1. "RVBAR_43_32,These bits indicate RVBARADDR[43:32]"
group.long 0xE78++0x03
line.long 0x00 "RVBARPLC1_CORE7,This register is a 32-bit readable/writable register"
hexmask.long 0x00 2.--31. 1. "RVBARP_31_2,These bits indicate RVBARADDR[31:2]"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "VLD,RVBARP valid" "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR"
group.long 0xE7C++0x03
line.long 0x00 "RVBARPHC1_CORE7,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--11. 1. "RVBARP_43_32,These bits indicate RVBARADDR[43:32]"
tree.end
tree "APMU_INST_2"
base ad:0xE6172000
group.long 0x00++0x03
line.long 0x00 "WPCR2,This register is 32-bit readable/writable register"
hexmask.long.word 0x00 16.--31. 1. "Code_value,Code Value Code value (H'5AA5) needs to be set to this field when some values are set to this register"
newline
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 0. "WPE,Write Protect Enable" "0: Write protect is disabled,1: Write protect is enabled"
group.long 0x04++0x03
line.long 0x00 "WPR2,These registers are 32-bit readable/writable registers"
hexmask.long 0x00 0.--31. 1. "WPRTCT_31_0,If Write Protect is enabled inverted values need to be set to this field before write access"
group.long 0x20++0x03
line.long 0x00 "PTCSR2,This register is a 32-bit readable/writable register"
hexmask.long 0x00 2.--31. 1. "Reserved_2,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "ERR,Indicates whether access error has occurred" "0: error has not occurred,1: error has occurred"
group.long 0x24++0x03
line.long 0x00 "PTERADR2,This register is a 32-bit readable register"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--15. 1. "ADDR_15_0,Indicate address causing access error"
group.long 0x28++0x03
line.long 0x00 "DCLSEIJTR2,This register is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 0. "EIJT,Error Injection enable" "0: error injection is not active,1: error injection is active"
repeat 2. (strings "02" "12" )(list 0x0 0x4 )
group.long ($2+0x40)++0x03
line.long 0x00 "A3PWRCTRL$1,This register is a 32-bit readable/writable register"
hexmask.long 0x00 5.--31. 1. "Reserved_5,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4. "A3_PDN_EN,Power down enable for A3 power domain" "0: A3 power domain cannot be powered down,1: A3 power domain is powered down if all A1 and.."
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
repeat.end
repeat 2. (strings "02" "12" )(list 0x0 0x4 )
group.long ($2+0x48)++0x03
line.long 0x00 "A3FSMSTSR$1,This register is a 32-bit readable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "STATE_7_0,Indicate current state of A3 FSM"
repeat.end
repeat 2. (strings "02" "12" )(list 0x0 0x4 )
group.long ($2+0x50)++0x03
line.long 0x00 "A3FSMLOCKR$1,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 16.--31. 1. "CNT_VALUE_15_0,Indicates count value for FSM deadlock error"
newline
rbitfld.long 0x00 13.--15. "Reserved_13,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred" "0: FSM dead lock has not occurred,1: FSM dead lock has occurred"
newline
bitfld.long 0x00 11. "LOCK_EN,FSM deadlock error enable" "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled"
newline
rbitfld.long 0x00 5.--10. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 4. "LOCK_EIJT,FSM deadlock error injection" "0,1"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "LOCK_CLR,FSM deadlock error clear" "0,1"
repeat.end
group.long 0x58++0x03
line.long 0x00 "INTSTSR2,This register is a 32-bit readable register"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 16.--19. "A2Cx_INT,Indicate whether each A2 domain FSM issues interrupt request" "0: FSM doesn't issue interrupt request,1: FSM issues interrupt request,?..."
newline
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
abitfld.long 0x00 0.--7. "A1Cx_INT,Indicate whether each A2 domain FSM issues interrupt request" "0x00=0: FSM doesn't issue interrupt request,0x01=1: FSM issues interrupt request"
group.long 0x5C++0x03
line.long 0x00 "ERRSTSR2,This register is a 32-bit readable register"
rbitfld.long 0x00 29.--31. "Reserved_29,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 28. "CR52_ERR,Indicates whether error flag is set in FSMLOCKRCR52" "0: Error is not detected,1: Error is detected and flag is set in.."
newline
rbitfld.long 0x00 26.--27. "Reserved_26,Reserved These bits are always read as 0" "0,1,2,3"
newline
rbitfld.long 0x00 24.--25. "A3Sx_ERR,Indicates whether error flag is set in A3FSMLOCKRx" "0: Error is not detected,1: Error is detected and flag is set in..,?..."
newline
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 16.--19. "A2Cx_ERR,Indicates whether error flag is set in FSMLOCKRCLx" "0: Error is not detected,1: Error is detected and flag is set in..,?..."
newline
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
abitfld.long 0x00 0.--7. "A1Cx_ERR,Indicates whether error flag is set in FSMLOCKRCx" "0x00=0: Error is not detected,0x01=1: Error is detected and flag is set in.."
group.long 0x60++0x03
line.long 0x00 "FRSTR2,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 16.--19. "FRSTRCLx,Forced reset request for each Cortex-A55 cluster" "0: Forced reset is not requested,1: Forced reset is requested,?..."
newline
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
abitfld.long 0x00 0.--7. "FRSTRCx,Forced reset request for each Cortex-A55 core" "0x00=0: Forced reset is not requested,0x01=1: Forced reset is requested"
group.long 0x68++0x03
line.long 0x00 "FRSTCTRL2,This register is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved These bits are always read as 1" "0,1"
newline
bitfld.long 0x00 30. "FRST_MOD_DBG,Forced reset modification in debug mode" "0: All reset signals are asserted by forced reset,1: Only warm reset of Cortex-A55 is asserted by"
newline
rbitfld.long 0x00 29. "Reserved_29,Reserved These bits are always read as 1" "0,1"
newline
rbitfld.long 0x00 28. "Reserved_28,Reserved These bits are always read as 1" "0,1"
newline
rbitfld.long 0x00 27. "Reserved_27,Reserved These bits are always read as 1" "0,1"
newline
hexmask.long 0x00 0.--26. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x80++0x03
line.long 0x00 "PADDCHKSTSR2,This register is a 32-bit readable/writable register"
bitfld.long 0x00 31. "PADD_CHK_SID_CLR,PADD_CHK_SID clear bit" "0,1"
newline
hexmask.long.tbyte 0x00 8.--30. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "PADD_CHK_SID_7_0,Indicates Source ID of fault transaction detected PADD_CHK mechanism"
group.long 0x84++0x03
line.long 0x00 "PWDATACHKSTSR2,This register is a 32-bit readable/writable register"
bitfld.long 0x00 31. "PWDATA_CHK_SID_CLR,PWDATA_CHK_SID clear bit" "0,1"
newline
hexmask.long.tbyte 0x00 8.--30. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "PWDATA_CHK_SID_7_0,Indicates Source ID of fault transaction detected PWDATA_CHK mechanism"
group.long 0xA4++0x03
line.long 0x00 "AA64nAA32CR2,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 13. "AA64nAA32_c7,AA64nAA32 control bit of Core 7" "0: AA32 mode,1: AA64 mode"
newline
bitfld.long 0x00 12. "AA64nAA32_c6,AA64nAA32 control bit of Core 6" "0: AA32 mode,1: AA64 mode"
newline
rbitfld.long 0x00 10.--11. "Reserved_10,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 9. "AA64nAA32_c5,AA64nAA32 control bit of Core 5" "0: AA32 mode,1: AA64 mode"
newline
bitfld.long 0x00 8. "AA64nAA32_c4,AA64nAA32 control bit of Core 4" "0: AA32 mode,1: AA64 mode"
newline
rbitfld.long 0x00 6.--7. "Reserved_6,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 5. "AA64nAA32_c3,AA64nAA32 control bit of Core 3" "0: AA32 mode,1: AA64 mode"
newline
bitfld.long 0x00 4. "AA64nAA32_c2,AA64nAA32 control bit of Core 2" "0: AA32 mode,1: AA64 mode"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "AA64nAA32_c1,AA64nAA32 control bit of Core 1" "0: AA32 mode,1: AA64 mode"
newline
bitfld.long 0x00 0. "AA64nAA32_c0,AA64nAA32 control bit of Core 0" "0: AA32 mode,1: AA64 mode"
group.long 0x300++0x03
line.long 0x00 "CR52CR2,This register is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 30. "NCPUHALT,NCPUHALT means inverted value of CPUHALT defined in Cortex-R52 TRM" "0: Processor halt after reset,1: No processor halt after reset"
newline
bitfld.long 0x00 29. "CFGRAMPROTEN,CFGRAMPROTEN defined in Cortex-R52 TRM" "0: RAM memory protection is disabled out of reset,1: RAM memory protection is enabled out of reset"
newline
bitfld.long 0x00 28. "CFGTCMBOOT,CFGTCMBOOT defined in Cortex-R52 TRM" "0: ATCM is disabled out of reset,1: ATCM is enabled and at address 0x0 out of reset"
newline
bitfld.long 0x00 27. "CFGINITREG,CFGINITREG defined in Cortex-R52 TRM" "0: Program-visible registers are not initialized..,1: Program-visible registers are initialized to"
newline
bitfld.long 0x00 26. "CFGL1CACHEINVDIS0,CFGL1CACHEINVDIS defined in Cortex-R52 TRM" "0: Automatic post-reset L1 cache invalidate is,1: Automatic post-reset L1 cache invalidate is"
newline
hexmask.long 0x00 0.--25. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x304++0x03
line.long 0x00 "CR52RSTCTRL2,This register is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 0. "CR52RST,Cortex-R52 reset" "0: All Cortex-R52 resets are negated,1: All Cortex-R52 resets are asserted"
group.long 0x30C++0x03
line.long 0x00 "FSMLOCKRCR522,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 16.--31. 1. "CNT_VALUE_15_0,Indicates count value for FSM deadlock error"
newline
rbitfld.long 0x00 13.--15. "Reserved_13,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred" "0: FSM dead lock has not occurred,1: FSM dead lock has occurred"
newline
bitfld.long 0x00 11. "LOCK_EN,FSM deadlock error enable" "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled"
newline
rbitfld.long 0x00 5.--10. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 4. "LOCK_EIJT,FSM deadlock error injection" "0,1"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "LOCK_CLR,FSM deadlock error clear" "0,1"
group.long 0x318++0x03
line.long 0x00 "FSMSTSRCR522,This register is a 32-bit readable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "STATE_7_0,Indicate current state of Cortex-R52 FSM"
group.long 0x31C++0x03
line.long 0x00 "G2GPRCR522,This register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "GPR_31_0,This fields are allowed to write any values and they don't affect module operation"
group.long 0x328++0x03
line.long 0x00 "CR52CMPEN2,This register is a 32-bit readable/writable register"
hexmask.long 0x00 2.--31. 1. "Reserved_2,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 1. "NSRCMPEN,Non-safety- related comparator enable" "0: Comparator for Non-safety-related signals is,1: Comparator for Non-safety-related signals is"
newline
bitfld.long 0x00 0. "CMPEN,Comparator enables" "0: Comparator is disabled,1: Comparator is enabled"
group.long 0x32C++0x03
line.long 0x00 "GCNTERRENCR522,This register is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 0. "GCNTERREN,Generic Counter error detection enable" "0: Error detection is disabled,1: Error detection is enabled"
group.long 0x330++0x03
line.long 0x00 "CR52RVBAR2,This register is a 32-bit readable/writable register"
hexmask.long 0x00 5.--31. 1. "CFGVECTABLE_31_5,CFGVECTABLE defined in Cortex-R52 TRM"
newline
rbitfld.long 0x00 0.--4. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x334++0x03
line.long 0x00 "CR52BAR2,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 18.--31. 1. "RBAR_31_18,Real time CPU (Cortex-R52) Boot Address"
newline
hexmask.long.word 0x00 5.--17. 1. "Reserved_5,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4. "BAREN,BAR enables" "0,1"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
rbitfld.long 0x00 0.--1. "BTMD_1_0,Boot Mode" "0: RBAR is assigned for boot address,?,2: Boot from BootROM,?..."
group.long 0x338++0x03
line.long 0x00 "CR52RVBARP2,This register is a 32-bit readable/writable register"
hexmask.long 0x00 5.--31. 1. "CFGVECTABLE_31_5,CFGVECTABLE defined in Cortex-R52 TRM"
newline
rbitfld.long 0x00 1.--4. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0. "VLD,CR52RVBARP valid" "0: CR52RVBAR is used to define CFGVECTABLE for,1: CR52RVBARP is used to define CFGVECTABLE for"
group.long 0x33C++0x03
line.long 0x00 "CR52BARP2,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 18.--31. 1. "RBAR_31_18,Real time CPU (Cortex-R52) Boot Address"
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hexmask.long.word 0x00 5.--17. 1. "Reserved_5,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4. "BAREN,BAR enables" "0: RBAR is not valid,1: RBAR is valid"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "VLD,CR52BARP valid" "0: CR52BAR is used to define Boot Address of,1: CR52BARP is used to define Boot Address of"
group.long 0x400++0x03
line.long 0x00 "PWRCTRLCL2_CLUSTER0,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 22.--31. 1. "Reserved_22,Reserved These bits are always read as 0"
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bitfld.long 0x00 21. "PCHMRETEN,MEM_RET mode transition enable by P-channel protocol" "0,1"
newline
bitfld.long 0x00 20. "PCHFRETEN,FUNC_RET mode transition enable by P-channel protocol" "0: Power mode transition to FUNC_RET mode is..,1: Power mode transition to FUNC_RET mode is.."
newline
rbitfld.long 0x00 18.--19. "Reserved_18,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 17. "PCHPDNEN,OFF mode transition enable by P-channel protocol" "0,1"
newline
bitfld.long 0x00 16. "PCHWUPEN,ON mode transition enable by P-channel protocol" "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled"
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hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0x404++0x03
line.long 0x00 "L3CTRLCL2_CLUSTER0,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 19.--31. 1. "Reserved_19,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 16.--18. "L3STS_2_0,Indicates current L3 cache partial power down/up status" "?,1: 1/4 of L3 cache is powered on,2: 1/2 of L3 cache is powered on,3: 3/4 of L3 cache is powered on,4: All L3 cache is powered on,?..."
newline
rbitfld.long 0x00 10.--15. "Reserved_10,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 9. "L3DENY,Indicates whether L3 cache partial power down/up request is denied" "0: request is not denied,1: request is denied"
newline
bitfld.long 0x00 8. "L3ACCEPT,Indicates whether L3 cache partial power down/up request is accepted" "0: request is not accepted,1: request is accepted"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4. "L3REQ,L3 cache partial power down/up request" "0: L3 cache partial power down/up is not requested,1: L3 cache partial power down/up is requested"
newline
rbitfld.long 0x00 3. "Reserved_3,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0.--2. "L3CTRL_2_0,L3 cache partial power down/up control" "0: All L3 cache is power-off or Cluster's power,1: 1/4 of L3 cache is power-on,2: 1/2 of L3 cache is power-on,3: 3/4 of L3 cache is power-on,4: All L3 cache is power-on,?..."
group.long 0x40C++0x03
line.long 0x00 "FSMLOCKRCL2_CLUSTER0,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 16.--31. 1. "CNT_VALUE_15_0,Indicates count value for FSM deadlock error"
newline
rbitfld.long 0x00 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred" "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred"
newline
rbitfld.long 0x00 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred" "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred"
newline
rbitfld.long 0x00 13. "Reserved_13,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred" "0: FSM dead lock has not occurred,1: FSM dead lock has occurred"
newline
bitfld.long 0x00 11. "LOCK_EN,FSM deadlock error enable" "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled"
newline
bitfld.long 0x00 10. "PRTCL_EN,P-channel protocol error enable" "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled"
newline
bitfld.long 0x00 9. "CRPT_EN,P-channel corruption error enable" "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled"
newline
rbitfld.long 0x00 8. "Reserved_8,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 7. "PRTCL_EIJT,P-channel protocol error injection" "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active"
newline
bitfld.long 0x00 6. "CRPT_EIJT,P-channel corruption error injection" "0,1"
newline
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 4. "LOCK_EIJT,FSM deadlock error injection" "0,1"
newline
bitfld.long 0x00 3. "PRTCL_CLR,P-channel protocol error clear" "0,1"
newline
bitfld.long 0x00 2. "CRPT_CLR,P-channel corruption error clear" "0,1"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "LOCK_CLR,FSM deadlock error clear" "0,1"
group.long 0x410++0x03
line.long 0x00 "PDENYSTSRCL2_CLUSTER0,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 23.--31. 1. "Reserved_23,Reserved These bits are always read as 0"
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bitfld.long 0x00 22. "DNY_OFF_ON,Indicates whether a denied state transition has occurred by power mode transition from OFF mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 21. "DNY_ON_OFF,Indicates whether a denied state transition has occurred by power mode transition from ON mode to OFF mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 20. "DNY_ON_FUNC,Indicates whether a denied state transition has occurred by power mode transition from ON mode to FUNC_RET mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 19. "DNY_FUNC_ON,Indicates whether a denied state transition has occurred by power mode transition from FUNC_RET mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 18. "DNY_ON_MEM,Indicates whether a denied state transition has occurred by power mode transition from ON mode to MEM_RET mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 17. "DNY_MEM_ON,Indicates whether a denied state transition has occurred by power mode transition from MEM_RET mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 16. "DNY_ON_L3CHG,Indicates whether a denied state transition has occurred by L3 cache partial power mode control" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
hexmask.long.word 0x00 0.--15. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x414++0x03
line.long 0x00 "PDENYINTRCL2_CLUSTER0,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 23.--31. 1. "Reserved_23,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 22. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 21. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 20. "INT_ON_FUNC,Issuing interrupt enable by DNY_ON_FUNC" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 19. "INT_FUNC_ON,Issuing interrupt enable by DNY_FUNC_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 18. "INT_ON_MEM,Issuing interrupt enable by DNY_ON_MEM" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 17. "INT_MEM_ON,Issuing interrupt enable by DNY_MEM_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 16. "INT_ON_L3CHG,Issuing interrupt enable by DNY_ON_L3CHG" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
hexmask.long.word 0x00 0.--15. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x418++0x03
line.long 0x00 "FSMSTSRCL2_CLUSTER0,This register is a 32-bit readable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "STATE_7_0,Indicate current state of Cortex-A55 cluster FSM"
group.long 0x41C++0x03
line.long 0x00 "G2GPRCL2_CLUSTER0,This register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "GPR0_31_0,This fields are allowed to write any values and they don't affect module operation"
group.long 0x420++0x03
line.long 0x00 "SAFECTRLCL2_CLUSTER0,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as H'0000 2"
newline
rbitfld.long 0x00 11. "Reserved_11,Reserved These bits are always read as 0" "0,1"
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bitfld.long 0x00 10. "A2_RTT_MRET,A2 RuntimeTEST using MEM_RET mode enable" "0: A2 RuntimeTEST using MEM_RET mode is disabled,1: A2 RuntimeTEST using MEM_RET mode is enabled"
newline
bitfld.long 0x00 9. "A2_RTT_POFF,A2 RuntimeTEST using Pseudo OFF mode enable" "0: A2 RuntimeTEST using Pseudo OFF mode is..,1: A2 RuntimeTEST using Pseudo OFF mode is enabled"
newline
hexmask.long.byte 0x00 2.--8. 1. "Reserved_2,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A55 clusters are booted" "0: RuntimeTEST is disabled before Cortex-A55,1: RuntimeTEST is enabled before Cortex-A55"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0x424++0x03
line.long 0x00 "DCLSENCL2_CLUSTER0,This register is a 32-bit readable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 0. "DCLSEN,Indicates Cortex-A55 cluster is DCLS mode" "0: Cortex-A55 cluster is not in DCLS mode,1: Cortex-A55 cluster is in DCLS mode"
group.long 0x428++0x03
line.long 0x00 "DCLSCMPENCL2_CLUSTER0,This register is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 0. "DCLSCMPEN,DCLS comparator enable" "0: DCLS comparator is disabled,1: DCLS comparator is enabled"
group.long 0x42C++0x03
line.long 0x00 "GCNTERRENCL2_CLUSTER0,This register is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 0. "GCNTERREN,Generic Counter error detection enable" "0: Error detection is disabled,1: Error detection is enabled"
group.long 0x430++0x03
line.long 0x00 "CA55BAR2_CLUSTER0,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 10.--31. 1. "BAR_39_18,Cortex-A55 Boot Address for AA32 mode"
newline
rbitfld.long 0x00 5.--9. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 4. "BAREN,BAR enables" "0,1"
newline
rbitfld.long 0x00 0.--3. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x438++0x03
line.long 0x00 "CA55BARP2_CLUSTER0,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 10.--31. 1. "BAR_39_18,Cortex-A55 Boot Address for AA32 mode"
newline
rbitfld.long 0x00 5.--9. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 4. "BAREN,BAR enables" "0,1"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "VLD,CA55BARP valid" "0: CA55BAR is used to define Cortex-A55's Boot,1: CA55BARP is used to define Cortex-A55's Boot"
group.long 0x440++0x03
line.long 0x00 "PWRCTRLCL2_CLUSTER1,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 22.--31. 1. "Reserved_22,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 21. "PCHMRETEN,MEM_RET mode transition enable by P-channel protocol" "0,1"
newline
bitfld.long 0x00 20. "PCHFRETEN,FUNC_RET mode transition enable by P-channel protocol" "0: Power mode transition to FUNC_RET mode is..,1: Power mode transition to FUNC_RET mode is.."
newline
rbitfld.long 0x00 18.--19. "Reserved_18,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 17. "PCHPDNEN,OFF mode transition enable by P-channel protocol" "0,1"
newline
bitfld.long 0x00 16. "PCHWUPEN,ON mode transition enable by P-channel protocol" "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled"
newline
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0x444++0x03
line.long 0x00 "L3CTRLCL2_CLUSTER1,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 19.--31. 1. "Reserved_19,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 16.--18. "L3STS_2_0,Indicates current L3 cache partial power down/up status" "?,1: 1/4 of L3 cache is powered on,2: 1/2 of L3 cache is powered on,3: 3/4 of L3 cache is powered on,4: All L3 cache is powered on,?..."
newline
rbitfld.long 0x00 10.--15. "Reserved_10,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 9. "L3DENY,Indicates whether L3 cache partial power down/up request is denied" "0: request is not denied,1: request is denied"
newline
bitfld.long 0x00 8. "L3ACCEPT,Indicates whether L3 cache partial power down/up request is accepted" "0: request is not accepted,1: request is accepted"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4. "L3REQ,L3 cache partial power down/up request" "0: L3 cache partial power down/up is not requested,1: L3 cache partial power down/up is requested"
newline
rbitfld.long 0x00 3. "Reserved_3,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0.--2. "L3CTRL_2_0,L3 cache partial power down/up control" "0: All L3 cache is power-off or Cluster's power,1: 1/4 of L3 cache is power-on,2: 1/2 of L3 cache is power-on,3: 3/4 of L3 cache is power-on,4: All L3 cache is power-on,?..."
group.long 0x44C++0x03
line.long 0x00 "FSMLOCKRCL2_CLUSTER1,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 16.--31. 1. "CNT_VALUE_15_0,Indicates count value for FSM deadlock error"
newline
rbitfld.long 0x00 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred" "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred"
newline
rbitfld.long 0x00 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred" "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred"
newline
rbitfld.long 0x00 13. "Reserved_13,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred" "0: FSM dead lock has not occurred,1: FSM dead lock has occurred"
newline
bitfld.long 0x00 11. "LOCK_EN,FSM deadlock error enable" "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled"
newline
bitfld.long 0x00 10. "PRTCL_EN,P-channel protocol error enable" "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled"
newline
bitfld.long 0x00 9. "CRPT_EN,P-channel corruption error enable" "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled"
newline
rbitfld.long 0x00 8. "Reserved_8,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 7. "PRTCL_EIJT,P-channel protocol error injection" "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active"
newline
bitfld.long 0x00 6. "CRPT_EIJT,P-channel corruption error injection" "0,1"
newline
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 4. "LOCK_EIJT,FSM deadlock error injection" "0,1"
newline
bitfld.long 0x00 3. "PRTCL_CLR,P-channel protocol error clear" "0,1"
newline
bitfld.long 0x00 2. "CRPT_CLR,P-channel corruption error clear" "0,1"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "LOCK_CLR,FSM deadlock error clear" "0,1"
group.long 0x450++0x03
line.long 0x00 "PDENYSTSRCL2_CLUSTER1,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 23.--31. 1. "Reserved_23,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 22. "DNY_OFF_ON,Indicates whether a denied state transition has occurred by power mode transition from OFF mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 21. "DNY_ON_OFF,Indicates whether a denied state transition has occurred by power mode transition from ON mode to OFF mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 20. "DNY_ON_FUNC,Indicates whether a denied state transition has occurred by power mode transition from ON mode to FUNC_RET mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 19. "DNY_FUNC_ON,Indicates whether a denied state transition has occurred by power mode transition from FUNC_RET mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 18. "DNY_ON_MEM,Indicates whether a denied state transition has occurred by power mode transition from ON mode to MEM_RET mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 17. "DNY_MEM_ON,Indicates whether a denied state transition has occurred by power mode transition from MEM_RET mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 16. "DNY_ON_L3CHG,Indicates whether a denied state transition has occurred by L3 cache partial power mode control" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
hexmask.long.word 0x00 0.--15. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x454++0x03
line.long 0x00 "PDENYINTRCL2_CLUSTER1,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 23.--31. 1. "Reserved_23,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 22. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 21. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 20. "INT_ON_FUNC,Issuing interrupt enable by DNY_ON_FUNC" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 19. "INT_FUNC_ON,Issuing interrupt enable by DNY_FUNC_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 18. "INT_ON_MEM,Issuing interrupt enable by DNY_ON_MEM" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 17. "INT_MEM_ON,Issuing interrupt enable by DNY_MEM_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 16. "INT_ON_L3CHG,Issuing interrupt enable by DNY_ON_L3CHG" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
hexmask.long.word 0x00 0.--15. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x458++0x03
line.long 0x00 "FSMSTSRCL2_CLUSTER1,This register is a 32-bit readable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "STATE_7_0,Indicate current state of Cortex-A55 cluster FSM"
group.long 0x45C++0x03
line.long 0x00 "G2GPRCL2_CLUSTER1,This register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "GPR0_31_0,This fields are allowed to write any values and they don't affect module operation"
group.long 0x460++0x03
line.long 0x00 "SAFECTRLCL2_CLUSTER1,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as H'0000 2"
newline
rbitfld.long 0x00 11. "Reserved_11,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 10. "A2_RTT_MRET,A2 RuntimeTEST using MEM_RET mode enable" "0: A2 RuntimeTEST using MEM_RET mode is disabled,1: A2 RuntimeTEST using MEM_RET mode is enabled"
newline
bitfld.long 0x00 9. "A2_RTT_POFF,A2 RuntimeTEST using Pseudo OFF mode enable" "0: A2 RuntimeTEST using Pseudo OFF mode is..,1: A2 RuntimeTEST using Pseudo OFF mode is enabled"
newline
hexmask.long.byte 0x00 2.--8. 1. "Reserved_2,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A55 clusters are booted" "0: RuntimeTEST is disabled before Cortex-A55,1: RuntimeTEST is enabled before Cortex-A55"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0x464++0x03
line.long 0x00 "DCLSENCL2_CLUSTER1,This register is a 32-bit readable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 0. "DCLSEN,Indicates Cortex-A55 cluster is DCLS mode" "0: Cortex-A55 cluster is not in DCLS mode,1: Cortex-A55 cluster is in DCLS mode"
group.long 0x468++0x03
line.long 0x00 "DCLSCMPENCL2_CLUSTER1,This register is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 0. "DCLSCMPEN,DCLS comparator enable" "0: DCLS comparator is disabled,1: DCLS comparator is enabled"
group.long 0x46C++0x03
line.long 0x00 "GCNTERRENCL2_CLUSTER1,This register is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 0. "GCNTERREN,Generic Counter error detection enable" "0: Error detection is disabled,1: Error detection is enabled"
group.long 0x470++0x03
line.long 0x00 "CA55BAR2_CLUSTER1,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 10.--31. 1. "BAR_39_18,Cortex-A55 Boot Address for AA32 mode"
newline
rbitfld.long 0x00 5.--9. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 4. "BAREN,BAR enables" "0,1"
newline
rbitfld.long 0x00 0.--3. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x478++0x03
line.long 0x00 "CA55BARP2_CLUSTER1,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 10.--31. 1. "BAR_39_18,Cortex-A55 Boot Address for AA32 mode"
newline
rbitfld.long 0x00 5.--9. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 4. "BAREN,BAR enables" "0,1"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "VLD,CA55BARP valid" "0: CA55BAR is used to define Cortex-A55's Boot,1: CA55BARP is used to define Cortex-A55's Boot"
group.long 0x480++0x03
line.long 0x00 "PWRCTRLCL2_CLUSTER2,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 22.--31. 1. "Reserved_22,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 21. "PCHMRETEN,MEM_RET mode transition enable by P-channel protocol" "0,1"
newline
bitfld.long 0x00 20. "PCHFRETEN,FUNC_RET mode transition enable by P-channel protocol" "0: Power mode transition to FUNC_RET mode is..,1: Power mode transition to FUNC_RET mode is.."
newline
rbitfld.long 0x00 18.--19. "Reserved_18,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 17. "PCHPDNEN,OFF mode transition enable by P-channel protocol" "0,1"
newline
bitfld.long 0x00 16. "PCHWUPEN,ON mode transition enable by P-channel protocol" "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled"
newline
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0x484++0x03
line.long 0x00 "L3CTRLCL2_CLUSTER2,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 19.--31. 1. "Reserved_19,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 16.--18. "L3STS_2_0,Indicates current L3 cache partial power down/up status" "?,1: 1/4 of L3 cache is powered on,2: 1/2 of L3 cache is powered on,3: 3/4 of L3 cache is powered on,4: All L3 cache is powered on,?..."
newline
rbitfld.long 0x00 10.--15. "Reserved_10,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 9. "L3DENY,Indicates whether L3 cache partial power down/up request is denied" "0: request is not denied,1: request is denied"
newline
bitfld.long 0x00 8. "L3ACCEPT,Indicates whether L3 cache partial power down/up request is accepted" "0: request is not accepted,1: request is accepted"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4. "L3REQ,L3 cache partial power down/up request" "0: L3 cache partial power down/up is not requested,1: L3 cache partial power down/up is requested"
newline
rbitfld.long 0x00 3. "Reserved_3,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0.--2. "L3CTRL_2_0,L3 cache partial power down/up control" "0: All L3 cache is power-off or Cluster's power,1: 1/4 of L3 cache is power-on,2: 1/2 of L3 cache is power-on,3: 3/4 of L3 cache is power-on,4: All L3 cache is power-on,?..."
group.long 0x48C++0x03
line.long 0x00 "FSMLOCKRCL2_CLUSTER2,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 16.--31. 1. "CNT_VALUE_15_0,Indicates count value for FSM deadlock error"
newline
rbitfld.long 0x00 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred" "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred"
newline
rbitfld.long 0x00 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred" "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred"
newline
rbitfld.long 0x00 13. "Reserved_13,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred" "0: FSM dead lock has not occurred,1: FSM dead lock has occurred"
newline
bitfld.long 0x00 11. "LOCK_EN,FSM deadlock error enable" "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled"
newline
bitfld.long 0x00 10. "PRTCL_EN,P-channel protocol error enable" "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled"
newline
bitfld.long 0x00 9. "CRPT_EN,P-channel corruption error enable" "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled"
newline
rbitfld.long 0x00 8. "Reserved_8,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 7. "PRTCL_EIJT,P-channel protocol error injection" "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active"
newline
bitfld.long 0x00 6. "CRPT_EIJT,P-channel corruption error injection" "0,1"
newline
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 4. "LOCK_EIJT,FSM deadlock error injection" "0,1"
newline
bitfld.long 0x00 3. "PRTCL_CLR,P-channel protocol error clear" "0,1"
newline
bitfld.long 0x00 2. "CRPT_CLR,P-channel corruption error clear" "0,1"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "LOCK_CLR,FSM deadlock error clear" "0,1"
group.long 0x490++0x03
line.long 0x00 "PDENYSTSRCL2_CLUSTER2,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 23.--31. 1. "Reserved_23,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 22. "DNY_OFF_ON,Indicates whether a denied state transition has occurred by power mode transition from OFF mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 21. "DNY_ON_OFF,Indicates whether a denied state transition has occurred by power mode transition from ON mode to OFF mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 20. "DNY_ON_FUNC,Indicates whether a denied state transition has occurred by power mode transition from ON mode to FUNC_RET mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 19. "DNY_FUNC_ON,Indicates whether a denied state transition has occurred by power mode transition from FUNC_RET mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 18. "DNY_ON_MEM,Indicates whether a denied state transition has occurred by power mode transition from ON mode to MEM_RET mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 17. "DNY_MEM_ON,Indicates whether a denied state transition has occurred by power mode transition from MEM_RET mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 16. "DNY_ON_L3CHG,Indicates whether a denied state transition has occurred by L3 cache partial power mode control" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
hexmask.long.word 0x00 0.--15. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x494++0x03
line.long 0x00 "PDENYINTRCL2_CLUSTER2,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 23.--31. 1. "Reserved_23,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 22. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 21. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 20. "INT_ON_FUNC,Issuing interrupt enable by DNY_ON_FUNC" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 19. "INT_FUNC_ON,Issuing interrupt enable by DNY_FUNC_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 18. "INT_ON_MEM,Issuing interrupt enable by DNY_ON_MEM" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 17. "INT_MEM_ON,Issuing interrupt enable by DNY_MEM_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 16. "INT_ON_L3CHG,Issuing interrupt enable by DNY_ON_L3CHG" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
hexmask.long.word 0x00 0.--15. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x498++0x03
line.long 0x00 "FSMSTSRCL2_CLUSTER2,This register is a 32-bit readable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "STATE_7_0,Indicate current state of Cortex-A55 cluster FSM"
group.long 0x49C++0x03
line.long 0x00 "G2GPRCL2_CLUSTER2,This register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "GPR0_31_0,This fields are allowed to write any values and they don't affect module operation"
group.long 0x4A0++0x03
line.long 0x00 "SAFECTRLCL2_CLUSTER2,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as H'0000 2"
newline
rbitfld.long 0x00 11. "Reserved_11,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 10. "A2_RTT_MRET,A2 RuntimeTEST using MEM_RET mode enable" "0: A2 RuntimeTEST using MEM_RET mode is disabled,1: A2 RuntimeTEST using MEM_RET mode is enabled"
newline
bitfld.long 0x00 9. "A2_RTT_POFF,A2 RuntimeTEST using Pseudo OFF mode enable" "0: A2 RuntimeTEST using Pseudo OFF mode is..,1: A2 RuntimeTEST using Pseudo OFF mode is enabled"
newline
hexmask.long.byte 0x00 2.--8. 1. "Reserved_2,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A55 clusters are booted" "0: RuntimeTEST is disabled before Cortex-A55,1: RuntimeTEST is enabled before Cortex-A55"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0x4A4++0x03
line.long 0x00 "DCLSENCL2_CLUSTER2,This register is a 32-bit readable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 0. "DCLSEN,Indicates Cortex-A55 cluster is DCLS mode" "0: Cortex-A55 cluster is not in DCLS mode,1: Cortex-A55 cluster is in DCLS mode"
group.long 0x4A8++0x03
line.long 0x00 "DCLSCMPENCL2_CLUSTER2,This register is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 0. "DCLSCMPEN,DCLS comparator enable" "0: DCLS comparator is disabled,1: DCLS comparator is enabled"
group.long 0x4AC++0x03
line.long 0x00 "GCNTERRENCL2_CLUSTER2,This register is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 0. "GCNTERREN,Generic Counter error detection enable" "0: Error detection is disabled,1: Error detection is enabled"
group.long 0x4B0++0x03
line.long 0x00 "CA55BAR2_CLUSTER2,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 10.--31. 1. "BAR_39_18,Cortex-A55 Boot Address for AA32 mode"
newline
rbitfld.long 0x00 5.--9. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 4. "BAREN,BAR enables" "0,1"
newline
rbitfld.long 0x00 0.--3. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4B8++0x03
line.long 0x00 "CA55BARP2_CLUSTER2,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 10.--31. 1. "BAR_39_18,Cortex-A55 Boot Address for AA32 mode"
newline
rbitfld.long 0x00 5.--9. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 4. "BAREN,BAR enables" "0,1"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "VLD,CA55BARP valid" "0: CA55BAR is used to define Cortex-A55's Boot,1: CA55BARP is used to define Cortex-A55's Boot"
group.long 0x4C0++0x03
line.long 0x00 "PWRCTRLCL2_CLUSTER3,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 22.--31. 1. "Reserved_22,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 21. "PCHMRETEN,MEM_RET mode transition enable by P-channel protocol" "0,1"
newline
bitfld.long 0x00 20. "PCHFRETEN,FUNC_RET mode transition enable by P-channel protocol" "0: Power mode transition to FUNC_RET mode is..,1: Power mode transition to FUNC_RET mode is.."
newline
rbitfld.long 0x00 18.--19. "Reserved_18,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 17. "PCHPDNEN,OFF mode transition enable by P-channel protocol" "0,1"
newline
bitfld.long 0x00 16. "PCHWUPEN,ON mode transition enable by P-channel protocol" "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled"
newline
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0x4C4++0x03
line.long 0x00 "L3CTRLCL2_CLUSTER3,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 19.--31. 1. "Reserved_19,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 16.--18. "L3STS_2_0,Indicates current L3 cache partial power down/up status" "?,1: 1/4 of L3 cache is powered on,2: 1/2 of L3 cache is powered on,3: 3/4 of L3 cache is powered on,4: All L3 cache is powered on,?..."
newline
rbitfld.long 0x00 10.--15. "Reserved_10,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 9. "L3DENY,Indicates whether L3 cache partial power down/up request is denied" "0: request is not denied,1: request is denied"
newline
bitfld.long 0x00 8. "L3ACCEPT,Indicates whether L3 cache partial power down/up request is accepted" "0: request is not accepted,1: request is accepted"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4. "L3REQ,L3 cache partial power down/up request" "0: L3 cache partial power down/up is not requested,1: L3 cache partial power down/up is requested"
newline
rbitfld.long 0x00 3. "Reserved_3,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0.--2. "L3CTRL_2_0,L3 cache partial power down/up control" "0: All L3 cache is power-off or Cluster's power,1: 1/4 of L3 cache is power-on,2: 1/2 of L3 cache is power-on,3: 3/4 of L3 cache is power-on,4: All L3 cache is power-on,?..."
group.long 0x4CC++0x03
line.long 0x00 "FSMLOCKRCL2_CLUSTER3,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 16.--31. 1. "CNT_VALUE_15_0,Indicates count value for FSM deadlock error"
newline
rbitfld.long 0x00 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred" "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred"
newline
rbitfld.long 0x00 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred" "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred"
newline
rbitfld.long 0x00 13. "Reserved_13,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred" "0: FSM dead lock has not occurred,1: FSM dead lock has occurred"
newline
bitfld.long 0x00 11. "LOCK_EN,FSM deadlock error enable" "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled"
newline
bitfld.long 0x00 10. "PRTCL_EN,P-channel protocol error enable" "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled"
newline
bitfld.long 0x00 9. "CRPT_EN,P-channel corruption error enable" "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled"
newline
rbitfld.long 0x00 8. "Reserved_8,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 7. "PRTCL_EIJT,P-channel protocol error injection" "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active"
newline
bitfld.long 0x00 6. "CRPT_EIJT,P-channel corruption error injection" "0,1"
newline
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 4. "LOCK_EIJT,FSM deadlock error injection" "0,1"
newline
bitfld.long 0x00 3. "PRTCL_CLR,P-channel protocol error clear" "0,1"
newline
bitfld.long 0x00 2. "CRPT_CLR,P-channel corruption error clear" "0,1"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "LOCK_CLR,FSM deadlock error clear" "0,1"
group.long 0x4D0++0x03
line.long 0x00 "PDENYSTSRCL2_CLUSTER3,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 23.--31. 1. "Reserved_23,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 22. "DNY_OFF_ON,Indicates whether a denied state transition has occurred by power mode transition from OFF mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 21. "DNY_ON_OFF,Indicates whether a denied state transition has occurred by power mode transition from ON mode to OFF mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 20. "DNY_ON_FUNC,Indicates whether a denied state transition has occurred by power mode transition from ON mode to FUNC_RET mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 19. "DNY_FUNC_ON,Indicates whether a denied state transition has occurred by power mode transition from FUNC_RET mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 18. "DNY_ON_MEM,Indicates whether a denied state transition has occurred by power mode transition from ON mode to MEM_RET mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 17. "DNY_MEM_ON,Indicates whether a denied state transition has occurred by power mode transition from MEM_RET mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 16. "DNY_ON_L3CHG,Indicates whether a denied state transition has occurred by L3 cache partial power mode control" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
hexmask.long.word 0x00 0.--15. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x4D4++0x03
line.long 0x00 "PDENYINTRCL2_CLUSTER3,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 23.--31. 1. "Reserved_23,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 22. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 21. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 20. "INT_ON_FUNC,Issuing interrupt enable by DNY_ON_FUNC" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 19. "INT_FUNC_ON,Issuing interrupt enable by DNY_FUNC_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 18. "INT_ON_MEM,Issuing interrupt enable by DNY_ON_MEM" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 17. "INT_MEM_ON,Issuing interrupt enable by DNY_MEM_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 16. "INT_ON_L3CHG,Issuing interrupt enable by DNY_ON_L3CHG" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
hexmask.long.word 0x00 0.--15. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x4D8++0x03
line.long 0x00 "FSMSTSRCL2_CLUSTER3,This register is a 32-bit readable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "STATE_7_0,Indicate current state of Cortex-A55 cluster FSM"
group.long 0x4DC++0x03
line.long 0x00 "G2GPRCL2_CLUSTER3,This register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "GPR0_31_0,This fields are allowed to write any values and they don't affect module operation"
group.long 0x4E0++0x03
line.long 0x00 "SAFECTRLCL2_CLUSTER3,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as H'0000 2"
newline
rbitfld.long 0x00 11. "Reserved_11,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 10. "A2_RTT_MRET,A2 RuntimeTEST using MEM_RET mode enable" "0: A2 RuntimeTEST using MEM_RET mode is disabled,1: A2 RuntimeTEST using MEM_RET mode is enabled"
newline
bitfld.long 0x00 9. "A2_RTT_POFF,A2 RuntimeTEST using Pseudo OFF mode enable" "0: A2 RuntimeTEST using Pseudo OFF mode is..,1: A2 RuntimeTEST using Pseudo OFF mode is enabled"
newline
hexmask.long.byte 0x00 2.--8. 1. "Reserved_2,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A55 clusters are booted" "0: RuntimeTEST is disabled before Cortex-A55,1: RuntimeTEST is enabled before Cortex-A55"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0x4E4++0x03
line.long 0x00 "DCLSENCL2_CLUSTER3,This register is a 32-bit readable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 0. "DCLSEN,Indicates Cortex-A55 cluster is DCLS mode" "0: Cortex-A55 cluster is not in DCLS mode,1: Cortex-A55 cluster is in DCLS mode"
group.long 0x4E8++0x03
line.long 0x00 "DCLSCMPENCL2_CLUSTER3,This register is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 0. "DCLSCMPEN,DCLS comparator enable" "0: DCLS comparator is disabled,1: DCLS comparator is enabled"
group.long 0x4EC++0x03
line.long 0x00 "GCNTERRENCL2_CLUSTER3,This register is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 0. "GCNTERREN,Generic Counter error detection enable" "0: Error detection is disabled,1: Error detection is enabled"
group.long 0x4F0++0x03
line.long 0x00 "CA55BAR2_CLUSTER3,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 10.--31. 1. "BAR_39_18,Cortex-A55 Boot Address for AA32 mode"
newline
rbitfld.long 0x00 5.--9. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 4. "BAREN,BAR enables" "0,1"
newline
rbitfld.long 0x00 0.--3. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4F8++0x03
line.long 0x00 "CA55BARP2_CLUSTER3,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 10.--31. 1. "BAR_39_18,Cortex-A55 Boot Address for AA32 mode"
newline
rbitfld.long 0x00 5.--9. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 4. "BAREN,BAR enables" "0,1"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "VLD,CA55BARP valid" "0: CA55BAR is used to define Cortex-A55's Boot,1: CA55BARP is used to define Cortex-A55's Boot"
group.long 0x800++0x03
line.long 0x00 "PWRCTRLC2_CORE0,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 19.--31. 1. "Reserved_19,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol" "0: Power mode transition to OFF_EMU mode is..,1: Power mode transition to OFF_EMU mode is.."
newline
bitfld.long 0x00 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled"
newline
bitfld.long 0x00 16. "PCHWUPEN,ON mode transition enable by P-channel protocol" "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled"
newline
hexmask.long.word 0x00 6.--15. 1. "Reserved_6,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 5. "DWUP_EN,This bit enables wakeup request from Debugger" "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled"
newline
bitfld.long 0x00 4. "IWUP_EN,This bit enables wakeup request from INTC-AP" "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "WUP_REQ,Wake up request" "0: Power on is not requested,1: Power on is requested"
group.long 0x80C++0x03
line.long 0x00 "FSMLOCKRC2_CORE0,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 16.--31. 1. "CNT_VALUE_15_0,Indicates count value for FSM deadlock error"
newline
rbitfld.long 0x00 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred" "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred"
newline
rbitfld.long 0x00 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred" "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred"
newline
rbitfld.long 0x00 13. "Reserved_13,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred" "0: FSM dead lock has not occurred,1: FSM dead lock has occurred"
newline
bitfld.long 0x00 11. "LOCK_EN,FSM deadlock error enable" "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled"
newline
bitfld.long 0x00 10. "PRTCL_EN,P-channel protocol error enable" "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled"
newline
bitfld.long 0x00 9. "CRPT_EN,P-channel corruption error enable" "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled"
newline
rbitfld.long 0x00 8. "Reserved_8,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 7. "PRTCL_EIJT,P-channel protocol error injection" "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active"
newline
bitfld.long 0x00 6. "CRPT_EIJT,P-channel corruption error injection" "0,1"
newline
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 4. "LOCK_EIJT,FSM deadlock error injection" "0,1"
newline
bitfld.long 0x00 3. "PRTCL_CLR,P-channel protocol error clear" "0,1"
newline
bitfld.long 0x00 2. "CRPT_CLR,P-channel corruption error clear" "0,1"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "LOCK_CLR,FSM deadlock error clear" "0,1"
group.long 0x810++0x03
line.long 0x00 "PDENYSTSRC2_CORE0,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
rbitfld.long 0x00 4.--5. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0x814++0x03
line.long 0x00 "PDENYINTRC2_CORE0,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
rbitfld.long 0x00 4.--5. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0x818++0x03
line.long 0x00 "FSMSTSRC2_CORE0,This register is a 32-bit readable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "STATE_7_0,Indicate current state of A3 FSM"
group.long 0x81C++0x03
line.long 0x00 "G2GPRC2_CORE0,This register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "GPR0_31_0,This fields are allowed to write any values and they don't affect module operation"
group.long 0x820++0x03
line.long 0x00 "SAFECTRLC2_CORE0,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are always read as H'0000 0"
newline
bitfld.long 0x00 13. "DBGEN_PPDN,When Cortex-A55 is in debug mode Cortex-A55 core is goes to OFF_EMU mode instead of OFF mode" "0: Cortex-A55 goes to OFF mode,1: Cortex-A55 goes to OFF_EMU mode"
newline
hexmask.long.byte 0x00 5.--12. 1. "Reserved_5,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4. "A1_RTT,A1 RuntimeTEST enable" "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A55 cores are booted" "0: RuntimeTEST is disabled before Cortex-A55 cores,1: RuntimeTEST is enabled before Cortex-A55 cores"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0x830++0x03
line.long 0x00 "RVBARLC2_CORE0,This register is a 32-bit readable/writable register"
hexmask.long 0x00 2.--31. 1. "RVBAR_31_2,These bits indicate RVBARADDR[31:2]"
newline
rbitfld.long 0x00 0.--1. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3"
group.long 0x834++0x03
line.long 0x00 "RVBARHC2_CORE0,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--11. 1. "RVBAR_43_32,These bits indicate RVBARADDR[43:32]"
group.long 0x838++0x03
line.long 0x00 "RVBARPLC2_CORE0,This register is a 32-bit readable/writable register"
hexmask.long 0x00 2.--31. 1. "RVBARP_31_2,These bits indicate RVBARADDR[31:2]"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "VLD,RVBARP valid" "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR"
group.long 0x83C++0x03
line.long 0x00 "RVBARPHC2_CORE0,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--11. 1. "RVBARP_43_32,These bits indicate RVBARADDR[43:32]"
group.long 0x840++0x03
line.long 0x00 "PWRCTRLC2_CORE1,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 19.--31. 1. "Reserved_19,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol" "0: Power mode transition to OFF_EMU mode is..,1: Power mode transition to OFF_EMU mode is.."
newline
bitfld.long 0x00 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled"
newline
bitfld.long 0x00 16. "PCHWUPEN,ON mode transition enable by P-channel protocol" "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled"
newline
hexmask.long.word 0x00 6.--15. 1. "Reserved_6,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 5. "DWUP_EN,This bit enables wakeup request from Debugger" "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled"
newline
bitfld.long 0x00 4. "IWUP_EN,This bit enables wakeup request from INTC-AP" "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "WUP_REQ,Wake up request" "0: Power on is not requested,1: Power on is requested"
group.long 0x84C++0x03
line.long 0x00 "FSMLOCKRC2_CORE1,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 16.--31. 1. "CNT_VALUE_15_0,Indicates count value for FSM deadlock error"
newline
rbitfld.long 0x00 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred" "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred"
newline
rbitfld.long 0x00 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred" "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred"
newline
rbitfld.long 0x00 13. "Reserved_13,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred" "0: FSM dead lock has not occurred,1: FSM dead lock has occurred"
newline
bitfld.long 0x00 11. "LOCK_EN,FSM deadlock error enable" "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled"
newline
bitfld.long 0x00 10. "PRTCL_EN,P-channel protocol error enable" "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled"
newline
bitfld.long 0x00 9. "CRPT_EN,P-channel corruption error enable" "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled"
newline
rbitfld.long 0x00 8. "Reserved_8,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 7. "PRTCL_EIJT,P-channel protocol error injection" "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active"
newline
bitfld.long 0x00 6. "CRPT_EIJT,P-channel corruption error injection" "0,1"
newline
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 4. "LOCK_EIJT,FSM deadlock error injection" "0,1"
newline
bitfld.long 0x00 3. "PRTCL_CLR,P-channel protocol error clear" "0,1"
newline
bitfld.long 0x00 2. "CRPT_CLR,P-channel corruption error clear" "0,1"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "LOCK_CLR,FSM deadlock error clear" "0,1"
group.long 0x850++0x03
line.long 0x00 "PDENYSTSRC2_CORE1,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
rbitfld.long 0x00 4.--5. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0x854++0x03
line.long 0x00 "PDENYINTRC2_CORE1,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
rbitfld.long 0x00 4.--5. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0x858++0x03
line.long 0x00 "FSMSTSRC2_CORE1,This register is a 32-bit readable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "STATE_7_0,Indicate current state of A3 FSM"
group.long 0x85C++0x03
line.long 0x00 "G2GPRC2_CORE1,This register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "GPR0_31_0,This fields are allowed to write any values and they don't affect module operation"
group.long 0x860++0x03
line.long 0x00 "SAFECTRLC2_CORE1,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are always read as H'0000 0"
newline
bitfld.long 0x00 13. "DBGEN_PPDN,When Cortex-A55 is in debug mode Cortex-A55 core is goes to OFF_EMU mode instead of OFF mode" "0: Cortex-A55 goes to OFF mode,1: Cortex-A55 goes to OFF_EMU mode"
newline
hexmask.long.byte 0x00 5.--12. 1. "Reserved_5,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4. "A1_RTT,A1 RuntimeTEST enable" "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A55 cores are booted" "0: RuntimeTEST is disabled before Cortex-A55 cores,1: RuntimeTEST is enabled before Cortex-A55 cores"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0x870++0x03
line.long 0x00 "RVBARLC2_CORE1,This register is a 32-bit readable/writable register"
hexmask.long 0x00 2.--31. 1. "RVBAR_31_2,These bits indicate RVBARADDR[31:2]"
newline
rbitfld.long 0x00 0.--1. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3"
group.long 0x874++0x03
line.long 0x00 "RVBARHC2_CORE1,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--11. 1. "RVBAR_43_32,These bits indicate RVBARADDR[43:32]"
group.long 0x878++0x03
line.long 0x00 "RVBARPLC2_CORE1,This register is a 32-bit readable/writable register"
hexmask.long 0x00 2.--31. 1. "RVBARP_31_2,These bits indicate RVBARADDR[31:2]"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "VLD,RVBARP valid" "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR"
group.long 0x87C++0x03
line.long 0x00 "RVBARPHC2_CORE1,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--11. 1. "RVBARP_43_32,These bits indicate RVBARADDR[43:32]"
group.long 0xA00++0x03
line.long 0x00 "PWRCTRLC2_CORE2,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 19.--31. 1. "Reserved_19,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol" "0: Power mode transition to OFF_EMU mode is..,1: Power mode transition to OFF_EMU mode is.."
newline
bitfld.long 0x00 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled"
newline
bitfld.long 0x00 16. "PCHWUPEN,ON mode transition enable by P-channel protocol" "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled"
newline
hexmask.long.word 0x00 6.--15. 1. "Reserved_6,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 5. "DWUP_EN,This bit enables wakeup request from Debugger" "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled"
newline
bitfld.long 0x00 4. "IWUP_EN,This bit enables wakeup request from INTC-AP" "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "WUP_REQ,Wake up request" "0: Power on is not requested,1: Power on is requested"
group.long 0xA0C++0x03
line.long 0x00 "FSMLOCKRC2_CORE2,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 16.--31. 1. "CNT_VALUE_15_0,Indicates count value for FSM deadlock error"
newline
rbitfld.long 0x00 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred" "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred"
newline
rbitfld.long 0x00 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred" "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred"
newline
rbitfld.long 0x00 13. "Reserved_13,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred" "0: FSM dead lock has not occurred,1: FSM dead lock has occurred"
newline
bitfld.long 0x00 11. "LOCK_EN,FSM deadlock error enable" "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled"
newline
bitfld.long 0x00 10. "PRTCL_EN,P-channel protocol error enable" "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled"
newline
bitfld.long 0x00 9. "CRPT_EN,P-channel corruption error enable" "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled"
newline
rbitfld.long 0x00 8. "Reserved_8,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 7. "PRTCL_EIJT,P-channel protocol error injection" "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active"
newline
bitfld.long 0x00 6. "CRPT_EIJT,P-channel corruption error injection" "0,1"
newline
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 4. "LOCK_EIJT,FSM deadlock error injection" "0,1"
newline
bitfld.long 0x00 3. "PRTCL_CLR,P-channel protocol error clear" "0,1"
newline
bitfld.long 0x00 2. "CRPT_CLR,P-channel corruption error clear" "0,1"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "LOCK_CLR,FSM deadlock error clear" "0,1"
group.long 0xA10++0x03
line.long 0x00 "PDENYSTSRC2_CORE2,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
rbitfld.long 0x00 4.--5. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0xA14++0x03
line.long 0x00 "PDENYINTRC2_CORE2,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
rbitfld.long 0x00 4.--5. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0xA18++0x03
line.long 0x00 "FSMSTSRC2_CORE2,This register is a 32-bit readable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "STATE_7_0,Indicate current state of A3 FSM"
group.long 0xA1C++0x03
line.long 0x00 "G2GPRC2_CORE2,This register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "GPR0_31_0,This fields are allowed to write any values and they don't affect module operation"
group.long 0xA20++0x03
line.long 0x00 "SAFECTRLC2_CORE2,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are always read as H'0000 0"
newline
bitfld.long 0x00 13. "DBGEN_PPDN,When Cortex-A55 is in debug mode Cortex-A55 core is goes to OFF_EMU mode instead of OFF mode" "0: Cortex-A55 goes to OFF mode,1: Cortex-A55 goes to OFF_EMU mode"
newline
hexmask.long.byte 0x00 5.--12. 1. "Reserved_5,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4. "A1_RTT,A1 RuntimeTEST enable" "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A55 cores are booted" "0: RuntimeTEST is disabled before Cortex-A55 cores,1: RuntimeTEST is enabled before Cortex-A55 cores"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0xA30++0x03
line.long 0x00 "RVBARLC2_CORE2,This register is a 32-bit readable/writable register"
hexmask.long 0x00 2.--31. 1. "RVBAR_31_2,These bits indicate RVBARADDR[31:2]"
newline
rbitfld.long 0x00 0.--1. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3"
group.long 0xA34++0x03
line.long 0x00 "RVBARHC2_CORE2,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--11. 1. "RVBAR_43_32,These bits indicate RVBARADDR[43:32]"
group.long 0xA38++0x03
line.long 0x00 "RVBARPLC2_CORE2,This register is a 32-bit readable/writable register"
hexmask.long 0x00 2.--31. 1. "RVBARP_31_2,These bits indicate RVBARADDR[31:2]"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "VLD,RVBARP valid" "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR"
group.long 0xA3C++0x03
line.long 0x00 "RVBARPHC2_CORE2,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--11. 1. "RVBARP_43_32,These bits indicate RVBARADDR[43:32]"
group.long 0xA40++0x03
line.long 0x00 "PWRCTRLC2_CORE3,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 19.--31. 1. "Reserved_19,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol" "0: Power mode transition to OFF_EMU mode is..,1: Power mode transition to OFF_EMU mode is.."
newline
bitfld.long 0x00 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled"
newline
bitfld.long 0x00 16. "PCHWUPEN,ON mode transition enable by P-channel protocol" "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled"
newline
hexmask.long.word 0x00 6.--15. 1. "Reserved_6,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 5. "DWUP_EN,This bit enables wakeup request from Debugger" "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled"
newline
bitfld.long 0x00 4. "IWUP_EN,This bit enables wakeup request from INTC-AP" "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "WUP_REQ,Wake up request" "0: Power on is not requested,1: Power on is requested"
group.long 0xA4C++0x03
line.long 0x00 "FSMLOCKRC2_CORE3,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 16.--31. 1. "CNT_VALUE_15_0,Indicates count value for FSM deadlock error"
newline
rbitfld.long 0x00 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred" "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred"
newline
rbitfld.long 0x00 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred" "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred"
newline
rbitfld.long 0x00 13. "Reserved_13,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred" "0: FSM dead lock has not occurred,1: FSM dead lock has occurred"
newline
bitfld.long 0x00 11. "LOCK_EN,FSM deadlock error enable" "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled"
newline
bitfld.long 0x00 10. "PRTCL_EN,P-channel protocol error enable" "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled"
newline
bitfld.long 0x00 9. "CRPT_EN,P-channel corruption error enable" "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled"
newline
rbitfld.long 0x00 8. "Reserved_8,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 7. "PRTCL_EIJT,P-channel protocol error injection" "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active"
newline
bitfld.long 0x00 6. "CRPT_EIJT,P-channel corruption error injection" "0,1"
newline
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 4. "LOCK_EIJT,FSM deadlock error injection" "0,1"
newline
bitfld.long 0x00 3. "PRTCL_CLR,P-channel protocol error clear" "0,1"
newline
bitfld.long 0x00 2. "CRPT_CLR,P-channel corruption error clear" "0,1"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "LOCK_CLR,FSM deadlock error clear" "0,1"
group.long 0xA50++0x03
line.long 0x00 "PDENYSTSRC2_CORE3,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
rbitfld.long 0x00 4.--5. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0xA54++0x03
line.long 0x00 "PDENYINTRC2_CORE3,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
rbitfld.long 0x00 4.--5. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0xA58++0x03
line.long 0x00 "FSMSTSRC2_CORE3,This register is a 32-bit readable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "STATE_7_0,Indicate current state of A3 FSM"
group.long 0xA5C++0x03
line.long 0x00 "G2GPRC2_CORE3,This register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "GPR0_31_0,This fields are allowed to write any values and they don't affect module operation"
group.long 0xA60++0x03
line.long 0x00 "SAFECTRLC2_CORE3,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are always read as H'0000 0"
newline
bitfld.long 0x00 13. "DBGEN_PPDN,When Cortex-A55 is in debug mode Cortex-A55 core is goes to OFF_EMU mode instead of OFF mode" "0: Cortex-A55 goes to OFF mode,1: Cortex-A55 goes to OFF_EMU mode"
newline
hexmask.long.byte 0x00 5.--12. 1. "Reserved_5,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4. "A1_RTT,A1 RuntimeTEST enable" "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A55 cores are booted" "0: RuntimeTEST is disabled before Cortex-A55 cores,1: RuntimeTEST is enabled before Cortex-A55 cores"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0xA70++0x03
line.long 0x00 "RVBARLC2_CORE3,This register is a 32-bit readable/writable register"
hexmask.long 0x00 2.--31. 1. "RVBAR_31_2,These bits indicate RVBARADDR[31:2]"
newline
rbitfld.long 0x00 0.--1. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3"
group.long 0xA74++0x03
line.long 0x00 "RVBARHC2_CORE3,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--11. 1. "RVBAR_43_32,These bits indicate RVBARADDR[43:32]"
group.long 0xA78++0x03
line.long 0x00 "RVBARPLC2_CORE3,This register is a 32-bit readable/writable register"
hexmask.long 0x00 2.--31. 1. "RVBARP_31_2,These bits indicate RVBARADDR[31:2]"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "VLD,RVBARP valid" "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR"
group.long 0xA7C++0x03
line.long 0x00 "RVBARPHC2_CORE3,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--11. 1. "RVBARP_43_32,These bits indicate RVBARADDR[43:32]"
group.long 0xC00++0x03
line.long 0x00 "PWRCTRLC2_CORE4,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 19.--31. 1. "Reserved_19,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol" "0: Power mode transition to OFF_EMU mode is..,1: Power mode transition to OFF_EMU mode is.."
newline
bitfld.long 0x00 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled"
newline
bitfld.long 0x00 16. "PCHWUPEN,ON mode transition enable by P-channel protocol" "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled"
newline
hexmask.long.word 0x00 6.--15. 1. "Reserved_6,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 5. "DWUP_EN,This bit enables wakeup request from Debugger" "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled"
newline
bitfld.long 0x00 4. "IWUP_EN,This bit enables wakeup request from INTC-AP" "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "WUP_REQ,Wake up request" "0: Power on is not requested,1: Power on is requested"
group.long 0xC0C++0x03
line.long 0x00 "FSMLOCKRC2_CORE4,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 16.--31. 1. "CNT_VALUE_15_0,Indicates count value for FSM deadlock error"
newline
rbitfld.long 0x00 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred" "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred"
newline
rbitfld.long 0x00 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred" "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred"
newline
rbitfld.long 0x00 13. "Reserved_13,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred" "0: FSM dead lock has not occurred,1: FSM dead lock has occurred"
newline
bitfld.long 0x00 11. "LOCK_EN,FSM deadlock error enable" "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled"
newline
bitfld.long 0x00 10. "PRTCL_EN,P-channel protocol error enable" "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled"
newline
bitfld.long 0x00 9. "CRPT_EN,P-channel corruption error enable" "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled"
newline
rbitfld.long 0x00 8. "Reserved_8,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 7. "PRTCL_EIJT,P-channel protocol error injection" "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active"
newline
bitfld.long 0x00 6. "CRPT_EIJT,P-channel corruption error injection" "0,1"
newline
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 4. "LOCK_EIJT,FSM deadlock error injection" "0,1"
newline
bitfld.long 0x00 3. "PRTCL_CLR,P-channel protocol error clear" "0,1"
newline
bitfld.long 0x00 2. "CRPT_CLR,P-channel corruption error clear" "0,1"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "LOCK_CLR,FSM deadlock error clear" "0,1"
group.long 0xC10++0x03
line.long 0x00 "PDENYSTSRC2_CORE4,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
rbitfld.long 0x00 4.--5. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0xC14++0x03
line.long 0x00 "PDENYINTRC2_CORE4,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
rbitfld.long 0x00 4.--5. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0xC18++0x03
line.long 0x00 "FSMSTSRC2_CORE4,This register is a 32-bit readable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "STATE_7_0,Indicate current state of A3 FSM"
group.long 0xC1C++0x03
line.long 0x00 "G2GPRC2_CORE4,This register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "GPR0_31_0,This fields are allowed to write any values and they don't affect module operation"
group.long 0xC20++0x03
line.long 0x00 "SAFECTRLC2_CORE4,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are always read as H'0000 0"
newline
bitfld.long 0x00 13. "DBGEN_PPDN,When Cortex-A55 is in debug mode Cortex-A55 core is goes to OFF_EMU mode instead of OFF mode" "0: Cortex-A55 goes to OFF mode,1: Cortex-A55 goes to OFF_EMU mode"
newline
hexmask.long.byte 0x00 5.--12. 1. "Reserved_5,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4. "A1_RTT,A1 RuntimeTEST enable" "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A55 cores are booted" "0: RuntimeTEST is disabled before Cortex-A55 cores,1: RuntimeTEST is enabled before Cortex-A55 cores"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0xC30++0x03
line.long 0x00 "RVBARLC2_CORE4,This register is a 32-bit readable/writable register"
hexmask.long 0x00 2.--31. 1. "RVBAR_31_2,These bits indicate RVBARADDR[31:2]"
newline
rbitfld.long 0x00 0.--1. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3"
group.long 0xC34++0x03
line.long 0x00 "RVBARHC2_CORE4,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--11. 1. "RVBAR_43_32,These bits indicate RVBARADDR[43:32]"
group.long 0xC38++0x03
line.long 0x00 "RVBARPLC2_CORE4,This register is a 32-bit readable/writable register"
hexmask.long 0x00 2.--31. 1. "RVBARP_31_2,These bits indicate RVBARADDR[31:2]"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "VLD,RVBARP valid" "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR"
group.long 0xC3C++0x03
line.long 0x00 "RVBARPHC2_CORE4,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--11. 1. "RVBARP_43_32,These bits indicate RVBARADDR[43:32]"
group.long 0xC40++0x03
line.long 0x00 "PWRCTRLC2_CORE5,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 19.--31. 1. "Reserved_19,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol" "0: Power mode transition to OFF_EMU mode is..,1: Power mode transition to OFF_EMU mode is.."
newline
bitfld.long 0x00 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled"
newline
bitfld.long 0x00 16. "PCHWUPEN,ON mode transition enable by P-channel protocol" "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled"
newline
hexmask.long.word 0x00 6.--15. 1. "Reserved_6,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 5. "DWUP_EN,This bit enables wakeup request from Debugger" "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled"
newline
bitfld.long 0x00 4. "IWUP_EN,This bit enables wakeup request from INTC-AP" "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "WUP_REQ,Wake up request" "0: Power on is not requested,1: Power on is requested"
group.long 0xC4C++0x03
line.long 0x00 "FSMLOCKRC2_CORE5,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 16.--31. 1. "CNT_VALUE_15_0,Indicates count value for FSM deadlock error"
newline
rbitfld.long 0x00 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred" "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred"
newline
rbitfld.long 0x00 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred" "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred"
newline
rbitfld.long 0x00 13. "Reserved_13,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred" "0: FSM dead lock has not occurred,1: FSM dead lock has occurred"
newline
bitfld.long 0x00 11. "LOCK_EN,FSM deadlock error enable" "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled"
newline
bitfld.long 0x00 10. "PRTCL_EN,P-channel protocol error enable" "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled"
newline
bitfld.long 0x00 9. "CRPT_EN,P-channel corruption error enable" "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled"
newline
rbitfld.long 0x00 8. "Reserved_8,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 7. "PRTCL_EIJT,P-channel protocol error injection" "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active"
newline
bitfld.long 0x00 6. "CRPT_EIJT,P-channel corruption error injection" "0,1"
newline
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 4. "LOCK_EIJT,FSM deadlock error injection" "0,1"
newline
bitfld.long 0x00 3. "PRTCL_CLR,P-channel protocol error clear" "0,1"
newline
bitfld.long 0x00 2. "CRPT_CLR,P-channel corruption error clear" "0,1"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "LOCK_CLR,FSM deadlock error clear" "0,1"
group.long 0xC50++0x03
line.long 0x00 "PDENYSTSRC2_CORE5,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
rbitfld.long 0x00 4.--5. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0xC54++0x03
line.long 0x00 "PDENYINTRC2_CORE5,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
rbitfld.long 0x00 4.--5. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0xC58++0x03
line.long 0x00 "FSMSTSRC2_CORE5,This register is a 32-bit readable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "STATE_7_0,Indicate current state of A3 FSM"
group.long 0xC5C++0x03
line.long 0x00 "G2GPRC2_CORE5,This register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "GPR0_31_0,This fields are allowed to write any values and they don't affect module operation"
group.long 0xC60++0x03
line.long 0x00 "SAFECTRLC2_CORE5,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are always read as H'0000 0"
newline
bitfld.long 0x00 13. "DBGEN_PPDN,When Cortex-A55 is in debug mode Cortex-A55 core is goes to OFF_EMU mode instead of OFF mode" "0: Cortex-A55 goes to OFF mode,1: Cortex-A55 goes to OFF_EMU mode"
newline
hexmask.long.byte 0x00 5.--12. 1. "Reserved_5,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4. "A1_RTT,A1 RuntimeTEST enable" "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A55 cores are booted" "0: RuntimeTEST is disabled before Cortex-A55 cores,1: RuntimeTEST is enabled before Cortex-A55 cores"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0xC70++0x03
line.long 0x00 "RVBARLC2_CORE5,This register is a 32-bit readable/writable register"
hexmask.long 0x00 2.--31. 1. "RVBAR_31_2,These bits indicate RVBARADDR[31:2]"
newline
rbitfld.long 0x00 0.--1. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3"
group.long 0xC74++0x03
line.long 0x00 "RVBARHC2_CORE5,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--11. 1. "RVBAR_43_32,These bits indicate RVBARADDR[43:32]"
group.long 0xC78++0x03
line.long 0x00 "RVBARPLC2_CORE5,This register is a 32-bit readable/writable register"
hexmask.long 0x00 2.--31. 1. "RVBARP_31_2,These bits indicate RVBARADDR[31:2]"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "VLD,RVBARP valid" "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR"
group.long 0xC7C++0x03
line.long 0x00 "RVBARPHC2_CORE5,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--11. 1. "RVBARP_43_32,These bits indicate RVBARADDR[43:32]"
group.long 0xE00++0x03
line.long 0x00 "PWRCTRLC2_CORE6,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 19.--31. 1. "Reserved_19,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol" "0: Power mode transition to OFF_EMU mode is..,1: Power mode transition to OFF_EMU mode is.."
newline
bitfld.long 0x00 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled"
newline
bitfld.long 0x00 16. "PCHWUPEN,ON mode transition enable by P-channel protocol" "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled"
newline
hexmask.long.word 0x00 6.--15. 1. "Reserved_6,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 5. "DWUP_EN,This bit enables wakeup request from Debugger" "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled"
newline
bitfld.long 0x00 4. "IWUP_EN,This bit enables wakeup request from INTC-AP" "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "WUP_REQ,Wake up request" "0: Power on is not requested,1: Power on is requested"
group.long 0xE0C++0x03
line.long 0x00 "FSMLOCKRC2_CORE6,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 16.--31. 1. "CNT_VALUE_15_0,Indicates count value for FSM deadlock error"
newline
rbitfld.long 0x00 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred" "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred"
newline
rbitfld.long 0x00 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred" "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred"
newline
rbitfld.long 0x00 13. "Reserved_13,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred" "0: FSM dead lock has not occurred,1: FSM dead lock has occurred"
newline
bitfld.long 0x00 11. "LOCK_EN,FSM deadlock error enable" "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled"
newline
bitfld.long 0x00 10. "PRTCL_EN,P-channel protocol error enable" "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled"
newline
bitfld.long 0x00 9. "CRPT_EN,P-channel corruption error enable" "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled"
newline
rbitfld.long 0x00 8. "Reserved_8,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 7. "PRTCL_EIJT,P-channel protocol error injection" "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active"
newline
bitfld.long 0x00 6. "CRPT_EIJT,P-channel corruption error injection" "0,1"
newline
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 4. "LOCK_EIJT,FSM deadlock error injection" "0,1"
newline
bitfld.long 0x00 3. "PRTCL_CLR,P-channel protocol error clear" "0,1"
newline
bitfld.long 0x00 2. "CRPT_CLR,P-channel corruption error clear" "0,1"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "LOCK_CLR,FSM deadlock error clear" "0,1"
group.long 0xE10++0x03
line.long 0x00 "PDENYSTSRC2_CORE6,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
rbitfld.long 0x00 4.--5. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0xE14++0x03
line.long 0x00 "PDENYINTRC2_CORE6,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
rbitfld.long 0x00 4.--5. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0xE18++0x03
line.long 0x00 "FSMSTSRC2_CORE6,This register is a 32-bit readable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "STATE_7_0,Indicate current state of A3 FSM"
group.long 0xE1C++0x03
line.long 0x00 "G2GPRC2_CORE6,This register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "GPR0_31_0,This fields are allowed to write any values and they don't affect module operation"
group.long 0xE20++0x03
line.long 0x00 "SAFECTRLC2_CORE6,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are always read as H'0000 0"
newline
bitfld.long 0x00 13. "DBGEN_PPDN,When Cortex-A55 is in debug mode Cortex-A55 core is goes to OFF_EMU mode instead of OFF mode" "0: Cortex-A55 goes to OFF mode,1: Cortex-A55 goes to OFF_EMU mode"
newline
hexmask.long.byte 0x00 5.--12. 1. "Reserved_5,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4. "A1_RTT,A1 RuntimeTEST enable" "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A55 cores are booted" "0: RuntimeTEST is disabled before Cortex-A55 cores,1: RuntimeTEST is enabled before Cortex-A55 cores"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0xE30++0x03
line.long 0x00 "RVBARLC2_CORE6,This register is a 32-bit readable/writable register"
hexmask.long 0x00 2.--31. 1. "RVBAR_31_2,These bits indicate RVBARADDR[31:2]"
newline
rbitfld.long 0x00 0.--1. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3"
group.long 0xE34++0x03
line.long 0x00 "RVBARHC2_CORE6,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--11. 1. "RVBAR_43_32,These bits indicate RVBARADDR[43:32]"
group.long 0xE38++0x03
line.long 0x00 "RVBARPLC2_CORE6,This register is a 32-bit readable/writable register"
hexmask.long 0x00 2.--31. 1. "RVBARP_31_2,These bits indicate RVBARADDR[31:2]"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "VLD,RVBARP valid" "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR"
group.long 0xE3C++0x03
line.long 0x00 "RVBARPHC2_CORE6,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--11. 1. "RVBARP_43_32,These bits indicate RVBARADDR[43:32]"
group.long 0xE40++0x03
line.long 0x00 "PWRCTRLC2_CORE7,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 19.--31. 1. "Reserved_19,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol" "0: Power mode transition to OFF_EMU mode is..,1: Power mode transition to OFF_EMU mode is.."
newline
bitfld.long 0x00 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled"
newline
bitfld.long 0x00 16. "PCHWUPEN,ON mode transition enable by P-channel protocol" "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled"
newline
hexmask.long.word 0x00 6.--15. 1. "Reserved_6,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 5. "DWUP_EN,This bit enables wakeup request from Debugger" "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled"
newline
bitfld.long 0x00 4. "IWUP_EN,This bit enables wakeup request from INTC-AP" "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "WUP_REQ,Wake up request" "0: Power on is not requested,1: Power on is requested"
group.long 0xE4C++0x03
line.long 0x00 "FSMLOCKRC2_CORE7,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 16.--31. 1. "CNT_VALUE_15_0,Indicates count value for FSM deadlock error"
newline
rbitfld.long 0x00 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred" "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred"
newline
rbitfld.long 0x00 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred" "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred"
newline
rbitfld.long 0x00 13. "Reserved_13,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred" "0: FSM dead lock has not occurred,1: FSM dead lock has occurred"
newline
bitfld.long 0x00 11. "LOCK_EN,FSM deadlock error enable" "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled"
newline
bitfld.long 0x00 10. "PRTCL_EN,P-channel protocol error enable" "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled"
newline
bitfld.long 0x00 9. "CRPT_EN,P-channel corruption error enable" "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled"
newline
rbitfld.long 0x00 8. "Reserved_8,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 7. "PRTCL_EIJT,P-channel protocol error injection" "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active"
newline
bitfld.long 0x00 6. "CRPT_EIJT,P-channel corruption error injection" "0,1"
newline
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 4. "LOCK_EIJT,FSM deadlock error injection" "0,1"
newline
bitfld.long 0x00 3. "PRTCL_CLR,P-channel protocol error clear" "0,1"
newline
bitfld.long 0x00 2. "CRPT_CLR,P-channel corruption error clear" "0,1"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "LOCK_CLR,FSM deadlock error clear" "0,1"
group.long 0xE50++0x03
line.long 0x00 "PDENYSTSRC2_CORE7,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
rbitfld.long 0x00 4.--5. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0xE54++0x03
line.long 0x00 "PDENYINTRC2_CORE7,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
rbitfld.long 0x00 4.--5. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0xE58++0x03
line.long 0x00 "FSMSTSRC2_CORE7,This register is a 32-bit readable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "STATE_7_0,Indicate current state of A3 FSM"
group.long 0xE5C++0x03
line.long 0x00 "G2GPRC2_CORE7,This register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "GPR0_31_0,This fields are allowed to write any values and they don't affect module operation"
group.long 0xE60++0x03
line.long 0x00 "SAFECTRLC2_CORE7,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are always read as H'0000 0"
newline
bitfld.long 0x00 13. "DBGEN_PPDN,When Cortex-A55 is in debug mode Cortex-A55 core is goes to OFF_EMU mode instead of OFF mode" "0: Cortex-A55 goes to OFF mode,1: Cortex-A55 goes to OFF_EMU mode"
newline
hexmask.long.byte 0x00 5.--12. 1. "Reserved_5,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4. "A1_RTT,A1 RuntimeTEST enable" "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A55 cores are booted" "0: RuntimeTEST is disabled before Cortex-A55 cores,1: RuntimeTEST is enabled before Cortex-A55 cores"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0xE70++0x03
line.long 0x00 "RVBARLC2_CORE7,This register is a 32-bit readable/writable register"
hexmask.long 0x00 2.--31. 1. "RVBAR_31_2,These bits indicate RVBARADDR[31:2]"
newline
rbitfld.long 0x00 0.--1. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3"
group.long 0xE74++0x03
line.long 0x00 "RVBARHC2_CORE7,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--11. 1. "RVBAR_43_32,These bits indicate RVBARADDR[43:32]"
group.long 0xE78++0x03
line.long 0x00 "RVBARPLC2_CORE7,This register is a 32-bit readable/writable register"
hexmask.long 0x00 2.--31. 1. "RVBARP_31_2,These bits indicate RVBARADDR[31:2]"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "VLD,RVBARP valid" "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR"
group.long 0xE7C++0x03
line.long 0x00 "RVBARPHC2_CORE7,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--11. 1. "RVBARP_43_32,These bits indicate RVBARADDR[43:32]"
tree.end
tree "APMU_INST_3"
base ad:0xE6173000
group.long 0x00++0x03
line.long 0x00 "WPCR3,This register is 32-bit readable/writable register"
hexmask.long.word 0x00 16.--31. 1. "Code_value,Code Value Code value (H'5AA5) needs to be set to this field when some values are set to this register"
newline
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 0. "WPE,Write Protect Enable" "0: Write protect is disabled,1: Write protect is enabled"
group.long 0x04++0x03
line.long 0x00 "WPR3,These registers are 32-bit readable/writable registers"
hexmask.long 0x00 0.--31. 1. "WPRTCT_31_0,If Write Protect is enabled inverted values need to be set to this field before write access"
group.long 0x20++0x03
line.long 0x00 "PTCSR3,This register is a 32-bit readable/writable register"
hexmask.long 0x00 2.--31. 1. "Reserved_2,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "ERR,Indicates whether access error has occurred" "0: error has not occurred,1: error has occurred"
group.long 0x24++0x03
line.long 0x00 "PTERADR3,This register is a 32-bit readable register"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--15. 1. "ADDR_15_0,Indicate address causing access error"
group.long 0x28++0x03
line.long 0x00 "DCLSEIJTR3,This register is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 0. "EIJT,Error Injection enable" "0: error injection is not active,1: error injection is active"
repeat 2. (strings "03" "13" )(list 0x0 0x4 )
group.long ($2+0x40)++0x03
line.long 0x00 "A3PWRCTRL$1,This register is a 32-bit readable/writable register"
hexmask.long 0x00 5.--31. 1. "Reserved_5,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4. "A3_PDN_EN,Power down enable for A3 power domain" "0: A3 power domain cannot be powered down,1: A3 power domain is powered down if all A1 and.."
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
repeat.end
repeat 2. (strings "03" "13" )(list 0x0 0x4 )
group.long ($2+0x48)++0x03
line.long 0x00 "A3FSMSTSR$1,This register is a 32-bit readable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "STATE_7_0,Indicate current state of A3 FSM"
repeat.end
repeat 2. (strings "03" "13" )(list 0x0 0x4 )
group.long ($2+0x50)++0x03
line.long 0x00 "A3FSMLOCKR$1,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 16.--31. 1. "CNT_VALUE_15_0,Indicates count value for FSM deadlock error"
newline
rbitfld.long 0x00 13.--15. "Reserved_13,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred" "0: FSM dead lock has not occurred,1: FSM dead lock has occurred"
newline
bitfld.long 0x00 11. "LOCK_EN,FSM deadlock error enable" "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled"
newline
rbitfld.long 0x00 5.--10. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 4. "LOCK_EIJT,FSM deadlock error injection" "0,1"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "LOCK_CLR,FSM deadlock error clear" "0,1"
repeat.end
group.long 0x58++0x03
line.long 0x00 "INTSTSR3,This register is a 32-bit readable register"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 16.--19. "A2Cx_INT,Indicate whether each A2 domain FSM issues interrupt request" "0: FSM doesn't issue interrupt request,1: FSM issues interrupt request,?..."
newline
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
abitfld.long 0x00 0.--7. "A1Cx_INT,Indicate whether each A2 domain FSM issues interrupt request" "0x00=0: FSM doesn't issue interrupt request,0x01=1: FSM issues interrupt request"
group.long 0x5C++0x03
line.long 0x00 "ERRSTSR3,This register is a 32-bit readable register"
rbitfld.long 0x00 29.--31. "Reserved_29,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 28. "CR52_ERR,Indicates whether error flag is set in FSMLOCKRCR52" "0: Error is not detected,1: Error is detected and flag is set in.."
newline
rbitfld.long 0x00 26.--27. "Reserved_26,Reserved These bits are always read as 0" "0,1,2,3"
newline
rbitfld.long 0x00 24.--25. "A3Sx_ERR,Indicates whether error flag is set in A3FSMLOCKRx" "0: Error is not detected,1: Error is detected and flag is set in..,?..."
newline
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 16.--19. "A2Cx_ERR,Indicates whether error flag is set in FSMLOCKRCLx" "0: Error is not detected,1: Error is detected and flag is set in..,?..."
newline
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
abitfld.long 0x00 0.--7. "A1Cx_ERR,Indicates whether error flag is set in FSMLOCKRCx" "0x00=0: Error is not detected,0x01=1: Error is detected and flag is set in.."
group.long 0x60++0x03
line.long 0x00 "FRSTR3,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 16.--19. "FRSTRCLx,Forced reset request for each Cortex-A55 cluster" "0: Forced reset is not requested,1: Forced reset is requested,?..."
newline
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
abitfld.long 0x00 0.--7. "FRSTRCx,Forced reset request for each Cortex-A55 core" "0x00=0: Forced reset is not requested,0x01=1: Forced reset is requested"
group.long 0x68++0x03
line.long 0x00 "FRSTCTRL3,This register is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved These bits are always read as 1" "0,1"
newline
bitfld.long 0x00 30. "FRST_MOD_DBG,Forced reset modification in debug mode" "0: All reset signals are asserted by forced reset,1: Only warm reset of Cortex-A55 is asserted by"
newline
rbitfld.long 0x00 29. "Reserved_29,Reserved These bits are always read as 1" "0,1"
newline
rbitfld.long 0x00 28. "Reserved_28,Reserved These bits are always read as 1" "0,1"
newline
rbitfld.long 0x00 27. "Reserved_27,Reserved These bits are always read as 1" "0,1"
newline
hexmask.long 0x00 0.--26. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x80++0x03
line.long 0x00 "PADDCHKSTSR3,This register is a 32-bit readable/writable register"
bitfld.long 0x00 31. "PADD_CHK_SID_CLR,PADD_CHK_SID clear bit" "0,1"
newline
hexmask.long.tbyte 0x00 8.--30. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "PADD_CHK_SID_7_0,Indicates Source ID of fault transaction detected PADD_CHK mechanism"
group.long 0x84++0x03
line.long 0x00 "PWDATACHKSTSR3,This register is a 32-bit readable/writable register"
bitfld.long 0x00 31. "PWDATA_CHK_SID_CLR,PWDATA_CHK_SID clear bit" "0,1"
newline
hexmask.long.tbyte 0x00 8.--30. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "PWDATA_CHK_SID_7_0,Indicates Source ID of fault transaction detected PWDATA_CHK mechanism"
group.long 0xA4++0x03
line.long 0x00 "AA64nAA32CR3,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 13. "AA64nAA32_c7,AA64nAA32 control bit of Core 7" "0: AA32 mode,1: AA64 mode"
newline
bitfld.long 0x00 12. "AA64nAA32_c6,AA64nAA32 control bit of Core 6" "0: AA32 mode,1: AA64 mode"
newline
rbitfld.long 0x00 10.--11. "Reserved_10,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 9. "AA64nAA32_c5,AA64nAA32 control bit of Core 5" "0: AA32 mode,1: AA64 mode"
newline
bitfld.long 0x00 8. "AA64nAA32_c4,AA64nAA32 control bit of Core 4" "0: AA32 mode,1: AA64 mode"
newline
rbitfld.long 0x00 6.--7. "Reserved_6,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 5. "AA64nAA32_c3,AA64nAA32 control bit of Core 3" "0: AA32 mode,1: AA64 mode"
newline
bitfld.long 0x00 4. "AA64nAA32_c2,AA64nAA32 control bit of Core 2" "0: AA32 mode,1: AA64 mode"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "AA64nAA32_c1,AA64nAA32 control bit of Core 1" "0: AA32 mode,1: AA64 mode"
newline
bitfld.long 0x00 0. "AA64nAA32_c0,AA64nAA32 control bit of Core 0" "0: AA32 mode,1: AA64 mode"
group.long 0x300++0x03
line.long 0x00 "CR52CR3,This register is a 32-bit readable/writable register"
rbitfld.long 0x00 31. "Reserved_31,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 30. "NCPUHALT,NCPUHALT means inverted value of CPUHALT defined in Cortex-R52 TRM" "0: Processor halt after reset,1: No processor halt after reset"
newline
bitfld.long 0x00 29. "CFGRAMPROTEN,CFGRAMPROTEN defined in Cortex-R52 TRM" "0: RAM memory protection is disabled out of reset,1: RAM memory protection is enabled out of reset"
newline
bitfld.long 0x00 28. "CFGTCMBOOT,CFGTCMBOOT defined in Cortex-R52 TRM" "0: ATCM is disabled out of reset,1: ATCM is enabled and at address 0x0 out of reset"
newline
bitfld.long 0x00 27. "CFGINITREG,CFGINITREG defined in Cortex-R52 TRM" "0: Program-visible registers are not initialized..,1: Program-visible registers are initialized to"
newline
bitfld.long 0x00 26. "CFGL1CACHEINVDIS0,CFGL1CACHEINVDIS defined in Cortex-R52 TRM" "0: Automatic post-reset L1 cache invalidate is,1: Automatic post-reset L1 cache invalidate is"
newline
hexmask.long 0x00 0.--25. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x304++0x03
line.long 0x00 "CR52RSTCTRL3,This register is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 0. "CR52RST,Cortex-R52 reset" "0: All Cortex-R52 resets are negated,1: All Cortex-R52 resets are asserted"
group.long 0x30C++0x03
line.long 0x00 "FSMLOCKRCR523,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 16.--31. 1. "CNT_VALUE_15_0,Indicates count value for FSM deadlock error"
newline
rbitfld.long 0x00 13.--15. "Reserved_13,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred" "0: FSM dead lock has not occurred,1: FSM dead lock has occurred"
newline
bitfld.long 0x00 11. "LOCK_EN,FSM deadlock error enable" "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled"
newline
rbitfld.long 0x00 5.--10. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 4. "LOCK_EIJT,FSM deadlock error injection" "0,1"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "LOCK_CLR,FSM deadlock error clear" "0,1"
group.long 0x318++0x03
line.long 0x00 "FSMSTSRCR523,This register is a 32-bit readable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "STATE_7_0,Indicate current state of Cortex-R52 FSM"
group.long 0x31C++0x03
line.long 0x00 "G2GPRCR523,This register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "GPR_31_0,This fields are allowed to write any values and they don't affect module operation"
group.long 0x328++0x03
line.long 0x00 "CR52CMPEN3,This register is a 32-bit readable/writable register"
hexmask.long 0x00 2.--31. 1. "Reserved_2,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 1. "NSRCMPEN,Non-safety- related comparator enable" "0: Comparator for Non-safety-related signals is,1: Comparator for Non-safety-related signals is"
newline
bitfld.long 0x00 0. "CMPEN,Comparator enables" "0: Comparator is disabled,1: Comparator is enabled"
group.long 0x32C++0x03
line.long 0x00 "GCNTERRENCR523,This register is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 0. "GCNTERREN,Generic Counter error detection enable" "0: Error detection is disabled,1: Error detection is enabled"
group.long 0x330++0x03
line.long 0x00 "CR52RVBAR3,This register is a 32-bit readable/writable register"
hexmask.long 0x00 5.--31. 1. "CFGVECTABLE_31_5,CFGVECTABLE defined in Cortex-R52 TRM"
newline
rbitfld.long 0x00 0.--4. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x334++0x03
line.long 0x00 "CR52BAR3,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 18.--31. 1. "RBAR_31_18,Real time CPU (Cortex-R52) Boot Address"
newline
hexmask.long.word 0x00 5.--17. 1. "Reserved_5,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4. "BAREN,BAR enables" "0,1"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
rbitfld.long 0x00 0.--1. "BTMD_1_0,Boot Mode" "0: RBAR is assigned for boot address,?,2: Boot from BootROM,?..."
group.long 0x338++0x03
line.long 0x00 "CR52RVBARP3,This register is a 32-bit readable/writable register"
hexmask.long 0x00 5.--31. 1. "CFGVECTABLE_31_5,CFGVECTABLE defined in Cortex-R52 TRM"
newline
rbitfld.long 0x00 1.--4. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0. "VLD,CR52RVBARP valid" "0: CR52RVBAR is used to define CFGVECTABLE for,1: CR52RVBARP is used to define CFGVECTABLE for"
group.long 0x33C++0x03
line.long 0x00 "CR52BARP3,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 18.--31. 1. "RBAR_31_18,Real time CPU (Cortex-R52) Boot Address"
newline
hexmask.long.word 0x00 5.--17. 1. "Reserved_5,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4. "BAREN,BAR enables" "0: RBAR is not valid,1: RBAR is valid"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "VLD,CR52BARP valid" "0: CR52BAR is used to define Boot Address of,1: CR52BARP is used to define Boot Address of"
group.long 0x400++0x03
line.long 0x00 "PWRCTRLCL3_CLUSTER0,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 22.--31. 1. "Reserved_22,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 21. "PCHMRETEN,MEM_RET mode transition enable by P-channel protocol" "0,1"
newline
bitfld.long 0x00 20. "PCHFRETEN,FUNC_RET mode transition enable by P-channel protocol" "0: Power mode transition to FUNC_RET mode is..,1: Power mode transition to FUNC_RET mode is.."
newline
rbitfld.long 0x00 18.--19. "Reserved_18,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 17. "PCHPDNEN,OFF mode transition enable by P-channel protocol" "0,1"
newline
bitfld.long 0x00 16. "PCHWUPEN,ON mode transition enable by P-channel protocol" "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled"
newline
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0x404++0x03
line.long 0x00 "L3CTRLCL3_CLUSTER0,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 19.--31. 1. "Reserved_19,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 16.--18. "L3STS_2_0,Indicates current L3 cache partial power down/up status" "?,1: 1/4 of L3 cache is powered on,2: 1/2 of L3 cache is powered on,3: 3/4 of L3 cache is powered on,4: All L3 cache is powered on,?..."
newline
rbitfld.long 0x00 10.--15. "Reserved_10,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 9. "L3DENY,Indicates whether L3 cache partial power down/up request is denied" "0: request is not denied,1: request is denied"
newline
bitfld.long 0x00 8. "L3ACCEPT,Indicates whether L3 cache partial power down/up request is accepted" "0: request is not accepted,1: request is accepted"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4. "L3REQ,L3 cache partial power down/up request" "0: L3 cache partial power down/up is not requested,1: L3 cache partial power down/up is requested"
newline
rbitfld.long 0x00 3. "Reserved_3,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0.--2. "L3CTRL_2_0,L3 cache partial power down/up control" "0: All L3 cache is power-off or Cluster's power,1: 1/4 of L3 cache is power-on,2: 1/2 of L3 cache is power-on,3: 3/4 of L3 cache is power-on,4: All L3 cache is power-on,?..."
group.long 0x40C++0x03
line.long 0x00 "FSMLOCKRCL3_CLUSTER0,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 16.--31. 1. "CNT_VALUE_15_0,Indicates count value for FSM deadlock error"
newline
rbitfld.long 0x00 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred" "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred"
newline
rbitfld.long 0x00 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred" "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred"
newline
rbitfld.long 0x00 13. "Reserved_13,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred" "0: FSM dead lock has not occurred,1: FSM dead lock has occurred"
newline
bitfld.long 0x00 11. "LOCK_EN,FSM deadlock error enable" "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled"
newline
bitfld.long 0x00 10. "PRTCL_EN,P-channel protocol error enable" "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled"
newline
bitfld.long 0x00 9. "CRPT_EN,P-channel corruption error enable" "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled"
newline
rbitfld.long 0x00 8. "Reserved_8,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 7. "PRTCL_EIJT,P-channel protocol error injection" "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active"
newline
bitfld.long 0x00 6. "CRPT_EIJT,P-channel corruption error injection" "0,1"
newline
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 4. "LOCK_EIJT,FSM deadlock error injection" "0,1"
newline
bitfld.long 0x00 3. "PRTCL_CLR,P-channel protocol error clear" "0,1"
newline
bitfld.long 0x00 2. "CRPT_CLR,P-channel corruption error clear" "0,1"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "LOCK_CLR,FSM deadlock error clear" "0,1"
group.long 0x410++0x03
line.long 0x00 "PDENYSTSRCL3_CLUSTER0,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 23.--31. 1. "Reserved_23,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 22. "DNY_OFF_ON,Indicates whether a denied state transition has occurred by power mode transition from OFF mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 21. "DNY_ON_OFF,Indicates whether a denied state transition has occurred by power mode transition from ON mode to OFF mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 20. "DNY_ON_FUNC,Indicates whether a denied state transition has occurred by power mode transition from ON mode to FUNC_RET mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 19. "DNY_FUNC_ON,Indicates whether a denied state transition has occurred by power mode transition from FUNC_RET mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 18. "DNY_ON_MEM,Indicates whether a denied state transition has occurred by power mode transition from ON mode to MEM_RET mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 17. "DNY_MEM_ON,Indicates whether a denied state transition has occurred by power mode transition from MEM_RET mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 16. "DNY_ON_L3CHG,Indicates whether a denied state transition has occurred by L3 cache partial power mode control" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
hexmask.long.word 0x00 0.--15. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x414++0x03
line.long 0x00 "PDENYINTRCL3_CLUSTER0,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 23.--31. 1. "Reserved_23,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 22. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 21. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 20. "INT_ON_FUNC,Issuing interrupt enable by DNY_ON_FUNC" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 19. "INT_FUNC_ON,Issuing interrupt enable by DNY_FUNC_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 18. "INT_ON_MEM,Issuing interrupt enable by DNY_ON_MEM" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 17. "INT_MEM_ON,Issuing interrupt enable by DNY_MEM_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 16. "INT_ON_L3CHG,Issuing interrupt enable by DNY_ON_L3CHG" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
hexmask.long.word 0x00 0.--15. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x418++0x03
line.long 0x00 "FSMSTSRCL3_CLUSTER0,This register is a 32-bit readable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "STATE_7_0,Indicate current state of Cortex-A55 cluster FSM"
group.long 0x41C++0x03
line.long 0x00 "G2GPRCL3_CLUSTER0,This register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "GPR0_31_0,This fields are allowed to write any values and they don't affect module operation"
group.long 0x420++0x03
line.long 0x00 "SAFECTRLCL3_CLUSTER0,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as H'0000 2"
newline
rbitfld.long 0x00 11. "Reserved_11,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 10. "A2_RTT_MRET,A2 RuntimeTEST using MEM_RET mode enable" "0: A2 RuntimeTEST using MEM_RET mode is disabled,1: A2 RuntimeTEST using MEM_RET mode is enabled"
newline
bitfld.long 0x00 9. "A2_RTT_POFF,A2 RuntimeTEST using Pseudo OFF mode enable" "0: A2 RuntimeTEST using Pseudo OFF mode is..,1: A2 RuntimeTEST using Pseudo OFF mode is enabled"
newline
hexmask.long.byte 0x00 2.--8. 1. "Reserved_2,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A55 clusters are booted" "0: RuntimeTEST is disabled before Cortex-A55,1: RuntimeTEST is enabled before Cortex-A55"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0x42C++0x03
line.long 0x00 "GCNTERRENCL3_CLUSTER0,This register is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 0. "GCNTERREN,Generic Counter error detection enable" "0: Error detection is disabled,1: Error detection is enabled"
group.long 0x430++0x03
line.long 0x00 "CA55BAR3_CLUSTER0,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 10.--31. 1. "BAR_39_18,Cortex-A55 Boot Address for AA32 mode"
newline
rbitfld.long 0x00 5.--9. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 4. "BAREN,BAR enables" "0,1"
newline
rbitfld.long 0x00 0.--3. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x438++0x03
line.long 0x00 "CA55BARP3_CLUSTER0,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 10.--31. 1. "BAR_39_18,Cortex-A55 Boot Address for AA32 mode"
newline
rbitfld.long 0x00 5.--9. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 4. "BAREN,BAR enables" "0,1"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "VLD,CA55BARP valid" "0: CA55BAR is used to define Cortex-A55's Boot,1: CA55BARP is used to define Cortex-A55's Boot"
group.long 0x440++0x03
line.long 0x00 "PWRCTRLCL3_CLUSTER1,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 22.--31. 1. "Reserved_22,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 21. "PCHMRETEN,MEM_RET mode transition enable by P-channel protocol" "0,1"
newline
bitfld.long 0x00 20. "PCHFRETEN,FUNC_RET mode transition enable by P-channel protocol" "0: Power mode transition to FUNC_RET mode is..,1: Power mode transition to FUNC_RET mode is.."
newline
rbitfld.long 0x00 18.--19. "Reserved_18,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 17. "PCHPDNEN,OFF mode transition enable by P-channel protocol" "0,1"
newline
bitfld.long 0x00 16. "PCHWUPEN,ON mode transition enable by P-channel protocol" "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled"
newline
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0x444++0x03
line.long 0x00 "L3CTRLCL3_CLUSTER1,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 19.--31. 1. "Reserved_19,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 16.--18. "L3STS_2_0,Indicates current L3 cache partial power down/up status" "?,1: 1/4 of L3 cache is powered on,2: 1/2 of L3 cache is powered on,3: 3/4 of L3 cache is powered on,4: All L3 cache is powered on,?..."
newline
rbitfld.long 0x00 10.--15. "Reserved_10,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 9. "L3DENY,Indicates whether L3 cache partial power down/up request is denied" "0: request is not denied,1: request is denied"
newline
bitfld.long 0x00 8. "L3ACCEPT,Indicates whether L3 cache partial power down/up request is accepted" "0: request is not accepted,1: request is accepted"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4. "L3REQ,L3 cache partial power down/up request" "0: L3 cache partial power down/up is not requested,1: L3 cache partial power down/up is requested"
newline
rbitfld.long 0x00 3. "Reserved_3,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0.--2. "L3CTRL_2_0,L3 cache partial power down/up control" "0: All L3 cache is power-off or Cluster's power,1: 1/4 of L3 cache is power-on,2: 1/2 of L3 cache is power-on,3: 3/4 of L3 cache is power-on,4: All L3 cache is power-on,?..."
group.long 0x44C++0x03
line.long 0x00 "FSMLOCKRCL3_CLUSTER1,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 16.--31. 1. "CNT_VALUE_15_0,Indicates count value for FSM deadlock error"
newline
rbitfld.long 0x00 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred" "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred"
newline
rbitfld.long 0x00 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred" "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred"
newline
rbitfld.long 0x00 13. "Reserved_13,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred" "0: FSM dead lock has not occurred,1: FSM dead lock has occurred"
newline
bitfld.long 0x00 11. "LOCK_EN,FSM deadlock error enable" "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled"
newline
bitfld.long 0x00 10. "PRTCL_EN,P-channel protocol error enable" "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled"
newline
bitfld.long 0x00 9. "CRPT_EN,P-channel corruption error enable" "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled"
newline
rbitfld.long 0x00 8. "Reserved_8,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 7. "PRTCL_EIJT,P-channel protocol error injection" "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active"
newline
bitfld.long 0x00 6. "CRPT_EIJT,P-channel corruption error injection" "0,1"
newline
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 4. "LOCK_EIJT,FSM deadlock error injection" "0,1"
newline
bitfld.long 0x00 3. "PRTCL_CLR,P-channel protocol error clear" "0,1"
newline
bitfld.long 0x00 2. "CRPT_CLR,P-channel corruption error clear" "0,1"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "LOCK_CLR,FSM deadlock error clear" "0,1"
group.long 0x450++0x03
line.long 0x00 "PDENYSTSRCL3_CLUSTER1,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 23.--31. 1. "Reserved_23,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 22. "DNY_OFF_ON,Indicates whether a denied state transition has occurred by power mode transition from OFF mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 21. "DNY_ON_OFF,Indicates whether a denied state transition has occurred by power mode transition from ON mode to OFF mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 20. "DNY_ON_FUNC,Indicates whether a denied state transition has occurred by power mode transition from ON mode to FUNC_RET mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 19. "DNY_FUNC_ON,Indicates whether a denied state transition has occurred by power mode transition from FUNC_RET mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 18. "DNY_ON_MEM,Indicates whether a denied state transition has occurred by power mode transition from ON mode to MEM_RET mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 17. "DNY_MEM_ON,Indicates whether a denied state transition has occurred by power mode transition from MEM_RET mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 16. "DNY_ON_L3CHG,Indicates whether a denied state transition has occurred by L3 cache partial power mode control" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
hexmask.long.word 0x00 0.--15. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x454++0x03
line.long 0x00 "PDENYINTRCL3_CLUSTER1,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 23.--31. 1. "Reserved_23,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 22. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 21. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 20. "INT_ON_FUNC,Issuing interrupt enable by DNY_ON_FUNC" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 19. "INT_FUNC_ON,Issuing interrupt enable by DNY_FUNC_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 18. "INT_ON_MEM,Issuing interrupt enable by DNY_ON_MEM" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 17. "INT_MEM_ON,Issuing interrupt enable by DNY_MEM_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 16. "INT_ON_L3CHG,Issuing interrupt enable by DNY_ON_L3CHG" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
hexmask.long.word 0x00 0.--15. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x458++0x03
line.long 0x00 "FSMSTSRCL3_CLUSTER1,This register is a 32-bit readable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "STATE_7_0,Indicate current state of Cortex-A55 cluster FSM"
group.long 0x45C++0x03
line.long 0x00 "G2GPRCL3_CLUSTER1,This register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "GPR0_31_0,This fields are allowed to write any values and they don't affect module operation"
group.long 0x460++0x03
line.long 0x00 "SAFECTRLCL3_CLUSTER1,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as H'0000 2"
newline
rbitfld.long 0x00 11. "Reserved_11,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 10. "A2_RTT_MRET,A2 RuntimeTEST using MEM_RET mode enable" "0: A2 RuntimeTEST using MEM_RET mode is disabled,1: A2 RuntimeTEST using MEM_RET mode is enabled"
newline
bitfld.long 0x00 9. "A2_RTT_POFF,A2 RuntimeTEST using Pseudo OFF mode enable" "0: A2 RuntimeTEST using Pseudo OFF mode is..,1: A2 RuntimeTEST using Pseudo OFF mode is enabled"
newline
hexmask.long.byte 0x00 2.--8. 1. "Reserved_2,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A55 clusters are booted" "0: RuntimeTEST is disabled before Cortex-A55,1: RuntimeTEST is enabled before Cortex-A55"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0x46C++0x03
line.long 0x00 "GCNTERRENCL3_CLUSTER1,This register is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 0. "GCNTERREN,Generic Counter error detection enable" "0: Error detection is disabled,1: Error detection is enabled"
group.long 0x470++0x03
line.long 0x00 "CA55BAR3_CLUSTER1,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 10.--31. 1. "BAR_39_18,Cortex-A55 Boot Address for AA32 mode"
newline
rbitfld.long 0x00 5.--9. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 4. "BAREN,BAR enables" "0,1"
newline
rbitfld.long 0x00 0.--3. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x478++0x03
line.long 0x00 "CA55BARP3_CLUSTER1,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 10.--31. 1. "BAR_39_18,Cortex-A55 Boot Address for AA32 mode"
newline
rbitfld.long 0x00 5.--9. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 4. "BAREN,BAR enables" "0,1"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "VLD,CA55BARP valid" "0: CA55BAR is used to define Cortex-A55's Boot,1: CA55BARP is used to define Cortex-A55's Boot"
group.long 0x480++0x03
line.long 0x00 "PWRCTRLCL3_CLUSTER2,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 22.--31. 1. "Reserved_22,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 21. "PCHMRETEN,MEM_RET mode transition enable by P-channel protocol" "0,1"
newline
bitfld.long 0x00 20. "PCHFRETEN,FUNC_RET mode transition enable by P-channel protocol" "0: Power mode transition to FUNC_RET mode is..,1: Power mode transition to FUNC_RET mode is.."
newline
rbitfld.long 0x00 18.--19. "Reserved_18,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 17. "PCHPDNEN,OFF mode transition enable by P-channel protocol" "0,1"
newline
bitfld.long 0x00 16. "PCHWUPEN,ON mode transition enable by P-channel protocol" "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled"
newline
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0x484++0x03
line.long 0x00 "L3CTRLCL3_CLUSTER2,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 19.--31. 1. "Reserved_19,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 16.--18. "L3STS_2_0,Indicates current L3 cache partial power down/up status" "?,1: 1/4 of L3 cache is powered on,2: 1/2 of L3 cache is powered on,3: 3/4 of L3 cache is powered on,4: All L3 cache is powered on,?..."
newline
rbitfld.long 0x00 10.--15. "Reserved_10,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 9. "L3DENY,Indicates whether L3 cache partial power down/up request is denied" "0: request is not denied,1: request is denied"
newline
bitfld.long 0x00 8. "L3ACCEPT,Indicates whether L3 cache partial power down/up request is accepted" "0: request is not accepted,1: request is accepted"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4. "L3REQ,L3 cache partial power down/up request" "0: L3 cache partial power down/up is not requested,1: L3 cache partial power down/up is requested"
newline
rbitfld.long 0x00 3. "Reserved_3,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0.--2. "L3CTRL_2_0,L3 cache partial power down/up control" "0: All L3 cache is power-off or Cluster's power,1: 1/4 of L3 cache is power-on,2: 1/2 of L3 cache is power-on,3: 3/4 of L3 cache is power-on,4: All L3 cache is power-on,?..."
group.long 0x48C++0x03
line.long 0x00 "FSMLOCKRCL3_CLUSTER2,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 16.--31. 1. "CNT_VALUE_15_0,Indicates count value for FSM deadlock error"
newline
rbitfld.long 0x00 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred" "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred"
newline
rbitfld.long 0x00 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred" "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred"
newline
rbitfld.long 0x00 13. "Reserved_13,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred" "0: FSM dead lock has not occurred,1: FSM dead lock has occurred"
newline
bitfld.long 0x00 11. "LOCK_EN,FSM deadlock error enable" "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled"
newline
bitfld.long 0x00 10. "PRTCL_EN,P-channel protocol error enable" "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled"
newline
bitfld.long 0x00 9. "CRPT_EN,P-channel corruption error enable" "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled"
newline
rbitfld.long 0x00 8. "Reserved_8,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 7. "PRTCL_EIJT,P-channel protocol error injection" "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active"
newline
bitfld.long 0x00 6. "CRPT_EIJT,P-channel corruption error injection" "0,1"
newline
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 4. "LOCK_EIJT,FSM deadlock error injection" "0,1"
newline
bitfld.long 0x00 3. "PRTCL_CLR,P-channel protocol error clear" "0,1"
newline
bitfld.long 0x00 2. "CRPT_CLR,P-channel corruption error clear" "0,1"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "LOCK_CLR,FSM deadlock error clear" "0,1"
group.long 0x490++0x03
line.long 0x00 "PDENYSTSRCL3_CLUSTER2,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 23.--31. 1. "Reserved_23,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 22. "DNY_OFF_ON,Indicates whether a denied state transition has occurred by power mode transition from OFF mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 21. "DNY_ON_OFF,Indicates whether a denied state transition has occurred by power mode transition from ON mode to OFF mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 20. "DNY_ON_FUNC,Indicates whether a denied state transition has occurred by power mode transition from ON mode to FUNC_RET mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 19. "DNY_FUNC_ON,Indicates whether a denied state transition has occurred by power mode transition from FUNC_RET mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 18. "DNY_ON_MEM,Indicates whether a denied state transition has occurred by power mode transition from ON mode to MEM_RET mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 17. "DNY_MEM_ON,Indicates whether a denied state transition has occurred by power mode transition from MEM_RET mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 16. "DNY_ON_L3CHG,Indicates whether a denied state transition has occurred by L3 cache partial power mode control" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
hexmask.long.word 0x00 0.--15. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x494++0x03
line.long 0x00 "PDENYINTRCL3_CLUSTER2,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 23.--31. 1. "Reserved_23,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 22. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 21. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 20. "INT_ON_FUNC,Issuing interrupt enable by DNY_ON_FUNC" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 19. "INT_FUNC_ON,Issuing interrupt enable by DNY_FUNC_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 18. "INT_ON_MEM,Issuing interrupt enable by DNY_ON_MEM" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 17. "INT_MEM_ON,Issuing interrupt enable by DNY_MEM_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 16. "INT_ON_L3CHG,Issuing interrupt enable by DNY_ON_L3CHG" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
hexmask.long.word 0x00 0.--15. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x498++0x03
line.long 0x00 "FSMSTSRCL3_CLUSTER2,This register is a 32-bit readable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "STATE_7_0,Indicate current state of Cortex-A55 cluster FSM"
group.long 0x49C++0x03
line.long 0x00 "G2GPRCL3_CLUSTER2,This register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "GPR0_31_0,This fields are allowed to write any values and they don't affect module operation"
group.long 0x4A0++0x03
line.long 0x00 "SAFECTRLCL3_CLUSTER2,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as H'0000 2"
newline
rbitfld.long 0x00 11. "Reserved_11,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 10. "A2_RTT_MRET,A2 RuntimeTEST using MEM_RET mode enable" "0: A2 RuntimeTEST using MEM_RET mode is disabled,1: A2 RuntimeTEST using MEM_RET mode is enabled"
newline
bitfld.long 0x00 9. "A2_RTT_POFF,A2 RuntimeTEST using Pseudo OFF mode enable" "0: A2 RuntimeTEST using Pseudo OFF mode is..,1: A2 RuntimeTEST using Pseudo OFF mode is enabled"
newline
hexmask.long.byte 0x00 2.--8. 1. "Reserved_2,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A55 clusters are booted" "0: RuntimeTEST is disabled before Cortex-A55,1: RuntimeTEST is enabled before Cortex-A55"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0x4AC++0x03
line.long 0x00 "GCNTERRENCL3_CLUSTER2,This register is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 0. "GCNTERREN,Generic Counter error detection enable" "0: Error detection is disabled,1: Error detection is enabled"
group.long 0x4B0++0x03
line.long 0x00 "CA55BAR3_CLUSTER2,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 10.--31. 1. "BAR_39_18,Cortex-A55 Boot Address for AA32 mode"
newline
rbitfld.long 0x00 5.--9. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 4. "BAREN,BAR enables" "0,1"
newline
rbitfld.long 0x00 0.--3. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4B8++0x03
line.long 0x00 "CA55BARP3_CLUSTER2,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 10.--31. 1. "BAR_39_18,Cortex-A55 Boot Address for AA32 mode"
newline
rbitfld.long 0x00 5.--9. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 4. "BAREN,BAR enables" "0,1"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "VLD,CA55BARP valid" "0: CA55BAR is used to define Cortex-A55's Boot,1: CA55BARP is used to define Cortex-A55's Boot"
group.long 0x4C0++0x03
line.long 0x00 "PWRCTRLCL3_CLUSTER3,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 22.--31. 1. "Reserved_22,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 21. "PCHMRETEN,MEM_RET mode transition enable by P-channel protocol" "0,1"
newline
bitfld.long 0x00 20. "PCHFRETEN,FUNC_RET mode transition enable by P-channel protocol" "0: Power mode transition to FUNC_RET mode is..,1: Power mode transition to FUNC_RET mode is.."
newline
rbitfld.long 0x00 18.--19. "Reserved_18,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 17. "PCHPDNEN,OFF mode transition enable by P-channel protocol" "0,1"
newline
bitfld.long 0x00 16. "PCHWUPEN,ON mode transition enable by P-channel protocol" "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled"
newline
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0x4C4++0x03
line.long 0x00 "L3CTRLCL3_CLUSTER3,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 19.--31. 1. "Reserved_19,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 16.--18. "L3STS_2_0,Indicates current L3 cache partial power down/up status" "?,1: 1/4 of L3 cache is powered on,2: 1/2 of L3 cache is powered on,3: 3/4 of L3 cache is powered on,4: All L3 cache is powered on,?..."
newline
rbitfld.long 0x00 10.--15. "Reserved_10,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 9. "L3DENY,Indicates whether L3 cache partial power down/up request is denied" "0: request is not denied,1: request is denied"
newline
bitfld.long 0x00 8. "L3ACCEPT,Indicates whether L3 cache partial power down/up request is accepted" "0: request is not accepted,1: request is accepted"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4. "L3REQ,L3 cache partial power down/up request" "0: L3 cache partial power down/up is not requested,1: L3 cache partial power down/up is requested"
newline
rbitfld.long 0x00 3. "Reserved_3,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0.--2. "L3CTRL_2_0,L3 cache partial power down/up control" "0: All L3 cache is power-off or Cluster's power,1: 1/4 of L3 cache is power-on,2: 1/2 of L3 cache is power-on,3: 3/4 of L3 cache is power-on,4: All L3 cache is power-on,?..."
group.long 0x4CC++0x03
line.long 0x00 "FSMLOCKRCL3_CLUSTER3,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 16.--31. 1. "CNT_VALUE_15_0,Indicates count value for FSM deadlock error"
newline
rbitfld.long 0x00 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred" "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred"
newline
rbitfld.long 0x00 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred" "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred"
newline
rbitfld.long 0x00 13. "Reserved_13,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred" "0: FSM dead lock has not occurred,1: FSM dead lock has occurred"
newline
bitfld.long 0x00 11. "LOCK_EN,FSM deadlock error enable" "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled"
newline
bitfld.long 0x00 10. "PRTCL_EN,P-channel protocol error enable" "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled"
newline
bitfld.long 0x00 9. "CRPT_EN,P-channel corruption error enable" "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled"
newline
rbitfld.long 0x00 8. "Reserved_8,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 7. "PRTCL_EIJT,P-channel protocol error injection" "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active"
newline
bitfld.long 0x00 6. "CRPT_EIJT,P-channel corruption error injection" "0,1"
newline
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 4. "LOCK_EIJT,FSM deadlock error injection" "0,1"
newline
bitfld.long 0x00 3. "PRTCL_CLR,P-channel protocol error clear" "0,1"
newline
bitfld.long 0x00 2. "CRPT_CLR,P-channel corruption error clear" "0,1"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "LOCK_CLR,FSM deadlock error clear" "0,1"
group.long 0x4D0++0x03
line.long 0x00 "PDENYSTSRCL3_CLUSTER3,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 23.--31. 1. "Reserved_23,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 22. "DNY_OFF_ON,Indicates whether a denied state transition has occurred by power mode transition from OFF mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 21. "DNY_ON_OFF,Indicates whether a denied state transition has occurred by power mode transition from ON mode to OFF mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 20. "DNY_ON_FUNC,Indicates whether a denied state transition has occurred by power mode transition from ON mode to FUNC_RET mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 19. "DNY_FUNC_ON,Indicates whether a denied state transition has occurred by power mode transition from FUNC_RET mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 18. "DNY_ON_MEM,Indicates whether a denied state transition has occurred by power mode transition from ON mode to MEM_RET mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 17. "DNY_MEM_ON,Indicates whether a denied state transition has occurred by power mode transition from MEM_RET mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 16. "DNY_ON_L3CHG,Indicates whether a denied state transition has occurred by L3 cache partial power mode control" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
hexmask.long.word 0x00 0.--15. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x4D4++0x03
line.long 0x00 "PDENYINTRCL3_CLUSTER3,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 23.--31. 1. "Reserved_23,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 22. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 21. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 20. "INT_ON_FUNC,Issuing interrupt enable by DNY_ON_FUNC" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 19. "INT_FUNC_ON,Issuing interrupt enable by DNY_FUNC_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 18. "INT_ON_MEM,Issuing interrupt enable by DNY_ON_MEM" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 17. "INT_MEM_ON,Issuing interrupt enable by DNY_MEM_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 16. "INT_ON_L3CHG,Issuing interrupt enable by DNY_ON_L3CHG" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
hexmask.long.word 0x00 0.--15. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x4D8++0x03
line.long 0x00 "FSMSTSRCL3_CLUSTER3,This register is a 32-bit readable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "STATE_7_0,Indicate current state of Cortex-A55 cluster FSM"
group.long 0x4DC++0x03
line.long 0x00 "G2GPRCL3_CLUSTER3,This register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "GPR0_31_0,This fields are allowed to write any values and they don't affect module operation"
group.long 0x4E0++0x03
line.long 0x00 "SAFECTRLCL3_CLUSTER3,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as H'0000 2"
newline
rbitfld.long 0x00 11. "Reserved_11,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 10. "A2_RTT_MRET,A2 RuntimeTEST using MEM_RET mode enable" "0: A2 RuntimeTEST using MEM_RET mode is disabled,1: A2 RuntimeTEST using MEM_RET mode is enabled"
newline
bitfld.long 0x00 9. "A2_RTT_POFF,A2 RuntimeTEST using Pseudo OFF mode enable" "0: A2 RuntimeTEST using Pseudo OFF mode is..,1: A2 RuntimeTEST using Pseudo OFF mode is enabled"
newline
hexmask.long.byte 0x00 2.--8. 1. "Reserved_2,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A55 clusters are booted" "0: RuntimeTEST is disabled before Cortex-A55,1: RuntimeTEST is enabled before Cortex-A55"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0x4EC++0x03
line.long 0x00 "GCNTERRENCL3_CLUSTER3,This register is a 32-bit readable/writable register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 0. "GCNTERREN,Generic Counter error detection enable" "0: Error detection is disabled,1: Error detection is enabled"
group.long 0x4F0++0x03
line.long 0x00 "CA55BAR3_CLUSTER3,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 10.--31. 1. "BAR_39_18,Cortex-A55 Boot Address for AA32 mode"
newline
rbitfld.long 0x00 5.--9. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 4. "BAREN,BAR enables" "0,1"
newline
rbitfld.long 0x00 0.--3. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4F8++0x03
line.long 0x00 "CA55BARP3_CLUSTER3,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 10.--31. 1. "BAR_39_18,Cortex-A55 Boot Address for AA32 mode"
newline
rbitfld.long 0x00 5.--9. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 4. "BAREN,BAR enables" "0,1"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "VLD,CA55BARP valid" "0: CA55BAR is used to define Cortex-A55's Boot,1: CA55BARP is used to define Cortex-A55's Boot"
group.long 0x800++0x03
line.long 0x00 "PWRCTRLC3_CORE0,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 19.--31. 1. "Reserved_19,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol" "0: Power mode transition to OFF_EMU mode is..,1: Power mode transition to OFF_EMU mode is.."
newline
bitfld.long 0x00 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled"
newline
bitfld.long 0x00 16. "PCHWUPEN,ON mode transition enable by P-channel protocol" "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled"
newline
hexmask.long.word 0x00 6.--15. 1. "Reserved_6,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 5. "DWUP_EN,This bit enables wakeup request from Debugger" "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled"
newline
bitfld.long 0x00 4. "IWUP_EN,This bit enables wakeup request from INTC-AP" "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "WUP_REQ,Wake up request" "0: Power on is not requested,1: Power on is requested"
group.long 0x80C++0x03
line.long 0x00 "FSMLOCKRC3_CORE0,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 16.--31. 1. "CNT_VALUE_15_0,Indicates count value for FSM deadlock error"
newline
rbitfld.long 0x00 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred" "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred"
newline
rbitfld.long 0x00 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred" "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred"
newline
rbitfld.long 0x00 13. "Reserved_13,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred" "0: FSM dead lock has not occurred,1: FSM dead lock has occurred"
newline
bitfld.long 0x00 11. "LOCK_EN,FSM deadlock error enable" "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled"
newline
bitfld.long 0x00 10. "PRTCL_EN,P-channel protocol error enable" "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled"
newline
bitfld.long 0x00 9. "CRPT_EN,P-channel corruption error enable" "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled"
newline
rbitfld.long 0x00 8. "Reserved_8,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 7. "PRTCL_EIJT,P-channel protocol error injection" "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active"
newline
bitfld.long 0x00 6. "CRPT_EIJT,P-channel corruption error injection" "0,1"
newline
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 4. "LOCK_EIJT,FSM deadlock error injection" "0,1"
newline
bitfld.long 0x00 3. "PRTCL_CLR,P-channel protocol error clear" "0,1"
newline
bitfld.long 0x00 2. "CRPT_CLR,P-channel corruption error clear" "0,1"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "LOCK_CLR,FSM deadlock error clear" "0,1"
group.long 0x810++0x03
line.long 0x00 "PDENYSTSRC3_CORE0,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
rbitfld.long 0x00 4.--5. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0x814++0x03
line.long 0x00 "PDENYINTRC3_CORE0,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
rbitfld.long 0x00 4.--5. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0x818++0x03
line.long 0x00 "FSMSTSRC3_CORE0,This register is a 32-bit readable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "STATE_7_0,Indicate current state of A3 FSM"
group.long 0x81C++0x03
line.long 0x00 "G2GPRC3_CORE0,This register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "GPR0_31_0,This fields are allowed to write any values and they don't affect module operation"
group.long 0x820++0x03
line.long 0x00 "SAFECTRLC3_CORE0,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are always read as H'0000 0"
newline
bitfld.long 0x00 13. "DBGEN_PPDN,When Cortex-A55 is in debug mode Cortex-A55 core is goes to OFF_EMU mode instead of OFF mode" "0: Cortex-A55 goes to OFF mode,1: Cortex-A55 goes to OFF_EMU mode"
newline
hexmask.long.byte 0x00 5.--12. 1. "Reserved_5,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4. "A1_RTT,A1 RuntimeTEST enable" "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A55 cores are booted" "0: RuntimeTEST is disabled before Cortex-A55 cores,1: RuntimeTEST is enabled before Cortex-A55 cores"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0x830++0x03
line.long 0x00 "RVBARLC3_CORE0,This register is a 32-bit readable/writable register"
hexmask.long 0x00 2.--31. 1. "RVBAR_31_2,These bits indicate RVBARADDR[31:2]"
newline
rbitfld.long 0x00 0.--1. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3"
group.long 0x834++0x03
line.long 0x00 "RVBARHC3_CORE0,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--11. 1. "RVBAR_43_32,These bits indicate RVBARADDR[43:32]"
group.long 0x838++0x03
line.long 0x00 "RVBARPLC3_CORE0,This register is a 32-bit readable/writable register"
hexmask.long 0x00 2.--31. 1. "RVBARP_31_2,These bits indicate RVBARADDR[31:2]"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "VLD,RVBARP valid" "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR"
group.long 0x83C++0x03
line.long 0x00 "RVBARPHC3_CORE0,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--11. 1. "RVBARP_43_32,These bits indicate RVBARADDR[43:32]"
group.long 0x840++0x03
line.long 0x00 "PWRCTRLC3_CORE1,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 19.--31. 1. "Reserved_19,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol" "0: Power mode transition to OFF_EMU mode is..,1: Power mode transition to OFF_EMU mode is.."
newline
bitfld.long 0x00 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled"
newline
bitfld.long 0x00 16. "PCHWUPEN,ON mode transition enable by P-channel protocol" "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled"
newline
hexmask.long.word 0x00 6.--15. 1. "Reserved_6,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 5. "DWUP_EN,This bit enables wakeup request from Debugger" "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled"
newline
bitfld.long 0x00 4. "IWUP_EN,This bit enables wakeup request from INTC-AP" "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "WUP_REQ,Wake up request" "0: Power on is not requested,1: Power on is requested"
group.long 0x84C++0x03
line.long 0x00 "FSMLOCKRC3_CORE1,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 16.--31. 1. "CNT_VALUE_15_0,Indicates count value for FSM deadlock error"
newline
rbitfld.long 0x00 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred" "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred"
newline
rbitfld.long 0x00 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred" "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred"
newline
rbitfld.long 0x00 13. "Reserved_13,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred" "0: FSM dead lock has not occurred,1: FSM dead lock has occurred"
newline
bitfld.long 0x00 11. "LOCK_EN,FSM deadlock error enable" "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled"
newline
bitfld.long 0x00 10. "PRTCL_EN,P-channel protocol error enable" "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled"
newline
bitfld.long 0x00 9. "CRPT_EN,P-channel corruption error enable" "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled"
newline
rbitfld.long 0x00 8. "Reserved_8,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 7. "PRTCL_EIJT,P-channel protocol error injection" "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active"
newline
bitfld.long 0x00 6. "CRPT_EIJT,P-channel corruption error injection" "0,1"
newline
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 4. "LOCK_EIJT,FSM deadlock error injection" "0,1"
newline
bitfld.long 0x00 3. "PRTCL_CLR,P-channel protocol error clear" "0,1"
newline
bitfld.long 0x00 2. "CRPT_CLR,P-channel corruption error clear" "0,1"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "LOCK_CLR,FSM deadlock error clear" "0,1"
group.long 0x850++0x03
line.long 0x00 "PDENYSTSRC3_CORE1,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
rbitfld.long 0x00 4.--5. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0x854++0x03
line.long 0x00 "PDENYINTRC3_CORE1,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
rbitfld.long 0x00 4.--5. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0x858++0x03
line.long 0x00 "FSMSTSRC3_CORE1,This register is a 32-bit readable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "STATE_7_0,Indicate current state of A3 FSM"
group.long 0x85C++0x03
line.long 0x00 "G2GPRC3_CORE1,This register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "GPR0_31_0,This fields are allowed to write any values and they don't affect module operation"
group.long 0x860++0x03
line.long 0x00 "SAFECTRLC3_CORE1,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are always read as H'0000 0"
newline
bitfld.long 0x00 13. "DBGEN_PPDN,When Cortex-A55 is in debug mode Cortex-A55 core is goes to OFF_EMU mode instead of OFF mode" "0: Cortex-A55 goes to OFF mode,1: Cortex-A55 goes to OFF_EMU mode"
newline
hexmask.long.byte 0x00 5.--12. 1. "Reserved_5,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4. "A1_RTT,A1 RuntimeTEST enable" "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A55 cores are booted" "0: RuntimeTEST is disabled before Cortex-A55 cores,1: RuntimeTEST is enabled before Cortex-A55 cores"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0x870++0x03
line.long 0x00 "RVBARLC3_CORE1,This register is a 32-bit readable/writable register"
hexmask.long 0x00 2.--31. 1. "RVBAR_31_2,These bits indicate RVBARADDR[31:2]"
newline
rbitfld.long 0x00 0.--1. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3"
group.long 0x874++0x03
line.long 0x00 "RVBARHC3_CORE1,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--11. 1. "RVBAR_43_32,These bits indicate RVBARADDR[43:32]"
group.long 0x878++0x03
line.long 0x00 "RVBARPLC3_CORE1,This register is a 32-bit readable/writable register"
hexmask.long 0x00 2.--31. 1. "RVBARP_31_2,These bits indicate RVBARADDR[31:2]"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "VLD,RVBARP valid" "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR"
group.long 0x87C++0x03
line.long 0x00 "RVBARPHC3_CORE1,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--11. 1. "RVBARP_43_32,These bits indicate RVBARADDR[43:32]"
group.long 0xA00++0x03
line.long 0x00 "PWRCTRLC3_CORE2,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 19.--31. 1. "Reserved_19,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol" "0: Power mode transition to OFF_EMU mode is..,1: Power mode transition to OFF_EMU mode is.."
newline
bitfld.long 0x00 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled"
newline
bitfld.long 0x00 16. "PCHWUPEN,ON mode transition enable by P-channel protocol" "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled"
newline
hexmask.long.word 0x00 6.--15. 1. "Reserved_6,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 5. "DWUP_EN,This bit enables wakeup request from Debugger" "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled"
newline
bitfld.long 0x00 4. "IWUP_EN,This bit enables wakeup request from INTC-AP" "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "WUP_REQ,Wake up request" "0: Power on is not requested,1: Power on is requested"
group.long 0xA0C++0x03
line.long 0x00 "FSMLOCKRC3_CORE2,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 16.--31. 1. "CNT_VALUE_15_0,Indicates count value for FSM deadlock error"
newline
rbitfld.long 0x00 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred" "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred"
newline
rbitfld.long 0x00 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred" "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred"
newline
rbitfld.long 0x00 13. "Reserved_13,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred" "0: FSM dead lock has not occurred,1: FSM dead lock has occurred"
newline
bitfld.long 0x00 11. "LOCK_EN,FSM deadlock error enable" "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled"
newline
bitfld.long 0x00 10. "PRTCL_EN,P-channel protocol error enable" "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled"
newline
bitfld.long 0x00 9. "CRPT_EN,P-channel corruption error enable" "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled"
newline
rbitfld.long 0x00 8. "Reserved_8,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 7. "PRTCL_EIJT,P-channel protocol error injection" "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active"
newline
bitfld.long 0x00 6. "CRPT_EIJT,P-channel corruption error injection" "0,1"
newline
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 4. "LOCK_EIJT,FSM deadlock error injection" "0,1"
newline
bitfld.long 0x00 3. "PRTCL_CLR,P-channel protocol error clear" "0,1"
newline
bitfld.long 0x00 2. "CRPT_CLR,P-channel corruption error clear" "0,1"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "LOCK_CLR,FSM deadlock error clear" "0,1"
group.long 0xA10++0x03
line.long 0x00 "PDENYSTSRC3_CORE2,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
rbitfld.long 0x00 4.--5. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0xA14++0x03
line.long 0x00 "PDENYINTRC3_CORE2,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
rbitfld.long 0x00 4.--5. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0xA18++0x03
line.long 0x00 "FSMSTSRC3_CORE2,This register is a 32-bit readable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "STATE_7_0,Indicate current state of A3 FSM"
group.long 0xA1C++0x03
line.long 0x00 "G2GPRC3_CORE2,This register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "GPR0_31_0,This fields are allowed to write any values and they don't affect module operation"
group.long 0xA20++0x03
line.long 0x00 "SAFECTRLC3_CORE2,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are always read as H'0000 0"
newline
bitfld.long 0x00 13. "DBGEN_PPDN,When Cortex-A55 is in debug mode Cortex-A55 core is goes to OFF_EMU mode instead of OFF mode" "0: Cortex-A55 goes to OFF mode,1: Cortex-A55 goes to OFF_EMU mode"
newline
hexmask.long.byte 0x00 5.--12. 1. "Reserved_5,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4. "A1_RTT,A1 RuntimeTEST enable" "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A55 cores are booted" "0: RuntimeTEST is disabled before Cortex-A55 cores,1: RuntimeTEST is enabled before Cortex-A55 cores"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0xA30++0x03
line.long 0x00 "RVBARLC3_CORE2,This register is a 32-bit readable/writable register"
hexmask.long 0x00 2.--31. 1. "RVBAR_31_2,These bits indicate RVBARADDR[31:2]"
newline
rbitfld.long 0x00 0.--1. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3"
group.long 0xA34++0x03
line.long 0x00 "RVBARHC3_CORE2,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--11. 1. "RVBAR_43_32,These bits indicate RVBARADDR[43:32]"
group.long 0xA38++0x03
line.long 0x00 "RVBARPLC3_CORE2,This register is a 32-bit readable/writable register"
hexmask.long 0x00 2.--31. 1. "RVBARP_31_2,These bits indicate RVBARADDR[31:2]"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "VLD,RVBARP valid" "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR"
group.long 0xA3C++0x03
line.long 0x00 "RVBARPHC3_CORE2,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--11. 1. "RVBARP_43_32,These bits indicate RVBARADDR[43:32]"
group.long 0xA40++0x03
line.long 0x00 "PWRCTRLC3_CORE3,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 19.--31. 1. "Reserved_19,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol" "0: Power mode transition to OFF_EMU mode is..,1: Power mode transition to OFF_EMU mode is.."
newline
bitfld.long 0x00 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled"
newline
bitfld.long 0x00 16. "PCHWUPEN,ON mode transition enable by P-channel protocol" "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled"
newline
hexmask.long.word 0x00 6.--15. 1. "Reserved_6,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 5. "DWUP_EN,This bit enables wakeup request from Debugger" "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled"
newline
bitfld.long 0x00 4. "IWUP_EN,This bit enables wakeup request from INTC-AP" "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "WUP_REQ,Wake up request" "0: Power on is not requested,1: Power on is requested"
group.long 0xA4C++0x03
line.long 0x00 "FSMLOCKRC3_CORE3,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 16.--31. 1. "CNT_VALUE_15_0,Indicates count value for FSM deadlock error"
newline
rbitfld.long 0x00 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred" "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred"
newline
rbitfld.long 0x00 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred" "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred"
newline
rbitfld.long 0x00 13. "Reserved_13,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred" "0: FSM dead lock has not occurred,1: FSM dead lock has occurred"
newline
bitfld.long 0x00 11. "LOCK_EN,FSM deadlock error enable" "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled"
newline
bitfld.long 0x00 10. "PRTCL_EN,P-channel protocol error enable" "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled"
newline
bitfld.long 0x00 9. "CRPT_EN,P-channel corruption error enable" "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled"
newline
rbitfld.long 0x00 8. "Reserved_8,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 7. "PRTCL_EIJT,P-channel protocol error injection" "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active"
newline
bitfld.long 0x00 6. "CRPT_EIJT,P-channel corruption error injection" "0,1"
newline
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 4. "LOCK_EIJT,FSM deadlock error injection" "0,1"
newline
bitfld.long 0x00 3. "PRTCL_CLR,P-channel protocol error clear" "0,1"
newline
bitfld.long 0x00 2. "CRPT_CLR,P-channel corruption error clear" "0,1"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "LOCK_CLR,FSM deadlock error clear" "0,1"
group.long 0xA50++0x03
line.long 0x00 "PDENYSTSRC3_CORE3,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
rbitfld.long 0x00 4.--5. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0xA54++0x03
line.long 0x00 "PDENYINTRC3_CORE3,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
rbitfld.long 0x00 4.--5. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0xA58++0x03
line.long 0x00 "FSMSTSRC3_CORE3,This register is a 32-bit readable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "STATE_7_0,Indicate current state of A3 FSM"
group.long 0xA5C++0x03
line.long 0x00 "G2GPRC3_CORE3,This register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "GPR0_31_0,This fields are allowed to write any values and they don't affect module operation"
group.long 0xA60++0x03
line.long 0x00 "SAFECTRLC3_CORE3,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are always read as H'0000 0"
newline
bitfld.long 0x00 13. "DBGEN_PPDN,When Cortex-A55 is in debug mode Cortex-A55 core is goes to OFF_EMU mode instead of OFF mode" "0: Cortex-A55 goes to OFF mode,1: Cortex-A55 goes to OFF_EMU mode"
newline
hexmask.long.byte 0x00 5.--12. 1. "Reserved_5,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4. "A1_RTT,A1 RuntimeTEST enable" "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A55 cores are booted" "0: RuntimeTEST is disabled before Cortex-A55 cores,1: RuntimeTEST is enabled before Cortex-A55 cores"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0xA70++0x03
line.long 0x00 "RVBARLC3_CORE3,This register is a 32-bit readable/writable register"
hexmask.long 0x00 2.--31. 1. "RVBAR_31_2,These bits indicate RVBARADDR[31:2]"
newline
rbitfld.long 0x00 0.--1. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3"
group.long 0xA74++0x03
line.long 0x00 "RVBARHC3_CORE3,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--11. 1. "RVBAR_43_32,These bits indicate RVBARADDR[43:32]"
group.long 0xA78++0x03
line.long 0x00 "RVBARPLC3_CORE3,This register is a 32-bit readable/writable register"
hexmask.long 0x00 2.--31. 1. "RVBARP_31_2,These bits indicate RVBARADDR[31:2]"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "VLD,RVBARP valid" "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR"
group.long 0xA7C++0x03
line.long 0x00 "RVBARPHC3_CORE3,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--11. 1. "RVBARP_43_32,These bits indicate RVBARADDR[43:32]"
group.long 0xC00++0x03
line.long 0x00 "PWRCTRLC3_CORE4,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 19.--31. 1. "Reserved_19,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol" "0: Power mode transition to OFF_EMU mode is..,1: Power mode transition to OFF_EMU mode is.."
newline
bitfld.long 0x00 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled"
newline
bitfld.long 0x00 16. "PCHWUPEN,ON mode transition enable by P-channel protocol" "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled"
newline
hexmask.long.word 0x00 6.--15. 1. "Reserved_6,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 5. "DWUP_EN,This bit enables wakeup request from Debugger" "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled"
newline
bitfld.long 0x00 4. "IWUP_EN,This bit enables wakeup request from INTC-AP" "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "WUP_REQ,Wake up request" "0: Power on is not requested,1: Power on is requested"
group.long 0xC0C++0x03
line.long 0x00 "FSMLOCKRC3_CORE4,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 16.--31. 1. "CNT_VALUE_15_0,Indicates count value for FSM deadlock error"
newline
rbitfld.long 0x00 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred" "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred"
newline
rbitfld.long 0x00 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred" "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred"
newline
rbitfld.long 0x00 13. "Reserved_13,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred" "0: FSM dead lock has not occurred,1: FSM dead lock has occurred"
newline
bitfld.long 0x00 11. "LOCK_EN,FSM deadlock error enable" "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled"
newline
bitfld.long 0x00 10. "PRTCL_EN,P-channel protocol error enable" "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled"
newline
bitfld.long 0x00 9. "CRPT_EN,P-channel corruption error enable" "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled"
newline
rbitfld.long 0x00 8. "Reserved_8,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 7. "PRTCL_EIJT,P-channel protocol error injection" "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active"
newline
bitfld.long 0x00 6. "CRPT_EIJT,P-channel corruption error injection" "0,1"
newline
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 4. "LOCK_EIJT,FSM deadlock error injection" "0,1"
newline
bitfld.long 0x00 3. "PRTCL_CLR,P-channel protocol error clear" "0,1"
newline
bitfld.long 0x00 2. "CRPT_CLR,P-channel corruption error clear" "0,1"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "LOCK_CLR,FSM deadlock error clear" "0,1"
group.long 0xC10++0x03
line.long 0x00 "PDENYSTSRC3_CORE4,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
rbitfld.long 0x00 4.--5. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0xC14++0x03
line.long 0x00 "PDENYINTRC3_CORE4,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
rbitfld.long 0x00 4.--5. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0xC18++0x03
line.long 0x00 "FSMSTSRC3_CORE4,This register is a 32-bit readable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "STATE_7_0,Indicate current state of A3 FSM"
group.long 0xC1C++0x03
line.long 0x00 "G2GPRC3_CORE4,This register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "GPR0_31_0,This fields are allowed to write any values and they don't affect module operation"
group.long 0xC20++0x03
line.long 0x00 "SAFECTRLC3_CORE4,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are always read as H'0000 0"
newline
bitfld.long 0x00 13. "DBGEN_PPDN,When Cortex-A55 is in debug mode Cortex-A55 core is goes to OFF_EMU mode instead of OFF mode" "0: Cortex-A55 goes to OFF mode,1: Cortex-A55 goes to OFF_EMU mode"
newline
hexmask.long.byte 0x00 5.--12. 1. "Reserved_5,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4. "A1_RTT,A1 RuntimeTEST enable" "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A55 cores are booted" "0: RuntimeTEST is disabled before Cortex-A55 cores,1: RuntimeTEST is enabled before Cortex-A55 cores"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0xC30++0x03
line.long 0x00 "RVBARLC3_CORE4,This register is a 32-bit readable/writable register"
hexmask.long 0x00 2.--31. 1. "RVBAR_31_2,These bits indicate RVBARADDR[31:2]"
newline
rbitfld.long 0x00 0.--1. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3"
group.long 0xC34++0x03
line.long 0x00 "RVBARHC3_CORE4,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--11. 1. "RVBAR_43_32,These bits indicate RVBARADDR[43:32]"
group.long 0xC38++0x03
line.long 0x00 "RVBARPLC3_CORE4,This register is a 32-bit readable/writable register"
hexmask.long 0x00 2.--31. 1. "RVBARP_31_2,These bits indicate RVBARADDR[31:2]"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "VLD,RVBARP valid" "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR"
group.long 0xC3C++0x03
line.long 0x00 "RVBARPHC3_CORE4,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--11. 1. "RVBARP_43_32,These bits indicate RVBARADDR[43:32]"
group.long 0xC40++0x03
line.long 0x00 "PWRCTRLC3_CORE5,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 19.--31. 1. "Reserved_19,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol" "0: Power mode transition to OFF_EMU mode is..,1: Power mode transition to OFF_EMU mode is.."
newline
bitfld.long 0x00 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled"
newline
bitfld.long 0x00 16. "PCHWUPEN,ON mode transition enable by P-channel protocol" "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled"
newline
hexmask.long.word 0x00 6.--15. 1. "Reserved_6,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 5. "DWUP_EN,This bit enables wakeup request from Debugger" "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled"
newline
bitfld.long 0x00 4. "IWUP_EN,This bit enables wakeup request from INTC-AP" "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "WUP_REQ,Wake up request" "0: Power on is not requested,1: Power on is requested"
group.long 0xC4C++0x03
line.long 0x00 "FSMLOCKRC3_CORE5,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 16.--31. 1. "CNT_VALUE_15_0,Indicates count value for FSM deadlock error"
newline
rbitfld.long 0x00 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred" "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred"
newline
rbitfld.long 0x00 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred" "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred"
newline
rbitfld.long 0x00 13. "Reserved_13,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred" "0: FSM dead lock has not occurred,1: FSM dead lock has occurred"
newline
bitfld.long 0x00 11. "LOCK_EN,FSM deadlock error enable" "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled"
newline
bitfld.long 0x00 10. "PRTCL_EN,P-channel protocol error enable" "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled"
newline
bitfld.long 0x00 9. "CRPT_EN,P-channel corruption error enable" "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled"
newline
rbitfld.long 0x00 8. "Reserved_8,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 7. "PRTCL_EIJT,P-channel protocol error injection" "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active"
newline
bitfld.long 0x00 6. "CRPT_EIJT,P-channel corruption error injection" "0,1"
newline
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 4. "LOCK_EIJT,FSM deadlock error injection" "0,1"
newline
bitfld.long 0x00 3. "PRTCL_CLR,P-channel protocol error clear" "0,1"
newline
bitfld.long 0x00 2. "CRPT_CLR,P-channel corruption error clear" "0,1"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "LOCK_CLR,FSM deadlock error clear" "0,1"
group.long 0xC50++0x03
line.long 0x00 "PDENYSTSRC3_CORE5,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
rbitfld.long 0x00 4.--5. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0xC54++0x03
line.long 0x00 "PDENYINTRC3_CORE5,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
rbitfld.long 0x00 4.--5. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0xC58++0x03
line.long 0x00 "FSMSTSRC3_CORE5,This register is a 32-bit readable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "STATE_7_0,Indicate current state of A3 FSM"
group.long 0xC5C++0x03
line.long 0x00 "G2GPRC3_CORE5,This register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "GPR0_31_0,This fields are allowed to write any values and they don't affect module operation"
group.long 0xC60++0x03
line.long 0x00 "SAFECTRLC3_CORE5,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are always read as H'0000 0"
newline
bitfld.long 0x00 13. "DBGEN_PPDN,When Cortex-A55 is in debug mode Cortex-A55 core is goes to OFF_EMU mode instead of OFF mode" "0: Cortex-A55 goes to OFF mode,1: Cortex-A55 goes to OFF_EMU mode"
newline
hexmask.long.byte 0x00 5.--12. 1. "Reserved_5,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4. "A1_RTT,A1 RuntimeTEST enable" "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A55 cores are booted" "0: RuntimeTEST is disabled before Cortex-A55 cores,1: RuntimeTEST is enabled before Cortex-A55 cores"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0xC70++0x03
line.long 0x00 "RVBARLC3_CORE5,This register is a 32-bit readable/writable register"
hexmask.long 0x00 2.--31. 1. "RVBAR_31_2,These bits indicate RVBARADDR[31:2]"
newline
rbitfld.long 0x00 0.--1. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3"
group.long 0xC74++0x03
line.long 0x00 "RVBARHC3_CORE5,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--11. 1. "RVBAR_43_32,These bits indicate RVBARADDR[43:32]"
group.long 0xC78++0x03
line.long 0x00 "RVBARPLC3_CORE5,This register is a 32-bit readable/writable register"
hexmask.long 0x00 2.--31. 1. "RVBARP_31_2,These bits indicate RVBARADDR[31:2]"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "VLD,RVBARP valid" "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR"
group.long 0xC7C++0x03
line.long 0x00 "RVBARPHC3_CORE5,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--11. 1. "RVBARP_43_32,These bits indicate RVBARADDR[43:32]"
group.long 0xE00++0x03
line.long 0x00 "PWRCTRLC3_CORE6,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 19.--31. 1. "Reserved_19,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol" "0: Power mode transition to OFF_EMU mode is..,1: Power mode transition to OFF_EMU mode is.."
newline
bitfld.long 0x00 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled"
newline
bitfld.long 0x00 16. "PCHWUPEN,ON mode transition enable by P-channel protocol" "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled"
newline
hexmask.long.word 0x00 6.--15. 1. "Reserved_6,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 5. "DWUP_EN,This bit enables wakeup request from Debugger" "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled"
newline
bitfld.long 0x00 4. "IWUP_EN,This bit enables wakeup request from INTC-AP" "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "WUP_REQ,Wake up request" "0: Power on is not requested,1: Power on is requested"
group.long 0xE0C++0x03
line.long 0x00 "FSMLOCKRC3_CORE6,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 16.--31. 1. "CNT_VALUE_15_0,Indicates count value for FSM deadlock error"
newline
rbitfld.long 0x00 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred" "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred"
newline
rbitfld.long 0x00 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred" "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred"
newline
rbitfld.long 0x00 13. "Reserved_13,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred" "0: FSM dead lock has not occurred,1: FSM dead lock has occurred"
newline
bitfld.long 0x00 11. "LOCK_EN,FSM deadlock error enable" "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled"
newline
bitfld.long 0x00 10. "PRTCL_EN,P-channel protocol error enable" "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled"
newline
bitfld.long 0x00 9. "CRPT_EN,P-channel corruption error enable" "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled"
newline
rbitfld.long 0x00 8. "Reserved_8,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 7. "PRTCL_EIJT,P-channel protocol error injection" "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active"
newline
bitfld.long 0x00 6. "CRPT_EIJT,P-channel corruption error injection" "0,1"
newline
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 4. "LOCK_EIJT,FSM deadlock error injection" "0,1"
newline
bitfld.long 0x00 3. "PRTCL_CLR,P-channel protocol error clear" "0,1"
newline
bitfld.long 0x00 2. "CRPT_CLR,P-channel corruption error clear" "0,1"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "LOCK_CLR,FSM deadlock error clear" "0,1"
group.long 0xE10++0x03
line.long 0x00 "PDENYSTSRC3_CORE6,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
rbitfld.long 0x00 4.--5. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0xE14++0x03
line.long 0x00 "PDENYINTRC3_CORE6,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
rbitfld.long 0x00 4.--5. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0xE18++0x03
line.long 0x00 "FSMSTSRC3_CORE6,This register is a 32-bit readable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "STATE_7_0,Indicate current state of A3 FSM"
group.long 0xE1C++0x03
line.long 0x00 "G2GPRC3_CORE6,This register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "GPR0_31_0,This fields are allowed to write any values and they don't affect module operation"
group.long 0xE20++0x03
line.long 0x00 "SAFECTRLC3_CORE6,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are always read as H'0000 0"
newline
bitfld.long 0x00 13. "DBGEN_PPDN,When Cortex-A55 is in debug mode Cortex-A55 core is goes to OFF_EMU mode instead of OFF mode" "0: Cortex-A55 goes to OFF mode,1: Cortex-A55 goes to OFF_EMU mode"
newline
hexmask.long.byte 0x00 5.--12. 1. "Reserved_5,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4. "A1_RTT,A1 RuntimeTEST enable" "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A55 cores are booted" "0: RuntimeTEST is disabled before Cortex-A55 cores,1: RuntimeTEST is enabled before Cortex-A55 cores"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0xE30++0x03
line.long 0x00 "RVBARLC3_CORE6,This register is a 32-bit readable/writable register"
hexmask.long 0x00 2.--31. 1. "RVBAR_31_2,These bits indicate RVBARADDR[31:2]"
newline
rbitfld.long 0x00 0.--1. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3"
group.long 0xE34++0x03
line.long 0x00 "RVBARHC3_CORE6,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--11. 1. "RVBAR_43_32,These bits indicate RVBARADDR[43:32]"
group.long 0xE38++0x03
line.long 0x00 "RVBARPLC3_CORE6,This register is a 32-bit readable/writable register"
hexmask.long 0x00 2.--31. 1. "RVBARP_31_2,These bits indicate RVBARADDR[31:2]"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "VLD,RVBARP valid" "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR"
group.long 0xE3C++0x03
line.long 0x00 "RVBARPHC3_CORE6,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--11. 1. "RVBARP_43_32,These bits indicate RVBARADDR[43:32]"
group.long 0xE40++0x03
line.long 0x00 "PWRCTRLC3_CORE7,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 19.--31. 1. "Reserved_19,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol" "0: Power mode transition to OFF_EMU mode is..,1: Power mode transition to OFF_EMU mode is.."
newline
bitfld.long 0x00 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled"
newline
bitfld.long 0x00 16. "PCHWUPEN,ON mode transition enable by P-channel protocol" "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled"
newline
hexmask.long.word 0x00 6.--15. 1. "Reserved_6,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 5. "DWUP_EN,This bit enables wakeup request from Debugger" "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled"
newline
bitfld.long 0x00 4. "IWUP_EN,This bit enables wakeup request from INTC-AP" "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "WUP_REQ,Wake up request" "0: Power on is not requested,1: Power on is requested"
group.long 0xE4C++0x03
line.long 0x00 "FSMLOCKRC3_CORE7,This register is a 32-bit readable/writable register"
hexmask.long.word 0x00 16.--31. 1. "CNT_VALUE_15_0,Indicates count value for FSM deadlock error"
newline
rbitfld.long 0x00 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred" "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred"
newline
rbitfld.long 0x00 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred" "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred"
newline
rbitfld.long 0x00 13. "Reserved_13,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred" "0: FSM dead lock has not occurred,1: FSM dead lock has occurred"
newline
bitfld.long 0x00 11. "LOCK_EN,FSM deadlock error enable" "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled"
newline
bitfld.long 0x00 10. "PRTCL_EN,P-channel protocol error enable" "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled"
newline
bitfld.long 0x00 9. "CRPT_EN,P-channel corruption error enable" "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled"
newline
rbitfld.long 0x00 8. "Reserved_8,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 7. "PRTCL_EIJT,P-channel protocol error injection" "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active"
newline
bitfld.long 0x00 6. "CRPT_EIJT,P-channel corruption error injection" "0,1"
newline
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 4. "LOCK_EIJT,FSM deadlock error injection" "0,1"
newline
bitfld.long 0x00 3. "PRTCL_CLR,P-channel protocol error clear" "0,1"
newline
bitfld.long 0x00 2. "CRPT_CLR,P-channel corruption error clear" "0,1"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "LOCK_CLR,FSM deadlock error clear" "0,1"
group.long 0xE50++0x03
line.long 0x00 "PDENYSTSRC3_CORE7,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
rbitfld.long 0x00 4.--5. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
bitfld.long 0x00 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode" "0: A denied state transition has not occurred,1: A denied state transition has occurred"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0xE54++0x03
line.long 0x00 "PDENYINTRC3_CORE7,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
rbitfld.long 0x00 4.--5. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
bitfld.long 0x00 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON" "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0xE58++0x03
line.long 0x00 "FSMSTSRC3_CORE7,This register is a 32-bit readable register"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "STATE_7_0,Indicate current state of A3 FSM"
group.long 0xE5C++0x03
line.long 0x00 "G2GPRC3_CORE7,This register is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "GPR0_31_0,This fields are allowed to write any values and they don't affect module operation"
group.long 0xE60++0x03
line.long 0x00 "SAFECTRLC3_CORE7,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are always read as H'0000 0"
newline
bitfld.long 0x00 13. "DBGEN_PPDN,When Cortex-A55 is in debug mode Cortex-A55 core is goes to OFF_EMU mode instead of OFF mode" "0: Cortex-A55 goes to OFF mode,1: Cortex-A55 goes to OFF_EMU mode"
newline
hexmask.long.byte 0x00 5.--12. 1. "Reserved_5,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4. "A1_RTT,A1 RuntimeTEST enable" "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A55 cores are booted" "0: RuntimeTEST is disabled before Cortex-A55 cores,1: RuntimeTEST is enabled before Cortex-A55 cores"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0xE70++0x03
line.long 0x00 "RVBARLC3_CORE7,This register is a 32-bit readable/writable register"
hexmask.long 0x00 2.--31. 1. "RVBAR_31_2,These bits indicate RVBARADDR[31:2]"
newline
rbitfld.long 0x00 0.--1. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3"
group.long 0xE74++0x03
line.long 0x00 "RVBARHC3_CORE7,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--11. 1. "RVBAR_43_32,These bits indicate RVBARADDR[43:32]"
group.long 0xE78++0x03
line.long 0x00 "RVBARPLC3_CORE7,This register is a 32-bit readable/writable register"
hexmask.long 0x00 2.--31. 1. "RVBARP_31_2,These bits indicate RVBARADDR[31:2]"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0. "VLD,RVBARP valid" "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR"
group.long 0xE7C++0x03
line.long 0x00 "RVBARPHC3_CORE7,This register is a 32-bit readable/writable register"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--11. 1. "RVBARP_43_32,These bits indicate RVBARADDR[43:32]"
tree.end
tree.end
tree "SYSC"
tree "SYSC_INST_0"
base ad:0xE6180000
group.long 0x00++0x03
line.long 0x00 "SYSCSR0,Refer to bit assignment table above"
hexmask.long 0x00 2.--31. 1. "Reserved_2,Reserved *2"
rbitfld.long 0x00 0.--1. "BUSY_1_0,Indicates whether the SYSC is processing Power-ON or Power-OFF sequence" "0: Processing Power-ON or OFF sequence,?,?,3: Not processing Power-ON or OFF sequence"
group.long 0x10++0x03
line.long 0x00 "SYSCPTCSR0,Refer to bit assignment table above"
hexmask.long 0x00 3.--31. 1. "Reserved_3,Reserved *2"
bitfld.long 0x00 2. "EIEI,Write access protection Error Interrupt request Enable for INTC" "0: Disable error interrupt request for INTC,1: Enable error interrupt request for INTC"
newline
bitfld.long 0x00 1. "EIE,Write access protection Error Interrupt request Enable for ECM (FuSa)" "0: Disable error interrupt request for ECM,1: Enable error interrupt request for ECM"
bitfld.long 0x00 0. "ERR,Indicates Write access protection Error status" "0: Not detected Write access protection error,1: Detected Write access protection error"
group.long 0x14++0x03
line.long 0x00 "SYSCPTERADR0,Refer to bit assignment table above"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved *2"
bitfld.long 0x00 16. "CLR,Write access protection error address clear If write 1 ADR is cleared to 0 and the next error address can be hold" "0,1"
newline
hexmask.long.word 0x00 0.--15. 1. "ADR_15_0,First Write access protection error address"
group.long 0x20++0x03
line.long 0x00 "SYSCRDNCSR0,Refer to bit assignment table above"
abitfld.long 0x00 16.--31. "EIE_15_0,HW Redundant Error Interrupt Enable This bit indicates whether the SYSC allows to generate error interrupt to ECM or not when HW Redundant Error is detected" "0x0000=0: Disable Error Interrupt Disable,0x0001=1: Enable Error Interrupt (send error to.."
abitfld.long 0x00 0.--15. "ERR_15_0,HW Redundant Error Status Indicates that HW Redundant Error is detected" "0x0000=0: Not detected HW Redundant Error,0x0001=1: Detected HW Redundant Error If write 1.."
group.long 0x24++0x03
line.long 0x00 "SYSCRDNIR0,Refer to bit assignment table above"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,These bits are always read as 0"
abitfld.long 0x00 0.--15. "ERIN_15_0,Injects HW Redundant Error By setting those bits errors of HW redundant are asserted regardless of violated HW Redundant or not" "0x0000=0: Not-inject HW Redundant Error,0x0001=1: Inject HW Redundant Error"
group.long 0x30++0x03
line.long 0x00 "SYSCAPBACR0,Refer to bit assignment table above"
hexmask.long 0x00 0.--31. 1. "VAL_31_0,APB BUS Access Check Register for FuSa 32 bit Write/Read register T.B.D (0 detail function is not clear)"
group.long 0x800++0x03
line.long 0x00 "SYSCPONSR00,Refer to bit assignment table above"
abitfld.long 0x00 0.--31. "PDR_31_0,Power-ON status for PDR00-31 power domains" "0x00000000=0: non-Power-ON state,0x00000001=1: Power-ON state The read value of.."
group.long 0x804++0x03
line.long 0x00 "SYSCPONSR10,Refer to bit assignment table above"
abitfld.long 0x00 0.--31. "PDR_63_32,Power-ON status for PDR32-63 power domains" "0x00000000=0: non-Power-ON state,0x00000001=1: Power-ON state The read value of.."
group.long 0x808++0x03
line.long 0x00 "SYSCPOFFSR00,Refer to bit assignment table above"
abitfld.long 0x00 0.--31. "PDR_31_0,Power-OFF Status for PDR31-00 power domains" "0x00000000=0: non-Power-OFF state,0x00000001=1: Power-OFF state The read value of.."
group.long 0x80C++0x03
line.long 0x00 "SYSCPOFFSR10,Refer to bit assignment table above"
abitfld.long 0x00 0.--31. "PDR_63_32,Power-OFF Status for PDR63-32 power domains" "0x00000000=0: non-Power-OFF state,0x00000001=1: Power-OFF state The read value of.."
group.long 0x810++0x03
line.long 0x00 "SYSCISCR00,Refer to bit assignment table above"
hexmask.long 0x00 0.--31. 1. "PDR_31_0,Power-ON or OFF process complete interrupt status for PDR00-31 power domains"
group.long 0x814++0x03
line.long 0x00 "SYSCISCR10,Refer to bit assignment table above"
hexmask.long 0x00 0.--31. 1. "PDR_63_32,Power-ON or OFF process complete interrupt status for PDR32-63 power domains"
group.long 0x820++0x03
line.long 0x00 "SYSCIER00,Refer to bit assignment table above"
abitfld.long 0x00 0.--31. "PDR_31_0,Power-ON or OFF process complete interrupt Enable for PDR00-31 power domains" "0x00000000=0: Disable complete interrupt,0x00000001=1: Enable complete interrupt"
group.long 0x824++0x03
line.long 0x00 "SYSCIER10,Refer to bit assignment table above"
abitfld.long 0x00 0.--31. "PDR_63_32,Power-ON or OFF process complete interrupt Enable for PDR32-63 power domains" "0x00000000=0: Disable complete interrupt,0x00000001=1: Enable complete interrupt"
group.long 0x830++0x03
line.long 0x00 "SYSCIMR00,Refer to bit assignment table above"
abitfld.long 0x00 0.--31. "PDR_31_0,Mask complete interrupt request to INTC for PDR00-31 power domains" "0x00000000=0: Not mask complete interrupt request,0x00000001=1: Masks complete interrupt request.."
group.long 0x834++0x03
line.long 0x00 "SYSCIMR10,Refer to bit assignment table above"
abitfld.long 0x00 0.--31. "PDR_63_32,Mask complete interrupt request to INTC for PDR32-63 power domains" "0x00000000=0: Not mask complete interrupt request,0x00000001=1: Masks complete interrupt request.."
group.long 0x860++0x03
line.long 0x00 "SYSCISOEHSR00,Refer to bit assignment table above"
abitfld.long 0x00 0.--31. "PDR_31_0,Isolation Error High Status/Clear" "0x00000000=0: Not isolation Error form High level,0x00000001=1: Isolation Error form High level"
group.long 0x864++0x03
line.long 0x00 "SYSCISOEHSR10,Refer to bit assignment table above"
abitfld.long 0x00 0.--31. "PDR_63_32,Isolation Error High Status/Clear" "0x00000000=0: Not isolation Error form High level,0x00000001=1: Isolation Error form High level"
group.long 0x868++0x03
line.long 0x00 "SYSCISOELSR00,Refer to bit assignment table above"
abitfld.long 0x00 0.--31. "PDR_31_0,Isolation Error Low Status/Clear" "0x00000000=0: Not isolation Error form Low level,0x00000001=1: Isolation Error form Low level"
group.long 0x86C++0x03
line.long 0x00 "SYSCISOELSR10,Refer to bit assignment table above"
abitfld.long 0x00 0.--31. "PDR_63_32,Isolation Error Low Status/Clear" "0x00000000=0: Not isolation Error form Low level,0x00000001=1: Isolation Error form Low level"
group.long 0x870++0x03
line.long 0x00 "SYSCISOEHIR00,Refer to bit assignment table above"
abitfld.long 0x00 0.--31. "PDR_31_0,Isolation Error High Injection for PDR00-31" "0x00000000=0: Not Error Injection,0x00000001=1: Error Injection"
group.long 0x874++0x03
line.long 0x00 "SYSCISOEHIR10,Refer to bit assignment table above"
abitfld.long 0x00 0.--31. "PDR_63_32,Isolation Error High Injection for PDR32-63" "0x00000000=0: Not Error Injection,0x00000001=1: Error Injection"
group.long 0x878++0x03
line.long 0x00 "SYSCISOELIR00,Refer to bit assignment table above"
abitfld.long 0x00 0.--31. "PDR_31_0,Isolation Error Low Injection for PDR00-31" "0x00000000=0: Not Error Injection,0x00000001=1: Error Injection"
group.long 0x87C++0x03
line.long 0x00 "SYSCISOELIR10,Refer to bit assignment table above"
abitfld.long 0x00 0.--31. "PDR_63_32,Isolation Error Low Injection for PDR32-63" "0x00000000=0: Not Error Injection,0x00000001=1: Error Injection"
group.long 0x1000++0x03
line.long 0x00 "PDRSR00,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1004++0x03
line.long 0x00 "PDRONCR00,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1008++0x03
line.long 0x00 "PDROFFCR00,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1040++0x03
line.long 0x00 "PDRSR01,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1044++0x03
line.long 0x00 "PDRONCR01,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1048++0x03
line.long 0x00 "PDROFFCR01,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1080++0x03
line.long 0x00 "PDRSR02,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1084++0x03
line.long 0x00 "PDRONCR02,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1088++0x03
line.long 0x00 "PDROFFCR02,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x10C0++0x03
line.long 0x00 "PDRSR03,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x10C4++0x03
line.long 0x00 "PDRONCR03,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x10C8++0x03
line.long 0x00 "PDROFFCR03,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1100++0x03
line.long 0x00 "PDRSR04,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1104++0x03
line.long 0x00 "PDRONCR04,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1108++0x03
line.long 0x00 "PDROFFCR04,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1140++0x03
line.long 0x00 "PDRSR05,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1144++0x03
line.long 0x00 "PDRONCR05,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1148++0x03
line.long 0x00 "PDROFFCR05,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1180++0x03
line.long 0x00 "PDRSR06,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1184++0x03
line.long 0x00 "PDRONCR06,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1188++0x03
line.long 0x00 "PDROFFCR06,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x11C0++0x03
line.long 0x00 "PDRSR07,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x11C4++0x03
line.long 0x00 "PDRONCR07,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x11C8++0x03
line.long 0x00 "PDROFFCR07,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1200++0x03
line.long 0x00 "PDRSR08,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1204++0x03
line.long 0x00 "PDRONCR08,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1208++0x03
line.long 0x00 "PDROFFCR08,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1240++0x03
line.long 0x00 "PDRSR09,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1244++0x03
line.long 0x00 "PDRONCR09,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1248++0x03
line.long 0x00 "PDROFFCR09,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1280++0x03
line.long 0x00 "PDRSR010,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1284++0x03
line.long 0x00 "PDRONCR010,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1288++0x03
line.long 0x00 "PDROFFCR010,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x12C0++0x03
line.long 0x00 "PDRSR011,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x12C4++0x03
line.long 0x00 "PDRONCR011,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x12C8++0x03
line.long 0x00 "PDROFFCR011,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1300++0x03
line.long 0x00 "PDRSR012,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1304++0x03
line.long 0x00 "PDRONCR012,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1308++0x03
line.long 0x00 "PDROFFCR012,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1340++0x03
line.long 0x00 "PDRSR013,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1344++0x03
line.long 0x00 "PDRONCR013,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1348++0x03
line.long 0x00 "PDROFFCR013,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1380++0x03
line.long 0x00 "PDRSR014,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1384++0x03
line.long 0x00 "PDRONCR014,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1388++0x03
line.long 0x00 "PDROFFCR014,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x13C0++0x03
line.long 0x00 "PDRSR015,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x13C4++0x03
line.long 0x00 "PDRONCR015,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x13C8++0x03
line.long 0x00 "PDROFFCR015,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1400++0x03
line.long 0x00 "PDRSR016,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1404++0x03
line.long 0x00 "PDRONCR016,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1408++0x03
line.long 0x00 "PDROFFCR016,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1440++0x03
line.long 0x00 "PDRSR017,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1444++0x03
line.long 0x00 "PDRONCR017,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1448++0x03
line.long 0x00 "PDROFFCR017,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1480++0x03
line.long 0x00 "PDRSR018,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1484++0x03
line.long 0x00 "PDRONCR018,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1488++0x03
line.long 0x00 "PDROFFCR018,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x14C0++0x03
line.long 0x00 "PDRSR019,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x14C4++0x03
line.long 0x00 "PDRONCR019,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x14C8++0x03
line.long 0x00 "PDROFFCR019,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1500++0x03
line.long 0x00 "PDRSR020,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1504++0x03
line.long 0x00 "PDRONCR020,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1508++0x03
line.long 0x00 "PDROFFCR020,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1540++0x03
line.long 0x00 "PDRSR021,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1544++0x03
line.long 0x00 "PDRONCR021,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1548++0x03
line.long 0x00 "PDROFFCR021,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1580++0x03
line.long 0x00 "PDRSR022,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1584++0x03
line.long 0x00 "PDRONCR022,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1588++0x03
line.long 0x00 "PDROFFCR022,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x15C0++0x03
line.long 0x00 "PDRSR023,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x15C4++0x03
line.long 0x00 "PDRONCR023,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x15C8++0x03
line.long 0x00 "PDROFFCR023,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1600++0x03
line.long 0x00 "PDRSR024,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1604++0x03
line.long 0x00 "PDRONCR024,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1608++0x03
line.long 0x00 "PDROFFCR024,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1640++0x03
line.long 0x00 "PDRSR025,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1644++0x03
line.long 0x00 "PDRONCR025,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1648++0x03
line.long 0x00 "PDROFFCR025,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1680++0x03
line.long 0x00 "PDRSR026,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1684++0x03
line.long 0x00 "PDRONCR026,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1688++0x03
line.long 0x00 "PDROFFCR026,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x16C0++0x03
line.long 0x00 "PDRSR027,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x16C4++0x03
line.long 0x00 "PDRONCR027,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x16C8++0x03
line.long 0x00 "PDROFFCR027,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1700++0x03
line.long 0x00 "PDRSR028,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1704++0x03
line.long 0x00 "PDRONCR028,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1708++0x03
line.long 0x00 "PDROFFCR028,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1740++0x03
line.long 0x00 "PDRSR029,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1744++0x03
line.long 0x00 "PDRONCR029,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1748++0x03
line.long 0x00 "PDROFFCR029,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1780++0x03
line.long 0x00 "PDRSR030,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1784++0x03
line.long 0x00 "PDRONCR030,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1788++0x03
line.long 0x00 "PDROFFCR030,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x17C0++0x03
line.long 0x00 "PDRSR031,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x17C4++0x03
line.long 0x00 "PDRONCR031,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x17C8++0x03
line.long 0x00 "PDROFFCR031,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1800++0x03
line.long 0x00 "PDRSR032,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1804++0x03
line.long 0x00 "PDRONCR032,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1808++0x03
line.long 0x00 "PDROFFCR032,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1840++0x03
line.long 0x00 "PDRSR033,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1844++0x03
line.long 0x00 "PDRONCR033,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1848++0x03
line.long 0x00 "PDROFFCR033,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1880++0x03
line.long 0x00 "PDRSR034,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1884++0x03
line.long 0x00 "PDRONCR034,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1888++0x03
line.long 0x00 "PDROFFCR034,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x18C0++0x03
line.long 0x00 "PDRSR035,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x18C4++0x03
line.long 0x00 "PDRONCR035,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x18C8++0x03
line.long 0x00 "PDROFFCR035,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1900++0x03
line.long 0x00 "PDRSR036,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1904++0x03
line.long 0x00 "PDRONCR036,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1908++0x03
line.long 0x00 "PDROFFCR036,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1940++0x03
line.long 0x00 "PDRSR037,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1944++0x03
line.long 0x00 "PDRONCR037,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1948++0x03
line.long 0x00 "PDROFFCR037,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1980++0x03
line.long 0x00 "PDRSR038,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1984++0x03
line.long 0x00 "PDRONCR038,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1988++0x03
line.long 0x00 "PDROFFCR038,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x19C0++0x03
line.long 0x00 "PDRSR039,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x19C4++0x03
line.long 0x00 "PDRONCR039,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x19C8++0x03
line.long 0x00 "PDROFFCR039,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1A00++0x03
line.long 0x00 "PDRSR040,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1A04++0x03
line.long 0x00 "PDRONCR040,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1A08++0x03
line.long 0x00 "PDROFFCR040,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1A40++0x03
line.long 0x00 "PDRSR041,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1A44++0x03
line.long 0x00 "PDRONCR041,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1A48++0x03
line.long 0x00 "PDROFFCR041,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1A80++0x03
line.long 0x00 "PDRSR042,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1A84++0x03
line.long 0x00 "PDRONCR042,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1A88++0x03
line.long 0x00 "PDROFFCR042,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1AC0++0x03
line.long 0x00 "PDRSR043,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1AC4++0x03
line.long 0x00 "PDRONCR043,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1AC8++0x03
line.long 0x00 "PDROFFCR043,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1B00++0x03
line.long 0x00 "PDRSR044,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1B04++0x03
line.long 0x00 "PDRONCR044,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1B08++0x03
line.long 0x00 "PDROFFCR044,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1B40++0x03
line.long 0x00 "PDRSR045,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1B44++0x03
line.long 0x00 "PDRONCR045,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1B48++0x03
line.long 0x00 "PDROFFCR045,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1B80++0x03
line.long 0x00 "PDRSR046,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1B84++0x03
line.long 0x00 "PDRONCR046,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1B88++0x03
line.long 0x00 "PDROFFCR046,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1BC0++0x03
line.long 0x00 "PDRSR047,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1BC4++0x03
line.long 0x00 "PDRONCR047,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1BC8++0x03
line.long 0x00 "PDROFFCR047,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1C00++0x03
line.long 0x00 "PDRSR048,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1C04++0x03
line.long 0x00 "PDRONCR048,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1C08++0x03
line.long 0x00 "PDROFFCR048,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1C40++0x03
line.long 0x00 "PDRSR049,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1C44++0x03
line.long 0x00 "PDRONCR049,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1C48++0x03
line.long 0x00 "PDROFFCR049,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1C80++0x03
line.long 0x00 "PDRSR050,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1C84++0x03
line.long 0x00 "PDRONCR050,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1C88++0x03
line.long 0x00 "PDROFFCR050,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1CC0++0x03
line.long 0x00 "PDRSR051,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1CC4++0x03
line.long 0x00 "PDRONCR051,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1CC8++0x03
line.long 0x00 "PDROFFCR051,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1D00++0x03
line.long 0x00 "PDRSR052,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1D04++0x03
line.long 0x00 "PDRONCR052,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1D08++0x03
line.long 0x00 "PDROFFCR052,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1D40++0x03
line.long 0x00 "PDRSR053,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1D44++0x03
line.long 0x00 "PDRONCR053,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1D48++0x03
line.long 0x00 "PDROFFCR053,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1D80++0x03
line.long 0x00 "PDRSR054,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1D84++0x03
line.long 0x00 "PDRONCR054,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1D88++0x03
line.long 0x00 "PDROFFCR054,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1DC0++0x03
line.long 0x00 "PDRSR055,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1DC4++0x03
line.long 0x00 "PDRONCR055,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1DC8++0x03
line.long 0x00 "PDROFFCR055,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1E00++0x03
line.long 0x00 "PDRSR056,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1E04++0x03
line.long 0x00 "PDRONCR056,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1E08++0x03
line.long 0x00 "PDROFFCR056,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1E40++0x03
line.long 0x00 "PDRSR057,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1E44++0x03
line.long 0x00 "PDRONCR057,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1E48++0x03
line.long 0x00 "PDROFFCR057,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1E80++0x03
line.long 0x00 "PDRSR058,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1E84++0x03
line.long 0x00 "PDRONCR058,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1E88++0x03
line.long 0x00 "PDROFFCR058,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1EC0++0x03
line.long 0x00 "PDRSR059,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1EC4++0x03
line.long 0x00 "PDRONCR059,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1EC8++0x03
line.long 0x00 "PDROFFCR059,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1F00++0x03
line.long 0x00 "PDRSR060,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1F04++0x03
line.long 0x00 "PDRONCR060,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1F08++0x03
line.long 0x00 "PDROFFCR060,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1F40++0x03
line.long 0x00 "PDRSR061,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1F44++0x03
line.long 0x00 "PDRONCR061,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1F48++0x03
line.long 0x00 "PDROFFCR061,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1F80++0x03
line.long 0x00 "PDRSR062,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1F84++0x03
line.long 0x00 "PDRONCR062,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1F88++0x03
line.long 0x00 "PDROFFCR062,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1FC0++0x03
line.long 0x00 "PDRSR063,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1FC4++0x03
line.long 0x00 "PDRONCR063,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1FC8++0x03
line.long 0x00 "PDROFFCR063,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
repeat 4. (strings "00" "10" "20" "30" )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0x3000)++0x03
line.long 0x00 "SYSCD0WACR$1,This register can be written by only Domain0 address"
abitfld.long 0x00 0.--31. "DnWACRm_31_0,Domain[n] Write access control for Common Registers" "0x00000000=0: Prohibit write access,0x00000001=1: Permit write access"
repeat.end
repeat 2. (strings "40" "50" )(list 0x00 0x04 )
group.long ($2+0x3010)++0x03
line.long 0x00 "SYSCD0WACR$1,This register can be written by only Domain0 address"
abitfld.long 0x00 0.--31. "DnWACRm_31_0,Domain[n] Write access control for Power domain register" "0x00000000=0: Prohibit write access,0x00000001=1: Permit write access"
repeat.end
repeat 4. (strings "00" "10" "20" "30" )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0x3020)++0x03
line.long 0x00 "SYSCD1WACR$1,This register can be written by only Domain0 address"
abitfld.long 0x00 0.--31. "DnWACRm_31_0,Domain[n] Write access control for Common Registers" "0x00000000=0: Prohibit write access,0x00000001=1: Permit write access"
repeat.end
repeat 2. (strings "40" "50" )(list 0x00 0x04 )
group.long ($2+0x3030)++0x03
line.long 0x00 "SYSCD1WACR$1,This register can be written by only Domain0 address"
abitfld.long 0x00 0.--31. "DnWACRm_31_0,Domain[n] Write access control for Power domain register" "0x00000000=0: Prohibit write access,0x00000001=1: Permit write access"
repeat.end
repeat 4. (strings "00" "10" "20" "30" )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0x3040)++0x03
line.long 0x00 "SYSCD2WACR$1,This register can be written by only Domain0 address"
abitfld.long 0x00 0.--31. "DnWACRm_31_0,Domain[n] Write access control for Common Registers" "0x00000000=0: Prohibit write access,0x00000001=1: Permit write access"
repeat.end
repeat 2. (strings "40" "50" )(list 0x00 0x04 )
group.long ($2+0x3050)++0x03
line.long 0x00 "SYSCD2WACR$1,This register can be written by only Domain0 address"
abitfld.long 0x00 0.--31. "DnWACRm_31_0,Domain[n] Write access control for Power domain register" "0x00000000=0: Prohibit write access,0x00000001=1: Permit write access"
repeat.end
repeat 4. (strings "00" "10" "20" "30" )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0x3060)++0x03
line.long 0x00 "SYSCD3WACR$1,This register can be written by only Domain0 address"
abitfld.long 0x00 0.--31. "DnWACRm_31_0,Domain[n] Write access control for Common Registers" "0x00000000=0: Prohibit write access,0x00000001=1: Permit write access"
repeat.end
repeat 2. (strings "40" "50" )(list 0x00 0x04 )
group.long ($2+0x3070)++0x03
line.long 0x00 "SYSCD3WACR$1,This register can be written by only Domain0 address"
abitfld.long 0x00 0.--31. "DnWACRm_31_0,Domain[n] Write access control for Power domain register" "0x00000000=0: Prohibit write access,0x00000001=1: Permit write access"
repeat.end
tree.end
tree "SYSC_INST_1"
base ad:0xE6184000
group.long 0x00++0x03
line.long 0x00 "SYSCSR1,Refer to bit assignment table above"
hexmask.long 0x00 2.--31. 1. "Reserved_2,Reserved *2"
rbitfld.long 0x00 0.--1. "BUSY_1_0,Indicates whether the SYSC is processing Power-ON or Power-OFF sequence" "0: Processing Power-ON or OFF sequence,?,?,3: Not processing Power-ON or OFF sequence"
group.long 0x10++0x03
line.long 0x00 "SYSCPTCSR1,Refer to bit assignment table above"
hexmask.long 0x00 3.--31. 1. "Reserved_3,Reserved *2"
bitfld.long 0x00 2. "EIEI,Write access protection Error Interrupt request Enable for INTC" "0: Disable error interrupt request for INTC,1: Enable error interrupt request for INTC"
newline
bitfld.long 0x00 1. "EIE,Write access protection Error Interrupt request Enable for ECM (FuSa)" "0: Disable error interrupt request for ECM,1: Enable error interrupt request for ECM"
bitfld.long 0x00 0. "ERR,Indicates Write access protection Error status" "0: Not detected Write access protection error,1: Detected Write access protection error"
group.long 0x14++0x03
line.long 0x00 "SYSCPTERADR1,Refer to bit assignment table above"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved *2"
bitfld.long 0x00 16. "CLR,Write access protection error address clear If write 1 ADR is cleared to 0 and the next error address can be hold" "0,1"
newline
hexmask.long.word 0x00 0.--15. 1. "ADR_15_0,First Write access protection error address"
group.long 0x20++0x03
line.long 0x00 "SYSCRDNCSR1,Refer to bit assignment table above"
abitfld.long 0x00 16.--31. "EIE_15_0,HW Redundant Error Interrupt Enable This bit indicates whether the SYSC allows to generate error interrupt to ECM or not when HW Redundant Error is detected" "0x0000=0: Disable Error Interrupt Disable,0x0001=1: Enable Error Interrupt (send error to.."
abitfld.long 0x00 0.--15. "ERR_15_0,HW Redundant Error Status Indicates that HW Redundant Error is detected" "0x0000=0: Not detected HW Redundant Error,0x0001=1: Detected HW Redundant Error If write 1.."
group.long 0x24++0x03
line.long 0x00 "SYSCRDNIR1,Refer to bit assignment table above"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,These bits are always read as 0"
abitfld.long 0x00 0.--15. "ERIN_15_0,Injects HW Redundant Error By setting those bits errors of HW redundant are asserted regardless of violated HW Redundant or not" "0x0000=0: Not-inject HW Redundant Error,0x0001=1: Inject HW Redundant Error"
group.long 0x30++0x03
line.long 0x00 "SYSCAPBACR1,Refer to bit assignment table above"
hexmask.long 0x00 0.--31. 1. "VAL_31_0,APB BUS Access Check Register for FuSa 32 bit Write/Read register T.B.D (0 detail function is not clear)"
group.long 0x800++0x03
line.long 0x00 "SYSCPONSR01,Refer to bit assignment table above"
abitfld.long 0x00 0.--31. "PDR_31_0,Power-ON status for PDR00-31 power domains" "0x00000000=0: non-Power-ON state,0x00000001=1: Power-ON state The read value of.."
group.long 0x804++0x03
line.long 0x00 "SYSCPONSR11,Refer to bit assignment table above"
abitfld.long 0x00 0.--31. "PDR_63_32,Power-ON status for PDR32-63 power domains" "0x00000000=0: non-Power-ON state,0x00000001=1: Power-ON state The read value of.."
group.long 0x808++0x03
line.long 0x00 "SYSCPOFFSR01,Refer to bit assignment table above"
abitfld.long 0x00 0.--31. "PDR_31_0,Power-OFF Status for PDR31-00 power domains" "0x00000000=0: non-Power-OFF state,0x00000001=1: Power-OFF state The read value of.."
group.long 0x80C++0x03
line.long 0x00 "SYSCPOFFSR11,Refer to bit assignment table above"
abitfld.long 0x00 0.--31. "PDR_63_32,Power-OFF Status for PDR63-32 power domains" "0x00000000=0: non-Power-OFF state,0x00000001=1: Power-OFF state The read value of.."
group.long 0x810++0x03
line.long 0x00 "SYSCISCR01,Refer to bit assignment table above"
hexmask.long 0x00 0.--31. 1. "PDR_31_0,Power-ON or OFF process complete interrupt status for PDR00-31 power domains"
group.long 0x814++0x03
line.long 0x00 "SYSCISCR11,Refer to bit assignment table above"
hexmask.long 0x00 0.--31. 1. "PDR_63_32,Power-ON or OFF process complete interrupt status for PDR32-63 power domains"
group.long 0x820++0x03
line.long 0x00 "SYSCIER01,Refer to bit assignment table above"
abitfld.long 0x00 0.--31. "PDR_31_0,Power-ON or OFF process complete interrupt Enable for PDR00-31 power domains" "0x00000000=0: Disable complete interrupt,0x00000001=1: Enable complete interrupt"
group.long 0x824++0x03
line.long 0x00 "SYSCIER11,Refer to bit assignment table above"
abitfld.long 0x00 0.--31. "PDR_63_32,Power-ON or OFF process complete interrupt Enable for PDR32-63 power domains" "0x00000000=0: Disable complete interrupt,0x00000001=1: Enable complete interrupt"
group.long 0x830++0x03
line.long 0x00 "SYSCIMR01,Refer to bit assignment table above"
abitfld.long 0x00 0.--31. "PDR_31_0,Mask complete interrupt request to INTC for PDR00-31 power domains" "0x00000000=0: Not mask complete interrupt request,0x00000001=1: Masks complete interrupt request.."
group.long 0x834++0x03
line.long 0x00 "SYSCIMR11,Refer to bit assignment table above"
abitfld.long 0x00 0.--31. "PDR_63_32,Mask complete interrupt request to INTC for PDR32-63 power domains" "0x00000000=0: Not mask complete interrupt request,0x00000001=1: Masks complete interrupt request.."
group.long 0x860++0x03
line.long 0x00 "SYSCISOEHSR01,Refer to bit assignment table above"
abitfld.long 0x00 0.--31. "PDR_31_0,Isolation Error High Status/Clear" "0x00000000=0: Not isolation Error form High level,0x00000001=1: Isolation Error form High level"
group.long 0x864++0x03
line.long 0x00 "SYSCISOEHSR11,Refer to bit assignment table above"
abitfld.long 0x00 0.--31. "PDR_63_32,Isolation Error High Status/Clear" "0x00000000=0: Not isolation Error form High level,0x00000001=1: Isolation Error form High level"
group.long 0x868++0x03
line.long 0x00 "SYSCISOELSR01,Refer to bit assignment table above"
abitfld.long 0x00 0.--31. "PDR_31_0,Isolation Error Low Status/Clear" "0x00000000=0: Not isolation Error form Low level,0x00000001=1: Isolation Error form Low level"
group.long 0x86C++0x03
line.long 0x00 "SYSCISOELSR11,Refer to bit assignment table above"
abitfld.long 0x00 0.--31. "PDR_63_32,Isolation Error Low Status/Clear" "0x00000000=0: Not isolation Error form Low level,0x00000001=1: Isolation Error form Low level"
group.long 0x870++0x03
line.long 0x00 "SYSCISOEHIR01,Refer to bit assignment table above"
abitfld.long 0x00 0.--31. "PDR_31_0,Isolation Error High Injection for PDR00-31" "0x00000000=0: Not Error Injection,0x00000001=1: Error Injection"
group.long 0x874++0x03
line.long 0x00 "SYSCISOEHIR11,Refer to bit assignment table above"
abitfld.long 0x00 0.--31. "PDR_63_32,Isolation Error High Injection for PDR32-63" "0x00000000=0: Not Error Injection,0x00000001=1: Error Injection"
group.long 0x878++0x03
line.long 0x00 "SYSCISOELIR01,Refer to bit assignment table above"
abitfld.long 0x00 0.--31. "PDR_31_0,Isolation Error Low Injection for PDR00-31" "0x00000000=0: Not Error Injection,0x00000001=1: Error Injection"
group.long 0x87C++0x03
line.long 0x00 "SYSCISOELIR11,Refer to bit assignment table above"
abitfld.long 0x00 0.--31. "PDR_63_32,Isolation Error Low Injection for PDR32-63" "0x00000000=0: Not Error Injection,0x00000001=1: Error Injection"
group.long 0x1000++0x03
line.long 0x00 "PDRSR10,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1004++0x03
line.long 0x00 "PDRONCR10,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1008++0x03
line.long 0x00 "PDROFFCR10,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1040++0x03
line.long 0x00 "PDRSR11,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1044++0x03
line.long 0x00 "PDRONCR11,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1048++0x03
line.long 0x00 "PDROFFCR11,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1080++0x03
line.long 0x00 "PDRSR12,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1084++0x03
line.long 0x00 "PDRONCR12,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1088++0x03
line.long 0x00 "PDROFFCR12,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x10C0++0x03
line.long 0x00 "PDRSR13,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x10C4++0x03
line.long 0x00 "PDRONCR13,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x10C8++0x03
line.long 0x00 "PDROFFCR13,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1100++0x03
line.long 0x00 "PDRSR14,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1104++0x03
line.long 0x00 "PDRONCR14,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1108++0x03
line.long 0x00 "PDROFFCR14,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1140++0x03
line.long 0x00 "PDRSR15,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1144++0x03
line.long 0x00 "PDRONCR15,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1148++0x03
line.long 0x00 "PDROFFCR15,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1180++0x03
line.long 0x00 "PDRSR16,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1184++0x03
line.long 0x00 "PDRONCR16,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1188++0x03
line.long 0x00 "PDROFFCR16,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x11C0++0x03
line.long 0x00 "PDRSR17,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x11C4++0x03
line.long 0x00 "PDRONCR17,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x11C8++0x03
line.long 0x00 "PDROFFCR17,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1200++0x03
line.long 0x00 "PDRSR18,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1204++0x03
line.long 0x00 "PDRONCR18,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1208++0x03
line.long 0x00 "PDROFFCR18,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1240++0x03
line.long 0x00 "PDRSR19,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1244++0x03
line.long 0x00 "PDRONCR19,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1248++0x03
line.long 0x00 "PDROFFCR19,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1280++0x03
line.long 0x00 "PDRSR110,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1284++0x03
line.long 0x00 "PDRONCR110,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1288++0x03
line.long 0x00 "PDROFFCR110,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x12C0++0x03
line.long 0x00 "PDRSR111,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x12C4++0x03
line.long 0x00 "PDRONCR111,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x12C8++0x03
line.long 0x00 "PDROFFCR111,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1300++0x03
line.long 0x00 "PDRSR112,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1304++0x03
line.long 0x00 "PDRONCR112,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1308++0x03
line.long 0x00 "PDROFFCR112,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1340++0x03
line.long 0x00 "PDRSR113,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1344++0x03
line.long 0x00 "PDRONCR113,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1348++0x03
line.long 0x00 "PDROFFCR113,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1380++0x03
line.long 0x00 "PDRSR114,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1384++0x03
line.long 0x00 "PDRONCR114,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1388++0x03
line.long 0x00 "PDROFFCR114,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x13C0++0x03
line.long 0x00 "PDRSR115,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x13C4++0x03
line.long 0x00 "PDRONCR115,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x13C8++0x03
line.long 0x00 "PDROFFCR115,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1400++0x03
line.long 0x00 "PDRSR116,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1404++0x03
line.long 0x00 "PDRONCR116,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1408++0x03
line.long 0x00 "PDROFFCR116,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1440++0x03
line.long 0x00 "PDRSR117,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1444++0x03
line.long 0x00 "PDRONCR117,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1448++0x03
line.long 0x00 "PDROFFCR117,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1480++0x03
line.long 0x00 "PDRSR118,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1484++0x03
line.long 0x00 "PDRONCR118,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1488++0x03
line.long 0x00 "PDROFFCR118,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x14C0++0x03
line.long 0x00 "PDRSR119,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x14C4++0x03
line.long 0x00 "PDRONCR119,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x14C8++0x03
line.long 0x00 "PDROFFCR119,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1500++0x03
line.long 0x00 "PDRSR120,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1504++0x03
line.long 0x00 "PDRONCR120,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1508++0x03
line.long 0x00 "PDROFFCR120,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1540++0x03
line.long 0x00 "PDRSR121,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1544++0x03
line.long 0x00 "PDRONCR121,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1548++0x03
line.long 0x00 "PDROFFCR121,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1580++0x03
line.long 0x00 "PDRSR122,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1584++0x03
line.long 0x00 "PDRONCR122,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1588++0x03
line.long 0x00 "PDROFFCR122,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x15C0++0x03
line.long 0x00 "PDRSR123,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x15C4++0x03
line.long 0x00 "PDRONCR123,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x15C8++0x03
line.long 0x00 "PDROFFCR123,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1600++0x03
line.long 0x00 "PDRSR124,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1604++0x03
line.long 0x00 "PDRONCR124,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1608++0x03
line.long 0x00 "PDROFFCR124,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1640++0x03
line.long 0x00 "PDRSR125,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1644++0x03
line.long 0x00 "PDRONCR125,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1648++0x03
line.long 0x00 "PDROFFCR125,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1680++0x03
line.long 0x00 "PDRSR126,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1684++0x03
line.long 0x00 "PDRONCR126,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1688++0x03
line.long 0x00 "PDROFFCR126,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x16C0++0x03
line.long 0x00 "PDRSR127,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x16C4++0x03
line.long 0x00 "PDRONCR127,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x16C8++0x03
line.long 0x00 "PDROFFCR127,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1700++0x03
line.long 0x00 "PDRSR128,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1704++0x03
line.long 0x00 "PDRONCR128,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1708++0x03
line.long 0x00 "PDROFFCR128,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1740++0x03
line.long 0x00 "PDRSR129,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1744++0x03
line.long 0x00 "PDRONCR129,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1748++0x03
line.long 0x00 "PDROFFCR129,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1780++0x03
line.long 0x00 "PDRSR130,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1784++0x03
line.long 0x00 "PDRONCR130,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1788++0x03
line.long 0x00 "PDROFFCR130,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x17C0++0x03
line.long 0x00 "PDRSR131,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x17C4++0x03
line.long 0x00 "PDRONCR131,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x17C8++0x03
line.long 0x00 "PDROFFCR131,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1800++0x03
line.long 0x00 "PDRSR132,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1804++0x03
line.long 0x00 "PDRONCR132,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1808++0x03
line.long 0x00 "PDROFFCR132,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1840++0x03
line.long 0x00 "PDRSR133,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1844++0x03
line.long 0x00 "PDRONCR133,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1848++0x03
line.long 0x00 "PDROFFCR133,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1880++0x03
line.long 0x00 "PDRSR134,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1884++0x03
line.long 0x00 "PDRONCR134,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1888++0x03
line.long 0x00 "PDROFFCR134,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x18C0++0x03
line.long 0x00 "PDRSR135,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x18C4++0x03
line.long 0x00 "PDRONCR135,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x18C8++0x03
line.long 0x00 "PDROFFCR135,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1900++0x03
line.long 0x00 "PDRSR136,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1904++0x03
line.long 0x00 "PDRONCR136,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1908++0x03
line.long 0x00 "PDROFFCR136,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1940++0x03
line.long 0x00 "PDRSR137,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1944++0x03
line.long 0x00 "PDRONCR137,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1948++0x03
line.long 0x00 "PDROFFCR137,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1980++0x03
line.long 0x00 "PDRSR138,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1984++0x03
line.long 0x00 "PDRONCR138,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1988++0x03
line.long 0x00 "PDROFFCR138,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x19C0++0x03
line.long 0x00 "PDRSR139,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x19C4++0x03
line.long 0x00 "PDRONCR139,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x19C8++0x03
line.long 0x00 "PDROFFCR139,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1A00++0x03
line.long 0x00 "PDRSR140,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1A04++0x03
line.long 0x00 "PDRONCR140,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1A08++0x03
line.long 0x00 "PDROFFCR140,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1A40++0x03
line.long 0x00 "PDRSR141,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1A44++0x03
line.long 0x00 "PDRONCR141,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1A48++0x03
line.long 0x00 "PDROFFCR141,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1A80++0x03
line.long 0x00 "PDRSR142,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1A84++0x03
line.long 0x00 "PDRONCR142,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1A88++0x03
line.long 0x00 "PDROFFCR142,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1AC0++0x03
line.long 0x00 "PDRSR143,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1AC4++0x03
line.long 0x00 "PDRONCR143,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1AC8++0x03
line.long 0x00 "PDROFFCR143,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1B00++0x03
line.long 0x00 "PDRSR144,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1B04++0x03
line.long 0x00 "PDRONCR144,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1B08++0x03
line.long 0x00 "PDROFFCR144,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1B40++0x03
line.long 0x00 "PDRSR145,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1B44++0x03
line.long 0x00 "PDRONCR145,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1B48++0x03
line.long 0x00 "PDROFFCR145,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1B80++0x03
line.long 0x00 "PDRSR146,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1B84++0x03
line.long 0x00 "PDRONCR146,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1B88++0x03
line.long 0x00 "PDROFFCR146,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1BC0++0x03
line.long 0x00 "PDRSR147,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1BC4++0x03
line.long 0x00 "PDRONCR147,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1BC8++0x03
line.long 0x00 "PDROFFCR147,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1C00++0x03
line.long 0x00 "PDRSR148,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1C04++0x03
line.long 0x00 "PDRONCR148,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1C08++0x03
line.long 0x00 "PDROFFCR148,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1C40++0x03
line.long 0x00 "PDRSR149,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1C44++0x03
line.long 0x00 "PDRONCR149,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1C48++0x03
line.long 0x00 "PDROFFCR149,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1C80++0x03
line.long 0x00 "PDRSR150,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1C84++0x03
line.long 0x00 "PDRONCR150,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1C88++0x03
line.long 0x00 "PDROFFCR150,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1CC0++0x03
line.long 0x00 "PDRSR151,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1CC4++0x03
line.long 0x00 "PDRONCR151,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1CC8++0x03
line.long 0x00 "PDROFFCR151,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1D00++0x03
line.long 0x00 "PDRSR152,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1D04++0x03
line.long 0x00 "PDRONCR152,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1D08++0x03
line.long 0x00 "PDROFFCR152,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1D40++0x03
line.long 0x00 "PDRSR153,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1D44++0x03
line.long 0x00 "PDRONCR153,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1D48++0x03
line.long 0x00 "PDROFFCR153,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1D80++0x03
line.long 0x00 "PDRSR154,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1D84++0x03
line.long 0x00 "PDRONCR154,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1D88++0x03
line.long 0x00 "PDROFFCR154,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1DC0++0x03
line.long 0x00 "PDRSR155,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1DC4++0x03
line.long 0x00 "PDRONCR155,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1DC8++0x03
line.long 0x00 "PDROFFCR155,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1E00++0x03
line.long 0x00 "PDRSR156,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1E04++0x03
line.long 0x00 "PDRONCR156,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1E08++0x03
line.long 0x00 "PDROFFCR156,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1E40++0x03
line.long 0x00 "PDRSR157,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1E44++0x03
line.long 0x00 "PDRONCR157,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1E48++0x03
line.long 0x00 "PDROFFCR157,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1E80++0x03
line.long 0x00 "PDRSR158,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1E84++0x03
line.long 0x00 "PDRONCR158,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1E88++0x03
line.long 0x00 "PDROFFCR158,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1EC0++0x03
line.long 0x00 "PDRSR159,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1EC4++0x03
line.long 0x00 "PDRONCR159,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1EC8++0x03
line.long 0x00 "PDROFFCR159,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1F00++0x03
line.long 0x00 "PDRSR160,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1F04++0x03
line.long 0x00 "PDRONCR160,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1F08++0x03
line.long 0x00 "PDROFFCR160,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1F40++0x03
line.long 0x00 "PDRSR161,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1F44++0x03
line.long 0x00 "PDRONCR161,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1F48++0x03
line.long 0x00 "PDROFFCR161,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1F80++0x03
line.long 0x00 "PDRSR162,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1F84++0x03
line.long 0x00 "PDRONCR162,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1F88++0x03
line.long 0x00 "PDROFFCR162,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1FC0++0x03
line.long 0x00 "PDRSR163,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1FC4++0x03
line.long 0x00 "PDRONCR163,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1FC8++0x03
line.long 0x00 "PDROFFCR163,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
repeat 4. (strings "01" "11" "21" "31" )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0x3000)++0x03
line.long 0x00 "SYSCD0WACR$1,This register can be written by only Domain0 address"
abitfld.long 0x00 0.--31. "DnWACRm_31_0,Domain[n] Write access control for Common Registers" "0x00000000=0: Prohibit write access,0x00000001=1: Permit write access"
repeat.end
repeat 2. (strings "41" "51" )(list 0x00 0x04 )
group.long ($2+0x3010)++0x03
line.long 0x00 "SYSCD0WACR$1,This register can be written by only Domain0 address"
abitfld.long 0x00 0.--31. "DnWACRm_31_0,Domain[n] Write access control for Power domain register" "0x00000000=0: Prohibit write access,0x00000001=1: Permit write access"
repeat.end
repeat 4. (strings "01" "11" "21" "31" )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0x3020)++0x03
line.long 0x00 "SYSCD1WACR$1,This register can be written by only Domain0 address"
abitfld.long 0x00 0.--31. "DnWACRm_31_0,Domain[n] Write access control for Common Registers" "0x00000000=0: Prohibit write access,0x00000001=1: Permit write access"
repeat.end
repeat 2. (strings "41" "51" )(list 0x00 0x04 )
group.long ($2+0x3030)++0x03
line.long 0x00 "SYSCD1WACR$1,This register can be written by only Domain0 address"
abitfld.long 0x00 0.--31. "DnWACRm_31_0,Domain[n] Write access control for Power domain register" "0x00000000=0: Prohibit write access,0x00000001=1: Permit write access"
repeat.end
repeat 4. (strings "01" "11" "21" "31" )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0x3040)++0x03
line.long 0x00 "SYSCD2WACR$1,This register can be written by only Domain0 address"
abitfld.long 0x00 0.--31. "DnWACRm_31_0,Domain[n] Write access control for Common Registers" "0x00000000=0: Prohibit write access,0x00000001=1: Permit write access"
repeat.end
repeat 2. (strings "41" "51" )(list 0x00 0x04 )
group.long ($2+0x3050)++0x03
line.long 0x00 "SYSCD2WACR$1,This register can be written by only Domain0 address"
abitfld.long 0x00 0.--31. "DnWACRm_31_0,Domain[n] Write access control for Power domain register" "0x00000000=0: Prohibit write access,0x00000001=1: Permit write access"
repeat.end
repeat 4. (strings "01" "11" "21" "31" )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0x3060)++0x03
line.long 0x00 "SYSCD3WACR$1,This register can be written by only Domain0 address"
abitfld.long 0x00 0.--31. "DnWACRm_31_0,Domain[n] Write access control for Common Registers" "0x00000000=0: Prohibit write access,0x00000001=1: Permit write access"
repeat.end
repeat 2. (strings "41" "51" )(list 0x00 0x04 )
group.long ($2+0x3070)++0x03
line.long 0x00 "SYSCD3WACR$1,This register can be written by only Domain0 address"
abitfld.long 0x00 0.--31. "DnWACRm_31_0,Domain[n] Write access control for Power domain register" "0x00000000=0: Prohibit write access,0x00000001=1: Permit write access"
repeat.end
tree.end
tree "SYSC_INST_2"
base ad:0xE6188000
group.long 0x00++0x03
line.long 0x00 "SYSCSR2,Refer to bit assignment table above"
hexmask.long 0x00 2.--31. 1. "Reserved_2,Reserved *2"
rbitfld.long 0x00 0.--1. "BUSY_1_0,Indicates whether the SYSC is processing Power-ON or Power-OFF sequence" "0: Processing Power-ON or OFF sequence,?,?,3: Not processing Power-ON or OFF sequence"
group.long 0x10++0x03
line.long 0x00 "SYSCPTCSR2,Refer to bit assignment table above"
hexmask.long 0x00 3.--31. 1. "Reserved_3,Reserved *2"
bitfld.long 0x00 2. "EIEI,Write access protection Error Interrupt request Enable for INTC" "0: Disable error interrupt request for INTC,1: Enable error interrupt request for INTC"
newline
bitfld.long 0x00 1. "EIE,Write access protection Error Interrupt request Enable for ECM (FuSa)" "0: Disable error interrupt request for ECM,1: Enable error interrupt request for ECM"
bitfld.long 0x00 0. "ERR,Indicates Write access protection Error status" "0: Not detected Write access protection error,1: Detected Write access protection error"
group.long 0x14++0x03
line.long 0x00 "SYSCPTERADR2,Refer to bit assignment table above"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved *2"
bitfld.long 0x00 16. "CLR,Write access protection error address clear If write 1 ADR is cleared to 0 and the next error address can be hold" "0,1"
newline
hexmask.long.word 0x00 0.--15. 1. "ADR_15_0,First Write access protection error address"
group.long 0x20++0x03
line.long 0x00 "SYSCRDNCSR2,Refer to bit assignment table above"
abitfld.long 0x00 16.--31. "EIE_15_0,HW Redundant Error Interrupt Enable This bit indicates whether the SYSC allows to generate error interrupt to ECM or not when HW Redundant Error is detected" "0x0000=0: Disable Error Interrupt Disable,0x0001=1: Enable Error Interrupt (send error to.."
abitfld.long 0x00 0.--15. "ERR_15_0,HW Redundant Error Status Indicates that HW Redundant Error is detected" "0x0000=0: Not detected HW Redundant Error,0x0001=1: Detected HW Redundant Error If write 1.."
group.long 0x24++0x03
line.long 0x00 "SYSCRDNIR2,Refer to bit assignment table above"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,These bits are always read as 0"
abitfld.long 0x00 0.--15. "ERIN_15_0,Injects HW Redundant Error By setting those bits errors of HW redundant are asserted regardless of violated HW Redundant or not" "0x0000=0: Not-inject HW Redundant Error,0x0001=1: Inject HW Redundant Error"
group.long 0x30++0x03
line.long 0x00 "SYSCAPBACR2,Refer to bit assignment table above"
hexmask.long 0x00 0.--31. 1. "VAL_31_0,APB BUS Access Check Register for FuSa 32 bit Write/Read register T.B.D (0 detail function is not clear)"
group.long 0x800++0x03
line.long 0x00 "SYSCPONSR02,Refer to bit assignment table above"
abitfld.long 0x00 0.--31. "PDR_31_0,Power-ON status for PDR00-31 power domains" "0x00000000=0: non-Power-ON state,0x00000001=1: Power-ON state The read value of.."
group.long 0x804++0x03
line.long 0x00 "SYSCPONSR12,Refer to bit assignment table above"
abitfld.long 0x00 0.--31. "PDR_63_32,Power-ON status for PDR32-63 power domains" "0x00000000=0: non-Power-ON state,0x00000001=1: Power-ON state The read value of.."
group.long 0x808++0x03
line.long 0x00 "SYSCPOFFSR02,Refer to bit assignment table above"
abitfld.long 0x00 0.--31. "PDR_31_0,Power-OFF Status for PDR31-00 power domains" "0x00000000=0: non-Power-OFF state,0x00000001=1: Power-OFF state The read value of.."
group.long 0x80C++0x03
line.long 0x00 "SYSCPOFFSR12,Refer to bit assignment table above"
abitfld.long 0x00 0.--31. "PDR_63_32,Power-OFF Status for PDR63-32 power domains" "0x00000000=0: non-Power-OFF state,0x00000001=1: Power-OFF state The read value of.."
group.long 0x810++0x03
line.long 0x00 "SYSCISCR02,Refer to bit assignment table above"
hexmask.long 0x00 0.--31. 1. "PDR_31_0,Power-ON or OFF process complete interrupt status for PDR00-31 power domains"
group.long 0x814++0x03
line.long 0x00 "SYSCISCR12,Refer to bit assignment table above"
hexmask.long 0x00 0.--31. 1. "PDR_63_32,Power-ON or OFF process complete interrupt status for PDR32-63 power domains"
group.long 0x820++0x03
line.long 0x00 "SYSCIER02,Refer to bit assignment table above"
abitfld.long 0x00 0.--31. "PDR_31_0,Power-ON or OFF process complete interrupt Enable for PDR00-31 power domains" "0x00000000=0: Disable complete interrupt,0x00000001=1: Enable complete interrupt"
group.long 0x824++0x03
line.long 0x00 "SYSCIER12,Refer to bit assignment table above"
abitfld.long 0x00 0.--31. "PDR_63_32,Power-ON or OFF process complete interrupt Enable for PDR32-63 power domains" "0x00000000=0: Disable complete interrupt,0x00000001=1: Enable complete interrupt"
group.long 0x830++0x03
line.long 0x00 "SYSCIMR02,Refer to bit assignment table above"
abitfld.long 0x00 0.--31. "PDR_31_0,Mask complete interrupt request to INTC for PDR00-31 power domains" "0x00000000=0: Not mask complete interrupt request,0x00000001=1: Masks complete interrupt request.."
group.long 0x834++0x03
line.long 0x00 "SYSCIMR12,Refer to bit assignment table above"
abitfld.long 0x00 0.--31. "PDR_63_32,Mask complete interrupt request to INTC for PDR32-63 power domains" "0x00000000=0: Not mask complete interrupt request,0x00000001=1: Masks complete interrupt request.."
group.long 0x860++0x03
line.long 0x00 "SYSCISOEHSR02,Refer to bit assignment table above"
abitfld.long 0x00 0.--31. "PDR_31_0,Isolation Error High Status/Clear" "0x00000000=0: Not isolation Error form High level,0x00000001=1: Isolation Error form High level"
group.long 0x864++0x03
line.long 0x00 "SYSCISOEHSR12,Refer to bit assignment table above"
abitfld.long 0x00 0.--31. "PDR_63_32,Isolation Error High Status/Clear" "0x00000000=0: Not isolation Error form High level,0x00000001=1: Isolation Error form High level"
group.long 0x868++0x03
line.long 0x00 "SYSCISOELSR02,Refer to bit assignment table above"
abitfld.long 0x00 0.--31. "PDR_31_0,Isolation Error Low Status/Clear" "0x00000000=0: Not isolation Error form Low level,0x00000001=1: Isolation Error form Low level"
group.long 0x86C++0x03
line.long 0x00 "SYSCISOELSR12,Refer to bit assignment table above"
abitfld.long 0x00 0.--31. "PDR_63_32,Isolation Error Low Status/Clear" "0x00000000=0: Not isolation Error form Low level,0x00000001=1: Isolation Error form Low level"
group.long 0x870++0x03
line.long 0x00 "SYSCISOEHIR02,Refer to bit assignment table above"
abitfld.long 0x00 0.--31. "PDR_31_0,Isolation Error High Injection for PDR00-31" "0x00000000=0: Not Error Injection,0x00000001=1: Error Injection"
group.long 0x874++0x03
line.long 0x00 "SYSCISOEHIR12,Refer to bit assignment table above"
abitfld.long 0x00 0.--31. "PDR_63_32,Isolation Error High Injection for PDR32-63" "0x00000000=0: Not Error Injection,0x00000001=1: Error Injection"
group.long 0x878++0x03
line.long 0x00 "SYSCISOELIR02,Refer to bit assignment table above"
abitfld.long 0x00 0.--31. "PDR_31_0,Isolation Error Low Injection for PDR00-31" "0x00000000=0: Not Error Injection,0x00000001=1: Error Injection"
group.long 0x87C++0x03
line.long 0x00 "SYSCISOELIR12,Refer to bit assignment table above"
abitfld.long 0x00 0.--31. "PDR_63_32,Isolation Error Low Injection for PDR32-63" "0x00000000=0: Not Error Injection,0x00000001=1: Error Injection"
group.long 0x1000++0x03
line.long 0x00 "PDRSR20,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1004++0x03
line.long 0x00 "PDRONCR20,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1008++0x03
line.long 0x00 "PDROFFCR20,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1040++0x03
line.long 0x00 "PDRSR21,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1044++0x03
line.long 0x00 "PDRONCR21,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1048++0x03
line.long 0x00 "PDROFFCR21,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1080++0x03
line.long 0x00 "PDRSR22,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1084++0x03
line.long 0x00 "PDRONCR22,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1088++0x03
line.long 0x00 "PDROFFCR22,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x10C0++0x03
line.long 0x00 "PDRSR23,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x10C4++0x03
line.long 0x00 "PDRONCR23,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x10C8++0x03
line.long 0x00 "PDROFFCR23,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1100++0x03
line.long 0x00 "PDRSR24,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1104++0x03
line.long 0x00 "PDRONCR24,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1108++0x03
line.long 0x00 "PDROFFCR24,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1140++0x03
line.long 0x00 "PDRSR25,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1144++0x03
line.long 0x00 "PDRONCR25,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1148++0x03
line.long 0x00 "PDROFFCR25,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1180++0x03
line.long 0x00 "PDRSR26,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1184++0x03
line.long 0x00 "PDRONCR26,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1188++0x03
line.long 0x00 "PDROFFCR26,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x11C0++0x03
line.long 0x00 "PDRSR27,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x11C4++0x03
line.long 0x00 "PDRONCR27,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x11C8++0x03
line.long 0x00 "PDROFFCR27,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1200++0x03
line.long 0x00 "PDRSR28,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1204++0x03
line.long 0x00 "PDRONCR28,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1208++0x03
line.long 0x00 "PDROFFCR28,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1240++0x03
line.long 0x00 "PDRSR29,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1244++0x03
line.long 0x00 "PDRONCR29,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1248++0x03
line.long 0x00 "PDROFFCR29,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1280++0x03
line.long 0x00 "PDRSR210,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1284++0x03
line.long 0x00 "PDRONCR210,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1288++0x03
line.long 0x00 "PDROFFCR210,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x12C0++0x03
line.long 0x00 "PDRSR211,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x12C4++0x03
line.long 0x00 "PDRONCR211,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x12C8++0x03
line.long 0x00 "PDROFFCR211,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1300++0x03
line.long 0x00 "PDRSR212,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1304++0x03
line.long 0x00 "PDRONCR212,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1308++0x03
line.long 0x00 "PDROFFCR212,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1340++0x03
line.long 0x00 "PDRSR213,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1344++0x03
line.long 0x00 "PDRONCR213,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1348++0x03
line.long 0x00 "PDROFFCR213,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1380++0x03
line.long 0x00 "PDRSR214,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1384++0x03
line.long 0x00 "PDRONCR214,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1388++0x03
line.long 0x00 "PDROFFCR214,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x13C0++0x03
line.long 0x00 "PDRSR215,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x13C4++0x03
line.long 0x00 "PDRONCR215,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x13C8++0x03
line.long 0x00 "PDROFFCR215,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1400++0x03
line.long 0x00 "PDRSR216,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1404++0x03
line.long 0x00 "PDRONCR216,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1408++0x03
line.long 0x00 "PDROFFCR216,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1440++0x03
line.long 0x00 "PDRSR217,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1444++0x03
line.long 0x00 "PDRONCR217,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1448++0x03
line.long 0x00 "PDROFFCR217,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1480++0x03
line.long 0x00 "PDRSR218,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1484++0x03
line.long 0x00 "PDRONCR218,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1488++0x03
line.long 0x00 "PDROFFCR218,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x14C0++0x03
line.long 0x00 "PDRSR219,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x14C4++0x03
line.long 0x00 "PDRONCR219,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x14C8++0x03
line.long 0x00 "PDROFFCR219,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1500++0x03
line.long 0x00 "PDRSR220,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1504++0x03
line.long 0x00 "PDRONCR220,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1508++0x03
line.long 0x00 "PDROFFCR220,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1540++0x03
line.long 0x00 "PDRSR221,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1544++0x03
line.long 0x00 "PDRONCR221,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1548++0x03
line.long 0x00 "PDROFFCR221,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1580++0x03
line.long 0x00 "PDRSR222,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1584++0x03
line.long 0x00 "PDRONCR222,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1588++0x03
line.long 0x00 "PDROFFCR222,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x15C0++0x03
line.long 0x00 "PDRSR223,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x15C4++0x03
line.long 0x00 "PDRONCR223,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x15C8++0x03
line.long 0x00 "PDROFFCR223,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1600++0x03
line.long 0x00 "PDRSR224,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1604++0x03
line.long 0x00 "PDRONCR224,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1608++0x03
line.long 0x00 "PDROFFCR224,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1640++0x03
line.long 0x00 "PDRSR225,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1644++0x03
line.long 0x00 "PDRONCR225,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1648++0x03
line.long 0x00 "PDROFFCR225,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1680++0x03
line.long 0x00 "PDRSR226,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1684++0x03
line.long 0x00 "PDRONCR226,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1688++0x03
line.long 0x00 "PDROFFCR226,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x16C0++0x03
line.long 0x00 "PDRSR227,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x16C4++0x03
line.long 0x00 "PDRONCR227,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x16C8++0x03
line.long 0x00 "PDROFFCR227,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1700++0x03
line.long 0x00 "PDRSR228,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1704++0x03
line.long 0x00 "PDRONCR228,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1708++0x03
line.long 0x00 "PDROFFCR228,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1740++0x03
line.long 0x00 "PDRSR229,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1744++0x03
line.long 0x00 "PDRONCR229,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1748++0x03
line.long 0x00 "PDROFFCR229,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1780++0x03
line.long 0x00 "PDRSR230,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1784++0x03
line.long 0x00 "PDRONCR230,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1788++0x03
line.long 0x00 "PDROFFCR230,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x17C0++0x03
line.long 0x00 "PDRSR231,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x17C4++0x03
line.long 0x00 "PDRONCR231,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x17C8++0x03
line.long 0x00 "PDROFFCR231,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1800++0x03
line.long 0x00 "PDRSR232,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1804++0x03
line.long 0x00 "PDRONCR232,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1808++0x03
line.long 0x00 "PDROFFCR232,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1840++0x03
line.long 0x00 "PDRSR233,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1844++0x03
line.long 0x00 "PDRONCR233,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1848++0x03
line.long 0x00 "PDROFFCR233,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1880++0x03
line.long 0x00 "PDRSR234,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1884++0x03
line.long 0x00 "PDRONCR234,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1888++0x03
line.long 0x00 "PDROFFCR234,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x18C0++0x03
line.long 0x00 "PDRSR235,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x18C4++0x03
line.long 0x00 "PDRONCR235,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x18C8++0x03
line.long 0x00 "PDROFFCR235,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1900++0x03
line.long 0x00 "PDRSR236,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1904++0x03
line.long 0x00 "PDRONCR236,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1908++0x03
line.long 0x00 "PDROFFCR236,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1940++0x03
line.long 0x00 "PDRSR237,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1944++0x03
line.long 0x00 "PDRONCR237,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1948++0x03
line.long 0x00 "PDROFFCR237,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1980++0x03
line.long 0x00 "PDRSR238,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1984++0x03
line.long 0x00 "PDRONCR238,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1988++0x03
line.long 0x00 "PDROFFCR238,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x19C0++0x03
line.long 0x00 "PDRSR239,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x19C4++0x03
line.long 0x00 "PDRONCR239,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x19C8++0x03
line.long 0x00 "PDROFFCR239,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1A00++0x03
line.long 0x00 "PDRSR240,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1A04++0x03
line.long 0x00 "PDRONCR240,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1A08++0x03
line.long 0x00 "PDROFFCR240,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1A40++0x03
line.long 0x00 "PDRSR241,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1A44++0x03
line.long 0x00 "PDRONCR241,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1A48++0x03
line.long 0x00 "PDROFFCR241,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1A80++0x03
line.long 0x00 "PDRSR242,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1A84++0x03
line.long 0x00 "PDRONCR242,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1A88++0x03
line.long 0x00 "PDROFFCR242,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1AC0++0x03
line.long 0x00 "PDRSR243,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1AC4++0x03
line.long 0x00 "PDRONCR243,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1AC8++0x03
line.long 0x00 "PDROFFCR243,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1B00++0x03
line.long 0x00 "PDRSR244,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1B04++0x03
line.long 0x00 "PDRONCR244,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1B08++0x03
line.long 0x00 "PDROFFCR244,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1B40++0x03
line.long 0x00 "PDRSR245,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1B44++0x03
line.long 0x00 "PDRONCR245,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1B48++0x03
line.long 0x00 "PDROFFCR245,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1B80++0x03
line.long 0x00 "PDRSR246,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1B84++0x03
line.long 0x00 "PDRONCR246,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1B88++0x03
line.long 0x00 "PDROFFCR246,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1BC0++0x03
line.long 0x00 "PDRSR247,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1BC4++0x03
line.long 0x00 "PDRONCR247,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1BC8++0x03
line.long 0x00 "PDROFFCR247,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1C00++0x03
line.long 0x00 "PDRSR248,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1C04++0x03
line.long 0x00 "PDRONCR248,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1C08++0x03
line.long 0x00 "PDROFFCR248,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1C40++0x03
line.long 0x00 "PDRSR249,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1C44++0x03
line.long 0x00 "PDRONCR249,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1C48++0x03
line.long 0x00 "PDROFFCR249,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1C80++0x03
line.long 0x00 "PDRSR250,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1C84++0x03
line.long 0x00 "PDRONCR250,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1C88++0x03
line.long 0x00 "PDROFFCR250,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1CC0++0x03
line.long 0x00 "PDRSR251,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1CC4++0x03
line.long 0x00 "PDRONCR251,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1CC8++0x03
line.long 0x00 "PDROFFCR251,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1D00++0x03
line.long 0x00 "PDRSR252,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1D04++0x03
line.long 0x00 "PDRONCR252,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1D08++0x03
line.long 0x00 "PDROFFCR252,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1D40++0x03
line.long 0x00 "PDRSR253,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1D44++0x03
line.long 0x00 "PDRONCR253,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1D48++0x03
line.long 0x00 "PDROFFCR253,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1D80++0x03
line.long 0x00 "PDRSR254,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1D84++0x03
line.long 0x00 "PDRONCR254,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1D88++0x03
line.long 0x00 "PDROFFCR254,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1DC0++0x03
line.long 0x00 "PDRSR255,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1DC4++0x03
line.long 0x00 "PDRONCR255,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1DC8++0x03
line.long 0x00 "PDROFFCR255,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1E00++0x03
line.long 0x00 "PDRSR256,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1E04++0x03
line.long 0x00 "PDRONCR256,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1E08++0x03
line.long 0x00 "PDROFFCR256,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1E40++0x03
line.long 0x00 "PDRSR257,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1E44++0x03
line.long 0x00 "PDRONCR257,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1E48++0x03
line.long 0x00 "PDROFFCR257,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1E80++0x03
line.long 0x00 "PDRSR258,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1E84++0x03
line.long 0x00 "PDRONCR258,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1E88++0x03
line.long 0x00 "PDROFFCR258,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1EC0++0x03
line.long 0x00 "PDRSR259,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1EC4++0x03
line.long 0x00 "PDRONCR259,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1EC8++0x03
line.long 0x00 "PDROFFCR259,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1F00++0x03
line.long 0x00 "PDRSR260,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1F04++0x03
line.long 0x00 "PDRONCR260,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1F08++0x03
line.long 0x00 "PDROFFCR260,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1F40++0x03
line.long 0x00 "PDRSR261,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1F44++0x03
line.long 0x00 "PDRONCR261,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1F48++0x03
line.long 0x00 "PDROFFCR261,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1F80++0x03
line.long 0x00 "PDRSR262,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1F84++0x03
line.long 0x00 "PDRONCR262,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1F88++0x03
line.long 0x00 "PDROFFCR262,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1FC0++0x03
line.long 0x00 "PDRSR263,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1FC4++0x03
line.long 0x00 "PDRONCR263,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1FC8++0x03
line.long 0x00 "PDROFFCR263,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
repeat 4. (strings "02" "12" "22" "32" )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0x3000)++0x03
line.long 0x00 "SYSCD0WACR$1,This register can be written by only Domain0 address"
abitfld.long 0x00 0.--31. "DnWACRm_31_0,Domain[n] Write access control for Common Registers" "0x00000000=0: Prohibit write access,0x00000001=1: Permit write access"
repeat.end
repeat 2. (strings "42" "52" )(list 0x00 0x04 )
group.long ($2+0x3010)++0x03
line.long 0x00 "SYSCD0WACR$1,This register can be written by only Domain0 address"
abitfld.long 0x00 0.--31. "DnWACRm_31_0,Domain[n] Write access control for Power domain register" "0x00000000=0: Prohibit write access,0x00000001=1: Permit write access"
repeat.end
repeat 4. (strings "02" "12" "22" "32" )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0x3020)++0x03
line.long 0x00 "SYSCD1WACR$1,This register can be written by only Domain0 address"
abitfld.long 0x00 0.--31. "DnWACRm_31_0,Domain[n] Write access control for Common Registers" "0x00000000=0: Prohibit write access,0x00000001=1: Permit write access"
repeat.end
repeat 2. (strings "42" "52" )(list 0x00 0x04 )
group.long ($2+0x3030)++0x03
line.long 0x00 "SYSCD1WACR$1,This register can be written by only Domain0 address"
abitfld.long 0x00 0.--31. "DnWACRm_31_0,Domain[n] Write access control for Power domain register" "0x00000000=0: Prohibit write access,0x00000001=1: Permit write access"
repeat.end
repeat 4. (strings "02" "12" "22" "32" )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0x3040)++0x03
line.long 0x00 "SYSCD2WACR$1,This register can be written by only Domain0 address"
abitfld.long 0x00 0.--31. "DnWACRm_31_0,Domain[n] Write access control for Common Registers" "0x00000000=0: Prohibit write access,0x00000001=1: Permit write access"
repeat.end
repeat 2. (strings "42" "52" )(list 0x00 0x04 )
group.long ($2+0x3050)++0x03
line.long 0x00 "SYSCD2WACR$1,This register can be written by only Domain0 address"
abitfld.long 0x00 0.--31. "DnWACRm_31_0,Domain[n] Write access control for Power domain register" "0x00000000=0: Prohibit write access,0x00000001=1: Permit write access"
repeat.end
repeat 4. (strings "02" "12" "22" "32" )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0x3060)++0x03
line.long 0x00 "SYSCD3WACR$1,This register can be written by only Domain0 address"
abitfld.long 0x00 0.--31. "DnWACRm_31_0,Domain[n] Write access control for Common Registers" "0x00000000=0: Prohibit write access,0x00000001=1: Permit write access"
repeat.end
repeat 2. (strings "42" "52" )(list 0x00 0x04 )
group.long ($2+0x3070)++0x03
line.long 0x00 "SYSCD3WACR$1,This register can be written by only Domain0 address"
abitfld.long 0x00 0.--31. "DnWACRm_31_0,Domain[n] Write access control for Power domain register" "0x00000000=0: Prohibit write access,0x00000001=1: Permit write access"
repeat.end
tree.end
tree "SYSC_INST_3"
base ad:0xE618C000
group.long 0x00++0x03
line.long 0x00 "SYSCSR3,Refer to bit assignment table above"
hexmask.long 0x00 2.--31. 1. "Reserved_2,Reserved *2"
rbitfld.long 0x00 0.--1. "BUSY_1_0,Indicates whether the SYSC is processing Power-ON or Power-OFF sequence" "0: Processing Power-ON or OFF sequence,?,?,3: Not processing Power-ON or OFF sequence"
group.long 0x10++0x03
line.long 0x00 "SYSCPTCSR3,Refer to bit assignment table above"
hexmask.long 0x00 3.--31. 1. "Reserved_3,Reserved *2"
bitfld.long 0x00 2. "EIEI,Write access protection Error Interrupt request Enable for INTC" "0: Disable error interrupt request for INTC,1: Enable error interrupt request for INTC"
newline
bitfld.long 0x00 1. "EIE,Write access protection Error Interrupt request Enable for ECM (FuSa)" "0: Disable error interrupt request for ECM,1: Enable error interrupt request for ECM"
bitfld.long 0x00 0. "ERR,Indicates Write access protection Error status" "0: Not detected Write access protection error,1: Detected Write access protection error"
group.long 0x14++0x03
line.long 0x00 "SYSCPTERADR3,Refer to bit assignment table above"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved *2"
bitfld.long 0x00 16. "CLR,Write access protection error address clear If write 1 ADR is cleared to 0 and the next error address can be hold" "0,1"
newline
hexmask.long.word 0x00 0.--15. 1. "ADR_15_0,First Write access protection error address"
group.long 0x20++0x03
line.long 0x00 "SYSCRDNCSR3,Refer to bit assignment table above"
abitfld.long 0x00 16.--31. "EIE_15_0,HW Redundant Error Interrupt Enable This bit indicates whether the SYSC allows to generate error interrupt to ECM or not when HW Redundant Error is detected" "0x0000=0: Disable Error Interrupt Disable,0x0001=1: Enable Error Interrupt (send error to.."
abitfld.long 0x00 0.--15. "ERR_15_0,HW Redundant Error Status Indicates that HW Redundant Error is detected" "0x0000=0: Not detected HW Redundant Error,0x0001=1: Detected HW Redundant Error If write 1.."
group.long 0x24++0x03
line.long 0x00 "SYSCRDNIR3,Refer to bit assignment table above"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,These bits are always read as 0"
abitfld.long 0x00 0.--15. "ERIN_15_0,Injects HW Redundant Error By setting those bits errors of HW redundant are asserted regardless of violated HW Redundant or not" "0x0000=0: Not-inject HW Redundant Error,0x0001=1: Inject HW Redundant Error"
group.long 0x30++0x03
line.long 0x00 "SYSCAPBACR3,Refer to bit assignment table above"
hexmask.long 0x00 0.--31. 1. "VAL_31_0,APB BUS Access Check Register for FuSa 32 bit Write/Read register T.B.D (0 detail function is not clear)"
group.long 0x800++0x03
line.long 0x00 "SYSCPONSR03,Refer to bit assignment table above"
abitfld.long 0x00 0.--31. "PDR_31_0,Power-ON status for PDR00-31 power domains" "0x00000000=0: non-Power-ON state,0x00000001=1: Power-ON state The read value of.."
group.long 0x804++0x03
line.long 0x00 "SYSCPONSR13,Refer to bit assignment table above"
abitfld.long 0x00 0.--31. "PDR_63_32,Power-ON status for PDR32-63 power domains" "0x00000000=0: non-Power-ON state,0x00000001=1: Power-ON state The read value of.."
group.long 0x808++0x03
line.long 0x00 "SYSCPOFFSR03,Refer to bit assignment table above"
abitfld.long 0x00 0.--31. "PDR_31_0,Power-OFF Status for PDR31-00 power domains" "0x00000000=0: non-Power-OFF state,0x00000001=1: Power-OFF state The read value of.."
group.long 0x80C++0x03
line.long 0x00 "SYSCPOFFSR13,Refer to bit assignment table above"
abitfld.long 0x00 0.--31. "PDR_63_32,Power-OFF Status for PDR63-32 power domains" "0x00000000=0: non-Power-OFF state,0x00000001=1: Power-OFF state The read value of.."
group.long 0x810++0x03
line.long 0x00 "SYSCISCR03,Refer to bit assignment table above"
hexmask.long 0x00 0.--31. 1. "PDR_31_0,Power-ON or OFF process complete interrupt status for PDR00-31 power domains"
group.long 0x814++0x03
line.long 0x00 "SYSCISCR13,Refer to bit assignment table above"
hexmask.long 0x00 0.--31. 1. "PDR_63_32,Power-ON or OFF process complete interrupt status for PDR32-63 power domains"
group.long 0x820++0x03
line.long 0x00 "SYSCIER03,Refer to bit assignment table above"
abitfld.long 0x00 0.--31. "PDR_31_0,Power-ON or OFF process complete interrupt Enable for PDR00-31 power domains" "0x00000000=0: Disable complete interrupt,0x00000001=1: Enable complete interrupt"
group.long 0x824++0x03
line.long 0x00 "SYSCIER13,Refer to bit assignment table above"
abitfld.long 0x00 0.--31. "PDR_63_32,Power-ON or OFF process complete interrupt Enable for PDR32-63 power domains" "0x00000000=0: Disable complete interrupt,0x00000001=1: Enable complete interrupt"
group.long 0x830++0x03
line.long 0x00 "SYSCIMR03,Refer to bit assignment table above"
abitfld.long 0x00 0.--31. "PDR_31_0,Mask complete interrupt request to INTC for PDR00-31 power domains" "0x00000000=0: Not mask complete interrupt request,0x00000001=1: Masks complete interrupt request.."
group.long 0x834++0x03
line.long 0x00 "SYSCIMR13,Refer to bit assignment table above"
abitfld.long 0x00 0.--31. "PDR_63_32,Mask complete interrupt request to INTC for PDR32-63 power domains" "0x00000000=0: Not mask complete interrupt request,0x00000001=1: Masks complete interrupt request.."
group.long 0x860++0x03
line.long 0x00 "SYSCISOEHSR03,Refer to bit assignment table above"
abitfld.long 0x00 0.--31. "PDR_31_0,Isolation Error High Status/Clear" "0x00000000=0: Not isolation Error form High level,0x00000001=1: Isolation Error form High level"
group.long 0x864++0x03
line.long 0x00 "SYSCISOEHSR13,Refer to bit assignment table above"
abitfld.long 0x00 0.--31. "PDR_63_32,Isolation Error High Status/Clear" "0x00000000=0: Not isolation Error form High level,0x00000001=1: Isolation Error form High level"
group.long 0x868++0x03
line.long 0x00 "SYSCISOELSR03,Refer to bit assignment table above"
abitfld.long 0x00 0.--31. "PDR_31_0,Isolation Error Low Status/Clear" "0x00000000=0: Not isolation Error form Low level,0x00000001=1: Isolation Error form Low level"
group.long 0x86C++0x03
line.long 0x00 "SYSCISOELSR13,Refer to bit assignment table above"
abitfld.long 0x00 0.--31. "PDR_63_32,Isolation Error Low Status/Clear" "0x00000000=0: Not isolation Error form Low level,0x00000001=1: Isolation Error form Low level"
group.long 0x870++0x03
line.long 0x00 "SYSCISOEHIR03,Refer to bit assignment table above"
abitfld.long 0x00 0.--31. "PDR_31_0,Isolation Error High Injection for PDR00-31" "0x00000000=0: Not Error Injection,0x00000001=1: Error Injection"
group.long 0x874++0x03
line.long 0x00 "SYSCISOEHIR13,Refer to bit assignment table above"
abitfld.long 0x00 0.--31. "PDR_63_32,Isolation Error High Injection for PDR32-63" "0x00000000=0: Not Error Injection,0x00000001=1: Error Injection"
group.long 0x878++0x03
line.long 0x00 "SYSCISOELIR03,Refer to bit assignment table above"
abitfld.long 0x00 0.--31. "PDR_31_0,Isolation Error Low Injection for PDR00-31" "0x00000000=0: Not Error Injection,0x00000001=1: Error Injection"
group.long 0x87C++0x03
line.long 0x00 "SYSCISOELIR13,Refer to bit assignment table above"
abitfld.long 0x00 0.--31. "PDR_63_32,Isolation Error Low Injection for PDR32-63" "0x00000000=0: Not Error Injection,0x00000001=1: Error Injection"
group.long 0x1000++0x03
line.long 0x00 "PDRSR30,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1004++0x03
line.long 0x00 "PDRONCR30,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1008++0x03
line.long 0x00 "PDROFFCR30,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1040++0x03
line.long 0x00 "PDRSR31,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1044++0x03
line.long 0x00 "PDRONCR31,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1048++0x03
line.long 0x00 "PDROFFCR31,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1080++0x03
line.long 0x00 "PDRSR32,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1084++0x03
line.long 0x00 "PDRONCR32,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1088++0x03
line.long 0x00 "PDROFFCR32,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x10C0++0x03
line.long 0x00 "PDRSR33,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x10C4++0x03
line.long 0x00 "PDRONCR33,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x10C8++0x03
line.long 0x00 "PDROFFCR33,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1100++0x03
line.long 0x00 "PDRSR34,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1104++0x03
line.long 0x00 "PDRONCR34,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1108++0x03
line.long 0x00 "PDROFFCR34,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1140++0x03
line.long 0x00 "PDRSR35,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1144++0x03
line.long 0x00 "PDRONCR35,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1148++0x03
line.long 0x00 "PDROFFCR35,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1180++0x03
line.long 0x00 "PDRSR36,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1184++0x03
line.long 0x00 "PDRONCR36,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1188++0x03
line.long 0x00 "PDROFFCR36,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x11C0++0x03
line.long 0x00 "PDRSR37,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x11C4++0x03
line.long 0x00 "PDRONCR37,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x11C8++0x03
line.long 0x00 "PDROFFCR37,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1200++0x03
line.long 0x00 "PDRSR38,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1204++0x03
line.long 0x00 "PDRONCR38,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1208++0x03
line.long 0x00 "PDROFFCR38,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1240++0x03
line.long 0x00 "PDRSR39,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1244++0x03
line.long 0x00 "PDRONCR39,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1248++0x03
line.long 0x00 "PDROFFCR39,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1280++0x03
line.long 0x00 "PDRSR310,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1284++0x03
line.long 0x00 "PDRONCR310,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1288++0x03
line.long 0x00 "PDROFFCR310,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x12C0++0x03
line.long 0x00 "PDRSR311,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x12C4++0x03
line.long 0x00 "PDRONCR311,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x12C8++0x03
line.long 0x00 "PDROFFCR311,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1300++0x03
line.long 0x00 "PDRSR312,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1304++0x03
line.long 0x00 "PDRONCR312,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1308++0x03
line.long 0x00 "PDROFFCR312,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1340++0x03
line.long 0x00 "PDRSR313,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1344++0x03
line.long 0x00 "PDRONCR313,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1348++0x03
line.long 0x00 "PDROFFCR313,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1380++0x03
line.long 0x00 "PDRSR314,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1384++0x03
line.long 0x00 "PDRONCR314,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1388++0x03
line.long 0x00 "PDROFFCR314,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x13C0++0x03
line.long 0x00 "PDRSR315,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x13C4++0x03
line.long 0x00 "PDRONCR315,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x13C8++0x03
line.long 0x00 "PDROFFCR315,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1400++0x03
line.long 0x00 "PDRSR316,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1404++0x03
line.long 0x00 "PDRONCR316,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1408++0x03
line.long 0x00 "PDROFFCR316,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1440++0x03
line.long 0x00 "PDRSR317,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1444++0x03
line.long 0x00 "PDRONCR317,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1448++0x03
line.long 0x00 "PDROFFCR317,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1480++0x03
line.long 0x00 "PDRSR318,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1484++0x03
line.long 0x00 "PDRONCR318,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1488++0x03
line.long 0x00 "PDROFFCR318,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x14C0++0x03
line.long 0x00 "PDRSR319,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x14C4++0x03
line.long 0x00 "PDRONCR319,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x14C8++0x03
line.long 0x00 "PDROFFCR319,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1500++0x03
line.long 0x00 "PDRSR320,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1504++0x03
line.long 0x00 "PDRONCR320,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1508++0x03
line.long 0x00 "PDROFFCR320,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1540++0x03
line.long 0x00 "PDRSR321,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1544++0x03
line.long 0x00 "PDRONCR321,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1548++0x03
line.long 0x00 "PDROFFCR321,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1580++0x03
line.long 0x00 "PDRSR322,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1584++0x03
line.long 0x00 "PDRONCR322,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1588++0x03
line.long 0x00 "PDROFFCR322,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x15C0++0x03
line.long 0x00 "PDRSR323,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x15C4++0x03
line.long 0x00 "PDRONCR323,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x15C8++0x03
line.long 0x00 "PDROFFCR323,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1600++0x03
line.long 0x00 "PDRSR324,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1604++0x03
line.long 0x00 "PDRONCR324,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1608++0x03
line.long 0x00 "PDROFFCR324,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1640++0x03
line.long 0x00 "PDRSR325,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1644++0x03
line.long 0x00 "PDRONCR325,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1648++0x03
line.long 0x00 "PDROFFCR325,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1680++0x03
line.long 0x00 "PDRSR326,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1684++0x03
line.long 0x00 "PDRONCR326,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1688++0x03
line.long 0x00 "PDROFFCR326,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x16C0++0x03
line.long 0x00 "PDRSR327,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x16C4++0x03
line.long 0x00 "PDRONCR327,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x16C8++0x03
line.long 0x00 "PDROFFCR327,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1700++0x03
line.long 0x00 "PDRSR328,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1704++0x03
line.long 0x00 "PDRONCR328,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1708++0x03
line.long 0x00 "PDROFFCR328,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1740++0x03
line.long 0x00 "PDRSR329,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1744++0x03
line.long 0x00 "PDRONCR329,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1748++0x03
line.long 0x00 "PDROFFCR329,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1780++0x03
line.long 0x00 "PDRSR330,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1784++0x03
line.long 0x00 "PDRONCR330,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1788++0x03
line.long 0x00 "PDROFFCR330,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x17C0++0x03
line.long 0x00 "PDRSR331,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x17C4++0x03
line.long 0x00 "PDRONCR331,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x17C8++0x03
line.long 0x00 "PDROFFCR331,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1800++0x03
line.long 0x00 "PDRSR332,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1804++0x03
line.long 0x00 "PDRONCR332,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1808++0x03
line.long 0x00 "PDROFFCR332,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1840++0x03
line.long 0x00 "PDRSR333,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1844++0x03
line.long 0x00 "PDRONCR333,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1848++0x03
line.long 0x00 "PDROFFCR333,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1880++0x03
line.long 0x00 "PDRSR334,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1884++0x03
line.long 0x00 "PDRONCR334,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1888++0x03
line.long 0x00 "PDROFFCR334,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x18C0++0x03
line.long 0x00 "PDRSR335,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x18C4++0x03
line.long 0x00 "PDRONCR335,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x18C8++0x03
line.long 0x00 "PDROFFCR335,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1900++0x03
line.long 0x00 "PDRSR336,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1904++0x03
line.long 0x00 "PDRONCR336,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1908++0x03
line.long 0x00 "PDROFFCR336,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1940++0x03
line.long 0x00 "PDRSR337,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1944++0x03
line.long 0x00 "PDRONCR337,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1948++0x03
line.long 0x00 "PDROFFCR337,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1980++0x03
line.long 0x00 "PDRSR338,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1984++0x03
line.long 0x00 "PDRONCR338,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1988++0x03
line.long 0x00 "PDROFFCR338,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x19C0++0x03
line.long 0x00 "PDRSR339,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x19C4++0x03
line.long 0x00 "PDRONCR339,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x19C8++0x03
line.long 0x00 "PDROFFCR339,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1A00++0x03
line.long 0x00 "PDRSR340,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1A04++0x03
line.long 0x00 "PDRONCR340,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1A08++0x03
line.long 0x00 "PDROFFCR340,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1A40++0x03
line.long 0x00 "PDRSR341,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1A44++0x03
line.long 0x00 "PDRONCR341,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1A48++0x03
line.long 0x00 "PDROFFCR341,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1A80++0x03
line.long 0x00 "PDRSR342,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1A84++0x03
line.long 0x00 "PDRONCR342,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1A88++0x03
line.long 0x00 "PDROFFCR342,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1AC0++0x03
line.long 0x00 "PDRSR343,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1AC4++0x03
line.long 0x00 "PDRONCR343,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1AC8++0x03
line.long 0x00 "PDROFFCR343,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1B00++0x03
line.long 0x00 "PDRSR344,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1B04++0x03
line.long 0x00 "PDRONCR344,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1B08++0x03
line.long 0x00 "PDROFFCR344,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1B40++0x03
line.long 0x00 "PDRSR345,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1B44++0x03
line.long 0x00 "PDRONCR345,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1B48++0x03
line.long 0x00 "PDROFFCR345,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1B80++0x03
line.long 0x00 "PDRSR346,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1B84++0x03
line.long 0x00 "PDRONCR346,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1B88++0x03
line.long 0x00 "PDROFFCR346,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1BC0++0x03
line.long 0x00 "PDRSR347,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1BC4++0x03
line.long 0x00 "PDRONCR347,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1BC8++0x03
line.long 0x00 "PDROFFCR347,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1C00++0x03
line.long 0x00 "PDRSR348,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1C04++0x03
line.long 0x00 "PDRONCR348,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1C08++0x03
line.long 0x00 "PDROFFCR348,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1C40++0x03
line.long 0x00 "PDRSR349,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1C44++0x03
line.long 0x00 "PDRONCR349,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1C48++0x03
line.long 0x00 "PDROFFCR349,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1C80++0x03
line.long 0x00 "PDRSR350,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1C84++0x03
line.long 0x00 "PDRONCR350,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1C88++0x03
line.long 0x00 "PDROFFCR350,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1CC0++0x03
line.long 0x00 "PDRSR351,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1CC4++0x03
line.long 0x00 "PDRONCR351,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1CC8++0x03
line.long 0x00 "PDROFFCR351,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1D00++0x03
line.long 0x00 "PDRSR352,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1D04++0x03
line.long 0x00 "PDRONCR352,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1D08++0x03
line.long 0x00 "PDROFFCR352,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1D40++0x03
line.long 0x00 "PDRSR353,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1D44++0x03
line.long 0x00 "PDRONCR353,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1D48++0x03
line.long 0x00 "PDROFFCR353,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1D80++0x03
line.long 0x00 "PDRSR354,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1D84++0x03
line.long 0x00 "PDRONCR354,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1D88++0x03
line.long 0x00 "PDROFFCR354,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1DC0++0x03
line.long 0x00 "PDRSR355,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1DC4++0x03
line.long 0x00 "PDRONCR355,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1DC8++0x03
line.long 0x00 "PDROFFCR355,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1E00++0x03
line.long 0x00 "PDRSR356,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1E04++0x03
line.long 0x00 "PDRONCR356,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1E08++0x03
line.long 0x00 "PDROFFCR356,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1E40++0x03
line.long 0x00 "PDRSR357,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1E44++0x03
line.long 0x00 "PDRONCR357,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1E48++0x03
line.long 0x00 "PDROFFCR357,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1E80++0x03
line.long 0x00 "PDRSR358,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1E84++0x03
line.long 0x00 "PDRONCR358,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1E88++0x03
line.long 0x00 "PDROFFCR358,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1EC0++0x03
line.long 0x00 "PDRSR359,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1EC4++0x03
line.long 0x00 "PDRONCR359,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1EC8++0x03
line.long 0x00 "PDROFFCR359,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1F00++0x03
line.long 0x00 "PDRSR360,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1F04++0x03
line.long 0x00 "PDRONCR360,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1F08++0x03
line.long 0x00 "PDROFFCR360,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1F40++0x03
line.long 0x00 "PDRSR361,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1F44++0x03
line.long 0x00 "PDRONCR361,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1F48++0x03
line.long 0x00 "PDROFFCR361,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1F80++0x03
line.long 0x00 "PDRSR362,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1F84++0x03
line.long 0x00 "PDRONCR362,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1F88++0x03
line.long 0x00 "PDROFFCR362,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
group.long 0x1FC0++0x03
line.long 0x00 "PDRSR363,Refer to bit assignment table above"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved *2"
rbitfld.long 0x00 12. "ON_STATE,Indicates status of Power-ON sequence" "0: Not processing Power-ON sequence,1: Processing Power ON sequence"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 8. "OFF_STATE,Indicates status of Power-OFF sequence" "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "ON,Indicates Power-ON state" "0: Not Power-ON state,1: Power-ON state"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved *2" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0. "OFF,Indicates Power-OFF state" "0: Not Power-OFF state,1: Power-OFF state"
group.long 0x1FC4++0x03
line.long 0x00 "PDRONCR363,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWRON,Power-ON request" "0,1"
group.long 0x1FC8++0x03
line.long 0x00 "PDROFFCR363,Refer to bit assignment table above"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved *2"
bitfld.long 0x00 0. "PWROFF,Power-OFF request" "0,1"
repeat 4. (strings "03" "13" "23" "33" )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0x3000)++0x03
line.long 0x00 "SYSCD0WACR$1,This register can be written by only Domain0 address"
abitfld.long 0x00 0.--31. "DnWACRm_31_0,Domain[n] Write access control for Common Registers" "0x00000000=0: Prohibit write access,0x00000001=1: Permit write access"
repeat.end
repeat 2. (strings "43" "53" )(list 0x00 0x04 )
group.long ($2+0x3010)++0x03
line.long 0x00 "SYSCD0WACR$1,This register can be written by only Domain0 address"
abitfld.long 0x00 0.--31. "DnWACRm_31_0,Domain[n] Write access control for Power domain register" "0x00000000=0: Prohibit write access,0x00000001=1: Permit write access"
repeat.end
repeat 4. (strings "03" "13" "23" "33" )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0x3020)++0x03
line.long 0x00 "SYSCD1WACR$1,This register can be written by only Domain0 address"
abitfld.long 0x00 0.--31. "DnWACRm_31_0,Domain[n] Write access control for Common Registers" "0x00000000=0: Prohibit write access,0x00000001=1: Permit write access"
repeat.end
repeat 2. (strings "43" "53" )(list 0x00 0x04 )
group.long ($2+0x3030)++0x03
line.long 0x00 "SYSCD1WACR$1,This register can be written by only Domain0 address"
abitfld.long 0x00 0.--31. "DnWACRm_31_0,Domain[n] Write access control for Power domain register" "0x00000000=0: Prohibit write access,0x00000001=1: Permit write access"
repeat.end
repeat 4. (strings "03" "13" "23" "33" )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0x3040)++0x03
line.long 0x00 "SYSCD2WACR$1,This register can be written by only Domain0 address"
abitfld.long 0x00 0.--31. "DnWACRm_31_0,Domain[n] Write access control for Common Registers" "0x00000000=0: Prohibit write access,0x00000001=1: Permit write access"
repeat.end
repeat 2. (strings "43" "53" )(list 0x00 0x04 )
group.long ($2+0x3050)++0x03
line.long 0x00 "SYSCD2WACR$1,This register can be written by only Domain0 address"
abitfld.long 0x00 0.--31. "DnWACRm_31_0,Domain[n] Write access control for Power domain register" "0x00000000=0: Prohibit write access,0x00000001=1: Permit write access"
repeat.end
repeat 4. (strings "03" "13" "23" "33" )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0x3060)++0x03
line.long 0x00 "SYSCD3WACR$1,This register can be written by only Domain0 address"
abitfld.long 0x00 0.--31. "DnWACRm_31_0,Domain[n] Write access control for Common Registers" "0x00000000=0: Prohibit write access,0x00000001=1: Permit write access"
repeat.end
repeat 2. (strings "43" "53" )(list 0x00 0x04 )
group.long ($2+0x3070)++0x03
line.long 0x00 "SYSCD3WACR$1,This register can be written by only Domain0 address"
abitfld.long 0x00 0.--31. "DnWACRm_31_0,Domain[n] Write access control for Power domain register" "0x00000000=0: Prohibit write access,0x00000001=1: Permit write access"
repeat.end
tree.end
tree.end
tree "THS"
tree "THS_INST_0"
base ad:0xE6198000
group.long 0x04++0x03
line.long 0x00 "IRQSTR1,"
hexmask.long 0x00 6.--31. 1. "Reserved_6,Reserved These bits are fixed to 0"
newline
bitfld.long 0x00 5. "TEMPD3_STR,TEMPD3 Detection Status" "0: Not detected,1: TEMP_CODE [11:0] bits detect that"
newline
bitfld.long 0x00 4. "TEMPD2_STR,TEMPD2 Detection Status" "0: Not detected,1: TEMP_CODE [11:0] bits detect that"
newline
bitfld.long 0x00 3. "TEMPD1_STR,TEMPD1 Detection Status" "0: Not detected,1: TEMP_CODE [11:0] bits detect that"
newline
bitfld.long 0x00 2. "TEMP3_STR,TEMP3 Detection Status" "0: Not detected,1: TEMP_CODE [11:0] bits detect that"
newline
bitfld.long 0x00 1. "TEMP2_STR,TEMP2 Detection Status" "0: Not detected,1: TEMP_CODE [11:0] bits detect that"
newline
bitfld.long 0x00 0. "TEMP1_STR,TEMP1 Detection Status" "0: Not detected,1: TEMP_CODE [11:0] bits detect that"
group.long 0x08++0x03
line.long 0x00 "IRQMSK1,"
hexmask.long 0x00 6.--31. 1. "Reserved_6,Reserved These bits are fixed to 0"
newline
bitfld.long 0x00 5. "TEMPD3_MSK,This bit selects masking or non-masking of TEMPD3 error requests" "0: Errors are masked,1: The mask is cleared"
newline
bitfld.long 0x00 4. "TEMPD2_MSK,This bit selects masking or non-masking of TEMPD2 error requests" "0: Errors are masked,1: The mask is cleared"
newline
bitfld.long 0x00 3. "TEMPD1_MSK,This bit selects masking or non-masking of TEMPD1 error requests" "0: Errors are masked,1: The mask is cleared"
newline
bitfld.long 0x00 2. "TEMP3_MSK,This bit selects masking or non-masking of TEMP3 error requests" "0: Errors are masked,1: The mask is cleared"
newline
bitfld.long 0x00 1. "TEMP2_MSK,This bit selects masking or non-masking of TEMP2 error requests" "0: Errors are masked,1: The mask is cleared"
newline
bitfld.long 0x00 0. "TEMP1_MSK,This bit selects masking or non-masking of TEMP1 error requests" "0: Errors are masked,1: The mask is cleared"
group.long 0x10++0x03
line.long 0x00 "IRQEN1,"
hexmask.long 0x00 6.--31. 1. "Reserved_6,Reserved These bits are fixed to 0"
newline
bitfld.long 0x00 5. "TEMPD3_EN,This bit enables or disables TEMPD3 errors" "0: TEMPD3 errors are disabled,1: TEMPD3 errors are enabled"
newline
bitfld.long 0x00 4. "TEMPD2_EN,This bit enables or disables TEMPD2 errors" "0: TEMPD2 errors are disabled,1: TEMPD2 errors are enabled"
newline
bitfld.long 0x00 3. "TEMPD1_EN,This bit enables or disables TEMPD1 errors" "0: TEMPD1 errors are disabled,1: TEMPD1 errors are enabled"
newline
bitfld.long 0x00 2. "TEMP3_EN,This bit enables or disables TEMP3 errors" "0: TEMP3 errors are disabled,1: TEMP3 errors are enabled"
newline
bitfld.long 0x00 1. "TEMP2_EN,This bit enables or disables TEMP2 errors" "0: TEMP2 errors are disabled,1: TEMP2 errors are enabled"
newline
bitfld.long 0x00 0. "TEMP1_EN,This bit enables or disables TEMP1 errors" "0: TEMP1 errors are disabled,1: TEMP1 errors are enabled"
group.long 0x14++0x03
line.long 0x00 "IRQTEMP11,"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are fixed to 0"
newline
rbitfld.long 0x00 12.--13. "Reserved_12,Reserved These bits are fixed to 0" "0,1,2,3"
newline
hexmask.long.word 0x00 0.--11. 1. "IRQTEMP1_11_0,These bits set the first threshold value of the temperature for TEMP1 and TEMPD1 errors"
group.long 0x18++0x03
line.long 0x00 "IRQTEMP21,"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are fixed to 0"
newline
rbitfld.long 0x00 12.--13. "Reserved_12,Reserved These bits are fixed to 0" "0,1,2,3"
newline
hexmask.long.word 0x00 0.--11. 1. "IRQTEMP2_11_0,These bits set the second threshold value of the temperature for TEMP2 and TEMPD2 errors"
group.long 0x1C++0x03
line.long 0x00 "IRQTEMP31,"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are fixed to 0"
newline
rbitfld.long 0x00 12.--13. "Reserved_12,Reserved These bits are fixed to 0" "0,1,2,3"
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hexmask.long.word 0x00 0.--11. 1. "IRQTEMP3_11_0,These bits set the third threshold value of the temperature for TEMP3 and TEMPD3 errors"
group.long 0x20++0x03
line.long 0x00 "THCTR1,"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are fixed to 0"
newline
rbitfld.long 0x00 24. "Reserved_24,Reserved These bits are fixed to 0" "0,1"
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rbitfld.long 0x00 21.--23. "Reserved_21,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 20. "CIVMTST,THS/CIVM failure check mode" "0: Normal mode,1: THS/CIVM failure check mode"
newline
rbitfld.long 0x00 18.--19. "Reserved_18,Reserved These bits are fixed to 0" "0,1,2,3"
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rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are fixed to 0" "0,1,2,3"
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rbitfld.long 0x00 10.--15. "Reserved_10,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 8.--9. "SENSSEL_1_0,Select the use sensor" "0: THS CIVM both ON,1: THS ON only,2: CIVM ON only,3: THS CIVM both ON (this setting is the"
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rbitfld.long 0x00 6.--7. "Reserved_6,Reserved These bits are fixed to 0" "0,1,2,3"
newline
bitfld.long 0x00 5. "TH_EN_B,THS/CIVM enable" "0: Enabled,1: Disabled"
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bitfld.long 0x00 1.--4. "Reserved_1,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0. "THSST,Enabling/disabling of the A/D converter for the thermal sensor" "0: Disabled,1: Enabled"
group.long 0x24++0x03
line.long 0x00 "THSTR1,"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved These bits are fixed to 0"
newline
rbitfld.long 0x00 3. "THACKMON,THACK signal monitor Indicates that the THCODE was generated" "0: Not detected,1: THCODE was generated"
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rbitfld.long 0x00 2. "THCNTOV_MON,THCNTOV signal monitor Indicates that the counter overflowed" "0: Not detected,1: Detected overflow"
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rbitfld.long 0x00 1. "THFAIL1,This bit is set to 1 when all of the THCODE bits are 1" "0: Normal operation,1: All of the THCODE bits are all 1"
newline
rbitfld.long 0x00 0. "THFAIL0,This bit is set to 1 when all of the THCODE bits are 0" "0: Normal operation,1: All of the THCODE bits are all 0"
group.long 0x28++0x03
line.long 0x00 "TEMP1,"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are fixed to 0"
newline
rbitfld.long 0x00 12.--13. "Reserved_12,Reserved These bits are fixed to 0" "0,1,2,3"
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hexmask.long.word 0x00 0.--11. 1. "TEMP_CODE_11_0,These bits indicate the digital value for the temperature detected by the thermal sensor"
group.long 0x2C++0x03
line.long 0x00 "VOLT1,"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are fixed to 0"
newline
rbitfld.long 0x00 10.--13. "Reserved_10,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x00 0.--9. 1. "VOLT_CODE_9_0,These bits indicate the digital value for the voltage detected by the chip internal voltage monitor"
group.long 0x68++0x03
line.long 0x00 "THSCP,"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved This bit values depend on FUSE bits"
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rbitfld.long 0x00 14.--15. "COR_PARA_VLD_1_0,Shows whether trimming parameter in FUSE is valid" "0,1,2,3"
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hexmask.long.word 0x00 0.--13. 1. "Reserved_0,Reserved These bits are indefinite"
group.long 0x6C++0x03
line.long 0x00 "IRQ_INJECTION1,"
hexmask.long 0x00 6.--31. 1. "Reserved_6,Reserved These bits are fixed to 0"
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bitfld.long 0x00 5. "TEMPD3_INJ,TEMPD3 Error Injection" "0: TEMPD3 Error Injection Disable,1: TEMPD3 Error Injection Enable"
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bitfld.long 0x00 4. "TEMPD2_INJ,TEMPD2 Error Injection" "0: TEMPD2 Error Injection Disable,1: TEMPD2 Error Injection Enable"
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bitfld.long 0x00 3. "TEMPD1_INJ,TEMPD1 Error Injection" "0: TEMPD1 Error Injection Disable,1: TEMPD1 Error Injection Enable"
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bitfld.long 0x00 2. "TEMP3_INJ,TEMP3 Error Injection" "0: TEMP3 Error Injection Disable,1: TEMP3 Error Injection Enable"
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bitfld.long 0x00 1. "TEMP2_INJ,TEMP2 Error Injection" "0: TEMP2 Error Injection Disable,1: TEMP2 Error Injection Enable"
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bitfld.long 0x00 0. "TEMP1_INJ,TEMP1 Error Injection" "0: TEMP1 Error Injection Disable,1: TEMP1 Error Injection Enable"
group.long 0x74++0x03
line.long 0x00 "TSC_ERROR_CTL1,"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are fixed to 0"
newline
bitfld.long 0x00 0. "TSC_ERR_CTL,TSC error injection" "0: Error injection disable,1: Error injection enable"
group.long 0x7C++0x03
line.long 0x00 "SEQ_RESET1,"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are fixed to 0"
newline
bitfld.long 0x00 0. "SEQ_RESET,This bit initializes the sequence and error value" "0,1"
group.long 0x8C++0x03
line.long 0x00 "CIVMTST_VOLT11,"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,These bits are fixed to 0"
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hexmask.long.word 0x00 0.--13. 1. "CIVMTST_VOLT1_CODE_YN_13_0,These bits indicate the digital value detected by the chip internal voltage monitor during CIVM test mode1"
group.long 0x98++0x03
line.long 0x00 "CIVMTST_VOLT41,"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,These bits are fixed to 0"
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hexmask.long.word 0x00 0.--13. 1. "CIVMTST_VOLT4_CODE_YN_13_0,These bits indicate the digital value detected by the chip internal voltage monitor during CIVM test mode4"
group.long 0x9C++0x03
line.long 0x00 "MANTST_VOLT1,"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,These bits are fixed to 0"
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hexmask.long.word 0x00 0.--13. 1. "MANTST_VOLT_CODE_YN_13_0,These bits indicate the digital value detected by the chip internal voltage monitor during Manual test mode"
group.long 0xC0++0x03
line.long 0x00 "THS_MANUAL_SET1,"
bitfld.long 0x00 31. "CTRSEL,Select control of THS/CIVM" "0: THS/CVM is controlled by Finite State Machine,1: THS/CVM is controlled by THS_MANUAL_SET.."
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rbitfld.long 0x00 25.--30. "Reserved_25,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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rbitfld.long 0x00 24. "Reserved_24,Reserved This bit is fixed to 0" "0,1"
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rbitfld.long 0x00 23. "Reserved_23,Reserved This bit is fixed to 0" "0,1"
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bitfld.long 0x00 20.--22. "CTR_THVF0SEL_2_0,ADC InV[A] select" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 19. "Reserved_19,Reserved This bit is fixed to 0" "0,1"
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bitfld.long 0x00 16.--18. "CTR_THVF1SEL_2_0,ADC InV[B] select" "?,?,?,?,4: VTHIU,?,?,7: VTHIL other"
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rbitfld.long 0x00 14.--15. "Reserved_14,Reserved These bits are fixed to 0" "0,1,2,3"
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rbitfld.long 0x00 12.--13. "Reserved_12,Reserved These bits are fixed to 0" "0,1,2,3"
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rbitfld.long 0x00 10.--11. "Reserved_10,Reserved These bits are fixed to 0" "0,1,2,3"
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rbitfld.long 0x00 8.--9. "Reserved_8,Reserved These bits are fixed to 0" "0,1,2,3"
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hexmask.long.byte 0x00 1.--7. 1. "Reserved_1,Reserved These bits are fixed to 0"
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rbitfld.long 0x00 0. "Reserved_0,Reserved This bit is fixed to 0" "0,1"
group.long 0xF8++0x03
line.long 0x00 "CVM_LOCK,"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are fixed to 0"
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bitfld.long 0x00 0. "VM_LOCK,This bit is implemented for only TSC1 This bit is a signal to lock the values of CVM_CTRL CVM_DETECT_MANUAL_SET CVM_TOFF_MANUAL_SET and CVM_LOCK(itself) registers" "0,1"
group.long 0xFC++0x03
line.long 0x00 "CVM_LOCK_BK,"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are fixed to 0"
newline
rbitfld.long 0x00 0. "R_VM_LOCK,This bit can monitor the readback value of VM_LOCK register This bit is implemented for only TSC1" "0,1"
group.long 0x100++0x03
line.long 0x00 "CVM_LATCH_BK1,"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are fixed to 0"
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rbitfld.long 0x00 0. "R_VMLATCH,Status of configuration lock" "0: CVM_CTRL CVM_DETECT_MANUAL_SET and,1: CVM_CTRL CVM_DETECT_MANUAL_SET and"
group.long 0x104++0x03
line.long 0x00 "CVM_CTRL1,"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are fixed to 0"
newline
rbitfld.long 0x00 16. "Reserved_16,Reserved These bits are fixed to 0" "0,1"
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rbitfld.long 0x00 13.--15. "Reserved_13,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 12. "THBGREN_N,BGR enable" "0: Enabled,1: Disabled This bit"
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rbitfld.long 0x00 9.--11. "Reserved_9,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 8. "OUTPC,This bit is a switching signal for CVM function" "0: Idle mode,1: CVM mode This bit is"
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bitfld.long 0x00 6.--7. "VMFLTFC_1_0,CVM digital output filter function control" "0: see Section 200.8 CVM Characteristics,1: see Section 200.8 CVM Characteristics,2: see Section 200.8 CVM Characteristics,3: filter skip This bit is implemented for only.."
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rbitfld.long 0x00 5. "Reserved_5,Reserved This bit is fixed to 0" "0,1"
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rbitfld.long 0x00 4. "Reserved_4,Reserved This bit is fixed to 0" "0,1"
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bitfld.long 0x00 0.--3. "CHOICE_PLACE_3_0,These bits enable or disable each CVM error output CHOICE_PLACE[3] : Writing 1 to this bit is prohibited" "0: disable,1: enable This bit is,?..."
group.long 0x108++0x03
line.long 0x00 "CVM_CTRL_BK1,"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are fixed to 0"
newline
rbitfld.long 0x00 24. "Reserved_24,Reserved This bit is fixed to 0" "0,1"
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hexmask.long.byte 0x00 17.--23. 1. "Reserved_17,Reserved These bits are fixed to 0"
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rbitfld.long 0x00 16. "Reserved_16,Reserved This bit is fixed to 0" "0,1"
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rbitfld.long 0x00 13.--15. "Reserved_13,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 12. "R_THBGREN_N,This bit can monitor the readback value of THBGREN_N in CVM_CTRL register" "0,1"
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rbitfld.long 0x00 9.--11. "Reserved_9,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 8. "OUTPC_BK,This bit can monitor the readback value of OUTPC in CVM_CTRL register" "0,1"
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rbitfld.long 0x00 6.--7. "R_VMFLTFC_1_0,This bit can monitor the readback value of VMFITFC in CVM_CTRL register" "0,1,2,3"
newline
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are fixed to 0" "0,1"
newline
rbitfld.long 0x00 4. "Reserved_4,Reserved These bits are fixed to 0" "0,1"
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rbitfld.long 0x00 0.--3. "CHOICE_PLACE_BK_3_0,These bits can monitor the readback value of CHOICE_PLACE [3:0] in CVM_CTRL register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x10C++0x03
line.long 0x00 "CVM_DETECT_MON1,"
rbitfld.long 0x00 26.--31. "Reserved_26,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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rbitfld.long 0x00 24.--25. "MODE_MAX_MON_1_0,Golden reference value for MODE_MAX The value is stored in e-fuse considering analogue characteristics of each die This bit is not implemented for TSC4" "0,1,2,3"
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rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 16.--19. "TRIM_MAX_MON_3_0,Golden reference value for TRIM_MAX The value is stored in e-fuse considering analogue characteristics of each die This bit is not implemented for TSC4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 10.--15. "Reserved_10,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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rbitfld.long 0x00 8.--9. "MODE_MIN_MON_1_0,Golden reference value for MODE_MIN The value is stored in e-fuse considering analogue characteristics of each die This bit is not implemented for TSC4" "0,1,2,3"
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rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 0.--3. "TRIM_MIN_MON_3_0,Golden reference value for TRIM_MIN The value is stored in e-fuse considering analogue characteristics of each die This bit is not implemented for TSC4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x110++0x03
line.long 0x00 "CVM_DETECT_MANUAL_SET1,"
rbitfld.long 0x00 29.--31. "Reserved_29,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 28. "CVM_DETECT_SEL_MAX,This bit selects either CVM_DETECT_MON register or CVM_MANUAL_SET register" "0: The values of bits 25 to 24 and bits 18 to 16..,1: The values of bits 25 to 24 and bits 18 to 16.."
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rbitfld.long 0x00 26.--27. "Reserved_26,Reserved This bit is fixed to 0" "0,1,2,3"
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bitfld.long 0x00 24.--25. "MODE_MAX_1_0,Coase grain overvoltage threshold setting" "0,1,2,3"
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rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "TRIM_MAX_3_0,Fine grain overvoltage threshold setting (available only when CVM_DETECT_SEL_MAX = 1.) This bit is not implemented for TSC4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 13.--15. "Reserved_13,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 12. "CVM_DETECT_SEL_MIN,This bit selects either CVM_DETECT_MON register or CVM_MANUAL_SET register" "0: The values of bits 9 to 8 and bits 2 to 0 in,1: The values of bits 9 to 8 and bits 2 to 0 in"
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rbitfld.long 0x00 10.--11. "Reserved_10,Reserved This bit is fixed to 0" "0,1,2,3"
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bitfld.long 0x00 8.--9. "MODE_MIN_1_0,Coase grain undervoltage threshold setting" "0,1,2,3"
newline
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "TRIM_MIN_3_0,Fine grain undervoltage threshold setting (available only when CVM_DETECT_SEL_MIN = 1.) This bit is not implemented for TSC4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x114++0x03
line.long 0x00 "CVM_DETECT_SET_BK1,"
rbitfld.long 0x00 26.--31. "Reserved_26,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 24.--25. "MODE_MAX_BK_1_0,These bits can monitor the readback value of MODE_MAX[1:0]" "0,1,2,3"
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rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 16.--19. "TRIM_MAX_BK_3_0,These bits can monitor the readback value of TRIM_MAX[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 10.--15. "Reserved_10,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 8.--9. "MODE_MIN_BK_1_0,These bits can monitor the readback value of MODE_MIN[1:0]" "0,1,2,3"
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rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 0.--3. "TRIM_MIN_BK_3_0,These bits can monitor the readback value of TRIM_MIN[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x118++0x03
line.long 0x00 "CVM_TOFF_MON1,"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved These bits are fixed to 0"
newline
rbitfld.long 0x00 0.--3. "TOFF_MON_3_0,Golden reference value for TOFF The value is stored in e-fuse considering analogue characteristics of each die This bit is not implemented for TSC4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x11C++0x03
line.long 0x00 "CVM_TOFF_MANUAL_SET1,"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved These bits are fixed to 0"
newline
bitfld.long 0x00 12. "TOFF_SEL,This bit selects either CVM_TOFF_MON register or CVM_TOFF_MANUAL_SET register" "0: Select value that bit 3 to 0 in CVM_TOFF_MON,1: Select value that bit 3 to 0 in"
newline
hexmask.long.byte 0x00 4.--11. 1. "Reserved_4,Reserved These bits are fixed to 0"
newline
bitfld.long 0x00 0.--3. "TOFF_3_0,CVM temperature compensation setting (available only when TOFF_SEL = 1.) This bit is not implemented for TSC4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x120++0x03
line.long 0x00 "CVM_TOFF_BK1,"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved These bits are fixed to 0"
newline
rbitfld.long 0x00 0.--3. "TOFF_BK_3_0,These bits can monitor the readback value of TOFF[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x124++0x03
line.long 0x00 "CVM_VMOUT_BK,"
hexmask.long 0x00 2.--31. 1. "Reserved_2,Reserved These bits are fixed to 0"
newline
rbitfld.long 0x00 0.--1. "VMOUT_BK_1_0,These bits can monitor the switch signal of analog voltage" "0: Undervoltage,1: Normal,2: Illegal,3: Overvoltage This bit is"
group.long 0x130++0x03
line.long 0x00 "TSC_ERROR_MON1,"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are fixed to 0"
newline
rbitfld.long 0x00 7. "ERR_ACKTOV,THACK timeout error status" "0: no error,1: THACK timeout error"
newline
rbitfld.long 0x00 6. "Reserved_6,Reserved This bit is fixed to 0" "0,1"
newline
rbitfld.long 0x00 5. "Reserved_5,Reserved This bit is fixed to 0" "0,1"
newline
rbitfld.long 0x00 4. "ERR_THCODE,THCODE error status Indicates that THCODE is all 0 or all F" "0: no error,1: THCODE error"
newline
rbitfld.long 0x00 3. "ERR_THCNTOV,THCNTOV error status Indicates that the counter overflowed" "0: no error,1: THCNTOV error"
newline
rbitfld.long 0x00 2. "THFAIL1,This bit is set to 1 when all of the THCODE bits are 1" "0: Normal operation,1: All of the THCODE bits are all 1"
newline
rbitfld.long 0x00 1. "THFAIL0,This bit is set to 1 when all of the THCODE bits are 0" "0: Normal operation,1: All of the THCODE bits are all 0"
newline
rbitfld.long 0x00 0. "TSC_ERROR,TSC error status TSC error is 1 if one or more of ERR_ACKTOV ERR_THCODE ERR_THCNTOV THFAIL1 and THFAIL0 errors are detected" "0: no error,1: TSC error"
group.long 0x138++0x03
line.long 0x00 "MANTST_SET_DT1,"
rbitfld.long 0x00 29.--31. "Reserved_29,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 28. "MANTST,Manual test mode" "0: Normal mode,1: Manual test mode This bit is"
newline
rbitfld.long 0x00 23.--27. "Reserved_23,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 20.--22. "MAN_THVF0SEL_2_0,ADC InV[A] select for manual test" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 19. "Reserved_19,Reserved These bits are fixed to 0" "0,1"
newline
bitfld.long 0x00 16.--18. "MAN_THVF1SEL_2_0,ADC InV[B] select for manual test" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 14.--15. "Reserved_14,Reserved These bits are fixed to 0" "0,1,2,3"
newline
rbitfld.long 0x00 12.--13. "Reserved_12,Reserved These bits are fixed to 0" "0,1,2,3"
newline
rbitfld.long 0x00 10.--11. "Reserved_10,Reserved These bits are fixed to 0" "0,1,2,3"
newline
rbitfld.long 0x00 8.--9. "Reserved_8,Reserved These bits are fixed to 0" "0,1,2,3"
newline
hexmask.long.byte 0x00 0.--7. 1. "Reserved_0,Reserved These bits are fixed to 0"
group.long 0x140++0x03
line.long 0x00 "SEQ_ACT_MON1,"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved These bits are fixed to 0"
newline
rbitfld.long 0x00 0.--3. "SEQ_ACT_3_0,Sequence Act Flag monitor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x144++0x03
line.long 0x00 "VMMSK_CTRL,"
hexmask.long 0x00 3.--31. 1. "Reserved_3,Reserved These bits are fixed to 0"
newline
bitfld.long 0x00 2. "CVMC_MSK_CTL_N,This bit selects masking or non-masking of CVM error at thermal sensor #3 module" "0: CVM error is masked,1: The mask is cleared"
newline
bitfld.long 0x00 1. "CVMB_MSKCTL_N,This bit selects masking or non-masking of CVM error at thermal sensor #2 module" "0: CVM error is masked,1: The mask is cleared"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are fixed to 0" "0,1"
group.long 0x180++0x03
line.long 0x00 "THSFMON001,"
rbitfld.long 0x00 28.--31. "Reserved_28,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 16.--27. 1. "Reserved_16,Reserved These bits are indefinite"
newline
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--11. 1. "THCODE_L_SR1_11_0,Parameter to be used in adjusting the characteristics Refer to 13.3.3.4 13.3.3.6 section"
group.long 0x184++0x03
line.long 0x00 "THSFMON011,"
rbitfld.long 0x00 28.--31. "Reserved_28,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 16.--27. 1. "Reserved_16,Reserved These bits are indefinite"
newline
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--11. 1. "THCODE_U_SR1_11_0,Parameter to be used in adjusting the characteristics Refer to 13.3.3.4 13.3.3.6 section"
group.long 0x188++0x03
line.long 0x00 "THSFMON021,"
rbitfld.long 0x00 28.--31. "Reserved_28,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 16.--27. 1. "Reserved_16,Reserved These bits are indefinite"
newline
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--11. 1. "THCODE_R_SR1_11_0,Parameter to be used in adjusting the characteristics Refer to 13.3.3.4 13.3.3.6 section"
group.long 0x1BC++0x03
line.long 0x00 "THSFMON15,"
rbitfld.long 0x00 28.--31. "Reserved_28,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 16.--27. 1. "Reserved_16,Reserved These bits are indefinite"
newline
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--11. 1. "PTAT_PF_L_SR1_11_0,Parameter to be used in adjusting the characteristics Refer to 13.3.3.4 13.3.3.6 section"
group.long 0x1C0++0x03
line.long 0x00 "THSFMON16,"
rbitfld.long 0x00 28.--31. "Reserved_28,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 16.--27. 1. "Reserved_16,Reserved These bits are indefinite"
newline
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--11. 1. "PTAT_PF_U_SR1_11_0,Parameter to be used in adjusting the characteristics Refer to 13.3.3.4 13.3.3.6 section"
group.long 0x1C4++0x03
line.long 0x00 "THSFMON17,"
rbitfld.long 0x00 28.--31. "Reserved_28,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 16.--27. 1. "Reserved_16,Reserved These bits are indefinite"
newline
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--11. 1. "PTAT_PF_R_SR1_11_0,Parameter to be used in adjusting the characteristics Refer to 13.3.3.4 13.3.3.6 section"
tree.end
tree "THS_INST_1"
base ad:0xE61A0000
group.long 0x04++0x03
line.long 0x00 "IRQSTR2,"
hexmask.long 0x00 6.--31. 1. "Reserved_6,Reserved These bits are fixed to 0"
newline
bitfld.long 0x00 5. "TEMPD3_STR,TEMPD3 Detection Status" "0: Not detected,1: TEMP_CODE [11:0] bits detect that"
newline
bitfld.long 0x00 4. "TEMPD2_STR,TEMPD2 Detection Status" "0: Not detected,1: TEMP_CODE [11:0] bits detect that"
newline
bitfld.long 0x00 3. "TEMPD1_STR,TEMPD1 Detection Status" "0: Not detected,1: TEMP_CODE [11:0] bits detect that"
newline
bitfld.long 0x00 2. "TEMP3_STR,TEMP3 Detection Status" "0: Not detected,1: TEMP_CODE [11:0] bits detect that"
newline
bitfld.long 0x00 1. "TEMP2_STR,TEMP2 Detection Status" "0: Not detected,1: TEMP_CODE [11:0] bits detect that"
newline
bitfld.long 0x00 0. "TEMP1_STR,TEMP1 Detection Status" "0: Not detected,1: TEMP_CODE [11:0] bits detect that"
group.long 0x08++0x03
line.long 0x00 "IRQMSK2,"
hexmask.long 0x00 6.--31. 1. "Reserved_6,Reserved These bits are fixed to 0"
newline
bitfld.long 0x00 5. "TEMPD3_MSK,This bit selects masking or non-masking of TEMPD3 error requests" "0: Errors are masked,1: The mask is cleared"
newline
bitfld.long 0x00 4. "TEMPD2_MSK,This bit selects masking or non-masking of TEMPD2 error requests" "0: Errors are masked,1: The mask is cleared"
newline
bitfld.long 0x00 3. "TEMPD1_MSK,This bit selects masking or non-masking of TEMPD1 error requests" "0: Errors are masked,1: The mask is cleared"
newline
bitfld.long 0x00 2. "TEMP3_MSK,This bit selects masking or non-masking of TEMP3 error requests" "0: Errors are masked,1: The mask is cleared"
newline
bitfld.long 0x00 1. "TEMP2_MSK,This bit selects masking or non-masking of TEMP2 error requests" "0: Errors are masked,1: The mask is cleared"
newline
bitfld.long 0x00 0. "TEMP1_MSK,This bit selects masking or non-masking of TEMP1 error requests" "0: Errors are masked,1: The mask is cleared"
group.long 0x10++0x03
line.long 0x00 "IRQEN2,"
hexmask.long 0x00 6.--31. 1. "Reserved_6,Reserved These bits are fixed to 0"
newline
bitfld.long 0x00 5. "TEMPD3_EN,This bit enables or disables TEMPD3 errors" "0: TEMPD3 errors are disabled,1: TEMPD3 errors are enabled"
newline
bitfld.long 0x00 4. "TEMPD2_EN,This bit enables or disables TEMPD2 errors" "0: TEMPD2 errors are disabled,1: TEMPD2 errors are enabled"
newline
bitfld.long 0x00 3. "TEMPD1_EN,This bit enables or disables TEMPD1 errors" "0: TEMPD1 errors are disabled,1: TEMPD1 errors are enabled"
newline
bitfld.long 0x00 2. "TEMP3_EN,This bit enables or disables TEMP3 errors" "0: TEMP3 errors are disabled,1: TEMP3 errors are enabled"
newline
bitfld.long 0x00 1. "TEMP2_EN,This bit enables or disables TEMP2 errors" "0: TEMP2 errors are disabled,1: TEMP2 errors are enabled"
newline
bitfld.long 0x00 0. "TEMP1_EN,This bit enables or disables TEMP1 errors" "0: TEMP1 errors are disabled,1: TEMP1 errors are enabled"
group.long 0x14++0x03
line.long 0x00 "IRQTEMP12,"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are fixed to 0"
newline
rbitfld.long 0x00 12.--13. "Reserved_12,Reserved These bits are fixed to 0" "0,1,2,3"
newline
hexmask.long.word 0x00 0.--11. 1. "IRQTEMP1_11_0,These bits set the first threshold value of the temperature for TEMP1 and TEMPD1 errors"
group.long 0x18++0x03
line.long 0x00 "IRQTEMP22,"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are fixed to 0"
newline
rbitfld.long 0x00 12.--13. "Reserved_12,Reserved These bits are fixed to 0" "0,1,2,3"
newline
hexmask.long.word 0x00 0.--11. 1. "IRQTEMP2_11_0,These bits set the second threshold value of the temperature for TEMP2 and TEMPD2 errors"
group.long 0x1C++0x03
line.long 0x00 "IRQTEMP32,"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are fixed to 0"
newline
rbitfld.long 0x00 12.--13. "Reserved_12,Reserved These bits are fixed to 0" "0,1,2,3"
newline
hexmask.long.word 0x00 0.--11. 1. "IRQTEMP3_11_0,These bits set the third threshold value of the temperature for TEMP3 and TEMPD3 errors"
group.long 0x20++0x03
line.long 0x00 "THCTR2,"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are fixed to 0"
newline
rbitfld.long 0x00 24. "Reserved_24,Reserved These bits are fixed to 0" "0,1"
newline
rbitfld.long 0x00 21.--23. "Reserved_21,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 20. "CIVMTST,THS/CIVM failure check mode" "0: Normal mode,1: THS/CIVM failure check mode"
newline
rbitfld.long 0x00 18.--19. "Reserved_18,Reserved These bits are fixed to 0" "0,1,2,3"
newline
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are fixed to 0" "0,1,2,3"
newline
rbitfld.long 0x00 10.--15. "Reserved_10,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--9. "SENSSEL_1_0,Select the use sensor" "0: THS CIVM both ON,1: THS ON only,2: CIVM ON only,3: THS CIVM both ON (this setting is the"
newline
rbitfld.long 0x00 6.--7. "Reserved_6,Reserved These bits are fixed to 0" "0,1,2,3"
newline
bitfld.long 0x00 5. "TH_EN_B,THS/CIVM enable" "0: Enabled,1: Disabled"
newline
bitfld.long 0x00 1.--4. "Reserved_1,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0. "THSST,Enabling/disabling of the A/D converter for the thermal sensor" "0: Disabled,1: Enabled"
group.long 0x24++0x03
line.long 0x00 "THSTR2,"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved These bits are fixed to 0"
newline
rbitfld.long 0x00 3. "THACKMON,THACK signal monitor Indicates that the THCODE was generated" "0: Not detected,1: THCODE was generated"
newline
rbitfld.long 0x00 2. "THCNTOV_MON,THCNTOV signal monitor Indicates that the counter overflowed" "0: Not detected,1: Detected overflow"
newline
rbitfld.long 0x00 1. "THFAIL1,This bit is set to 1 when all of the THCODE bits are 1" "0: Normal operation,1: All of the THCODE bits are all 1"
newline
rbitfld.long 0x00 0. "THFAIL0,This bit is set to 1 when all of the THCODE bits are 0" "0: Normal operation,1: All of the THCODE bits are all 0"
group.long 0x28++0x03
line.long 0x00 "TEMP2,"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are fixed to 0"
newline
rbitfld.long 0x00 12.--13. "Reserved_12,Reserved These bits are fixed to 0" "0,1,2,3"
newline
hexmask.long.word 0x00 0.--11. 1. "TEMP_CODE_11_0,These bits indicate the digital value for the temperature detected by the thermal sensor"
group.long 0x2C++0x03
line.long 0x00 "VOLT2,"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are fixed to 0"
newline
rbitfld.long 0x00 10.--13. "Reserved_10,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--9. 1. "VOLT_CODE_9_0,These bits indicate the digital value for the voltage detected by the chip internal voltage monitor"
group.long 0x6C++0x03
line.long 0x00 "IRQ_INJECTION2,"
hexmask.long 0x00 6.--31. 1. "Reserved_6,Reserved These bits are fixed to 0"
newline
bitfld.long 0x00 5. "TEMPD3_INJ,TEMPD3 Error Injection" "0: TEMPD3 Error Injection Disable,1: TEMPD3 Error Injection Enable"
newline
bitfld.long 0x00 4. "TEMPD2_INJ,TEMPD2 Error Injection" "0: TEMPD2 Error Injection Disable,1: TEMPD2 Error Injection Enable"
newline
bitfld.long 0x00 3. "TEMPD1_INJ,TEMPD1 Error Injection" "0: TEMPD1 Error Injection Disable,1: TEMPD1 Error Injection Enable"
newline
bitfld.long 0x00 2. "TEMP3_INJ,TEMP3 Error Injection" "0: TEMP3 Error Injection Disable,1: TEMP3 Error Injection Enable"
newline
bitfld.long 0x00 1. "TEMP2_INJ,TEMP2 Error Injection" "0: TEMP2 Error Injection Disable,1: TEMP2 Error Injection Enable"
newline
bitfld.long 0x00 0. "TEMP1_INJ,TEMP1 Error Injection" "0: TEMP1 Error Injection Disable,1: TEMP1 Error Injection Enable"
group.long 0x74++0x03
line.long 0x00 "TSC_ERROR_CTL2,"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are fixed to 0"
newline
bitfld.long 0x00 0. "TSC_ERR_CTL,TSC error injection" "0: Error injection disable,1: Error injection enable"
group.long 0x7C++0x03
line.long 0x00 "SEQ_RESET2,"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are fixed to 0"
newline
bitfld.long 0x00 0. "SEQ_RESET,This bit initializes the sequence and error value" "0,1"
group.long 0x8C++0x03
line.long 0x00 "CIVMTST_VOLT12,"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,These bits are fixed to 0"
newline
hexmask.long.word 0x00 0.--13. 1. "CIVMTST_VOLT1_CODE_YN_13_0,These bits indicate the digital value detected by the chip internal voltage monitor during CIVM test mode1"
group.long 0x98++0x03
line.long 0x00 "CIVMTST_VOLT42,"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,These bits are fixed to 0"
newline
hexmask.long.word 0x00 0.--13. 1. "CIVMTST_VOLT4_CODE_YN_13_0,These bits indicate the digital value detected by the chip internal voltage monitor during CIVM test mode4"
group.long 0x9C++0x03
line.long 0x00 "MANTST_VOLT2,"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,These bits are fixed to 0"
newline
hexmask.long.word 0x00 0.--13. 1. "MANTST_VOLT_CODE_YN_13_0,These bits indicate the digital value detected by the chip internal voltage monitor during Manual test mode"
group.long 0xC0++0x03
line.long 0x00 "THS_MANUAL_SET2,"
bitfld.long 0x00 31. "CTRSEL,Select control of THS/CIVM" "0: THS/CVM is controlled by Finite State Machine,1: THS/CVM is controlled by THS_MANUAL_SET.."
newline
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 24. "Reserved_24,Reserved This bit is fixed to 0" "0,1"
newline
rbitfld.long 0x00 23. "Reserved_23,Reserved This bit is fixed to 0" "0,1"
newline
bitfld.long 0x00 20.--22. "CTR_THVF0SEL_2_0,ADC InV[A] select" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 19. "Reserved_19,Reserved This bit is fixed to 0" "0,1"
newline
bitfld.long 0x00 16.--18. "CTR_THVF1SEL_2_0,ADC InV[B] select" "?,?,?,?,4: VTHIU,?,?,7: VTHIL other"
newline
rbitfld.long 0x00 14.--15. "Reserved_14,Reserved These bits are fixed to 0" "0,1,2,3"
newline
rbitfld.long 0x00 12.--13. "Reserved_12,Reserved These bits are fixed to 0" "0,1,2,3"
newline
rbitfld.long 0x00 10.--11. "Reserved_10,Reserved These bits are fixed to 0" "0,1,2,3"
newline
rbitfld.long 0x00 8.--9. "Reserved_8,Reserved These bits are fixed to 0" "0,1,2,3"
newline
hexmask.long.byte 0x00 1.--7. 1. "Reserved_1,Reserved These bits are fixed to 0"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved This bit is fixed to 0" "0,1"
group.long 0x100++0x03
line.long 0x00 "CVM_LATCH_BK2,"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are fixed to 0"
newline
rbitfld.long 0x00 0. "R_VMLATCH,Status of configuration lock" "0: CVM_CTRL CVM_DETECT_MANUAL_SET and,1: CVM_CTRL CVM_DETECT_MANUAL_SET and"
group.long 0x104++0x03
line.long 0x00 "CVM_CTRL2,"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are fixed to 0"
newline
rbitfld.long 0x00 16. "Reserved_16,Reserved These bits are fixed to 0" "0,1"
newline
rbitfld.long 0x00 13.--15. "Reserved_13,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 12. "THBGREN_N,BGR enable" "0: Enabled,1: Disabled This bit"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 8. "OUTPC,This bit is a switching signal for CVM function" "0: Idle mode,1: CVM mode This bit is"
newline
bitfld.long 0x00 6.--7. "VMFLTFC_1_0,CVM digital output filter function control" "0: see Section 200.8 CVM Characteristics,1: see Section 200.8 CVM Characteristics,2: see Section 200.8 CVM Characteristics,3: filter skip This bit is implemented for only.."
newline
rbitfld.long 0x00 5. "Reserved_5,Reserved This bit is fixed to 0" "0,1"
newline
rbitfld.long 0x00 4. "Reserved_4,Reserved This bit is fixed to 0" "0,1"
newline
bitfld.long 0x00 0.--3. "CHOICE_PLACE_3_0,These bits enable or disable each CVM error output CHOICE_PLACE[3] : Writing 1 to this bit is prohibited" "0: disable,1: enable This bit is,?..."
group.long 0x108++0x03
line.long 0x00 "CVM_CTRL_BK2,"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are fixed to 0"
newline
rbitfld.long 0x00 24. "Reserved_24,Reserved This bit is fixed to 0" "0,1"
newline
hexmask.long.byte 0x00 17.--23. 1. "Reserved_17,Reserved These bits are fixed to 0"
newline
rbitfld.long 0x00 16. "Reserved_16,Reserved This bit is fixed to 0" "0,1"
newline
rbitfld.long 0x00 13.--15. "Reserved_13,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 12. "R_THBGREN_N,This bit can monitor the readback value of THBGREN_N in CVM_CTRL register" "0,1"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 8. "OUTPC_BK,This bit can monitor the readback value of OUTPC in CVM_CTRL register" "0,1"
newline
rbitfld.long 0x00 6.--7. "R_VMFLTFC_1_0,This bit can monitor the readback value of VMFITFC in CVM_CTRL register" "0,1,2,3"
newline
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are fixed to 0" "0,1"
newline
rbitfld.long 0x00 4. "Reserved_4,Reserved These bits are fixed to 0" "0,1"
newline
rbitfld.long 0x00 0.--3. "CHOICE_PLACE_BK_3_0,These bits can monitor the readback value of CHOICE_PLACE [3:0] in CVM_CTRL register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x10C++0x03
line.long 0x00 "CVM_DETECT_MON2,"
rbitfld.long 0x00 26.--31. "Reserved_26,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 24.--25. "MODE_MAX_MON_1_0,Golden reference value for MODE_MAX The value is stored in e-fuse considering analogue characteristics of each die This bit is not implemented for TSC4" "0,1,2,3"
newline
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 16.--19. "TRIM_MAX_MON_3_0,Golden reference value for TRIM_MAX The value is stored in e-fuse considering analogue characteristics of each die This bit is not implemented for TSC4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 10.--15. "Reserved_10,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 8.--9. "MODE_MIN_MON_1_0,Golden reference value for MODE_MIN The value is stored in e-fuse considering analogue characteristics of each die This bit is not implemented for TSC4" "0,1,2,3"
newline
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 0.--3. "TRIM_MIN_MON_3_0,Golden reference value for TRIM_MIN The value is stored in e-fuse considering analogue characteristics of each die This bit is not implemented for TSC4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x110++0x03
line.long 0x00 "CVM_DETECT_MANUAL_SET2,"
rbitfld.long 0x00 29.--31. "Reserved_29,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 28. "CVM_DETECT_SEL_MAX,This bit selects either CVM_DETECT_MON register or CVM_MANUAL_SET register" "0: The values of bits 25 to 24 and bits 18 to 16..,1: The values of bits 25 to 24 and bits 18 to 16.."
newline
rbitfld.long 0x00 26.--27. "Reserved_26,Reserved This bit is fixed to 0" "0,1,2,3"
newline
bitfld.long 0x00 24.--25. "MODE_MAX_1_0,Coase grain overvoltage threshold setting" "0,1,2,3"
newline
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 16.--19. "TRIM_MAX_3_0,Fine grain overvoltage threshold setting (available only when CVM_DETECT_SEL_MAX = 1.) This bit is not implemented for TSC4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 13.--15. "Reserved_13,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 12. "CVM_DETECT_SEL_MIN,This bit selects either CVM_DETECT_MON register or CVM_MANUAL_SET register" "0: The values of bits 9 to 8 and bits 2 to 0 in,1: The values of bits 9 to 8 and bits 2 to 0 in"
newline
rbitfld.long 0x00 10.--11. "Reserved_10,Reserved This bit is fixed to 0" "0,1,2,3"
newline
bitfld.long 0x00 8.--9. "MODE_MIN_1_0,Coase grain undervoltage threshold setting" "0,1,2,3"
newline
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "TRIM_MIN_3_0,Fine grain undervoltage threshold setting (available only when CVM_DETECT_SEL_MIN = 1.) This bit is not implemented for TSC4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x114++0x03
line.long 0x00 "CVM_DETECT_SET_BK2,"
rbitfld.long 0x00 26.--31. "Reserved_26,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 24.--25. "MODE_MAX_BK_1_0,These bits can monitor the readback value of MODE_MAX[1:0]" "0,1,2,3"
newline
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 16.--19. "TRIM_MAX_BK_3_0,These bits can monitor the readback value of TRIM_MAX[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 10.--15. "Reserved_10,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 8.--9. "MODE_MIN_BK_1_0,These bits can monitor the readback value of MODE_MIN[1:0]" "0,1,2,3"
newline
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 0.--3. "TRIM_MIN_BK_3_0,These bits can monitor the readback value of TRIM_MIN[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x118++0x03
line.long 0x00 "CVM_TOFF_MON2,"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved These bits are fixed to 0"
newline
rbitfld.long 0x00 0.--3. "TOFF_MON_3_0,Golden reference value for TOFF The value is stored in e-fuse considering analogue characteristics of each die This bit is not implemented for TSC4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x11C++0x03
line.long 0x00 "CVM_TOFF_MANUAL_SET2,"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved These bits are fixed to 0"
newline
bitfld.long 0x00 12. "TOFF_SEL,This bit selects either CVM_TOFF_MON register or CVM_TOFF_MANUAL_SET register" "0: Select value that bit 3 to 0 in CVM_TOFF_MON,1: Select value that bit 3 to 0 in"
newline
hexmask.long.byte 0x00 4.--11. 1. "Reserved_4,Reserved These bits are fixed to 0"
newline
bitfld.long 0x00 0.--3. "TOFF_3_0,CVM temperature compensation setting (available only when TOFF_SEL = 1.) This bit is not implemented for TSC4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x120++0x03
line.long 0x00 "CVM_TOFF_BK2,"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved These bits are fixed to 0"
newline
rbitfld.long 0x00 0.--3. "TOFF_BK_3_0,These bits can monitor the readback value of TOFF[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x130++0x03
line.long 0x00 "TSC_ERROR_MON2,"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are fixed to 0"
newline
rbitfld.long 0x00 7. "ERR_ACKTOV,THACK timeout error status" "0: no error,1: THACK timeout error"
newline
rbitfld.long 0x00 6. "Reserved_6,Reserved This bit is fixed to 0" "0,1"
newline
rbitfld.long 0x00 5. "Reserved_5,Reserved This bit is fixed to 0" "0,1"
newline
rbitfld.long 0x00 4. "ERR_THCODE,THCODE error status Indicates that THCODE is all 0 or all F" "0: no error,1: THCODE error"
newline
rbitfld.long 0x00 3. "ERR_THCNTOV,THCNTOV error status Indicates that the counter overflowed" "0: no error,1: THCNTOV error"
newline
rbitfld.long 0x00 2. "THFAIL1,This bit is set to 1 when all of the THCODE bits are 1" "0: Normal operation,1: All of the THCODE bits are all 1"
newline
rbitfld.long 0x00 1. "THFAIL0,This bit is set to 1 when all of the THCODE bits are 0" "0: Normal operation,1: All of the THCODE bits are all 0"
newline
rbitfld.long 0x00 0. "TSC_ERROR,TSC error status TSC error is 1 if one or more of ERR_ACKTOV ERR_THCODE ERR_THCNTOV THFAIL1 and THFAIL0 errors are detected" "0: no error,1: TSC error"
group.long 0x138++0x03
line.long 0x00 "MANTST_SET_DT2,"
rbitfld.long 0x00 29.--31. "Reserved_29,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 28. "MANTST,Manual test mode" "0: Normal mode,1: Manual test mode This bit is"
newline
rbitfld.long 0x00 23.--27. "Reserved_23,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 20.--22. "MAN_THVF0SEL_2_0,ADC InV[A] select for manual test" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 19. "Reserved_19,Reserved These bits are fixed to 0" "0,1"
newline
bitfld.long 0x00 16.--18. "MAN_THVF1SEL_2_0,ADC InV[B] select for manual test" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 14.--15. "Reserved_14,Reserved These bits are fixed to 0" "0,1,2,3"
newline
rbitfld.long 0x00 12.--13. "Reserved_12,Reserved These bits are fixed to 0" "0,1,2,3"
newline
rbitfld.long 0x00 10.--11. "Reserved_10,Reserved These bits are fixed to 0" "0,1,2,3"
newline
rbitfld.long 0x00 8.--9. "Reserved_8,Reserved These bits are fixed to 0" "0,1,2,3"
newline
hexmask.long.byte 0x00 0.--7. 1. "Reserved_0,Reserved These bits are fixed to 0"
group.long 0x140++0x03
line.long 0x00 "SEQ_ACT_MON2,"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved These bits are fixed to 0"
newline
rbitfld.long 0x00 0.--3. "SEQ_ACT_3_0,Sequence Act Flag monitor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x180++0x03
line.long 0x00 "THSFMON002,"
rbitfld.long 0x00 28.--31. "Reserved_28,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 16.--27. 1. "Reserved_16,Reserved These bits are indefinite"
newline
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--11. 1. "THCODE_L_SR1_11_0,Parameter to be used in adjusting the characteristics Refer to 13.3.3.4 13.3.3.6 section"
group.long 0x184++0x03
line.long 0x00 "THSFMON012,"
rbitfld.long 0x00 28.--31. "Reserved_28,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 16.--27. 1. "Reserved_16,Reserved These bits are indefinite"
newline
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--11. 1. "THCODE_U_SR1_11_0,Parameter to be used in adjusting the characteristics Refer to 13.3.3.4 13.3.3.6 section"
group.long 0x188++0x03
line.long 0x00 "THSFMON022,"
rbitfld.long 0x00 28.--31. "Reserved_28,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 16.--27. 1. "Reserved_16,Reserved These bits are indefinite"
newline
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--11. 1. "THCODE_R_SR1_11_0,Parameter to be used in adjusting the characteristics Refer to 13.3.3.4 13.3.3.6 section"
tree.end
tree "THS_INST_2"
base ad:0xE61A8000
group.long 0x04++0x03
line.long 0x00 "IRQSTR3,"
hexmask.long 0x00 6.--31. 1. "Reserved_6,Reserved These bits are fixed to 0"
newline
bitfld.long 0x00 5. "TEMPD3_STR,TEMPD3 Detection Status" "0: Not detected,1: TEMP_CODE [11:0] bits detect that"
newline
bitfld.long 0x00 4. "TEMPD2_STR,TEMPD2 Detection Status" "0: Not detected,1: TEMP_CODE [11:0] bits detect that"
newline
bitfld.long 0x00 3. "TEMPD1_STR,TEMPD1 Detection Status" "0: Not detected,1: TEMP_CODE [11:0] bits detect that"
newline
bitfld.long 0x00 2. "TEMP3_STR,TEMP3 Detection Status" "0: Not detected,1: TEMP_CODE [11:0] bits detect that"
newline
bitfld.long 0x00 1. "TEMP2_STR,TEMP2 Detection Status" "0: Not detected,1: TEMP_CODE [11:0] bits detect that"
newline
bitfld.long 0x00 0. "TEMP1_STR,TEMP1 Detection Status" "0: Not detected,1: TEMP_CODE [11:0] bits detect that"
group.long 0x08++0x03
line.long 0x00 "IRQMSK3,"
hexmask.long 0x00 6.--31. 1. "Reserved_6,Reserved These bits are fixed to 0"
newline
bitfld.long 0x00 5. "TEMPD3_MSK,This bit selects masking or non-masking of TEMPD3 error requests" "0: Errors are masked,1: The mask is cleared"
newline
bitfld.long 0x00 4. "TEMPD2_MSK,This bit selects masking or non-masking of TEMPD2 error requests" "0: Errors are masked,1: The mask is cleared"
newline
bitfld.long 0x00 3. "TEMPD1_MSK,This bit selects masking or non-masking of TEMPD1 error requests" "0: Errors are masked,1: The mask is cleared"
newline
bitfld.long 0x00 2. "TEMP3_MSK,This bit selects masking or non-masking of TEMP3 error requests" "0: Errors are masked,1: The mask is cleared"
newline
bitfld.long 0x00 1. "TEMP2_MSK,This bit selects masking or non-masking of TEMP2 error requests" "0: Errors are masked,1: The mask is cleared"
newline
bitfld.long 0x00 0. "TEMP1_MSK,This bit selects masking or non-masking of TEMP1 error requests" "0: Errors are masked,1: The mask is cleared"
group.long 0x10++0x03
line.long 0x00 "IRQEN3,"
hexmask.long 0x00 6.--31. 1. "Reserved_6,Reserved These bits are fixed to 0"
newline
bitfld.long 0x00 5. "TEMPD3_EN,This bit enables or disables TEMPD3 errors" "0: TEMPD3 errors are disabled,1: TEMPD3 errors are enabled"
newline
bitfld.long 0x00 4. "TEMPD2_EN,This bit enables or disables TEMPD2 errors" "0: TEMPD2 errors are disabled,1: TEMPD2 errors are enabled"
newline
bitfld.long 0x00 3. "TEMPD1_EN,This bit enables or disables TEMPD1 errors" "0: TEMPD1 errors are disabled,1: TEMPD1 errors are enabled"
newline
bitfld.long 0x00 2. "TEMP3_EN,This bit enables or disables TEMP3 errors" "0: TEMP3 errors are disabled,1: TEMP3 errors are enabled"
newline
bitfld.long 0x00 1. "TEMP2_EN,This bit enables or disables TEMP2 errors" "0: TEMP2 errors are disabled,1: TEMP2 errors are enabled"
newline
bitfld.long 0x00 0. "TEMP1_EN,This bit enables or disables TEMP1 errors" "0: TEMP1 errors are disabled,1: TEMP1 errors are enabled"
group.long 0x14++0x03
line.long 0x00 "IRQTEMP13,"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are fixed to 0"
newline
rbitfld.long 0x00 12.--13. "Reserved_12,Reserved These bits are fixed to 0" "0,1,2,3"
newline
hexmask.long.word 0x00 0.--11. 1. "IRQTEMP1_11_0,These bits set the first threshold value of the temperature for TEMP1 and TEMPD1 errors"
group.long 0x18++0x03
line.long 0x00 "IRQTEMP23,"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are fixed to 0"
newline
rbitfld.long 0x00 12.--13. "Reserved_12,Reserved These bits are fixed to 0" "0,1,2,3"
newline
hexmask.long.word 0x00 0.--11. 1. "IRQTEMP2_11_0,These bits set the second threshold value of the temperature for TEMP2 and TEMPD2 errors"
group.long 0x1C++0x03
line.long 0x00 "IRQTEMP33,"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are fixed to 0"
newline
rbitfld.long 0x00 12.--13. "Reserved_12,Reserved These bits are fixed to 0" "0,1,2,3"
newline
hexmask.long.word 0x00 0.--11. 1. "IRQTEMP3_11_0,These bits set the third threshold value of the temperature for TEMP3 and TEMPD3 errors"
group.long 0x20++0x03
line.long 0x00 "THCTR3,"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are fixed to 0"
newline
rbitfld.long 0x00 24. "Reserved_24,Reserved These bits are fixed to 0" "0,1"
newline
rbitfld.long 0x00 21.--23. "Reserved_21,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 20. "CIVMTST,THS/CIVM failure check mode" "0: Normal mode,1: THS/CIVM failure check mode"
newline
rbitfld.long 0x00 18.--19. "Reserved_18,Reserved These bits are fixed to 0" "0,1,2,3"
newline
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are fixed to 0" "0,1,2,3"
newline
rbitfld.long 0x00 10.--15. "Reserved_10,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--9. "SENSSEL_1_0,Select the use sensor" "0: THS CIVM both ON,1: THS ON only,2: CIVM ON only,3: THS CIVM both ON (this setting is the"
newline
rbitfld.long 0x00 6.--7. "Reserved_6,Reserved These bits are fixed to 0" "0,1,2,3"
newline
bitfld.long 0x00 5. "TH_EN_B,THS/CIVM enable" "0: Enabled,1: Disabled"
newline
bitfld.long 0x00 1.--4. "Reserved_1,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0. "THSST,Enabling/disabling of the A/D converter for the thermal sensor" "0: Disabled,1: Enabled"
group.long 0x24++0x03
line.long 0x00 "THSTR3,"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved These bits are fixed to 0"
newline
rbitfld.long 0x00 3. "THACKMON,THACK signal monitor Indicates that the THCODE was generated" "0: Not detected,1: THCODE was generated"
newline
rbitfld.long 0x00 2. "THCNTOV_MON,THCNTOV signal monitor Indicates that the counter overflowed" "0: Not detected,1: Detected overflow"
newline
rbitfld.long 0x00 1. "THFAIL1,This bit is set to 1 when all of the THCODE bits are 1" "0: Normal operation,1: All of the THCODE bits are all 1"
newline
rbitfld.long 0x00 0. "THFAIL0,This bit is set to 1 when all of the THCODE bits are 0" "0: Normal operation,1: All of the THCODE bits are all 0"
group.long 0x28++0x03
line.long 0x00 "TEMP3,"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are fixed to 0"
newline
rbitfld.long 0x00 12.--13. "Reserved_12,Reserved These bits are fixed to 0" "0,1,2,3"
newline
hexmask.long.word 0x00 0.--11. 1. "TEMP_CODE_11_0,These bits indicate the digital value for the temperature detected by the thermal sensor"
group.long 0x2C++0x03
line.long 0x00 "VOLT3,"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are fixed to 0"
newline
rbitfld.long 0x00 10.--13. "Reserved_10,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--9. 1. "VOLT_CODE_9_0,These bits indicate the digital value for the voltage detected by the chip internal voltage monitor"
group.long 0x6C++0x03
line.long 0x00 "IRQ_INJECTION3,"
hexmask.long 0x00 6.--31. 1. "Reserved_6,Reserved These bits are fixed to 0"
newline
bitfld.long 0x00 5. "TEMPD3_INJ,TEMPD3 Error Injection" "0: TEMPD3 Error Injection Disable,1: TEMPD3 Error Injection Enable"
newline
bitfld.long 0x00 4. "TEMPD2_INJ,TEMPD2 Error Injection" "0: TEMPD2 Error Injection Disable,1: TEMPD2 Error Injection Enable"
newline
bitfld.long 0x00 3. "TEMPD1_INJ,TEMPD1 Error Injection" "0: TEMPD1 Error Injection Disable,1: TEMPD1 Error Injection Enable"
newline
bitfld.long 0x00 2. "TEMP3_INJ,TEMP3 Error Injection" "0: TEMP3 Error Injection Disable,1: TEMP3 Error Injection Enable"
newline
bitfld.long 0x00 1. "TEMP2_INJ,TEMP2 Error Injection" "0: TEMP2 Error Injection Disable,1: TEMP2 Error Injection Enable"
newline
bitfld.long 0x00 0. "TEMP1_INJ,TEMP1 Error Injection" "0: TEMP1 Error Injection Disable,1: TEMP1 Error Injection Enable"
group.long 0x74++0x03
line.long 0x00 "TSC_ERROR_CTL3,"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are fixed to 0"
newline
bitfld.long 0x00 0. "TSC_ERR_CTL,TSC error injection" "0: Error injection disable,1: Error injection enable"
group.long 0x7C++0x03
line.long 0x00 "SEQ_RESET3,"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are fixed to 0"
newline
bitfld.long 0x00 0. "SEQ_RESET,This bit initializes the sequence and error value" "0,1"
group.long 0x8C++0x03
line.long 0x00 "CIVMTST_VOLT13,"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,These bits are fixed to 0"
newline
hexmask.long.word 0x00 0.--13. 1. "CIVMTST_VOLT1_CODE_YN_13_0,These bits indicate the digital value detected by the chip internal voltage monitor during CIVM test mode1"
group.long 0x98++0x03
line.long 0x00 "CIVMTST_VOLT43,"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,These bits are fixed to 0"
newline
hexmask.long.word 0x00 0.--13. 1. "CIVMTST_VOLT4_CODE_YN_13_0,These bits indicate the digital value detected by the chip internal voltage monitor during CIVM test mode4"
group.long 0x9C++0x03
line.long 0x00 "MANTST_VOLT3,"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,These bits are fixed to 0"
newline
hexmask.long.word 0x00 0.--13. 1. "MANTST_VOLT_CODE_YN_13_0,These bits indicate the digital value detected by the chip internal voltage monitor during Manual test mode"
group.long 0xC0++0x03
line.long 0x00 "THS_MANUAL_SET3,"
bitfld.long 0x00 31. "CTRSEL,Select control of THS/CIVM" "0: THS/CVM is controlled by Finite State Machine,1: THS/CVM is controlled by THS_MANUAL_SET.."
newline
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 24. "Reserved_24,Reserved This bit is fixed to 0" "0,1"
newline
rbitfld.long 0x00 23. "Reserved_23,Reserved This bit is fixed to 0" "0,1"
newline
bitfld.long 0x00 20.--22. "CTR_THVF0SEL_2_0,ADC InV[A] select" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 19. "Reserved_19,Reserved This bit is fixed to 0" "0,1"
newline
bitfld.long 0x00 16.--18. "CTR_THVF1SEL_2_0,ADC InV[B] select" "?,?,?,?,4: VTHIU,?,?,7: VTHIL other"
newline
rbitfld.long 0x00 14.--15. "Reserved_14,Reserved These bits are fixed to 0" "0,1,2,3"
newline
rbitfld.long 0x00 12.--13. "Reserved_12,Reserved These bits are fixed to 0" "0,1,2,3"
newline
rbitfld.long 0x00 10.--11. "Reserved_10,Reserved These bits are fixed to 0" "0,1,2,3"
newline
rbitfld.long 0x00 8.--9. "Reserved_8,Reserved These bits are fixed to 0" "0,1,2,3"
newline
hexmask.long.byte 0x00 1.--7. 1. "Reserved_1,Reserved These bits are fixed to 0"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved This bit is fixed to 0" "0,1"
group.long 0x100++0x03
line.long 0x00 "CVM_LATCH_BK3,"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are fixed to 0"
newline
rbitfld.long 0x00 0. "R_VMLATCH,Status of configuration lock" "0: CVM_CTRL CVM_DETECT_MANUAL_SET and,1: CVM_CTRL CVM_DETECT_MANUAL_SET and"
group.long 0x104++0x03
line.long 0x00 "CVM_CTRL3,"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are fixed to 0"
newline
rbitfld.long 0x00 16. "Reserved_16,Reserved These bits are fixed to 0" "0,1"
newline
rbitfld.long 0x00 13.--15. "Reserved_13,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 12. "THBGREN_N,BGR enable" "0: Enabled,1: Disabled This bit"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 8. "OUTPC,This bit is a switching signal for CVM function" "0: Idle mode,1: CVM mode This bit is"
newline
bitfld.long 0x00 6.--7. "VMFLTFC_1_0,CVM digital output filter function control" "0: see Section 200.8 CVM Characteristics,1: see Section 200.8 CVM Characteristics,2: see Section 200.8 CVM Characteristics,3: filter skip This bit is implemented for only.."
newline
rbitfld.long 0x00 5. "Reserved_5,Reserved This bit is fixed to 0" "0,1"
newline
rbitfld.long 0x00 4. "Reserved_4,Reserved This bit is fixed to 0" "0,1"
newline
bitfld.long 0x00 0.--3. "CHOICE_PLACE_3_0,These bits enable or disable each CVM error output CHOICE_PLACE[3] : Writing 1 to this bit is prohibited" "0: disable,1: enable This bit is,?..."
group.long 0x108++0x03
line.long 0x00 "CVM_CTRL_BK3,"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are fixed to 0"
newline
rbitfld.long 0x00 24. "Reserved_24,Reserved This bit is fixed to 0" "0,1"
newline
hexmask.long.byte 0x00 17.--23. 1. "Reserved_17,Reserved These bits are fixed to 0"
newline
rbitfld.long 0x00 16. "Reserved_16,Reserved This bit is fixed to 0" "0,1"
newline
rbitfld.long 0x00 13.--15. "Reserved_13,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 12. "R_THBGREN_N,This bit can monitor the readback value of THBGREN_N in CVM_CTRL register" "0,1"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 8. "OUTPC_BK,This bit can monitor the readback value of OUTPC in CVM_CTRL register" "0,1"
newline
rbitfld.long 0x00 6.--7. "R_VMFLTFC_1_0,This bit can monitor the readback value of VMFITFC in CVM_CTRL register" "0,1,2,3"
newline
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are fixed to 0" "0,1"
newline
rbitfld.long 0x00 4. "Reserved_4,Reserved These bits are fixed to 0" "0,1"
newline
rbitfld.long 0x00 0.--3. "CHOICE_PLACE_BK_3_0,These bits can monitor the readback value of CHOICE_PLACE [3:0] in CVM_CTRL register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x10C++0x03
line.long 0x00 "CVM_DETECT_MON3,"
rbitfld.long 0x00 26.--31. "Reserved_26,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 24.--25. "MODE_MAX_MON_1_0,Golden reference value for MODE_MAX The value is stored in e-fuse considering analogue characteristics of each die This bit is not implemented for TSC4" "0,1,2,3"
newline
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 16.--19. "TRIM_MAX_MON_3_0,Golden reference value for TRIM_MAX The value is stored in e-fuse considering analogue characteristics of each die This bit is not implemented for TSC4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 10.--15. "Reserved_10,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 8.--9. "MODE_MIN_MON_1_0,Golden reference value for MODE_MIN The value is stored in e-fuse considering analogue characteristics of each die This bit is not implemented for TSC4" "0,1,2,3"
newline
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 0.--3. "TRIM_MIN_MON_3_0,Golden reference value for TRIM_MIN The value is stored in e-fuse considering analogue characteristics of each die This bit is not implemented for TSC4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x110++0x03
line.long 0x00 "CVM_DETECT_MANUAL_SET3,"
rbitfld.long 0x00 29.--31. "Reserved_29,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 28. "CVM_DETECT_SEL_MAX,This bit selects either CVM_DETECT_MON register or CVM_MANUAL_SET register" "0: The values of bits 25 to 24 and bits 18 to 16..,1: The values of bits 25 to 24 and bits 18 to 16.."
newline
rbitfld.long 0x00 26.--27. "Reserved_26,Reserved This bit is fixed to 0" "0,1,2,3"
newline
bitfld.long 0x00 24.--25. "MODE_MAX_1_0,Coase grain overvoltage threshold setting" "0,1,2,3"
newline
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 16.--19. "TRIM_MAX_3_0,Fine grain overvoltage threshold setting (available only when CVM_DETECT_SEL_MAX = 1.) This bit is not implemented for TSC4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 13.--15. "Reserved_13,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 12. "CVM_DETECT_SEL_MIN,This bit selects either CVM_DETECT_MON register or CVM_MANUAL_SET register" "0: The values of bits 9 to 8 and bits 2 to 0 in,1: The values of bits 9 to 8 and bits 2 to 0 in"
newline
rbitfld.long 0x00 10.--11. "Reserved_10,Reserved This bit is fixed to 0" "0,1,2,3"
newline
bitfld.long 0x00 8.--9. "MODE_MIN_1_0,Coase grain undervoltage threshold setting" "0,1,2,3"
newline
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "TRIM_MIN_3_0,Fine grain undervoltage threshold setting (available only when CVM_DETECT_SEL_MIN = 1.) This bit is not implemented for TSC4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x114++0x03
line.long 0x00 "CVM_DETECT_SET_BK3,"
rbitfld.long 0x00 26.--31. "Reserved_26,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 24.--25. "MODE_MAX_BK_1_0,These bits can monitor the readback value of MODE_MAX[1:0]" "0,1,2,3"
newline
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 16.--19. "TRIM_MAX_BK_3_0,These bits can monitor the readback value of TRIM_MAX[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 10.--15. "Reserved_10,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 8.--9. "MODE_MIN_BK_1_0,These bits can monitor the readback value of MODE_MIN[1:0]" "0,1,2,3"
newline
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 0.--3. "TRIM_MIN_BK_3_0,These bits can monitor the readback value of TRIM_MIN[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x118++0x03
line.long 0x00 "CVM_TOFF_MON3,"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved These bits are fixed to 0"
newline
rbitfld.long 0x00 0.--3. "TOFF_MON_3_0,Golden reference value for TOFF The value is stored in e-fuse considering analogue characteristics of each die This bit is not implemented for TSC4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x11C++0x03
line.long 0x00 "CVM_TOFF_MANUAL_SET3,"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved These bits are fixed to 0"
newline
bitfld.long 0x00 12. "TOFF_SEL,This bit selects either CVM_TOFF_MON register or CVM_TOFF_MANUAL_SET register" "0: Select value that bit 3 to 0 in CVM_TOFF_MON,1: Select value that bit 3 to 0 in"
newline
hexmask.long.byte 0x00 4.--11. 1. "Reserved_4,Reserved These bits are fixed to 0"
newline
bitfld.long 0x00 0.--3. "TOFF_3_0,CVM temperature compensation setting (available only when TOFF_SEL = 1.) This bit is not implemented for TSC4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x120++0x03
line.long 0x00 "CVM_TOFF_BK3,"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved These bits are fixed to 0"
newline
rbitfld.long 0x00 0.--3. "TOFF_BK_3_0,These bits can monitor the readback value of TOFF[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x130++0x03
line.long 0x00 "TSC_ERROR_MON3,"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are fixed to 0"
newline
rbitfld.long 0x00 7. "ERR_ACKTOV,THACK timeout error status" "0: no error,1: THACK timeout error"
newline
rbitfld.long 0x00 6. "Reserved_6,Reserved This bit is fixed to 0" "0,1"
newline
rbitfld.long 0x00 5. "Reserved_5,Reserved This bit is fixed to 0" "0,1"
newline
rbitfld.long 0x00 4. "ERR_THCODE,THCODE error status Indicates that THCODE is all 0 or all F" "0: no error,1: THCODE error"
newline
rbitfld.long 0x00 3. "ERR_THCNTOV,THCNTOV error status Indicates that the counter overflowed" "0: no error,1: THCNTOV error"
newline
rbitfld.long 0x00 2. "THFAIL1,This bit is set to 1 when all of the THCODE bits are 1" "0: Normal operation,1: All of the THCODE bits are all 1"
newline
rbitfld.long 0x00 1. "THFAIL0,This bit is set to 1 when all of the THCODE bits are 0" "0: Normal operation,1: All of the THCODE bits are all 0"
newline
rbitfld.long 0x00 0. "TSC_ERROR,TSC error status TSC error is 1 if one or more of ERR_ACKTOV ERR_THCODE ERR_THCNTOV THFAIL1 and THFAIL0 errors are detected" "0: no error,1: TSC error"
group.long 0x138++0x03
line.long 0x00 "MANTST_SET_DT3,"
rbitfld.long 0x00 29.--31. "Reserved_29,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 28. "MANTST,Manual test mode" "0: Normal mode,1: Manual test mode This bit is"
newline
rbitfld.long 0x00 23.--27. "Reserved_23,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 20.--22. "MAN_THVF0SEL_2_0,ADC InV[A] select for manual test" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 19. "Reserved_19,Reserved These bits are fixed to 0" "0,1"
newline
bitfld.long 0x00 16.--18. "MAN_THVF1SEL_2_0,ADC InV[B] select for manual test" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 14.--15. "Reserved_14,Reserved These bits are fixed to 0" "0,1,2,3"
newline
rbitfld.long 0x00 12.--13. "Reserved_12,Reserved These bits are fixed to 0" "0,1,2,3"
newline
rbitfld.long 0x00 10.--11. "Reserved_10,Reserved These bits are fixed to 0" "0,1,2,3"
newline
rbitfld.long 0x00 8.--9. "Reserved_8,Reserved These bits are fixed to 0" "0,1,2,3"
newline
hexmask.long.byte 0x00 0.--7. 1. "Reserved_0,Reserved These bits are fixed to 0"
group.long 0x140++0x03
line.long 0x00 "SEQ_ACT_MON3,"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved These bits are fixed to 0"
newline
rbitfld.long 0x00 0.--3. "SEQ_ACT_3_0,Sequence Act Flag monitor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x180++0x03
line.long 0x00 "THSFMON003,"
rbitfld.long 0x00 28.--31. "Reserved_28,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 16.--27. 1. "Reserved_16,Reserved These bits are indefinite"
newline
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--11. 1. "THCODE_L_SR1_11_0,Parameter to be used in adjusting the characteristics Refer to 13.3.3.4 13.3.3.6 section"
group.long 0x184++0x03
line.long 0x00 "THSFMON013,"
rbitfld.long 0x00 28.--31. "Reserved_28,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 16.--27. 1. "Reserved_16,Reserved These bits are indefinite"
newline
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--11. 1. "THCODE_U_SR1_11_0,Parameter to be used in adjusting the characteristics Refer to 13.3.3.4 13.3.3.6 section"
group.long 0x188++0x03
line.long 0x00 "THSFMON023,"
rbitfld.long 0x00 28.--31. "Reserved_28,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 16.--27. 1. "Reserved_16,Reserved These bits are indefinite"
newline
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--11. 1. "THCODE_R_SR1_11_0,Parameter to be used in adjusting the characteristics Refer to 13.3.3.4 13.3.3.6 section"
tree.end
tree "THS_INST_3"
base ad:0xE61B0000
group.long 0x04++0x03
line.long 0x00 "IRQSTR4,"
hexmask.long 0x00 6.--31. 1. "Reserved_6,Reserved These bits are fixed to 0"
newline
bitfld.long 0x00 5. "TEMPD3_STR,TEMPD3 Detection Status" "0: Not detected,1: TEMP_CODE [11:0] bits detect that"
newline
bitfld.long 0x00 4. "TEMPD2_STR,TEMPD2 Detection Status" "0: Not detected,1: TEMP_CODE [11:0] bits detect that"
newline
bitfld.long 0x00 3. "TEMPD1_STR,TEMPD1 Detection Status" "0: Not detected,1: TEMP_CODE [11:0] bits detect that"
newline
bitfld.long 0x00 2. "TEMP3_STR,TEMP3 Detection Status" "0: Not detected,1: TEMP_CODE [11:0] bits detect that"
newline
bitfld.long 0x00 1. "TEMP2_STR,TEMP2 Detection Status" "0: Not detected,1: TEMP_CODE [11:0] bits detect that"
newline
bitfld.long 0x00 0. "TEMP1_STR,TEMP1 Detection Status" "0: Not detected,1: TEMP_CODE [11:0] bits detect that"
group.long 0x08++0x03
line.long 0x00 "IRQMSK4,"
hexmask.long 0x00 6.--31. 1. "Reserved_6,Reserved These bits are fixed to 0"
newline
bitfld.long 0x00 5. "TEMPD3_MSK,This bit selects masking or non-masking of TEMPD3 error requests" "0: Errors are masked,1: The mask is cleared"
newline
bitfld.long 0x00 4. "TEMPD2_MSK,This bit selects masking or non-masking of TEMPD2 error requests" "0: Errors are masked,1: The mask is cleared"
newline
bitfld.long 0x00 3. "TEMPD1_MSK,This bit selects masking or non-masking of TEMPD1 error requests" "0: Errors are masked,1: The mask is cleared"
newline
bitfld.long 0x00 2. "TEMP3_MSK,This bit selects masking or non-masking of TEMP3 error requests" "0: Errors are masked,1: The mask is cleared"
newline
bitfld.long 0x00 1. "TEMP2_MSK,This bit selects masking or non-masking of TEMP2 error requests" "0: Errors are masked,1: The mask is cleared"
newline
bitfld.long 0x00 0. "TEMP1_MSK,This bit selects masking or non-masking of TEMP1 error requests" "0: Errors are masked,1: The mask is cleared"
group.long 0x10++0x03
line.long 0x00 "IRQEN4,"
hexmask.long 0x00 6.--31. 1. "Reserved_6,Reserved These bits are fixed to 0"
newline
bitfld.long 0x00 5. "TEMPD3_EN,This bit enables or disables TEMPD3 errors" "0: TEMPD3 errors are disabled,1: TEMPD3 errors are enabled"
newline
bitfld.long 0x00 4. "TEMPD2_EN,This bit enables or disables TEMPD2 errors" "0: TEMPD2 errors are disabled,1: TEMPD2 errors are enabled"
newline
bitfld.long 0x00 3. "TEMPD1_EN,This bit enables or disables TEMPD1 errors" "0: TEMPD1 errors are disabled,1: TEMPD1 errors are enabled"
newline
bitfld.long 0x00 2. "TEMP3_EN,This bit enables or disables TEMP3 errors" "0: TEMP3 errors are disabled,1: TEMP3 errors are enabled"
newline
bitfld.long 0x00 1. "TEMP2_EN,This bit enables or disables TEMP2 errors" "0: TEMP2 errors are disabled,1: TEMP2 errors are enabled"
newline
bitfld.long 0x00 0. "TEMP1_EN,This bit enables or disables TEMP1 errors" "0: TEMP1 errors are disabled,1: TEMP1 errors are enabled"
group.long 0x14++0x03
line.long 0x00 "IRQTEMP14,"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are fixed to 0"
newline
rbitfld.long 0x00 12.--13. "Reserved_12,Reserved These bits are fixed to 0" "0,1,2,3"
newline
hexmask.long.word 0x00 0.--11. 1. "IRQTEMP1_11_0,These bits set the first threshold value of the temperature for TEMP1 and TEMPD1 errors"
group.long 0x18++0x03
line.long 0x00 "IRQTEMP24,"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are fixed to 0"
newline
rbitfld.long 0x00 12.--13. "Reserved_12,Reserved These bits are fixed to 0" "0,1,2,3"
newline
hexmask.long.word 0x00 0.--11. 1. "IRQTEMP2_11_0,These bits set the second threshold value of the temperature for TEMP2 and TEMPD2 errors"
group.long 0x1C++0x03
line.long 0x00 "IRQTEMP34,"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are fixed to 0"
newline
rbitfld.long 0x00 12.--13. "Reserved_12,Reserved These bits are fixed to 0" "0,1,2,3"
newline
hexmask.long.word 0x00 0.--11. 1. "IRQTEMP3_11_0,These bits set the third threshold value of the temperature for TEMP3 and TEMPD3 errors"
group.long 0x20++0x03
line.long 0x00 "THCTR4,"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are fixed to 0"
newline
rbitfld.long 0x00 24. "Reserved_24,Reserved These bits are fixed to 0" "0,1"
newline
rbitfld.long 0x00 21.--23. "Reserved_21,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 20. "CIVMTST,THS/CIVM failure check mode" "0: Normal mode,1: THS/CIVM failure check mode"
newline
rbitfld.long 0x00 18.--19. "Reserved_18,Reserved These bits are fixed to 0" "0,1,2,3"
newline
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are fixed to 0" "0,1,2,3"
newline
rbitfld.long 0x00 10.--15. "Reserved_10,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--9. "SENSSEL_1_0,Select the use sensor" "0: THS CIVM both ON,1: THS ON only,2: CIVM ON only,3: THS CIVM both ON (this setting is the"
newline
rbitfld.long 0x00 6.--7. "Reserved_6,Reserved These bits are fixed to 0" "0,1,2,3"
newline
bitfld.long 0x00 5. "TH_EN_B,THS/CIVM enable" "0: Enabled,1: Disabled"
newline
bitfld.long 0x00 1.--4. "Reserved_1,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0. "THSST,Enabling/disabling of the A/D converter for the thermal sensor" "0: Disabled,1: Enabled"
group.long 0x24++0x03
line.long 0x00 "THSTR4,"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved These bits are fixed to 0"
newline
rbitfld.long 0x00 3. "THACKMON,THACK signal monitor Indicates that the THCODE was generated" "0: Not detected,1: THCODE was generated"
newline
rbitfld.long 0x00 2. "THCNTOV_MON,THCNTOV signal monitor Indicates that the counter overflowed" "0: Not detected,1: Detected overflow"
newline
rbitfld.long 0x00 1. "THFAIL1,This bit is set to 1 when all of the THCODE bits are 1" "0: Normal operation,1: All of the THCODE bits are all 1"
newline
rbitfld.long 0x00 0. "THFAIL0,This bit is set to 1 when all of the THCODE bits are 0" "0: Normal operation,1: All of the THCODE bits are all 0"
group.long 0x28++0x03
line.long 0x00 "TEMP4,"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are fixed to 0"
newline
rbitfld.long 0x00 12.--13. "Reserved_12,Reserved These bits are fixed to 0" "0,1,2,3"
newline
hexmask.long.word 0x00 0.--11. 1. "TEMP_CODE_11_0,These bits indicate the digital value for the temperature detected by the thermal sensor"
group.long 0x2C++0x03
line.long 0x00 "VOLT4,"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are fixed to 0"
newline
rbitfld.long 0x00 10.--13. "Reserved_10,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--9. 1. "VOLT_CODE_9_0,These bits indicate the digital value for the voltage detected by the chip internal voltage monitor"
group.long 0x6C++0x03
line.long 0x00 "IRQ_INJECTION4,"
hexmask.long 0x00 6.--31. 1. "Reserved_6,Reserved These bits are fixed to 0"
newline
bitfld.long 0x00 5. "TEMPD3_INJ,TEMPD3 Error Injection" "0: TEMPD3 Error Injection Disable,1: TEMPD3 Error Injection Enable"
newline
bitfld.long 0x00 4. "TEMPD2_INJ,TEMPD2 Error Injection" "0: TEMPD2 Error Injection Disable,1: TEMPD2 Error Injection Enable"
newline
bitfld.long 0x00 3. "TEMPD1_INJ,TEMPD1 Error Injection" "0: TEMPD1 Error Injection Disable,1: TEMPD1 Error Injection Enable"
newline
bitfld.long 0x00 2. "TEMP3_INJ,TEMP3 Error Injection" "0: TEMP3 Error Injection Disable,1: TEMP3 Error Injection Enable"
newline
bitfld.long 0x00 1. "TEMP2_INJ,TEMP2 Error Injection" "0: TEMP2 Error Injection Disable,1: TEMP2 Error Injection Enable"
newline
bitfld.long 0x00 0. "TEMP1_INJ,TEMP1 Error Injection" "0: TEMP1 Error Injection Disable,1: TEMP1 Error Injection Enable"
group.long 0x74++0x03
line.long 0x00 "TSC_ERROR_CTL4,"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are fixed to 0"
newline
bitfld.long 0x00 0. "TSC_ERR_CTL,TSC error injection" "0: Error injection disable,1: Error injection enable"
group.long 0x7C++0x03
line.long 0x00 "SEQ_RESET4,"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are fixed to 0"
newline
bitfld.long 0x00 0. "SEQ_RESET,This bit initializes the sequence and error value" "0,1"
group.long 0x8C++0x03
line.long 0x00 "CIVMTST_VOLT14,"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,These bits are fixed to 0"
newline
hexmask.long.word 0x00 0.--13. 1. "CIVMTST_VOLT1_CODE_YN_13_0,These bits indicate the digital value detected by the chip internal voltage monitor during CIVM test mode1"
group.long 0x98++0x03
line.long 0x00 "CIVMTST_VOLT44,"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,These bits are fixed to 0"
newline
hexmask.long.word 0x00 0.--13. 1. "CIVMTST_VOLT4_CODE_YN_13_0,These bits indicate the digital value detected by the chip internal voltage monitor during CIVM test mode4"
group.long 0x9C++0x03
line.long 0x00 "MANTST_VOLT4,"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,These bits are fixed to 0"
newline
hexmask.long.word 0x00 0.--13. 1. "MANTST_VOLT_CODE_YN_13_0,These bits indicate the digital value detected by the chip internal voltage monitor during Manual test mode"
group.long 0xC0++0x03
line.long 0x00 "THS_MANUAL_SET4,"
bitfld.long 0x00 31. "CTRSEL,Select control of THS/CIVM" "0: THS/CVM is controlled by Finite State Machine,1: THS/CVM is controlled by THS_MANUAL_SET.."
newline
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 24. "Reserved_24,Reserved This bit is fixed to 0" "0,1"
newline
rbitfld.long 0x00 23. "Reserved_23,Reserved This bit is fixed to 0" "0,1"
newline
bitfld.long 0x00 20.--22. "CTR_THVF0SEL_2_0,ADC InV[A] select" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 19. "Reserved_19,Reserved This bit is fixed to 0" "0,1"
newline
bitfld.long 0x00 16.--18. "CTR_THVF1SEL_2_0,ADC InV[B] select" "?,?,?,?,4: VTHIU,?,?,7: VTHIL other"
newline
rbitfld.long 0x00 14.--15. "Reserved_14,Reserved These bits are fixed to 0" "0,1,2,3"
newline
rbitfld.long 0x00 12.--13. "Reserved_12,Reserved These bits are fixed to 0" "0,1,2,3"
newline
rbitfld.long 0x00 10.--11. "Reserved_10,Reserved These bits are fixed to 0" "0,1,2,3"
newline
rbitfld.long 0x00 8.--9. "Reserved_8,Reserved These bits are fixed to 0" "0,1,2,3"
newline
hexmask.long.byte 0x00 1.--7. 1. "Reserved_1,Reserved These bits are fixed to 0"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved This bit is fixed to 0" "0,1"
group.long 0x104++0x03
line.long 0x00 "CVM_CTRL4,"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are fixed to 0"
newline
rbitfld.long 0x00 16. "Reserved_16,Reserved These bits are fixed to 0" "0,1"
newline
rbitfld.long 0x00 13.--15. "Reserved_13,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 12. "THBGREN_N,BGR enable" "0: Enabled,1: Disabled This bit"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 8. "OUTPC,This bit is a switching signal for CVM function" "0: Idle mode,1: CVM mode This bit is"
newline
bitfld.long 0x00 6.--7. "VMFLTFC_1_0,CVM digital output filter function control" "0: see Section 200.8 CVM Characteristics,1: see Section 200.8 CVM Characteristics,2: see Section 200.8 CVM Characteristics,3: filter skip This bit is implemented for only.."
newline
rbitfld.long 0x00 5. "Reserved_5,Reserved This bit is fixed to 0" "0,1"
newline
rbitfld.long 0x00 4. "Reserved_4,Reserved This bit is fixed to 0" "0,1"
newline
bitfld.long 0x00 0.--3. "CHOICE_PLACE_3_0,These bits enable or disable each CVM error output CHOICE_PLACE[3] : Writing 1 to this bit is prohibited" "0: disable,1: enable This bit is,?..."
group.long 0x108++0x03
line.long 0x00 "CVM_CTRL_BK4,"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are fixed to 0"
newline
rbitfld.long 0x00 24. "Reserved_24,Reserved This bit is fixed to 0" "0,1"
newline
hexmask.long.byte 0x00 17.--23. 1. "Reserved_17,Reserved These bits are fixed to 0"
newline
rbitfld.long 0x00 16. "Reserved_16,Reserved This bit is fixed to 0" "0,1"
newline
rbitfld.long 0x00 13.--15. "Reserved_13,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 12. "R_THBGREN_N,This bit can monitor the readback value of THBGREN_N in CVM_CTRL register" "0,1"
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 8. "OUTPC_BK,This bit can monitor the readback value of OUTPC in CVM_CTRL register" "0,1"
newline
rbitfld.long 0x00 6.--7. "R_VMFLTFC_1_0,This bit can monitor the readback value of VMFITFC in CVM_CTRL register" "0,1,2,3"
newline
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are fixed to 0" "0,1"
newline
rbitfld.long 0x00 4. "Reserved_4,Reserved These bits are fixed to 0" "0,1"
newline
rbitfld.long 0x00 0.--3. "CHOICE_PLACE_BK_3_0,These bits can monitor the readback value of CHOICE_PLACE [3:0] in CVM_CTRL register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x10C++0x03
line.long 0x00 "CVM_DETECT_MON4,"
rbitfld.long 0x00 26.--31. "Reserved_26,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 24.--25. "MODE_MAX_MON_1_0,Golden reference value for MODE_MAX The value is stored in e-fuse considering analogue characteristics of each die This bit is not implemented for TSC4" "0,1,2,3"
newline
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 16.--19. "TRIM_MAX_MON_3_0,Golden reference value for TRIM_MAX The value is stored in e-fuse considering analogue characteristics of each die This bit is not implemented for TSC4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 10.--15. "Reserved_10,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 8.--9. "MODE_MIN_MON_1_0,Golden reference value for MODE_MIN The value is stored in e-fuse considering analogue characteristics of each die This bit is not implemented for TSC4" "0,1,2,3"
newline
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 0.--3. "TRIM_MIN_MON_3_0,Golden reference value for TRIM_MIN The value is stored in e-fuse considering analogue characteristics of each die This bit is not implemented for TSC4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x110++0x03
line.long 0x00 "CVM_DETECT_MANUAL_SET4,"
rbitfld.long 0x00 29.--31. "Reserved_29,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 28. "CVM_DETECT_SEL_MAX,This bit selects either CVM_DETECT_MON register or CVM_MANUAL_SET register" "0: The values of bits 25 to 24 and bits 18 to 16..,1: The values of bits 25 to 24 and bits 18 to 16.."
newline
rbitfld.long 0x00 26.--27. "Reserved_26,Reserved This bit is fixed to 0" "0,1,2,3"
newline
bitfld.long 0x00 24.--25. "MODE_MAX_1_0,Coase grain overvoltage threshold setting" "0,1,2,3"
newline
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 16.--19. "TRIM_MAX_3_0,Fine grain overvoltage threshold setting (available only when CVM_DETECT_SEL_MAX = 1.) This bit is not implemented for TSC4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 13.--15. "Reserved_13,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 12. "CVM_DETECT_SEL_MIN,This bit selects either CVM_DETECT_MON register or CVM_MANUAL_SET register" "0: The values of bits 9 to 8 and bits 2 to 0 in,1: The values of bits 9 to 8 and bits 2 to 0 in"
newline
rbitfld.long 0x00 10.--11. "Reserved_10,Reserved This bit is fixed to 0" "0,1,2,3"
newline
bitfld.long 0x00 8.--9. "MODE_MIN_1_0,Coase grain undervoltage threshold setting" "0,1,2,3"
newline
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "TRIM_MIN_3_0,Fine grain undervoltage threshold setting (available only when CVM_DETECT_SEL_MIN = 1.) This bit is not implemented for TSC4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x114++0x03
line.long 0x00 "CVM_DETECT_SET_BK4,"
rbitfld.long 0x00 26.--31. "Reserved_26,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 24.--25. "MODE_MAX_BK_1_0,These bits can monitor the readback value of MODE_MAX[1:0]" "0,1,2,3"
newline
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 16.--19. "TRIM_MAX_BK_3_0,These bits can monitor the readback value of TRIM_MAX[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 10.--15. "Reserved_10,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 8.--9. "MODE_MIN_BK_1_0,These bits can monitor the readback value of MODE_MIN[1:0]" "0,1,2,3"
newline
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 0.--3. "TRIM_MIN_BK_3_0,These bits can monitor the readback value of TRIM_MIN[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x118++0x03
line.long 0x00 "CVM_TOFF_MON4,"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved These bits are fixed to 0"
newline
rbitfld.long 0x00 0.--3. "TOFF_MON_3_0,Golden reference value for TOFF The value is stored in e-fuse considering analogue characteristics of each die This bit is not implemented for TSC4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x11C++0x03
line.long 0x00 "CVM_TOFF_MANUAL_SET4,"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved These bits are fixed to 0"
newline
bitfld.long 0x00 12. "TOFF_SEL,This bit selects either CVM_TOFF_MON register or CVM_TOFF_MANUAL_SET register" "0: Select value that bit 3 to 0 in CVM_TOFF_MON,1: Select value that bit 3 to 0 in"
newline
hexmask.long.byte 0x00 4.--11. 1. "Reserved_4,Reserved These bits are fixed to 0"
newline
bitfld.long 0x00 0.--3. "TOFF_3_0,CVM temperature compensation setting (available only when TOFF_SEL = 1.) This bit is not implemented for TSC4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x120++0x03
line.long 0x00 "CVM_TOFF_BK4,"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved These bits are fixed to 0"
newline
rbitfld.long 0x00 0.--3. "TOFF_BK_3_0,These bits can monitor the readback value of TOFF[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x130++0x03
line.long 0x00 "TSC_ERROR_MON4,"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are fixed to 0"
newline
rbitfld.long 0x00 7. "ERR_ACKTOV,THACK timeout error status" "0: no error,1: THACK timeout error"
newline
rbitfld.long 0x00 6. "Reserved_6,Reserved This bit is fixed to 0" "0,1"
newline
rbitfld.long 0x00 5. "Reserved_5,Reserved This bit is fixed to 0" "0,1"
newline
rbitfld.long 0x00 4. "ERR_THCODE,THCODE error status Indicates that THCODE is all 0 or all F" "0: no error,1: THCODE error"
newline
rbitfld.long 0x00 3. "ERR_THCNTOV,THCNTOV error status Indicates that the counter overflowed" "0: no error,1: THCNTOV error"
newline
rbitfld.long 0x00 2. "THFAIL1,This bit is set to 1 when all of the THCODE bits are 1" "0: Normal operation,1: All of the THCODE bits are all 1"
newline
rbitfld.long 0x00 1. "THFAIL0,This bit is set to 1 when all of the THCODE bits are 0" "0: Normal operation,1: All of the THCODE bits are all 0"
newline
rbitfld.long 0x00 0. "TSC_ERROR,TSC error status TSC error is 1 if one or more of ERR_ACKTOV ERR_THCODE ERR_THCNTOV THFAIL1 and THFAIL0 errors are detected" "0: no error,1: TSC error"
group.long 0x138++0x03
line.long 0x00 "MANTST_SET_DT4,"
rbitfld.long 0x00 29.--31. "Reserved_29,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 28. "MANTST,Manual test mode" "0: Normal mode,1: Manual test mode This bit is"
newline
rbitfld.long 0x00 23.--27. "Reserved_23,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 20.--22. "MAN_THVF0SEL_2_0,ADC InV[A] select for manual test" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 19. "Reserved_19,Reserved These bits are fixed to 0" "0,1"
newline
bitfld.long 0x00 16.--18. "MAN_THVF1SEL_2_0,ADC InV[B] select for manual test" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 14.--15. "Reserved_14,Reserved These bits are fixed to 0" "0,1,2,3"
newline
rbitfld.long 0x00 12.--13. "Reserved_12,Reserved These bits are fixed to 0" "0,1,2,3"
newline
rbitfld.long 0x00 10.--11. "Reserved_10,Reserved These bits are fixed to 0" "0,1,2,3"
newline
rbitfld.long 0x00 8.--9. "Reserved_8,Reserved These bits are fixed to 0" "0,1,2,3"
newline
hexmask.long.byte 0x00 0.--7. 1. "Reserved_0,Reserved These bits are fixed to 0"
group.long 0x140++0x03
line.long 0x00 "SEQ_ACT_MON4,"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved These bits are fixed to 0"
newline
rbitfld.long 0x00 0.--3. "SEQ_ACT_3_0,Sequence Act Flag monitor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x180++0x03
line.long 0x00 "THSFMON004,"
rbitfld.long 0x00 28.--31. "Reserved_28,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 16.--27. 1. "Reserved_16,Reserved These bits are indefinite"
newline
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--11. 1. "THCODE_L_SR1_11_0,Parameter to be used in adjusting the characteristics Refer to 13.3.3.4 13.3.3.6 section"
group.long 0x184++0x03
line.long 0x00 "THSFMON014,"
rbitfld.long 0x00 28.--31. "Reserved_28,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 16.--27. 1. "Reserved_16,Reserved These bits are indefinite"
newline
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--11. 1. "THCODE_U_SR1_11_0,Parameter to be used in adjusting the characteristics Refer to 13.3.3.4 13.3.3.6 section"
group.long 0x188++0x03
line.long 0x00 "THSFMON024,"
rbitfld.long 0x00 28.--31. "Reserved_28,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 16.--27. 1. "Reserved_16,Reserved These bits are indefinite"
newline
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are fixed to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--11. 1. "THCODE_R_SR1_11_0,Parameter to be used in adjusting the characteristics Refer to 13.3.3.4 13.3.3.6 section"
tree.end
tree.end
tree "RESET_RST"
tree "RESET_RST_INST_0"
base ad:0xE6160000
group.long 0x00++0x03
line.long 0x00 "MODEMR0,MODEMR0 is a 32-bit read-only register which can be accessed only in longwords"
rbitfld.long 0x00 31. "MD31,The value of MD31" "0,1"
rbitfld.long 0x00 30. "Reserved_30,Reserved" "0,1"
newline
rbitfld.long 0x00 29. "MD29,The value of MD29" "0,1"
rbitfld.long 0x00 28. "Reserved_28,Reserved" "0,1"
newline
rbitfld.long 0x00 27. "Reserved_27,Reserved" "0,1"
rbitfld.long 0x00 26. "Reserved_26,Reserved" "0,1"
newline
rbitfld.long 0x00 25. "MD25,The value of MD25" "0,1"
rbitfld.long 0x00 24. "Reserved_24,Reserved" "0,1"
newline
rbitfld.long 0x00 23. "Reserved_23,Reserved" "0,1"
rbitfld.long 0x00 22. "MD22,The value of MD22" "0,1"
newline
rbitfld.long 0x00 21. "MD21,The value of MD21" "0,1"
rbitfld.long 0x00 20. "MD20,The value of MD20" "0,1"
newline
rbitfld.long 0x00 19. "Reserved_19,Reserved" "0,1"
rbitfld.long 0x00 18. "Reserved_18,Reserved" "0,1"
newline
rbitfld.long 0x00 17. "MD17,The value of MD17" "0,1"
rbitfld.long 0x00 16. "Reserved_16,Reserved" "0,1"
newline
rbitfld.long 0x00 15. "Reserved_15,Reserved" "0,1"
rbitfld.long 0x00 14. "MD14,The value of MD14" "0,1"
newline
rbitfld.long 0x00 13. "MD13,The value of MD13" "0,1"
rbitfld.long 0x00 12. "Reserved_12,Reserved" "0,1"
newline
rbitfld.long 0x00 11. "MD11,The value of MD11" "0,1"
rbitfld.long 0x00 10. "MD10,The value of MD10" "0,1"
newline
rbitfld.long 0x00 9. "MD9,The value of MD9" "0,1"
rbitfld.long 0x00 8. "Reserved_8,Reserved" "0,1"
newline
rbitfld.long 0x00 7. "MD7,The value of MD7" "0,1"
rbitfld.long 0x00 6. "MD6,The value of MD6" "0,1"
newline
rbitfld.long 0x00 5. "MD5,The value of MD5" "0,1"
rbitfld.long 0x00 4. "MD4,The value of MD4" "0,1"
newline
rbitfld.long 0x00 3. "MD3,The value of MD3" "0,1"
rbitfld.long 0x00 2. "MD2,The value of MD2" "0,1"
newline
rbitfld.long 0x00 1. "MD1,The value of MD1" "0,1"
rbitfld.long 0x00 0. "Reserved_0,Reserved" "0,1"
group.long 0x04++0x03
line.long 0x00 "MODEMR1,MODEMR1 is a 32-bit read-only register which can be accessed only in longwords"
rbitfld.long 0x00 31. "Reserved_31,Reserved" "0,1"
rbitfld.long 0x00 30. "Reserved_30,Reserved" "0,1"
newline
rbitfld.long 0x00 29. "Reserved_29,Reserved" "0,1"
rbitfld.long 0x00 28. "MDT0,The value of MDT0" "0,1"
newline
rbitfld.long 0x00 27. "Reserved_27,Reserved" "0,1"
rbitfld.long 0x00 26. "Reserved_26,Reserved" "0,1"
newline
rbitfld.long 0x00 25. "Reserved_25,Reserved" "0,1"
rbitfld.long 0x00 24. "Reserved_24,Reserved" "0,1"
newline
rbitfld.long 0x00 23. "Reserved_23,Reserved" "0,1"
rbitfld.long 0x00 22. "Reserved_22,Reserved" "0,1"
newline
rbitfld.long 0x00 21. "Reserved_21,Reserved" "0,1"
rbitfld.long 0x00 20. "Reserved_20,Reserved" "0,1"
newline
rbitfld.long 0x00 19. "Reserved_19,Reserved" "0,1"
rbitfld.long 0x00 18. "Reserved_18,Reserved" "0,1"
newline
rbitfld.long 0x00 17. "Reserved_17,Reserved" "0,1"
rbitfld.long 0x00 16. "Reserved_16,Reserved" "0,1"
newline
rbitfld.long 0x00 15. "Reserved_15,Reserved" "0,1"
rbitfld.long 0x00 14. "Reserved_14,Reserved" "0,1"
newline
rbitfld.long 0x00 13. "Reserved_13,Reserved" "0,1"
rbitfld.long 0x00 12. "Reserved_12,Reserved" "0,1"
newline
rbitfld.long 0x00 11. "Reserved_11,Reserved" "0,1"
rbitfld.long 0x00 10. "Reserved_10,Reserved" "0,1"
newline
rbitfld.long 0x00 9. "Reserved_9,Reserved" "0,1"
rbitfld.long 0x00 8. "MD40,The value of MD40" "0,1"
newline
rbitfld.long 0x00 7. "MD39,The value of MD39" "0,1"
rbitfld.long 0x00 6. "Reserved_6,Reserved" "0,1"
newline
rbitfld.long 0x00 5. "MD37,The value of MD37" "0,1"
rbitfld.long 0x00 4. "MD36,The value of MD36" "0,1"
newline
rbitfld.long 0x00 3. "Reserved_3,Reserved" "0,1"
rbitfld.long 0x00 2. "Reserved_2,Reserved" "0,1"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved" "0,1"
rbitfld.long 0x00 0. "MD32,The value of MD32" "0,1"
group.long 0x10++0x03
line.long 0x00 "WDTRSTCR,WDTRSTCR is a 32-bit readable/writable register which can be accessed only in longwords"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Code value (HA55A) When read returns 0"
bitfld.long 0x00 15. "RESBAR2S,Select BAR2 registers reset condition" "0: ICUMXBAR and ICUMXCPCR are initialized only by,1: ICUMXBAR and ICUMXCPCR are initialized by"
newline
hexmask.long.word 0x00 2.--14. 1. "Reserved_2,Reserved"
bitfld.long 0x00 1. "SWDT_RSTMSK,System WatchDog Reset Mask" "0: Reset request,1: Not reset request"
newline
bitfld.long 0x00 0. "RWDT_RSTMSK,RWDT Reset Mask" "0: Reset request,1: Not reset request"
group.long 0x14++0x03
line.long 0x00 "RSTOUTCR,RSTOUTCR is a 32-bit readable/writable register which can be accessed only in longwords"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
bitfld.long 0x00 0. "RESOUT,PRESETOUT0# control by software This bit is used to specify the output level of PRESETOUT0#" "0: PRESETOUT0# is asserted,1: PRESETOUT#0 is negated"
group.long 0x18++0x03
line.long 0x00 "SRESCR0,SRESCR0 is a 32bit readable/writeable register which can be accessed only in longwords"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Code value (H5AA5) When read returns 0"
bitfld.long 0x00 15. "SPRES,Soft Power On Reset Soft Power On Reset is asserted" "0,1"
newline
hexmask.long.word 0x00 0.--14. 1. "Reserved_0,Reserved"
repeat 4. (strings "0" "1" "2" "3" )(list 0x0 0x4 0x8 0xC )
group.long ($2+0x20)++0x03
line.long 0x00 "RSTFR$1,RSTFRn is a 32bit readable/writeable register which can be accessed only in longwords"
hexmask.long 0x00 5.--31. 1. "Reserved_5,Reserved"
bitfld.long 0x00 4. "RCMCU,Soft Power On Reset Factor (Control domain) 0Reset Controller is not Soft Power On Reset factor" "0,1"
newline
bitfld.long 0x00 3. "RCPRES,Soft Power On Reset Factor Bit 0SRESCR0.SPRES is not Soft Power On Reset factor" "0,1"
bitfld.long 0x00 2. "RCSWDT,Soft Power On Reset Factor Bit 0System-WDT is not Soft Power On Reset factor" "0,1"
newline
bitfld.long 0x00 1. "RCRWDT,Soft Power On Reset Factor Bit 0RWDT is not Soft Power On Reset factor" "0,1"
bitfld.long 0x00 0. "RPF,Soft Power On Reset detection bit 0Soft Power On Reset is not detected" "0,1"
repeat.end
repeat 8. (strings "0" "1" "2" "3" "4" "5" "6" "7" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C )
group.long ($2+0x30)++0x03
line.long 0x00 "STBCHR$1,STBCHRn are 32-bit readable/writable registers which can be accessed only in longwords"
hexmask.long 0x00 0.--31. 1. "STBn_31_0,defined purely for software purpose"
repeat.end
group.long 0x50++0x03
line.long 0x00 "APBSFTYCHKR,APBSFTYCHKR is a 32-bit readable/writable register"
hexmask.long 0x00 0.--31. 1. "CHK_31_0,This register is functional safety use only"
group.long 0x54++0x03
line.long 0x00 "ICUMXBAR,ICUMXBAR is a 32-bit readable/writable register which can be accessed only in longwords"
hexmask.long.tbyte 0x00 9.--31. 1. "RBAR2_31_9,ICUMXB Boot Address2 When the ICUMXB accesses to the range of physical address from 0x0000 0000 to 0x0000 01FF the address bit in [31:9] is replaced by RBAR2[31:9]"
rbitfld.long 0x00 5.--8. "Reserved_5,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4. "BAREN,BAREN bit" "0: RBAR2 is not valid,1: RBAR2 is valid"
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved" "0,1,2,3"
newline
bitfld.long 0x00 0.--1. "BTMD_1_0,Specifies the Boot area of ICUMXB During Hardware Power On Reset the initial value of these bits depends upon MD4 MD3 MD2 and MD1 pin setting" "0: RBAR2[31:9] is assigned to Boot,1: Prohibited,2: Boots from BootROM,3: Prohibited"
group.long 0x58++0x03
line.long 0x00 "ICUMXCPCR,ICUMXCPCR is a 32-bit readable/writable register which can be accessed only in longwords"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
bitfld.long 0x00 0. "ICUMXCPINIT," "0,1"
group.long 0x68++0x03
line.long 0x00 "RSTPTCSR,RSTPTCSR is a 32-bit readable/writable register which can be accessed only in longwords"
hexmask.long 0x00 2.--31. 1. "Reserved_2,Reserved"
bitfld.long 0x00 1. "EIE,Enable error interrupt request of write access protection" "0: Disable error interrupt request,1: Enable error interrupt request When EIE=1 and"
newline
eventfld.long 0x00 0. "ERR,Display the status of error detection on secure access protection" "0: Not detect error,1: Detect error of write access protection to"
group.long 0x6C++0x03
line.long 0x00 "RSTPTERADR,RSTPTERADR is a 32-bit read-only register which can be accessed only in longwords"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved"
hexmask.long.word 0x00 1.--15. 1. "ADDR_15_1,Offset address[15:1] of the first illegal write access to the protected registers"
newline
eventfld.long 0x00 0. "ADDR_0,Offset address[0] of the first illegal write access to the protected registers" "0,1"
group.long 0x3800++0x03
line.long 0x00 "RSTD0WACR,RSTDnWACR is a 32-bit readable / writable register which can be accessed only in longwords"
rbitfld.long 0x00 28.--31. "Reserved_28,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 27. "RSTPTERADR,Write permission-RSTPTERADR register from domain n" "0: Prohibit write access,1: Permit write access"
newline
bitfld.long 0x00 26. "RSTPTCSR,Write permission-RSTPTCSR register from domain n" "0: Prohibit write access,1: Permit write access"
rbitfld.long 0x00 23.--25. "Reserved_23,Reserved" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 22. "ICUMXCPCR,Write permission-ICUMXCPCR register from domain n" "0: Prohibit write access,1: Permit write access"
bitfld.long 0x00 21. "ICUMXBAR,Write permission-ICUMXBAR register from domain n" "0: Prohibit write access,1: Permit write access"
newline
bitfld.long 0x00 20. "APBSFTYCHKR,Write permission-APBSFTYCHKR register from domain n" "0: Prohibit write access,1: Permit write access"
bitfld.long 0x00 19. "STBCHR7,Write permission-STBCHR7 register from domain n" "0: Prohibit write access,1: Permit write access"
newline
bitfld.long 0x00 18. "STBCHR6,Write permission-STBCHR6 register from domain n" "0: Prohibit write access,1: Permit write access"
bitfld.long 0x00 17. "STBCHR5,Write permission-STBCHR5 register from domain n" "0: Prohibit write access,1: Permit write access"
newline
bitfld.long 0x00 16. "STBCHR4,Write permission-STBCHR4 register from domain n" "0: Prohibit write access,1: Permit write access"
bitfld.long 0x00 15. "STBCHR3,Write permission-STBCHR3 register from domain n" "0: Prohibit write access,1: Permit write access"
newline
bitfld.long 0x00 14. "STBCHR2,Write permission-STBCHR2 register from domain n" "0: Prohibit write access,1: Permit write access"
bitfld.long 0x00 13. "STBCHR1,Write permission-STBCHR1 register from domain n" "0: Prohibit write access,1: Permit write access"
newline
bitfld.long 0x00 12. "STBCHR0,Write permission-STBCHR0 register from domain n" "0: Prohibit write access,1: Permit write access"
bitfld.long 0x00 11. "RSTFR3,Write permission-RSTFR3 register from domain n" "0: Prohibit write access,1: Permit write access"
newline
bitfld.long 0x00 10. "RSTFR2,Write permission-RSTFR2 register from domain n" "0: Prohibit write access,1: Permit write access"
bitfld.long 0x00 9. "RSTFR1,Write permission-RSTFR1 register from domain n" "0: Prohibit write access,1: Permit write access"
newline
bitfld.long 0x00 8. "RSTFR0,Write permission-RSTFR0 register from domain n" "0: Prohibit write access,1: Permit write access"
rbitfld.long 0x00 7. "Reserved_7,Reserved" "0,1"
newline
bitfld.long 0x00 6. "SRESCR0,Write permission-SRESCR0 register from domain n" "0: Prohibit write access,1: Permit write access"
bitfld.long 0x00 5. "RSTOUTCR,Write permission-RSTOUTCR register from domain n" "0: Prohibit write access,1: Permit write access"
newline
bitfld.long 0x00 4. "WDTRSTCR,Write permission-WDTRSTCR register from domain n" "0: Prohibit write access,1: Permit write access"
rbitfld.long 0x00 0.--3. "Reserved_0,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree.end
tree "RESET_RST_INST_1"
base ad:0xE6164000
group.long 0x3A00++0x03
line.long 0x00 "RSTD1WACR,RSTDnWACR is a 32-bit readable / writable register which can be accessed only in longwords"
rbitfld.long 0x00 28.--31. "Reserved_28,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 27. "RSTPTERADR,Write permission-RSTPTERADR register from domain n" "0: Prohibit write access,1: Permit write access"
bitfld.long 0x00 26. "RSTPTCSR,Write permission-RSTPTCSR register from domain n" "0: Prohibit write access,1: Permit write access"
newline
rbitfld.long 0x00 23.--25. "Reserved_23,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 22. "ICUMXCPCR,Write permission-ICUMXCPCR register from domain n" "0: Prohibit write access,1: Permit write access"
bitfld.long 0x00 21. "ICUMXBAR,Write permission-ICUMXBAR register from domain n" "0: Prohibit write access,1: Permit write access"
newline
bitfld.long 0x00 20. "APBSFTYCHKR,Write permission-APBSFTYCHKR register from domain n" "0: Prohibit write access,1: Permit write access"
bitfld.long 0x00 19. "STBCHR7,Write permission-STBCHR7 register from domain n" "0: Prohibit write access,1: Permit write access"
bitfld.long 0x00 18. "STBCHR6,Write permission-STBCHR6 register from domain n" "0: Prohibit write access,1: Permit write access"
newline
bitfld.long 0x00 17. "STBCHR5,Write permission-STBCHR5 register from domain n" "0: Prohibit write access,1: Permit write access"
bitfld.long 0x00 16. "STBCHR4,Write permission-STBCHR4 register from domain n" "0: Prohibit write access,1: Permit write access"
bitfld.long 0x00 15. "STBCHR3,Write permission-STBCHR3 register from domain n" "0: Prohibit write access,1: Permit write access"
newline
bitfld.long 0x00 14. "STBCHR2,Write permission-STBCHR2 register from domain n" "0: Prohibit write access,1: Permit write access"
bitfld.long 0x00 13. "STBCHR1,Write permission-STBCHR1 register from domain n" "0: Prohibit write access,1: Permit write access"
bitfld.long 0x00 12. "STBCHR0,Write permission-STBCHR0 register from domain n" "0: Prohibit write access,1: Permit write access"
newline
bitfld.long 0x00 11. "RSTFR3,Write permission-RSTFR3 register from domain n" "0: Prohibit write access,1: Permit write access"
bitfld.long 0x00 10. "RSTFR2,Write permission-RSTFR2 register from domain n" "0: Prohibit write access,1: Permit write access"
bitfld.long 0x00 9. "RSTFR1,Write permission-RSTFR1 register from domain n" "0: Prohibit write access,1: Permit write access"
newline
bitfld.long 0x00 8. "RSTFR0,Write permission-RSTFR0 register from domain n" "0: Prohibit write access,1: Permit write access"
bitfld.long 0x00 7. "SRESCR1,Write permission-SRESCR1 register from domain n" "0: Prohibit write access,1: Permit write access"
bitfld.long 0x00 6. "SRESCR0,Write permission-SRESCR0 register from domain n" "0: Prohibit write access,1: Permit write access"
newline
bitfld.long 0x00 5. "RSTOUTCR,Write permission-RSTOUTCR register from domain n" "0: Prohibit write access,1: Permit write access"
bitfld.long 0x00 4. "WDTRSTCR,Write permission-WDTRSTCR register from domain n" "0: Prohibit write access,1: Permit write access"
rbitfld.long 0x00 0.--3. "Reserved_0,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree.end
tree "RESET_RST_INST_2"
base ad:0xE6168000
group.long 0x3C00++0x03
line.long 0x00 "RSTD2WACR,RSTDnWACR is a 32-bit readable / writable register which can be accessed only in longwords"
rbitfld.long 0x00 28.--31. "Reserved_28,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 27. "RSTPTERADR,Write permission-RSTPTERADR register from domain n" "0: Prohibit write access,1: Permit write access"
bitfld.long 0x00 26. "RSTPTCSR,Write permission-RSTPTCSR register from domain n" "0: Prohibit write access,1: Permit write access"
newline
rbitfld.long 0x00 23.--25. "Reserved_23,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 22. "ICUMXCPCR,Write permission-ICUMXCPCR register from domain n" "0: Prohibit write access,1: Permit write access"
bitfld.long 0x00 21. "ICUMXBAR,Write permission-ICUMXBAR register from domain n" "0: Prohibit write access,1: Permit write access"
newline
bitfld.long 0x00 20. "APBSFTYCHKR,Write permission-APBSFTYCHKR register from domain n" "0: Prohibit write access,1: Permit write access"
bitfld.long 0x00 19. "STBCHR7,Write permission-STBCHR7 register from domain n" "0: Prohibit write access,1: Permit write access"
bitfld.long 0x00 18. "STBCHR6,Write permission-STBCHR6 register from domain n" "0: Prohibit write access,1: Permit write access"
newline
bitfld.long 0x00 17. "STBCHR5,Write permission-STBCHR5 register from domain n" "0: Prohibit write access,1: Permit write access"
bitfld.long 0x00 16. "STBCHR4,Write permission-STBCHR4 register from domain n" "0: Prohibit write access,1: Permit write access"
bitfld.long 0x00 15. "STBCHR3,Write permission-STBCHR3 register from domain n" "0: Prohibit write access,1: Permit write access"
newline
bitfld.long 0x00 14. "STBCHR2,Write permission-STBCHR2 register from domain n" "0: Prohibit write access,1: Permit write access"
bitfld.long 0x00 13. "STBCHR1,Write permission-STBCHR1 register from domain n" "0: Prohibit write access,1: Permit write access"
bitfld.long 0x00 12. "STBCHR0,Write permission-STBCHR0 register from domain n" "0: Prohibit write access,1: Permit write access"
newline
bitfld.long 0x00 11. "RSTFR3,Write permission-RSTFR3 register from domain n" "0: Prohibit write access,1: Permit write access"
bitfld.long 0x00 10. "RSTFR2,Write permission-RSTFR2 register from domain n" "0: Prohibit write access,1: Permit write access"
bitfld.long 0x00 9. "RSTFR1,Write permission-RSTFR1 register from domain n" "0: Prohibit write access,1: Permit write access"
newline
bitfld.long 0x00 8. "RSTFR0,Write permission-RSTFR0 register from domain n" "0: Prohibit write access,1: Permit write access"
bitfld.long 0x00 7. "SRESCR1,Write permission-SRESCR1 register from domain n" "0: Prohibit write access,1: Permit write access"
bitfld.long 0x00 6. "SRESCR0,Write permission-SRESCR0 register from domain n" "0: Prohibit write access,1: Permit write access"
newline
bitfld.long 0x00 5. "RSTOUTCR,Write permission-RSTOUTCR register from domain n" "0: Prohibit write access,1: Permit write access"
bitfld.long 0x00 4. "WDTRSTCR,Write permission-WDTRSTCR register from domain n" "0: Prohibit write access,1: Permit write access"
rbitfld.long 0x00 0.--3. "Reserved_0,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree.end
tree "RESET_RST_INST_3"
base ad:0xE616C000
group.long 0x3E00++0x03
line.long 0x00 "RSTD3WACR,RSTDnWACR is a 32-bit readable / writable register which can be accessed only in longwords"
rbitfld.long 0x00 28.--31. "Reserved_28,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 27. "RSTPTERADR,Write permission-RSTPTERADR register from domain n" "0: Prohibit write access,1: Permit write access"
bitfld.long 0x00 26. "RSTPTCSR,Write permission-RSTPTCSR register from domain n" "0: Prohibit write access,1: Permit write access"
newline
rbitfld.long 0x00 23.--25. "Reserved_23,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 22. "ICUMXCPCR,Write permission-ICUMXCPCR register from domain n" "0: Prohibit write access,1: Permit write access"
bitfld.long 0x00 21. "ICUMXBAR,Write permission-ICUMXBAR register from domain n" "0: Prohibit write access,1: Permit write access"
newline
bitfld.long 0x00 20. "APBSFTYCHKR,Write permission-APBSFTYCHKR register from domain n" "0: Prohibit write access,1: Permit write access"
bitfld.long 0x00 19. "STBCHR7,Write permission-STBCHR7 register from domain n" "0: Prohibit write access,1: Permit write access"
bitfld.long 0x00 18. "STBCHR6,Write permission-STBCHR6 register from domain n" "0: Prohibit write access,1: Permit write access"
newline
bitfld.long 0x00 17. "STBCHR5,Write permission-STBCHR5 register from domain n" "0: Prohibit write access,1: Permit write access"
bitfld.long 0x00 16. "STBCHR4,Write permission-STBCHR4 register from domain n" "0: Prohibit write access,1: Permit write access"
bitfld.long 0x00 15. "STBCHR3,Write permission-STBCHR3 register from domain n" "0: Prohibit write access,1: Permit write access"
newline
bitfld.long 0x00 14. "STBCHR2,Write permission-STBCHR2 register from domain n" "0: Prohibit write access,1: Permit write access"
bitfld.long 0x00 13. "STBCHR1,Write permission-STBCHR1 register from domain n" "0: Prohibit write access,1: Permit write access"
bitfld.long 0x00 12. "STBCHR0,Write permission-STBCHR0 register from domain n" "0: Prohibit write access,1: Permit write access"
newline
bitfld.long 0x00 11. "RSTFR3,Write permission-RSTFR3 register from domain n" "0: Prohibit write access,1: Permit write access"
bitfld.long 0x00 10. "RSTFR2,Write permission-RSTFR2 register from domain n" "0: Prohibit write access,1: Permit write access"
bitfld.long 0x00 9. "RSTFR1,Write permission-RSTFR1 register from domain n" "0: Prohibit write access,1: Permit write access"
newline
bitfld.long 0x00 8. "RSTFR0,Write permission-RSTFR0 register from domain n" "0: Prohibit write access,1: Permit write access"
bitfld.long 0x00 7. "SRESCR1,Write permission-SRESCR1 register from domain n" "0: Prohibit write access,1: Permit write access"
bitfld.long 0x00 6. "SRESCR0,Write permission-SRESCR0 register from domain n" "0: Prohibit write access,1: Permit write access"
newline
bitfld.long 0x00 5. "RSTOUTCR,Write permission-RSTOUTCR register from domain n" "0: Prohibit write access,1: Permit write access"
bitfld.long 0x00 4. "WDTRSTCR,Write permission-WDTRSTCR register from domain n" "0: Prohibit write access,1: Permit write access"
rbitfld.long 0x00 0.--3. "Reserved_0,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree.end
tree.end
tree "INTC"
tree "INTC_INST_0"
base ad:0xFFEA0000
group.long 0x00++0x03
line.long 0x00 "IMNTRSESR,This register shows secure access error status"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "SEC_ERR,security access error status" "0,1"
group.long 0x04++0x03
line.long 0x00 "INMTRESIDR,This register shows master ID when occurred secure access error Only secure access is allowed"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--19. 1. "ERR_S_ID,Error ID information for security access error"
group.long 0x08++0x03
line.long 0x00 "IMNTRESADDR,This register shows Slave register address when occurred secure access error"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
hexmask.long.word 0x00 0.--15. 1. "ERR_S_ADDR,Error Address information for security access error"
group.long 0x0C++0x03
line.long 0x00 "IMNTAPEDCEN,This register is functional safety use only"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved These bits are always read as 0"
bitfld.long 0x00 3. "EDCEN3,EDC enable for AXI4 stream channel 3" "0: Disable check function(Masking EDC error signal,1: Enable check function(Dont mask EDC error.."
newline
bitfld.long 0x00 2. "EDCEN2,EDC enable for AXI4 stream channel 2" "0: Disable check function(Masking EDC error signal,1: Enable check function(Dont mask EDC error.."
bitfld.long 0x00 1. "EDCEN1,EDC enable for AXI4 stream channel 1" "0: Disable check function(Masking EDC error signal,1: Enable check function(Dont mask EDC error.."
newline
bitfld.long 0x00 0. "EDCEN0,EDC enable for AXI4 stream channel 0" "0: Disable check function(Masking EDC error signal,1: Enable check function(Dont mask EDC error.."
group.long 0x10++0x03
line.long 0x00 "IMNTAPDBGEDC,This register is functional safety use only"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
bitfld.long 0x00 22.--24. "ACEM,EDC error injection for ACE Master I/F" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 19.--21. "ACES,EDC error injection for ACE Slave I/F" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "OTHER,EDC error injection for sideband signal I/F" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 6.--7. "AXI4_3,EDC error injection for AXI4 stream channel 3" "0,1,2,3"
newline
bitfld.long 0x00 4.--5. "AXI4_2,EDC error injection for AXI4 stream channel 2" "0,1,2,3"
bitfld.long 0x00 2.--3. "AXI4_1,EDC error injection for AXIa stream channel 1" "0,1,2,3"
newline
bitfld.long 0x00 0.--1. "AXI4_0,EDC error injection for AXI4 stream channel 0" "0,1,2,3"
group.long 0x20++0x03
line.long 0x00 "IMNTEDCESTS,This register is functional safety use only"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved These bits are always read as 0"
bitfld.long 0x00 3. "AXI4_3,EDC error status for AXI4 stream channel 3" "0,1"
newline
bitfld.long 0x00 2. "AXI4_2,EDC error status for AXI4 stream channel 2" "0,1"
bitfld.long 0x00 1. "AXI4_1,EDC error status for AXI4 stream channel 1" "0,1"
newline
bitfld.long 0x00 0. "AXI4_0,EDC error status for AXI4 stream channel 0" "0,1"
group.long 0x24++0x03
line.long 0x00 "IMNTAPDBGTC,This register is functional safety use only"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved These bits are always read as 0"
bitfld.long 0x00 0.--3. "TC_INJ,Error injection for tranfer count of AXI4 stream bit3: for channel 3 bit2: for channel 2 bit1: for channel 1 bit0: for channel 0" "0: disable error injection,1: enable error injection,?..."
group.long 0x1000++0x03
line.long 0x00 "IMNTRCCR,Only secure access is allowed"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Key Code"
hexmask.long.word 0x00 4.--15. 1. "Reserved_4,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 0.--3. "IMNTR_CLK,Select the clock of interrupt IMNTRs counter" "0: 4058 Hz,1: 2029 Hz,2: 1014 Hz,3: 507 Hz,4: 8117 Hz,5: 16 kHz,6: 32 kHz,7: 65 kHz,8: 130 kHz,9: 260 kHz Other,?..."
tree.end
tree "INTC_INST_1"
base ad:0xFFEA2000
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x00)++0x03
line.long 0x00 "IMNTRCR$1,This register is functional safety use only"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Key Code"
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "NUM1_EN,Enable to use CNT_NUM1 for only assert period" "0: CNT_NUM1 is disable,1: CNT_NUM1 is enable"
bitfld.long 0x00 5.--6. "CNT_NUM1,Select the number of interrupt IMNTRs counter for only assert Period" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 4. "CNT_RESET,Reset the interrupt IMNTRs counter" "0: Ignored,1: Reset the counter"
newline
bitfld.long 0x00 2.--3. "CNT_NUM0,Select the number of interrupt IMNTRs counter" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 1. "IMNTR_EN,Enable the interrupt IMNTR" "0: Disable,1: Enable"
bitfld.long 0x00 0. "WAIT_SET,Enable the waiting interrupt mode when IMNTR_EN is Enable" "0: Disable,1: Enable"
repeat.end
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x40)++0x03
line.long 0x00 "IMNTRCR$1,This register is functional safety use only"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Key Code"
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "NUM1_EN,Enable to use CNT_NUM1 for only assert period" "0: CNT_NUM1 is disable,1: CNT_NUM1 is enable"
bitfld.long 0x00 5.--6. "CNT_NUM1,Select the number of interrupt IMNTRs counter for only assert Period" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 4. "CNT_RESET,Reset the interrupt IMNTRs counter" "0: Ignored,1: Reset the counter"
newline
bitfld.long 0x00 2.--3. "CNT_NUM0,Select the number of interrupt IMNTRs counter" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 1. "IMNTR_EN,Enable the interrupt IMNTR" "0: Disable,1: Enable"
bitfld.long 0x00 0. "WAIT_SET,Enable the waiting interrupt mode when IMNTR_EN is Enable" "0: Disable,1: Enable"
repeat.end
repeat 16. (strings "32" "33" "34" "35" "36" "37" "38" "39" "40" "41" "42" "43" "44" "45" "46" "47" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x80)++0x03
line.long 0x00 "IMNTRCR$1,This register is functional safety use only"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Key Code"
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "NUM1_EN,Enable to use CNT_NUM1 for only assert period" "0: CNT_NUM1 is disable,1: CNT_NUM1 is enable"
bitfld.long 0x00 5.--6. "CNT_NUM1,Select the number of interrupt IMNTRs counter for only assert Period" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 4. "CNT_RESET,Reset the interrupt IMNTRs counter" "0: Ignored,1: Reset the counter"
newline
bitfld.long 0x00 2.--3. "CNT_NUM0,Select the number of interrupt IMNTRs counter" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 1. "IMNTR_EN,Enable the interrupt IMNTR" "0: Disable,1: Enable"
bitfld.long 0x00 0. "WAIT_SET,Enable the waiting interrupt mode when IMNTR_EN is Enable" "0: Disable,1: Enable"
repeat.end
repeat 16. (strings "48" "49" "50" "51" "52" "53" "54" "55" "56" "57" "58" "59" "60" "61" "62" "63" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0xC0)++0x03
line.long 0x00 "IMNTRCR$1,This register is functional safety use only"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Key Code"
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "NUM1_EN,Enable to use CNT_NUM1 for only assert period" "0: CNT_NUM1 is disable,1: CNT_NUM1 is enable"
bitfld.long 0x00 5.--6. "CNT_NUM1,Select the number of interrupt IMNTRs counter for only assert Period" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 4. "CNT_RESET,Reset the interrupt IMNTRs counter" "0: Ignored,1: Reset the counter"
newline
bitfld.long 0x00 2.--3. "CNT_NUM0,Select the number of interrupt IMNTRs counter" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 1. "IMNTR_EN,Enable the interrupt IMNTR" "0: Disable,1: Enable"
bitfld.long 0x00 0. "WAIT_SET,Enable the waiting interrupt mode when IMNTR_EN is Enable" "0: Disable,1: Enable"
repeat.end
repeat 16. (strings "64" "65" "66" "67" "68" "69" "70" "71" "72" "73" "74" "75" "76" "77" "78" "79" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x100)++0x03
line.long 0x00 "IMNTRCR$1,This register is functional safety use only"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Key Code"
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "NUM1_EN,Enable to use CNT_NUM1 for only assert period" "0: CNT_NUM1 is disable,1: CNT_NUM1 is enable"
bitfld.long 0x00 5.--6. "CNT_NUM1,Select the number of interrupt IMNTRs counter for only assert Period" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 4. "CNT_RESET,Reset the interrupt IMNTRs counter" "0: Ignored,1: Reset the counter"
newline
bitfld.long 0x00 2.--3. "CNT_NUM0,Select the number of interrupt IMNTRs counter" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 1. "IMNTR_EN,Enable the interrupt IMNTR" "0: Disable,1: Enable"
bitfld.long 0x00 0. "WAIT_SET,Enable the waiting interrupt mode when IMNTR_EN is Enable" "0: Disable,1: Enable"
repeat.end
repeat 16. (strings "80" "81" "82" "83" "84" "85" "86" "87" "88" "89" "90" "91" "92" "93" "94" "95" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x140)++0x03
line.long 0x00 "IMNTRCR$1,This register is functional safety use only"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Key Code"
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "NUM1_EN,Enable to use CNT_NUM1 for only assert period" "0: CNT_NUM1 is disable,1: CNT_NUM1 is enable"
bitfld.long 0x00 5.--6. "CNT_NUM1,Select the number of interrupt IMNTRs counter for only assert Period" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 4. "CNT_RESET,Reset the interrupt IMNTRs counter" "0: Ignored,1: Reset the counter"
newline
bitfld.long 0x00 2.--3. "CNT_NUM0,Select the number of interrupt IMNTRs counter" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 1. "IMNTR_EN,Enable the interrupt IMNTR" "0: Disable,1: Enable"
bitfld.long 0x00 0. "WAIT_SET,Enable the waiting interrupt mode when IMNTR_EN is Enable" "0: Disable,1: Enable"
repeat.end
repeat 16. (strings "96" "97" "98" "99" "100" "101" "102" "103" "104" "105" "106" "107" "108" "109" "110" "111" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x180)++0x03
line.long 0x00 "IMNTRCR$1,This register is functional safety use only"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Key Code"
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "NUM1_EN,Enable to use CNT_NUM1 for only assert period" "0: CNT_NUM1 is disable,1: CNT_NUM1 is enable"
bitfld.long 0x00 5.--6. "CNT_NUM1,Select the number of interrupt IMNTRs counter for only assert Period" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 4. "CNT_RESET,Reset the interrupt IMNTRs counter" "0: Ignored,1: Reset the counter"
newline
bitfld.long 0x00 2.--3. "CNT_NUM0,Select the number of interrupt IMNTRs counter" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 1. "IMNTR_EN,Enable the interrupt IMNTR" "0: Disable,1: Enable"
bitfld.long 0x00 0. "WAIT_SET,Enable the waiting interrupt mode when IMNTR_EN is Enable" "0: Disable,1: Enable"
repeat.end
repeat 16. (strings "112" "113" "114" "115" "116" "117" "118" "119" "120" "121" "122" "123" "124" "125" "126" "127" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x1C0)++0x03
line.long 0x00 "IMNTRCR$1,This register is functional safety use only"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Key Code"
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "NUM1_EN,Enable to use CNT_NUM1 for only assert period" "0: CNT_NUM1 is disable,1: CNT_NUM1 is enable"
bitfld.long 0x00 5.--6. "CNT_NUM1,Select the number of interrupt IMNTRs counter for only assert Period" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 4. "CNT_RESET,Reset the interrupt IMNTRs counter" "0: Ignored,1: Reset the counter"
newline
bitfld.long 0x00 2.--3. "CNT_NUM0,Select the number of interrupt IMNTRs counter" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 1. "IMNTR_EN,Enable the interrupt IMNTR" "0: Disable,1: Enable"
bitfld.long 0x00 0. "WAIT_SET,Enable the waiting interrupt mode when IMNTR_EN is Enable" "0: Disable,1: Enable"
repeat.end
repeat 16. (strings "128" "129" "130" "131" "132" "133" "134" "135" "136" "137" "138" "139" "140" "141" "142" "143" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x200)++0x03
line.long 0x00 "IMNTRCR$1,This register is functional safety use only"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Key Code"
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "NUM1_EN,Enable to use CNT_NUM1 for only assert period" "0: CNT_NUM1 is disable,1: CNT_NUM1 is enable"
bitfld.long 0x00 5.--6. "CNT_NUM1,Select the number of interrupt IMNTRs counter for only assert Period" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 4. "CNT_RESET,Reset the interrupt IMNTRs counter" "0: Ignored,1: Reset the counter"
newline
bitfld.long 0x00 2.--3. "CNT_NUM0,Select the number of interrupt IMNTRs counter" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 1. "IMNTR_EN,Enable the interrupt IMNTR" "0: Disable,1: Enable"
bitfld.long 0x00 0. "WAIT_SET,Enable the waiting interrupt mode when IMNTR_EN is Enable" "0: Disable,1: Enable"
repeat.end
repeat 16. (strings "144" "145" "146" "147" "148" "149" "150" "151" "152" "153" "154" "155" "156" "157" "158" "159" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x240)++0x03
line.long 0x00 "IMNTRCR$1,This register is functional safety use only"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Key Code"
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "NUM1_EN,Enable to use CNT_NUM1 for only assert period" "0: CNT_NUM1 is disable,1: CNT_NUM1 is enable"
bitfld.long 0x00 5.--6. "CNT_NUM1,Select the number of interrupt IMNTRs counter for only assert Period" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 4. "CNT_RESET,Reset the interrupt IMNTRs counter" "0: Ignored,1: Reset the counter"
newline
bitfld.long 0x00 2.--3. "CNT_NUM0,Select the number of interrupt IMNTRs counter" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 1. "IMNTR_EN,Enable the interrupt IMNTR" "0: Disable,1: Enable"
bitfld.long 0x00 0. "WAIT_SET,Enable the waiting interrupt mode when IMNTR_EN is Enable" "0: Disable,1: Enable"
repeat.end
repeat 16. (strings "160" "161" "162" "163" "164" "165" "166" "167" "168" "169" "170" "171" "172" "173" "174" "175" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x280)++0x03
line.long 0x00 "IMNTRCR$1,This register is functional safety use only"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Key Code"
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "NUM1_EN,Enable to use CNT_NUM1 for only assert period" "0: CNT_NUM1 is disable,1: CNT_NUM1 is enable"
bitfld.long 0x00 5.--6. "CNT_NUM1,Select the number of interrupt IMNTRs counter for only assert Period" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 4. "CNT_RESET,Reset the interrupt IMNTRs counter" "0: Ignored,1: Reset the counter"
newline
bitfld.long 0x00 2.--3. "CNT_NUM0,Select the number of interrupt IMNTRs counter" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 1. "IMNTR_EN,Enable the interrupt IMNTR" "0: Disable,1: Enable"
bitfld.long 0x00 0. "WAIT_SET,Enable the waiting interrupt mode when IMNTR_EN is Enable" "0: Disable,1: Enable"
repeat.end
repeat 16. (strings "176" "177" "178" "179" "180" "181" "182" "183" "184" "185" "186" "187" "188" "189" "190" "191" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x2C0)++0x03
line.long 0x00 "IMNTRCR$1,This register is functional safety use only"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Key Code"
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "NUM1_EN,Enable to use CNT_NUM1 for only assert period" "0: CNT_NUM1 is disable,1: CNT_NUM1 is enable"
bitfld.long 0x00 5.--6. "CNT_NUM1,Select the number of interrupt IMNTRs counter for only assert Period" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 4. "CNT_RESET,Reset the interrupt IMNTRs counter" "0: Ignored,1: Reset the counter"
newline
bitfld.long 0x00 2.--3. "CNT_NUM0,Select the number of interrupt IMNTRs counter" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 1. "IMNTR_EN,Enable the interrupt IMNTR" "0: Disable,1: Enable"
bitfld.long 0x00 0. "WAIT_SET,Enable the waiting interrupt mode when IMNTR_EN is Enable" "0: Disable,1: Enable"
repeat.end
repeat 16. (strings "192" "193" "194" "195" "196" "197" "198" "199" "200" "201" "202" "203" "204" "205" "206" "207" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x300)++0x03
line.long 0x00 "IMNTRCR$1,This register is functional safety use only"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Key Code"
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "NUM1_EN,Enable to use CNT_NUM1 for only assert period" "0: CNT_NUM1 is disable,1: CNT_NUM1 is enable"
bitfld.long 0x00 5.--6. "CNT_NUM1,Select the number of interrupt IMNTRs counter for only assert Period" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 4. "CNT_RESET,Reset the interrupt IMNTRs counter" "0: Ignored,1: Reset the counter"
newline
bitfld.long 0x00 2.--3. "CNT_NUM0,Select the number of interrupt IMNTRs counter" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 1. "IMNTR_EN,Enable the interrupt IMNTR" "0: Disable,1: Enable"
bitfld.long 0x00 0. "WAIT_SET,Enable the waiting interrupt mode when IMNTR_EN is Enable" "0: Disable,1: Enable"
repeat.end
repeat 16. (strings "208" "209" "210" "211" "212" "213" "214" "215" "216" "217" "218" "219" "220" "221" "222" "223" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x340)++0x03
line.long 0x00 "IMNTRCR$1,This register is functional safety use only"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Key Code"
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "NUM1_EN,Enable to use CNT_NUM1 for only assert period" "0: CNT_NUM1 is disable,1: CNT_NUM1 is enable"
bitfld.long 0x00 5.--6. "CNT_NUM1,Select the number of interrupt IMNTRs counter for only assert Period" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 4. "CNT_RESET,Reset the interrupt IMNTRs counter" "0: Ignored,1: Reset the counter"
newline
bitfld.long 0x00 2.--3. "CNT_NUM0,Select the number of interrupt IMNTRs counter" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 1. "IMNTR_EN,Enable the interrupt IMNTR" "0: Disable,1: Enable"
bitfld.long 0x00 0. "WAIT_SET,Enable the waiting interrupt mode when IMNTR_EN is Enable" "0: Disable,1: Enable"
repeat.end
repeat 16. (strings "224" "225" "226" "227" "228" "229" "230" "231" "232" "233" "234" "235" "236" "237" "238" "239" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x380)++0x03
line.long 0x00 "IMNTRCR$1,This register is functional safety use only"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Key Code"
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "NUM1_EN,Enable to use CNT_NUM1 for only assert period" "0: CNT_NUM1 is disable,1: CNT_NUM1 is enable"
bitfld.long 0x00 5.--6. "CNT_NUM1,Select the number of interrupt IMNTRs counter for only assert Period" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 4. "CNT_RESET,Reset the interrupt IMNTRs counter" "0: Ignored,1: Reset the counter"
newline
bitfld.long 0x00 2.--3. "CNT_NUM0,Select the number of interrupt IMNTRs counter" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 1. "IMNTR_EN,Enable the interrupt IMNTR" "0: Disable,1: Enable"
bitfld.long 0x00 0. "WAIT_SET,Enable the waiting interrupt mode when IMNTR_EN is Enable" "0: Disable,1: Enable"
repeat.end
repeat 16. (strings "240" "241" "242" "243" "244" "245" "246" "247" "248" "249" "250" "251" "252" "253" "254" "255" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x3C0)++0x03
line.long 0x00 "IMNTRCR$1,This register is functional safety use only"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Key Code"
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "NUM1_EN,Enable to use CNT_NUM1 for only assert period" "0: CNT_NUM1 is disable,1: CNT_NUM1 is enable"
bitfld.long 0x00 5.--6. "CNT_NUM1,Select the number of interrupt IMNTRs counter for only assert Period" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 4. "CNT_RESET,Reset the interrupt IMNTRs counter" "0: Ignored,1: Reset the counter"
newline
bitfld.long 0x00 2.--3. "CNT_NUM0,Select the number of interrupt IMNTRs counter" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 1. "IMNTR_EN,Enable the interrupt IMNTR" "0: Disable,1: Enable"
bitfld.long 0x00 0. "WAIT_SET,Enable the waiting interrupt mode when IMNTR_EN is Enable" "0: Disable,1: Enable"
repeat.end
repeat 16. (strings "256" "257" "258" "259" "260" "261" "262" "263" "264" "265" "266" "267" "268" "269" "270" "271" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x400)++0x03
line.long 0x00 "IMNTRCR$1,This register is functional safety use only"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Key Code"
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "NUM1_EN,Enable to use CNT_NUM1 for only assert period" "0: CNT_NUM1 is disable,1: CNT_NUM1 is enable"
bitfld.long 0x00 5.--6. "CNT_NUM1,Select the number of interrupt IMNTRs counter for only assert Period" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 4. "CNT_RESET,Reset the interrupt IMNTRs counter" "0: Ignored,1: Reset the counter"
newline
bitfld.long 0x00 2.--3. "CNT_NUM0,Select the number of interrupt IMNTRs counter" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 1. "IMNTR_EN,Enable the interrupt IMNTR" "0: Disable,1: Enable"
bitfld.long 0x00 0. "WAIT_SET,Enable the waiting interrupt mode when IMNTR_EN is Enable" "0: Disable,1: Enable"
repeat.end
repeat 16. (strings "272" "273" "274" "275" "276" "277" "278" "279" "280" "281" "282" "283" "284" "285" "286" "287" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x440)++0x03
line.long 0x00 "IMNTRCR$1,This register is functional safety use only"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Key Code"
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "NUM1_EN,Enable to use CNT_NUM1 for only assert period" "0: CNT_NUM1 is disable,1: CNT_NUM1 is enable"
bitfld.long 0x00 5.--6. "CNT_NUM1,Select the number of interrupt IMNTRs counter for only assert Period" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 4. "CNT_RESET,Reset the interrupt IMNTRs counter" "0: Ignored,1: Reset the counter"
newline
bitfld.long 0x00 2.--3. "CNT_NUM0,Select the number of interrupt IMNTRs counter" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 1. "IMNTR_EN,Enable the interrupt IMNTR" "0: Disable,1: Enable"
bitfld.long 0x00 0. "WAIT_SET,Enable the waiting interrupt mode when IMNTR_EN is Enable" "0: Disable,1: Enable"
repeat.end
repeat 16. (strings "288" "289" "290" "291" "292" "293" "294" "295" "296" "297" "298" "299" "300" "301" "302" "303" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x480)++0x03
line.long 0x00 "IMNTRCR$1,This register is functional safety use only"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Key Code"
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "NUM1_EN,Enable to use CNT_NUM1 for only assert period" "0: CNT_NUM1 is disable,1: CNT_NUM1 is enable"
bitfld.long 0x00 5.--6. "CNT_NUM1,Select the number of interrupt IMNTRs counter for only assert Period" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 4. "CNT_RESET,Reset the interrupt IMNTRs counter" "0: Ignored,1: Reset the counter"
newline
bitfld.long 0x00 2.--3. "CNT_NUM0,Select the number of interrupt IMNTRs counter" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 1. "IMNTR_EN,Enable the interrupt IMNTR" "0: Disable,1: Enable"
bitfld.long 0x00 0. "WAIT_SET,Enable the waiting interrupt mode when IMNTR_EN is Enable" "0: Disable,1: Enable"
repeat.end
repeat 16. (strings "304" "305" "306" "307" "308" "309" "310" "311" "312" "313" "314" "315" "316" "317" "318" "319" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x4C0)++0x03
line.long 0x00 "IMNTRCR$1,This register is functional safety use only"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Key Code"
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "NUM1_EN,Enable to use CNT_NUM1 for only assert period" "0: CNT_NUM1 is disable,1: CNT_NUM1 is enable"
bitfld.long 0x00 5.--6. "CNT_NUM1,Select the number of interrupt IMNTRs counter for only assert Period" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 4. "CNT_RESET,Reset the interrupt IMNTRs counter" "0: Ignored,1: Reset the counter"
newline
bitfld.long 0x00 2.--3. "CNT_NUM0,Select the number of interrupt IMNTRs counter" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 1. "IMNTR_EN,Enable the interrupt IMNTR" "0: Disable,1: Enable"
bitfld.long 0x00 0. "WAIT_SET,Enable the waiting interrupt mode when IMNTR_EN is Enable" "0: Disable,1: Enable"
repeat.end
repeat 16. (strings "320" "321" "322" "323" "324" "325" "326" "327" "328" "329" "330" "331" "332" "333" "334" "335" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x500)++0x03
line.long 0x00 "IMNTRCR$1,This register is functional safety use only"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Key Code"
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "NUM1_EN,Enable to use CNT_NUM1 for only assert period" "0: CNT_NUM1 is disable,1: CNT_NUM1 is enable"
bitfld.long 0x00 5.--6. "CNT_NUM1,Select the number of interrupt IMNTRs counter for only assert Period" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 4. "CNT_RESET,Reset the interrupt IMNTRs counter" "0: Ignored,1: Reset the counter"
newline
bitfld.long 0x00 2.--3. "CNT_NUM0,Select the number of interrupt IMNTRs counter" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 1. "IMNTR_EN,Enable the interrupt IMNTR" "0: Disable,1: Enable"
bitfld.long 0x00 0. "WAIT_SET,Enable the waiting interrupt mode when IMNTR_EN is Enable" "0: Disable,1: Enable"
repeat.end
repeat 16. (strings "336" "337" "338" "339" "340" "341" "342" "343" "344" "345" "346" "347" "348" "349" "350" "351" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x540)++0x03
line.long 0x00 "IMNTRCR$1,This register is functional safety use only"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Key Code"
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "NUM1_EN,Enable to use CNT_NUM1 for only assert period" "0: CNT_NUM1 is disable,1: CNT_NUM1 is enable"
bitfld.long 0x00 5.--6. "CNT_NUM1,Select the number of interrupt IMNTRs counter for only assert Period" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 4. "CNT_RESET,Reset the interrupt IMNTRs counter" "0: Ignored,1: Reset the counter"
newline
bitfld.long 0x00 2.--3. "CNT_NUM0,Select the number of interrupt IMNTRs counter" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 1. "IMNTR_EN,Enable the interrupt IMNTR" "0: Disable,1: Enable"
bitfld.long 0x00 0. "WAIT_SET,Enable the waiting interrupt mode when IMNTR_EN is Enable" "0: Disable,1: Enable"
repeat.end
repeat 16. (strings "352" "353" "354" "355" "356" "357" "358" "359" "360" "361" "362" "363" "364" "365" "366" "367" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x580)++0x03
line.long 0x00 "IMNTRCR$1,This register is functional safety use only"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Key Code"
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "NUM1_EN,Enable to use CNT_NUM1 for only assert period" "0: CNT_NUM1 is disable,1: CNT_NUM1 is enable"
bitfld.long 0x00 5.--6. "CNT_NUM1,Select the number of interrupt IMNTRs counter for only assert Period" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 4. "CNT_RESET,Reset the interrupt IMNTRs counter" "0: Ignored,1: Reset the counter"
newline
bitfld.long 0x00 2.--3. "CNT_NUM0,Select the number of interrupt IMNTRs counter" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 1. "IMNTR_EN,Enable the interrupt IMNTR" "0: Disable,1: Enable"
bitfld.long 0x00 0. "WAIT_SET,Enable the waiting interrupt mode when IMNTR_EN is Enable" "0: Disable,1: Enable"
repeat.end
repeat 16. (strings "368" "369" "370" "371" "372" "373" "374" "375" "376" "377" "378" "379" "380" "381" "382" "383" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x5C0)++0x03
line.long 0x00 "IMNTRCR$1,This register is functional safety use only"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Key Code"
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "NUM1_EN,Enable to use CNT_NUM1 for only assert period" "0: CNT_NUM1 is disable,1: CNT_NUM1 is enable"
bitfld.long 0x00 5.--6. "CNT_NUM1,Select the number of interrupt IMNTRs counter for only assert Period" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 4. "CNT_RESET,Reset the interrupt IMNTRs counter" "0: Ignored,1: Reset the counter"
newline
bitfld.long 0x00 2.--3. "CNT_NUM0,Select the number of interrupt IMNTRs counter" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 1. "IMNTR_EN,Enable the interrupt IMNTR" "0: Disable,1: Enable"
bitfld.long 0x00 0. "WAIT_SET,Enable the waiting interrupt mode when IMNTR_EN is Enable" "0: Disable,1: Enable"
repeat.end
repeat 16. (strings "384" "385" "386" "387" "388" "389" "390" "391" "392" "393" "394" "395" "396" "397" "398" "399" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x600)++0x03
line.long 0x00 "IMNTRCR$1,This register is functional safety use only"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Key Code"
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "NUM1_EN,Enable to use CNT_NUM1 for only assert period" "0: CNT_NUM1 is disable,1: CNT_NUM1 is enable"
bitfld.long 0x00 5.--6. "CNT_NUM1,Select the number of interrupt IMNTRs counter for only assert Period" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 4. "CNT_RESET,Reset the interrupt IMNTRs counter" "0: Ignored,1: Reset the counter"
newline
bitfld.long 0x00 2.--3. "CNT_NUM0,Select the number of interrupt IMNTRs counter" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 1. "IMNTR_EN,Enable the interrupt IMNTR" "0: Disable,1: Enable"
bitfld.long 0x00 0. "WAIT_SET,Enable the waiting interrupt mode when IMNTR_EN is Enable" "0: Disable,1: Enable"
repeat.end
repeat 16. (strings "400" "401" "402" "403" "404" "405" "406" "407" "408" "409" "410" "411" "412" "413" "414" "415" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x640)++0x03
line.long 0x00 "IMNTRCR$1,This register is functional safety use only"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Key Code"
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "NUM1_EN,Enable to use CNT_NUM1 for only assert period" "0: CNT_NUM1 is disable,1: CNT_NUM1 is enable"
bitfld.long 0x00 5.--6. "CNT_NUM1,Select the number of interrupt IMNTRs counter for only assert Period" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 4. "CNT_RESET,Reset the interrupt IMNTRs counter" "0: Ignored,1: Reset the counter"
newline
bitfld.long 0x00 2.--3. "CNT_NUM0,Select the number of interrupt IMNTRs counter" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 1. "IMNTR_EN,Enable the interrupt IMNTR" "0: Disable,1: Enable"
bitfld.long 0x00 0. "WAIT_SET,Enable the waiting interrupt mode when IMNTR_EN is Enable" "0: Disable,1: Enable"
repeat.end
repeat 16. (strings "416" "417" "418" "419" "420" "421" "422" "423" "424" "425" "426" "427" "428" "429" "430" "431" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x680)++0x03
line.long 0x00 "IMNTRCR$1,This register is functional safety use only"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Key Code"
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "NUM1_EN,Enable to use CNT_NUM1 for only assert period" "0: CNT_NUM1 is disable,1: CNT_NUM1 is enable"
bitfld.long 0x00 5.--6. "CNT_NUM1,Select the number of interrupt IMNTRs counter for only assert Period" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 4. "CNT_RESET,Reset the interrupt IMNTRs counter" "0: Ignored,1: Reset the counter"
newline
bitfld.long 0x00 2.--3. "CNT_NUM0,Select the number of interrupt IMNTRs counter" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 1. "IMNTR_EN,Enable the interrupt IMNTR" "0: Disable,1: Enable"
bitfld.long 0x00 0. "WAIT_SET,Enable the waiting interrupt mode when IMNTR_EN is Enable" "0: Disable,1: Enable"
repeat.end
repeat 16. (strings "432" "433" "434" "435" "436" "437" "438" "439" "440" "441" "442" "443" "444" "445" "446" "447" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x6C0)++0x03
line.long 0x00 "IMNTRCR$1,This register is functional safety use only"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Key Code"
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "NUM1_EN,Enable to use CNT_NUM1 for only assert period" "0: CNT_NUM1 is disable,1: CNT_NUM1 is enable"
bitfld.long 0x00 5.--6. "CNT_NUM1,Select the number of interrupt IMNTRs counter for only assert Period" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 4. "CNT_RESET,Reset the interrupt IMNTRs counter" "0: Ignored,1: Reset the counter"
newline
bitfld.long 0x00 2.--3. "CNT_NUM0,Select the number of interrupt IMNTRs counter" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 1. "IMNTR_EN,Enable the interrupt IMNTR" "0: Disable,1: Enable"
bitfld.long 0x00 0. "WAIT_SET,Enable the waiting interrupt mode when IMNTR_EN is Enable" "0: Disable,1: Enable"
repeat.end
repeat 16. (strings "448" "449" "450" "451" "452" "453" "454" "455" "456" "457" "458" "459" "460" "461" "462" "463" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x700)++0x03
line.long 0x00 "IMNTRCR$1,This register is functional safety use only"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Key Code"
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "NUM1_EN,Enable to use CNT_NUM1 for only assert period" "0: CNT_NUM1 is disable,1: CNT_NUM1 is enable"
bitfld.long 0x00 5.--6. "CNT_NUM1,Select the number of interrupt IMNTRs counter for only assert Period" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 4. "CNT_RESET,Reset the interrupt IMNTRs counter" "0: Ignored,1: Reset the counter"
newline
bitfld.long 0x00 2.--3. "CNT_NUM0,Select the number of interrupt IMNTRs counter" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 1. "IMNTR_EN,Enable the interrupt IMNTR" "0: Disable,1: Enable"
bitfld.long 0x00 0. "WAIT_SET,Enable the waiting interrupt mode when IMNTR_EN is Enable" "0: Disable,1: Enable"
repeat.end
repeat 16. (strings "464" "465" "466" "467" "468" "469" "470" "471" "472" "473" "474" "475" "476" "477" "478" "479" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x740)++0x03
line.long 0x00 "IMNTRCR$1,This register is functional safety use only"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Key Code"
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "NUM1_EN,Enable to use CNT_NUM1 for only assert period" "0: CNT_NUM1 is disable,1: CNT_NUM1 is enable"
bitfld.long 0x00 5.--6. "CNT_NUM1,Select the number of interrupt IMNTRs counter for only assert Period" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 4. "CNT_RESET,Reset the interrupt IMNTRs counter" "0: Ignored,1: Reset the counter"
newline
bitfld.long 0x00 2.--3. "CNT_NUM0,Select the number of interrupt IMNTRs counter" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 1. "IMNTR_EN,Enable the interrupt IMNTR" "0: Disable,1: Enable"
bitfld.long 0x00 0. "WAIT_SET,Enable the waiting interrupt mode when IMNTR_EN is Enable" "0: Disable,1: Enable"
repeat.end
repeat 16. (strings "480" "481" "482" "483" "484" "485" "486" "487" "488" "489" "490" "491" "492" "493" "494" "495" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x780)++0x03
line.long 0x00 "IMNTRCR$1,This register is functional safety use only"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Key Code"
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "NUM1_EN,Enable to use CNT_NUM1 for only assert period" "0: CNT_NUM1 is disable,1: CNT_NUM1 is enable"
bitfld.long 0x00 5.--6. "CNT_NUM1,Select the number of interrupt IMNTRs counter for only assert Period" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 4. "CNT_RESET,Reset the interrupt IMNTRs counter" "0: Ignored,1: Reset the counter"
newline
bitfld.long 0x00 2.--3. "CNT_NUM0,Select the number of interrupt IMNTRs counter" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 1. "IMNTR_EN,Enable the interrupt IMNTR" "0: Disable,1: Enable"
bitfld.long 0x00 0. "WAIT_SET,Enable the waiting interrupt mode when IMNTR_EN is Enable" "0: Disable,1: Enable"
repeat.end
repeat 16. (strings "496" "497" "498" "499" "500" "501" "502" "503" "504" "505" "506" "507" "508" "509" "510" "511" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x7C0)++0x03
line.long 0x00 "IMNTRCR$1,This register is functional safety use only"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Key Code"
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "NUM1_EN,Enable to use CNT_NUM1 for only assert period" "0: CNT_NUM1 is disable,1: CNT_NUM1 is enable"
bitfld.long 0x00 5.--6. "CNT_NUM1,Select the number of interrupt IMNTRs counter for only assert Period" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 4. "CNT_RESET,Reset the interrupt IMNTRs counter" "0: Ignored,1: Reset the counter"
newline
bitfld.long 0x00 2.--3. "CNT_NUM0,Select the number of interrupt IMNTRs counter" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 1. "IMNTR_EN,Enable the interrupt IMNTR" "0: Disable,1: Enable"
bitfld.long 0x00 0. "WAIT_SET,Enable the waiting interrupt mode when IMNTR_EN is Enable" "0: Disable,1: Enable"
repeat.end
repeat 16. (strings "512" "513" "514" "515" "516" "517" "518" "519" "520" "521" "522" "523" "524" "525" "526" "527" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x800)++0x03
line.long 0x00 "IMNTRCR$1,This register is functional safety use only"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Key Code"
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "NUM1_EN,Enable to use CNT_NUM1 for only assert period" "0: CNT_NUM1 is disable,1: CNT_NUM1 is enable"
bitfld.long 0x00 5.--6. "CNT_NUM1,Select the number of interrupt IMNTRs counter for only assert Period" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 4. "CNT_RESET,Reset the interrupt IMNTRs counter" "0: Ignored,1: Reset the counter"
newline
bitfld.long 0x00 2.--3. "CNT_NUM0,Select the number of interrupt IMNTRs counter" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 1. "IMNTR_EN,Enable the interrupt IMNTR" "0: Disable,1: Enable"
bitfld.long 0x00 0. "WAIT_SET,Enable the waiting interrupt mode when IMNTR_EN is Enable" "0: Disable,1: Enable"
repeat.end
repeat 16. (strings "528" "529" "530" "531" "532" "533" "534" "535" "536" "537" "538" "539" "540" "541" "542" "543" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x840)++0x03
line.long 0x00 "IMNTRCR$1,This register is functional safety use only"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Key Code"
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "NUM1_EN,Enable to use CNT_NUM1 for only assert period" "0: CNT_NUM1 is disable,1: CNT_NUM1 is enable"
bitfld.long 0x00 5.--6. "CNT_NUM1,Select the number of interrupt IMNTRs counter for only assert Period" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 4. "CNT_RESET,Reset the interrupt IMNTRs counter" "0: Ignored,1: Reset the counter"
newline
bitfld.long 0x00 2.--3. "CNT_NUM0,Select the number of interrupt IMNTRs counter" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 1. "IMNTR_EN,Enable the interrupt IMNTR" "0: Disable,1: Enable"
bitfld.long 0x00 0. "WAIT_SET,Enable the waiting interrupt mode when IMNTR_EN is Enable" "0: Disable,1: Enable"
repeat.end
repeat 16. (strings "544" "545" "546" "547" "548" "549" "550" "551" "552" "553" "554" "555" "556" "557" "558" "559" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x880)++0x03
line.long 0x00 "IMNTRCR$1,This register is functional safety use only"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Key Code"
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "NUM1_EN,Enable to use CNT_NUM1 for only assert period" "0: CNT_NUM1 is disable,1: CNT_NUM1 is enable"
bitfld.long 0x00 5.--6. "CNT_NUM1,Select the number of interrupt IMNTRs counter for only assert Period" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 4. "CNT_RESET,Reset the interrupt IMNTRs counter" "0: Ignored,1: Reset the counter"
newline
bitfld.long 0x00 2.--3. "CNT_NUM0,Select the number of interrupt IMNTRs counter" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 1. "IMNTR_EN,Enable the interrupt IMNTR" "0: Disable,1: Enable"
bitfld.long 0x00 0. "WAIT_SET,Enable the waiting interrupt mode when IMNTR_EN is Enable" "0: Disable,1: Enable"
repeat.end
repeat 16. (strings "560" "561" "562" "563" "564" "565" "566" "567" "568" "569" "570" "571" "572" "573" "574" "575" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x8C0)++0x03
line.long 0x00 "IMNTRCR$1,This register is functional safety use only"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Key Code"
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "NUM1_EN,Enable to use CNT_NUM1 for only assert period" "0: CNT_NUM1 is disable,1: CNT_NUM1 is enable"
bitfld.long 0x00 5.--6. "CNT_NUM1,Select the number of interrupt IMNTRs counter for only assert Period" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 4. "CNT_RESET,Reset the interrupt IMNTRs counter" "0: Ignored,1: Reset the counter"
newline
bitfld.long 0x00 2.--3. "CNT_NUM0,Select the number of interrupt IMNTRs counter" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 1. "IMNTR_EN,Enable the interrupt IMNTR" "0: Disable,1: Enable"
bitfld.long 0x00 0. "WAIT_SET,Enable the waiting interrupt mode when IMNTR_EN is Enable" "0: Disable,1: Enable"
repeat.end
repeat 16. (strings "576" "577" "578" "579" "580" "581" "582" "583" "584" "585" "586" "587" "588" "589" "590" "591" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x900)++0x03
line.long 0x00 "IMNTRCR$1,This register is functional safety use only"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Key Code"
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "NUM1_EN,Enable to use CNT_NUM1 for only assert period" "0: CNT_NUM1 is disable,1: CNT_NUM1 is enable"
bitfld.long 0x00 5.--6. "CNT_NUM1,Select the number of interrupt IMNTRs counter for only assert Period" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 4. "CNT_RESET,Reset the interrupt IMNTRs counter" "0: Ignored,1: Reset the counter"
newline
bitfld.long 0x00 2.--3. "CNT_NUM0,Select the number of interrupt IMNTRs counter" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 1. "IMNTR_EN,Enable the interrupt IMNTR" "0: Disable,1: Enable"
bitfld.long 0x00 0. "WAIT_SET,Enable the waiting interrupt mode when IMNTR_EN is Enable" "0: Disable,1: Enable"
repeat.end
repeat 16. (strings "592" "593" "594" "595" "596" "597" "598" "599" "600" "601" "602" "603" "604" "605" "606" "607" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x940)++0x03
line.long 0x00 "IMNTRCR$1,This register is functional safety use only"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Key Code"
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "NUM1_EN,Enable to use CNT_NUM1 for only assert period" "0: CNT_NUM1 is disable,1: CNT_NUM1 is enable"
bitfld.long 0x00 5.--6. "CNT_NUM1,Select the number of interrupt IMNTRs counter for only assert Period" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 4. "CNT_RESET,Reset the interrupt IMNTRs counter" "0: Ignored,1: Reset the counter"
newline
bitfld.long 0x00 2.--3. "CNT_NUM0,Select the number of interrupt IMNTRs counter" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 1. "IMNTR_EN,Enable the interrupt IMNTR" "0: Disable,1: Enable"
bitfld.long 0x00 0. "WAIT_SET,Enable the waiting interrupt mode when IMNTR_EN is Enable" "0: Disable,1: Enable"
repeat.end
repeat 16. (strings "608" "609" "610" "611" "612" "613" "614" "615" "616" "617" "618" "619" "620" "621" "622" "623" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x980)++0x03
line.long 0x00 "IMNTRCR$1,This register is functional safety use only"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Key Code"
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "NUM1_EN,Enable to use CNT_NUM1 for only assert period" "0: CNT_NUM1 is disable,1: CNT_NUM1 is enable"
bitfld.long 0x00 5.--6. "CNT_NUM1,Select the number of interrupt IMNTRs counter for only assert Period" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 4. "CNT_RESET,Reset the interrupt IMNTRs counter" "0: Ignored,1: Reset the counter"
newline
bitfld.long 0x00 2.--3. "CNT_NUM0,Select the number of interrupt IMNTRs counter" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 1. "IMNTR_EN,Enable the interrupt IMNTR" "0: Disable,1: Enable"
bitfld.long 0x00 0. "WAIT_SET,Enable the waiting interrupt mode when IMNTR_EN is Enable" "0: Disable,1: Enable"
repeat.end
repeat 16. (strings "624" "625" "626" "627" "628" "629" "630" "631" "632" "633" "634" "635" "636" "637" "638" "639" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x9C0)++0x03
line.long 0x00 "IMNTRCR$1,This register is functional safety use only"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Key Code"
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "NUM1_EN,Enable to use CNT_NUM1 for only assert period" "0: CNT_NUM1 is disable,1: CNT_NUM1 is enable"
bitfld.long 0x00 5.--6. "CNT_NUM1,Select the number of interrupt IMNTRs counter for only assert Period" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 4. "CNT_RESET,Reset the interrupt IMNTRs counter" "0: Ignored,1: Reset the counter"
newline
bitfld.long 0x00 2.--3. "CNT_NUM0,Select the number of interrupt IMNTRs counter" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 1. "IMNTR_EN,Enable the interrupt IMNTR" "0: Disable,1: Enable"
bitfld.long 0x00 0. "WAIT_SET,Enable the waiting interrupt mode when IMNTR_EN is Enable" "0: Disable,1: Enable"
repeat.end
repeat 16. (strings "640" "641" "642" "643" "644" "645" "646" "647" "648" "649" "650" "651" "652" "653" "654" "655" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0xA00)++0x03
line.long 0x00 "IMNTRCR$1,This register is functional safety use only"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Key Code"
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "NUM1_EN,Enable to use CNT_NUM1 for only assert period" "0: CNT_NUM1 is disable,1: CNT_NUM1 is enable"
bitfld.long 0x00 5.--6. "CNT_NUM1,Select the number of interrupt IMNTRs counter for only assert Period" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 4. "CNT_RESET,Reset the interrupt IMNTRs counter" "0: Ignored,1: Reset the counter"
newline
bitfld.long 0x00 2.--3. "CNT_NUM0,Select the number of interrupt IMNTRs counter" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 1. "IMNTR_EN,Enable the interrupt IMNTR" "0: Disable,1: Enable"
bitfld.long 0x00 0. "WAIT_SET,Enable the waiting interrupt mode when IMNTR_EN is Enable" "0: Disable,1: Enable"
repeat.end
repeat 16. (strings "656" "657" "658" "659" "660" "661" "662" "663" "664" "665" "666" "667" "668" "669" "670" "671" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0xA40)++0x03
line.long 0x00 "IMNTRCR$1,This register is functional safety use only"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Key Code"
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "NUM1_EN,Enable to use CNT_NUM1 for only assert period" "0: CNT_NUM1 is disable,1: CNT_NUM1 is enable"
bitfld.long 0x00 5.--6. "CNT_NUM1,Select the number of interrupt IMNTRs counter for only assert Period" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 4. "CNT_RESET,Reset the interrupt IMNTRs counter" "0: Ignored,1: Reset the counter"
newline
bitfld.long 0x00 2.--3. "CNT_NUM0,Select the number of interrupt IMNTRs counter" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 1. "IMNTR_EN,Enable the interrupt IMNTR" "0: Disable,1: Enable"
bitfld.long 0x00 0. "WAIT_SET,Enable the waiting interrupt mode when IMNTR_EN is Enable" "0: Disable,1: Enable"
repeat.end
repeat 16. (strings "672" "673" "674" "675" "676" "677" "678" "679" "680" "681" "682" "683" "684" "685" "686" "687" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0xA80)++0x03
line.long 0x00 "IMNTRCR$1,This register is functional safety use only"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Key Code"
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "NUM1_EN,Enable to use CNT_NUM1 for only assert period" "0: CNT_NUM1 is disable,1: CNT_NUM1 is enable"
bitfld.long 0x00 5.--6. "CNT_NUM1,Select the number of interrupt IMNTRs counter for only assert Period" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 4. "CNT_RESET,Reset the interrupt IMNTRs counter" "0: Ignored,1: Reset the counter"
newline
bitfld.long 0x00 2.--3. "CNT_NUM0,Select the number of interrupt IMNTRs counter" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 1. "IMNTR_EN,Enable the interrupt IMNTR" "0: Disable,1: Enable"
bitfld.long 0x00 0. "WAIT_SET,Enable the waiting interrupt mode when IMNTR_EN is Enable" "0: Disable,1: Enable"
repeat.end
repeat 16. (strings "688" "689" "690" "691" "692" "693" "694" "695" "696" "697" "698" "699" "700" "701" "702" "703" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0xAC0)++0x03
line.long 0x00 "IMNTRCR$1,This register is functional safety use only"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Key Code"
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "NUM1_EN,Enable to use CNT_NUM1 for only assert period" "0: CNT_NUM1 is disable,1: CNT_NUM1 is enable"
bitfld.long 0x00 5.--6. "CNT_NUM1,Select the number of interrupt IMNTRs counter for only assert Period" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 4. "CNT_RESET,Reset the interrupt IMNTRs counter" "0: Ignored,1: Reset the counter"
newline
bitfld.long 0x00 2.--3. "CNT_NUM0,Select the number of interrupt IMNTRs counter" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 1. "IMNTR_EN,Enable the interrupt IMNTR" "0: Disable,1: Enable"
bitfld.long 0x00 0. "WAIT_SET,Enable the waiting interrupt mode when IMNTR_EN is Enable" "0: Disable,1: Enable"
repeat.end
repeat 16. (strings "704" "705" "706" "707" "708" "709" "710" "711" "712" "713" "714" "715" "716" "717" "718" "719" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0xB00)++0x03
line.long 0x00 "IMNTRCR$1,This register is functional safety use only"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Key Code"
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "NUM1_EN,Enable to use CNT_NUM1 for only assert period" "0: CNT_NUM1 is disable,1: CNT_NUM1 is enable"
bitfld.long 0x00 5.--6. "CNT_NUM1,Select the number of interrupt IMNTRs counter for only assert Period" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 4. "CNT_RESET,Reset the interrupt IMNTRs counter" "0: Ignored,1: Reset the counter"
newline
bitfld.long 0x00 2.--3. "CNT_NUM0,Select the number of interrupt IMNTRs counter" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 1. "IMNTR_EN,Enable the interrupt IMNTR" "0: Disable,1: Enable"
bitfld.long 0x00 0. "WAIT_SET,Enable the waiting interrupt mode when IMNTR_EN is Enable" "0: Disable,1: Enable"
repeat.end
repeat 16. (strings "720" "721" "722" "723" "724" "725" "726" "727" "728" "729" "730" "731" "732" "733" "734" "735" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0xB40)++0x03
line.long 0x00 "IMNTRCR$1,This register is functional safety use only"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Key Code"
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "NUM1_EN,Enable to use CNT_NUM1 for only assert period" "0: CNT_NUM1 is disable,1: CNT_NUM1 is enable"
bitfld.long 0x00 5.--6. "CNT_NUM1,Select the number of interrupt IMNTRs counter for only assert Period" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 4. "CNT_RESET,Reset the interrupt IMNTRs counter" "0: Ignored,1: Reset the counter"
newline
bitfld.long 0x00 2.--3. "CNT_NUM0,Select the number of interrupt IMNTRs counter" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 1. "IMNTR_EN,Enable the interrupt IMNTR" "0: Disable,1: Enable"
bitfld.long 0x00 0. "WAIT_SET,Enable the waiting interrupt mode when IMNTR_EN is Enable" "0: Disable,1: Enable"
repeat.end
repeat 16. (strings "736" "737" "738" "739" "740" "741" "742" "743" "744" "745" "746" "747" "748" "749" "750" "751" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0xB80)++0x03
line.long 0x00 "IMNTRCR$1,This register is functional safety use only"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Key Code"
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "NUM1_EN,Enable to use CNT_NUM1 for only assert period" "0: CNT_NUM1 is disable,1: CNT_NUM1 is enable"
bitfld.long 0x00 5.--6. "CNT_NUM1,Select the number of interrupt IMNTRs counter for only assert Period" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 4. "CNT_RESET,Reset the interrupt IMNTRs counter" "0: Ignored,1: Reset the counter"
newline
bitfld.long 0x00 2.--3. "CNT_NUM0,Select the number of interrupt IMNTRs counter" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 1. "IMNTR_EN,Enable the interrupt IMNTR" "0: Disable,1: Enable"
bitfld.long 0x00 0. "WAIT_SET,Enable the waiting interrupt mode when IMNTR_EN is Enable" "0: Disable,1: Enable"
repeat.end
repeat 16. (strings "752" "753" "754" "755" "756" "757" "758" "759" "760" "761" "762" "763" "764" "765" "766" "767" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0xBC0)++0x03
line.long 0x00 "IMNTRCR$1,This register is functional safety use only"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Key Code"
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "NUM1_EN,Enable to use CNT_NUM1 for only assert period" "0: CNT_NUM1 is disable,1: CNT_NUM1 is enable"
bitfld.long 0x00 5.--6. "CNT_NUM1,Select the number of interrupt IMNTRs counter for only assert Period" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 4. "CNT_RESET,Reset the interrupt IMNTRs counter" "0: Ignored,1: Reset the counter"
newline
bitfld.long 0x00 2.--3. "CNT_NUM0,Select the number of interrupt IMNTRs counter" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 1. "IMNTR_EN,Enable the interrupt IMNTR" "0: Disable,1: Enable"
bitfld.long 0x00 0. "WAIT_SET,Enable the waiting interrupt mode when IMNTR_EN is Enable" "0: Disable,1: Enable"
repeat.end
repeat 16. (strings "768" "769" "770" "771" "772" "773" "774" "775" "776" "777" "778" "779" "780" "781" "782" "783" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0xC00)++0x03
line.long 0x00 "IMNTRCR$1,This register is functional safety use only"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Key Code"
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "NUM1_EN,Enable to use CNT_NUM1 for only assert period" "0: CNT_NUM1 is disable,1: CNT_NUM1 is enable"
bitfld.long 0x00 5.--6. "CNT_NUM1,Select the number of interrupt IMNTRs counter for only assert Period" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 4. "CNT_RESET,Reset the interrupt IMNTRs counter" "0: Ignored,1: Reset the counter"
newline
bitfld.long 0x00 2.--3. "CNT_NUM0,Select the number of interrupt IMNTRs counter" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 1. "IMNTR_EN,Enable the interrupt IMNTR" "0: Disable,1: Enable"
bitfld.long 0x00 0. "WAIT_SET,Enable the waiting interrupt mode when IMNTR_EN is Enable" "0: Disable,1: Enable"
repeat.end
repeat 16. (strings "784" "785" "786" "787" "788" "789" "790" "791" "792" "793" "794" "795" "796" "797" "798" "799" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0xC40)++0x03
line.long 0x00 "IMNTRCR$1,This register is functional safety use only"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Key Code"
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "NUM1_EN,Enable to use CNT_NUM1 for only assert period" "0: CNT_NUM1 is disable,1: CNT_NUM1 is enable"
bitfld.long 0x00 5.--6. "CNT_NUM1,Select the number of interrupt IMNTRs counter for only assert Period" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 4. "CNT_RESET,Reset the interrupt IMNTRs counter" "0: Ignored,1: Reset the counter"
newline
bitfld.long 0x00 2.--3. "CNT_NUM0,Select the number of interrupt IMNTRs counter" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 1. "IMNTR_EN,Enable the interrupt IMNTR" "0: Disable,1: Enable"
bitfld.long 0x00 0. "WAIT_SET,Enable the waiting interrupt mode when IMNTR_EN is Enable" "0: Disable,1: Enable"
repeat.end
repeat 16. (strings "800" "801" "802" "803" "804" "805" "806" "807" "808" "809" "810" "811" "812" "813" "814" "815" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0xC80)++0x03
line.long 0x00 "IMNTRCR$1,This register is functional safety use only"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Key Code"
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "NUM1_EN,Enable to use CNT_NUM1 for only assert period" "0: CNT_NUM1 is disable,1: CNT_NUM1 is enable"
bitfld.long 0x00 5.--6. "CNT_NUM1,Select the number of interrupt IMNTRs counter for only assert Period" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 4. "CNT_RESET,Reset the interrupt IMNTRs counter" "0: Ignored,1: Reset the counter"
newline
bitfld.long 0x00 2.--3. "CNT_NUM0,Select the number of interrupt IMNTRs counter" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 1. "IMNTR_EN,Enable the interrupt IMNTR" "0: Disable,1: Enable"
bitfld.long 0x00 0. "WAIT_SET,Enable the waiting interrupt mode when IMNTR_EN is Enable" "0: Disable,1: Enable"
repeat.end
repeat 16. (strings "816" "817" "818" "819" "820" "821" "822" "823" "824" "825" "826" "827" "828" "829" "830" "831" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0xCC0)++0x03
line.long 0x00 "IMNTRCR$1,This register is functional safety use only"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Key Code"
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "NUM1_EN,Enable to use CNT_NUM1 for only assert period" "0: CNT_NUM1 is disable,1: CNT_NUM1 is enable"
bitfld.long 0x00 5.--6. "CNT_NUM1,Select the number of interrupt IMNTRs counter for only assert Period" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 4. "CNT_RESET,Reset the interrupt IMNTRs counter" "0: Ignored,1: Reset the counter"
newline
bitfld.long 0x00 2.--3. "CNT_NUM0,Select the number of interrupt IMNTRs counter" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 1. "IMNTR_EN,Enable the interrupt IMNTR" "0: Disable,1: Enable"
bitfld.long 0x00 0. "WAIT_SET,Enable the waiting interrupt mode when IMNTR_EN is Enable" "0: Disable,1: Enable"
repeat.end
repeat 16. (strings "832" "833" "834" "835" "836" "837" "838" "839" "840" "841" "842" "843" "844" "845" "846" "847" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0xD00)++0x03
line.long 0x00 "IMNTRCR$1,This register is functional safety use only"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Key Code"
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "NUM1_EN,Enable to use CNT_NUM1 for only assert period" "0: CNT_NUM1 is disable,1: CNT_NUM1 is enable"
bitfld.long 0x00 5.--6. "CNT_NUM1,Select the number of interrupt IMNTRs counter for only assert Period" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 4. "CNT_RESET,Reset the interrupt IMNTRs counter" "0: Ignored,1: Reset the counter"
newline
bitfld.long 0x00 2.--3. "CNT_NUM0,Select the number of interrupt IMNTRs counter" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 1. "IMNTR_EN,Enable the interrupt IMNTR" "0: Disable,1: Enable"
bitfld.long 0x00 0. "WAIT_SET,Enable the waiting interrupt mode when IMNTR_EN is Enable" "0: Disable,1: Enable"
repeat.end
repeat 16. (strings "848" "849" "850" "851" "852" "853" "854" "855" "856" "857" "858" "859" "860" "861" "862" "863" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0xD40)++0x03
line.long 0x00 "IMNTRCR$1,This register is functional safety use only"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Key Code"
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "NUM1_EN,Enable to use CNT_NUM1 for only assert period" "0: CNT_NUM1 is disable,1: CNT_NUM1 is enable"
bitfld.long 0x00 5.--6. "CNT_NUM1,Select the number of interrupt IMNTRs counter for only assert Period" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 4. "CNT_RESET,Reset the interrupt IMNTRs counter" "0: Ignored,1: Reset the counter"
newline
bitfld.long 0x00 2.--3. "CNT_NUM0,Select the number of interrupt IMNTRs counter" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 1. "IMNTR_EN,Enable the interrupt IMNTR" "0: Disable,1: Enable"
bitfld.long 0x00 0. "WAIT_SET,Enable the waiting interrupt mode when IMNTR_EN is Enable" "0: Disable,1: Enable"
repeat.end
repeat 16. (strings "864" "865" "866" "867" "868" "869" "870" "871" "872" "873" "874" "875" "876" "877" "878" "879" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0xD80)++0x03
line.long 0x00 "IMNTRCR$1,This register is functional safety use only"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Key Code"
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "NUM1_EN,Enable to use CNT_NUM1 for only assert period" "0: CNT_NUM1 is disable,1: CNT_NUM1 is enable"
bitfld.long 0x00 5.--6. "CNT_NUM1,Select the number of interrupt IMNTRs counter for only assert Period" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 4. "CNT_RESET,Reset the interrupt IMNTRs counter" "0: Ignored,1: Reset the counter"
newline
bitfld.long 0x00 2.--3. "CNT_NUM0,Select the number of interrupt IMNTRs counter" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 1. "IMNTR_EN,Enable the interrupt IMNTR" "0: Disable,1: Enable"
bitfld.long 0x00 0. "WAIT_SET,Enable the waiting interrupt mode when IMNTR_EN is Enable" "0: Disable,1: Enable"
repeat.end
repeat 16. (strings "880" "881" "882" "883" "884" "885" "886" "887" "888" "889" "890" "891" "892" "893" "894" "895" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0xDC0)++0x03
line.long 0x00 "IMNTRCR$1,This register is functional safety use only"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Key Code"
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "NUM1_EN,Enable to use CNT_NUM1 for only assert period" "0: CNT_NUM1 is disable,1: CNT_NUM1 is enable"
bitfld.long 0x00 5.--6. "CNT_NUM1,Select the number of interrupt IMNTRs counter for only assert Period" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 4. "CNT_RESET,Reset the interrupt IMNTRs counter" "0: Ignored,1: Reset the counter"
newline
bitfld.long 0x00 2.--3. "CNT_NUM0,Select the number of interrupt IMNTRs counter" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 1. "IMNTR_EN,Enable the interrupt IMNTR" "0: Disable,1: Enable"
bitfld.long 0x00 0. "WAIT_SET,Enable the waiting interrupt mode when IMNTR_EN is Enable" "0: Disable,1: Enable"
repeat.end
repeat 16. (strings "896" "897" "898" "899" "900" "901" "902" "903" "904" "905" "906" "907" "908" "909" "910" "911" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0xE00)++0x03
line.long 0x00 "IMNTRCR$1,This register is functional safety use only"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Key Code"
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "NUM1_EN,Enable to use CNT_NUM1 for only assert period" "0: CNT_NUM1 is disable,1: CNT_NUM1 is enable"
bitfld.long 0x00 5.--6. "CNT_NUM1,Select the number of interrupt IMNTRs counter for only assert Period" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 4. "CNT_RESET,Reset the interrupt IMNTRs counter" "0: Ignored,1: Reset the counter"
newline
bitfld.long 0x00 2.--3. "CNT_NUM0,Select the number of interrupt IMNTRs counter" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 1. "IMNTR_EN,Enable the interrupt IMNTR" "0: Disable,1: Enable"
bitfld.long 0x00 0. "WAIT_SET,Enable the waiting interrupt mode when IMNTR_EN is Enable" "0: Disable,1: Enable"
repeat.end
repeat 16. (strings "912" "913" "914" "915" "916" "917" "918" "919" "920" "921" "922" "923" "924" "925" "926" "927" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0xE40)++0x03
line.long 0x00 "IMNTRCR$1,This register is functional safety use only"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Key Code"
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "NUM1_EN,Enable to use CNT_NUM1 for only assert period" "0: CNT_NUM1 is disable,1: CNT_NUM1 is enable"
bitfld.long 0x00 5.--6. "CNT_NUM1,Select the number of interrupt IMNTRs counter for only assert Period" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 4. "CNT_RESET,Reset the interrupt IMNTRs counter" "0: Ignored,1: Reset the counter"
newline
bitfld.long 0x00 2.--3. "CNT_NUM0,Select the number of interrupt IMNTRs counter" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 1. "IMNTR_EN,Enable the interrupt IMNTR" "0: Disable,1: Enable"
bitfld.long 0x00 0. "WAIT_SET,Enable the waiting interrupt mode when IMNTR_EN is Enable" "0: Disable,1: Enable"
repeat.end
repeat 16. (strings "928" "929" "930" "931" "932" "933" "934" "935" "936" "937" "938" "939" "940" "941" "942" "943" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0xE80)++0x03
line.long 0x00 "IMNTRCR$1,This register is functional safety use only"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Key Code"
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "NUM1_EN,Enable to use CNT_NUM1 for only assert period" "0: CNT_NUM1 is disable,1: CNT_NUM1 is enable"
bitfld.long 0x00 5.--6. "CNT_NUM1,Select the number of interrupt IMNTRs counter for only assert Period" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 4. "CNT_RESET,Reset the interrupt IMNTRs counter" "0: Ignored,1: Reset the counter"
newline
bitfld.long 0x00 2.--3. "CNT_NUM0,Select the number of interrupt IMNTRs counter" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 1. "IMNTR_EN,Enable the interrupt IMNTR" "0: Disable,1: Enable"
bitfld.long 0x00 0. "WAIT_SET,Enable the waiting interrupt mode when IMNTR_EN is Enable" "0: Disable,1: Enable"
repeat.end
repeat 16. (strings "944" "945" "946" "947" "948" "949" "950" "951" "952" "953" "954" "955" "956" "957" "958" "959" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0xEC0)++0x03
line.long 0x00 "IMNTRCR$1,This register is functional safety use only"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Key Code"
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "NUM1_EN,Enable to use CNT_NUM1 for only assert period" "0: CNT_NUM1 is disable,1: CNT_NUM1 is enable"
bitfld.long 0x00 5.--6. "CNT_NUM1,Select the number of interrupt IMNTRs counter for only assert Period" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 4. "CNT_RESET,Reset the interrupt IMNTRs counter" "0: Ignored,1: Reset the counter"
newline
bitfld.long 0x00 2.--3. "CNT_NUM0,Select the number of interrupt IMNTRs counter" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 1. "IMNTR_EN,Enable the interrupt IMNTR" "0: Disable,1: Enable"
bitfld.long 0x00 0. "WAIT_SET,Enable the waiting interrupt mode when IMNTR_EN is Enable" "0: Disable,1: Enable"
repeat.end
repeat 8. (strings "960" "961" "962" "963" "964" "965" "966" "967" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C )
group.long ($2+0xF00)++0x03
line.long 0x00 "IMNTRCR$1,This register is functional safety use only"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Key Code"
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "NUM1_EN,Enable to use CNT_NUM1 for only assert period" "0: CNT_NUM1 is disable,1: CNT_NUM1 is enable"
bitfld.long 0x00 5.--6. "CNT_NUM1,Select the number of interrupt IMNTRs counter for only assert Period" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 4. "CNT_RESET,Reset the interrupt IMNTRs counter" "0: Ignored,1: Reset the counter"
newline
bitfld.long 0x00 2.--3. "CNT_NUM0,Select the number of interrupt IMNTRs counter" "0: 32,1: 64,2: 128,3: 256"
bitfld.long 0x00 1. "IMNTR_EN,Enable the interrupt IMNTR" "0: Disable,1: Enable"
bitfld.long 0x00 0. "WAIT_SET,Enable the waiting interrupt mode when IMNTR_EN is Enable" "0: Disable,1: Enable"
repeat.end
tree.end
tree "INTC_INST_2"
base ad:0xFFEA3000
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x00)++0x03
line.long 0x00 "IMNTRSR$1,This register is functional safety use only"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Key Code"
eventfld.long 0x00 15. "CNT_ERR7,Show the error state of count up mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 14. "WAIT_ERR7,Show the error state of waiting interrupt mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 13. "CNT_ERR6,Show the error state of count up mode" "0: Ignored,1: Clear this bit"
newline
eventfld.long 0x00 12. "WAIT_ERR6,Show the error state of waiting interrupt mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 11. "CNT_ERR5,Show the error state of count up mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 10. "WAIT_ERR5,Show the error state of waiting interrupt mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 9. "CNT_ERR4,Show the error state of count up mode" "0: Ignored,1: Clear this bit"
newline
eventfld.long 0x00 8. "WAIT_ERR4,Show the error state of waiting interrupt mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 7. "CNT_ERR3,Show the error state of count up mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 6. "WAIT_ERR3,Show the error state of waiting interrupt mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 5. "CNT_ERR2,Show the error state of count up mode" "0: Ignored,1: Clear this bit"
newline
eventfld.long 0x00 4. "WAIT_ERR2,Show the error state of waiting interrupt mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 3. "CNT_ERR1,Show the error state of count up mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 2. "WAIT_ERR1,Show the error state of waiting interrupt mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 1. "CNT_ERR0,Show the error state of count up mode" "0: Ignored,1: Clear this bit"
newline
eventfld.long 0x00 0. "WAIT_ERR0,Show the error state of waiting interrupt mode" "0: Ignored,1: Clear this bit"
repeat.end
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x40)++0x03
line.long 0x00 "IMNTRSR$1,This register is functional safety use only"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Key Code"
eventfld.long 0x00 15. "CNT_ERR7,Show the error state of count up mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 14. "WAIT_ERR7,Show the error state of waiting interrupt mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 13. "CNT_ERR6,Show the error state of count up mode" "0: Ignored,1: Clear this bit"
newline
eventfld.long 0x00 12. "WAIT_ERR6,Show the error state of waiting interrupt mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 11. "CNT_ERR5,Show the error state of count up mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 10. "WAIT_ERR5,Show the error state of waiting interrupt mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 9. "CNT_ERR4,Show the error state of count up mode" "0: Ignored,1: Clear this bit"
newline
eventfld.long 0x00 8. "WAIT_ERR4,Show the error state of waiting interrupt mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 7. "CNT_ERR3,Show the error state of count up mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 6. "WAIT_ERR3,Show the error state of waiting interrupt mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 5. "CNT_ERR2,Show the error state of count up mode" "0: Ignored,1: Clear this bit"
newline
eventfld.long 0x00 4. "WAIT_ERR2,Show the error state of waiting interrupt mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 3. "CNT_ERR1,Show the error state of count up mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 2. "WAIT_ERR1,Show the error state of waiting interrupt mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 1. "CNT_ERR0,Show the error state of count up mode" "0: Ignored,1: Clear this bit"
newline
eventfld.long 0x00 0. "WAIT_ERR0,Show the error state of waiting interrupt mode" "0: Ignored,1: Clear this bit"
repeat.end
repeat 16. (strings "32" "33" "34" "35" "36" "37" "38" "39" "40" "41" "42" "43" "44" "45" "46" "47" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x80)++0x03
line.long 0x00 "IMNTRSR$1,This register is functional safety use only"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Key Code"
eventfld.long 0x00 15. "CNT_ERR7,Show the error state of count up mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 14. "WAIT_ERR7,Show the error state of waiting interrupt mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 13. "CNT_ERR6,Show the error state of count up mode" "0: Ignored,1: Clear this bit"
newline
eventfld.long 0x00 12. "WAIT_ERR6,Show the error state of waiting interrupt mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 11. "CNT_ERR5,Show the error state of count up mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 10. "WAIT_ERR5,Show the error state of waiting interrupt mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 9. "CNT_ERR4,Show the error state of count up mode" "0: Ignored,1: Clear this bit"
newline
eventfld.long 0x00 8. "WAIT_ERR4,Show the error state of waiting interrupt mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 7. "CNT_ERR3,Show the error state of count up mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 6. "WAIT_ERR3,Show the error state of waiting interrupt mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 5. "CNT_ERR2,Show the error state of count up mode" "0: Ignored,1: Clear this bit"
newline
eventfld.long 0x00 4. "WAIT_ERR2,Show the error state of waiting interrupt mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 3. "CNT_ERR1,Show the error state of count up mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 2. "WAIT_ERR1,Show the error state of waiting interrupt mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 1. "CNT_ERR0,Show the error state of count up mode" "0: Ignored,1: Clear this bit"
newline
eventfld.long 0x00 0. "WAIT_ERR0,Show the error state of waiting interrupt mode" "0: Ignored,1: Clear this bit"
repeat.end
repeat 16. (strings "48" "49" "50" "51" "52" "53" "54" "55" "56" "57" "58" "59" "60" "61" "62" "63" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0xC0)++0x03
line.long 0x00 "IMNTRSR$1,This register is functional safety use only"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Key Code"
eventfld.long 0x00 15. "CNT_ERR7,Show the error state of count up mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 14. "WAIT_ERR7,Show the error state of waiting interrupt mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 13. "CNT_ERR6,Show the error state of count up mode" "0: Ignored,1: Clear this bit"
newline
eventfld.long 0x00 12. "WAIT_ERR6,Show the error state of waiting interrupt mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 11. "CNT_ERR5,Show the error state of count up mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 10. "WAIT_ERR5,Show the error state of waiting interrupt mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 9. "CNT_ERR4,Show the error state of count up mode" "0: Ignored,1: Clear this bit"
newline
eventfld.long 0x00 8. "WAIT_ERR4,Show the error state of waiting interrupt mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 7. "CNT_ERR3,Show the error state of count up mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 6. "WAIT_ERR3,Show the error state of waiting interrupt mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 5. "CNT_ERR2,Show the error state of count up mode" "0: Ignored,1: Clear this bit"
newline
eventfld.long 0x00 4. "WAIT_ERR2,Show the error state of waiting interrupt mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 3. "CNT_ERR1,Show the error state of count up mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 2. "WAIT_ERR1,Show the error state of waiting interrupt mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 1. "CNT_ERR0,Show the error state of count up mode" "0: Ignored,1: Clear this bit"
newline
eventfld.long 0x00 0. "WAIT_ERR0,Show the error state of waiting interrupt mode" "0: Ignored,1: Clear this bit"
repeat.end
repeat 16. (strings "64" "65" "66" "67" "68" "69" "70" "71" "72" "73" "74" "75" "76" "77" "78" "79" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x100)++0x03
line.long 0x00 "IMNTRSR$1,This register is functional safety use only"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Key Code"
eventfld.long 0x00 15. "CNT_ERR7,Show the error state of count up mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 14. "WAIT_ERR7,Show the error state of waiting interrupt mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 13. "CNT_ERR6,Show the error state of count up mode" "0: Ignored,1: Clear this bit"
newline
eventfld.long 0x00 12. "WAIT_ERR6,Show the error state of waiting interrupt mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 11. "CNT_ERR5,Show the error state of count up mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 10. "WAIT_ERR5,Show the error state of waiting interrupt mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 9. "CNT_ERR4,Show the error state of count up mode" "0: Ignored,1: Clear this bit"
newline
eventfld.long 0x00 8. "WAIT_ERR4,Show the error state of waiting interrupt mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 7. "CNT_ERR3,Show the error state of count up mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 6. "WAIT_ERR3,Show the error state of waiting interrupt mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 5. "CNT_ERR2,Show the error state of count up mode" "0: Ignored,1: Clear this bit"
newline
eventfld.long 0x00 4. "WAIT_ERR2,Show the error state of waiting interrupt mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 3. "CNT_ERR1,Show the error state of count up mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 2. "WAIT_ERR1,Show the error state of waiting interrupt mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 1. "CNT_ERR0,Show the error state of count up mode" "0: Ignored,1: Clear this bit"
newline
eventfld.long 0x00 0. "WAIT_ERR0,Show the error state of waiting interrupt mode" "0: Ignored,1: Clear this bit"
repeat.end
repeat 16. (strings "80" "81" "82" "83" "84" "85" "86" "87" "88" "89" "90" "91" "92" "93" "94" "95" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x140)++0x03
line.long 0x00 "IMNTRSR$1,This register is functional safety use only"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Key Code"
eventfld.long 0x00 15. "CNT_ERR7,Show the error state of count up mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 14. "WAIT_ERR7,Show the error state of waiting interrupt mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 13. "CNT_ERR6,Show the error state of count up mode" "0: Ignored,1: Clear this bit"
newline
eventfld.long 0x00 12. "WAIT_ERR6,Show the error state of waiting interrupt mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 11. "CNT_ERR5,Show the error state of count up mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 10. "WAIT_ERR5,Show the error state of waiting interrupt mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 9. "CNT_ERR4,Show the error state of count up mode" "0: Ignored,1: Clear this bit"
newline
eventfld.long 0x00 8. "WAIT_ERR4,Show the error state of waiting interrupt mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 7. "CNT_ERR3,Show the error state of count up mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 6. "WAIT_ERR3,Show the error state of waiting interrupt mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 5. "CNT_ERR2,Show the error state of count up mode" "0: Ignored,1: Clear this bit"
newline
eventfld.long 0x00 4. "WAIT_ERR2,Show the error state of waiting interrupt mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 3. "CNT_ERR1,Show the error state of count up mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 2. "WAIT_ERR1,Show the error state of waiting interrupt mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 1. "CNT_ERR0,Show the error state of count up mode" "0: Ignored,1: Clear this bit"
newline
eventfld.long 0x00 0. "WAIT_ERR0,Show the error state of waiting interrupt mode" "0: Ignored,1: Clear this bit"
repeat.end
repeat 16. (strings "96" "97" "98" "99" "100" "101" "102" "103" "104" "105" "106" "107" "108" "109" "110" "111" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x180)++0x03
line.long 0x00 "IMNTRSR$1,This register is functional safety use only"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Key Code"
eventfld.long 0x00 15. "CNT_ERR7,Show the error state of count up mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 14. "WAIT_ERR7,Show the error state of waiting interrupt mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 13. "CNT_ERR6,Show the error state of count up mode" "0: Ignored,1: Clear this bit"
newline
eventfld.long 0x00 12. "WAIT_ERR6,Show the error state of waiting interrupt mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 11. "CNT_ERR5,Show the error state of count up mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 10. "WAIT_ERR5,Show the error state of waiting interrupt mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 9. "CNT_ERR4,Show the error state of count up mode" "0: Ignored,1: Clear this bit"
newline
eventfld.long 0x00 8. "WAIT_ERR4,Show the error state of waiting interrupt mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 7. "CNT_ERR3,Show the error state of count up mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 6. "WAIT_ERR3,Show the error state of waiting interrupt mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 5. "CNT_ERR2,Show the error state of count up mode" "0: Ignored,1: Clear this bit"
newline
eventfld.long 0x00 4. "WAIT_ERR2,Show the error state of waiting interrupt mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 3. "CNT_ERR1,Show the error state of count up mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 2. "WAIT_ERR1,Show the error state of waiting interrupt mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 1. "CNT_ERR0,Show the error state of count up mode" "0: Ignored,1: Clear this bit"
newline
eventfld.long 0x00 0. "WAIT_ERR0,Show the error state of waiting interrupt mode" "0: Ignored,1: Clear this bit"
repeat.end
repeat 9. (strings "112" "113" "114" "115" "116" "117" "118" "119" "120" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 )
group.long ($2+0x1C0)++0x03
line.long 0x00 "IMNTRSR$1,This register is functional safety use only"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Key Code"
eventfld.long 0x00 15. "CNT_ERR7,Show the error state of count up mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 14. "WAIT_ERR7,Show the error state of waiting interrupt mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 13. "CNT_ERR6,Show the error state of count up mode" "0: Ignored,1: Clear this bit"
newline
eventfld.long 0x00 12. "WAIT_ERR6,Show the error state of waiting interrupt mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 11. "CNT_ERR5,Show the error state of count up mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 10. "WAIT_ERR5,Show the error state of waiting interrupt mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 9. "CNT_ERR4,Show the error state of count up mode" "0: Ignored,1: Clear this bit"
newline
eventfld.long 0x00 8. "WAIT_ERR4,Show the error state of waiting interrupt mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 7. "CNT_ERR3,Show the error state of count up mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 6. "WAIT_ERR3,Show the error state of waiting interrupt mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 5. "CNT_ERR2,Show the error state of count up mode" "0: Ignored,1: Clear this bit"
newline
eventfld.long 0x00 4. "WAIT_ERR2,Show the error state of waiting interrupt mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 3. "CNT_ERR1,Show the error state of count up mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 2. "WAIT_ERR1,Show the error state of waiting interrupt mode" "0: Ignored,1: Clear this bit"
eventfld.long 0x00 1. "CNT_ERR0,Show the error state of count up mode" "0: Ignored,1: Clear this bit"
newline
eventfld.long 0x00 0. "WAIT_ERR0,Show the error state of waiting interrupt mode" "0: Ignored,1: Clear this bit"
repeat.end
tree.end
tree "INTC_INST_3"
base ad:0xFFEA6000
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x00)++0x03
line.long 0x00 "IMNTRRTR$1,This register is functional safety use only"
rbitfld.long 0x00 31. "IMNTR_EN15,Show the configuration of IMNTRCRxs IMNTR_EN bit" "0: IMNTRCRxs IMNTR_EN bit is 0,1: IMNTRCRxs IMNTR_EN bit is 1"
rbitfld.long 0x00 30. "WAIT_SET15,Show the configuration of IMNTRCRxs WAIT_SET bit" "0: IMNTRCRxs WAIT_SET bit is 0,1: IMNTRCRxs WAIT_SET bit is 1"
rbitfld.long 0x00 29. "IMNTR_EN14,Show the configuration of IMNTRCRxs IMNTR_EN bit" "0: IMNTRCRxs IMNTR_EN bit is 0,1: IMNTRCRxs IMNTR_EN bit is 1"
newline
rbitfld.long 0x00 28. "WAIT_SET14,Show the configuration of IMNTRCRxs WAIT_SET bit" "0: IMNTRCRxs WAIT_SET bit is 0,1: IMNTRCRxs WAIT_SET bit is 1"
rbitfld.long 0x00 27. "IMNTR_EN13,Show the configuration of IMNTRCRxs IMNTR_EN bit" "0: IMNTRCRxs IMNTR_EN bit is 0,1: IMNTRCRxs IMNTR_EN bit is 1"
rbitfld.long 0x00 26. "WAIT_SET13,Show the configuration of IMNTRCRxs WAIT_SET bit" "0: IMNTRCRxs WAIT_SET bit is 0,1: IMNTRCRxs WAIT_SET bit is 1"
newline
rbitfld.long 0x00 25. "IMNTR_EN12,Show the configuration of IMNTRCRxs IMNTR_EN bit" "0: IMNTRCRxs IMNTR_EN bit is 0,1: IMNTRCRxs IMNTR_EN bit is 1"
rbitfld.long 0x00 24. "WAIT_SET12,Show the configuration of IMNTRCRxs WAIT_SET bit" "0: IMNTRCRxs WAIT_SET bit is 0,1: IMNTRCRxs WAIT_SET bit is 1"
rbitfld.long 0x00 23. "IMNTR_EN11,Show the configuration of IMNTRCRxs IMNTR_EN bit" "0: IMNTRCRxs IMNTR_EN bit is 0,1: IMNTRCRxs IMNTR_EN bit is 1"
newline
rbitfld.long 0x00 22. "WAIT_SET11,Show the configuration of IMNTRCRxs WAIT_SET bit" "0: IMNTRCRxs WAIT_SET bit is 0,1: IMNTRCRxs WAIT_SET bit is 1"
rbitfld.long 0x00 21. "IMNTR_EN10,Show the configuration of IMNTRCRxs IMNTR_EN bit" "0: IMNTRCRxs IMNTR_EN bit is 0,1: IMNTRCRxs IMNTR_EN bit is 1"
rbitfld.long 0x00 20. "WAIT_SET10,Show the configuration of IMNTRCRxs WAIT_SET bit" "0: IMNTRCRxs WAIT_SET bit is 0,1: IMNTRCRxs WAIT_SET bit is 1"
newline
rbitfld.long 0x00 19. "IMNTR_EN9,Show the configuration of IMNTRCRxs IMNTR_EN bit" "0: IMNTRCRxs IMNTR_EN bit is 0,1: IMNTRCRxs IMNTR_EN bit is 1"
rbitfld.long 0x00 18. "WAIT_SET9,Show the configuration of IMNTRCRxs WAIT_SET bit" "0: IMNTRCRxs WAIT_SET bit is 0,1: IMNTRCRxs WAIT_SET bit is 1"
rbitfld.long 0x00 17. "IMNTR_EN8,Show the configuration of IMNTRCRxs IMNTR_EN bit" "0: IMNTRCRxs IMNTR_EN bit is 0,1: IMNTRCRxs IMNTR_EN bit is 1"
newline
rbitfld.long 0x00 16. "WAIT_SET8,Show the configuration of IMNTRCRxs WAIT_SET bit" "0: IMNTRCRxs WAIT_SET bit is 0,1: IMNTRCRxs WAIT_SET bit is 1"
rbitfld.long 0x00 15. "IMNTR_EN7,Show the configuration of IMNTRCRxs IMNTR_EN bit" "0: IMNTRCRxs IMNTR_EN bit is 0,1: IMNTRCRxs IMNTR_EN bit is 1"
rbitfld.long 0x00 14. "WAIT_SET7,Show the configuration of IMNTRCRxs WAIT_SET bit" "0: IMNTRCRxs WAIT_SET bit is 0,1: IMNTRCRxs WAIT_SET bit is 1"
newline
rbitfld.long 0x00 13. "IMNTR_EN6,Show the configuration of IMNTRCRxs IMNTR_EN bit" "0: IMNTRCRxs IMNTR_EN bit is 0,1: IMNTRCRxs IMNTR_EN bit is 1"
rbitfld.long 0x00 12. "WAIT_SET6,Show the configuration of IMNTRCRxs WAIT_SET bit" "0: IMNTRCRxs WAIT_SET bit is 0,1: IMNTRCRxs WAIT_SET bit is 1"
rbitfld.long 0x00 11. "IMNTR_EN5,Show the configuration of IMNTRCRxs IMNTR_EN bit" "0: IMNTRCRxs IMNTR_EN bit is 0,1: IMNTRCRxs IMNTR_EN bit is 1"
newline
rbitfld.long 0x00 10. "WAIT_SET5,Show the configuration of IMNTRCRxs WAIT_SET bit" "0: IMNTRCRxs WAIT_SET bit is 0,1: IMNTRCRxs WAIT_SET bit is 1"
rbitfld.long 0x00 9. "IMNTR_EN4,Show the configuration of IMNTRCRxs IMNTR_EN bit" "0: IMNTRCRxs IMNTR_EN bit is 0,1: IMNTRCRxs IMNTR_EN bit is 1"
rbitfld.long 0x00 8. "WAIT_SET4,Show the configuration of IMNTRCRxs WAIT_SET bit" "0: IMNTRCRxs WAIT_SET bit is 0,1: IMNTRCRxs WAIT_SET bit is 1"
newline
rbitfld.long 0x00 7. "IMNTR_EN3,Show the configuration of IMNTRCRxs IMNTR_EN bit" "0: IMNTRCRxs IMNTR_EN bit is 0,1: IMNTRCRxs IMNTR_EN bit is 1"
rbitfld.long 0x00 6. "WAIT_SET3,Show the configuration of IMNTRCRxs WAIT_SET bit" "0: IMNTRCRxs WAIT_SET bit is 0,1: IMNTRCRxs WAIT_SET bit is 1"
rbitfld.long 0x00 5. "IMNTR_EN2,Show the configuration of IMNTRCRxs IMNTR_EN bit" "0: IMNTRCRxs IMNTR_EN bit is 0,1: IMNTRCRxs IMNTR_EN bit is 1"
newline
rbitfld.long 0x00 4. "WAIT_SET2,Show the configuration of IMNTRCRxs WAIT_SET bit" "0: IMNTRCRxs WAIT_SET bit is 0,1: IMNTRCRxs WAIT_SET bit is 1"
rbitfld.long 0x00 3. "IMNTR_EN1,Show the configuration of IMNTRCRxs IMNTR_EN bit" "0: IMNTRCRxs IMNTR_EN bit is 0,1: IMNTRCRxs IMNTR_EN bit is 1"
rbitfld.long 0x00 2. "WAIT_SET1,Show the configuration of IMNTRCRxs WAIT_SET bit" "0: IMNTRCRxs WAIT_SET bit is 0,1: IMNTRCRxs WAIT_SET bit is 1"
newline
rbitfld.long 0x00 1. "IMNTR_EN0,Show the configuration of IMNTRCRxs IMNTR_EN bit" "0: IMNTRCRxs IMNTR_EN bit is 0,1: IMNTRCRxs IMNTR_EN bit is 1"
rbitfld.long 0x00 0. "WAIT_SET0,Show the configuration of IMNTRCRxs WAIT_SET bit" "0: IMNTRCRxs WAIT_SET bit is 0,1: IMNTRCRxs WAIT_SET bit is 1"
repeat.end
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x40)++0x03
line.long 0x00 "IMNTRRTR$1,This register is functional safety use only"
rbitfld.long 0x00 31. "IMNTR_EN15,Show the configuration of IMNTRCRxs IMNTR_EN bit" "0: IMNTRCRxs IMNTR_EN bit is 0,1: IMNTRCRxs IMNTR_EN bit is 1"
rbitfld.long 0x00 30. "WAIT_SET15,Show the configuration of IMNTRCRxs WAIT_SET bit" "0: IMNTRCRxs WAIT_SET bit is 0,1: IMNTRCRxs WAIT_SET bit is 1"
rbitfld.long 0x00 29. "IMNTR_EN14,Show the configuration of IMNTRCRxs IMNTR_EN bit" "0: IMNTRCRxs IMNTR_EN bit is 0,1: IMNTRCRxs IMNTR_EN bit is 1"
newline
rbitfld.long 0x00 28. "WAIT_SET14,Show the configuration of IMNTRCRxs WAIT_SET bit" "0: IMNTRCRxs WAIT_SET bit is 0,1: IMNTRCRxs WAIT_SET bit is 1"
rbitfld.long 0x00 27. "IMNTR_EN13,Show the configuration of IMNTRCRxs IMNTR_EN bit" "0: IMNTRCRxs IMNTR_EN bit is 0,1: IMNTRCRxs IMNTR_EN bit is 1"
rbitfld.long 0x00 26. "WAIT_SET13,Show the configuration of IMNTRCRxs WAIT_SET bit" "0: IMNTRCRxs WAIT_SET bit is 0,1: IMNTRCRxs WAIT_SET bit is 1"
newline
rbitfld.long 0x00 25. "IMNTR_EN12,Show the configuration of IMNTRCRxs IMNTR_EN bit" "0: IMNTRCRxs IMNTR_EN bit is 0,1: IMNTRCRxs IMNTR_EN bit is 1"
rbitfld.long 0x00 24. "WAIT_SET12,Show the configuration of IMNTRCRxs WAIT_SET bit" "0: IMNTRCRxs WAIT_SET bit is 0,1: IMNTRCRxs WAIT_SET bit is 1"
rbitfld.long 0x00 23. "IMNTR_EN11,Show the configuration of IMNTRCRxs IMNTR_EN bit" "0: IMNTRCRxs IMNTR_EN bit is 0,1: IMNTRCRxs IMNTR_EN bit is 1"
newline
rbitfld.long 0x00 22. "WAIT_SET11,Show the configuration of IMNTRCRxs WAIT_SET bit" "0: IMNTRCRxs WAIT_SET bit is 0,1: IMNTRCRxs WAIT_SET bit is 1"
rbitfld.long 0x00 21. "IMNTR_EN10,Show the configuration of IMNTRCRxs IMNTR_EN bit" "0: IMNTRCRxs IMNTR_EN bit is 0,1: IMNTRCRxs IMNTR_EN bit is 1"
rbitfld.long 0x00 20. "WAIT_SET10,Show the configuration of IMNTRCRxs WAIT_SET bit" "0: IMNTRCRxs WAIT_SET bit is 0,1: IMNTRCRxs WAIT_SET bit is 1"
newline
rbitfld.long 0x00 19. "IMNTR_EN9,Show the configuration of IMNTRCRxs IMNTR_EN bit" "0: IMNTRCRxs IMNTR_EN bit is 0,1: IMNTRCRxs IMNTR_EN bit is 1"
rbitfld.long 0x00 18. "WAIT_SET9,Show the configuration of IMNTRCRxs WAIT_SET bit" "0: IMNTRCRxs WAIT_SET bit is 0,1: IMNTRCRxs WAIT_SET bit is 1"
rbitfld.long 0x00 17. "IMNTR_EN8,Show the configuration of IMNTRCRxs IMNTR_EN bit" "0: IMNTRCRxs IMNTR_EN bit is 0,1: IMNTRCRxs IMNTR_EN bit is 1"
newline
rbitfld.long 0x00 16. "WAIT_SET8,Show the configuration of IMNTRCRxs WAIT_SET bit" "0: IMNTRCRxs WAIT_SET bit is 0,1: IMNTRCRxs WAIT_SET bit is 1"
rbitfld.long 0x00 15. "IMNTR_EN7,Show the configuration of IMNTRCRxs IMNTR_EN bit" "0: IMNTRCRxs IMNTR_EN bit is 0,1: IMNTRCRxs IMNTR_EN bit is 1"
rbitfld.long 0x00 14. "WAIT_SET7,Show the configuration of IMNTRCRxs WAIT_SET bit" "0: IMNTRCRxs WAIT_SET bit is 0,1: IMNTRCRxs WAIT_SET bit is 1"
newline
rbitfld.long 0x00 13. "IMNTR_EN6,Show the configuration of IMNTRCRxs IMNTR_EN bit" "0: IMNTRCRxs IMNTR_EN bit is 0,1: IMNTRCRxs IMNTR_EN bit is 1"
rbitfld.long 0x00 12. "WAIT_SET6,Show the configuration of IMNTRCRxs WAIT_SET bit" "0: IMNTRCRxs WAIT_SET bit is 0,1: IMNTRCRxs WAIT_SET bit is 1"
rbitfld.long 0x00 11. "IMNTR_EN5,Show the configuration of IMNTRCRxs IMNTR_EN bit" "0: IMNTRCRxs IMNTR_EN bit is 0,1: IMNTRCRxs IMNTR_EN bit is 1"
newline
rbitfld.long 0x00 10. "WAIT_SET5,Show the configuration of IMNTRCRxs WAIT_SET bit" "0: IMNTRCRxs WAIT_SET bit is 0,1: IMNTRCRxs WAIT_SET bit is 1"
rbitfld.long 0x00 9. "IMNTR_EN4,Show the configuration of IMNTRCRxs IMNTR_EN bit" "0: IMNTRCRxs IMNTR_EN bit is 0,1: IMNTRCRxs IMNTR_EN bit is 1"
rbitfld.long 0x00 8. "WAIT_SET4,Show the configuration of IMNTRCRxs WAIT_SET bit" "0: IMNTRCRxs WAIT_SET bit is 0,1: IMNTRCRxs WAIT_SET bit is 1"
newline
rbitfld.long 0x00 7. "IMNTR_EN3,Show the configuration of IMNTRCRxs IMNTR_EN bit" "0: IMNTRCRxs IMNTR_EN bit is 0,1: IMNTRCRxs IMNTR_EN bit is 1"
rbitfld.long 0x00 6. "WAIT_SET3,Show the configuration of IMNTRCRxs WAIT_SET bit" "0: IMNTRCRxs WAIT_SET bit is 0,1: IMNTRCRxs WAIT_SET bit is 1"
rbitfld.long 0x00 5. "IMNTR_EN2,Show the configuration of IMNTRCRxs IMNTR_EN bit" "0: IMNTRCRxs IMNTR_EN bit is 0,1: IMNTRCRxs IMNTR_EN bit is 1"
newline
rbitfld.long 0x00 4. "WAIT_SET2,Show the configuration of IMNTRCRxs WAIT_SET bit" "0: IMNTRCRxs WAIT_SET bit is 0,1: IMNTRCRxs WAIT_SET bit is 1"
rbitfld.long 0x00 3. "IMNTR_EN1,Show the configuration of IMNTRCRxs IMNTR_EN bit" "0: IMNTRCRxs IMNTR_EN bit is 0,1: IMNTRCRxs IMNTR_EN bit is 1"
rbitfld.long 0x00 2. "WAIT_SET1,Show the configuration of IMNTRCRxs WAIT_SET bit" "0: IMNTRCRxs WAIT_SET bit is 0,1: IMNTRCRxs WAIT_SET bit is 1"
newline
rbitfld.long 0x00 1. "IMNTR_EN0,Show the configuration of IMNTRCRxs IMNTR_EN bit" "0: IMNTRCRxs IMNTR_EN bit is 0,1: IMNTRCRxs IMNTR_EN bit is 1"
rbitfld.long 0x00 0. "WAIT_SET0,Show the configuration of IMNTRCRxs WAIT_SET bit" "0: IMNTRCRxs WAIT_SET bit is 0,1: IMNTRCRxs WAIT_SET bit is 1"
repeat.end
repeat 16. (strings "32" "33" "34" "35" "36" "37" "38" "39" "40" "41" "42" "43" "44" "45" "46" "47" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x80)++0x03
line.long 0x00 "IMNTRRTR$1,This register is functional safety use only"
rbitfld.long 0x00 31. "IMNTR_EN15,Show the configuration of IMNTRCRxs IMNTR_EN bit" "0: IMNTRCRxs IMNTR_EN bit is 0,1: IMNTRCRxs IMNTR_EN bit is 1"
rbitfld.long 0x00 30. "WAIT_SET15,Show the configuration of IMNTRCRxs WAIT_SET bit" "0: IMNTRCRxs WAIT_SET bit is 0,1: IMNTRCRxs WAIT_SET bit is 1"
rbitfld.long 0x00 29. "IMNTR_EN14,Show the configuration of IMNTRCRxs IMNTR_EN bit" "0: IMNTRCRxs IMNTR_EN bit is 0,1: IMNTRCRxs IMNTR_EN bit is 1"
newline
rbitfld.long 0x00 28. "WAIT_SET14,Show the configuration of IMNTRCRxs WAIT_SET bit" "0: IMNTRCRxs WAIT_SET bit is 0,1: IMNTRCRxs WAIT_SET bit is 1"
rbitfld.long 0x00 27. "IMNTR_EN13,Show the configuration of IMNTRCRxs IMNTR_EN bit" "0: IMNTRCRxs IMNTR_EN bit is 0,1: IMNTRCRxs IMNTR_EN bit is 1"
rbitfld.long 0x00 26. "WAIT_SET13,Show the configuration of IMNTRCRxs WAIT_SET bit" "0: IMNTRCRxs WAIT_SET bit is 0,1: IMNTRCRxs WAIT_SET bit is 1"
newline
rbitfld.long 0x00 25. "IMNTR_EN12,Show the configuration of IMNTRCRxs IMNTR_EN bit" "0: IMNTRCRxs IMNTR_EN bit is 0,1: IMNTRCRxs IMNTR_EN bit is 1"
rbitfld.long 0x00 24. "WAIT_SET12,Show the configuration of IMNTRCRxs WAIT_SET bit" "0: IMNTRCRxs WAIT_SET bit is 0,1: IMNTRCRxs WAIT_SET bit is 1"
rbitfld.long 0x00 23. "IMNTR_EN11,Show the configuration of IMNTRCRxs IMNTR_EN bit" "0: IMNTRCRxs IMNTR_EN bit is 0,1: IMNTRCRxs IMNTR_EN bit is 1"
newline
rbitfld.long 0x00 22. "WAIT_SET11,Show the configuration of IMNTRCRxs WAIT_SET bit" "0: IMNTRCRxs WAIT_SET bit is 0,1: IMNTRCRxs WAIT_SET bit is 1"
rbitfld.long 0x00 21. "IMNTR_EN10,Show the configuration of IMNTRCRxs IMNTR_EN bit" "0: IMNTRCRxs IMNTR_EN bit is 0,1: IMNTRCRxs IMNTR_EN bit is 1"
rbitfld.long 0x00 20. "WAIT_SET10,Show the configuration of IMNTRCRxs WAIT_SET bit" "0: IMNTRCRxs WAIT_SET bit is 0,1: IMNTRCRxs WAIT_SET bit is 1"
newline
rbitfld.long 0x00 19. "IMNTR_EN9,Show the configuration of IMNTRCRxs IMNTR_EN bit" "0: IMNTRCRxs IMNTR_EN bit is 0,1: IMNTRCRxs IMNTR_EN bit is 1"
rbitfld.long 0x00 18. "WAIT_SET9,Show the configuration of IMNTRCRxs WAIT_SET bit" "0: IMNTRCRxs WAIT_SET bit is 0,1: IMNTRCRxs WAIT_SET bit is 1"
rbitfld.long 0x00 17. "IMNTR_EN8,Show the configuration of IMNTRCRxs IMNTR_EN bit" "0: IMNTRCRxs IMNTR_EN bit is 0,1: IMNTRCRxs IMNTR_EN bit is 1"
newline
rbitfld.long 0x00 16. "WAIT_SET8,Show the configuration of IMNTRCRxs WAIT_SET bit" "0: IMNTRCRxs WAIT_SET bit is 0,1: IMNTRCRxs WAIT_SET bit is 1"
rbitfld.long 0x00 15. "IMNTR_EN7,Show the configuration of IMNTRCRxs IMNTR_EN bit" "0: IMNTRCRxs IMNTR_EN bit is 0,1: IMNTRCRxs IMNTR_EN bit is 1"
rbitfld.long 0x00 14. "WAIT_SET7,Show the configuration of IMNTRCRxs WAIT_SET bit" "0: IMNTRCRxs WAIT_SET bit is 0,1: IMNTRCRxs WAIT_SET bit is 1"
newline
rbitfld.long 0x00 13. "IMNTR_EN6,Show the configuration of IMNTRCRxs IMNTR_EN bit" "0: IMNTRCRxs IMNTR_EN bit is 0,1: IMNTRCRxs IMNTR_EN bit is 1"
rbitfld.long 0x00 12. "WAIT_SET6,Show the configuration of IMNTRCRxs WAIT_SET bit" "0: IMNTRCRxs WAIT_SET bit is 0,1: IMNTRCRxs WAIT_SET bit is 1"
rbitfld.long 0x00 11. "IMNTR_EN5,Show the configuration of IMNTRCRxs IMNTR_EN bit" "0: IMNTRCRxs IMNTR_EN bit is 0,1: IMNTRCRxs IMNTR_EN bit is 1"
newline
rbitfld.long 0x00 10. "WAIT_SET5,Show the configuration of IMNTRCRxs WAIT_SET bit" "0: IMNTRCRxs WAIT_SET bit is 0,1: IMNTRCRxs WAIT_SET bit is 1"
rbitfld.long 0x00 9. "IMNTR_EN4,Show the configuration of IMNTRCRxs IMNTR_EN bit" "0: IMNTRCRxs IMNTR_EN bit is 0,1: IMNTRCRxs IMNTR_EN bit is 1"
rbitfld.long 0x00 8. "WAIT_SET4,Show the configuration of IMNTRCRxs WAIT_SET bit" "0: IMNTRCRxs WAIT_SET bit is 0,1: IMNTRCRxs WAIT_SET bit is 1"
newline
rbitfld.long 0x00 7. "IMNTR_EN3,Show the configuration of IMNTRCRxs IMNTR_EN bit" "0: IMNTRCRxs IMNTR_EN bit is 0,1: IMNTRCRxs IMNTR_EN bit is 1"
rbitfld.long 0x00 6. "WAIT_SET3,Show the configuration of IMNTRCRxs WAIT_SET bit" "0: IMNTRCRxs WAIT_SET bit is 0,1: IMNTRCRxs WAIT_SET bit is 1"
rbitfld.long 0x00 5. "IMNTR_EN2,Show the configuration of IMNTRCRxs IMNTR_EN bit" "0: IMNTRCRxs IMNTR_EN bit is 0,1: IMNTRCRxs IMNTR_EN bit is 1"
newline
rbitfld.long 0x00 4. "WAIT_SET2,Show the configuration of IMNTRCRxs WAIT_SET bit" "0: IMNTRCRxs WAIT_SET bit is 0,1: IMNTRCRxs WAIT_SET bit is 1"
rbitfld.long 0x00 3. "IMNTR_EN1,Show the configuration of IMNTRCRxs IMNTR_EN bit" "0: IMNTRCRxs IMNTR_EN bit is 0,1: IMNTRCRxs IMNTR_EN bit is 1"
rbitfld.long 0x00 2. "WAIT_SET1,Show the configuration of IMNTRCRxs WAIT_SET bit" "0: IMNTRCRxs WAIT_SET bit is 0,1: IMNTRCRxs WAIT_SET bit is 1"
newline
rbitfld.long 0x00 1. "IMNTR_EN0,Show the configuration of IMNTRCRxs IMNTR_EN bit" "0: IMNTRCRxs IMNTR_EN bit is 0,1: IMNTRCRxs IMNTR_EN bit is 1"
rbitfld.long 0x00 0. "WAIT_SET0,Show the configuration of IMNTRCRxs WAIT_SET bit" "0: IMNTRCRxs WAIT_SET bit is 0,1: IMNTRCRxs WAIT_SET bit is 1"
repeat.end
repeat 13. (strings "48" "49" "50" "51" "52" "53" "54" "55" "56" "57" "58" "59" "60" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 )
group.long ($2+0xC0)++0x03
line.long 0x00 "IMNTRRTR$1,This register is functional safety use only"
rbitfld.long 0x00 31. "IMNTR_EN15,Show the configuration of IMNTRCRxs IMNTR_EN bit" "0: IMNTRCRxs IMNTR_EN bit is 0,1: IMNTRCRxs IMNTR_EN bit is 1"
rbitfld.long 0x00 30. "WAIT_SET15,Show the configuration of IMNTRCRxs WAIT_SET bit" "0: IMNTRCRxs WAIT_SET bit is 0,1: IMNTRCRxs WAIT_SET bit is 1"
rbitfld.long 0x00 29. "IMNTR_EN14,Show the configuration of IMNTRCRxs IMNTR_EN bit" "0: IMNTRCRxs IMNTR_EN bit is 0,1: IMNTRCRxs IMNTR_EN bit is 1"
newline
rbitfld.long 0x00 28. "WAIT_SET14,Show the configuration of IMNTRCRxs WAIT_SET bit" "0: IMNTRCRxs WAIT_SET bit is 0,1: IMNTRCRxs WAIT_SET bit is 1"
rbitfld.long 0x00 27. "IMNTR_EN13,Show the configuration of IMNTRCRxs IMNTR_EN bit" "0: IMNTRCRxs IMNTR_EN bit is 0,1: IMNTRCRxs IMNTR_EN bit is 1"
rbitfld.long 0x00 26. "WAIT_SET13,Show the configuration of IMNTRCRxs WAIT_SET bit" "0: IMNTRCRxs WAIT_SET bit is 0,1: IMNTRCRxs WAIT_SET bit is 1"
newline
rbitfld.long 0x00 25. "IMNTR_EN12,Show the configuration of IMNTRCRxs IMNTR_EN bit" "0: IMNTRCRxs IMNTR_EN bit is 0,1: IMNTRCRxs IMNTR_EN bit is 1"
rbitfld.long 0x00 24. "WAIT_SET12,Show the configuration of IMNTRCRxs WAIT_SET bit" "0: IMNTRCRxs WAIT_SET bit is 0,1: IMNTRCRxs WAIT_SET bit is 1"
rbitfld.long 0x00 23. "IMNTR_EN11,Show the configuration of IMNTRCRxs IMNTR_EN bit" "0: IMNTRCRxs IMNTR_EN bit is 0,1: IMNTRCRxs IMNTR_EN bit is 1"
newline
rbitfld.long 0x00 22. "WAIT_SET11,Show the configuration of IMNTRCRxs WAIT_SET bit" "0: IMNTRCRxs WAIT_SET bit is 0,1: IMNTRCRxs WAIT_SET bit is 1"
rbitfld.long 0x00 21. "IMNTR_EN10,Show the configuration of IMNTRCRxs IMNTR_EN bit" "0: IMNTRCRxs IMNTR_EN bit is 0,1: IMNTRCRxs IMNTR_EN bit is 1"
rbitfld.long 0x00 20. "WAIT_SET10,Show the configuration of IMNTRCRxs WAIT_SET bit" "0: IMNTRCRxs WAIT_SET bit is 0,1: IMNTRCRxs WAIT_SET bit is 1"
newline
rbitfld.long 0x00 19. "IMNTR_EN9,Show the configuration of IMNTRCRxs IMNTR_EN bit" "0: IMNTRCRxs IMNTR_EN bit is 0,1: IMNTRCRxs IMNTR_EN bit is 1"
rbitfld.long 0x00 18. "WAIT_SET9,Show the configuration of IMNTRCRxs WAIT_SET bit" "0: IMNTRCRxs WAIT_SET bit is 0,1: IMNTRCRxs WAIT_SET bit is 1"
rbitfld.long 0x00 17. "IMNTR_EN8,Show the configuration of IMNTRCRxs IMNTR_EN bit" "0: IMNTRCRxs IMNTR_EN bit is 0,1: IMNTRCRxs IMNTR_EN bit is 1"
newline
rbitfld.long 0x00 16. "WAIT_SET8,Show the configuration of IMNTRCRxs WAIT_SET bit" "0: IMNTRCRxs WAIT_SET bit is 0,1: IMNTRCRxs WAIT_SET bit is 1"
rbitfld.long 0x00 15. "IMNTR_EN7,Show the configuration of IMNTRCRxs IMNTR_EN bit" "0: IMNTRCRxs IMNTR_EN bit is 0,1: IMNTRCRxs IMNTR_EN bit is 1"
rbitfld.long 0x00 14. "WAIT_SET7,Show the configuration of IMNTRCRxs WAIT_SET bit" "0: IMNTRCRxs WAIT_SET bit is 0,1: IMNTRCRxs WAIT_SET bit is 1"
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rbitfld.long 0x00 13. "IMNTR_EN6,Show the configuration of IMNTRCRxs IMNTR_EN bit" "0: IMNTRCRxs IMNTR_EN bit is 0,1: IMNTRCRxs IMNTR_EN bit is 1"
rbitfld.long 0x00 12. "WAIT_SET6,Show the configuration of IMNTRCRxs WAIT_SET bit" "0: IMNTRCRxs WAIT_SET bit is 0,1: IMNTRCRxs WAIT_SET bit is 1"
rbitfld.long 0x00 11. "IMNTR_EN5,Show the configuration of IMNTRCRxs IMNTR_EN bit" "0: IMNTRCRxs IMNTR_EN bit is 0,1: IMNTRCRxs IMNTR_EN bit is 1"
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rbitfld.long 0x00 10. "WAIT_SET5,Show the configuration of IMNTRCRxs WAIT_SET bit" "0: IMNTRCRxs WAIT_SET bit is 0,1: IMNTRCRxs WAIT_SET bit is 1"
rbitfld.long 0x00 9. "IMNTR_EN4,Show the configuration of IMNTRCRxs IMNTR_EN bit" "0: IMNTRCRxs IMNTR_EN bit is 0,1: IMNTRCRxs IMNTR_EN bit is 1"
rbitfld.long 0x00 8. "WAIT_SET4,Show the configuration of IMNTRCRxs WAIT_SET bit" "0: IMNTRCRxs WAIT_SET bit is 0,1: IMNTRCRxs WAIT_SET bit is 1"
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rbitfld.long 0x00 7. "IMNTR_EN3,Show the configuration of IMNTRCRxs IMNTR_EN bit" "0: IMNTRCRxs IMNTR_EN bit is 0,1: IMNTRCRxs IMNTR_EN bit is 1"
rbitfld.long 0x00 6. "WAIT_SET3,Show the configuration of IMNTRCRxs WAIT_SET bit" "0: IMNTRCRxs WAIT_SET bit is 0,1: IMNTRCRxs WAIT_SET bit is 1"
rbitfld.long 0x00 5. "IMNTR_EN2,Show the configuration of IMNTRCRxs IMNTR_EN bit" "0: IMNTRCRxs IMNTR_EN bit is 0,1: IMNTRCRxs IMNTR_EN bit is 1"
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rbitfld.long 0x00 4. "WAIT_SET2,Show the configuration of IMNTRCRxs WAIT_SET bit" "0: IMNTRCRxs WAIT_SET bit is 0,1: IMNTRCRxs WAIT_SET bit is 1"
rbitfld.long 0x00 3. "IMNTR_EN1,Show the configuration of IMNTRCRxs IMNTR_EN bit" "0: IMNTRCRxs IMNTR_EN bit is 0,1: IMNTRCRxs IMNTR_EN bit is 1"
rbitfld.long 0x00 2. "WAIT_SET1,Show the configuration of IMNTRCRxs WAIT_SET bit" "0: IMNTRCRxs WAIT_SET bit is 0,1: IMNTRCRxs WAIT_SET bit is 1"
newline
rbitfld.long 0x00 1. "IMNTR_EN0,Show the configuration of IMNTRCRxs IMNTR_EN bit" "0: IMNTRCRxs IMNTR_EN bit is 0,1: IMNTRCRxs IMNTR_EN bit is 1"
rbitfld.long 0x00 0. "WAIT_SET0,Show the configuration of IMNTRCRxs WAIT_SET bit" "0: IMNTRCRxs WAIT_SET bit is 0,1: IMNTRCRxs WAIT_SET bit is 1"
repeat.end
tree.end
tree "INTC_INST_4"
base ad:0xE61C0000
group.long 0x00++0x03
line.long 0x00 "INTREQ_STS0,This register shows interrupt request status"
hexmask.long 0x00 6.--31. 1. "Reserved_6,Reserved These bits are always read as 0"
rbitfld.long 0x00 0.--5. "INTREQ,Interrupt Status" "0: Interrupt not generation,1: Interrupt generation,?..."
group.long 0x04++0x03
line.long 0x00 "INTEN_STS0,This register shows interrupt enable status and clear interrupt enable"
hexmask.long 0x00 6.--31. 1. "Reserved_6,Reserved These bits are always read as 0"
eventfld.long 0x00 0.--5. "INTEN,Interrupt Enable" "0: No functional effect,1: Interrupt enable clear,?..."
group.long 0x08++0x03
line.long 0x00 "INTEN_SET0,This register set interrupt enable"
hexmask.long 0x00 6.--31. 1. "Reserved_6,Reserved These bits are always read as 0"
bitfld.long 0x00 0.--5. "INTENS,Interrupt Enable Set" "0: No functional effect,1: Interrupt enable set,?..."
group.long 0x100++0x03
line.long 0x00 "DETECT_STATUS,This register shows IRQn event detection status and provides the function to clear edge-triggered event"
hexmask.long 0x00 6.--31. 1. "Reserved_6,Reserved These bits are always read as 0"
eventfld.long 0x00 0.--5. "IRQnDET,IRQn Event Detection Status Edge-triggered mode: Read" "0: No functional effect,1: No functional effect,?..."
group.long 0x104++0x03
line.long 0x00 "MONITOR,This register provide external signal monitor"
hexmask.long 0x00 6.--31. 1. "Reserved_6,"
rbitfld.long 0x00 0.--5. "IRQnMON,IRQn External Signal Level Monitor This function show input value when signal is enabled by corresponding configuration register SS bits" "0: IRQn is low level,1: IRQn is high level,?..."
group.long 0x108++0x03
line.long 0x00 "HLVL_STS,This register provides interrupt detail detect status"
hexmask.long 0x00 6.--31. 1. "Reserved_6,Reserved These bits are always read as 0"
rbitfld.long 0x00 0.--5. "IRQnHSTS,IRQn High Level Interrupt Status" "0: IRQn high level interrupt request not occurred,1: IRQn high level interrupt request occurred,?..."
group.long 0x10C++0x03
line.long 0x00 "LLVL_STS,This register provides interrupt detail detect status"
hexmask.long 0x00 6.--31. 1. "Reserved_6,Reserved These bits are always read as 0"
rbitfld.long 0x00 0.--5. "IRQnLSTS,IRQn Low Level Interrupt Status" "0: IRQn low level interrupt request not occurred,1: IRQn low level interrupt request occurred,?..."
group.long 0x110++0x03
line.long 0x00 "S_R_EDGE_STS,This register provides interrupt detail detect status"
hexmask.long 0x00 6.--31. 1. "Reserved_6,"
rbitfld.long 0x00 0.--5. "IRQnSRSTS,IRQn Synchronous Rise Edge Interrupt Status" "0: IRQn rise edge interrupt request not occurred,1: IRQn rise edge interrupt request occurred,?..."
group.long 0x114++0x03
line.long 0x00 "S_F_EDGE_STS,This register provides interrupt detail detect status"
hexmask.long 0x00 6.--31. 1. "Reserved_6,Reserved These bits are always read as 0"
rbitfld.long 0x00 0.--5. "IRQnSFSTS,IRQn Synchronous Fall Edge Interrupt Status" "0: IRQn fall edge interrupt request not occurred,1: IRQn fall edge interrupt request occurred,?..."
group.long 0x118++0x03
line.long 0x00 "A_R_EDGE_STS,This register provides interrupt detail detect status"
hexmask.long 0x00 6.--31. 1. "Reserved_6,Reserved These bits are always read as 0"
rbitfld.long 0x00 0.--5. "IRQnARSTS,IRQn Asynchronous Rise Edge Interrupt Status" "0: IRQn rise edge interrupt request not occurred,1: IRQn rise edge interrupt request occurred,?..."
group.long 0x11C++0x03
line.long 0x00 "A_F_EDGE_STS,This register provides interrupt detail detect status"
hexmask.long 0x00 6.--31. 1. "Reserved_6,Reserved These bits are always read as 0"
rbitfld.long 0x00 0.--5. "IRQnAFSTS,IRQn Asynchronous Fall Edge Interrupt Status" "0: IRQn fall edge interrupt request not occurred,1: IRQn fall edge interrupt request occurred,?..."
group.long 0x120++0x03
line.long 0x00 "CHTEN_STS,This register shows chattering reduction enable status"
hexmask.long 0x00 6.--31. 1. "Reserved_6,Reserved These bits are always read as 0"
rbitfld.long 0x00 0.--5. "CHTEN,Chattering Reduction Enable Status" "0: Chattering reduction disabled,1: Chattering reduction enabled,?..."
repeat 6. (strings "0" "1" "2" "3" "4" "5" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 )
group.long ($2+0x180)++0x03
line.long 0x00 "CONFIG_$1,This register provides detection mode and chattering reduction setting"
bitfld.long 0x00 31. "CHTEN,Chattering Reduction Enable" "0: Chattering reduction disabled,1: Chattering reduction enabled"
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 22.--23. "STS1,IRQn Scan Timing These bits provide chattering reduction timing" "0: 1 ms,1: 2 ms,2: 4 ms,3: 8 ms This"
bitfld.long 0x00 16.--21. "STS2,IRQn Chattering Reduction Period The chattering reduction period is defined by STS1 x STS2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.long.word 0x00 6.--15. 1. "Reserved_6,Reserved These bits are always read as 0"
bitfld.long 0x00 0.--5. "SS,Sense Selection" "0: Disable event detection,1: Enable low level sensitive,2: Enable high level sensitive,?,4: Enable synchronous falling edge triggered,?,?,?,8: Enable synchronous rising edge triggered,?,?,?,12: Enable synchronous both edge triggered,?,?,?,16: Enable asynchronous falling edge triggered,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,32: Enable asynchronous rising edge triggered,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,48: Enable asynchronous both edge triggered Others,?..."
repeat.end
group.long 0x400++0x03
line.long 0x00 "NMIREQ_STS0,This register shows external NMI request status"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "C7STS,NMI Status for CPU7 interface" "0: not during NMI service,1: during NMI service"
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rbitfld.long 0x00 6. "C6STS,NMI Status for CPU6 interface" "0: not during NMI service,1: during NMI service"
rbitfld.long 0x00 5. "C5STS,NMI Status for CPU5 interface" "0: not during NMI service,1: during NMI service"
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rbitfld.long 0x00 4. "C4STS,NMI Status for CPU4 interface" "0: not during NMI service,1: during NMI service"
rbitfld.long 0x00 3. "C3STS,NMI Status for CPU3 interface" "0: not during NMI service,1: during NMI service"
newline
rbitfld.long 0x00 2. "C2STS,NMI Status for CPU2 interface" "0: not during NMI service,1: during NMI service"
rbitfld.long 0x00 1. "C1STS,NMI Status for CPU1 interface" "0: not during NMI service,1: during NMI service"
newline
rbitfld.long 0x00 0. "C0STS,NMI Status for CPU0 interface" "0: not during NMI service,1: during NMI service"
group.long 0x404++0x03
line.long 0x00 "NMIEN_STS0,This register shows NMI interrupt enable status and clears NMI interrupt enable"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
eventfld.long 0x00 7. "C7IEN,Interrupt Enable for CPU7 interface" "0: No functional effect,1: NMI interrupt enable clear"
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eventfld.long 0x00 6. "C6IEN,Interrupt Enable for CPU6 interface" "0: No functional effect,1: NMI interrupt enable clear"
eventfld.long 0x00 5. "C5IEN,Interrupt Enable for CPU5 interface" "0: No functional effect,1: NMI interrupt enable clear"
newline
eventfld.long 0x00 4. "C4IEN,Interrupt Enable for CPU4 interface" "0: No functional effect,1: NMI interrupt enable clear"
eventfld.long 0x00 3. "C3IEN,Interrupt Enable for CPU3 interface" "0: No functional effect,1: NMI interrupt enable clear"
newline
eventfld.long 0x00 2. "C2IEN,Interrupt Enable for CPU2 interface" "0: No functional effect,1: NMI interrupt enable clear"
eventfld.long 0x00 1. "C1IEN,Interrupt Enable for CPU1 interface" "0: No functional effect,1: NMI interrupt enable clear"
newline
eventfld.long 0x00 0. "C0IEN,Interrupt Enable for CPU0 interface" "0: No functional effect,1: NMI interrupt enable clear"
group.long 0x408++0x03
line.long 0x00 "NMIEN_SET0,This register enables the NMI interrupt to each CPU For the CPUn interface see section 15.4.1 INTC-AP Register Configuration and Function Description"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "C7SET,Interrupt Enable Set for CPU7 interface" "0: No functional effect,1: Interrupt enable set"
newline
bitfld.long 0x00 6. "C6SET,Interrupt Enable Set for CPU6 interface" "0: No functional effect,1: Interrupt enable set"
bitfld.long 0x00 5. "C5SET,Interrupt Enable Set for CPU5 interface" "0: No functional effect,1: Interrupt enable set"
newline
bitfld.long 0x00 4. "C4SET,Interrupt Enable Set for CPU4 interface" "0: No functional effect,1: Interrupt enable set"
bitfld.long 0x00 3. "C3SET,Interrupt Enable Set for CPU3 interface" "0: No functional effect,1: Interrupt enable set"
newline
bitfld.long 0x00 2. "C2SET,Interrupt Enable Set for CPU2 interface" "0: No functional effect,1: Interrupt enable set"
bitfld.long 0x00 1. "C1SET,Interrupt Enable Set for CPU1 interface" "0: No functional effect,1: Interrupt enable set"
newline
bitfld.long 0x00 0. "C0SET,Interrupt Enable Set for CPU0 interface" "0: No functional effect,1: Interrupt enable set"
group.long 0x500++0x03
line.long 0x00 "DETECT_STATUS_NMI,This register shows NMIn event detection status and provides the function to clear edge-triggered event"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
eventfld.long 0x00 7. "NMI7DET,NMI Event Detection Status for CPU7 interface Edge-triggered mode: Read" "0: No functional effect,1: No functional effect"
newline
eventfld.long 0x00 6. "NMI6DET,NMI Event Detection Status for CPU6 interface Edge-triggered mode: Read" "0: No functional effect,1: No functional effect"
eventfld.long 0x00 5. "NMI5DET,NMI Event Detection Status for CPU5 interface Edge-triggered mode: Read" "0: No functional effect,1: No functional effect"
newline
eventfld.long 0x00 4. "NMI4DET,NMI Event Detection Status for CPU4 interface Edge-triggered mode: Read" "0: No functional effect,1: No functional effect"
eventfld.long 0x00 3. "NMI3DET,NMI Event Detection Status for CPU3 interface Edge-triggered mode: Read" "0: No functional effect,1: No functional effect"
newline
eventfld.long 0x00 2. "NMI2DET,NMI Event Detection Status for CPU2 interface Edge-triggered mode: Read" "0: No functional effect,1: No functional effect"
eventfld.long 0x00 1. "NMI1DET,NMI Event Detection Status for CPU1 interface Edge-triggered mode: Read" "0: No functional effect,1: No functional effect"
newline
eventfld.long 0x00 0. "NMI0DET,NMI Event Detection Status for CPU0 interface Edge-triggered mode: Read" "0: No functional effect,1: No functional effect"
group.long 0x504++0x03
line.long 0x00 "MONITOR_NMI,This register provides external signal monitor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "NMI7MON,NMI External Signal Level Monitor for CPU7 interface This function show input value when signal is enabled by corresponding configuration register SS bits" "0: NMI is low level,1: NMI is high level"
newline
rbitfld.long 0x00 6. "NMI6MON,NMI External Signal Level Monitor for CPU6 interface This function show input value when signal is enabled by corresponding configuration register SS bits" "0: NMI is low level,1: NMI is high level"
rbitfld.long 0x00 5. "NMI5MON,NMI External Signal Level Monitor for CPU5 interface This function show input value when signal is enabled by corresponding configuration register SS bits" "0: NMI is low level,1: NMI is high level"
newline
rbitfld.long 0x00 4. "NMI4MON,NMI External Signal Level Monitor for CPU4 interface This function show input value when signal is enabled by corresponding configuration register SS bits" "0: NMI is low level,1: NMI is high level"
rbitfld.long 0x00 3. "NMI3MON,NMI External Signal Level Monitor for CPU3 interface This function show input value when signal is enabled by corresponding configuration register SS bits" "0: NMI is low level,1: NMI is high level"
newline
rbitfld.long 0x00 2. "NMI2MON,NMI External Signal Level Monitor for CPU2 interface This function show input value when signal is enabled by corresponding configuration register SS bits" "0: NMI is low level,1: NMI is high level"
rbitfld.long 0x00 1. "NMI1MON,NMI External Signal Level Monitor for CPU1 interface This function show input value when signal is enabled by corresponding configuration register SS bits" "0: NMI is low level,1: NMI is high level"
newline
rbitfld.long 0x00 0. "NMI0MON,NMI External Signal Level Monitor for CPU0 interface This function show input value when signal is enabled by corresponding configuration register SS bits" "0: NMI is low level,1: NMI is high level"
group.long 0x508++0x03
line.long 0x00 "HLVL_STS_NMI,This register provides interrupt detail detect status"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "NMI7HSTS,NMI High Level Interrupt Status for CPU7 interface" "0: NMI high level interrupt request not occurred,1: NMI high level interrupt request occurred"
newline
rbitfld.long 0x00 6. "NMI6HSTS,NMI High Level Interrupt Status for CPU6 interface" "0: NMI high level interrupt request not occurred,1: NMI high level interrupt request occurred"
rbitfld.long 0x00 5. "NMI5HSTS,NMI High Level Interrupt Status for CPU5 interface" "0: NMI high level interrupt request not occurred,1: NMI high level interrupt request occurred"
newline
rbitfld.long 0x00 4. "NMI4HSTS,NMI High Level Interrupt Status for CPU4 interface" "0: NMI high level interrupt request not occurred,1: NMI high level interrupt request occurred"
rbitfld.long 0x00 3. "NMI3HSTS,NMI High Level Interrupt Status for CPU3 interface" "0: NMI high level interrupt request not occurred,1: NMI high level interrupt request occurred"
newline
rbitfld.long 0x00 2. "NMI2HSTS,NMI High Level Interrupt Status for CPU2 interface" "0: NMI high level interrupt request not occurred,1: NMI high level interrupt request occurred"
rbitfld.long 0x00 1. "NMI1HSTS,NMI High Level Interrupt Status for CPU1 interface" "0: NMI high level interrupt request not occurred,1: NMI high level interrupt request occurred"
newline
rbitfld.long 0x00 0. "NMI0HSTS,NMI High Level Interrupt Status for CPU0 interface" "0: NMI high level interrupt request not occurred,1: NMI high level interrupt request occurred"
group.long 0x50C++0x03
line.long 0x00 "LLVL_STS_NMI,This register provides interrupt detail detect status"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "NMI7LSTS,NMI Low Level Interrupt Status for CPU7 interface" "0: NMI low level interrupt request not occurred,1: NMI low level interrupt request occurred"
newline
rbitfld.long 0x00 6. "NMI6LSTS,NMI Low Level Interrupt Status for CPU6 interface" "0: NMI low level interrupt request not occurred,1: NMI low level interrupt request occurred"
rbitfld.long 0x00 5. "NMI5LSTS,NMI Low Level Interrupt Status for CPU5 interface" "0: NMI low level interrupt request not occurred,1: NMI low level interrupt request occurred"
newline
rbitfld.long 0x00 4. "NMI4LSTS,NMI Low Level Interrupt Status for CPU4 interface" "0: NMI low level interrupt request not occurred,1: NMI low level interrupt request occurred"
rbitfld.long 0x00 3. "NMI3LSTS,NMI Low Level Interrupt Status for CPU3 interface" "0: NMI low level interrupt request not occurred,1: NMI low level interrupt request occurred"
newline
rbitfld.long 0x00 2. "NMI2LSTS,NMI Low Level Interrupt Status for CPU2 interface" "0: NMI low level interrupt request not occurred,1: NMI low level interrupt request occurred"
rbitfld.long 0x00 1. "NMI1LSTS,NMI Low Level Interrupt Status for CPU1 interface" "0: NMI low level interrupt request not occurred,1: NMI low level interrupt request occurred"
newline
rbitfld.long 0x00 0. "NMI0LSTS,NMI Low Level Interrupt Status for CPU0 interface" "0: NMI low level interrupt request not occurred,1: NMI low level interrupt request occurred"
group.long 0x510++0x03
line.long 0x00 "S_R_EDGE_STS_NMI,This register provides interrupt detail detect status"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "NMI7SRSTS,NMI Synchronous Rise Edge Interrupt Status for CPU7 interface" "0: NMI rise edge interrupt request not occurred,1: NMI rise edge interrupt request occurred"
newline
rbitfld.long 0x00 6. "NMI6SRSTS,NMI Synchronous Rise Edge Interrupt Status for CPU6 interface" "0: NMI rise edge interrupt request not occurred,1: NMI rise edge interrupt request occurred"
rbitfld.long 0x00 5. "NMI5SRSTS,NMI Synchronous Rise Edge Interrupt Status for CPU5 interface" "0: NMI rise edge interrupt request not occurred,1: NMI rise edge interrupt request occurred"
newline
rbitfld.long 0x00 4. "NMI4SRSTS,NMI Synchronous Rise Edge Interrupt Status for CPU4 interface" "0: NMI rise edge interrupt request not occurred,1: NMI rise edge interrupt request occurred"
rbitfld.long 0x00 3. "NMI3SRSTS,NMI Synchronous Rise Edge Interrupt Status for CPU3 interface" "0: NMI rise edge interrupt request not occurred,1: NMI rise edge interrupt request occurred"
newline
rbitfld.long 0x00 2. "NMI2SRSTS,NMI Synchronous Rise Edge Interrupt Status for CPU2 interface" "0: NMI rise edge interrupt request not occurred,1: NMI rise edge interrupt request occurred"
rbitfld.long 0x00 1. "NMI1SRSTS,NMI Synchronous Rise Edge Interrupt Status for CPU1 interface" "0: NMI rise edge interrupt request not occurred,1: NMI rise edge interrupt request occurred"
newline
rbitfld.long 0x00 0. "NMI0SRSTS,NMI Synchronous Rise Edge Interrupt Status for CPU0 interface" "0: NMI rise edge interrupt request not occurred,1: NMI rise edge interrupt request occurred"
group.long 0x514++0x03
line.long 0x00 "S_F_EDGE_STS_NMI,This register provides interrupt detail detect status"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "NMI7SFSTS,NMI Synchronous Fall Edge Interrupt Status for CPU7 interface" "0: NMI fall edge interrupt request not occurred,1: NMI fall edge interrupt request occurred"
newline
rbitfld.long 0x00 6. "NMI6SFSTS,NMI Synchronous Fall Edge Interrupt Status for CPU6 interface" "0: NMI fall edge interrupt request not occurred,1: NMI fall edge interrupt request occurred"
rbitfld.long 0x00 5. "NMI5SFSTS,NMI Synchronous Fall Edge Interrupt Status for CPU5 interface" "0: NMI fall edge interrupt request not occurred,1: NMI fall edge interrupt request occurred"
newline
rbitfld.long 0x00 4. "NMI4SFSTS,NMI Synchronous Fall Edge Interrupt Status for CPU4 interface" "0: NMI fall edge interrupt request not occurred,1: NMI fall edge interrupt request occurred"
rbitfld.long 0x00 3. "NMI3SFSTS,NMI Synchronous Fall Edge Interrupt Status for CPU3 interface" "0: NMI fall edge interrupt request not occurred,1: NMI fall edge interrupt request occurred"
newline
rbitfld.long 0x00 2. "NMI2SFSTS,NMI Synchronous Fall Edge Interrupt Status for CPU2 interface" "0: NMI fall edge interrupt request not occurred,1: NMI fall edge interrupt request occurred"
rbitfld.long 0x00 1. "NMI1SFSTS,NMI Synchronous Fall Edge Interrupt Status for CPU1 interface" "0: NMI fall edge interrupt request not occurred,1: NMI fall edge interrupt request occurred"
newline
rbitfld.long 0x00 0. "NMI0SFSTS,NMI Synchronous Fall Edge Interrupt Status for CPU0 interface" "0: NMI fall edge interrupt request not occurred,1: NMI fall edge interrupt request occurred"
group.long 0x518++0x03
line.long 0x00 "A_R_EDGE_STS_NMI,This register provides interrupt detail detect status"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "NMI7ARSTS,NMI Asynchronous Rise Edge Interrupt Status for CPU7 interface" "0: NMI rise edge interrupt request not occurred,1: NMI rise edge interrupt request occurred"
newline
rbitfld.long 0x00 6. "NMI6ARSTS,NMI Asynchronous Rise Edge Interrupt Status for CPU6 interface" "0: NMI rise edge interrupt request not occurred,1: NMI rise edge interrupt request occurred"
rbitfld.long 0x00 5. "NMI5ARSTS,NMI Asynchronous Rise Edge Interrupt Status for CPU5 interface" "0: NMI rise edge interrupt request not occurred,1: NMI rise edge interrupt request occurred"
newline
rbitfld.long 0x00 4. "NMI4ARSTS,NMI Asynchronous Rise Edge Interrupt Status for CPU4 interface" "0: NMI rise edge interrupt request not occurred,1: NMI rise edge interrupt request occurred"
rbitfld.long 0x00 3. "NMI3ARSTS,NMI Asynchronous Rise Edge Interrupt Status for CPU3 interface" "0: NMI rise edge interrupt request not occurred,1: NMI rise edge interrupt request occurred"
newline
rbitfld.long 0x00 2. "NMI2ARSTS,NMI Asynchronous Rise Edge Interrupt Status for CPU2 interface" "0: NMI rise edge interrupt request not occurred,1: NMI rise edge interrupt request occurred"
rbitfld.long 0x00 1. "NMI1ARSTS,NMI Asynchronous Rise Edge Interrupt Status for CPU1 interface" "0: NMI rise edge interrupt request not occurred,1: NMI rise edge interrupt request occurred"
newline
rbitfld.long 0x00 0. "NMI0ARSTS,NMI Asynchronous Rise Edge Interrupt Status for CPU0 interface" "0: NMI rise edge interrupt request not occurred,1: NMI rise edge interrupt request occurred"
group.long 0x51C++0x03
line.long 0x00 "A_F_EDGE_STS_NMI,This register provides interrupt detail detect status"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "NMI7AFSTS,NMI Asynchronous Fall Edge Interrupt Status for CPU7 interface" "0: NMI fall edge interrupt request not occurred,1: NMI fall edge interrupt request occurred"
newline
rbitfld.long 0x00 6. "NMI6AFSTS,NMI Asynchronous Fall Edge Interrupt Status for CPU6 interface" "0: NMI fall edge interrupt request not occurred,1: NMI fall edge interrupt request occurred"
rbitfld.long 0x00 5. "NMI5AFSTS,NMI Asynchronous Fall Edge Interrupt Status for CPU5 interface" "0: NMI fall edge interrupt request not occurred,1: NMI fall edge interrupt request occurred"
newline
rbitfld.long 0x00 4. "NMI4AFSTS,NMI Asynchronous Fall Edge Interrupt Status for CPU4 interface" "0: NMI fall edge interrupt request not occurred,1: NMI fall edge interrupt request occurred"
rbitfld.long 0x00 3. "NMI3AFSTS,NMI Asynchronous Fall Edge Interrupt Status for CPU3 interface" "0: NMI fall edge interrupt request not occurred,1: NMI fall edge interrupt request occurred"
newline
rbitfld.long 0x00 2. "NMI2AFSTS,NMI Asynchronous Fall Edge Interrupt Status for CPU2 interface" "0: NMI fall edge interrupt request not occurred,1: NMI fall edge interrupt request occurred"
rbitfld.long 0x00 1. "NMI1AFSTS,NMI Asynchronous Fall Edge Interrupt Status for CPU1 interface" "0: NMI fall edge interrupt request not occurred,1: NMI fall edge interrupt request occurred"
newline
rbitfld.long 0x00 0. "NMI0AFSTS,NMI Asynchronous Fall Edge Interrupt Status for CPU0 interface" "0: NMI fall edge interrupt request not occurred,1: NMI fall edge interrupt request occurred"
group.long 0x520++0x03
line.long 0x00 "CHTEN_STS_NMI,This register shows chattering reduction enable status"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "CHTEN,Chattering Reduction Enable Status" "0: Chattering reduction disabled,1: Chattering reduction enabled After you set"
group.long 0x540++0x03
line.long 0x00 "DEB_SET_NMI,This register provides chattering reduction setting"
bitfld.long 0x00 31. "CHTEN,Chattering Reduction Enable" "0: Chattering reduction disabled,1: Chattering reduction enabled"
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 22.--23. "STS1,NMI Scan Timing These bits provide chattering reduction timing" "0: 1 ms,1: 2 ms,2: 4 ms,3: 8 ms"
bitfld.long 0x00 16.--21. "STS2,NMI Chattering Reduction Period The chattering reduction period is defined by STS1 x STS2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.long.word 0x00 0.--15. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x580++0x03
line.long 0x00 "CONFIG_0_NMI,This register provides chattering reduction setting"
hexmask.long 0x00 6.--31. 1. "Reserved_6,Reserved These bits are always read as 0"
bitfld.long 0x00 0.--5. "SS,Sense Selection" "0: Disable event detection,1: Enable low level sensitive,2: Enable high level sensitive,?,4: Enable synchronous falling edge triggered,?,?,?,8: Enable synchronous rising edge triggered,?,?,?,12: Enable synchronous both edge triggered,?,?,?,16: Enable asynchronous falling edge triggered,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,32: Enable asynchronous rising edge triggered,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,48: Enable asynchronous both edge triggered Others,?..."
group.long 0x584++0x03
line.long 0x00 "CONFIG_1_NMI,This register provides chattering reduction setting"
hexmask.long 0x00 6.--31. 1. "Reserved_6,Reserved These bits are always read as 0"
bitfld.long 0x00 0.--5. "SS,Sense Selection" "0: Disable event detection,1: Enable low level sensitive,2: Enable high level sensitive,?,4: Enable synchronous falling edge triggered,?,?,?,8: Enable synchronous rising edge triggered,?,?,?,12: Enable synchronous both edge triggered,?,?,?,16: Enable asynchronous falling edge triggered,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,32: Enable asynchronous rising edge triggered,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,48: Enable asynchronous both edge triggered Others,?..."
group.long 0x588++0x03
line.long 0x00 "CONFIG_2_NMI,This register provides chattering reduction setting"
hexmask.long 0x00 6.--31. 1. "Reserved_6,Reserved These bits are always read as 0"
bitfld.long 0x00 0.--5. "SS,Sense Selection" "0: Disable event detection,1: Enable low level sensitive,2: Enable high level sensitive,?,4: Enable synchronous falling edge triggered,?,?,?,8: Enable synchronous rising edge triggered,?,?,?,12: Enable synchronous both edge triggered,?,?,?,16: Enable asynchronous falling edge triggered,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,32: Enable asynchronous rising edge triggered,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,48: Enable asynchronous both edge triggered Others,?..."
group.long 0x58C++0x03
line.long 0x00 "CONFIG_3_NMI,This register provides chattering reduction setting"
hexmask.long 0x00 6.--31. 1. "Reserved_6,Reserved These bits are always read as 0"
bitfld.long 0x00 0.--5. "SS,Sense Selection" "0: Disable event detection,1: Enable low level sensitive,2: Enable high level sensitive,?,4: Enable synchronous falling edge triggered,?,?,?,8: Enable synchronous rising edge triggered,?,?,?,12: Enable synchronous both edge triggered,?,?,?,16: Enable asynchronous falling edge triggered,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,32: Enable asynchronous rising edge triggered,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,48: Enable asynchronous both edge triggered Others,?..."
group.long 0x590++0x03
line.long 0x00 "CONFIG_4_NMI,This register provides chattering reduction setting"
hexmask.long 0x00 6.--31. 1. "Reserved_6,Reserved These bits are always read as 0"
bitfld.long 0x00 0.--5. "SS,Sense Selection" "0: Disable event detection,1: Enable low level sensitive,2: Enable high level sensitive,?,4: Enable synchronous falling edge triggered,?,?,?,8: Enable synchronous rising edge triggered,?,?,?,12: Enable synchronous both edge triggered,?,?,?,16: Enable asynchronous falling edge triggered,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,32: Enable asynchronous rising edge triggered,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,48: Enable asynchronous both edge triggered Others,?..."
group.long 0x594++0x03
line.long 0x00 "CONFIG_5_NMI,This register provides chattering reduction setting"
hexmask.long 0x00 6.--31. 1. "Reserved_6,Reserved These bits are always read as 0"
bitfld.long 0x00 0.--5. "SS,Sense Selection" "0: Disable event detection,1: Enable low level sensitive,2: Enable high level sensitive,?,4: Enable synchronous falling edge triggered,?,?,?,8: Enable synchronous rising edge triggered,?,?,?,12: Enable synchronous both edge triggered,?,?,?,16: Enable asynchronous falling edge triggered,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,32: Enable asynchronous rising edge triggered,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,48: Enable asynchronous both edge triggered Others,?..."
group.long 0x598++0x03
line.long 0x00 "CONFIG_6_NMI,This register provides chattering reduction setting"
hexmask.long 0x00 6.--31. 1. "Reserved_6,Reserved These bits are always read as 0"
bitfld.long 0x00 0.--5. "SS,Sense Selection" "0: Disable event detection,1: Enable low level sensitive,2: Enable high level sensitive,?,4: Enable synchronous falling edge triggered,?,?,?,8: Enable synchronous rising edge triggered,?,?,?,12: Enable synchronous both edge triggered,?,?,?,16: Enable asynchronous falling edge triggered,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,32: Enable asynchronous rising edge triggered,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,48: Enable asynchronous both edge triggered Others,?..."
group.long 0x59C++0x03
line.long 0x00 "CONFIG_7_NMI,This register provides chattering reduction setting"
hexmask.long 0x00 6.--31. 1. "Reserved_6,Reserved These bits are always read as 0"
bitfld.long 0x00 0.--5. "SS,Sense Selection" "0: Disable event detection,1: Enable low level sensitive,2: Enable high level sensitive,?,4: Enable synchronous falling edge triggered,?,?,?,8: Enable synchronous rising edge triggered,?,?,?,12: Enable synchronous both edge triggered,?,?,?,16: Enable asynchronous falling edge triggered,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,32: Enable asynchronous rising edge triggered,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,48: Enable asynchronous both edge triggered Others,?..."
group.long 0x5A0++0x03
line.long 0x00 "CONFIG_8_NMI,This register provides chattering reduction setting"
hexmask.long 0x00 6.--31. 1. "Reserved_6,Reserved These bits are always read as 0"
bitfld.long 0x00 0.--5. "SS,Sense Selection" "0: Disable event detection,1: Enable low level sensitive,2: Enable high level sensitive,?,4: Enable synchronous falling edge triggered,?,?,?,8: Enable synchronous rising edge triggered,?,?,?,12: Enable synchronous both edge triggered,?,?,?,16: Enable asynchronous falling edge triggered,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,32: Enable asynchronous rising edge triggered,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,48: Enable asynchronous both edge triggered Others,?..."
group.long 0xA00++0x03
line.long 0x00 "NMI_LCK,This register provides NMI mask locking feature"
hexmask.long 0x00 0.--31. 1. "MSKLCK,Lock code setting"
group.long 0xA04++0x03
line.long 0x00 "NMI_LCKCODE,This register sets the value for lock code of NMI mask"
hexmask.long 0x00 0.--31. 1. "LCKCODE,NMI mask lock code setting"
group.long 0xA08++0x03
line.long 0x00 "NMI_DBG,This register enables the debug feature for NMI mask lock"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
bitfld.long 0x00 0. "DBGEN,Enable debug for NMI mask lock feature" "0,1"
group.long 0xA0C++0x03
line.long 0x00 "NMI_DBGCODE,This register sets value for debug code of NMI mask lock"
hexmask.long 0x00 0.--31. 1. "DBGCODE,NMI mask lock debug code setting"
tree.end
tree "INTC_INST_5"
base ad:0xFFEA8000
repeat 16. (strings "00" "01" "02" "03" "04" "05" "06" "07" "08" "09" "10" "11" "12" "13" "14" "15" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x00)++0x03
line.long 0x00 "G4MH_INTSTS_R$1,"
abitfld.long 0x00 0.--31. "INT_STS,Interrupt to G4MH status" "0x00000000=0: no interrupt,0x00000001=1: Interrupt"
repeat.end
repeat 14. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 )
group.long ($2+0x40)++0x03
line.long 0x00 "G4MH_INTSTS_R$1,"
abitfld.long 0x00 0.--31. "INT_STS,Interrupt to G4MH status" "0x00000000=0: no interrupt,0x00000001=1: Interrupt"
repeat.end
repeat 16. (strings "00" "01" "02" "03" "04" "05" "06" "07" "08" "09" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x100)++0x03
line.long 0x00 "G4MH_INTMSK_R$1,"
abitfld.long 0x00 0.--31. "INT_MASK,Interrupt to G4MH mask setting" "0x00000000=0: unmask,0x00000001=1: mask"
repeat.end
repeat 14. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 )
group.long ($2+0x140)++0x03
line.long 0x00 "G4MH_INTMSK_R$1,"
abitfld.long 0x00 0.--31. "INT_MASK,Interrupt to G4MH mask setting" "0x00000000=0: unmask,0x00000001=1: mask"
repeat.end
repeat 16. (strings "00" "01" "02" "03" "04" "05" "06" "07" "08" "09" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x200)++0x03
line.long 0x00 "G4MH_INTSEL_R$1,D=(n*4+3) mod 32 m=round((n*4+3)/32)"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved" "0,1,2,3"
bitfld.long 0x00 24.--29. "BIT_Num0,Indicate the No" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 22.--23. "Reserved_22,Reserved" "0,1,2,3"
bitfld.long 0x00 16.--21. "BIT_Num1,Indicate the No" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 14.--15. "Reserved_14,Reserved" "0,1,2,3"
bitfld.long 0x00 8.--13. "BIT_Num2,Indicate the No" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 6.--7. "Reserved_6,Reserved" "0,1,2,3"
bitfld.long 0x00 0.--5. "BIT_Num3,Indicate the No" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
repeat.end
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x240)++0x03
line.long 0x00 "G4MH_INTSEL_R$1,D=(n*4+3) mod 32 m=round((n*4+3)/32)"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved" "0,1,2,3"
bitfld.long 0x00 24.--29. "BIT_Num0,Indicate the No" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 22.--23. "Reserved_22,Reserved" "0,1,2,3"
bitfld.long 0x00 16.--21. "BIT_Num1,Indicate the No" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 14.--15. "Reserved_14,Reserved" "0,1,2,3"
bitfld.long 0x00 8.--13. "BIT_Num2,Indicate the No" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 6.--7. "Reserved_6,Reserved" "0,1,2,3"
bitfld.long 0x00 0.--5. "BIT_Num3,Indicate the No" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
repeat.end
repeat 16. (strings "32" "33" "34" "35" "36" "37" "38" "39" "40" "41" "42" "43" "44" "45" "46" "47" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x280)++0x03
line.long 0x00 "G4MH_INTSEL_R$1,D=(n*4+3) mod 32 m=round((n*4+3)/32)"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved" "0,1,2,3"
bitfld.long 0x00 24.--29. "BIT_Num0,Indicate the No" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 22.--23. "Reserved_22,Reserved" "0,1,2,3"
bitfld.long 0x00 16.--21. "BIT_Num1,Indicate the No" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 14.--15. "Reserved_14,Reserved" "0,1,2,3"
bitfld.long 0x00 8.--13. "BIT_Num2,Indicate the No" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 6.--7. "Reserved_6,Reserved" "0,1,2,3"
bitfld.long 0x00 0.--5. "BIT_Num3,Indicate the No" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
repeat.end
repeat 16. (strings "48" "49" "50" "51" "52" "53" "54" "55" "56" "57" "58" "59" "60" "61" "62" "63" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x2C0)++0x03
line.long 0x00 "G4MH_INTSEL_R$1,D=(n*4+3) mod 32 m=round((n*4+3)/32)"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved" "0,1,2,3"
bitfld.long 0x00 24.--29. "BIT_Num0,Indicate the No" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 22.--23. "Reserved_22,Reserved" "0,1,2,3"
bitfld.long 0x00 16.--21. "BIT_Num1,Indicate the No" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 14.--15. "Reserved_14,Reserved" "0,1,2,3"
bitfld.long 0x00 8.--13. "BIT_Num2,Indicate the No" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 6.--7. "Reserved_6,Reserved" "0,1,2,3"
bitfld.long 0x00 0.--5. "BIT_Num3,Indicate the No" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
repeat.end
repeat 16. (strings "64" "65" "66" "67" "68" "69" "70" "71" "72" "73" "74" "75" "76" "77" "78" "79" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x300)++0x03
line.long 0x00 "G4MH_INTSEL_R$1,D=(n*4+3) mod 32 m=round((n*4+3)/32)"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved" "0,1,2,3"
bitfld.long 0x00 24.--29. "BIT_Num0,Indicate the No" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 22.--23. "Reserved_22,Reserved" "0,1,2,3"
bitfld.long 0x00 16.--21. "BIT_Num1,Indicate the No" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 14.--15. "Reserved_14,Reserved" "0,1,2,3"
bitfld.long 0x00 8.--13. "BIT_Num2,Indicate the No" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 6.--7. "Reserved_6,Reserved" "0,1,2,3"
bitfld.long 0x00 0.--5. "BIT_Num3,Indicate the No" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
repeat.end
repeat 16. (strings "80" "81" "82" "83" "84" "85" "86" "87" "88" "89" "90" "91" "92" "93" "94" "95" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x340)++0x03
line.long 0x00 "G4MH_INTSEL_R$1,D=(n*4+3) mod 32 m=round((n*4+3)/32)"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved" "0,1,2,3"
bitfld.long 0x00 24.--29. "BIT_Num0,Indicate the No" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 22.--23. "Reserved_22,Reserved" "0,1,2,3"
bitfld.long 0x00 16.--21. "BIT_Num1,Indicate the No" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 14.--15. "Reserved_14,Reserved" "0,1,2,3"
bitfld.long 0x00 8.--13. "BIT_Num2,Indicate the No" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 6.--7. "Reserved_6,Reserved" "0,1,2,3"
bitfld.long 0x00 0.--5. "BIT_Num3,Indicate the No" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
repeat.end
repeat 16. (strings "96" "97" "98" "99" "100" "101" "102" "103" "104" "105" "106" "107" "108" "109" "110" "111" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x380)++0x03
line.long 0x00 "G4MH_INTSEL_R$1,D=(n*4+3) mod 32 m=round((n*4+3)/32)"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved" "0,1,2,3"
bitfld.long 0x00 24.--29. "BIT_Num0,Indicate the No" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 22.--23. "Reserved_22,Reserved" "0,1,2,3"
bitfld.long 0x00 16.--21. "BIT_Num1,Indicate the No" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 14.--15. "Reserved_14,Reserved" "0,1,2,3"
bitfld.long 0x00 8.--13. "BIT_Num2,Indicate the No" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 6.--7. "Reserved_6,Reserved" "0,1,2,3"
bitfld.long 0x00 0.--5. "BIT_Num3,Indicate the No" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
repeat.end
repeat 16. (strings "112" "113" "114" "115" "116" "117" "118" "119" "120" "121" "122" "123" "124" "125" "126" "127" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x3C0)++0x03
line.long 0x00 "G4MH_INTSEL_R$1,D=(n*4+3) mod 32 m=round((n*4+3)/32)"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved" "0,1,2,3"
bitfld.long 0x00 24.--29. "BIT_Num0,Indicate the No" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 22.--23. "Reserved_22,Reserved" "0,1,2,3"
bitfld.long 0x00 16.--21. "BIT_Num1,Indicate the No" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 14.--15. "Reserved_14,Reserved" "0,1,2,3"
bitfld.long 0x00 8.--13. "BIT_Num2,Indicate the No" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 6.--7. "Reserved_6,Reserved" "0,1,2,3"
bitfld.long 0x00 0.--5. "BIT_Num3,Indicate the No" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
repeat.end
repeat 16. (strings "128" "129" "130" "131" "132" "133" "134" "135" "136" "137" "138" "139" "140" "141" "142" "143" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x400)++0x03
line.long 0x00 "G4MH_INTSEL_R$1,D=(n*4+3) mod 32 m=round((n*4+3)/32)"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved" "0,1,2,3"
bitfld.long 0x00 24.--29. "BIT_Num0,Indicate the No" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 22.--23. "Reserved_22,Reserved" "0,1,2,3"
bitfld.long 0x00 16.--21. "BIT_Num1,Indicate the No" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 14.--15. "Reserved_14,Reserved" "0,1,2,3"
bitfld.long 0x00 8.--13. "BIT_Num2,Indicate the No" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 6.--7. "Reserved_6,Reserved" "0,1,2,3"
bitfld.long 0x00 0.--5. "BIT_Num3,Indicate the No" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
repeat.end
repeat 16. (strings "144" "145" "146" "147" "148" "149" "150" "151" "152" "153" "154" "155" "156" "157" "158" "159" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x440)++0x03
line.long 0x00 "G4MH_INTSEL_R$1,D=(n*4+3) mod 32 m=round((n*4+3)/32)"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved" "0,1,2,3"
bitfld.long 0x00 24.--29. "BIT_Num0,Indicate the No" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 22.--23. "Reserved_22,Reserved" "0,1,2,3"
bitfld.long 0x00 16.--21. "BIT_Num1,Indicate the No" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 14.--15. "Reserved_14,Reserved" "0,1,2,3"
bitfld.long 0x00 8.--13. "BIT_Num2,Indicate the No" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 6.--7. "Reserved_6,Reserved" "0,1,2,3"
bitfld.long 0x00 0.--5. "BIT_Num3,Indicate the No" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
repeat.end
repeat 16. (strings "160" "161" "162" "163" "164" "165" "166" "167" "168" "169" "170" "171" "172" "173" "174" "175" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x480)++0x03
line.long 0x00 "G4MH_INTSEL_R$1,D=(n*4+3) mod 32 m=round((n*4+3)/32)"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved" "0,1,2,3"
bitfld.long 0x00 24.--29. "BIT_Num0,Indicate the No" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 22.--23. "Reserved_22,Reserved" "0,1,2,3"
bitfld.long 0x00 16.--21. "BIT_Num1,Indicate the No" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 14.--15. "Reserved_14,Reserved" "0,1,2,3"
bitfld.long 0x00 8.--13. "BIT_Num2,Indicate the No" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 6.--7. "Reserved_6,Reserved" "0,1,2,3"
bitfld.long 0x00 0.--5. "BIT_Num3,Indicate the No" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
repeat.end
repeat 16. (strings "176" "177" "178" "179" "180" "181" "182" "183" "184" "185" "186" "187" "188" "189" "190" "191" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x4C0)++0x03
line.long 0x00 "G4MH_INTSEL_R$1,D=(n*4+3) mod 32 m=round((n*4+3)/32)"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved" "0,1,2,3"
bitfld.long 0x00 24.--29. "BIT_Num0,Indicate the No" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 22.--23. "Reserved_22,Reserved" "0,1,2,3"
bitfld.long 0x00 16.--21. "BIT_Num1,Indicate the No" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 14.--15. "Reserved_14,Reserved" "0,1,2,3"
bitfld.long 0x00 8.--13. "BIT_Num2,Indicate the No" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 6.--7. "Reserved_6,Reserved" "0,1,2,3"
bitfld.long 0x00 0.--5. "BIT_Num3,Indicate the No" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
repeat.end
repeat 16. (strings "192" "193" "194" "195" "196" "197" "198" "199" "200" "201" "202" "203" "204" "205" "206" "207" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x500)++0x03
line.long 0x00 "G4MH_INTSEL_R$1,D=(n*4+3) mod 32 m=round((n*4+3)/32)"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved" "0,1,2,3"
bitfld.long 0x00 24.--29. "BIT_Num0,Indicate the No" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 22.--23. "Reserved_22,Reserved" "0,1,2,3"
bitfld.long 0x00 16.--21. "BIT_Num1,Indicate the No" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 14.--15. "Reserved_14,Reserved" "0,1,2,3"
bitfld.long 0x00 8.--13. "BIT_Num2,Indicate the No" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 6.--7. "Reserved_6,Reserved" "0,1,2,3"
bitfld.long 0x00 0.--5. "BIT_Num3,Indicate the No" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
repeat.end
repeat 16. (strings "208" "209" "210" "211" "212" "213" "214" "215" "216" "217" "218" "219" "220" "221" "222" "223" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x540)++0x03
line.long 0x00 "G4MH_INTSEL_R$1,D=(n*4+3) mod 32 m=round((n*4+3)/32)"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved" "0,1,2,3"
bitfld.long 0x00 24.--29. "BIT_Num0,Indicate the No" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 22.--23. "Reserved_22,Reserved" "0,1,2,3"
bitfld.long 0x00 16.--21. "BIT_Num1,Indicate the No" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 14.--15. "Reserved_14,Reserved" "0,1,2,3"
bitfld.long 0x00 8.--13. "BIT_Num2,Indicate the No" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 6.--7. "Reserved_6,Reserved" "0,1,2,3"
bitfld.long 0x00 0.--5. "BIT_Num3,Indicate the No" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
repeat.end
repeat 16. (strings "224" "225" "226" "227" "228" "229" "230" "231" "232" "233" "234" "235" "236" "237" "238" "239" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x580)++0x03
line.long 0x00 "G4MH_INTSEL_R$1,D=(n*4+3) mod 32 m=round((n*4+3)/32)"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved" "0,1,2,3"
bitfld.long 0x00 24.--29. "BIT_Num0,Indicate the No" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 22.--23. "Reserved_22,Reserved" "0,1,2,3"
bitfld.long 0x00 16.--21. "BIT_Num1,Indicate the No" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 14.--15. "Reserved_14,Reserved" "0,1,2,3"
bitfld.long 0x00 8.--13. "BIT_Num2,Indicate the No" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 6.--7. "Reserved_6,Reserved" "0,1,2,3"
bitfld.long 0x00 0.--5. "BIT_Num3,Indicate the No" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
repeat.end
tree.end
tree.end
tree "MFIS"
tree "MFIS_INST_0"
base ad:0xE6260000
repeat 8. (strings "0" "1" "2" "3" "4" "5" "6" "7" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C )
group.long ($2+0xC0)++0x03
line.long 0x00 "MFISLCKR$1,MFISLCKR is the dedicated register to realize the mutex function by use of LDR/STR instruction"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "LCK,Mutex Control [Reading]" "0: Releases the shared,1: Forbidden"
repeat.end
group.long 0x2C0++0x03
line.long 0x00 "MFIEDCSIDADDR,"
bitfld.long 0x00 31. "CLR,Clear SRC_ID which captured at EDC address check" "0: No effect,1: Clear SRC_ID"
hexmask.long.tbyte 0x00 8.--30. 1. "Reserved,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SRC_ID,SRC_ID after EDC error detection"
group.long 0x2C4++0x03
line.long 0x00 "MFIEDCSIDWDATA,"
bitfld.long 0x00 31. "CLR,Clear SRC_ID which captured at EDC address check" "0: No effect,1: Clear SRC_ID"
hexmask.long.tbyte 0x00 8.--30. 1. "Reserved,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SRC_ID,SRC_ID after EDC error detection"
group.long 0x600++0x03
line.long 0x00 "MFISOFTMDR,This register indicate the value of input port SOFTMD[3:0]"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "SOFTMD,Show SOFTMD[3:0] from FUSE module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x604++0x03
line.long 0x00 "MFISBTSTSR,This register indicates the boot status and is used for software"
hexmask.long 0x00 0.--31. 1. "Status_31_0,Update and monitor secure status"
repeat 16. (strings "8" "9" "10" "11" "12" "13" "14" "15" "16" "17" "18" "19" "20" "21" "22" "23" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x724)++0x03
line.long 0x00 "MFISLCKR$1,MFISLCKR is the dedicated register to realize the mutex function by use of LDR/STR instruction"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "LCK,Mutex Control [Reading]" "0: Releases the shared,1: Forbidden"
repeat.end
repeat 16. (strings "24" "25" "26" "27" "28" "29" "30" "31" "32" "33" "34" "35" "36" "37" "38" "39" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x764)++0x03
line.long 0x00 "MFISLCKR$1,MFISLCKR is the dedicated register to realize the mutex function by use of LDR/STR instruction"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "LCK,Mutex Control [Reading]" "0: Releases the shared,1: Forbidden"
repeat.end
repeat 16. (strings "40" "41" "42" "43" "44" "45" "46" "47" "48" "49" "50" "51" "52" "53" "54" "55" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x7A4)++0x03
line.long 0x00 "MFISLCKR$1,MFISLCKR is the dedicated register to realize the mutex function by use of LDR/STR instruction"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "LCK,Mutex Control [Reading]" "0: Releases the shared,1: Forbidden"
repeat.end
repeat 8. (strings "56" "57" "58" "59" "60" "61" "62" "63" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C )
group.long ($2+0x7E4)++0x03
line.long 0x00 "MFISLCKR$1,MFISLCKR is the dedicated register to realize the mutex function by use of LDR/STR instruction"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "LCK,Mutex Control [Reading]" "0: Releases the shared,1: Forbidden"
repeat.end
group.long 0x8B8++0x03
line.long 0x00 "MFISCMPERRSTSR,"
hexmask.long.word 0x00 16.--31. 1. "Reserved0,Reserved These bits are always read as 0"
abitfld.long 0x00 4.--15. "CMPERRSTS,Error detection status [Read]" "0x000=0: No effect,0x001=1: Clear error status"
rbitfld.long 0x00 0.--3. "Reserved1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x900++0x03
line.long 0x00 "MFISWPCNTR,This register is used to control write protection for all registers in ECM Unless writing code value this register cannot be updated"
hexmask.long.word 0x00 16.--31. 1. "CodeValue_15_0,Code Value(H'ACCE) When read return 0"
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved"
bitfld.long 0x00 0. "WPD,Write Protection Disable 1b1: Disable write protection 1b0: Enable write protection" "0,1"
group.long 0x904++0x03
line.long 0x00 "MFISWACNTR,This register is used when write access for the target register is executed"
hexmask.long.word 0x00 16.--31. 1. "CodeValue_15_0,Code Value(H'ACCE) When read return 0"
hexmask.long.word 0x00 0.--15. 1. "RegisterAddress_15_0,Lower 16-bits of the target register address"
group.long 0x944++0x03
line.long 0x00 "MFIERRINJ,"
hexmask.long 0x00 2.--31. 1. "Reserved,Reserved These bits are always read as 0"
bitfld.long 0x00 1. "POS_INJ,Post-fault injection" "0: Normal Operation,1: Error asserted"
bitfld.long 0x00 0. "PRE_INJ,Pre-fault injection" "0: Normal Operation,1: Error asserted"
group.long 0x1400++0x03
line.long 0x00 "MFISARIICR0,MFISARIICR is a read/write register to generate the interrupt from Cortex-A55 CPU core i [i = 0 1 2 3 4 5 6 7] to Cortex-R52 CPU core by software"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved"
hexmask.long.word 0x00 1.--15. 1. "IIC_14_0,Interrupt Source (from Cortex-A55 CPU core i [i = 0 1 2 3 4 5 6 7] to Cortex-R52 CPU core) Bits used to specify the source for interrupts generated by the IIR"
bitfld.long 0x00 0. "IIR,Internal Interrupt Request While this bit is 1 an interrupt request is issued to the Cortex-R52 CPU core" "0,1"
group.long 0x1440++0x03
line.long 0x00 "MFISARIMBR0,MFISARIMBR is a read/write register to inform the interrupt messages to the corresponding CPU"
hexmask.long 0x00 0.--31. 1. "IMSG_31_0,The message buffer for CPU communication or temporary buffer used for general purpose"
group.long 0x1480++0x03
line.long 0x00 "MFISAM0IICR0,MFISAMIICR is a read/write register to generate the interrupt from Cortex-A55 CPU core i [i = 0 1 2 3 4 5 6 7] to G4MH core k [k=0 1] domain by software"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved"
hexmask.long.word 0x00 1.--15. 1. "IIC_14_0,Interrupt Source (from Cortex-A55 CPU core i [i = 0 1 2 3 4 5 6 7] to G4MH core k [k=0 1]) Bits used to specify the source for interrupts generated by the IIR"
bitfld.long 0x00 0. "IIR,Internal Interrupt Request While this bit is 1 an interrupt request is issued to the G4MH core k [k=0 1]" "0,1"
group.long 0x14C0++0x03
line.long 0x00 "MFISAM0IMBR0,MFISAMIMBR is a read/write register to inform the interrupt messages to the corresponding CPU"
hexmask.long 0x00 0.--31. 1. "IMSG_31_0,The message buffer for CPU communication or temporary buffer used for general purpose"
group.long 0x1580++0x03
line.long 0x00 "MFISAM1IICR0,MFISAMIICR is a read/write register to generate the interrupt from Cortex-A55 CPU core i [i = 0 1 2 3 4 5 6 7] to G4MH core k [k=0 1] domain by software"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved"
hexmask.long.word 0x00 1.--15. 1. "IIC_14_0,Interrupt Source (from Cortex-A55 CPU core i [i = 0 1 2 3 4 5 6 7] to G4MH core k [k=0 1]) Bits used to specify the source for interrupts generated by the IIR"
bitfld.long 0x00 0. "IIR,Internal Interrupt Request While this bit is 1 an interrupt request is issued to the G4MH core k [k=0 1]" "0,1"
group.long 0x15C0++0x03
line.long 0x00 "MFISAM1IMBR0,MFISAMIMBR is a read/write register to inform the interrupt messages to the corresponding CPU"
hexmask.long 0x00 0.--31. 1. "IMSG_31_0,The message buffer for CPU communication or temporary buffer used for general purpose"
group.long 0x2408++0x03
line.long 0x00 "MFISARIICR1,MFISARIICR is a read/write register to generate the interrupt from Cortex-A55 CPU core i [i = 0 1 2 3 4 5 6 7] to Cortex-R52 CPU core by software"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved"
hexmask.long.word 0x00 1.--15. 1. "IIC_14_0,Interrupt Source (from Cortex-A55 CPU core i [i = 0 1 2 3 4 5 6 7] to Cortex-R52 CPU core) Bits used to specify the source for interrupts generated by the IIR"
bitfld.long 0x00 0. "IIR,Internal Interrupt Request While this bit is 1 an interrupt request is issued to the Cortex-R52 CPU core" "0,1"
group.long 0x2444++0x03
line.long 0x00 "MFISARIMBR1,MFISARIMBR is a read/write register to inform the interrupt messages to the corresponding CPU"
hexmask.long 0x00 0.--31. 1. "IMSG_31_0,The message buffer for CPU communication or temporary buffer used for general purpose"
group.long 0x2488++0x03
line.long 0x00 "MFISAM0IICR1,MFISAMIICR is a read/write register to generate the interrupt from Cortex-A55 CPU core i [i = 0 1 2 3 4 5 6 7] to G4MH core k [k=0 1] domain by software"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved"
hexmask.long.word 0x00 1.--15. 1. "IIC_14_0,Interrupt Source (from Cortex-A55 CPU core i [i = 0 1 2 3 4 5 6 7] to G4MH core k [k=0 1]) Bits used to specify the source for interrupts generated by the IIR"
bitfld.long 0x00 0. "IIR,Internal Interrupt Request While this bit is 1 an interrupt request is issued to the G4MH core k [k=0 1]" "0,1"
group.long 0x24C4++0x03
line.long 0x00 "MFISAM0IMBR1,MFISAMIMBR is a read/write register to inform the interrupt messages to the corresponding CPU"
hexmask.long 0x00 0.--31. 1. "IMSG_31_0,The message buffer for CPU communication or temporary buffer used for general purpose"
group.long 0x2588++0x03
line.long 0x00 "MFISAM1IICR1,MFISAMIICR is a read/write register to generate the interrupt from Cortex-A55 CPU core i [i = 0 1 2 3 4 5 6 7] to G4MH core k [k=0 1] domain by software"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved"
hexmask.long.word 0x00 1.--15. 1. "IIC_14_0,Interrupt Source (from Cortex-A55 CPU core i [i = 0 1 2 3 4 5 6 7] to G4MH core k [k=0 1]) Bits used to specify the source for interrupts generated by the IIR"
bitfld.long 0x00 0. "IIR,Internal Interrupt Request While this bit is 1 an interrupt request is issued to the G4MH core k [k=0 1]" "0,1"
group.long 0x25C4++0x03
line.long 0x00 "MFISAM1IMBR1,MFISAMIMBR is a read/write register to inform the interrupt messages to the corresponding CPU"
hexmask.long 0x00 0.--31. 1. "IMSG_31_0,The message buffer for CPU communication or temporary buffer used for general purpose"
group.long 0x3410++0x03
line.long 0x00 "MFISARIICR2,MFISARIICR is a read/write register to generate the interrupt from Cortex-A55 CPU core i [i = 0 1 2 3 4 5 6 7] to Cortex-R52 CPU core by software"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved"
hexmask.long.word 0x00 1.--15. 1. "IIC_14_0,Interrupt Source (from Cortex-A55 CPU core i [i = 0 1 2 3 4 5 6 7] to Cortex-R52 CPU core) Bits used to specify the source for interrupts generated by the IIR"
bitfld.long 0x00 0. "IIR,Internal Interrupt Request While this bit is 1 an interrupt request is issued to the Cortex-R52 CPU core" "0,1"
group.long 0x3448++0x03
line.long 0x00 "MFISARIMBR2,MFISARIMBR is a read/write register to inform the interrupt messages to the corresponding CPU"
hexmask.long 0x00 0.--31. 1. "IMSG_31_0,The message buffer for CPU communication or temporary buffer used for general purpose"
group.long 0x3490++0x03
line.long 0x00 "MFISAM0IICR2,MFISAMIICR is a read/write register to generate the interrupt from Cortex-A55 CPU core i [i = 0 1 2 3 4 5 6 7] to G4MH core k [k=0 1] domain by software"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved"
hexmask.long.word 0x00 1.--15. 1. "IIC_14_0,Interrupt Source (from Cortex-A55 CPU core i [i = 0 1 2 3 4 5 6 7] to G4MH core k [k=0 1]) Bits used to specify the source for interrupts generated by the IIR"
bitfld.long 0x00 0. "IIR,Internal Interrupt Request While this bit is 1 an interrupt request is issued to the G4MH core k [k=0 1]" "0,1"
group.long 0x34C8++0x03
line.long 0x00 "MFISAM0IMBR2,MFISAMIMBR is a read/write register to inform the interrupt messages to the corresponding CPU"
hexmask.long 0x00 0.--31. 1. "IMSG_31_0,The message buffer for CPU communication or temporary buffer used for general purpose"
group.long 0x3590++0x03
line.long 0x00 "MFISAM1IICR2,MFISAMIICR is a read/write register to generate the interrupt from Cortex-A55 CPU core i [i = 0 1 2 3 4 5 6 7] to G4MH core k [k=0 1] domain by software"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved"
hexmask.long.word 0x00 1.--15. 1. "IIC_14_0,Interrupt Source (from Cortex-A55 CPU core i [i = 0 1 2 3 4 5 6 7] to G4MH core k [k=0 1]) Bits used to specify the source for interrupts generated by the IIR"
bitfld.long 0x00 0. "IIR,Internal Interrupt Request While this bit is 1 an interrupt request is issued to the G4MH core k [k=0 1]" "0,1"
group.long 0x35C8++0x03
line.long 0x00 "MFISAM1IMBR2,MFISAMIMBR is a read/write register to inform the interrupt messages to the corresponding CPU"
hexmask.long 0x00 0.--31. 1. "IMSG_31_0,The message buffer for CPU communication or temporary buffer used for general purpose"
group.long 0x4418++0x03
line.long 0x00 "MFISARIICR3,MFISARIICR is a read/write register to generate the interrupt from Cortex-A55 CPU core i [i = 0 1 2 3 4 5 6 7] to Cortex-R52 CPU core by software"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved"
hexmask.long.word 0x00 1.--15. 1. "IIC_14_0,Interrupt Source (from Cortex-A55 CPU core i [i = 0 1 2 3 4 5 6 7] to Cortex-R52 CPU core) Bits used to specify the source for interrupts generated by the IIR"
bitfld.long 0x00 0. "IIR,Internal Interrupt Request While this bit is 1 an interrupt request is issued to the Cortex-R52 CPU core" "0,1"
group.long 0x444C++0x03
line.long 0x00 "MFISARIMBR3,MFISARIMBR is a read/write register to inform the interrupt messages to the corresponding CPU"
hexmask.long 0x00 0.--31. 1. "IMSG_31_0,The message buffer for CPU communication or temporary buffer used for general purpose"
group.long 0x4498++0x03
line.long 0x00 "MFISAM0IICR3,MFISAMIICR is a read/write register to generate the interrupt from Cortex-A55 CPU core i [i = 0 1 2 3 4 5 6 7] to G4MH core k [k=0 1] domain by software"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved"
hexmask.long.word 0x00 1.--15. 1. "IIC_14_0,Interrupt Source (from Cortex-A55 CPU core i [i = 0 1 2 3 4 5 6 7] to G4MH core k [k=0 1]) Bits used to specify the source for interrupts generated by the IIR"
bitfld.long 0x00 0. "IIR,Internal Interrupt Request While this bit is 1 an interrupt request is issued to the G4MH core k [k=0 1]" "0,1"
group.long 0x44CC++0x03
line.long 0x00 "MFISAM0IMBR3,MFISAMIMBR is a read/write register to inform the interrupt messages to the corresponding CPU"
hexmask.long 0x00 0.--31. 1. "IMSG_31_0,The message buffer for CPU communication or temporary buffer used for general purpose"
group.long 0x4598++0x03
line.long 0x00 "MFISAM1IICR3,MFISAMIICR is a read/write register to generate the interrupt from Cortex-A55 CPU core i [i = 0 1 2 3 4 5 6 7] to G4MH core k [k=0 1] domain by software"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved"
hexmask.long.word 0x00 1.--15. 1. "IIC_14_0,Interrupt Source (from Cortex-A55 CPU core i [i = 0 1 2 3 4 5 6 7] to G4MH core k [k=0 1]) Bits used to specify the source for interrupts generated by the IIR"
bitfld.long 0x00 0. "IIR,Internal Interrupt Request While this bit is 1 an interrupt request is issued to the G4MH core k [k=0 1]" "0,1"
group.long 0x45CC++0x03
line.long 0x00 "MFISAM1IMBR3,MFISAMIMBR is a read/write register to inform the interrupt messages to the corresponding CPU"
hexmask.long 0x00 0.--31. 1. "IMSG_31_0,The message buffer for CPU communication or temporary buffer used for general purpose"
group.long 0x5420++0x03
line.long 0x00 "MFISARIICR4,MFISARIICR is a read/write register to generate the interrupt from Cortex-A55 CPU core i [i = 0 1 2 3 4 5 6 7] to Cortex-R52 CPU core by software"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved"
hexmask.long.word 0x00 1.--15. 1. "IIC_14_0,Interrupt Source (from Cortex-A55 CPU core i [i = 0 1 2 3 4 5 6 7] to Cortex-R52 CPU core) Bits used to specify the source for interrupts generated by the IIR"
bitfld.long 0x00 0. "IIR,Internal Interrupt Request While this bit is 1 an interrupt request is issued to the Cortex-R52 CPU core" "0,1"
group.long 0x5450++0x03
line.long 0x00 "MFISARIMBR4,MFISARIMBR is a read/write register to inform the interrupt messages to the corresponding CPU"
hexmask.long 0x00 0.--31. 1. "IMSG_31_0,The message buffer for CPU communication or temporary buffer used for general purpose"
group.long 0x54A0++0x03
line.long 0x00 "MFISAM0IICR4,MFISAMIICR is a read/write register to generate the interrupt from Cortex-A55 CPU core i [i = 0 1 2 3 4 5 6 7] to G4MH core k [k=0 1] domain by software"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved"
hexmask.long.word 0x00 1.--15. 1. "IIC_14_0,Interrupt Source (from Cortex-A55 CPU core i [i = 0 1 2 3 4 5 6 7] to G4MH core k [k=0 1]) Bits used to specify the source for interrupts generated by the IIR"
bitfld.long 0x00 0. "IIR,Internal Interrupt Request While this bit is 1 an interrupt request is issued to the G4MH core k [k=0 1]" "0,1"
group.long 0x54D0++0x03
line.long 0x00 "MFISAM0IMBR4,MFISAMIMBR is a read/write register to inform the interrupt messages to the corresponding CPU"
hexmask.long 0x00 0.--31. 1. "IMSG_31_0,The message buffer for CPU communication or temporary buffer used for general purpose"
group.long 0x55A0++0x03
line.long 0x00 "MFISAM1IICR4,MFISAMIICR is a read/write register to generate the interrupt from Cortex-A55 CPU core i [i = 0 1 2 3 4 5 6 7] to G4MH core k [k=0 1] domain by software"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved"
hexmask.long.word 0x00 1.--15. 1. "IIC_14_0,Interrupt Source (from Cortex-A55 CPU core i [i = 0 1 2 3 4 5 6 7] to G4MH core k [k=0 1]) Bits used to specify the source for interrupts generated by the IIR"
bitfld.long 0x00 0. "IIR,Internal Interrupt Request While this bit is 1 an interrupt request is issued to the G4MH core k [k=0 1]" "0,1"
group.long 0x55D0++0x03
line.long 0x00 "MFISAM1IMBR4,MFISAMIMBR is a read/write register to inform the interrupt messages to the corresponding CPU"
hexmask.long 0x00 0.--31. 1. "IMSG_31_0,The message buffer for CPU communication or temporary buffer used for general purpose"
group.long 0x6428++0x03
line.long 0x00 "MFISARIICR5,MFISARIICR is a read/write register to generate the interrupt from Cortex-A55 CPU core i [i = 0 1 2 3 4 5 6 7] to Cortex-R52 CPU core by software"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved"
hexmask.long.word 0x00 1.--15. 1. "IIC_14_0,Interrupt Source (from Cortex-A55 CPU core i [i = 0 1 2 3 4 5 6 7] to Cortex-R52 CPU core) Bits used to specify the source for interrupts generated by the IIR"
bitfld.long 0x00 0. "IIR,Internal Interrupt Request While this bit is 1 an interrupt request is issued to the Cortex-R52 CPU core" "0,1"
group.long 0x6454++0x03
line.long 0x00 "MFISARIMBR5,MFISARIMBR is a read/write register to inform the interrupt messages to the corresponding CPU"
hexmask.long 0x00 0.--31. 1. "IMSG_31_0,The message buffer for CPU communication or temporary buffer used for general purpose"
group.long 0x64A8++0x03
line.long 0x00 "MFISAM0IICR5,MFISAMIICR is a read/write register to generate the interrupt from Cortex-A55 CPU core i [i = 0 1 2 3 4 5 6 7] to G4MH core k [k=0 1] domain by software"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved"
hexmask.long.word 0x00 1.--15. 1. "IIC_14_0,Interrupt Source (from Cortex-A55 CPU core i [i = 0 1 2 3 4 5 6 7] to G4MH core k [k=0 1]) Bits used to specify the source for interrupts generated by the IIR"
bitfld.long 0x00 0. "IIR,Internal Interrupt Request While this bit is 1 an interrupt request is issued to the G4MH core k [k=0 1]" "0,1"
group.long 0x64D4++0x03
line.long 0x00 "MFISAM0IMBR5,MFISAMIMBR is a read/write register to inform the interrupt messages to the corresponding CPU"
hexmask.long 0x00 0.--31. 1. "IMSG_31_0,The message buffer for CPU communication or temporary buffer used for general purpose"
group.long 0x65A8++0x03
line.long 0x00 "MFISAM1IICR5,MFISAMIICR is a read/write register to generate the interrupt from Cortex-A55 CPU core i [i = 0 1 2 3 4 5 6 7] to G4MH core k [k=0 1] domain by software"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved"
hexmask.long.word 0x00 1.--15. 1. "IIC_14_0,Interrupt Source (from Cortex-A55 CPU core i [i = 0 1 2 3 4 5 6 7] to G4MH core k [k=0 1]) Bits used to specify the source for interrupts generated by the IIR"
bitfld.long 0x00 0. "IIR,Internal Interrupt Request While this bit is 1 an interrupt request is issued to the G4MH core k [k=0 1]" "0,1"
group.long 0x65D4++0x03
line.long 0x00 "MFISAM1IMBR5,MFISAMIMBR is a read/write register to inform the interrupt messages to the corresponding CPU"
hexmask.long 0x00 0.--31. 1. "IMSG_31_0,The message buffer for CPU communication or temporary buffer used for general purpose"
group.long 0x7430++0x03
line.long 0x00 "MFISARIICR6,MFISARIICR is a read/write register to generate the interrupt from Cortex-A55 CPU core i [i = 0 1 2 3 4 5 6 7] to Cortex-R52 CPU core by software"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved"
hexmask.long.word 0x00 1.--15. 1. "IIC_14_0,Interrupt Source (from Cortex-A55 CPU core i [i = 0 1 2 3 4 5 6 7] to Cortex-R52 CPU core) Bits used to specify the source for interrupts generated by the IIR"
bitfld.long 0x00 0. "IIR,Internal Interrupt Request While this bit is 1 an interrupt request is issued to the Cortex-R52 CPU core" "0,1"
group.long 0x7458++0x03
line.long 0x00 "MFISARIMBR6,MFISARIMBR is a read/write register to inform the interrupt messages to the corresponding CPU"
hexmask.long 0x00 0.--31. 1. "IMSG_31_0,The message buffer for CPU communication or temporary buffer used for general purpose"
group.long 0x74B0++0x03
line.long 0x00 "MFISAM0IICR6,MFISAMIICR is a read/write register to generate the interrupt from Cortex-A55 CPU core i [i = 0 1 2 3 4 5 6 7] to G4MH core k [k=0 1] domain by software"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved"
hexmask.long.word 0x00 1.--15. 1. "IIC_14_0,Interrupt Source (from Cortex-A55 CPU core i [i = 0 1 2 3 4 5 6 7] to G4MH core k [k=0 1]) Bits used to specify the source for interrupts generated by the IIR"
bitfld.long 0x00 0. "IIR,Internal Interrupt Request While this bit is 1 an interrupt request is issued to the G4MH core k [k=0 1]" "0,1"
group.long 0x74D8++0x03
line.long 0x00 "MFISAM0IMBR6,MFISAMIMBR is a read/write register to inform the interrupt messages to the corresponding CPU"
hexmask.long 0x00 0.--31. 1. "IMSG_31_0,The message buffer for CPU communication or temporary buffer used for general purpose"
group.long 0x75B0++0x03
line.long 0x00 "MFISAM1IICR6,MFISAMIICR is a read/write register to generate the interrupt from Cortex-A55 CPU core i [i = 0 1 2 3 4 5 6 7] to G4MH core k [k=0 1] domain by software"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved"
hexmask.long.word 0x00 1.--15. 1. "IIC_14_0,Interrupt Source (from Cortex-A55 CPU core i [i = 0 1 2 3 4 5 6 7] to G4MH core k [k=0 1]) Bits used to specify the source for interrupts generated by the IIR"
bitfld.long 0x00 0. "IIR,Internal Interrupt Request While this bit is 1 an interrupt request is issued to the G4MH core k [k=0 1]" "0,1"
group.long 0x75D8++0x03
line.long 0x00 "MFISAM1IMBR6,MFISAMIMBR is a read/write register to inform the interrupt messages to the corresponding CPU"
hexmask.long 0x00 0.--31. 1. "IMSG_31_0,The message buffer for CPU communication or temporary buffer used for general purpose"
group.long 0x8438++0x03
line.long 0x00 "MFISARIICR7,MFISARIICR is a read/write register to generate the interrupt from Cortex-A55 CPU core i [i = 0 1 2 3 4 5 6 7] to Cortex-R52 CPU core by software"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved"
hexmask.long.word 0x00 1.--15. 1. "IIC_14_0,Interrupt Source (from Cortex-A55 CPU core i [i = 0 1 2 3 4 5 6 7] to Cortex-R52 CPU core) Bits used to specify the source for interrupts generated by the IIR"
bitfld.long 0x00 0. "IIR,Internal Interrupt Request While this bit is 1 an interrupt request is issued to the Cortex-R52 CPU core" "0,1"
group.long 0x845C++0x03
line.long 0x00 "MFISARIMBR7,MFISARIMBR is a read/write register to inform the interrupt messages to the corresponding CPU"
hexmask.long 0x00 0.--31. 1. "IMSG_31_0,The message buffer for CPU communication or temporary buffer used for general purpose"
group.long 0x84B8++0x03
line.long 0x00 "MFISAM0IICR7,MFISAMIICR is a read/write register to generate the interrupt from Cortex-A55 CPU core i [i = 0 1 2 3 4 5 6 7] to G4MH core k [k=0 1] domain by software"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved"
hexmask.long.word 0x00 1.--15. 1. "IIC_14_0,Interrupt Source (from Cortex-A55 CPU core i [i = 0 1 2 3 4 5 6 7] to G4MH core k [k=0 1]) Bits used to specify the source for interrupts generated by the IIR"
bitfld.long 0x00 0. "IIR,Internal Interrupt Request While this bit is 1 an interrupt request is issued to the G4MH core k [k=0 1]" "0,1"
group.long 0x84DC++0x03
line.long 0x00 "MFISAM0IMBR7,MFISAMIMBR is a read/write register to inform the interrupt messages to the corresponding CPU"
hexmask.long 0x00 0.--31. 1. "IMSG_31_0,The message buffer for CPU communication or temporary buffer used for general purpose"
group.long 0x85B8++0x03
line.long 0x00 "MFISAM1IICR7,MFISAMIICR is a read/write register to generate the interrupt from Cortex-A55 CPU core i [i = 0 1 2 3 4 5 6 7] to G4MH core k [k=0 1] domain by software"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved"
hexmask.long.word 0x00 1.--15. 1. "IIC_14_0,Interrupt Source (from Cortex-A55 CPU core i [i = 0 1 2 3 4 5 6 7] to G4MH core k [k=0 1]) Bits used to specify the source for interrupts generated by the IIR"
bitfld.long 0x00 0. "IIR,Internal Interrupt Request While this bit is 1 an interrupt request is issued to the G4MH core k [k=0 1]" "0,1"
group.long 0x85DC++0x03
line.long 0x00 "MFISAM1IMBR7,MFISAMIMBR is a read/write register to inform the interrupt messages to the corresponding CPU"
hexmask.long 0x00 0.--31. 1. "IMSG_31_0,The message buffer for CPU communication or temporary buffer used for general purpose"
repeat 8. (strings "0" "1" "2" "3" "4" "5" "6" "7" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 )
group.long ($2+0x9404)++0x03
line.long 0x00 "MFISAREICR$1,MFISAREICR is a read/write register to generate the interrupt from Cortex-R52 CPU core to Cortex-A55 CPU core i [i = 0 1 2 3 4 5 6 7] by software"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved"
hexmask.long.word 0x00 1.--15. 1. "EIC_14_0,Interrupt Source (from Cortex-R52 CPU core to Cortex-A55 CPU core i [i = 0 1 2 3 4 5 6 7]) Bits used to specify the source for interrupts generated by the IIR"
bitfld.long 0x00 0. "EIR,Internal Interrupt Request While this bit is 1 an interrupt request is issued to the Cortex-A55 CPU core i [i = 0 1 2 3 4 5 6 7]" "0,1"
repeat.end
repeat 8. (strings "0" "1" "2" "3" "4" "5" "6" "7" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C )
group.long ($2+0x9460)++0x03
line.long 0x00 "MFISAREMBR$1,MFISAMEMBR is a read/write register to inform the interrupt messages to the corresponding CPU"
hexmask.long 0x00 0.--31. 1. "EMSG_31_0,The message buffer for CPU communication or temporary buffer used for general purpose"
repeat.end
group.long 0x9504++0x03
line.long 0x00 "MFISRM0EICR0,MFISRMREICR is a read/write register to generate the interrupt from Cortex-R52 CPU core to G4MH core k [k=0 1] domain by software"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved"
hexmask.long.word 0x00 1.--15. 1. "IIC_14_0,Interrupt Source (from Cortex-R52 CPU core to G4MH core k [k=0 1]) Bits used to specify the source for interrupts generated by the IIR"
bitfld.long 0x00 0. "IIR,Internal Interrupt Request While this bit is 1 an interrupt request is issued to the G4MH core k [k=0 1]" "0,1"
group.long 0x9560++0x03
line.long 0x00 "MFISRM0EMBR0,MFISRMREMBR is a read/write register to inform the interrupt messages to the corresponding CPU"
hexmask.long 0x00 0.--31. 1. "IMSG_31_0,The message buffer for CPU communication or temporary buffer used for general purpose"
group.long 0x9604++0x03
line.long 0x00 "MFISRM1EICR0,MFISRMREICR is a read/write register to generate the interrupt from Cortex-R52 CPU core to G4MH core k [k=0 1] domain by software"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved"
hexmask.long.word 0x00 1.--15. 1. "IIC_14_0,Interrupt Source (from Cortex-R52 CPU core to G4MH core k [k=0 1]) Bits used to specify the source for interrupts generated by the IIR"
bitfld.long 0x00 0. "IIR,Internal Interrupt Request While this bit is 1 an interrupt request is issued to the G4MH core k [k=0 1]" "0,1"
group.long 0x9660++0x03
line.long 0x00 "MFISRM1EMBR0,MFISRMREMBR is a read/write register to inform the interrupt messages to the corresponding CPU"
hexmask.long 0x00 0.--31. 1. "IMSG_31_0,The message buffer for CPU communication or temporary buffer used for general purpose"
repeat 8. (strings "0" "1" "2" "3" "4" "5" "6" "7" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 )
group.long ($2+0xA484)++0x03
line.long 0x00 "MFISAM0EICR$1,MFISAMEICR is a read/write register to generate the interrupt from G4MH core k [k=0 1] core domain to ARM Application domain by software"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved"
hexmask.long.word 0x00 1.--15. 1. "IIC_14_0,Interrupt Source (from G4MH core k [k=0 1] to Cortex-A55 CPU core i [i = 0 1 2 3 4 5 6 7]) Bits used to specify the source for interrupts generated by the IIR"
bitfld.long 0x00 0. "IIR,Internal Interrupt Request While this bit is 1 an interrupt request is issued to the Cortex-A55 CPU core i [i = 0 1 2 3 4 5 6 7]" "0,1"
repeat.end
repeat 8. (strings "0" "1" "2" "3" "4" "5" "6" "7" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C )
group.long ($2+0xA4E0)++0x03
line.long 0x00 "MFISAM0EMBR$1,MFISAMEMBR is a read/write register to inform the interrupt messages to the corresponding CPU"
hexmask.long 0x00 0.--31. 1. "IMSG_31_0,The message buffer for CPU communication or temporary buffer used for general purpose"
repeat.end
group.long 0xA500++0x03
line.long 0x00 "MFISRM0IICR0,MFISRMRIICR is a read/write register to generate the interrupt from G4MH core k [k=0 1] domain to Cortex-R52 CPU core by software"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved"
hexmask.long.word 0x00 1.--15. 1. "IIC_14_0,Interrupt Source (from G4MH core k [k=0 1] to Cortex-R52 CPU core) Bits used to specify the source for interrupts generated by the IIR"
bitfld.long 0x00 0. "IIR,Internal Interrupt Request While this bit is 1 an interrupt request is issued to the Cortex-R52 CPU core" "0,1"
group.long 0xA540++0x03
line.long 0x00 "MFISRM0IMBR0,MFISRMRIMBR is a read/write register to inform the interrupt messages to the corresponding CPU"
hexmask.long 0x00 0.--31. 1. "IMSG_31_0,The message buffer for CPU communication or temporary buffer used for general purpose"
repeat 8. (strings "0" "1" "2" "3" "4" "5" "6" "7" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 )
group.long ($2+0xB484)++0x03
line.long 0x00 "MFISAM1EICR$1,MFISAMEICR is a read/write register to generate the interrupt from G4MH core k [k=0 1] core domain to ARM Application domain by software"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved"
hexmask.long.word 0x00 1.--15. 1. "IIC_14_0,Interrupt Source (from G4MH core k [k=0 1] to Cortex-A55 CPU core i [i = 0 1 2 3 4 5 6 7]) Bits used to specify the source for interrupts generated by the IIR"
bitfld.long 0x00 0. "IIR,Internal Interrupt Request While this bit is 1 an interrupt request is issued to the Cortex-A55 CPU core i [i = 0 1 2 3 4 5 6 7]" "0,1"
repeat.end
repeat 8. (strings "0" "1" "2" "3" "4" "5" "6" "7" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C )
group.long ($2+0xB4E0)++0x03
line.long 0x00 "MFISAM1EMBR$1,MFISAMEMBR is a read/write register to inform the interrupt messages to the corresponding CPU"
hexmask.long 0x00 0.--31. 1. "IMSG_31_0,The message buffer for CPU communication or temporary buffer used for general purpose"
repeat.end
group.long 0xB500++0x03
line.long 0x00 "MFISRM1IICR0,MFISRMRIICR is a read/write register to generate the interrupt from G4MH core k [k=0 1] domain to Cortex-R52 CPU core by software"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved"
hexmask.long.word 0x00 1.--15. 1. "IIC_14_0,Interrupt Source (from G4MH core k [k=0 1] to Cortex-R52 CPU core) Bits used to specify the source for interrupts generated by the IIR"
bitfld.long 0x00 0. "IIR,Internal Interrupt Request While this bit is 1 an interrupt request is issued to the Cortex-R52 CPU core" "0,1"
group.long 0xB540++0x03
line.long 0x00 "MFISRM1IMBR0,MFISRMRIMBR is a read/write register to inform the interrupt messages to the corresponding CPU"
hexmask.long 0x00 0.--31. 1. "IMSG_31_0,The message buffer for CPU communication or temporary buffer used for general purpose"
tree.end
tree "MFIS_INST_1"
base ad:0xFFF00000
group.long 0x44++0x03
line.long 0x00 "PRR,"
rbitfld.long 0x00 29.--31. "CA55_11EN,Cortex-A55 Cluster 3 State Bit 31 Cortex-A55 Cluster 3 State" "0: The product has Cortex-A55 CPU6,1: The product does not have Cortex-A55 CPU6,?..."
rbitfld.long 0x00 26.--28. "CA55_10EN,Cortex-A55 Cluster 2 State Bit 28 Cortex-A55 Cluster 2 State" "0: The product has Cortex-A55 CPU4,1: The product does not have Cortex-A55 CPU4,?..."
newline
rbitfld.long 0x00 23.--25. "CA55_01EN,Cortex-A55 Cluster 1 State Bit 25 Cortex-A55 Cluster 1 State" "0: The product has Cortex-A55 CPU2,1: The product does not have Cortex-A55 CPU2,?..."
rbitfld.long 0x00 20.--22. "CA55_00EN,Cortex-A55 Cluster 0 State Bit 22 Cortex-A55 Cluster 0 State" "0: The product has Cortex-A55 CPU0,1: The product does not have Cortex-A55 CPU0,?..."
newline
rbitfld.long 0x00 19. "CR52EN,Cortex-R52 Bit 19 Cortex-R52 State" "0: The product has a Cortex-R52 CPU,1: The product does not have Cortex-R52 CPU"
rbitfld.long 0x00 17.--18. "Reserved_17,Reserved These bits are always read as 0" "0,1,2,3"
newline
rbitfld.long 0x00 16. "G4MHEN,G4MH state Bit 17 G4MH State" "0: The product has G4MH CPU,1: The product does not have G4MH CPU"
rbitfld.long 0x00 15. "R_O,Chip Release" "0: Renesas,1: Other"
newline
hexmask.long.byte 0x00 8.--14. 1. "Product,S4 series Product code: 0x5A S4-x/S4N-x Identifying code S4/S4N Bit(HE607_8940 Bit0) :0 S4-x S4/S4N Bit(HE607_8940 Bit0) :1 S4N-x"
rbitfld.long 0x00 4.--7. "CUT,CUT level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 0.--3. "MASK,MASK level H'0: R-Car S4 ver1.0 H'1: R-Car S4 ver1.1 H'2: R-Car S4 ver1.2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree.end
tree.end
tree "ECM"
base ad:0xE6250000
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x00)++0x03
line.long 0x00 "ECMERRCTLR$1,This register is used to enable error checking function"
hexmask.long 0x00 0.--31. 1. "Enable_31_0,Error detection enable"
repeat.end
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x40)++0x03
line.long 0x00 "ECMERRCTLR$1,This register is used to enable error checking function"
hexmask.long 0x00 0.--31. 1. "Enable_31_0,Error detection enable"
repeat.end
repeat 16. (strings "32" "33" "34" "35" "36" "37" "38" "39" "40" "41" "42" "43" "44" "45" "46" "47" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x80)++0x03
line.long 0x00 "ECMERRCTLR$1,This register is used to enable error checking function"
hexmask.long 0x00 0.--31. 1. "Enable_31_0,Error detection enable"
repeat.end
repeat 3. (strings "48" "49" "50" )(list 0x0 0x4 0x8 )
group.long ($2+0xC0)++0x03
line.long 0x00 "ECMERRCTLR$1,This register is used to enable error checking function"
hexmask.long 0x00 0.--31. 1. "Enable_31_0,Error detection enable"
repeat.end
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x100)++0x03
line.long 0x00 "ECMERRSTSR$1,This register is used to enable error checking function"
hexmask.long 0x00 0.--31. 1. "Status_31_0,Error detection status"
repeat.end
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x140)++0x03
line.long 0x00 "ECMERRSTSR$1,This register is used to enable error checking function"
hexmask.long 0x00 0.--31. 1. "Status_31_0,Error detection status"
repeat.end
repeat 16. (strings "32" "33" "34" "35" "36" "37" "38" "39" "40" "41" "42" "43" "44" "45" "46" "47" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x180)++0x03
line.long 0x00 "ECMERRSTSR$1,This register is used to enable error checking function"
hexmask.long 0x00 0.--31. 1. "Status_31_0,Error detection status"
repeat.end
repeat 3. (strings "48" "49" "50" )(list 0x00 0x04 0x08 )
group.long ($2+0x1C0)++0x03
line.long 0x00 "ECMERRSTSR$1,This register is used to enable error checking function"
hexmask.long 0x00 0.--31. 1. "Status_31_0,Error detection status"
repeat.end
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x200)++0x03
line.long 0x00 "ECMERRTGTR$1,This register is used to choose the destination of interrupt signal which is output when error status register is set to 1b1"
hexmask.long 0x00 0.--31. 1. "Target_31_0,Error detection target"
repeat.end
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x240)++0x03
line.long 0x00 "ECMERRTGTR$1,This register is used to choose the destination of interrupt signal which is output when error status register is set to 1b1"
hexmask.long 0x00 0.--31. 1. "Target_31_0,Error detection target"
repeat.end
repeat 16. (strings "32" "33" "34" "35" "36" "37" "38" "39" "40" "41" "42" "43" "44" "45" "46" "47" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x280)++0x03
line.long 0x00 "ECMERRTGTR$1,This register is used to choose the destination of interrupt signal which is output when error status register is set to 1b1"
hexmask.long 0x00 0.--31. 1. "Target_31_0,Error detection target"
repeat.end
repeat 3. (strings "48" "49" "50" )(list 0x00 0x04 0x08 )
group.long ($2+0x2C0)++0x03
line.long 0x00 "ECMERRTGTR$1,This register is used to choose the destination of interrupt signal which is output when error status register is set to 1b1"
hexmask.long 0x00 0.--31. 1. "Target_31_0,Error detection target"
repeat.end
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x400)++0x03
line.long 0x00 "ECMERRCNTR$1,This register is used to enable counting the number of errors when 1-bit or multi-bit error of RAM ECC happened at the corresponding modules"
rbitfld.long 0x00 29.--31. "Reserved_29,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24.--28. "MECN_1bit,Maximum Error Count Number(1-bit) When error count value is the same as the maximum error count number the assert error notification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 21.--23. "Reserved_21,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--20. "CECN_1bit,Current Error Count Number(1-bit) If ECM detected error related to this error then count-up the error and update this field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 13.--15. "Reserved_13,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--12. "MECN_mbit,Maximum Error Count Number(multi-bit) When error count value is the same as the maximum error count number the assert error notification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "CECN_mbit,Current Error Count Number(multi-bit) If ECM detected error related to this error then count-up the error and update this field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
repeat.end
repeat 6. (strings "16" "17" "18" "19" "20" "21" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 )
group.long ($2+0x440)++0x03
line.long 0x00 "ECMERRCNTR$1,This register is used to enable counting the number of errors when 1-bit or multi-bit error of RAM ECC happened at the corresponding modules"
rbitfld.long 0x00 29.--31. "Reserved_29,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24.--28. "MECN_1bit,Maximum Error Count Number(1-bit) When error count value is the same as the maximum error count number the assert error notification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 21.--23. "Reserved_21,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--20. "CECN_1bit,Current Error Count Number(1-bit) If ECM detected error related to this error then count-up the error and update this field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 13.--15. "Reserved_13,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--12. "MECN_mbit,Maximum Error Count Number(multi-bit) When error count value is the same as the maximum error count number the assert error notification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "CECN_mbit,Current Error Count Number(multi-bit) If ECM detected error related to this error then count-up the error and update this field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
repeat.end
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x600)++0x03
line.long 0x00 "ECMERRFATALR$1,"
hexmask.long 0x00 0.--31. 1. "Fatal_31_0,Error Fatal/Normal setting when corresponding ECMERRTGTR[n]:Target is 0 otherwise the error will be masked to Fatal/Normal error output 1b1: Fatal 1b0: Normal"
repeat.end
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x640)++0x03
line.long 0x00 "ECMERRFATALR$1,"
hexmask.long 0x00 0.--31. 1. "Fatal_31_0,Error Fatal/Normal setting when corresponding ECMERRTGTR[n]:Target is 0 otherwise the error will be masked to Fatal/Normal error output 1b1: Fatal 1b0: Normal"
repeat.end
repeat 16. (strings "32" "33" "34" "35" "36" "37" "38" "39" "40" "41" "42" "43" "44" "45" "46" "47" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x680)++0x03
line.long 0x00 "ECMERRFATALR$1,"
hexmask.long 0x00 0.--31. 1. "Fatal_31_0,Error Fatal/Normal setting when corresponding ECMERRTGTR[n]:Target is 0 otherwise the error will be masked to Fatal/Normal error output 1b1: Fatal 1b0: Normal"
repeat.end
repeat 3. (strings "48" "49" "50" )(list 0x00 0x04 0x08 )
group.long ($2+0x6C0)++0x03
line.long 0x00 "ECMERRFATALR$1,"
hexmask.long 0x00 0.--31. 1. "Fatal_31_0,Error Fatal/Normal setting when corresponding ECMERRTGTR[n]:Target is 0 otherwise the error will be masked to Fatal/Normal error output 1b1: Fatal 1b0: Normal"
repeat.end
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x700)++0x03
line.long 0x00 "ECMPSSTATCTLRA$1,This register decides the group of the port safe state to each error signal"
bitfld.long 0x00 30.--31. "PSSG15_1_0,Post safe state group of error factor 15 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
bitfld.long 0x00 28.--29. "PSSG14_1_0,Post safe state group of error factor 14 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
newline
bitfld.long 0x00 26.--27. "PSSG13_1_0,Post safe state group of error factor 13 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
bitfld.long 0x00 24.--25. "PSSG12_1_0,Post safe state group of error factor 12 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
newline
bitfld.long 0x00 22.--23. "PSSG11_1_0,Post safe state group of error factor 11 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
bitfld.long 0x00 20.--21. "PSSG10_1_0,Post safe state group of error factor 10 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
newline
bitfld.long 0x00 18.--19. "PSSG9_1_0,Post safe state group of error factor 9 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
bitfld.long 0x00 16.--17. "PSSG8_1_0,Post safe state group of error factor 8 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
newline
bitfld.long 0x00 14.--15. "PSSG7_1_0,Post safe state group of error factor 7 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
bitfld.long 0x00 12.--13. "PSSG6_1_0,Post safe state group of error factor 6 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
newline
bitfld.long 0x00 10.--11. "PSSG5_1_0,Post safe state group of error factor 5 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
bitfld.long 0x00 8.--9. "PSSG4_1_0,Post safe state group of error factor 4 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
newline
bitfld.long 0x00 6.--7. "PSSG3_1_0,Post safe state group of error factor 3 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
bitfld.long 0x00 4.--5. "PSSG2_1_0,Post safe state group of error factor 2 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
newline
bitfld.long 0x00 2.--3. "PSSG1_1_0,Post safe state group of error factor 1 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
bitfld.long 0x00 0.--1. "PSSG0_1_0,Post safe state group of error factor 0 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
repeat.end
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x740)++0x03
line.long 0x00 "ECMPSSTATCTLRA$1,This register decides the group of the port safe state to each error signal"
bitfld.long 0x00 30.--31. "PSSG15_1_0,Post safe state group of error factor 15 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
bitfld.long 0x00 28.--29. "PSSG14_1_0,Post safe state group of error factor 14 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
newline
bitfld.long 0x00 26.--27. "PSSG13_1_0,Post safe state group of error factor 13 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
bitfld.long 0x00 24.--25. "PSSG12_1_0,Post safe state group of error factor 12 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
newline
bitfld.long 0x00 22.--23. "PSSG11_1_0,Post safe state group of error factor 11 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
bitfld.long 0x00 20.--21. "PSSG10_1_0,Post safe state group of error factor 10 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
newline
bitfld.long 0x00 18.--19. "PSSG9_1_0,Post safe state group of error factor 9 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
bitfld.long 0x00 16.--17. "PSSG8_1_0,Post safe state group of error factor 8 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
newline
bitfld.long 0x00 14.--15. "PSSG7_1_0,Post safe state group of error factor 7 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
bitfld.long 0x00 12.--13. "PSSG6_1_0,Post safe state group of error factor 6 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
newline
bitfld.long 0x00 10.--11. "PSSG5_1_0,Post safe state group of error factor 5 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
bitfld.long 0x00 8.--9. "PSSG4_1_0,Post safe state group of error factor 4 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
newline
bitfld.long 0x00 6.--7. "PSSG3_1_0,Post safe state group of error factor 3 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
bitfld.long 0x00 4.--5. "PSSG2_1_0,Post safe state group of error factor 2 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
newline
bitfld.long 0x00 2.--3. "PSSG1_1_0,Post safe state group of error factor 1 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
bitfld.long 0x00 0.--1. "PSSG0_1_0,Post safe state group of error factor 0 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
repeat.end
repeat 16. (strings "32" "33" "34" "35" "36" "37" "38" "39" "40" "41" "42" "43" "44" "45" "46" "47" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x780)++0x03
line.long 0x00 "ECMPSSTATCTLRA$1,This register decides the group of the port safe state to each error signal"
bitfld.long 0x00 30.--31. "PSSG15_1_0,Post safe state group of error factor 15 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
bitfld.long 0x00 28.--29. "PSSG14_1_0,Post safe state group of error factor 14 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
newline
bitfld.long 0x00 26.--27. "PSSG13_1_0,Post safe state group of error factor 13 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
bitfld.long 0x00 24.--25. "PSSG12_1_0,Post safe state group of error factor 12 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
newline
bitfld.long 0x00 22.--23. "PSSG11_1_0,Post safe state group of error factor 11 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
bitfld.long 0x00 20.--21. "PSSG10_1_0,Post safe state group of error factor 10 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
newline
bitfld.long 0x00 18.--19. "PSSG9_1_0,Post safe state group of error factor 9 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
bitfld.long 0x00 16.--17. "PSSG8_1_0,Post safe state group of error factor 8 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
newline
bitfld.long 0x00 14.--15. "PSSG7_1_0,Post safe state group of error factor 7 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
bitfld.long 0x00 12.--13. "PSSG6_1_0,Post safe state group of error factor 6 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
newline
bitfld.long 0x00 10.--11. "PSSG5_1_0,Post safe state group of error factor 5 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
bitfld.long 0x00 8.--9. "PSSG4_1_0,Post safe state group of error factor 4 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
newline
bitfld.long 0x00 6.--7. "PSSG3_1_0,Post safe state group of error factor 3 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
bitfld.long 0x00 4.--5. "PSSG2_1_0,Post safe state group of error factor 2 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
newline
bitfld.long 0x00 2.--3. "PSSG1_1_0,Post safe state group of error factor 1 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
bitfld.long 0x00 0.--1. "PSSG0_1_0,Post safe state group of error factor 0 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
repeat.end
repeat 3. (strings "48" "49" "50" )(list 0x00 0x04 0x08 )
group.long ($2+0x7C0)++0x03
line.long 0x00 "ECMPSSTATCTLRA$1,This register decides the group of the port safe state to each error signal"
bitfld.long 0x00 30.--31. "PSSG15_1_0,Post safe state group of error factor 15 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
bitfld.long 0x00 28.--29. "PSSG14_1_0,Post safe state group of error factor 14 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
newline
bitfld.long 0x00 26.--27. "PSSG13_1_0,Post safe state group of error factor 13 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
bitfld.long 0x00 24.--25. "PSSG12_1_0,Post safe state group of error factor 12 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
newline
bitfld.long 0x00 22.--23. "PSSG11_1_0,Post safe state group of error factor 11 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
bitfld.long 0x00 20.--21. "PSSG10_1_0,Post safe state group of error factor 10 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
newline
bitfld.long 0x00 18.--19. "PSSG9_1_0,Post safe state group of error factor 9 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
bitfld.long 0x00 16.--17. "PSSG8_1_0,Post safe state group of error factor 8 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
newline
bitfld.long 0x00 14.--15. "PSSG7_1_0,Post safe state group of error factor 7 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
bitfld.long 0x00 12.--13. "PSSG6_1_0,Post safe state group of error factor 6 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
newline
bitfld.long 0x00 10.--11. "PSSG5_1_0,Post safe state group of error factor 5 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
bitfld.long 0x00 8.--9. "PSSG4_1_0,Post safe state group of error factor 4 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
newline
bitfld.long 0x00 6.--7. "PSSG3_1_0,Post safe state group of error factor 3 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
bitfld.long 0x00 4.--5. "PSSG2_1_0,Post safe state group of error factor 2 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
newline
bitfld.long 0x00 2.--3. "PSSG1_1_0,Post safe state group of error factor 1 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
bitfld.long 0x00 0.--1. "PSSG0_1_0,Post safe state group of error factor 0 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
repeat.end
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x800)++0x03
line.long 0x00 "ECMPSSTATCTLRB$1,This register decides the group of the port safe state to each error signal"
bitfld.long 0x00 30.--31. "PSSG31_1_0,Post safe state group of error factor 31 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
bitfld.long 0x00 28.--29. "PSSG30_1_0,Post safe state group of error factor 30 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
newline
bitfld.long 0x00 26.--27. "PSSG29_1_0,Post safe state group of error factor 29 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
bitfld.long 0x00 24.--25. "PSSG28_1_0,Post safe state group of error factor 28 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
newline
bitfld.long 0x00 22.--23. "PSSG27_1_0,Post safe state group of error factor 27 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
bitfld.long 0x00 20.--21. "PSSG26_1_0,Post safe state group of error factor 26 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
newline
bitfld.long 0x00 18.--19. "PSSG25_1_0,Post safe state group of error factor 25 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
bitfld.long 0x00 16.--17. "PSSG24_1_0,Post safe state group of error factor 24 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
newline
bitfld.long 0x00 14.--15. "PSSG23_1_0,Post safe state group of error factor 23 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
bitfld.long 0x00 12.--13. "PSSG22_1_0,Post safe state group of error factor 22 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
newline
bitfld.long 0x00 10.--11. "PSSG21_1_0,Post safe state group of error factor 21 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
bitfld.long 0x00 8.--9. "PSSG20_1_0,Post safe state group of error factor 20 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
newline
bitfld.long 0x00 6.--7. "PSSG19_1_0,Post safe state group of error factor 19 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
bitfld.long 0x00 4.--5. "PSSG18_1_0,Post safe state group of error factor 18 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
newline
bitfld.long 0x00 2.--3. "PSSG17_1_0,Post safe state group of error factor 17 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
bitfld.long 0x00 0.--1. "PSSG16_1_0,Post safe state group of error factor 16 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
repeat.end
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x840)++0x03
line.long 0x00 "ECMPSSTATCTLRB$1,This register decides the group of the port safe state to each error signal"
bitfld.long 0x00 30.--31. "PSSG31_1_0,Post safe state group of error factor 31 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
bitfld.long 0x00 28.--29. "PSSG30_1_0,Post safe state group of error factor 30 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
newline
bitfld.long 0x00 26.--27. "PSSG29_1_0,Post safe state group of error factor 29 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
bitfld.long 0x00 24.--25. "PSSG28_1_0,Post safe state group of error factor 28 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
newline
bitfld.long 0x00 22.--23. "PSSG27_1_0,Post safe state group of error factor 27 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
bitfld.long 0x00 20.--21. "PSSG26_1_0,Post safe state group of error factor 26 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
newline
bitfld.long 0x00 18.--19. "PSSG25_1_0,Post safe state group of error factor 25 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
bitfld.long 0x00 16.--17. "PSSG24_1_0,Post safe state group of error factor 24 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
newline
bitfld.long 0x00 14.--15. "PSSG23_1_0,Post safe state group of error factor 23 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
bitfld.long 0x00 12.--13. "PSSG22_1_0,Post safe state group of error factor 22 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
newline
bitfld.long 0x00 10.--11. "PSSG21_1_0,Post safe state group of error factor 21 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
bitfld.long 0x00 8.--9. "PSSG20_1_0,Post safe state group of error factor 20 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
newline
bitfld.long 0x00 6.--7. "PSSG19_1_0,Post safe state group of error factor 19 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
bitfld.long 0x00 4.--5. "PSSG18_1_0,Post safe state group of error factor 18 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
newline
bitfld.long 0x00 2.--3. "PSSG17_1_0,Post safe state group of error factor 17 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
bitfld.long 0x00 0.--1. "PSSG16_1_0,Post safe state group of error factor 16 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
repeat.end
repeat 16. (strings "32" "33" "34" "35" "36" "37" "38" "39" "40" "41" "42" "43" "44" "45" "46" "47" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x880)++0x03
line.long 0x00 "ECMPSSTATCTLRB$1,This register decides the group of the port safe state to each error signal"
bitfld.long 0x00 30.--31. "PSSG31_1_0,Post safe state group of error factor 31 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
bitfld.long 0x00 28.--29. "PSSG30_1_0,Post safe state group of error factor 30 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
newline
bitfld.long 0x00 26.--27. "PSSG29_1_0,Post safe state group of error factor 29 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
bitfld.long 0x00 24.--25. "PSSG28_1_0,Post safe state group of error factor 28 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
newline
bitfld.long 0x00 22.--23. "PSSG27_1_0,Post safe state group of error factor 27 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
bitfld.long 0x00 20.--21. "PSSG26_1_0,Post safe state group of error factor 26 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
newline
bitfld.long 0x00 18.--19. "PSSG25_1_0,Post safe state group of error factor 25 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
bitfld.long 0x00 16.--17. "PSSG24_1_0,Post safe state group of error factor 24 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
newline
bitfld.long 0x00 14.--15. "PSSG23_1_0,Post safe state group of error factor 23 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
bitfld.long 0x00 12.--13. "PSSG22_1_0,Post safe state group of error factor 22 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
newline
bitfld.long 0x00 10.--11. "PSSG21_1_0,Post safe state group of error factor 21 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
bitfld.long 0x00 8.--9. "PSSG20_1_0,Post safe state group of error factor 20 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
newline
bitfld.long 0x00 6.--7. "PSSG19_1_0,Post safe state group of error factor 19 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
bitfld.long 0x00 4.--5. "PSSG18_1_0,Post safe state group of error factor 18 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
newline
bitfld.long 0x00 2.--3. "PSSG17_1_0,Post safe state group of error factor 17 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
bitfld.long 0x00 0.--1. "PSSG16_1_0,Post safe state group of error factor 16 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
repeat.end
repeat 3. (strings "48" "49" "50" )(list 0x00 0x04 0x08 )
group.long ($2+0x8C0)++0x03
line.long 0x00 "ECMPSSTATCTLRB$1,This register decides the group of the port safe state to each error signal"
bitfld.long 0x00 30.--31. "PSSG31_1_0,Post safe state group of error factor 31 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
bitfld.long 0x00 28.--29. "PSSG30_1_0,Post safe state group of error factor 30 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
newline
bitfld.long 0x00 26.--27. "PSSG29_1_0,Post safe state group of error factor 29 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
bitfld.long 0x00 24.--25. "PSSG28_1_0,Post safe state group of error factor 28 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
newline
bitfld.long 0x00 22.--23. "PSSG27_1_0,Post safe state group of error factor 27 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
bitfld.long 0x00 20.--21. "PSSG26_1_0,Post safe state group of error factor 26 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
newline
bitfld.long 0x00 18.--19. "PSSG25_1_0,Post safe state group of error factor 25 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
bitfld.long 0x00 16.--17. "PSSG24_1_0,Post safe state group of error factor 24 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
newline
bitfld.long 0x00 14.--15. "PSSG23_1_0,Post safe state group of error factor 23 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
bitfld.long 0x00 12.--13. "PSSG22_1_0,Post safe state group of error factor 22 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
newline
bitfld.long 0x00 10.--11. "PSSG21_1_0,Post safe state group of error factor 21 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
bitfld.long 0x00 8.--9. "PSSG20_1_0,Post safe state group of error factor 20 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
newline
bitfld.long 0x00 6.--7. "PSSG19_1_0,Post safe state group of error factor 19 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
bitfld.long 0x00 4.--5. "PSSG18_1_0,Post safe state group of error factor 18 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
newline
bitfld.long 0x00 2.--3. "PSSG17_1_0,Post safe state group of error factor 17 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
bitfld.long 0x00 0.--1. "PSSG16_1_0,Post safe state group of error factor 16 of ECMERRCTRLn 2b00 : port safe state group0 2b01 : port safe state group1 2b10 : port safe state group2 2b11 : port safe state group3" "0,1,2,3"
repeat.end
group.long 0x900++0x03
line.long 0x00 "ECMPSSTATCTLRM,"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
bitfld.long 0x00 0. "EOR,Error output control enable" "0: keep initial value of the error output status,1: error output enable(clear initial value)"
group.long 0x928++0x03
line.long 0x00 "ECMGEIIDR,"
hexmask.long 0x00 3.--31. 1. "Reserved_3,Reserved"
bitfld.long 0x00 0.--2. "SGE_ID,Software Error Interrupt ID" "0,1,2,3,4,5,6,7"
group.long 0x940++0x03
line.long 0x00 "SAFCLERRENR,"
hexmask.long 0x00 0.--31. 1. "CLR_31_0,Enable Error Insertion Set"
group.long 0x944++0x03
line.long 0x00 "SAFSTERRENR,"
hexmask.long 0x00 0.--31. 1. "SET_31_0,B1: Set Error Insertion"
group.long 0x948++0x03
line.long 0x00 "SAFCTLR,SAFCTLR is used to enable debug function"
bitfld.long 0x00 31. "DBGEN,Error Insertion Enable Status" "0: Disable debug function,1: Enable debug function"
hexmask.long 0x00 6.--30. 1. "Reserved_6,Reserved"
newline
bitfld.long 0x00 0.--5. "REGSEL_5_0,Select Error status register which ECM update error status" "0: ECM Error Status 0 Register select,1: ECM Error Status 1 Register select,2: ECM Error Status 2 Register select,3: ECM Error Status 3 Register select,4: ECM Error Status 4 Register select,5: ECM Error Status 5 Register select,6: ECM Error Status 6 Register select,7: ECM Error Status 7 Register select,8: ECM Error Status 8 Register select,9: ECM Error Status 9 Register select,10: ECM Error Status 10 Register select,11: ECM Error Status 11 Register select,12: ECM Error Status 12 Register select,13: ECM Error Status 13 Register select,14: ECM Error Status 14 Register select,15: ECM Error Status 15 Register select,16: ECM Error Status 16 Register select,17: ECM Error Status 17 Register select,18: ECM Error Status 18 Register select,19: ECM Error Status 19 Register select,20: ECM Error Status 20 Register select,21: ECM Error Status 21 Register select,22: ECM Error Status 22 Register select,23: ECM Error Status 23 Register select,24: ECM Error Status 24 Register select,25: ECM Error Status 25 Register select,26: ECM Error Status 26 Register select,27: ECM Error Status 27 Register select,28: ECM Error Status 28 Register select,29: ECM Error Status 29 Register select,30: ECM Error Status 30 Register select,31: ECM Error Status 31 Register select,32: ECM Error Status 32 Register select,33: ECM Error Status 33 Register select,34: ECM Error Status 34 Register select,35: ECM Error Status 35 Register select,36: ECM Error Status 36 Register select,37: ECM Error Status 37 Register select,38: ECM Error Status 38 Register select,39: ECM Error Status 39 Register select,40: ECM Error Status 40 Register select,41: ECM Error Status 41 Register select,42: ECM Error Status 42 Register select,43: ECM Error Status 43 Register select,44: ECM Error Status 44 Register select,45: ECM Error Status 45 Register select,46: ECM Error Status 46 Register select,47: ECM Error Status 47 Register select,48: ECM Error Status 48 Register select,49: ECM Error Status 49 Register select,50: ECM Error Status 50 Register select,?..."
group.long 0x94C++0x03
line.long 0x00 "SAFSTSR,"
hexmask.long 0x00 0.--31. 1. "STS_31_0,Error Insertion Enable Status"
group.long 0x95C++0x03
line.long 0x00 "ECMEDCERRSIDPADDR,Error SID register for PADDR"
bitfld.long 0x00 31. "CLR,Clear for SRC_ID captured at EDC library" "0: No effect,1: Clear SRC ID"
hexmask.long.tbyte 0x00 8.--30. 1. "Reserved_8,Reserved"
newline
hexmask.long.byte 0x00 0.--7. 1. "SRC_ID,SRC_ID after EDC error detection"
group.long 0x960++0x03
line.long 0x00 "ECMEDCERRSIDPWDATAR,Error SID register for PWDATA"
bitfld.long 0x00 31. "CLR,Clear for SRC_ID captured at EDC library" "0: No effect,1: Clear SRC ID"
hexmask.long.tbyte 0x00 8.--30. 1. "Reserved_8,Reserved"
newline
hexmask.long.byte 0x00 0.--7. 1. "SRC_ID,SRC_ID after EDC error detection"
group.long 0x984++0x03
line.long 0x00 "ECMDCLSERMON00R,"
abitfld.long 0x00 0.--31. "DCLS_DUPERR_31_0,DCLS duplication Error Read" "0x00000000=0: no error Write No effect,0x00000001=1: detect DCLS duplication error"
group.long 0x988++0x03
line.long 0x00 "ECMDCLSERMON01R,"
abitfld.long 0x00 9.--31. "DCLS_DUPERR_31_25,DCLS duplication Error Read" "0x000000=0: no error Write No effect,0x000001=1: detect DCLS duplication error"
hexmask.long.word 0x00 0.--8. 1. "Reserved_0,Reserved"
group.long 0xA00++0x03
line.long 0x00 "ECMWPCNTR,This register is used to control write protection for all registers in ECM Unless writing code value this register cannot be updated"
hexmask.long.word 0x00 16.--31. 1. "CodeValue_15_0,Code Value(H'ACCE) When read return 0"
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved"
newline
bitfld.long 0x00 0. "WPD,Write Protection Disable 1b1: Disable write protection 1b0: Enable write protection" "0,1"
group.long 0xA04++0x03
line.long 0x00 "ECMWACNTR,This register is used when write access for the target register is executed"
hexmask.long.word 0x00 16.--31. 1. "CodeValue_15_0,Code Value(H'ACCE) When read return 0"
hexmask.long.word 0x00 0.--15. 1. "RegisterAddress_15_0,Lower 16-bits of the target register address"
tree.end
tree "AXI_BUS"
tree "AXI_BUS_INST_0"
base ad:0xE67E0000
repeat 16. (strings "00" "01" "02" "03" "04" "05" "06" "07" "08" "09" "010" "011" "012" "013" "014" "015" )(list 0x0 0x8 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x00)++0x07
line.quad 0x00 "QOSBW_FIX_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 53.--56. "Reserved_53,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 50.--52. "FIXQOS_BANK_n_5,FIXQOS_BANK[n]_5 Setting" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.byte 0x00 42.--49. 1. "FIXQOS_BANK_n_4,FIXQOS_BANK[n]_4 Setting"
newline
hexmask.quad.word 0x00 32.--41. 1. "FIXQOS_BANK_n_3,FIXQOS_BANK[n]_3 Setting"
newline
hexmask.quad.byte 0x00 24.--31. 1. "FIXQOS_BANK_n_2,FIXQOS_BANK[n]_2 Setting"
newline
hexmask.quad.byte 0x00 16.--23. 1. "FIXQOS_BANK_n_1,FIXQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--15. 1. "FIXQOS_BANK_n_0,FIXQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "016" "017" "018" "019" "020" "021" "022" "023" "024" "025" "026" "027" "028" "029" "030" "031" )(list 0x0 0x8 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x80)++0x07
line.quad 0x00 "QOSBW_FIX_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 53.--56. "Reserved_53,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 50.--52. "FIXQOS_BANK_n_5,FIXQOS_BANK[n]_5 Setting" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.byte 0x00 42.--49. 1. "FIXQOS_BANK_n_4,FIXQOS_BANK[n]_4 Setting"
newline
hexmask.quad.word 0x00 32.--41. 1. "FIXQOS_BANK_n_3,FIXQOS_BANK[n]_3 Setting"
newline
hexmask.quad.byte 0x00 24.--31. 1. "FIXQOS_BANK_n_2,FIXQOS_BANK[n]_2 Setting"
newline
hexmask.quad.byte 0x00 16.--23. 1. "FIXQOS_BANK_n_1,FIXQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--15. 1. "FIXQOS_BANK_n_0,FIXQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "032" "033" "034" "035" "036" "037" "038" "039" "040" "041" "042" "043" "044" "045" "046" "047" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x100)++0x07
line.quad 0x00 "QOSBW_FIX_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 53.--56. "Reserved_53,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 50.--52. "FIXQOS_BANK_n_5,FIXQOS_BANK[n]_5 Setting" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.byte 0x00 42.--49. 1. "FIXQOS_BANK_n_4,FIXQOS_BANK[n]_4 Setting"
newline
hexmask.quad.word 0x00 32.--41. 1. "FIXQOS_BANK_n_3,FIXQOS_BANK[n]_3 Setting"
newline
hexmask.quad.byte 0x00 24.--31. 1. "FIXQOS_BANK_n_2,FIXQOS_BANK[n]_2 Setting"
newline
hexmask.quad.byte 0x00 16.--23. 1. "FIXQOS_BANK_n_1,FIXQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--15. 1. "FIXQOS_BANK_n_0,FIXQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "048" "049" "050" "051" "052" "053" "054" "055" "056" "057" "058" "059" "060" "061" "062" "063" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x180)++0x07
line.quad 0x00 "QOSBW_FIX_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 53.--56. "Reserved_53,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 50.--52. "FIXQOS_BANK_n_5,FIXQOS_BANK[n]_5 Setting" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.byte 0x00 42.--49. 1. "FIXQOS_BANK_n_4,FIXQOS_BANK[n]_4 Setting"
newline
hexmask.quad.word 0x00 32.--41. 1. "FIXQOS_BANK_n_3,FIXQOS_BANK[n]_3 Setting"
newline
hexmask.quad.byte 0x00 24.--31. 1. "FIXQOS_BANK_n_2,FIXQOS_BANK[n]_2 Setting"
newline
hexmask.quad.byte 0x00 16.--23. 1. "FIXQOS_BANK_n_1,FIXQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--15. 1. "FIXQOS_BANK_n_0,FIXQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "064" "065" "066" "067" "068" "069" "070" "071" "072" "073" "074" "075" "076" "077" "078" "079" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x200)++0x07
line.quad 0x00 "QOSBW_FIX_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 53.--56. "Reserved_53,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 50.--52. "FIXQOS_BANK_n_5,FIXQOS_BANK[n]_5 Setting" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.byte 0x00 42.--49. 1. "FIXQOS_BANK_n_4,FIXQOS_BANK[n]_4 Setting"
newline
hexmask.quad.word 0x00 32.--41. 1. "FIXQOS_BANK_n_3,FIXQOS_BANK[n]_3 Setting"
newline
hexmask.quad.byte 0x00 24.--31. 1. "FIXQOS_BANK_n_2,FIXQOS_BANK[n]_2 Setting"
newline
hexmask.quad.byte 0x00 16.--23. 1. "FIXQOS_BANK_n_1,FIXQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--15. 1. "FIXQOS_BANK_n_0,FIXQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "080" "081" "082" "083" "084" "085" "086" "087" "088" "089" "090" "091" "092" "093" "094" "095" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x280)++0x07
line.quad 0x00 "QOSBW_FIX_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 53.--56. "Reserved_53,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 50.--52. "FIXQOS_BANK_n_5,FIXQOS_BANK[n]_5 Setting" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.byte 0x00 42.--49. 1. "FIXQOS_BANK_n_4,FIXQOS_BANK[n]_4 Setting"
newline
hexmask.quad.word 0x00 32.--41. 1. "FIXQOS_BANK_n_3,FIXQOS_BANK[n]_3 Setting"
newline
hexmask.quad.byte 0x00 24.--31. 1. "FIXQOS_BANK_n_2,FIXQOS_BANK[n]_2 Setting"
newline
hexmask.quad.byte 0x00 16.--23. 1. "FIXQOS_BANK_n_1,FIXQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--15. 1. "FIXQOS_BANK_n_0,FIXQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "096" "097" "098" "099" "0100" "0101" "0102" "0103" "0104" "0105" "0106" "0107" "0108" "0109" "0110" "0111" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x300)++0x07
line.quad 0x00 "QOSBW_FIX_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 53.--56. "Reserved_53,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 50.--52. "FIXQOS_BANK_n_5,FIXQOS_BANK[n]_5 Setting" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.byte 0x00 42.--49. 1. "FIXQOS_BANK_n_4,FIXQOS_BANK[n]_4 Setting"
newline
hexmask.quad.word 0x00 32.--41. 1. "FIXQOS_BANK_n_3,FIXQOS_BANK[n]_3 Setting"
newline
hexmask.quad.byte 0x00 24.--31. 1. "FIXQOS_BANK_n_2,FIXQOS_BANK[n]_2 Setting"
newline
hexmask.quad.byte 0x00 16.--23. 1. "FIXQOS_BANK_n_1,FIXQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--15. 1. "FIXQOS_BANK_n_0,FIXQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "0112" "0113" "0114" "0115" "0116" "0117" "0118" "0119" "0120" "0121" "0122" "0123" "0124" "0125" "0126" "0127" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x380)++0x07
line.quad 0x00 "QOSBW_FIX_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 53.--56. "Reserved_53,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 50.--52. "FIXQOS_BANK_n_5,FIXQOS_BANK[n]_5 Setting" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.byte 0x00 42.--49. 1. "FIXQOS_BANK_n_4,FIXQOS_BANK[n]_4 Setting"
newline
hexmask.quad.word 0x00 32.--41. 1. "FIXQOS_BANK_n_3,FIXQOS_BANK[n]_3 Setting"
newline
hexmask.quad.byte 0x00 24.--31. 1. "FIXQOS_BANK_n_2,FIXQOS_BANK[n]_2 Setting"
newline
hexmask.quad.byte 0x00 16.--23. 1. "FIXQOS_BANK_n_1,FIXQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--15. 1. "FIXQOS_BANK_n_0,FIXQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "0128" "0129" "0130" "0131" "0132" "0133" "0134" "0135" "0136" "0137" "0138" "0139" "0140" "0141" "0142" "0143" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x400)++0x07
line.quad 0x00 "QOSBW_FIX_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 53.--56. "Reserved_53,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 50.--52. "FIXQOS_BANK_n_5,FIXQOS_BANK[n]_5 Setting" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.byte 0x00 42.--49. 1. "FIXQOS_BANK_n_4,FIXQOS_BANK[n]_4 Setting"
newline
hexmask.quad.word 0x00 32.--41. 1. "FIXQOS_BANK_n_3,FIXQOS_BANK[n]_3 Setting"
newline
hexmask.quad.byte 0x00 24.--31. 1. "FIXQOS_BANK_n_2,FIXQOS_BANK[n]_2 Setting"
newline
hexmask.quad.byte 0x00 16.--23. 1. "FIXQOS_BANK_n_1,FIXQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--15. 1. "FIXQOS_BANK_n_0,FIXQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "0144" "0145" "0146" "0147" "0148" "0149" "0150" "0151" "0152" "0153" "0154" "0155" "0156" "0157" "0158" "0159" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x480)++0x07
line.quad 0x00 "QOSBW_FIX_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 53.--56. "Reserved_53,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 50.--52. "FIXQOS_BANK_n_5,FIXQOS_BANK[n]_5 Setting" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.byte 0x00 42.--49. 1. "FIXQOS_BANK_n_4,FIXQOS_BANK[n]_4 Setting"
newline
hexmask.quad.word 0x00 32.--41. 1. "FIXQOS_BANK_n_3,FIXQOS_BANK[n]_3 Setting"
newline
hexmask.quad.byte 0x00 24.--31. 1. "FIXQOS_BANK_n_2,FIXQOS_BANK[n]_2 Setting"
newline
hexmask.quad.byte 0x00 16.--23. 1. "FIXQOS_BANK_n_1,FIXQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--15. 1. "FIXQOS_BANK_n_0,FIXQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "0160" "0161" "0162" "0163" "0164" "0165" "0166" "0167" "0168" "0169" "0170" "0171" "0172" "0173" "0174" "0175" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x500)++0x07
line.quad 0x00 "QOSBW_FIX_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 53.--56. "Reserved_53,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 50.--52. "FIXQOS_BANK_n_5,FIXQOS_BANK[n]_5 Setting" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.byte 0x00 42.--49. 1. "FIXQOS_BANK_n_4,FIXQOS_BANK[n]_4 Setting"
newline
hexmask.quad.word 0x00 32.--41. 1. "FIXQOS_BANK_n_3,FIXQOS_BANK[n]_3 Setting"
newline
hexmask.quad.byte 0x00 24.--31. 1. "FIXQOS_BANK_n_2,FIXQOS_BANK[n]_2 Setting"
newline
hexmask.quad.byte 0x00 16.--23. 1. "FIXQOS_BANK_n_1,FIXQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--15. 1. "FIXQOS_BANK_n_0,FIXQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "0176" "0177" "0178" "0179" "0180" "0181" "0182" "0183" "0184" "0185" "0186" "0187" "0188" "0189" "0190" "0191" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x580)++0x07
line.quad 0x00 "QOSBW_FIX_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 53.--56. "Reserved_53,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 50.--52. "FIXQOS_BANK_n_5,FIXQOS_BANK[n]_5 Setting" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.byte 0x00 42.--49. 1. "FIXQOS_BANK_n_4,FIXQOS_BANK[n]_4 Setting"
newline
hexmask.quad.word 0x00 32.--41. 1. "FIXQOS_BANK_n_3,FIXQOS_BANK[n]_3 Setting"
newline
hexmask.quad.byte 0x00 24.--31. 1. "FIXQOS_BANK_n_2,FIXQOS_BANK[n]_2 Setting"
newline
hexmask.quad.byte 0x00 16.--23. 1. "FIXQOS_BANK_n_1,FIXQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--15. 1. "FIXQOS_BANK_n_0,FIXQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "0192" "0193" "0194" "0195" "0196" "0197" "0198" "0199" "0200" "0201" "0202" "0203" "0204" "0205" "0206" "0207" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x600)++0x07
line.quad 0x00 "QOSBW_FIX_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 53.--56. "Reserved_53,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 50.--52. "FIXQOS_BANK_n_5,FIXQOS_BANK[n]_5 Setting" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.byte 0x00 42.--49. 1. "FIXQOS_BANK_n_4,FIXQOS_BANK[n]_4 Setting"
newline
hexmask.quad.word 0x00 32.--41. 1. "FIXQOS_BANK_n_3,FIXQOS_BANK[n]_3 Setting"
newline
hexmask.quad.byte 0x00 24.--31. 1. "FIXQOS_BANK_n_2,FIXQOS_BANK[n]_2 Setting"
newline
hexmask.quad.byte 0x00 16.--23. 1. "FIXQOS_BANK_n_1,FIXQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--15. 1. "FIXQOS_BANK_n_0,FIXQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "0208" "0209" "0210" "0211" "0212" "0213" "0214" "0215" "0216" "0217" "0218" "0219" "0220" "0221" "0222" "0223" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x680)++0x07
line.quad 0x00 "QOSBW_FIX_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 53.--56. "Reserved_53,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 50.--52. "FIXQOS_BANK_n_5,FIXQOS_BANK[n]_5 Setting" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.byte 0x00 42.--49. 1. "FIXQOS_BANK_n_4,FIXQOS_BANK[n]_4 Setting"
newline
hexmask.quad.word 0x00 32.--41. 1. "FIXQOS_BANK_n_3,FIXQOS_BANK[n]_3 Setting"
newline
hexmask.quad.byte 0x00 24.--31. 1. "FIXQOS_BANK_n_2,FIXQOS_BANK[n]_2 Setting"
newline
hexmask.quad.byte 0x00 16.--23. 1. "FIXQOS_BANK_n_1,FIXQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--15. 1. "FIXQOS_BANK_n_0,FIXQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "0224" "0225" "0226" "0227" "0228" "0229" "0230" "0231" "0232" "0233" "0234" "0235" "0236" "0237" "0238" "0239" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x700)++0x07
line.quad 0x00 "QOSBW_FIX_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 53.--56. "Reserved_53,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 50.--52. "FIXQOS_BANK_n_5,FIXQOS_BANK[n]_5 Setting" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.byte 0x00 42.--49. 1. "FIXQOS_BANK_n_4,FIXQOS_BANK[n]_4 Setting"
newline
hexmask.quad.word 0x00 32.--41. 1. "FIXQOS_BANK_n_3,FIXQOS_BANK[n]_3 Setting"
newline
hexmask.quad.byte 0x00 24.--31. 1. "FIXQOS_BANK_n_2,FIXQOS_BANK[n]_2 Setting"
newline
hexmask.quad.byte 0x00 16.--23. 1. "FIXQOS_BANK_n_1,FIXQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--15. 1. "FIXQOS_BANK_n_0,FIXQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "0240" "0241" "0242" "0243" "0244" "0245" "0246" "0247" "0248" "0249" "0250" "0251" "0252" "0253" "0254" "0255" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x780)++0x07
line.quad 0x00 "QOSBW_FIX_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 53.--56. "Reserved_53,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 50.--52. "FIXQOS_BANK_n_5,FIXQOS_BANK[n]_5 Setting" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.byte 0x00 42.--49. 1. "FIXQOS_BANK_n_4,FIXQOS_BANK[n]_4 Setting"
newline
hexmask.quad.word 0x00 32.--41. 1. "FIXQOS_BANK_n_3,FIXQOS_BANK[n]_3 Setting"
newline
hexmask.quad.byte 0x00 24.--31. 1. "FIXQOS_BANK_n_2,FIXQOS_BANK[n]_2 Setting"
newline
hexmask.quad.byte 0x00 16.--23. 1. "FIXQOS_BANK_n_1,FIXQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--15. 1. "FIXQOS_BANK_n_0,FIXQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "0256" "0257" "0258" "0259" "0260" "0261" "0262" "0263" "0264" "0265" "0266" "0267" "0268" "0269" "0270" "0271" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x800)++0x07
line.quad 0x00 "QOSBW_FIX_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 53.--56. "Reserved_53,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 50.--52. "FIXQOS_BANK_n_5,FIXQOS_BANK[n]_5 Setting" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.byte 0x00 42.--49. 1. "FIXQOS_BANK_n_4,FIXQOS_BANK[n]_4 Setting"
newline
hexmask.quad.word 0x00 32.--41. 1. "FIXQOS_BANK_n_3,FIXQOS_BANK[n]_3 Setting"
newline
hexmask.quad.byte 0x00 24.--31. 1. "FIXQOS_BANK_n_2,FIXQOS_BANK[n]_2 Setting"
newline
hexmask.quad.byte 0x00 16.--23. 1. "FIXQOS_BANK_n_1,FIXQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--15. 1. "FIXQOS_BANK_n_0,FIXQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "0272" "0273" "0274" "0275" "0276" "0277" "0278" "0279" "0280" "0281" "0282" "0283" "0284" "0285" "0286" "0287" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x880)++0x07
line.quad 0x00 "QOSBW_FIX_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 53.--56. "Reserved_53,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 50.--52. "FIXQOS_BANK_n_5,FIXQOS_BANK[n]_5 Setting" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.byte 0x00 42.--49. 1. "FIXQOS_BANK_n_4,FIXQOS_BANK[n]_4 Setting"
newline
hexmask.quad.word 0x00 32.--41. 1. "FIXQOS_BANK_n_3,FIXQOS_BANK[n]_3 Setting"
newline
hexmask.quad.byte 0x00 24.--31. 1. "FIXQOS_BANK_n_2,FIXQOS_BANK[n]_2 Setting"
newline
hexmask.quad.byte 0x00 16.--23. 1. "FIXQOS_BANK_n_1,FIXQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--15. 1. "FIXQOS_BANK_n_0,FIXQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "0288" "0289" "0290" "0291" "0292" "0293" "0294" "0295" "0296" "0297" "0298" "0299" "0300" "0301" "0302" "0303" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x900)++0x07
line.quad 0x00 "QOSBW_FIX_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 53.--56. "Reserved_53,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 50.--52. "FIXQOS_BANK_n_5,FIXQOS_BANK[n]_5 Setting" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.byte 0x00 42.--49. 1. "FIXQOS_BANK_n_4,FIXQOS_BANK[n]_4 Setting"
newline
hexmask.quad.word 0x00 32.--41. 1. "FIXQOS_BANK_n_3,FIXQOS_BANK[n]_3 Setting"
newline
hexmask.quad.byte 0x00 24.--31. 1. "FIXQOS_BANK_n_2,FIXQOS_BANK[n]_2 Setting"
newline
hexmask.quad.byte 0x00 16.--23. 1. "FIXQOS_BANK_n_1,FIXQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--15. 1. "FIXQOS_BANK_n_0,FIXQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "0304" "0305" "0306" "0307" "0308" "0309" "0310" "0311" "0312" "0313" "0314" "0315" "0316" "0317" "0318" "0319" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x980)++0x07
line.quad 0x00 "QOSBW_FIX_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 53.--56. "Reserved_53,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 50.--52. "FIXQOS_BANK_n_5,FIXQOS_BANK[n]_5 Setting" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.byte 0x00 42.--49. 1. "FIXQOS_BANK_n_4,FIXQOS_BANK[n]_4 Setting"
newline
hexmask.quad.word 0x00 32.--41. 1. "FIXQOS_BANK_n_3,FIXQOS_BANK[n]_3 Setting"
newline
hexmask.quad.byte 0x00 24.--31. 1. "FIXQOS_BANK_n_2,FIXQOS_BANK[n]_2 Setting"
newline
hexmask.quad.byte 0x00 16.--23. 1. "FIXQOS_BANK_n_1,FIXQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--15. 1. "FIXQOS_BANK_n_0,FIXQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "0320" "0321" "0322" "0323" "0324" "0325" "0326" "0327" "0328" "0329" "0330" "0331" "0332" "0333" "0334" "0335" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0xA00)++0x07
line.quad 0x00 "QOSBW_FIX_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 53.--56. "Reserved_53,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 50.--52. "FIXQOS_BANK_n_5,FIXQOS_BANK[n]_5 Setting" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.byte 0x00 42.--49. 1. "FIXQOS_BANK_n_4,FIXQOS_BANK[n]_4 Setting"
newline
hexmask.quad.word 0x00 32.--41. 1. "FIXQOS_BANK_n_3,FIXQOS_BANK[n]_3 Setting"
newline
hexmask.quad.byte 0x00 24.--31. 1. "FIXQOS_BANK_n_2,FIXQOS_BANK[n]_2 Setting"
newline
hexmask.quad.byte 0x00 16.--23. 1. "FIXQOS_BANK_n_1,FIXQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--15. 1. "FIXQOS_BANK_n_0,FIXQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "0336" "0337" "0338" "0339" "0340" "0341" "0342" "0343" "0344" "0345" "0346" "0347" "0348" "0349" "0350" "0351" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0xA80)++0x07
line.quad 0x00 "QOSBW_FIX_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 53.--56. "Reserved_53,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 50.--52. "FIXQOS_BANK_n_5,FIXQOS_BANK[n]_5 Setting" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.byte 0x00 42.--49. 1. "FIXQOS_BANK_n_4,FIXQOS_BANK[n]_4 Setting"
newline
hexmask.quad.word 0x00 32.--41. 1. "FIXQOS_BANK_n_3,FIXQOS_BANK[n]_3 Setting"
newline
hexmask.quad.byte 0x00 24.--31. 1. "FIXQOS_BANK_n_2,FIXQOS_BANK[n]_2 Setting"
newline
hexmask.quad.byte 0x00 16.--23. 1. "FIXQOS_BANK_n_1,FIXQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--15. 1. "FIXQOS_BANK_n_0,FIXQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "0352" "0353" "0354" "0355" "0356" "0357" "0358" "0359" "0360" "0361" "0362" "0363" "0364" "0365" "0366" "0367" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0xB00)++0x07
line.quad 0x00 "QOSBW_FIX_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 53.--56. "Reserved_53,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 50.--52. "FIXQOS_BANK_n_5,FIXQOS_BANK[n]_5 Setting" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.byte 0x00 42.--49. 1. "FIXQOS_BANK_n_4,FIXQOS_BANK[n]_4 Setting"
newline
hexmask.quad.word 0x00 32.--41. 1. "FIXQOS_BANK_n_3,FIXQOS_BANK[n]_3 Setting"
newline
hexmask.quad.byte 0x00 24.--31. 1. "FIXQOS_BANK_n_2,FIXQOS_BANK[n]_2 Setting"
newline
hexmask.quad.byte 0x00 16.--23. 1. "FIXQOS_BANK_n_1,FIXQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--15. 1. "FIXQOS_BANK_n_0,FIXQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "0368" "0369" "0370" "0371" "0372" "0373" "0374" "0375" "0376" "0377" "0378" "0379" "0380" "0381" "0382" "0383" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0xB80)++0x07
line.quad 0x00 "QOSBW_FIX_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 53.--56. "Reserved_53,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 50.--52. "FIXQOS_BANK_n_5,FIXQOS_BANK[n]_5 Setting" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.byte 0x00 42.--49. 1. "FIXQOS_BANK_n_4,FIXQOS_BANK[n]_4 Setting"
newline
hexmask.quad.word 0x00 32.--41. 1. "FIXQOS_BANK_n_3,FIXQOS_BANK[n]_3 Setting"
newline
hexmask.quad.byte 0x00 24.--31. 1. "FIXQOS_BANK_n_2,FIXQOS_BANK[n]_2 Setting"
newline
hexmask.quad.byte 0x00 16.--23. 1. "FIXQOS_BANK_n_1,FIXQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--15. 1. "FIXQOS_BANK_n_0,FIXQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "0384" "0385" "0386" "0387" "0388" "0389" "0390" "0391" "0392" "0393" "0394" "0395" "0396" "0397" "0398" "0399" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0xC00)++0x07
line.quad 0x00 "QOSBW_FIX_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 53.--56. "Reserved_53,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 50.--52. "FIXQOS_BANK_n_5,FIXQOS_BANK[n]_5 Setting" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.byte 0x00 42.--49. 1. "FIXQOS_BANK_n_4,FIXQOS_BANK[n]_4 Setting"
newline
hexmask.quad.word 0x00 32.--41. 1. "FIXQOS_BANK_n_3,FIXQOS_BANK[n]_3 Setting"
newline
hexmask.quad.byte 0x00 24.--31. 1. "FIXQOS_BANK_n_2,FIXQOS_BANK[n]_2 Setting"
newline
hexmask.quad.byte 0x00 16.--23. 1. "FIXQOS_BANK_n_1,FIXQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--15. 1. "FIXQOS_BANK_n_0,FIXQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "0400" "0401" "0402" "0403" "0404" "0405" "0406" "0407" "0408" "0409" "0410" "0411" "0412" "0413" "0414" "0415" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0xC80)++0x07
line.quad 0x00 "QOSBW_FIX_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 53.--56. "Reserved_53,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 50.--52. "FIXQOS_BANK_n_5,FIXQOS_BANK[n]_5 Setting" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.byte 0x00 42.--49. 1. "FIXQOS_BANK_n_4,FIXQOS_BANK[n]_4 Setting"
newline
hexmask.quad.word 0x00 32.--41. 1. "FIXQOS_BANK_n_3,FIXQOS_BANK[n]_3 Setting"
newline
hexmask.quad.byte 0x00 24.--31. 1. "FIXQOS_BANK_n_2,FIXQOS_BANK[n]_2 Setting"
newline
hexmask.quad.byte 0x00 16.--23. 1. "FIXQOS_BANK_n_1,FIXQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--15. 1. "FIXQOS_BANK_n_0,FIXQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "0416" "0417" "0418" "0419" "0420" "0421" "0422" "0423" "0424" "0425" "0426" "0427" "0428" "0429" "0430" "0431" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0xD00)++0x07
line.quad 0x00 "QOSBW_FIX_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 53.--56. "Reserved_53,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 50.--52. "FIXQOS_BANK_n_5,FIXQOS_BANK[n]_5 Setting" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.byte 0x00 42.--49. 1. "FIXQOS_BANK_n_4,FIXQOS_BANK[n]_4 Setting"
newline
hexmask.quad.word 0x00 32.--41. 1. "FIXQOS_BANK_n_3,FIXQOS_BANK[n]_3 Setting"
newline
hexmask.quad.byte 0x00 24.--31. 1. "FIXQOS_BANK_n_2,FIXQOS_BANK[n]_2 Setting"
newline
hexmask.quad.byte 0x00 16.--23. 1. "FIXQOS_BANK_n_1,FIXQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--15. 1. "FIXQOS_BANK_n_0,FIXQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "0432" "0433" "0434" "0435" "0436" "0437" "0438" "0439" "0440" "0441" "0442" "0443" "0444" "0445" "0446" "0447" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0xD80)++0x07
line.quad 0x00 "QOSBW_FIX_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 53.--56. "Reserved_53,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 50.--52. "FIXQOS_BANK_n_5,FIXQOS_BANK[n]_5 Setting" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.byte 0x00 42.--49. 1. "FIXQOS_BANK_n_4,FIXQOS_BANK[n]_4 Setting"
newline
hexmask.quad.word 0x00 32.--41. 1. "FIXQOS_BANK_n_3,FIXQOS_BANK[n]_3 Setting"
newline
hexmask.quad.byte 0x00 24.--31. 1. "FIXQOS_BANK_n_2,FIXQOS_BANK[n]_2 Setting"
newline
hexmask.quad.byte 0x00 16.--23. 1. "FIXQOS_BANK_n_1,FIXQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--15. 1. "FIXQOS_BANK_n_0,FIXQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "0448" "0449" "0450" "0451" "0452" "0453" "0454" "0455" "0456" "0457" "0458" "0459" "0460" "0461" "0462" "0463" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0xE00)++0x07
line.quad 0x00 "QOSBW_FIX_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 53.--56. "Reserved_53,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 50.--52. "FIXQOS_BANK_n_5,FIXQOS_BANK[n]_5 Setting" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.byte 0x00 42.--49. 1. "FIXQOS_BANK_n_4,FIXQOS_BANK[n]_4 Setting"
newline
hexmask.quad.word 0x00 32.--41. 1. "FIXQOS_BANK_n_3,FIXQOS_BANK[n]_3 Setting"
newline
hexmask.quad.byte 0x00 24.--31. 1. "FIXQOS_BANK_n_2,FIXQOS_BANK[n]_2 Setting"
newline
hexmask.quad.byte 0x00 16.--23. 1. "FIXQOS_BANK_n_1,FIXQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--15. 1. "FIXQOS_BANK_n_0,FIXQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "0464" "0465" "0466" "0467" "0468" "0469" "0470" "0471" "0472" "0473" "0474" "0475" "0476" "0477" "0478" "0479" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0xE80)++0x07
line.quad 0x00 "QOSBW_FIX_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 53.--56. "Reserved_53,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 50.--52. "FIXQOS_BANK_n_5,FIXQOS_BANK[n]_5 Setting" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.byte 0x00 42.--49. 1. "FIXQOS_BANK_n_4,FIXQOS_BANK[n]_4 Setting"
newline
hexmask.quad.word 0x00 32.--41. 1. "FIXQOS_BANK_n_3,FIXQOS_BANK[n]_3 Setting"
newline
hexmask.quad.byte 0x00 24.--31. 1. "FIXQOS_BANK_n_2,FIXQOS_BANK[n]_2 Setting"
newline
hexmask.quad.byte 0x00 16.--23. 1. "FIXQOS_BANK_n_1,FIXQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--15. 1. "FIXQOS_BANK_n_0,FIXQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "0480" "0481" "0482" "0483" "0484" "0485" "0486" "0487" "0488" "0489" "0490" "0491" "0492" "0493" "0494" "0495" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0xF00)++0x07
line.quad 0x00 "QOSBW_FIX_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 53.--56. "Reserved_53,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 50.--52. "FIXQOS_BANK_n_5,FIXQOS_BANK[n]_5 Setting" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.byte 0x00 42.--49. 1. "FIXQOS_BANK_n_4,FIXQOS_BANK[n]_4 Setting"
newline
hexmask.quad.word 0x00 32.--41. 1. "FIXQOS_BANK_n_3,FIXQOS_BANK[n]_3 Setting"
newline
hexmask.quad.byte 0x00 24.--31. 1. "FIXQOS_BANK_n_2,FIXQOS_BANK[n]_2 Setting"
newline
hexmask.quad.byte 0x00 16.--23. 1. "FIXQOS_BANK_n_1,FIXQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--15. 1. "FIXQOS_BANK_n_0,FIXQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "0496" "0497" "0498" "0499" "0500" "0501" "0502" "0503" "0504" "0505" "0506" "0507" "0508" "0509" "0510" "0511" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0xF80)++0x07
line.quad 0x00 "QOSBW_FIX_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 53.--56. "Reserved_53,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 50.--52. "FIXQOS_BANK_n_5,FIXQOS_BANK[n]_5 Setting" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.byte 0x00 42.--49. 1. "FIXQOS_BANK_n_4,FIXQOS_BANK[n]_4 Setting"
newline
hexmask.quad.word 0x00 32.--41. 1. "FIXQOS_BANK_n_3,FIXQOS_BANK[n]_3 Setting"
newline
hexmask.quad.byte 0x00 24.--31. 1. "FIXQOS_BANK_n_2,FIXQOS_BANK[n]_2 Setting"
newline
hexmask.quad.byte 0x00 16.--23. 1. "FIXQOS_BANK_n_1,FIXQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--15. 1. "FIXQOS_BANK_n_0,FIXQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "10" "11" "12" "13" "14" "15" "16" "17" "18" "19" "110" "111" "112" "113" "114" "115" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x1000)++0x07
line.quad 0x00 "QOSBW_FIX_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 53.--56. "Reserved_53,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 50.--52. "FIXQOS_BANK_n_5,FIXQOS_BANK[n]_5 Setting" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.byte 0x00 42.--49. 1. "FIXQOS_BANK_n_4,FIXQOS_BANK[n]_4 Setting"
newline
hexmask.quad.word 0x00 32.--41. 1. "FIXQOS_BANK_n_3,FIXQOS_BANK[n]_3 Setting"
newline
hexmask.quad.byte 0x00 24.--31. 1. "FIXQOS_BANK_n_2,FIXQOS_BANK[n]_2 Setting"
newline
hexmask.quad.byte 0x00 16.--23. 1. "FIXQOS_BANK_n_1,FIXQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--15. 1. "FIXQOS_BANK_n_0,FIXQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "116" "117" "118" "119" "120" "121" "122" "123" "124" "125" "126" "127" "128" "129" "130" "131" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x1080)++0x07
line.quad 0x00 "QOSBW_FIX_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 53.--56. "Reserved_53,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 50.--52. "FIXQOS_BANK_n_5,FIXQOS_BANK[n]_5 Setting" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.byte 0x00 42.--49. 1. "FIXQOS_BANK_n_4,FIXQOS_BANK[n]_4 Setting"
newline
hexmask.quad.word 0x00 32.--41. 1. "FIXQOS_BANK_n_3,FIXQOS_BANK[n]_3 Setting"
newline
hexmask.quad.byte 0x00 24.--31. 1. "FIXQOS_BANK_n_2,FIXQOS_BANK[n]_2 Setting"
newline
hexmask.quad.byte 0x00 16.--23. 1. "FIXQOS_BANK_n_1,FIXQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--15. 1. "FIXQOS_BANK_n_0,FIXQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "132" "133" "134" "135" "136" "137" "138" "139" "140" "141" "142" "143" "144" "145" "146" "147" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x1100)++0x07
line.quad 0x00 "QOSBW_FIX_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 53.--56. "Reserved_53,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 50.--52. "FIXQOS_BANK_n_5,FIXQOS_BANK[n]_5 Setting" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.byte 0x00 42.--49. 1. "FIXQOS_BANK_n_4,FIXQOS_BANK[n]_4 Setting"
newline
hexmask.quad.word 0x00 32.--41. 1. "FIXQOS_BANK_n_3,FIXQOS_BANK[n]_3 Setting"
newline
hexmask.quad.byte 0x00 24.--31. 1. "FIXQOS_BANK_n_2,FIXQOS_BANK[n]_2 Setting"
newline
hexmask.quad.byte 0x00 16.--23. 1. "FIXQOS_BANK_n_1,FIXQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--15. 1. "FIXQOS_BANK_n_0,FIXQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "148" "149" "150" "151" "152" "153" "154" "155" "156" "157" "158" "159" "160" "161" "162" "163" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x1180)++0x07
line.quad 0x00 "QOSBW_FIX_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 53.--56. "Reserved_53,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 50.--52. "FIXQOS_BANK_n_5,FIXQOS_BANK[n]_5 Setting" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.byte 0x00 42.--49. 1. "FIXQOS_BANK_n_4,FIXQOS_BANK[n]_4 Setting"
newline
hexmask.quad.word 0x00 32.--41. 1. "FIXQOS_BANK_n_3,FIXQOS_BANK[n]_3 Setting"
newline
hexmask.quad.byte 0x00 24.--31. 1. "FIXQOS_BANK_n_2,FIXQOS_BANK[n]_2 Setting"
newline
hexmask.quad.byte 0x00 16.--23. 1. "FIXQOS_BANK_n_1,FIXQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--15. 1. "FIXQOS_BANK_n_0,FIXQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "164" "165" "166" "167" "168" "169" "170" "171" "172" "173" "174" "175" "176" "177" "178" "179" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x1200)++0x07
line.quad 0x00 "QOSBW_FIX_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 53.--56. "Reserved_53,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 50.--52. "FIXQOS_BANK_n_5,FIXQOS_BANK[n]_5 Setting" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.byte 0x00 42.--49. 1. "FIXQOS_BANK_n_4,FIXQOS_BANK[n]_4 Setting"
newline
hexmask.quad.word 0x00 32.--41. 1. "FIXQOS_BANK_n_3,FIXQOS_BANK[n]_3 Setting"
newline
hexmask.quad.byte 0x00 24.--31. 1. "FIXQOS_BANK_n_2,FIXQOS_BANK[n]_2 Setting"
newline
hexmask.quad.byte 0x00 16.--23. 1. "FIXQOS_BANK_n_1,FIXQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--15. 1. "FIXQOS_BANK_n_0,FIXQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "180" "181" "182" "183" "184" "185" "186" "187" "188" "189" "190" "191" "192" "193" "194" "195" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x1280)++0x07
line.quad 0x00 "QOSBW_FIX_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 53.--56. "Reserved_53,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 50.--52. "FIXQOS_BANK_n_5,FIXQOS_BANK[n]_5 Setting" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.byte 0x00 42.--49. 1. "FIXQOS_BANK_n_4,FIXQOS_BANK[n]_4 Setting"
newline
hexmask.quad.word 0x00 32.--41. 1. "FIXQOS_BANK_n_3,FIXQOS_BANK[n]_3 Setting"
newline
hexmask.quad.byte 0x00 24.--31. 1. "FIXQOS_BANK_n_2,FIXQOS_BANK[n]_2 Setting"
newline
hexmask.quad.byte 0x00 16.--23. 1. "FIXQOS_BANK_n_1,FIXQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--15. 1. "FIXQOS_BANK_n_0,FIXQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "196" "197" "198" "199" "1100" "1101" "1102" "1103" "1104" "1105" "1106" "1107" "1108" "1109" "1110" "1111" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x1300)++0x07
line.quad 0x00 "QOSBW_FIX_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 53.--56. "Reserved_53,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 50.--52. "FIXQOS_BANK_n_5,FIXQOS_BANK[n]_5 Setting" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.byte 0x00 42.--49. 1. "FIXQOS_BANK_n_4,FIXQOS_BANK[n]_4 Setting"
newline
hexmask.quad.word 0x00 32.--41. 1. "FIXQOS_BANK_n_3,FIXQOS_BANK[n]_3 Setting"
newline
hexmask.quad.byte 0x00 24.--31. 1. "FIXQOS_BANK_n_2,FIXQOS_BANK[n]_2 Setting"
newline
hexmask.quad.byte 0x00 16.--23. 1. "FIXQOS_BANK_n_1,FIXQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--15. 1. "FIXQOS_BANK_n_0,FIXQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "1112" "1113" "1114" "1115" "1116" "1117" "1118" "1119" "1120" "1121" "1122" "1123" "1124" "1125" "1126" "1127" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x1380)++0x07
line.quad 0x00 "QOSBW_FIX_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 53.--56. "Reserved_53,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 50.--52. "FIXQOS_BANK_n_5,FIXQOS_BANK[n]_5 Setting" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.byte 0x00 42.--49. 1. "FIXQOS_BANK_n_4,FIXQOS_BANK[n]_4 Setting"
newline
hexmask.quad.word 0x00 32.--41. 1. "FIXQOS_BANK_n_3,FIXQOS_BANK[n]_3 Setting"
newline
hexmask.quad.byte 0x00 24.--31. 1. "FIXQOS_BANK_n_2,FIXQOS_BANK[n]_2 Setting"
newline
hexmask.quad.byte 0x00 16.--23. 1. "FIXQOS_BANK_n_1,FIXQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--15. 1. "FIXQOS_BANK_n_0,FIXQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "1128" "1129" "1130" "1131" "1132" "1133" "1134" "1135" "1136" "1137" "1138" "1139" "1140" "1141" "1142" "1143" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x1400)++0x07
line.quad 0x00 "QOSBW_FIX_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 53.--56. "Reserved_53,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 50.--52. "FIXQOS_BANK_n_5,FIXQOS_BANK[n]_5 Setting" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.byte 0x00 42.--49. 1. "FIXQOS_BANK_n_4,FIXQOS_BANK[n]_4 Setting"
newline
hexmask.quad.word 0x00 32.--41. 1. "FIXQOS_BANK_n_3,FIXQOS_BANK[n]_3 Setting"
newline
hexmask.quad.byte 0x00 24.--31. 1. "FIXQOS_BANK_n_2,FIXQOS_BANK[n]_2 Setting"
newline
hexmask.quad.byte 0x00 16.--23. 1. "FIXQOS_BANK_n_1,FIXQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--15. 1. "FIXQOS_BANK_n_0,FIXQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "1144" "1145" "1146" "1147" "1148" "1149" "1150" "1151" "1152" "1153" "1154" "1155" "1156" "1157" "1158" "1159" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x1480)++0x07
line.quad 0x00 "QOSBW_FIX_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 53.--56. "Reserved_53,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 50.--52. "FIXQOS_BANK_n_5,FIXQOS_BANK[n]_5 Setting" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.byte 0x00 42.--49. 1. "FIXQOS_BANK_n_4,FIXQOS_BANK[n]_4 Setting"
newline
hexmask.quad.word 0x00 32.--41. 1. "FIXQOS_BANK_n_3,FIXQOS_BANK[n]_3 Setting"
newline
hexmask.quad.byte 0x00 24.--31. 1. "FIXQOS_BANK_n_2,FIXQOS_BANK[n]_2 Setting"
newline
hexmask.quad.byte 0x00 16.--23. 1. "FIXQOS_BANK_n_1,FIXQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--15. 1. "FIXQOS_BANK_n_0,FIXQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "1160" "1161" "1162" "1163" "1164" "1165" "1166" "1167" "1168" "1169" "1170" "1171" "1172" "1173" "1174" "1175" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x1500)++0x07
line.quad 0x00 "QOSBW_FIX_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 53.--56. "Reserved_53,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 50.--52. "FIXQOS_BANK_n_5,FIXQOS_BANK[n]_5 Setting" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.byte 0x00 42.--49. 1. "FIXQOS_BANK_n_4,FIXQOS_BANK[n]_4 Setting"
newline
hexmask.quad.word 0x00 32.--41. 1. "FIXQOS_BANK_n_3,FIXQOS_BANK[n]_3 Setting"
newline
hexmask.quad.byte 0x00 24.--31. 1. "FIXQOS_BANK_n_2,FIXQOS_BANK[n]_2 Setting"
newline
hexmask.quad.byte 0x00 16.--23. 1. "FIXQOS_BANK_n_1,FIXQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--15. 1. "FIXQOS_BANK_n_0,FIXQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "1176" "1177" "1178" "1179" "1180" "1181" "1182" "1183" "1184" "1185" "1186" "1187" "1188" "1189" "1190" "1191" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x1580)++0x07
line.quad 0x00 "QOSBW_FIX_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 53.--56. "Reserved_53,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 50.--52. "FIXQOS_BANK_n_5,FIXQOS_BANK[n]_5 Setting" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.byte 0x00 42.--49. 1. "FIXQOS_BANK_n_4,FIXQOS_BANK[n]_4 Setting"
newline
hexmask.quad.word 0x00 32.--41. 1. "FIXQOS_BANK_n_3,FIXQOS_BANK[n]_3 Setting"
newline
hexmask.quad.byte 0x00 24.--31. 1. "FIXQOS_BANK_n_2,FIXQOS_BANK[n]_2 Setting"
newline
hexmask.quad.byte 0x00 16.--23. 1. "FIXQOS_BANK_n_1,FIXQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--15. 1. "FIXQOS_BANK_n_0,FIXQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "1192" "1193" "1194" "1195" "1196" "1197" "1198" "1199" "1200" "1201" "1202" "1203" "1204" "1205" "1206" "1207" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x1600)++0x07
line.quad 0x00 "QOSBW_FIX_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 53.--56. "Reserved_53,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 50.--52. "FIXQOS_BANK_n_5,FIXQOS_BANK[n]_5 Setting" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.byte 0x00 42.--49. 1. "FIXQOS_BANK_n_4,FIXQOS_BANK[n]_4 Setting"
newline
hexmask.quad.word 0x00 32.--41. 1. "FIXQOS_BANK_n_3,FIXQOS_BANK[n]_3 Setting"
newline
hexmask.quad.byte 0x00 24.--31. 1. "FIXQOS_BANK_n_2,FIXQOS_BANK[n]_2 Setting"
newline
hexmask.quad.byte 0x00 16.--23. 1. "FIXQOS_BANK_n_1,FIXQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--15. 1. "FIXQOS_BANK_n_0,FIXQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "1208" "1209" "1210" "1211" "1212" "1213" "1214" "1215" "1216" "1217" "1218" "1219" "1220" "1221" "1222" "1223" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x1680)++0x07
line.quad 0x00 "QOSBW_FIX_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 53.--56. "Reserved_53,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 50.--52. "FIXQOS_BANK_n_5,FIXQOS_BANK[n]_5 Setting" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.byte 0x00 42.--49. 1. "FIXQOS_BANK_n_4,FIXQOS_BANK[n]_4 Setting"
newline
hexmask.quad.word 0x00 32.--41. 1. "FIXQOS_BANK_n_3,FIXQOS_BANK[n]_3 Setting"
newline
hexmask.quad.byte 0x00 24.--31. 1. "FIXQOS_BANK_n_2,FIXQOS_BANK[n]_2 Setting"
newline
hexmask.quad.byte 0x00 16.--23. 1. "FIXQOS_BANK_n_1,FIXQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--15. 1. "FIXQOS_BANK_n_0,FIXQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "1224" "1225" "1226" "1227" "1228" "1229" "1230" "1231" "1232" "1233" "1234" "1235" "1236" "1237" "1238" "1239" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x1700)++0x07
line.quad 0x00 "QOSBW_FIX_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 53.--56. "Reserved_53,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 50.--52. "FIXQOS_BANK_n_5,FIXQOS_BANK[n]_5 Setting" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.byte 0x00 42.--49. 1. "FIXQOS_BANK_n_4,FIXQOS_BANK[n]_4 Setting"
newline
hexmask.quad.word 0x00 32.--41. 1. "FIXQOS_BANK_n_3,FIXQOS_BANK[n]_3 Setting"
newline
hexmask.quad.byte 0x00 24.--31. 1. "FIXQOS_BANK_n_2,FIXQOS_BANK[n]_2 Setting"
newline
hexmask.quad.byte 0x00 16.--23. 1. "FIXQOS_BANK_n_1,FIXQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--15. 1. "FIXQOS_BANK_n_0,FIXQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "1240" "1241" "1242" "1243" "1244" "1245" "1246" "1247" "1248" "1249" "1250" "1251" "1252" "1253" "1254" "1255" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x1780)++0x07
line.quad 0x00 "QOSBW_FIX_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 53.--56. "Reserved_53,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 50.--52. "FIXQOS_BANK_n_5,FIXQOS_BANK[n]_5 Setting" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.byte 0x00 42.--49. 1. "FIXQOS_BANK_n_4,FIXQOS_BANK[n]_4 Setting"
newline
hexmask.quad.word 0x00 32.--41. 1. "FIXQOS_BANK_n_3,FIXQOS_BANK[n]_3 Setting"
newline
hexmask.quad.byte 0x00 24.--31. 1. "FIXQOS_BANK_n_2,FIXQOS_BANK[n]_2 Setting"
newline
hexmask.quad.byte 0x00 16.--23. 1. "FIXQOS_BANK_n_1,FIXQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--15. 1. "FIXQOS_BANK_n_0,FIXQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "1256" "1257" "1258" "1259" "1260" "1261" "1262" "1263" "1264" "1265" "1266" "1267" "1268" "1269" "1270" "1271" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x1800)++0x07
line.quad 0x00 "QOSBW_FIX_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 53.--56. "Reserved_53,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 50.--52. "FIXQOS_BANK_n_5,FIXQOS_BANK[n]_5 Setting" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.byte 0x00 42.--49. 1. "FIXQOS_BANK_n_4,FIXQOS_BANK[n]_4 Setting"
newline
hexmask.quad.word 0x00 32.--41. 1. "FIXQOS_BANK_n_3,FIXQOS_BANK[n]_3 Setting"
newline
hexmask.quad.byte 0x00 24.--31. 1. "FIXQOS_BANK_n_2,FIXQOS_BANK[n]_2 Setting"
newline
hexmask.quad.byte 0x00 16.--23. 1. "FIXQOS_BANK_n_1,FIXQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--15. 1. "FIXQOS_BANK_n_0,FIXQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "1272" "1273" "1274" "1275" "1276" "1277" "1278" "1279" "1280" "1281" "1282" "1283" "1284" "1285" "1286" "1287" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x1880)++0x07
line.quad 0x00 "QOSBW_FIX_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 53.--56. "Reserved_53,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 50.--52. "FIXQOS_BANK_n_5,FIXQOS_BANK[n]_5 Setting" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.byte 0x00 42.--49. 1. "FIXQOS_BANK_n_4,FIXQOS_BANK[n]_4 Setting"
newline
hexmask.quad.word 0x00 32.--41. 1. "FIXQOS_BANK_n_3,FIXQOS_BANK[n]_3 Setting"
newline
hexmask.quad.byte 0x00 24.--31. 1. "FIXQOS_BANK_n_2,FIXQOS_BANK[n]_2 Setting"
newline
hexmask.quad.byte 0x00 16.--23. 1. "FIXQOS_BANK_n_1,FIXQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--15. 1. "FIXQOS_BANK_n_0,FIXQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "1288" "1289" "1290" "1291" "1292" "1293" "1294" "1295" "1296" "1297" "1298" "1299" "1300" "1301" "1302" "1303" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x1900)++0x07
line.quad 0x00 "QOSBW_FIX_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 53.--56. "Reserved_53,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 50.--52. "FIXQOS_BANK_n_5,FIXQOS_BANK[n]_5 Setting" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.byte 0x00 42.--49. 1. "FIXQOS_BANK_n_4,FIXQOS_BANK[n]_4 Setting"
newline
hexmask.quad.word 0x00 32.--41. 1. "FIXQOS_BANK_n_3,FIXQOS_BANK[n]_3 Setting"
newline
hexmask.quad.byte 0x00 24.--31. 1. "FIXQOS_BANK_n_2,FIXQOS_BANK[n]_2 Setting"
newline
hexmask.quad.byte 0x00 16.--23. 1. "FIXQOS_BANK_n_1,FIXQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--15. 1. "FIXQOS_BANK_n_0,FIXQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "1304" "1305" "1306" "1307" "1308" "1309" "1310" "1311" "1312" "1313" "1314" "1315" "1316" "1317" "1318" "1319" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x1980)++0x07
line.quad 0x00 "QOSBW_FIX_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 53.--56. "Reserved_53,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 50.--52. "FIXQOS_BANK_n_5,FIXQOS_BANK[n]_5 Setting" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.byte 0x00 42.--49. 1. "FIXQOS_BANK_n_4,FIXQOS_BANK[n]_4 Setting"
newline
hexmask.quad.word 0x00 32.--41. 1. "FIXQOS_BANK_n_3,FIXQOS_BANK[n]_3 Setting"
newline
hexmask.quad.byte 0x00 24.--31. 1. "FIXQOS_BANK_n_2,FIXQOS_BANK[n]_2 Setting"
newline
hexmask.quad.byte 0x00 16.--23. 1. "FIXQOS_BANK_n_1,FIXQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--15. 1. "FIXQOS_BANK_n_0,FIXQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "1320" "1321" "1322" "1323" "1324" "1325" "1326" "1327" "1328" "1329" "1330" "1331" "1332" "1333" "1334" "1335" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x1A00)++0x07
line.quad 0x00 "QOSBW_FIX_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 53.--56. "Reserved_53,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 50.--52. "FIXQOS_BANK_n_5,FIXQOS_BANK[n]_5 Setting" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.byte 0x00 42.--49. 1. "FIXQOS_BANK_n_4,FIXQOS_BANK[n]_4 Setting"
newline
hexmask.quad.word 0x00 32.--41. 1. "FIXQOS_BANK_n_3,FIXQOS_BANK[n]_3 Setting"
newline
hexmask.quad.byte 0x00 24.--31. 1. "FIXQOS_BANK_n_2,FIXQOS_BANK[n]_2 Setting"
newline
hexmask.quad.byte 0x00 16.--23. 1. "FIXQOS_BANK_n_1,FIXQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--15. 1. "FIXQOS_BANK_n_0,FIXQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "1336" "1337" "1338" "1339" "1340" "1341" "1342" "1343" "1344" "1345" "1346" "1347" "1348" "1349" "1350" "1351" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x1A80)++0x07
line.quad 0x00 "QOSBW_FIX_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 53.--56. "Reserved_53,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 50.--52. "FIXQOS_BANK_n_5,FIXQOS_BANK[n]_5 Setting" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.byte 0x00 42.--49. 1. "FIXQOS_BANK_n_4,FIXQOS_BANK[n]_4 Setting"
newline
hexmask.quad.word 0x00 32.--41. 1. "FIXQOS_BANK_n_3,FIXQOS_BANK[n]_3 Setting"
newline
hexmask.quad.byte 0x00 24.--31. 1. "FIXQOS_BANK_n_2,FIXQOS_BANK[n]_2 Setting"
newline
hexmask.quad.byte 0x00 16.--23. 1. "FIXQOS_BANK_n_1,FIXQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--15. 1. "FIXQOS_BANK_n_0,FIXQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "1352" "1353" "1354" "1355" "1356" "1357" "1358" "1359" "1360" "1361" "1362" "1363" "1364" "1365" "1366" "1367" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x1B00)++0x07
line.quad 0x00 "QOSBW_FIX_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 53.--56. "Reserved_53,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 50.--52. "FIXQOS_BANK_n_5,FIXQOS_BANK[n]_5 Setting" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.byte 0x00 42.--49. 1. "FIXQOS_BANK_n_4,FIXQOS_BANK[n]_4 Setting"
newline
hexmask.quad.word 0x00 32.--41. 1. "FIXQOS_BANK_n_3,FIXQOS_BANK[n]_3 Setting"
newline
hexmask.quad.byte 0x00 24.--31. 1. "FIXQOS_BANK_n_2,FIXQOS_BANK[n]_2 Setting"
newline
hexmask.quad.byte 0x00 16.--23. 1. "FIXQOS_BANK_n_1,FIXQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--15. 1. "FIXQOS_BANK_n_0,FIXQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "1368" "1369" "1370" "1371" "1372" "1373" "1374" "1375" "1376" "1377" "1378" "1379" "1380" "1381" "1382" "1383" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x1B80)++0x07
line.quad 0x00 "QOSBW_FIX_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 53.--56. "Reserved_53,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 50.--52. "FIXQOS_BANK_n_5,FIXQOS_BANK[n]_5 Setting" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.byte 0x00 42.--49. 1. "FIXQOS_BANK_n_4,FIXQOS_BANK[n]_4 Setting"
newline
hexmask.quad.word 0x00 32.--41. 1. "FIXQOS_BANK_n_3,FIXQOS_BANK[n]_3 Setting"
newline
hexmask.quad.byte 0x00 24.--31. 1. "FIXQOS_BANK_n_2,FIXQOS_BANK[n]_2 Setting"
newline
hexmask.quad.byte 0x00 16.--23. 1. "FIXQOS_BANK_n_1,FIXQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--15. 1. "FIXQOS_BANK_n_0,FIXQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "1384" "1385" "1386" "1387" "1388" "1389" "1390" "1391" "1392" "1393" "1394" "1395" "1396" "1397" "1398" "1399" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x1C00)++0x07
line.quad 0x00 "QOSBW_FIX_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 53.--56. "Reserved_53,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 50.--52. "FIXQOS_BANK_n_5,FIXQOS_BANK[n]_5 Setting" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.byte 0x00 42.--49. 1. "FIXQOS_BANK_n_4,FIXQOS_BANK[n]_4 Setting"
newline
hexmask.quad.word 0x00 32.--41. 1. "FIXQOS_BANK_n_3,FIXQOS_BANK[n]_3 Setting"
newline
hexmask.quad.byte 0x00 24.--31. 1. "FIXQOS_BANK_n_2,FIXQOS_BANK[n]_2 Setting"
newline
hexmask.quad.byte 0x00 16.--23. 1. "FIXQOS_BANK_n_1,FIXQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--15. 1. "FIXQOS_BANK_n_0,FIXQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "1400" "1401" "1402" "1403" "1404" "1405" "1406" "1407" "1408" "1409" "1410" "1411" "1412" "1413" "1414" "1415" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x1C80)++0x07
line.quad 0x00 "QOSBW_FIX_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 53.--56. "Reserved_53,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 50.--52. "FIXQOS_BANK_n_5,FIXQOS_BANK[n]_5 Setting" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.byte 0x00 42.--49. 1. "FIXQOS_BANK_n_4,FIXQOS_BANK[n]_4 Setting"
newline
hexmask.quad.word 0x00 32.--41. 1. "FIXQOS_BANK_n_3,FIXQOS_BANK[n]_3 Setting"
newline
hexmask.quad.byte 0x00 24.--31. 1. "FIXQOS_BANK_n_2,FIXQOS_BANK[n]_2 Setting"
newline
hexmask.quad.byte 0x00 16.--23. 1. "FIXQOS_BANK_n_1,FIXQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--15. 1. "FIXQOS_BANK_n_0,FIXQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "1416" "1417" "1418" "1419" "1420" "1421" "1422" "1423" "1424" "1425" "1426" "1427" "1428" "1429" "1430" "1431" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x1D00)++0x07
line.quad 0x00 "QOSBW_FIX_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 53.--56. "Reserved_53,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 50.--52. "FIXQOS_BANK_n_5,FIXQOS_BANK[n]_5 Setting" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.byte 0x00 42.--49. 1. "FIXQOS_BANK_n_4,FIXQOS_BANK[n]_4 Setting"
newline
hexmask.quad.word 0x00 32.--41. 1. "FIXQOS_BANK_n_3,FIXQOS_BANK[n]_3 Setting"
newline
hexmask.quad.byte 0x00 24.--31. 1. "FIXQOS_BANK_n_2,FIXQOS_BANK[n]_2 Setting"
newline
hexmask.quad.byte 0x00 16.--23. 1. "FIXQOS_BANK_n_1,FIXQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--15. 1. "FIXQOS_BANK_n_0,FIXQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "1432" "1433" "1434" "1435" "1436" "1437" "1438" "1439" "1440" "1441" "1442" "1443" "1444" "1445" "1446" "1447" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x1D80)++0x07
line.quad 0x00 "QOSBW_FIX_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 53.--56. "Reserved_53,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 50.--52. "FIXQOS_BANK_n_5,FIXQOS_BANK[n]_5 Setting" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.byte 0x00 42.--49. 1. "FIXQOS_BANK_n_4,FIXQOS_BANK[n]_4 Setting"
newline
hexmask.quad.word 0x00 32.--41. 1. "FIXQOS_BANK_n_3,FIXQOS_BANK[n]_3 Setting"
newline
hexmask.quad.byte 0x00 24.--31. 1. "FIXQOS_BANK_n_2,FIXQOS_BANK[n]_2 Setting"
newline
hexmask.quad.byte 0x00 16.--23. 1. "FIXQOS_BANK_n_1,FIXQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--15. 1. "FIXQOS_BANK_n_0,FIXQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "1448" "1449" "1450" "1451" "1452" "1453" "1454" "1455" "1456" "1457" "1458" "1459" "1460" "1461" "1462" "1463" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x1E00)++0x07
line.quad 0x00 "QOSBW_FIX_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 53.--56. "Reserved_53,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 50.--52. "FIXQOS_BANK_n_5,FIXQOS_BANK[n]_5 Setting" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.byte 0x00 42.--49. 1. "FIXQOS_BANK_n_4,FIXQOS_BANK[n]_4 Setting"
newline
hexmask.quad.word 0x00 32.--41. 1. "FIXQOS_BANK_n_3,FIXQOS_BANK[n]_3 Setting"
newline
hexmask.quad.byte 0x00 24.--31. 1. "FIXQOS_BANK_n_2,FIXQOS_BANK[n]_2 Setting"
newline
hexmask.quad.byte 0x00 16.--23. 1. "FIXQOS_BANK_n_1,FIXQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--15. 1. "FIXQOS_BANK_n_0,FIXQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "1464" "1465" "1466" "1467" "1468" "1469" "1470" "1471" "1472" "1473" "1474" "1475" "1476" "1477" "1478" "1479" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x1E80)++0x07
line.quad 0x00 "QOSBW_FIX_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 53.--56. "Reserved_53,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 50.--52. "FIXQOS_BANK_n_5,FIXQOS_BANK[n]_5 Setting" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.byte 0x00 42.--49. 1. "FIXQOS_BANK_n_4,FIXQOS_BANK[n]_4 Setting"
newline
hexmask.quad.word 0x00 32.--41. 1. "FIXQOS_BANK_n_3,FIXQOS_BANK[n]_3 Setting"
newline
hexmask.quad.byte 0x00 24.--31. 1. "FIXQOS_BANK_n_2,FIXQOS_BANK[n]_2 Setting"
newline
hexmask.quad.byte 0x00 16.--23. 1. "FIXQOS_BANK_n_1,FIXQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--15. 1. "FIXQOS_BANK_n_0,FIXQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "1480" "1481" "1482" "1483" "1484" "1485" "1486" "1487" "1488" "1489" "1490" "1491" "1492" "1493" "1494" "1495" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x1F00)++0x07
line.quad 0x00 "QOSBW_FIX_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 53.--56. "Reserved_53,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 50.--52. "FIXQOS_BANK_n_5,FIXQOS_BANK[n]_5 Setting" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.byte 0x00 42.--49. 1. "FIXQOS_BANK_n_4,FIXQOS_BANK[n]_4 Setting"
newline
hexmask.quad.word 0x00 32.--41. 1. "FIXQOS_BANK_n_3,FIXQOS_BANK[n]_3 Setting"
newline
hexmask.quad.byte 0x00 24.--31. 1. "FIXQOS_BANK_n_2,FIXQOS_BANK[n]_2 Setting"
newline
hexmask.quad.byte 0x00 16.--23. 1. "FIXQOS_BANK_n_1,FIXQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--15. 1. "FIXQOS_BANK_n_0,FIXQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "1496" "1497" "1498" "1499" "1500" "1501" "1502" "1503" "1504" "1505" "1506" "1507" "1508" "1509" "1510" "1511" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x1F80)++0x07
line.quad 0x00 "QOSBW_FIX_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 53.--56. "Reserved_53,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 50.--52. "FIXQOS_BANK_n_5,FIXQOS_BANK[n]_5 Setting" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.byte 0x00 42.--49. 1. "FIXQOS_BANK_n_4,FIXQOS_BANK[n]_4 Setting"
newline
hexmask.quad.word 0x00 32.--41. 1. "FIXQOS_BANK_n_3,FIXQOS_BANK[n]_3 Setting"
newline
hexmask.quad.byte 0x00 24.--31. 1. "FIXQOS_BANK_n_2,FIXQOS_BANK[n]_2 Setting"
newline
hexmask.quad.byte 0x00 16.--23. 1. "FIXQOS_BANK_n_1,FIXQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--15. 1. "FIXQOS_BANK_n_0,FIXQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "00" "01" "02" "03" "04" "05" "06" "07" "08" "09" "010" "011" "012" "013" "014" "015" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x2000)++0x07
line.quad 0x00 "QOSBW_BE_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 54.--56. "Reserved_54,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 52.--53. "BEQOS_BANK_n_5,BEQOS_BANK[n]_5 Setting" "0,1,2,3"
newline
bitfld.quad 0x00 48.--51. "BEQOS_BANK_n_4,BEQOS_BANK[n]_4 Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 44.--47. "Reserved_44,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 36.--43. 1. "BEQOS_BANK_n_3,BEQOS_BANK[n]_3 Setting"
newline
hexmask.quad.word 0x00 20.--35. 1. "BEQOS_BANK_n_2,BEQOS_BANK[n]_2 Setting"
newline
hexmask.quad.word 0x00 10.--19. 1. "BEQOS_BANK_n_1,BEQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--9. 1. "BEQOS_BANK_n_0,BEQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "016" "017" "018" "019" "020" "021" "022" "023" "024" "025" "026" "027" "028" "029" "030" "031" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x2080)++0x07
line.quad 0x00 "QOSBW_BE_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 54.--56. "Reserved_54,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 52.--53. "BEQOS_BANK_n_5,BEQOS_BANK[n]_5 Setting" "0,1,2,3"
newline
bitfld.quad 0x00 48.--51. "BEQOS_BANK_n_4,BEQOS_BANK[n]_4 Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 44.--47. "Reserved_44,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 36.--43. 1. "BEQOS_BANK_n_3,BEQOS_BANK[n]_3 Setting"
newline
hexmask.quad.word 0x00 20.--35. 1. "BEQOS_BANK_n_2,BEQOS_BANK[n]_2 Setting"
newline
hexmask.quad.word 0x00 10.--19. 1. "BEQOS_BANK_n_1,BEQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--9. 1. "BEQOS_BANK_n_0,BEQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "032" "033" "034" "035" "036" "037" "038" "039" "040" "041" "042" "043" "044" "045" "046" "047" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x2100)++0x07
line.quad 0x00 "QOSBW_BE_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 54.--56. "Reserved_54,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 52.--53. "BEQOS_BANK_n_5,BEQOS_BANK[n]_5 Setting" "0,1,2,3"
newline
bitfld.quad 0x00 48.--51. "BEQOS_BANK_n_4,BEQOS_BANK[n]_4 Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 44.--47. "Reserved_44,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 36.--43. 1. "BEQOS_BANK_n_3,BEQOS_BANK[n]_3 Setting"
newline
hexmask.quad.word 0x00 20.--35. 1. "BEQOS_BANK_n_2,BEQOS_BANK[n]_2 Setting"
newline
hexmask.quad.word 0x00 10.--19. 1. "BEQOS_BANK_n_1,BEQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--9. 1. "BEQOS_BANK_n_0,BEQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "048" "049" "050" "051" "052" "053" "054" "055" "056" "057" "058" "059" "060" "061" "062" "063" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x2180)++0x07
line.quad 0x00 "QOSBW_BE_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 54.--56. "Reserved_54,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 52.--53. "BEQOS_BANK_n_5,BEQOS_BANK[n]_5 Setting" "0,1,2,3"
newline
bitfld.quad 0x00 48.--51. "BEQOS_BANK_n_4,BEQOS_BANK[n]_4 Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 44.--47. "Reserved_44,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 36.--43. 1. "BEQOS_BANK_n_3,BEQOS_BANK[n]_3 Setting"
newline
hexmask.quad.word 0x00 20.--35. 1. "BEQOS_BANK_n_2,BEQOS_BANK[n]_2 Setting"
newline
hexmask.quad.word 0x00 10.--19. 1. "BEQOS_BANK_n_1,BEQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--9. 1. "BEQOS_BANK_n_0,BEQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "064" "065" "066" "067" "068" "069" "070" "071" "072" "073" "074" "075" "076" "077" "078" "079" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x2200)++0x07
line.quad 0x00 "QOSBW_BE_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 54.--56. "Reserved_54,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 52.--53. "BEQOS_BANK_n_5,BEQOS_BANK[n]_5 Setting" "0,1,2,3"
newline
bitfld.quad 0x00 48.--51. "BEQOS_BANK_n_4,BEQOS_BANK[n]_4 Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 44.--47. "Reserved_44,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 36.--43. 1. "BEQOS_BANK_n_3,BEQOS_BANK[n]_3 Setting"
newline
hexmask.quad.word 0x00 20.--35. 1. "BEQOS_BANK_n_2,BEQOS_BANK[n]_2 Setting"
newline
hexmask.quad.word 0x00 10.--19. 1. "BEQOS_BANK_n_1,BEQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--9. 1. "BEQOS_BANK_n_0,BEQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "080" "081" "082" "083" "084" "085" "086" "087" "088" "089" "090" "091" "092" "093" "094" "095" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x2280)++0x07
line.quad 0x00 "QOSBW_BE_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 54.--56. "Reserved_54,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 52.--53. "BEQOS_BANK_n_5,BEQOS_BANK[n]_5 Setting" "0,1,2,3"
newline
bitfld.quad 0x00 48.--51. "BEQOS_BANK_n_4,BEQOS_BANK[n]_4 Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 44.--47. "Reserved_44,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 36.--43. 1. "BEQOS_BANK_n_3,BEQOS_BANK[n]_3 Setting"
newline
hexmask.quad.word 0x00 20.--35. 1. "BEQOS_BANK_n_2,BEQOS_BANK[n]_2 Setting"
newline
hexmask.quad.word 0x00 10.--19. 1. "BEQOS_BANK_n_1,BEQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--9. 1. "BEQOS_BANK_n_0,BEQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "096" "097" "098" "099" "0100" "0101" "0102" "0103" "0104" "0105" "0106" "0107" "0108" "0109" "0110" "0111" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x2300)++0x07
line.quad 0x00 "QOSBW_BE_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 54.--56. "Reserved_54,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 52.--53. "BEQOS_BANK_n_5,BEQOS_BANK[n]_5 Setting" "0,1,2,3"
newline
bitfld.quad 0x00 48.--51. "BEQOS_BANK_n_4,BEQOS_BANK[n]_4 Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 44.--47. "Reserved_44,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 36.--43. 1. "BEQOS_BANK_n_3,BEQOS_BANK[n]_3 Setting"
newline
hexmask.quad.word 0x00 20.--35. 1. "BEQOS_BANK_n_2,BEQOS_BANK[n]_2 Setting"
newline
hexmask.quad.word 0x00 10.--19. 1. "BEQOS_BANK_n_1,BEQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--9. 1. "BEQOS_BANK_n_0,BEQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "0112" "0113" "0114" "0115" "0116" "0117" "0118" "0119" "0120" "0121" "0122" "0123" "0124" "0125" "0126" "0127" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x2380)++0x07
line.quad 0x00 "QOSBW_BE_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 54.--56. "Reserved_54,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 52.--53. "BEQOS_BANK_n_5,BEQOS_BANK[n]_5 Setting" "0,1,2,3"
newline
bitfld.quad 0x00 48.--51. "BEQOS_BANK_n_4,BEQOS_BANK[n]_4 Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 44.--47. "Reserved_44,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 36.--43. 1. "BEQOS_BANK_n_3,BEQOS_BANK[n]_3 Setting"
newline
hexmask.quad.word 0x00 20.--35. 1. "BEQOS_BANK_n_2,BEQOS_BANK[n]_2 Setting"
newline
hexmask.quad.word 0x00 10.--19. 1. "BEQOS_BANK_n_1,BEQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--9. 1. "BEQOS_BANK_n_0,BEQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "0128" "0129" "0130" "0131" "0132" "0133" "0134" "0135" "0136" "0137" "0138" "0139" "0140" "0141" "0142" "0143" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x2400)++0x07
line.quad 0x00 "QOSBW_BE_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 54.--56. "Reserved_54,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 52.--53. "BEQOS_BANK_n_5,BEQOS_BANK[n]_5 Setting" "0,1,2,3"
newline
bitfld.quad 0x00 48.--51. "BEQOS_BANK_n_4,BEQOS_BANK[n]_4 Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 44.--47. "Reserved_44,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 36.--43. 1. "BEQOS_BANK_n_3,BEQOS_BANK[n]_3 Setting"
newline
hexmask.quad.word 0x00 20.--35. 1. "BEQOS_BANK_n_2,BEQOS_BANK[n]_2 Setting"
newline
hexmask.quad.word 0x00 10.--19. 1. "BEQOS_BANK_n_1,BEQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--9. 1. "BEQOS_BANK_n_0,BEQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "0144" "0145" "0146" "0147" "0148" "0149" "0150" "0151" "0152" "0153" "0154" "0155" "0156" "0157" "0158" "0159" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x2480)++0x07
line.quad 0x00 "QOSBW_BE_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 54.--56. "Reserved_54,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 52.--53. "BEQOS_BANK_n_5,BEQOS_BANK[n]_5 Setting" "0,1,2,3"
newline
bitfld.quad 0x00 48.--51. "BEQOS_BANK_n_4,BEQOS_BANK[n]_4 Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 44.--47. "Reserved_44,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 36.--43. 1. "BEQOS_BANK_n_3,BEQOS_BANK[n]_3 Setting"
newline
hexmask.quad.word 0x00 20.--35. 1. "BEQOS_BANK_n_2,BEQOS_BANK[n]_2 Setting"
newline
hexmask.quad.word 0x00 10.--19. 1. "BEQOS_BANK_n_1,BEQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--9. 1. "BEQOS_BANK_n_0,BEQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "0160" "0161" "0162" "0163" "0164" "0165" "0166" "0167" "0168" "0169" "0170" "0171" "0172" "0173" "0174" "0175" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x2500)++0x07
line.quad 0x00 "QOSBW_BE_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 54.--56. "Reserved_54,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 52.--53. "BEQOS_BANK_n_5,BEQOS_BANK[n]_5 Setting" "0,1,2,3"
newline
bitfld.quad 0x00 48.--51. "BEQOS_BANK_n_4,BEQOS_BANK[n]_4 Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 44.--47. "Reserved_44,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 36.--43. 1. "BEQOS_BANK_n_3,BEQOS_BANK[n]_3 Setting"
newline
hexmask.quad.word 0x00 20.--35. 1. "BEQOS_BANK_n_2,BEQOS_BANK[n]_2 Setting"
newline
hexmask.quad.word 0x00 10.--19. 1. "BEQOS_BANK_n_1,BEQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--9. 1. "BEQOS_BANK_n_0,BEQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "0176" "0177" "0178" "0179" "0180" "0181" "0182" "0183" "0184" "0185" "0186" "0187" "0188" "0189" "0190" "0191" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x2580)++0x07
line.quad 0x00 "QOSBW_BE_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 54.--56. "Reserved_54,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 52.--53. "BEQOS_BANK_n_5,BEQOS_BANK[n]_5 Setting" "0,1,2,3"
newline
bitfld.quad 0x00 48.--51. "BEQOS_BANK_n_4,BEQOS_BANK[n]_4 Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 44.--47. "Reserved_44,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 36.--43. 1. "BEQOS_BANK_n_3,BEQOS_BANK[n]_3 Setting"
newline
hexmask.quad.word 0x00 20.--35. 1. "BEQOS_BANK_n_2,BEQOS_BANK[n]_2 Setting"
newline
hexmask.quad.word 0x00 10.--19. 1. "BEQOS_BANK_n_1,BEQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--9. 1. "BEQOS_BANK_n_0,BEQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "0192" "0193" "0194" "0195" "0196" "0197" "0198" "0199" "0200" "0201" "0202" "0203" "0204" "0205" "0206" "0207" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x2600)++0x07
line.quad 0x00 "QOSBW_BE_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 54.--56. "Reserved_54,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 52.--53. "BEQOS_BANK_n_5,BEQOS_BANK[n]_5 Setting" "0,1,2,3"
newline
bitfld.quad 0x00 48.--51. "BEQOS_BANK_n_4,BEQOS_BANK[n]_4 Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 44.--47. "Reserved_44,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 36.--43. 1. "BEQOS_BANK_n_3,BEQOS_BANK[n]_3 Setting"
newline
hexmask.quad.word 0x00 20.--35. 1. "BEQOS_BANK_n_2,BEQOS_BANK[n]_2 Setting"
newline
hexmask.quad.word 0x00 10.--19. 1. "BEQOS_BANK_n_1,BEQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--9. 1. "BEQOS_BANK_n_0,BEQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "0208" "0209" "0210" "0211" "0212" "0213" "0214" "0215" "0216" "0217" "0218" "0219" "0220" "0221" "0222" "0223" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x2680)++0x07
line.quad 0x00 "QOSBW_BE_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 54.--56. "Reserved_54,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 52.--53. "BEQOS_BANK_n_5,BEQOS_BANK[n]_5 Setting" "0,1,2,3"
newline
bitfld.quad 0x00 48.--51. "BEQOS_BANK_n_4,BEQOS_BANK[n]_4 Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 44.--47. "Reserved_44,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 36.--43. 1. "BEQOS_BANK_n_3,BEQOS_BANK[n]_3 Setting"
newline
hexmask.quad.word 0x00 20.--35. 1. "BEQOS_BANK_n_2,BEQOS_BANK[n]_2 Setting"
newline
hexmask.quad.word 0x00 10.--19. 1. "BEQOS_BANK_n_1,BEQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--9. 1. "BEQOS_BANK_n_0,BEQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "0224" "0225" "0226" "0227" "0228" "0229" "0230" "0231" "0232" "0233" "0234" "0235" "0236" "0237" "0238" "0239" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x2700)++0x07
line.quad 0x00 "QOSBW_BE_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 54.--56. "Reserved_54,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 52.--53. "BEQOS_BANK_n_5,BEQOS_BANK[n]_5 Setting" "0,1,2,3"
newline
bitfld.quad 0x00 48.--51. "BEQOS_BANK_n_4,BEQOS_BANK[n]_4 Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 44.--47. "Reserved_44,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 36.--43. 1. "BEQOS_BANK_n_3,BEQOS_BANK[n]_3 Setting"
newline
hexmask.quad.word 0x00 20.--35. 1. "BEQOS_BANK_n_2,BEQOS_BANK[n]_2 Setting"
newline
hexmask.quad.word 0x00 10.--19. 1. "BEQOS_BANK_n_1,BEQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--9. 1. "BEQOS_BANK_n_0,BEQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "0240" "0241" "0242" "0243" "0244" "0245" "0246" "0247" "0248" "0249" "0250" "0251" "0252" "0253" "0254" "0255" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x2780)++0x07
line.quad 0x00 "QOSBW_BE_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 54.--56. "Reserved_54,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 52.--53. "BEQOS_BANK_n_5,BEQOS_BANK[n]_5 Setting" "0,1,2,3"
newline
bitfld.quad 0x00 48.--51. "BEQOS_BANK_n_4,BEQOS_BANK[n]_4 Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 44.--47. "Reserved_44,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 36.--43. 1. "BEQOS_BANK_n_3,BEQOS_BANK[n]_3 Setting"
newline
hexmask.quad.word 0x00 20.--35. 1. "BEQOS_BANK_n_2,BEQOS_BANK[n]_2 Setting"
newline
hexmask.quad.word 0x00 10.--19. 1. "BEQOS_BANK_n_1,BEQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--9. 1. "BEQOS_BANK_n_0,BEQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "0256" "0257" "0258" "0259" "0260" "0261" "0262" "0263" "0264" "0265" "0266" "0267" "0268" "0269" "0270" "0271" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x2800)++0x07
line.quad 0x00 "QOSBW_BE_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 54.--56. "Reserved_54,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 52.--53. "BEQOS_BANK_n_5,BEQOS_BANK[n]_5 Setting" "0,1,2,3"
newline
bitfld.quad 0x00 48.--51. "BEQOS_BANK_n_4,BEQOS_BANK[n]_4 Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 44.--47. "Reserved_44,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 36.--43. 1. "BEQOS_BANK_n_3,BEQOS_BANK[n]_3 Setting"
newline
hexmask.quad.word 0x00 20.--35. 1. "BEQOS_BANK_n_2,BEQOS_BANK[n]_2 Setting"
newline
hexmask.quad.word 0x00 10.--19. 1. "BEQOS_BANK_n_1,BEQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--9. 1. "BEQOS_BANK_n_0,BEQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "0272" "0273" "0274" "0275" "0276" "0277" "0278" "0279" "0280" "0281" "0282" "0283" "0284" "0285" "0286" "0287" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x2880)++0x07
line.quad 0x00 "QOSBW_BE_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 54.--56. "Reserved_54,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 52.--53. "BEQOS_BANK_n_5,BEQOS_BANK[n]_5 Setting" "0,1,2,3"
newline
bitfld.quad 0x00 48.--51. "BEQOS_BANK_n_4,BEQOS_BANK[n]_4 Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 44.--47. "Reserved_44,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 36.--43. 1. "BEQOS_BANK_n_3,BEQOS_BANK[n]_3 Setting"
newline
hexmask.quad.word 0x00 20.--35. 1. "BEQOS_BANK_n_2,BEQOS_BANK[n]_2 Setting"
newline
hexmask.quad.word 0x00 10.--19. 1. "BEQOS_BANK_n_1,BEQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--9. 1. "BEQOS_BANK_n_0,BEQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "0288" "0289" "0290" "0291" "0292" "0293" "0294" "0295" "0296" "0297" "0298" "0299" "0300" "0301" "0302" "0303" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x2900)++0x07
line.quad 0x00 "QOSBW_BE_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 54.--56. "Reserved_54,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 52.--53. "BEQOS_BANK_n_5,BEQOS_BANK[n]_5 Setting" "0,1,2,3"
newline
bitfld.quad 0x00 48.--51. "BEQOS_BANK_n_4,BEQOS_BANK[n]_4 Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 44.--47. "Reserved_44,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 36.--43. 1. "BEQOS_BANK_n_3,BEQOS_BANK[n]_3 Setting"
newline
hexmask.quad.word 0x00 20.--35. 1. "BEQOS_BANK_n_2,BEQOS_BANK[n]_2 Setting"
newline
hexmask.quad.word 0x00 10.--19. 1. "BEQOS_BANK_n_1,BEQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--9. 1. "BEQOS_BANK_n_0,BEQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "0304" "0305" "0306" "0307" "0308" "0309" "0310" "0311" "0312" "0313" "0314" "0315" "0316" "0317" "0318" "0319" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x2980)++0x07
line.quad 0x00 "QOSBW_BE_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 54.--56. "Reserved_54,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 52.--53. "BEQOS_BANK_n_5,BEQOS_BANK[n]_5 Setting" "0,1,2,3"
newline
bitfld.quad 0x00 48.--51. "BEQOS_BANK_n_4,BEQOS_BANK[n]_4 Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 44.--47. "Reserved_44,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 36.--43. 1. "BEQOS_BANK_n_3,BEQOS_BANK[n]_3 Setting"
newline
hexmask.quad.word 0x00 20.--35. 1. "BEQOS_BANK_n_2,BEQOS_BANK[n]_2 Setting"
newline
hexmask.quad.word 0x00 10.--19. 1. "BEQOS_BANK_n_1,BEQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--9. 1. "BEQOS_BANK_n_0,BEQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "0320" "0321" "0322" "0323" "0324" "0325" "0326" "0327" "0328" "0329" "0330" "0331" "0332" "0333" "0334" "0335" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x2A00)++0x07
line.quad 0x00 "QOSBW_BE_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 54.--56. "Reserved_54,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 52.--53. "BEQOS_BANK_n_5,BEQOS_BANK[n]_5 Setting" "0,1,2,3"
newline
bitfld.quad 0x00 48.--51. "BEQOS_BANK_n_4,BEQOS_BANK[n]_4 Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 44.--47. "Reserved_44,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 36.--43. 1. "BEQOS_BANK_n_3,BEQOS_BANK[n]_3 Setting"
newline
hexmask.quad.word 0x00 20.--35. 1. "BEQOS_BANK_n_2,BEQOS_BANK[n]_2 Setting"
newline
hexmask.quad.word 0x00 10.--19. 1. "BEQOS_BANK_n_1,BEQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--9. 1. "BEQOS_BANK_n_0,BEQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "0336" "0337" "0338" "0339" "0340" "0341" "0342" "0343" "0344" "0345" "0346" "0347" "0348" "0349" "0350" "0351" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x2A80)++0x07
line.quad 0x00 "QOSBW_BE_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 54.--56. "Reserved_54,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 52.--53. "BEQOS_BANK_n_5,BEQOS_BANK[n]_5 Setting" "0,1,2,3"
newline
bitfld.quad 0x00 48.--51. "BEQOS_BANK_n_4,BEQOS_BANK[n]_4 Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 44.--47. "Reserved_44,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 36.--43. 1. "BEQOS_BANK_n_3,BEQOS_BANK[n]_3 Setting"
newline
hexmask.quad.word 0x00 20.--35. 1. "BEQOS_BANK_n_2,BEQOS_BANK[n]_2 Setting"
newline
hexmask.quad.word 0x00 10.--19. 1. "BEQOS_BANK_n_1,BEQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--9. 1. "BEQOS_BANK_n_0,BEQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "0352" "0353" "0354" "0355" "0356" "0357" "0358" "0359" "0360" "0361" "0362" "0363" "0364" "0365" "0366" "0367" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x2B00)++0x07
line.quad 0x00 "QOSBW_BE_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 54.--56. "Reserved_54,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 52.--53. "BEQOS_BANK_n_5,BEQOS_BANK[n]_5 Setting" "0,1,2,3"
newline
bitfld.quad 0x00 48.--51. "BEQOS_BANK_n_4,BEQOS_BANK[n]_4 Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 44.--47. "Reserved_44,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 36.--43. 1. "BEQOS_BANK_n_3,BEQOS_BANK[n]_3 Setting"
newline
hexmask.quad.word 0x00 20.--35. 1. "BEQOS_BANK_n_2,BEQOS_BANK[n]_2 Setting"
newline
hexmask.quad.word 0x00 10.--19. 1. "BEQOS_BANK_n_1,BEQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--9. 1. "BEQOS_BANK_n_0,BEQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "0368" "0369" "0370" "0371" "0372" "0373" "0374" "0375" "0376" "0377" "0378" "0379" "0380" "0381" "0382" "0383" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x2B80)++0x07
line.quad 0x00 "QOSBW_BE_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 54.--56. "Reserved_54,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 52.--53. "BEQOS_BANK_n_5,BEQOS_BANK[n]_5 Setting" "0,1,2,3"
newline
bitfld.quad 0x00 48.--51. "BEQOS_BANK_n_4,BEQOS_BANK[n]_4 Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 44.--47. "Reserved_44,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 36.--43. 1. "BEQOS_BANK_n_3,BEQOS_BANK[n]_3 Setting"
newline
hexmask.quad.word 0x00 20.--35. 1. "BEQOS_BANK_n_2,BEQOS_BANK[n]_2 Setting"
newline
hexmask.quad.word 0x00 10.--19. 1. "BEQOS_BANK_n_1,BEQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--9. 1. "BEQOS_BANK_n_0,BEQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "0384" "0385" "0386" "0387" "0388" "0389" "0390" "0391" "0392" "0393" "0394" "0395" "0396" "0397" "0398" "0399" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x2C00)++0x07
line.quad 0x00 "QOSBW_BE_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 54.--56. "Reserved_54,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 52.--53. "BEQOS_BANK_n_5,BEQOS_BANK[n]_5 Setting" "0,1,2,3"
newline
bitfld.quad 0x00 48.--51. "BEQOS_BANK_n_4,BEQOS_BANK[n]_4 Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 44.--47. "Reserved_44,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 36.--43. 1. "BEQOS_BANK_n_3,BEQOS_BANK[n]_3 Setting"
newline
hexmask.quad.word 0x00 20.--35. 1. "BEQOS_BANK_n_2,BEQOS_BANK[n]_2 Setting"
newline
hexmask.quad.word 0x00 10.--19. 1. "BEQOS_BANK_n_1,BEQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--9. 1. "BEQOS_BANK_n_0,BEQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "0400" "0401" "0402" "0403" "0404" "0405" "0406" "0407" "0408" "0409" "0410" "0411" "0412" "0413" "0414" "0415" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x2C80)++0x07
line.quad 0x00 "QOSBW_BE_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 54.--56. "Reserved_54,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 52.--53. "BEQOS_BANK_n_5,BEQOS_BANK[n]_5 Setting" "0,1,2,3"
newline
bitfld.quad 0x00 48.--51. "BEQOS_BANK_n_4,BEQOS_BANK[n]_4 Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 44.--47. "Reserved_44,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 36.--43. 1. "BEQOS_BANK_n_3,BEQOS_BANK[n]_3 Setting"
newline
hexmask.quad.word 0x00 20.--35. 1. "BEQOS_BANK_n_2,BEQOS_BANK[n]_2 Setting"
newline
hexmask.quad.word 0x00 10.--19. 1. "BEQOS_BANK_n_1,BEQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--9. 1. "BEQOS_BANK_n_0,BEQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "0416" "0417" "0418" "0419" "0420" "0421" "0422" "0423" "0424" "0425" "0426" "0427" "0428" "0429" "0430" "0431" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x2D00)++0x07
line.quad 0x00 "QOSBW_BE_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 54.--56. "Reserved_54,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 52.--53. "BEQOS_BANK_n_5,BEQOS_BANK[n]_5 Setting" "0,1,2,3"
newline
bitfld.quad 0x00 48.--51. "BEQOS_BANK_n_4,BEQOS_BANK[n]_4 Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 44.--47. "Reserved_44,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 36.--43. 1. "BEQOS_BANK_n_3,BEQOS_BANK[n]_3 Setting"
newline
hexmask.quad.word 0x00 20.--35. 1. "BEQOS_BANK_n_2,BEQOS_BANK[n]_2 Setting"
newline
hexmask.quad.word 0x00 10.--19. 1. "BEQOS_BANK_n_1,BEQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--9. 1. "BEQOS_BANK_n_0,BEQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "0432" "0433" "0434" "0435" "0436" "0437" "0438" "0439" "0440" "0441" "0442" "0443" "0444" "0445" "0446" "0447" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x2D80)++0x07
line.quad 0x00 "QOSBW_BE_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 54.--56. "Reserved_54,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 52.--53. "BEQOS_BANK_n_5,BEQOS_BANK[n]_5 Setting" "0,1,2,3"
newline
bitfld.quad 0x00 48.--51. "BEQOS_BANK_n_4,BEQOS_BANK[n]_4 Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 44.--47. "Reserved_44,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 36.--43. 1. "BEQOS_BANK_n_3,BEQOS_BANK[n]_3 Setting"
newline
hexmask.quad.word 0x00 20.--35. 1. "BEQOS_BANK_n_2,BEQOS_BANK[n]_2 Setting"
newline
hexmask.quad.word 0x00 10.--19. 1. "BEQOS_BANK_n_1,BEQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--9. 1. "BEQOS_BANK_n_0,BEQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "0448" "0449" "0450" "0451" "0452" "0453" "0454" "0455" "0456" "0457" "0458" "0459" "0460" "0461" "0462" "0463" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x2E00)++0x07
line.quad 0x00 "QOSBW_BE_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 54.--56. "Reserved_54,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 52.--53. "BEQOS_BANK_n_5,BEQOS_BANK[n]_5 Setting" "0,1,2,3"
newline
bitfld.quad 0x00 48.--51. "BEQOS_BANK_n_4,BEQOS_BANK[n]_4 Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 44.--47. "Reserved_44,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 36.--43. 1. "BEQOS_BANK_n_3,BEQOS_BANK[n]_3 Setting"
newline
hexmask.quad.word 0x00 20.--35. 1. "BEQOS_BANK_n_2,BEQOS_BANK[n]_2 Setting"
newline
hexmask.quad.word 0x00 10.--19. 1. "BEQOS_BANK_n_1,BEQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--9. 1. "BEQOS_BANK_n_0,BEQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "0464" "0465" "0466" "0467" "0468" "0469" "0470" "0471" "0472" "0473" "0474" "0475" "0476" "0477" "0478" "0479" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x2E80)++0x07
line.quad 0x00 "QOSBW_BE_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 54.--56. "Reserved_54,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 52.--53. "BEQOS_BANK_n_5,BEQOS_BANK[n]_5 Setting" "0,1,2,3"
newline
bitfld.quad 0x00 48.--51. "BEQOS_BANK_n_4,BEQOS_BANK[n]_4 Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 44.--47. "Reserved_44,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 36.--43. 1. "BEQOS_BANK_n_3,BEQOS_BANK[n]_3 Setting"
newline
hexmask.quad.word 0x00 20.--35. 1. "BEQOS_BANK_n_2,BEQOS_BANK[n]_2 Setting"
newline
hexmask.quad.word 0x00 10.--19. 1. "BEQOS_BANK_n_1,BEQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--9. 1. "BEQOS_BANK_n_0,BEQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "0480" "0481" "0482" "0483" "0484" "0485" "0486" "0487" "0488" "0489" "0490" "0491" "0492" "0493" "0494" "0495" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x2F00)++0x07
line.quad 0x00 "QOSBW_BE_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 54.--56. "Reserved_54,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 52.--53. "BEQOS_BANK_n_5,BEQOS_BANK[n]_5 Setting" "0,1,2,3"
newline
bitfld.quad 0x00 48.--51. "BEQOS_BANK_n_4,BEQOS_BANK[n]_4 Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 44.--47. "Reserved_44,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 36.--43. 1. "BEQOS_BANK_n_3,BEQOS_BANK[n]_3 Setting"
newline
hexmask.quad.word 0x00 20.--35. 1. "BEQOS_BANK_n_2,BEQOS_BANK[n]_2 Setting"
newline
hexmask.quad.word 0x00 10.--19. 1. "BEQOS_BANK_n_1,BEQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--9. 1. "BEQOS_BANK_n_0,BEQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "0496" "0497" "0498" "0499" "0500" "0501" "0502" "0503" "0504" "0505" "0506" "0507" "0508" "0509" "0510" "0511" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x2F80)++0x07
line.quad 0x00 "QOSBW_BE_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 54.--56. "Reserved_54,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 52.--53. "BEQOS_BANK_n_5,BEQOS_BANK[n]_5 Setting" "0,1,2,3"
newline
bitfld.quad 0x00 48.--51. "BEQOS_BANK_n_4,BEQOS_BANK[n]_4 Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 44.--47. "Reserved_44,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 36.--43. 1. "BEQOS_BANK_n_3,BEQOS_BANK[n]_3 Setting"
newline
hexmask.quad.word 0x00 20.--35. 1. "BEQOS_BANK_n_2,BEQOS_BANK[n]_2 Setting"
newline
hexmask.quad.word 0x00 10.--19. 1. "BEQOS_BANK_n_1,BEQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--9. 1. "BEQOS_BANK_n_0,BEQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "10" "11" "12" "13" "14" "15" "16" "17" "18" "19" "110" "111" "112" "113" "114" "115" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x3000)++0x07
line.quad 0x00 "QOSBW_BE_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 54.--56. "Reserved_54,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 52.--53. "BEQOS_BANK_n_5,BEQOS_BANK[n]_5 Setting" "0,1,2,3"
newline
bitfld.quad 0x00 48.--51. "BEQOS_BANK_n_4,BEQOS_BANK[n]_4 Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 44.--47. "Reserved_44,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 36.--43. 1. "BEQOS_BANK_n_3,BEQOS_BANK[n]_3 Setting"
newline
hexmask.quad.word 0x00 20.--35. 1. "BEQOS_BANK_n_2,BEQOS_BANK[n]_2 Setting"
newline
hexmask.quad.word 0x00 10.--19. 1. "BEQOS_BANK_n_1,BEQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--9. 1. "BEQOS_BANK_n_0,BEQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "116" "117" "118" "119" "120" "121" "122" "123" "124" "125" "126" "127" "128" "129" "130" "131" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x3080)++0x07
line.quad 0x00 "QOSBW_BE_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 54.--56. "Reserved_54,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 52.--53. "BEQOS_BANK_n_5,BEQOS_BANK[n]_5 Setting" "0,1,2,3"
newline
bitfld.quad 0x00 48.--51. "BEQOS_BANK_n_4,BEQOS_BANK[n]_4 Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 44.--47. "Reserved_44,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 36.--43. 1. "BEQOS_BANK_n_3,BEQOS_BANK[n]_3 Setting"
newline
hexmask.quad.word 0x00 20.--35. 1. "BEQOS_BANK_n_2,BEQOS_BANK[n]_2 Setting"
newline
hexmask.quad.word 0x00 10.--19. 1. "BEQOS_BANK_n_1,BEQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--9. 1. "BEQOS_BANK_n_0,BEQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "132" "133" "134" "135" "136" "137" "138" "139" "140" "141" "142" "143" "144" "145" "146" "147" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x3100)++0x07
line.quad 0x00 "QOSBW_BE_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 54.--56. "Reserved_54,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 52.--53. "BEQOS_BANK_n_5,BEQOS_BANK[n]_5 Setting" "0,1,2,3"
newline
bitfld.quad 0x00 48.--51. "BEQOS_BANK_n_4,BEQOS_BANK[n]_4 Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 44.--47. "Reserved_44,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 36.--43. 1. "BEQOS_BANK_n_3,BEQOS_BANK[n]_3 Setting"
newline
hexmask.quad.word 0x00 20.--35. 1. "BEQOS_BANK_n_2,BEQOS_BANK[n]_2 Setting"
newline
hexmask.quad.word 0x00 10.--19. 1. "BEQOS_BANK_n_1,BEQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--9. 1. "BEQOS_BANK_n_0,BEQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "148" "149" "150" "151" "152" "153" "154" "155" "156" "157" "158" "159" "160" "161" "162" "163" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x3180)++0x07
line.quad 0x00 "QOSBW_BE_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 54.--56. "Reserved_54,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 52.--53. "BEQOS_BANK_n_5,BEQOS_BANK[n]_5 Setting" "0,1,2,3"
newline
bitfld.quad 0x00 48.--51. "BEQOS_BANK_n_4,BEQOS_BANK[n]_4 Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 44.--47. "Reserved_44,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 36.--43. 1. "BEQOS_BANK_n_3,BEQOS_BANK[n]_3 Setting"
newline
hexmask.quad.word 0x00 20.--35. 1. "BEQOS_BANK_n_2,BEQOS_BANK[n]_2 Setting"
newline
hexmask.quad.word 0x00 10.--19. 1. "BEQOS_BANK_n_1,BEQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--9. 1. "BEQOS_BANK_n_0,BEQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "164" "165" "166" "167" "168" "169" "170" "171" "172" "173" "174" "175" "176" "177" "178" "179" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x3200)++0x07
line.quad 0x00 "QOSBW_BE_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 54.--56. "Reserved_54,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 52.--53. "BEQOS_BANK_n_5,BEQOS_BANK[n]_5 Setting" "0,1,2,3"
newline
bitfld.quad 0x00 48.--51. "BEQOS_BANK_n_4,BEQOS_BANK[n]_4 Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 44.--47. "Reserved_44,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 36.--43. 1. "BEQOS_BANK_n_3,BEQOS_BANK[n]_3 Setting"
newline
hexmask.quad.word 0x00 20.--35. 1. "BEQOS_BANK_n_2,BEQOS_BANK[n]_2 Setting"
newline
hexmask.quad.word 0x00 10.--19. 1. "BEQOS_BANK_n_1,BEQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--9. 1. "BEQOS_BANK_n_0,BEQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "180" "181" "182" "183" "184" "185" "186" "187" "188" "189" "190" "191" "192" "193" "194" "195" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x3280)++0x07
line.quad 0x00 "QOSBW_BE_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 54.--56. "Reserved_54,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 52.--53. "BEQOS_BANK_n_5,BEQOS_BANK[n]_5 Setting" "0,1,2,3"
newline
bitfld.quad 0x00 48.--51. "BEQOS_BANK_n_4,BEQOS_BANK[n]_4 Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 44.--47. "Reserved_44,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 36.--43. 1. "BEQOS_BANK_n_3,BEQOS_BANK[n]_3 Setting"
newline
hexmask.quad.word 0x00 20.--35. 1. "BEQOS_BANK_n_2,BEQOS_BANK[n]_2 Setting"
newline
hexmask.quad.word 0x00 10.--19. 1. "BEQOS_BANK_n_1,BEQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--9. 1. "BEQOS_BANK_n_0,BEQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "196" "197" "198" "199" "1100" "1101" "1102" "1103" "1104" "1105" "1106" "1107" "1108" "1109" "1110" "1111" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x3300)++0x07
line.quad 0x00 "QOSBW_BE_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 54.--56. "Reserved_54,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 52.--53. "BEQOS_BANK_n_5,BEQOS_BANK[n]_5 Setting" "0,1,2,3"
newline
bitfld.quad 0x00 48.--51. "BEQOS_BANK_n_4,BEQOS_BANK[n]_4 Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 44.--47. "Reserved_44,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 36.--43. 1. "BEQOS_BANK_n_3,BEQOS_BANK[n]_3 Setting"
newline
hexmask.quad.word 0x00 20.--35. 1. "BEQOS_BANK_n_2,BEQOS_BANK[n]_2 Setting"
newline
hexmask.quad.word 0x00 10.--19. 1. "BEQOS_BANK_n_1,BEQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--9. 1. "BEQOS_BANK_n_0,BEQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "1112" "1113" "1114" "1115" "1116" "1117" "1118" "1119" "1120" "1121" "1122" "1123" "1124" "1125" "1126" "1127" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x3380)++0x07
line.quad 0x00 "QOSBW_BE_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 54.--56. "Reserved_54,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 52.--53. "BEQOS_BANK_n_5,BEQOS_BANK[n]_5 Setting" "0,1,2,3"
newline
bitfld.quad 0x00 48.--51. "BEQOS_BANK_n_4,BEQOS_BANK[n]_4 Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 44.--47. "Reserved_44,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 36.--43. 1. "BEQOS_BANK_n_3,BEQOS_BANK[n]_3 Setting"
newline
hexmask.quad.word 0x00 20.--35. 1. "BEQOS_BANK_n_2,BEQOS_BANK[n]_2 Setting"
newline
hexmask.quad.word 0x00 10.--19. 1. "BEQOS_BANK_n_1,BEQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--9. 1. "BEQOS_BANK_n_0,BEQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "1128" "1129" "1130" "1131" "1132" "1133" "1134" "1135" "1136" "1137" "1138" "1139" "1140" "1141" "1142" "1143" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x3400)++0x07
line.quad 0x00 "QOSBW_BE_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 54.--56. "Reserved_54,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 52.--53. "BEQOS_BANK_n_5,BEQOS_BANK[n]_5 Setting" "0,1,2,3"
newline
bitfld.quad 0x00 48.--51. "BEQOS_BANK_n_4,BEQOS_BANK[n]_4 Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 44.--47. "Reserved_44,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 36.--43. 1. "BEQOS_BANK_n_3,BEQOS_BANK[n]_3 Setting"
newline
hexmask.quad.word 0x00 20.--35. 1. "BEQOS_BANK_n_2,BEQOS_BANK[n]_2 Setting"
newline
hexmask.quad.word 0x00 10.--19. 1. "BEQOS_BANK_n_1,BEQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--9. 1. "BEQOS_BANK_n_0,BEQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "1144" "1145" "1146" "1147" "1148" "1149" "1150" "1151" "1152" "1153" "1154" "1155" "1156" "1157" "1158" "1159" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x3480)++0x07
line.quad 0x00 "QOSBW_BE_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 54.--56. "Reserved_54,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 52.--53. "BEQOS_BANK_n_5,BEQOS_BANK[n]_5 Setting" "0,1,2,3"
newline
bitfld.quad 0x00 48.--51. "BEQOS_BANK_n_4,BEQOS_BANK[n]_4 Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 44.--47. "Reserved_44,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 36.--43. 1. "BEQOS_BANK_n_3,BEQOS_BANK[n]_3 Setting"
newline
hexmask.quad.word 0x00 20.--35. 1. "BEQOS_BANK_n_2,BEQOS_BANK[n]_2 Setting"
newline
hexmask.quad.word 0x00 10.--19. 1. "BEQOS_BANK_n_1,BEQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--9. 1. "BEQOS_BANK_n_0,BEQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "1160" "1161" "1162" "1163" "1164" "1165" "1166" "1167" "1168" "1169" "1170" "1171" "1172" "1173" "1174" "1175" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x3500)++0x07
line.quad 0x00 "QOSBW_BE_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 54.--56. "Reserved_54,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 52.--53. "BEQOS_BANK_n_5,BEQOS_BANK[n]_5 Setting" "0,1,2,3"
newline
bitfld.quad 0x00 48.--51. "BEQOS_BANK_n_4,BEQOS_BANK[n]_4 Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 44.--47. "Reserved_44,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 36.--43. 1. "BEQOS_BANK_n_3,BEQOS_BANK[n]_3 Setting"
newline
hexmask.quad.word 0x00 20.--35. 1. "BEQOS_BANK_n_2,BEQOS_BANK[n]_2 Setting"
newline
hexmask.quad.word 0x00 10.--19. 1. "BEQOS_BANK_n_1,BEQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--9. 1. "BEQOS_BANK_n_0,BEQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "1176" "1177" "1178" "1179" "1180" "1181" "1182" "1183" "1184" "1185" "1186" "1187" "1188" "1189" "1190" "1191" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x3580)++0x07
line.quad 0x00 "QOSBW_BE_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 54.--56. "Reserved_54,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 52.--53. "BEQOS_BANK_n_5,BEQOS_BANK[n]_5 Setting" "0,1,2,3"
newline
bitfld.quad 0x00 48.--51. "BEQOS_BANK_n_4,BEQOS_BANK[n]_4 Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 44.--47. "Reserved_44,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 36.--43. 1. "BEQOS_BANK_n_3,BEQOS_BANK[n]_3 Setting"
newline
hexmask.quad.word 0x00 20.--35. 1. "BEQOS_BANK_n_2,BEQOS_BANK[n]_2 Setting"
newline
hexmask.quad.word 0x00 10.--19. 1. "BEQOS_BANK_n_1,BEQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--9. 1. "BEQOS_BANK_n_0,BEQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "1192" "1193" "1194" "1195" "1196" "1197" "1198" "1199" "1200" "1201" "1202" "1203" "1204" "1205" "1206" "1207" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x3600)++0x07
line.quad 0x00 "QOSBW_BE_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 54.--56. "Reserved_54,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 52.--53. "BEQOS_BANK_n_5,BEQOS_BANK[n]_5 Setting" "0,1,2,3"
newline
bitfld.quad 0x00 48.--51. "BEQOS_BANK_n_4,BEQOS_BANK[n]_4 Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 44.--47. "Reserved_44,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 36.--43. 1. "BEQOS_BANK_n_3,BEQOS_BANK[n]_3 Setting"
newline
hexmask.quad.word 0x00 20.--35. 1. "BEQOS_BANK_n_2,BEQOS_BANK[n]_2 Setting"
newline
hexmask.quad.word 0x00 10.--19. 1. "BEQOS_BANK_n_1,BEQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--9. 1. "BEQOS_BANK_n_0,BEQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "1208" "1209" "1210" "1211" "1212" "1213" "1214" "1215" "1216" "1217" "1218" "1219" "1220" "1221" "1222" "1223" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x3680)++0x07
line.quad 0x00 "QOSBW_BE_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 54.--56. "Reserved_54,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 52.--53. "BEQOS_BANK_n_5,BEQOS_BANK[n]_5 Setting" "0,1,2,3"
newline
bitfld.quad 0x00 48.--51. "BEQOS_BANK_n_4,BEQOS_BANK[n]_4 Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 44.--47. "Reserved_44,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 36.--43. 1. "BEQOS_BANK_n_3,BEQOS_BANK[n]_3 Setting"
newline
hexmask.quad.word 0x00 20.--35. 1. "BEQOS_BANK_n_2,BEQOS_BANK[n]_2 Setting"
newline
hexmask.quad.word 0x00 10.--19. 1. "BEQOS_BANK_n_1,BEQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--9. 1. "BEQOS_BANK_n_0,BEQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "1224" "1225" "1226" "1227" "1228" "1229" "1230" "1231" "1232" "1233" "1234" "1235" "1236" "1237" "1238" "1239" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x3700)++0x07
line.quad 0x00 "QOSBW_BE_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 54.--56. "Reserved_54,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 52.--53. "BEQOS_BANK_n_5,BEQOS_BANK[n]_5 Setting" "0,1,2,3"
newline
bitfld.quad 0x00 48.--51. "BEQOS_BANK_n_4,BEQOS_BANK[n]_4 Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 44.--47. "Reserved_44,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 36.--43. 1. "BEQOS_BANK_n_3,BEQOS_BANK[n]_3 Setting"
newline
hexmask.quad.word 0x00 20.--35. 1. "BEQOS_BANK_n_2,BEQOS_BANK[n]_2 Setting"
newline
hexmask.quad.word 0x00 10.--19. 1. "BEQOS_BANK_n_1,BEQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--9. 1. "BEQOS_BANK_n_0,BEQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "1240" "1241" "1242" "1243" "1244" "1245" "1246" "1247" "1248" "1249" "1250" "1251" "1252" "1253" "1254" "1255" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x3780)++0x07
line.quad 0x00 "QOSBW_BE_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 54.--56. "Reserved_54,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 52.--53. "BEQOS_BANK_n_5,BEQOS_BANK[n]_5 Setting" "0,1,2,3"
newline
bitfld.quad 0x00 48.--51. "BEQOS_BANK_n_4,BEQOS_BANK[n]_4 Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 44.--47. "Reserved_44,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 36.--43. 1. "BEQOS_BANK_n_3,BEQOS_BANK[n]_3 Setting"
newline
hexmask.quad.word 0x00 20.--35. 1. "BEQOS_BANK_n_2,BEQOS_BANK[n]_2 Setting"
newline
hexmask.quad.word 0x00 10.--19. 1. "BEQOS_BANK_n_1,BEQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--9. 1. "BEQOS_BANK_n_0,BEQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "1256" "1257" "1258" "1259" "1260" "1261" "1262" "1263" "1264" "1265" "1266" "1267" "1268" "1269" "1270" "1271" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x3800)++0x07
line.quad 0x00 "QOSBW_BE_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 54.--56. "Reserved_54,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 52.--53. "BEQOS_BANK_n_5,BEQOS_BANK[n]_5 Setting" "0,1,2,3"
newline
bitfld.quad 0x00 48.--51. "BEQOS_BANK_n_4,BEQOS_BANK[n]_4 Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 44.--47. "Reserved_44,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 36.--43. 1. "BEQOS_BANK_n_3,BEQOS_BANK[n]_3 Setting"
newline
hexmask.quad.word 0x00 20.--35. 1. "BEQOS_BANK_n_2,BEQOS_BANK[n]_2 Setting"
newline
hexmask.quad.word 0x00 10.--19. 1. "BEQOS_BANK_n_1,BEQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--9. 1. "BEQOS_BANK_n_0,BEQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "1272" "1273" "1274" "1275" "1276" "1277" "1278" "1279" "1280" "1281" "1282" "1283" "1284" "1285" "1286" "1287" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x3880)++0x07
line.quad 0x00 "QOSBW_BE_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 54.--56. "Reserved_54,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 52.--53. "BEQOS_BANK_n_5,BEQOS_BANK[n]_5 Setting" "0,1,2,3"
newline
bitfld.quad 0x00 48.--51. "BEQOS_BANK_n_4,BEQOS_BANK[n]_4 Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 44.--47. "Reserved_44,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 36.--43. 1. "BEQOS_BANK_n_3,BEQOS_BANK[n]_3 Setting"
newline
hexmask.quad.word 0x00 20.--35. 1. "BEQOS_BANK_n_2,BEQOS_BANK[n]_2 Setting"
newline
hexmask.quad.word 0x00 10.--19. 1. "BEQOS_BANK_n_1,BEQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--9. 1. "BEQOS_BANK_n_0,BEQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "1288" "1289" "1290" "1291" "1292" "1293" "1294" "1295" "1296" "1297" "1298" "1299" "1300" "1301" "1302" "1303" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x3900)++0x07
line.quad 0x00 "QOSBW_BE_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 54.--56. "Reserved_54,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 52.--53. "BEQOS_BANK_n_5,BEQOS_BANK[n]_5 Setting" "0,1,2,3"
newline
bitfld.quad 0x00 48.--51. "BEQOS_BANK_n_4,BEQOS_BANK[n]_4 Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 44.--47. "Reserved_44,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 36.--43. 1. "BEQOS_BANK_n_3,BEQOS_BANK[n]_3 Setting"
newline
hexmask.quad.word 0x00 20.--35. 1. "BEQOS_BANK_n_2,BEQOS_BANK[n]_2 Setting"
newline
hexmask.quad.word 0x00 10.--19. 1. "BEQOS_BANK_n_1,BEQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--9. 1. "BEQOS_BANK_n_0,BEQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "1304" "1305" "1306" "1307" "1308" "1309" "1310" "1311" "1312" "1313" "1314" "1315" "1316" "1317" "1318" "1319" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x3980)++0x07
line.quad 0x00 "QOSBW_BE_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 54.--56. "Reserved_54,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 52.--53. "BEQOS_BANK_n_5,BEQOS_BANK[n]_5 Setting" "0,1,2,3"
newline
bitfld.quad 0x00 48.--51. "BEQOS_BANK_n_4,BEQOS_BANK[n]_4 Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 44.--47. "Reserved_44,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 36.--43. 1. "BEQOS_BANK_n_3,BEQOS_BANK[n]_3 Setting"
newline
hexmask.quad.word 0x00 20.--35. 1. "BEQOS_BANK_n_2,BEQOS_BANK[n]_2 Setting"
newline
hexmask.quad.word 0x00 10.--19. 1. "BEQOS_BANK_n_1,BEQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--9. 1. "BEQOS_BANK_n_0,BEQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "1320" "1321" "1322" "1323" "1324" "1325" "1326" "1327" "1328" "1329" "1330" "1331" "1332" "1333" "1334" "1335" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x3A00)++0x07
line.quad 0x00 "QOSBW_BE_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 54.--56. "Reserved_54,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 52.--53. "BEQOS_BANK_n_5,BEQOS_BANK[n]_5 Setting" "0,1,2,3"
newline
bitfld.quad 0x00 48.--51. "BEQOS_BANK_n_4,BEQOS_BANK[n]_4 Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 44.--47. "Reserved_44,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 36.--43. 1. "BEQOS_BANK_n_3,BEQOS_BANK[n]_3 Setting"
newline
hexmask.quad.word 0x00 20.--35. 1. "BEQOS_BANK_n_2,BEQOS_BANK[n]_2 Setting"
newline
hexmask.quad.word 0x00 10.--19. 1. "BEQOS_BANK_n_1,BEQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--9. 1. "BEQOS_BANK_n_0,BEQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "1336" "1337" "1338" "1339" "1340" "1341" "1342" "1343" "1344" "1345" "1346" "1347" "1348" "1349" "1350" "1351" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x3A80)++0x07
line.quad 0x00 "QOSBW_BE_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 54.--56. "Reserved_54,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 52.--53. "BEQOS_BANK_n_5,BEQOS_BANK[n]_5 Setting" "0,1,2,3"
newline
bitfld.quad 0x00 48.--51. "BEQOS_BANK_n_4,BEQOS_BANK[n]_4 Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 44.--47. "Reserved_44,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 36.--43. 1. "BEQOS_BANK_n_3,BEQOS_BANK[n]_3 Setting"
newline
hexmask.quad.word 0x00 20.--35. 1. "BEQOS_BANK_n_2,BEQOS_BANK[n]_2 Setting"
newline
hexmask.quad.word 0x00 10.--19. 1. "BEQOS_BANK_n_1,BEQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--9. 1. "BEQOS_BANK_n_0,BEQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "1352" "1353" "1354" "1355" "1356" "1357" "1358" "1359" "1360" "1361" "1362" "1363" "1364" "1365" "1366" "1367" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x3B00)++0x07
line.quad 0x00 "QOSBW_BE_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 54.--56. "Reserved_54,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 52.--53. "BEQOS_BANK_n_5,BEQOS_BANK[n]_5 Setting" "0,1,2,3"
newline
bitfld.quad 0x00 48.--51. "BEQOS_BANK_n_4,BEQOS_BANK[n]_4 Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 44.--47. "Reserved_44,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 36.--43. 1. "BEQOS_BANK_n_3,BEQOS_BANK[n]_3 Setting"
newline
hexmask.quad.word 0x00 20.--35. 1. "BEQOS_BANK_n_2,BEQOS_BANK[n]_2 Setting"
newline
hexmask.quad.word 0x00 10.--19. 1. "BEQOS_BANK_n_1,BEQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--9. 1. "BEQOS_BANK_n_0,BEQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "1368" "1369" "1370" "1371" "1372" "1373" "1374" "1375" "1376" "1377" "1378" "1379" "1380" "1381" "1382" "1383" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x3B80)++0x07
line.quad 0x00 "QOSBW_BE_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 54.--56. "Reserved_54,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 52.--53. "BEQOS_BANK_n_5,BEQOS_BANK[n]_5 Setting" "0,1,2,3"
newline
bitfld.quad 0x00 48.--51. "BEQOS_BANK_n_4,BEQOS_BANK[n]_4 Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 44.--47. "Reserved_44,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 36.--43. 1. "BEQOS_BANK_n_3,BEQOS_BANK[n]_3 Setting"
newline
hexmask.quad.word 0x00 20.--35. 1. "BEQOS_BANK_n_2,BEQOS_BANK[n]_2 Setting"
newline
hexmask.quad.word 0x00 10.--19. 1. "BEQOS_BANK_n_1,BEQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--9. 1. "BEQOS_BANK_n_0,BEQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "1384" "1385" "1386" "1387" "1388" "1389" "1390" "1391" "1392" "1393" "1394" "1395" "1396" "1397" "1398" "1399" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x3C00)++0x07
line.quad 0x00 "QOSBW_BE_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 54.--56. "Reserved_54,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 52.--53. "BEQOS_BANK_n_5,BEQOS_BANK[n]_5 Setting" "0,1,2,3"
newline
bitfld.quad 0x00 48.--51. "BEQOS_BANK_n_4,BEQOS_BANK[n]_4 Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 44.--47. "Reserved_44,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 36.--43. 1. "BEQOS_BANK_n_3,BEQOS_BANK[n]_3 Setting"
newline
hexmask.quad.word 0x00 20.--35. 1. "BEQOS_BANK_n_2,BEQOS_BANK[n]_2 Setting"
newline
hexmask.quad.word 0x00 10.--19. 1. "BEQOS_BANK_n_1,BEQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--9. 1. "BEQOS_BANK_n_0,BEQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "1400" "1401" "1402" "1403" "1404" "1405" "1406" "1407" "1408" "1409" "1410" "1411" "1412" "1413" "1414" "1415" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x3C80)++0x07
line.quad 0x00 "QOSBW_BE_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 54.--56. "Reserved_54,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 52.--53. "BEQOS_BANK_n_5,BEQOS_BANK[n]_5 Setting" "0,1,2,3"
newline
bitfld.quad 0x00 48.--51. "BEQOS_BANK_n_4,BEQOS_BANK[n]_4 Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 44.--47. "Reserved_44,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 36.--43. 1. "BEQOS_BANK_n_3,BEQOS_BANK[n]_3 Setting"
newline
hexmask.quad.word 0x00 20.--35. 1. "BEQOS_BANK_n_2,BEQOS_BANK[n]_2 Setting"
newline
hexmask.quad.word 0x00 10.--19. 1. "BEQOS_BANK_n_1,BEQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--9. 1. "BEQOS_BANK_n_0,BEQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "1416" "1417" "1418" "1419" "1420" "1421" "1422" "1423" "1424" "1425" "1426" "1427" "1428" "1429" "1430" "1431" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x3D00)++0x07
line.quad 0x00 "QOSBW_BE_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 54.--56. "Reserved_54,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 52.--53. "BEQOS_BANK_n_5,BEQOS_BANK[n]_5 Setting" "0,1,2,3"
newline
bitfld.quad 0x00 48.--51. "BEQOS_BANK_n_4,BEQOS_BANK[n]_4 Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 44.--47. "Reserved_44,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 36.--43. 1. "BEQOS_BANK_n_3,BEQOS_BANK[n]_3 Setting"
newline
hexmask.quad.word 0x00 20.--35. 1. "BEQOS_BANK_n_2,BEQOS_BANK[n]_2 Setting"
newline
hexmask.quad.word 0x00 10.--19. 1. "BEQOS_BANK_n_1,BEQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--9. 1. "BEQOS_BANK_n_0,BEQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "1432" "1433" "1434" "1435" "1436" "1437" "1438" "1439" "1440" "1441" "1442" "1443" "1444" "1445" "1446" "1447" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x3D80)++0x07
line.quad 0x00 "QOSBW_BE_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 54.--56. "Reserved_54,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 52.--53. "BEQOS_BANK_n_5,BEQOS_BANK[n]_5 Setting" "0,1,2,3"
newline
bitfld.quad 0x00 48.--51. "BEQOS_BANK_n_4,BEQOS_BANK[n]_4 Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 44.--47. "Reserved_44,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 36.--43. 1. "BEQOS_BANK_n_3,BEQOS_BANK[n]_3 Setting"
newline
hexmask.quad.word 0x00 20.--35. 1. "BEQOS_BANK_n_2,BEQOS_BANK[n]_2 Setting"
newline
hexmask.quad.word 0x00 10.--19. 1. "BEQOS_BANK_n_1,BEQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--9. 1. "BEQOS_BANK_n_0,BEQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "1448" "1449" "1450" "1451" "1452" "1453" "1454" "1455" "1456" "1457" "1458" "1459" "1460" "1461" "1462" "1463" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x3E00)++0x07
line.quad 0x00 "QOSBW_BE_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 54.--56. "Reserved_54,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 52.--53. "BEQOS_BANK_n_5,BEQOS_BANK[n]_5 Setting" "0,1,2,3"
newline
bitfld.quad 0x00 48.--51. "BEQOS_BANK_n_4,BEQOS_BANK[n]_4 Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 44.--47. "Reserved_44,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 36.--43. 1. "BEQOS_BANK_n_3,BEQOS_BANK[n]_3 Setting"
newline
hexmask.quad.word 0x00 20.--35. 1. "BEQOS_BANK_n_2,BEQOS_BANK[n]_2 Setting"
newline
hexmask.quad.word 0x00 10.--19. 1. "BEQOS_BANK_n_1,BEQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--9. 1. "BEQOS_BANK_n_0,BEQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "1464" "1465" "1466" "1467" "1468" "1469" "1470" "1471" "1472" "1473" "1474" "1475" "1476" "1477" "1478" "1479" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x3E80)++0x07
line.quad 0x00 "QOSBW_BE_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 54.--56. "Reserved_54,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 52.--53. "BEQOS_BANK_n_5,BEQOS_BANK[n]_5 Setting" "0,1,2,3"
newline
bitfld.quad 0x00 48.--51. "BEQOS_BANK_n_4,BEQOS_BANK[n]_4 Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 44.--47. "Reserved_44,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 36.--43. 1. "BEQOS_BANK_n_3,BEQOS_BANK[n]_3 Setting"
newline
hexmask.quad.word 0x00 20.--35. 1. "BEQOS_BANK_n_2,BEQOS_BANK[n]_2 Setting"
newline
hexmask.quad.word 0x00 10.--19. 1. "BEQOS_BANK_n_1,BEQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--9. 1. "BEQOS_BANK_n_0,BEQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "1480" "1481" "1482" "1483" "1484" "1485" "1486" "1487" "1488" "1489" "1490" "1491" "1492" "1493" "1494" "1495" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x3F00)++0x07
line.quad 0x00 "QOSBW_BE_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 54.--56. "Reserved_54,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 52.--53. "BEQOS_BANK_n_5,BEQOS_BANK[n]_5 Setting" "0,1,2,3"
newline
bitfld.quad 0x00 48.--51. "BEQOS_BANK_n_4,BEQOS_BANK[n]_4 Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 44.--47. "Reserved_44,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 36.--43. 1. "BEQOS_BANK_n_3,BEQOS_BANK[n]_3 Setting"
newline
hexmask.quad.word 0x00 20.--35. 1. "BEQOS_BANK_n_2,BEQOS_BANK[n]_2 Setting"
newline
hexmask.quad.word 0x00 10.--19. 1. "BEQOS_BANK_n_1,BEQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--9. 1. "BEQOS_BANK_n_0,BEQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "1496" "1497" "1498" "1499" "1500" "1501" "1502" "1503" "1504" "1505" "1506" "1507" "1508" "1509" "1510" "1511" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x3F80)++0x07
line.quad 0x00 "QOSBW_BE_QOS_BANK$1,QOSCTRL_MEMBANK is 1"
hexmask.quad.byte 0x00 57.--63. 1. "Reserved_57,Reserved These bits are always read as 0"
newline
bitfld.quad 0x00 54.--56. "Reserved_54,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 52.--53. "BEQOS_BANK_n_5,BEQOS_BANK[n]_5 Setting" "0,1,2,3"
newline
bitfld.quad 0x00 48.--51. "BEQOS_BANK_n_4,BEQOS_BANK[n]_4 Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 44.--47. "Reserved_44,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 36.--43. 1. "BEQOS_BANK_n_3,BEQOS_BANK[n]_3 Setting"
newline
hexmask.quad.word 0x00 20.--35. 1. "BEQOS_BANK_n_2,BEQOS_BANK[n]_2 Setting"
newline
hexmask.quad.word 0x00 10.--19. 1. "BEQOS_BANK_n_1,BEQOS_BANK[n]_1 Setting"
newline
hexmask.quad.word 0x00 0.--9. 1. "BEQOS_BANK_n_0,BEQOS_BANK[n]_0 Setting"
repeat.end
repeat 16. (strings "00" "01" "02" "03" "04" "05" "06" "07" "08" "09" "010" "011" "012" "013" "014" "015" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x4000)++0x07
line.quad 0x00 "QOSMON_FIX_TRAFFIC_BANK$1,"
hexmask.quad.tbyte 0x00 40.--63. 1. "Reserved_40,Reserved These bits are always read as 0"
newline
hexmask.quad.quad 0x00 0.--39. 1. "traffic_fix,Bandwidth performance result of FIX"
repeat.end
repeat 16. (strings "016" "017" "018" "019" "020" "021" "022" "023" "024" "025" "026" "027" "028" "029" "030" "031" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x4080)++0x07
line.quad 0x00 "QOSMON_FIX_TRAFFIC_BANK$1,"
hexmask.quad.tbyte 0x00 40.--63. 1. "Reserved_40,Reserved These bits are always read as 0"
newline
hexmask.quad.quad 0x00 0.--39. 1. "traffic_fix,Bandwidth performance result of FIX"
repeat.end
repeat 16. (strings "032" "033" "034" "035" "036" "037" "038" "039" "040" "041" "042" "043" "044" "045" "046" "047" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x4100)++0x07
line.quad 0x00 "QOSMON_FIX_TRAFFIC_BANK$1,"
hexmask.quad.tbyte 0x00 40.--63. 1. "Reserved_40,Reserved These bits are always read as 0"
newline
hexmask.quad.quad 0x00 0.--39. 1. "traffic_fix,Bandwidth performance result of FIX"
repeat.end
repeat 16. (strings "048" "049" "050" "051" "052" "053" "054" "055" "056" "057" "058" "059" "060" "061" "062" "063" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x4180)++0x07
line.quad 0x00 "QOSMON_FIX_TRAFFIC_BANK$1,"
hexmask.quad.tbyte 0x00 40.--63. 1. "Reserved_40,Reserved These bits are always read as 0"
newline
hexmask.quad.quad 0x00 0.--39. 1. "traffic_fix,Bandwidth performance result of FIX"
repeat.end
repeat 16. (strings "064" "065" "066" "067" "068" "069" "070" "071" "072" "073" "074" "075" "076" "077" "078" "079" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x4200)++0x07
line.quad 0x00 "QOSMON_FIX_TRAFFIC_BANK$1,"
hexmask.quad.tbyte 0x00 40.--63. 1. "Reserved_40,Reserved These bits are always read as 0"
newline
hexmask.quad.quad 0x00 0.--39. 1. "traffic_fix,Bandwidth performance result of FIX"
repeat.end
repeat 16. (strings "080" "081" "082" "083" "084" "085" "086" "087" "088" "089" "090" "091" "092" "093" "094" "095" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x4280)++0x07
line.quad 0x00 "QOSMON_FIX_TRAFFIC_BANK$1,"
hexmask.quad.tbyte 0x00 40.--63. 1. "Reserved_40,Reserved These bits are always read as 0"
newline
hexmask.quad.quad 0x00 0.--39. 1. "traffic_fix,Bandwidth performance result of FIX"
repeat.end
repeat 16. (strings "096" "097" "098" "099" "0100" "0101" "0102" "0103" "0104" "0105" "0106" "0107" "0108" "0109" "0110" "0111" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x4300)++0x07
line.quad 0x00 "QOSMON_FIX_TRAFFIC_BANK$1,"
hexmask.quad.tbyte 0x00 40.--63. 1. "Reserved_40,Reserved These bits are always read as 0"
newline
hexmask.quad.quad 0x00 0.--39. 1. "traffic_fix,Bandwidth performance result of FIX"
repeat.end
repeat 16. (strings "0112" "0113" "0114" "0115" "0116" "0117" "0118" "0119" "0120" "0121" "0122" "0123" "0124" "0125" "0126" "0127" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x4380)++0x07
line.quad 0x00 "QOSMON_FIX_TRAFFIC_BANK$1,"
hexmask.quad.tbyte 0x00 40.--63. 1. "Reserved_40,Reserved These bits are always read as 0"
newline
hexmask.quad.quad 0x00 0.--39. 1. "traffic_fix,Bandwidth performance result of FIX"
repeat.end
repeat 16. (strings "0128" "0129" "0130" "0131" "0132" "0133" "0134" "0135" "0136" "0137" "0138" "0139" "0140" "0141" "0142" "0143" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x4400)++0x07
line.quad 0x00 "QOSMON_FIX_TRAFFIC_BANK$1,"
hexmask.quad.tbyte 0x00 40.--63. 1. "Reserved_40,Reserved These bits are always read as 0"
newline
hexmask.quad.quad 0x00 0.--39. 1. "traffic_fix,Bandwidth performance result of FIX"
repeat.end
repeat 16. (strings "0144" "0145" "0146" "0147" "0148" "0149" "0150" "0151" "0152" "0153" "0154" "0155" "0156" "0157" "0158" "0159" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x4480)++0x07
line.quad 0x00 "QOSMON_FIX_TRAFFIC_BANK$1,"
hexmask.quad.tbyte 0x00 40.--63. 1. "Reserved_40,Reserved These bits are always read as 0"
newline
hexmask.quad.quad 0x00 0.--39. 1. "traffic_fix,Bandwidth performance result of FIX"
repeat.end
repeat 16. (strings "0160" "0161" "0162" "0163" "0164" "0165" "0166" "0167" "0168" "0169" "0170" "0171" "0172" "0173" "0174" "0175" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x4500)++0x07
line.quad 0x00 "QOSMON_FIX_TRAFFIC_BANK$1,"
hexmask.quad.tbyte 0x00 40.--63. 1. "Reserved_40,Reserved These bits are always read as 0"
newline
hexmask.quad.quad 0x00 0.--39. 1. "traffic_fix,Bandwidth performance result of FIX"
repeat.end
repeat 16. (strings "0176" "0177" "0178" "0179" "0180" "0181" "0182" "0183" "0184" "0185" "0186" "0187" "0188" "0189" "0190" "0191" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x4580)++0x07
line.quad 0x00 "QOSMON_FIX_TRAFFIC_BANK$1,"
hexmask.quad.tbyte 0x00 40.--63. 1. "Reserved_40,Reserved These bits are always read as 0"
newline
hexmask.quad.quad 0x00 0.--39. 1. "traffic_fix,Bandwidth performance result of FIX"
repeat.end
repeat 16. (strings "0192" "0193" "0194" "0195" "0196" "0197" "0198" "0199" "0200" "0201" "0202" "0203" "0204" "0205" "0206" "0207" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x4600)++0x07
line.quad 0x00 "QOSMON_FIX_TRAFFIC_BANK$1,"
hexmask.quad.tbyte 0x00 40.--63. 1. "Reserved_40,Reserved These bits are always read as 0"
newline
hexmask.quad.quad 0x00 0.--39. 1. "traffic_fix,Bandwidth performance result of FIX"
repeat.end
repeat 16. (strings "0208" "0209" "0210" "0211" "0212" "0213" "0214" "0215" "0216" "0217" "0218" "0219" "0220" "0221" "0222" "0223" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x4680)++0x07
line.quad 0x00 "QOSMON_FIX_TRAFFIC_BANK$1,"
hexmask.quad.tbyte 0x00 40.--63. 1. "Reserved_40,Reserved These bits are always read as 0"
newline
hexmask.quad.quad 0x00 0.--39. 1. "traffic_fix,Bandwidth performance result of FIX"
repeat.end
repeat 16. (strings "0224" "0225" "0226" "0227" "0228" "0229" "0230" "0231" "0232" "0233" "0234" "0235" "0236" "0237" "0238" "0239" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x4700)++0x07
line.quad 0x00 "QOSMON_FIX_TRAFFIC_BANK$1,"
hexmask.quad.tbyte 0x00 40.--63. 1. "Reserved_40,Reserved These bits are always read as 0"
newline
hexmask.quad.quad 0x00 0.--39. 1. "traffic_fix,Bandwidth performance result of FIX"
repeat.end
repeat 16. (strings "0240" "0241" "0242" "0243" "0244" "0245" "0246" "0247" "0248" "0249" "0250" "0251" "0252" "0253" "0254" "0255" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x4780)++0x07
line.quad 0x00 "QOSMON_FIX_TRAFFIC_BANK$1,"
hexmask.quad.tbyte 0x00 40.--63. 1. "Reserved_40,Reserved These bits are always read as 0"
newline
hexmask.quad.quad 0x00 0.--39. 1. "traffic_fix,Bandwidth performance result of FIX"
repeat.end
repeat 16. (strings "10" "11" "12" "13" "14" "15" "16" "17" "18" "19" "110" "111" "112" "113" "114" "115" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x4800)++0x07
line.quad 0x00 "QOSMON_FIX_TRAFFIC_BANK$1,"
hexmask.quad.tbyte 0x00 40.--63. 1. "Reserved_40,Reserved These bits are always read as 0"
newline
hexmask.quad.quad 0x00 0.--39. 1. "traffic_fix,Bandwidth performance result of FIX"
repeat.end
repeat 16. (strings "116" "117" "118" "119" "120" "121" "122" "123" "124" "125" "126" "127" "128" "129" "130" "131" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x4880)++0x07
line.quad 0x00 "QOSMON_FIX_TRAFFIC_BANK$1,"
hexmask.quad.tbyte 0x00 40.--63. 1. "Reserved_40,Reserved These bits are always read as 0"
newline
hexmask.quad.quad 0x00 0.--39. 1. "traffic_fix,Bandwidth performance result of FIX"
repeat.end
repeat 16. (strings "132" "133" "134" "135" "136" "137" "138" "139" "140" "141" "142" "143" "144" "145" "146" "147" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x4900)++0x07
line.quad 0x00 "QOSMON_FIX_TRAFFIC_BANK$1,"
hexmask.quad.tbyte 0x00 40.--63. 1. "Reserved_40,Reserved These bits are always read as 0"
newline
hexmask.quad.quad 0x00 0.--39. 1. "traffic_fix,Bandwidth performance result of FIX"
repeat.end
repeat 16. (strings "148" "149" "150" "151" "152" "153" "154" "155" "156" "157" "158" "159" "160" "161" "162" "163" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x4980)++0x07
line.quad 0x00 "QOSMON_FIX_TRAFFIC_BANK$1,"
hexmask.quad.tbyte 0x00 40.--63. 1. "Reserved_40,Reserved These bits are always read as 0"
newline
hexmask.quad.quad 0x00 0.--39. 1. "traffic_fix,Bandwidth performance result of FIX"
repeat.end
repeat 16. (strings "164" "165" "166" "167" "168" "169" "170" "171" "172" "173" "174" "175" "176" "177" "178" "179" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x4A00)++0x07
line.quad 0x00 "QOSMON_FIX_TRAFFIC_BANK$1,"
hexmask.quad.tbyte 0x00 40.--63. 1. "Reserved_40,Reserved These bits are always read as 0"
newline
hexmask.quad.quad 0x00 0.--39. 1. "traffic_fix,Bandwidth performance result of FIX"
repeat.end
repeat 16. (strings "180" "181" "182" "183" "184" "185" "186" "187" "188" "189" "190" "191" "192" "193" "194" "195" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x4A80)++0x07
line.quad 0x00 "QOSMON_FIX_TRAFFIC_BANK$1,"
hexmask.quad.tbyte 0x00 40.--63. 1. "Reserved_40,Reserved These bits are always read as 0"
newline
hexmask.quad.quad 0x00 0.--39. 1. "traffic_fix,Bandwidth performance result of FIX"
repeat.end
repeat 16. (strings "196" "197" "198" "199" "1100" "1101" "1102" "1103" "1104" "1105" "1106" "1107" "1108" "1109" "1110" "1111" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x4B00)++0x07
line.quad 0x00 "QOSMON_FIX_TRAFFIC_BANK$1,"
hexmask.quad.tbyte 0x00 40.--63. 1. "Reserved_40,Reserved These bits are always read as 0"
newline
hexmask.quad.quad 0x00 0.--39. 1. "traffic_fix,Bandwidth performance result of FIX"
repeat.end
repeat 16. (strings "1112" "1113" "1114" "1115" "1116" "1117" "1118" "1119" "1120" "1121" "1122" "1123" "1124" "1125" "1126" "1127" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x4B80)++0x07
line.quad 0x00 "QOSMON_FIX_TRAFFIC_BANK$1,"
hexmask.quad.tbyte 0x00 40.--63. 1. "Reserved_40,Reserved These bits are always read as 0"
newline
hexmask.quad.quad 0x00 0.--39. 1. "traffic_fix,Bandwidth performance result of FIX"
repeat.end
repeat 16. (strings "1128" "1129" "1130" "1131" "1132" "1133" "1134" "1135" "1136" "1137" "1138" "1139" "1140" "1141" "1142" "1143" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x4C00)++0x07
line.quad 0x00 "QOSMON_FIX_TRAFFIC_BANK$1,"
hexmask.quad.tbyte 0x00 40.--63. 1. "Reserved_40,Reserved These bits are always read as 0"
newline
hexmask.quad.quad 0x00 0.--39. 1. "traffic_fix,Bandwidth performance result of FIX"
repeat.end
repeat 16. (strings "1144" "1145" "1146" "1147" "1148" "1149" "1150" "1151" "1152" "1153" "1154" "1155" "1156" "1157" "1158" "1159" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x4C80)++0x07
line.quad 0x00 "QOSMON_FIX_TRAFFIC_BANK$1,"
hexmask.quad.tbyte 0x00 40.--63. 1. "Reserved_40,Reserved These bits are always read as 0"
newline
hexmask.quad.quad 0x00 0.--39. 1. "traffic_fix,Bandwidth performance result of FIX"
repeat.end
repeat 16. (strings "1160" "1161" "1162" "1163" "1164" "1165" "1166" "1167" "1168" "1169" "1170" "1171" "1172" "1173" "1174" "1175" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x4D00)++0x07
line.quad 0x00 "QOSMON_FIX_TRAFFIC_BANK$1,"
hexmask.quad.tbyte 0x00 40.--63. 1. "Reserved_40,Reserved These bits are always read as 0"
newline
hexmask.quad.quad 0x00 0.--39. 1. "traffic_fix,Bandwidth performance result of FIX"
repeat.end
repeat 16. (strings "1176" "1177" "1178" "1179" "1180" "1181" "1182" "1183" "1184" "1185" "1186" "1187" "1188" "1189" "1190" "1191" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x4D80)++0x07
line.quad 0x00 "QOSMON_FIX_TRAFFIC_BANK$1,"
hexmask.quad.tbyte 0x00 40.--63. 1. "Reserved_40,Reserved These bits are always read as 0"
newline
hexmask.quad.quad 0x00 0.--39. 1. "traffic_fix,Bandwidth performance result of FIX"
repeat.end
repeat 16. (strings "1192" "1193" "1194" "1195" "1196" "1197" "1198" "1199" "1200" "1201" "1202" "1203" "1204" "1205" "1206" "1207" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x4E00)++0x07
line.quad 0x00 "QOSMON_FIX_TRAFFIC_BANK$1,"
hexmask.quad.tbyte 0x00 40.--63. 1. "Reserved_40,Reserved These bits are always read as 0"
newline
hexmask.quad.quad 0x00 0.--39. 1. "traffic_fix,Bandwidth performance result of FIX"
repeat.end
repeat 16. (strings "1208" "1209" "1210" "1211" "1212" "1213" "1214" "1215" "1216" "1217" "1218" "1219" "1220" "1221" "1222" "1223" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x4E80)++0x07
line.quad 0x00 "QOSMON_FIX_TRAFFIC_BANK$1,"
hexmask.quad.tbyte 0x00 40.--63. 1. "Reserved_40,Reserved These bits are always read as 0"
newline
hexmask.quad.quad 0x00 0.--39. 1. "traffic_fix,Bandwidth performance result of FIX"
repeat.end
repeat 16. (strings "1224" "1225" "1226" "1227" "1228" "1229" "1230" "1231" "1232" "1233" "1234" "1235" "1236" "1237" "1238" "1239" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x4F00)++0x07
line.quad 0x00 "QOSMON_FIX_TRAFFIC_BANK$1,"
hexmask.quad.tbyte 0x00 40.--63. 1. "Reserved_40,Reserved These bits are always read as 0"
newline
hexmask.quad.quad 0x00 0.--39. 1. "traffic_fix,Bandwidth performance result of FIX"
repeat.end
repeat 16. (strings "1240" "1241" "1242" "1243" "1244" "1245" "1246" "1247" "1248" "1249" "1250" "1251" "1252" "1253" "1254" "1255" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x4F80)++0x07
line.quad 0x00 "QOSMON_FIX_TRAFFIC_BANK$1,"
hexmask.quad.tbyte 0x00 40.--63. 1. "Reserved_40,Reserved These bits are always read as 0"
newline
hexmask.quad.quad 0x00 0.--39. 1. "traffic_fix,Bandwidth performance result of FIX"
repeat.end
repeat 16. (strings "00" "01" "02" "03" "04" "05" "06" "07" "08" "09" "010" "011" "012" "013" "014" "015" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x5000)++0x07
line.quad 0x00 "QOSMON_BE_TRAFFIC_BANK$1,"
hexmask.quad.tbyte 0x00 40.--63. 1. "Reserved_40,Reserved These bits are always read as 0"
newline
hexmask.quad.quad 0x00 0.--39. 1. "traffic_be,Bandwidth performance result of BE"
repeat.end
repeat 16. (strings "016" "017" "018" "019" "020" "021" "022" "023" "024" "025" "026" "027" "028" "029" "030" "031" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x5080)++0x07
line.quad 0x00 "QOSMON_BE_TRAFFIC_BANK$1,"
hexmask.quad.tbyte 0x00 40.--63. 1. "Reserved_40,Reserved These bits are always read as 0"
newline
hexmask.quad.quad 0x00 0.--39. 1. "traffic_be,Bandwidth performance result of BE"
repeat.end
repeat 16. (strings "032" "033" "034" "035" "036" "037" "038" "039" "040" "041" "042" "043" "044" "045" "046" "047" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x5100)++0x07
line.quad 0x00 "QOSMON_BE_TRAFFIC_BANK$1,"
hexmask.quad.tbyte 0x00 40.--63. 1. "Reserved_40,Reserved These bits are always read as 0"
newline
hexmask.quad.quad 0x00 0.--39. 1. "traffic_be,Bandwidth performance result of BE"
repeat.end
repeat 16. (strings "048" "049" "050" "051" "052" "053" "054" "055" "056" "057" "058" "059" "060" "061" "062" "063" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x5180)++0x07
line.quad 0x00 "QOSMON_BE_TRAFFIC_BANK$1,"
hexmask.quad.tbyte 0x00 40.--63. 1. "Reserved_40,Reserved These bits are always read as 0"
newline
hexmask.quad.quad 0x00 0.--39. 1. "traffic_be,Bandwidth performance result of BE"
repeat.end
repeat 16. (strings "064" "065" "066" "067" "068" "069" "070" "071" "072" "073" "074" "075" "076" "077" "078" "079" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x5200)++0x07
line.quad 0x00 "QOSMON_BE_TRAFFIC_BANK$1,"
hexmask.quad.tbyte 0x00 40.--63. 1. "Reserved_40,Reserved These bits are always read as 0"
newline
hexmask.quad.quad 0x00 0.--39. 1. "traffic_be,Bandwidth performance result of BE"
repeat.end
repeat 16. (strings "080" "081" "082" "083" "084" "085" "086" "087" "088" "089" "090" "091" "092" "093" "094" "095" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x5280)++0x07
line.quad 0x00 "QOSMON_BE_TRAFFIC_BANK$1,"
hexmask.quad.tbyte 0x00 40.--63. 1. "Reserved_40,Reserved These bits are always read as 0"
newline
hexmask.quad.quad 0x00 0.--39. 1. "traffic_be,Bandwidth performance result of BE"
repeat.end
repeat 16. (strings "096" "097" "098" "099" "0100" "0101" "0102" "0103" "0104" "0105" "0106" "0107" "0108" "0109" "0110" "0111" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x5300)++0x07
line.quad 0x00 "QOSMON_BE_TRAFFIC_BANK$1,"
hexmask.quad.tbyte 0x00 40.--63. 1. "Reserved_40,Reserved These bits are always read as 0"
newline
hexmask.quad.quad 0x00 0.--39. 1. "traffic_be,Bandwidth performance result of BE"
repeat.end
repeat 16. (strings "0112" "0113" "0114" "0115" "0116" "0117" "0118" "0119" "0120" "0121" "0122" "0123" "0124" "0125" "0126" "0127" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x5380)++0x07
line.quad 0x00 "QOSMON_BE_TRAFFIC_BANK$1,"
hexmask.quad.tbyte 0x00 40.--63. 1. "Reserved_40,Reserved These bits are always read as 0"
newline
hexmask.quad.quad 0x00 0.--39. 1. "traffic_be,Bandwidth performance result of BE"
repeat.end
repeat 16. (strings "0128" "0129" "0130" "0131" "0132" "0133" "0134" "0135" "0136" "0137" "0138" "0139" "0140" "0141" "0142" "0143" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x5400)++0x07
line.quad 0x00 "QOSMON_BE_TRAFFIC_BANK$1,"
hexmask.quad.tbyte 0x00 40.--63. 1. "Reserved_40,Reserved These bits are always read as 0"
newline
hexmask.quad.quad 0x00 0.--39. 1. "traffic_be,Bandwidth performance result of BE"
repeat.end
repeat 16. (strings "0144" "0145" "0146" "0147" "0148" "0149" "0150" "0151" "0152" "0153" "0154" "0155" "0156" "0157" "0158" "0159" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x5480)++0x07
line.quad 0x00 "QOSMON_BE_TRAFFIC_BANK$1,"
hexmask.quad.tbyte 0x00 40.--63. 1. "Reserved_40,Reserved These bits are always read as 0"
newline
hexmask.quad.quad 0x00 0.--39. 1. "traffic_be,Bandwidth performance result of BE"
repeat.end
repeat 16. (strings "0160" "0161" "0162" "0163" "0164" "0165" "0166" "0167" "0168" "0169" "0170" "0171" "0172" "0173" "0174" "0175" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x5500)++0x07
line.quad 0x00 "QOSMON_BE_TRAFFIC_BANK$1,"
hexmask.quad.tbyte 0x00 40.--63. 1. "Reserved_40,Reserved These bits are always read as 0"
newline
hexmask.quad.quad 0x00 0.--39. 1. "traffic_be,Bandwidth performance result of BE"
repeat.end
repeat 16. (strings "0176" "0177" "0178" "0179" "0180" "0181" "0182" "0183" "0184" "0185" "0186" "0187" "0188" "0189" "0190" "0191" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x5580)++0x07
line.quad 0x00 "QOSMON_BE_TRAFFIC_BANK$1,"
hexmask.quad.tbyte 0x00 40.--63. 1. "Reserved_40,Reserved These bits are always read as 0"
newline
hexmask.quad.quad 0x00 0.--39. 1. "traffic_be,Bandwidth performance result of BE"
repeat.end
repeat 16. (strings "0192" "0193" "0194" "0195" "0196" "0197" "0198" "0199" "0200" "0201" "0202" "0203" "0204" "0205" "0206" "0207" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x5600)++0x07
line.quad 0x00 "QOSMON_BE_TRAFFIC_BANK$1,"
hexmask.quad.tbyte 0x00 40.--63. 1. "Reserved_40,Reserved These bits are always read as 0"
newline
hexmask.quad.quad 0x00 0.--39. 1. "traffic_be,Bandwidth performance result of BE"
repeat.end
repeat 16. (strings "0208" "0209" "0210" "0211" "0212" "0213" "0214" "0215" "0216" "0217" "0218" "0219" "0220" "0221" "0222" "0223" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x5680)++0x07
line.quad 0x00 "QOSMON_BE_TRAFFIC_BANK$1,"
hexmask.quad.tbyte 0x00 40.--63. 1. "Reserved_40,Reserved These bits are always read as 0"
newline
hexmask.quad.quad 0x00 0.--39. 1. "traffic_be,Bandwidth performance result of BE"
repeat.end
repeat 16. (strings "0224" "0225" "0226" "0227" "0228" "0229" "0230" "0231" "0232" "0233" "0234" "0235" "0236" "0237" "0238" "0239" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x5700)++0x07
line.quad 0x00 "QOSMON_BE_TRAFFIC_BANK$1,"
hexmask.quad.tbyte 0x00 40.--63. 1. "Reserved_40,Reserved These bits are always read as 0"
newline
hexmask.quad.quad 0x00 0.--39. 1. "traffic_be,Bandwidth performance result of BE"
repeat.end
repeat 16. (strings "0240" "0241" "0242" "0243" "0244" "0245" "0246" "0247" "0248" "0249" "0250" "0251" "0252" "0253" "0254" "0255" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x5780)++0x07
line.quad 0x00 "QOSMON_BE_TRAFFIC_BANK$1,"
hexmask.quad.tbyte 0x00 40.--63. 1. "Reserved_40,Reserved These bits are always read as 0"
newline
hexmask.quad.quad 0x00 0.--39. 1. "traffic_be,Bandwidth performance result of BE"
repeat.end
repeat 16. (strings "10" "11" "12" "13" "14" "15" "16" "17" "18" "19" "110" "111" "112" "113" "114" "115" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x5800)++0x07
line.quad 0x00 "QOSMON_BE_TRAFFIC_BANK$1,"
hexmask.quad.tbyte 0x00 40.--63. 1. "Reserved_40,Reserved These bits are always read as 0"
newline
hexmask.quad.quad 0x00 0.--39. 1. "traffic_be,Bandwidth performance result of BE"
repeat.end
repeat 16. (strings "116" "117" "118" "119" "120" "121" "122" "123" "124" "125" "126" "127" "128" "129" "130" "131" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x5880)++0x07
line.quad 0x00 "QOSMON_BE_TRAFFIC_BANK$1,"
hexmask.quad.tbyte 0x00 40.--63. 1. "Reserved_40,Reserved These bits are always read as 0"
newline
hexmask.quad.quad 0x00 0.--39. 1. "traffic_be,Bandwidth performance result of BE"
repeat.end
repeat 16. (strings "132" "133" "134" "135" "136" "137" "138" "139" "140" "141" "142" "143" "144" "145" "146" "147" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x5900)++0x07
line.quad 0x00 "QOSMON_BE_TRAFFIC_BANK$1,"
hexmask.quad.tbyte 0x00 40.--63. 1. "Reserved_40,Reserved These bits are always read as 0"
newline
hexmask.quad.quad 0x00 0.--39. 1. "traffic_be,Bandwidth performance result of BE"
repeat.end
repeat 16. (strings "148" "149" "150" "151" "152" "153" "154" "155" "156" "157" "158" "159" "160" "161" "162" "163" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x5980)++0x07
line.quad 0x00 "QOSMON_BE_TRAFFIC_BANK$1,"
hexmask.quad.tbyte 0x00 40.--63. 1. "Reserved_40,Reserved These bits are always read as 0"
newline
hexmask.quad.quad 0x00 0.--39. 1. "traffic_be,Bandwidth performance result of BE"
repeat.end
repeat 16. (strings "164" "165" "166" "167" "168" "169" "170" "171" "172" "173" "174" "175" "176" "177" "178" "179" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x5A00)++0x07
line.quad 0x00 "QOSMON_BE_TRAFFIC_BANK$1,"
hexmask.quad.tbyte 0x00 40.--63. 1. "Reserved_40,Reserved These bits are always read as 0"
newline
hexmask.quad.quad 0x00 0.--39. 1. "traffic_be,Bandwidth performance result of BE"
repeat.end
repeat 16. (strings "180" "181" "182" "183" "184" "185" "186" "187" "188" "189" "190" "191" "192" "193" "194" "195" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x5A80)++0x07
line.quad 0x00 "QOSMON_BE_TRAFFIC_BANK$1,"
hexmask.quad.tbyte 0x00 40.--63. 1. "Reserved_40,Reserved These bits are always read as 0"
newline
hexmask.quad.quad 0x00 0.--39. 1. "traffic_be,Bandwidth performance result of BE"
repeat.end
repeat 16. (strings "196" "197" "198" "199" "1100" "1101" "1102" "1103" "1104" "1105" "1106" "1107" "1108" "1109" "1110" "1111" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x5B00)++0x07
line.quad 0x00 "QOSMON_BE_TRAFFIC_BANK$1,"
hexmask.quad.tbyte 0x00 40.--63. 1. "Reserved_40,Reserved These bits are always read as 0"
newline
hexmask.quad.quad 0x00 0.--39. 1. "traffic_be,Bandwidth performance result of BE"
repeat.end
repeat 16. (strings "1112" "1113" "1114" "1115" "1116" "1117" "1118" "1119" "1120" "1121" "1122" "1123" "1124" "1125" "1126" "1127" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x5B80)++0x07
line.quad 0x00 "QOSMON_BE_TRAFFIC_BANK$1,"
hexmask.quad.tbyte 0x00 40.--63. 1. "Reserved_40,Reserved These bits are always read as 0"
newline
hexmask.quad.quad 0x00 0.--39. 1. "traffic_be,Bandwidth performance result of BE"
repeat.end
repeat 16. (strings "1128" "1129" "1130" "1131" "1132" "1133" "1134" "1135" "1136" "1137" "1138" "1139" "1140" "1141" "1142" "1143" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x5C00)++0x07
line.quad 0x00 "QOSMON_BE_TRAFFIC_BANK$1,"
hexmask.quad.tbyte 0x00 40.--63. 1. "Reserved_40,Reserved These bits are always read as 0"
newline
hexmask.quad.quad 0x00 0.--39. 1. "traffic_be,Bandwidth performance result of BE"
repeat.end
repeat 16. (strings "1144" "1145" "1146" "1147" "1148" "1149" "1150" "1151" "1152" "1153" "1154" "1155" "1156" "1157" "1158" "1159" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x5C80)++0x07
line.quad 0x00 "QOSMON_BE_TRAFFIC_BANK$1,"
hexmask.quad.tbyte 0x00 40.--63. 1. "Reserved_40,Reserved These bits are always read as 0"
newline
hexmask.quad.quad 0x00 0.--39. 1. "traffic_be,Bandwidth performance result of BE"
repeat.end
repeat 16. (strings "1160" "1161" "1162" "1163" "1164" "1165" "1166" "1167" "1168" "1169" "1170" "1171" "1172" "1173" "1174" "1175" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x5D00)++0x07
line.quad 0x00 "QOSMON_BE_TRAFFIC_BANK$1,"
hexmask.quad.tbyte 0x00 40.--63. 1. "Reserved_40,Reserved These bits are always read as 0"
newline
hexmask.quad.quad 0x00 0.--39. 1. "traffic_be,Bandwidth performance result of BE"
repeat.end
repeat 16. (strings "1176" "1177" "1178" "1179" "1180" "1181" "1182" "1183" "1184" "1185" "1186" "1187" "1188" "1189" "1190" "1191" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x5D80)++0x07
line.quad 0x00 "QOSMON_BE_TRAFFIC_BANK$1,"
hexmask.quad.tbyte 0x00 40.--63. 1. "Reserved_40,Reserved These bits are always read as 0"
newline
hexmask.quad.quad 0x00 0.--39. 1. "traffic_be,Bandwidth performance result of BE"
repeat.end
repeat 16. (strings "1192" "1193" "1194" "1195" "1196" "1197" "1198" "1199" "1200" "1201" "1202" "1203" "1204" "1205" "1206" "1207" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x5E00)++0x07
line.quad 0x00 "QOSMON_BE_TRAFFIC_BANK$1,"
hexmask.quad.tbyte 0x00 40.--63. 1. "Reserved_40,Reserved These bits are always read as 0"
newline
hexmask.quad.quad 0x00 0.--39. 1. "traffic_be,Bandwidth performance result of BE"
repeat.end
repeat 16. (strings "1208" "1209" "1210" "1211" "1212" "1213" "1214" "1215" "1216" "1217" "1218" "1219" "1220" "1221" "1222" "1223" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x5E80)++0x07
line.quad 0x00 "QOSMON_BE_TRAFFIC_BANK$1,"
hexmask.quad.tbyte 0x00 40.--63. 1. "Reserved_40,Reserved These bits are always read as 0"
newline
hexmask.quad.quad 0x00 0.--39. 1. "traffic_be,Bandwidth performance result of BE"
repeat.end
repeat 16. (strings "1224" "1225" "1226" "1227" "1228" "1229" "1230" "1231" "1232" "1233" "1234" "1235" "1236" "1237" "1238" "1239" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x5F00)++0x07
line.quad 0x00 "QOSMON_BE_TRAFFIC_BANK$1,"
hexmask.quad.tbyte 0x00 40.--63. 1. "Reserved_40,Reserved These bits are always read as 0"
newline
hexmask.quad.quad 0x00 0.--39. 1. "traffic_be,Bandwidth performance result of BE"
repeat.end
repeat 16. (strings "1240" "1241" "1242" "1243" "1244" "1245" "1246" "1247" "1248" "1249" "1250" "1251" "1252" "1253" "1254" "1255" )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 )
group.quad ($2+0x5F80)++0x07
line.quad 0x00 "QOSMON_BE_TRAFFIC_BANK$1,"
hexmask.quad.tbyte 0x00 40.--63. 1. "Reserved_40,Reserved These bits are always read as 0"
newline
hexmask.quad.quad 0x00 0.--39. 1. "traffic_be,Bandwidth performance result of BE"
repeat.end
group.long 0x8000++0x03
line.long 0x00 "QOSCTRL_SL_INIT,Note: This register must be written during statqen bit of QOSCTRL_STATQC register is 0"
bitfld.long 0x00 28.--31. "Reserved_28,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 24.--27. "refsslot,refsslot Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 16.--19. "slotsslot,slotsslot Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--8. 1. "sslotclk,sslotclk Setting"
group.long 0x8004++0x03
line.long 0x00 "QOSCTRL_REF_ARS,Note: This register must be written during statqen bit of QOSCTRL_STATQC register is 0"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 16.--24. 1. "arbstopcycle,arbstopcycle Setting"
newline
hexmask.long.word 0x00 0.--15. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x8008++0x03
line.long 0x00 "QOSCTRL_STATQC,"
hexmask.long.tbyte 0x00 9.--31. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "refresh_mode,refresh_mode setting" "0,1"
newline
hexmask.long.byte 0x00 1.--7. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 0. "statqen,QOS control Enable" "0: Disable,1: Enable"
group.long 0x800C++0x03
line.long 0x00 "QOSCTRL_MEMBANK,Note: This register can be written regardless of statqen bit value of QOSCTRL_STATQC register"
hexmask.long.tbyte 0x00 9.--31. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 8. "exe_membank,Current using bank of QOSBW Status" "0: using QOSBW_FIX_QOS_BANK0 and..,1: using QOSBW_FIX_QOS_BANK1 and.."
newline
hexmask.long.byte 0x00 1.--7. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 0. "membank,Bank of QOSBW_FIX_QOS_BANK0 QOSBW_FIX_QOS_BANK1 QOSBW_BE_QOS_BANK0 and QOSBW_BE_QOS_BANK1 registers to control QOS Setting" "0: use QOSBW_FIX_QOS_BANK0 and QOSBW_BE_QOS_BANK0,1: use QOSBW_FIX_QOS_BANK1 and QOSBW_BE_QOS_BANK1"
group.long 0x8010++0x03
line.long 0x00 "QOSMON_PERFMON,"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 16. "preset,Performance monitor reset" "0,1"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "pm_bankchange,2Bank mode configuration" "0,1"
newline
hexmask.long.byte 0x00 1.--7. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 0. "pmen,Performance monitor enable" "0,1"
group.long 0x8018++0x03
line.long 0x00 "QOSMON_PMONINT,"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 24. "pm_overrun,Bandwidth performance monitor over run bit" "0,1"
newline
hexmask.long.byte 0x00 17.--23. 1. "Reserved_17,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 16. "pm_interrupt,Bandwidth performance monitor interrupt status" "0,1"
newline
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 0. "pbank,Bandwidth Monitor Bank bit status" "0,1"
group.long 0x801C++0x03
line.long 0x00 "QOSMON_PMONCHGTIME,"
hexmask.long 0x00 0.--31. 1. "sslotnum,Subslot period for bank change of bandwidth performance monitor"
group.long 0x8030++0x03
line.long 0x00 "QOSWT_WTEN,Note: This register must be written during statqen bit of QOSCTRL_STATQC register is 0"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 0. "wtbank_en,wtbank_en Enable" "0: Disable,1: Enable"
group.long 0x8034++0x03
line.long 0x00 "QOSWT_WTREF,Note: This register must be written during statqen bit of QOSCTRL_STATQC register is 0"
hexmask.long.word 0x00 16.--31. 1. "wtrefsslot1_enable,wtrefsslot1_enable Setting"
newline
hexmask.long.word 0x00 0.--15. 1. "wtrefsslot0_enable,wtrefsslot0_enable Setting"
group.long 0x8038++0x03
line.long 0x00 "QOSWT_WTSET0,Note: This register must be written during statqen bit of QOSCTRL_STATQC register is 0"
hexmask.long.word 0x00 16.--31. 1. "wtperiold0,wtperiod0 Setting"
newline
bitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "wtsslot0,wtsslot0 Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "wtslotsslot0,wtslotsslot0 Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x803C++0x03
line.long 0x00 "QOSWT_WTSET1,Note: This register must be written during statqen bit of QOSCTRL_STATQC register is 0"
hexmask.long.word 0x00 16.--31. 1. "wtperiold1,wtperiod1 Setting"
newline
bitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "wtsslot1,wtsslot1 Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "wtslotsslot1,wtslotsslot1 Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8040++0x03
line.long 0x00 "QOSCTRL_MBCS,"
hexmask.long.word 0x00 16.--31. 1. "bankchange_sslotnum1,Adjust Bank Switching Timing of QoS configuration"
newline
hexmask.long.word 0x00 0.--15. 1. "bankchange_sslotnum0,Adjust Bank Switching Timing of QoS configuration"
group.long 0x8044++0x03
line.long 0x00 "QOSCTRL_REF_ENBL,Note: This register must be written during statqen bit of QOSCTRL_STATQC register is 0"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--15. 1. "refssloten,refssloten Setting"
group.long 0x8048++0x03
line.long 0x00 "QOSWT_WTACC,Note: This register must be written during statqen bit of QOSCTRL_STATQC register is 0"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 0. "wtaccess_en,Output Enable for WT mode Set a provided value by Renesas on this bit" "0,1"
group.long 0x804C++0x03
line.long 0x00 "QOSCTRL_BWG,"
hexmask.long 0x00 3.--31. 1. "Reserved_3,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 0.--2. "FIXLSB,Bandwidth granularity of QoS setting" "0,1,2,3,4,5,6,7"
group.long 0x8090++0x03
line.long 0x00 "QOSMON_PMONAUTOOFFEN,"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 0. "pmon_autooff_en,Enable bit of auto disable function of bandwidth performance monitor" "0,1"
group.long 0x8094++0x03
line.long 0x00 "QOSMON_PMONAUTOOFFSSLOT,"
hexmask.long 0x00 0.--31. 1. "sslotnum,Subslot period for auto disable function of bandwidth performance monitor"
group.long 0xC000++0x03
line.long 0x00 "QOSMON_PMONTIME,"
hexmask.long 0x00 0.--31. 1. "sslocnt,Slobslot counter of bandwidth performance monitor"
group.long 0x10000++0x03
line.long 0x00 "QOSCTRL_RAS,Note: This register must be written during statqen bit of QOSCTRL_STATQC register is 0"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "EnumInit,EnumInit Setting"
group.long 0x10018++0x03
line.long 0x00 "QOSCTRL_RAEN,Note: This register must be written during statqen bit of QOSCTRL_STATQC register is 0"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 0. "RAllocEnable,RAllocEnable Enable" "0,1"
group.long 0x10030++0x03
line.long 0x00 "QOSCTRL_DANN_LOW,Note: This register must be written during statqen bit of QOSCTRL_STATQC register is 0"
bitfld.long 0x00 29.--31. "Reserved_29,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 24.--28. "DAccNodeNum_FIX3,DAccNodeNum_FIX3 Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 21.--23. "Reserved_21,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--20. "DAccNodeNum_FIX2,DAccNodeNum_FIX2 Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 13.--15. "Reserved_13,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 8.--12. "DAccNodeNum_FIX1,DAccNodeNum_FIX1 Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0.--4. "DAccNodeNum_FIX0,DAccNodeNum_FIX0 Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x10034++0x03
line.long 0x00 "QOSCTRL_DANN_HIGH,Note: This register must be written during statqen bit of QOSCTRL_STATQC register is 0"
bitfld.long 0x00 29.--31. "Reserved_29,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 24.--28. "DAccNodeNum_BE3,DAccNodeNum_BE3 Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 21.--23. "Reserved_21,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--20. "DAccNodeNum_BE2,DAccNodeNum_BE2 Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 13.--15. "Reserved_13,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 8.--12. "DAccNodeNum_BE1,DAccNodeNum_BE1 Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0.--4. "DAccNodeNum_BE0,DAccNodeNum_BE0 Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x10038++0x03
line.long 0x00 "QOSCTRL_DANT,Note: This register must be written during statqen bit of QOSCTRL_STATQC register is 0"
hexmask.long.word 0x00 23.--31. 1. "Reserved_23,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--22. 1. "DAccNodeThreshold2,DAccNodeThreshold2 Setting"
newline
bitfld.long 0x00 15. "Reserved_15,Reserved These bits are always read as 0" "0,1"
newline
hexmask.long.byte 0x00 8.--14. 1. "DAccNodeThreshold1,DAccNodeThreshold1 Setting"
newline
bitfld.long 0x00 7. "Reserved_7,Reserved These bits are always read as 0" "0,1"
newline
hexmask.long.byte 0x00 0.--6. 1. "DAccNodeThreshold0,DAccNodeThreshold0 Setting"
group.long 0x10040++0x03
line.long 0x00 "QOSCTRL_EMS_LOW,Note: This register must be written during statqen bit of QOSCTRL_STATQC register is 0"
bitfld.long 0x00 31. "Reserved_31,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 28.--30. "emaxschedule7,emaxschedule7 Setting" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 27. "Reserved_27,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 24.--26. "emaxschedule6,emaxschedule6 Setting" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 23. "Reserved_23,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 20.--22. "emaxschedule5,emaxschedule5 Setting" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 19. "Reserved_19,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 16.--18. "emaxschedule4,emaxschedule4 Setting" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15. "Reserved_15,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 12.--14. "emaxschedule3,emaxschedule3 Setting" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 11. "Reserved_11,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 8.--10. "emaxschedule2,emaxschedule2 Setting" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 7. "Reserved_7,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 4.--6. "emaxschedule1,emaxschedule1 Setting" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3. "Reserved_3,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0.--2. "emaxschedule0,emaxschedule0 Setting" "0,1,2,3,4,5,6,7"
group.long 0x10044++0x03
line.long 0x00 "QOSCTRL_EMS_HIGH,Note: This register must be written during statqen bit of QOSCTRL_STATQC register is 0"
bitfld.long 0x00 31. "Reserved_31,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 28.--30. "emaxschedule15,emaxschedule15 Setting" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 27. "Reserved_27,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 24.--26. "emaxschedule14,emaxschedule14 Setting" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 23. "Reserved_23,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 20.--22. "emaxschedule13,emaxschedule13 Setting" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 19. "Reserved_19,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 16.--18. "emaxschedule12,emaxschedule12 Setting" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15. "Reserved_15,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 12.--14. "emaxschedule11,emaxschedule11 Setting" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 11. "Reserved_11,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 8.--10. "emaxschedule10,emaxschedule10 Setting" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 7. "Reserved_7,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 4.--6. "emaxschedule9,emaxschedule9 Setting" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3. "Reserved_3,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0.--2. "emaxschedule8,emaxschedule8 Setting" "0,1,2,3,4,5,6,7"
group.long 0x10048++0x03
line.long 0x00 "QOSCTRL_FSS,"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved The write value should always be H'0080"
newline
hexmask.long.word 0x00 0.--15. 1. "Reserved_0,Functional safety setup"
group.long 0x10050++0x03
line.long 0x00 "QOSCTRL_INSFC,Note: This register must be written during statqen bit of QOSCTRL_STATQC register is 0"
hexmask.long.word 0x00 16.--31. 1. "insfclear_sslot,insfclear_sslot Setting"
newline
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 0. "insfclear_en,insfclear_en Enable" "0,1"
group.long 0x10060++0x03
line.long 0x00 "QOSCTRL_EARLYR,Note: This register must be written during statqen bit of QOSCTRL_STATQC register is 0"
hexmask.long 0x00 2.--31. 1. "Reserved_2,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 0.--1. "early_return_mode,early_return_mode Setting" "0,1,2,3"
group.long 0x10080++0x03
line.long 0x00 "QOSCTRL_RACNT0,Note: This register must be written during statqen bit of QOSCTRL_STATQC register is 0"
bitfld.long 0x00 26.--31. "Reserved_26,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 24.--25. "gpu_ticket_mode,gpu_ticket_mode Setting" "0,1,2,3"
newline
bitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 18.--19. "be_ticket_mask_cycle,be ticket_mask_cycle Setting" "0,1,2,3"
newline
bitfld.long 0x00 16.--17. "ticket_mask_cycle,ticket_mask_cycle Setting" "0,1,2,3"
newline
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 1. "swapin_inform_disable,swapin_inform_disable Setting" "0,1"
newline
bitfld.long 0x00 0. "beticket_mask_disable,beticket_mask_disable Setting" "0,1"
group.long 0x10088++0x03
line.long 0x00 "QOSCTRL_STATGEN0,Note: This register must be written during statqen bit of QOSCTRL_STATQC register is 0"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 12.--13. "vip_ticket_mode,vip_ticket_mode Setting" "0,1,2,3"
newline
bitfld.long 0x00 10.--11. "Reserved_10,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 8.--9. "imp_ticket_mode,imp_ticket_mode Setting" "0,1,2,3"
newline
bitfld.long 0x00 6.--7. "Reserved_6,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 4.--5. "cpu_ticket_mode,cpu_ticket_mode Setting" "0,1,2,3"
newline
bitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 0.--1. "gpu_ticket_mode,gpu_ticket_mode Setting" "0,1,2,3"
tree.end
tree "AXI_BUS_INST_1"
base ad:0x0
tree.end
tree "AXI_BUS_INST_2"
base ad:0xE6780000
group.long 0x4300++0x03
line.long 0x00 "MMCR,"
bitfld.long 0x00 31. "CTRL31,Bus Control 31 This bit should be setting the value which provided by Renesas" "0,1"
hexmask.long.word 0x00 17.--30. 1. "Reserved_17,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 16. "CTRL16,Bus Control 16 This bit should be setting the value which provided by Renesas" "0,1"
hexmask.long.word 0x00 6.--15. 1. "Reserved_6,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 5. "CTRL5,Bus Control 3 This bit should be setting the value which provided by Renesas" "0,1"
bitfld.long 0x00 4. "CTRL4,Bus Control 3 This bit should be setting the value which provided by Renesas" "0,1"
newline
bitfld.long 0x00 3. "CTRL3,Bus Control 3 This bit should be setting the value which provided by Renesas" "0,1"
bitfld.long 0x00 2. "CTRL2,Bus Control 3 This bit should be setting the value which provided by Renesas" "0,1"
newline
bitfld.long 0x00 0.--1. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3"
group.long 0x5300++0x03
line.long 0x00 "DUMMYERRCR,"
hexmask.long 0x00 6.--31. 1. "Reserved_6,Reserved These bits are always read as 0"
bitfld.long 0x00 5. "RGNERRINJ,Region ID Error Detection for ECM Injection" "0,1"
newline
bitfld.long 0x00 4. "SECERRINJ,Secure Error Detection for ECM Injection" "0,1"
bitfld.long 0x00 3. "EDCERRINJ,EDC Error Detection for ECM Injection" "0,1"
newline
bitfld.long 0x00 0.--2. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x6000)++0x03
line.long 0x00 "DPTDIVCR$1,"
hexmask.long.word 0x00 22.--31. 1. "Reserved_22,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--21. 1. "DIVADDR_37_16,Protection area division physical address [37:16]"
repeat.end
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x6040)++0x03
line.long 0x00 "DPTDIVCR$1,"
hexmask.long.word 0x00 22.--31. 1. "Reserved_22,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--21. 1. "DIVADDR_37_16,Protection area division physical address [37:16]"
repeat.end
repeat 16. (strings "32" "33" "34" "35" "36" "37" "38" "39" "40" "41" "42" "43" "44" "45" "46" "47" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x6080)++0x03
line.long 0x00 "DPTDIVCR$1,"
hexmask.long.word 0x00 22.--31. 1. "Reserved_22,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--21. 1. "DIVADDR_37_16,Protection area division physical address [37:16]"
repeat.end
repeat 15. (strings "48" "49" "50" "51" "52" "53" "54" "55" "56" "57" "58" "59" "60" "61" "62" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 )
group.long ($2+0x60C0)++0x03
line.long 0x00 "DPTDIVCR$1,"
hexmask.long.word 0x00 22.--31. 1. "Reserved_22,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--21. 1. "DIVADDR_37_16,Protection area division physical address [37:16]"
repeat.end
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x6100)++0x03
line.long 0x00 "DPTRGNCR$1,"
bitfld.long 0x00 31. "RGN15RP,RegionID15 Read Privilege Setting" "0: Has the privilege to Read to the relevant DRAM,1: Does not have the privilege Read to the.."
bitfld.long 0x00 30. "RGN14RP,RegionID14 Read Privilege Setting" "0: Has the privilege to Read to the relevant DRAM,1: Does not have the privilege Read to the.."
newline
bitfld.long 0x00 29. "RGN13RP,RegionID13 Read Privilege Setting" "0: Has the privilege to Read to the relevant DRAM,1: Does not have the privilege Read to the.."
bitfld.long 0x00 28. "RGN12RP,RegionID12 Read Privilege Setting" "0: Has the privilege to Read to the relevant DRAM,1: Does not have the privilege Read to the.."
newline
bitfld.long 0x00 27. "RGN11RP,RegionID11 Read Privilege Setting" "0: Has the privilege to Read to the relevant DRAM,1: Does not have the privilege Read to the.."
bitfld.long 0x00 26. "RGN10RP,RegionID10 Read Privilege Setting" "0: Has the privilege to Read to the relevant DRAM,1: Does not have the privilege Read to the.."
newline
bitfld.long 0x00 25. "RGN9RP,RegionID9 Read Privilege Setting" "0: Has the privilege to Read to the relevant DRAM,1: Does not have the privilege Read to the.."
bitfld.long 0x00 24. "RGN8RP,RegionID8 Read Privilege Setting" "0: Has the privilege to Read to the relevant DRAM,1: Does not have the privilege Read to the.."
newline
bitfld.long 0x00 23. "RGN7RP,RegionID7 Read Privilege Setting" "0: Has the privilege to Read to the relevant DRAM,1: Does not have the privilege Read to the.."
bitfld.long 0x00 22. "RGN6RP,RegionID6 Read Privilege Setting" "0: Has the privilege to Read to the relevant DRAM,1: Does not have the privilege Read to the.."
newline
bitfld.long 0x00 21. "RGN5RP,RegionID5 Read Privilege Setting" "0: Has the privilege to Read to the relevant DRAM,1: Does not have the privilege Read to the.."
bitfld.long 0x00 20. "RGN4RP,RegionID4 Read Privilege Setting" "0: Has the privilege to Read to the relevant DRAM,1: Does not have the privilege Read to the.."
newline
bitfld.long 0x00 19. "RGN3RP,RegionID3 Read Privilege Setting" "0: Has the privilege to Read to the relevant DRAM,1: Does not have the privilege Read to the.."
bitfld.long 0x00 18. "RGN2RP,RegionID2 Read Privilege Setting" "0: Has the privilege to Read to the relevant DRAM,1: Does not have the privilege Read to the.."
newline
bitfld.long 0x00 17. "RGN1RP,RegionID1 Read Privilege Setting" "0: Has the privilege to Read to the relevant DRAM,1: Does not have the privilege Read to the.."
bitfld.long 0x00 16. "RGN0RP,RegionID0 Read Privilege Setting" "0: Has the privilege to Read to the relevant DRAM,1: Does not have the privilege Read to the.."
newline
bitfld.long 0x00 15. "RGN15WP,RegionID15 Write Privilege Setting" "0: Has the privilege to write to the relevant DRAM,1: Does not have the privilege write to the"
bitfld.long 0x00 14. "RGN14WP,RegionID14 Write Privilege Setting" "0: Has the privilege to write to the relevant DRAM,1: Does not have the privilege write to the"
newline
bitfld.long 0x00 13. "RGN13WP,RegionID13 Write Privilege Setting" "0: Has the privilege to write to the relevant DRAM,1: Does not have the privilege write to the"
bitfld.long 0x00 12. "RGN12WP,RegionID12 Write Privilege Setting" "0: Has the privilege to write to the relevant DRAM,1: Does not have the privilege write to the"
newline
bitfld.long 0x00 11. "RGN11WP,RegionID11 Write Privilege Setting" "0: Has the privilege to write to the relevant DRAM,1: Does not have the privilege write to the"
bitfld.long 0x00 10. "RGN10WP,RegionID10 Write Privilege Setting" "0: Has the privilege to write to the relevant DRAM,1: Does not have the privilege write to the"
newline
bitfld.long 0x00 9. "RGN9WP,RegionID9 Write Privilege Setting" "0: Has the privilege to write to the relevant DRAM,1: Does not have the privilege write to the"
bitfld.long 0x00 8. "RGN8WP,RegionID8 Write Privilege Setting" "0: Has the privilege to write to the relevant DRAM,1: Does not have the privilege write to the"
newline
bitfld.long 0x00 7. "RGN7WP,RegionID7 Write Privilege Setting" "0: Has the privilege to write to the relevant DRAM,1: Does not have the privilege write to the"
bitfld.long 0x00 6. "RGN6WP,RegionID6 Write Privilege Setting" "0: Has the privilege to write to the relevant DRAM,1: Does not have the privilege write to the"
newline
bitfld.long 0x00 5. "RGN5WP,RegionID5 Write Privilege Setting" "0: Has the privilege to write to the relevant DRAM,1: Does not have the privilege write to the"
bitfld.long 0x00 4. "RGN4WP,RegionID4 Write Privilege Setting" "0: Has the privilege to write to the relevant DRAM,1: Does not have the privilege write to the"
newline
bitfld.long 0x00 3. "RGN3WP,RegionID3 Write Privilege Setting" "0: Has the privilege to write to the relevant DRAM,1: Does not have the privilege write to the"
bitfld.long 0x00 2. "RGN2WP,RegionID2 Write Privilege Setting" "0: Has the privilege to write to the relevant DRAM,1: Does not have the privilege write to the"
newline
bitfld.long 0x00 1. "RGN1WP,RegionID1 Write Privilege Setting" "0: Has the privilege to write to the relevant DRAM,1: Does not have the privilege write to the"
bitfld.long 0x00 0. "RGN0WP,RegionID0 Write Privilege Setting" "0: Has the privilege to write to the relevant DRAM,1: Does not have the privilege write to the"
repeat.end
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x6140)++0x03
line.long 0x00 "DPTRGNCR$1,"
bitfld.long 0x00 31. "RGN15RP,RegionID15 Read Privilege Setting" "0: Has the privilege to Read to the relevant DRAM,1: Does not have the privilege Read to the.."
bitfld.long 0x00 30. "RGN14RP,RegionID14 Read Privilege Setting" "0: Has the privilege to Read to the relevant DRAM,1: Does not have the privilege Read to the.."
newline
bitfld.long 0x00 29. "RGN13RP,RegionID13 Read Privilege Setting" "0: Has the privilege to Read to the relevant DRAM,1: Does not have the privilege Read to the.."
bitfld.long 0x00 28. "RGN12RP,RegionID12 Read Privilege Setting" "0: Has the privilege to Read to the relevant DRAM,1: Does not have the privilege Read to the.."
newline
bitfld.long 0x00 27. "RGN11RP,RegionID11 Read Privilege Setting" "0: Has the privilege to Read to the relevant DRAM,1: Does not have the privilege Read to the.."
bitfld.long 0x00 26. "RGN10RP,RegionID10 Read Privilege Setting" "0: Has the privilege to Read to the relevant DRAM,1: Does not have the privilege Read to the.."
newline
bitfld.long 0x00 25. "RGN9RP,RegionID9 Read Privilege Setting" "0: Has the privilege to Read to the relevant DRAM,1: Does not have the privilege Read to the.."
bitfld.long 0x00 24. "RGN8RP,RegionID8 Read Privilege Setting" "0: Has the privilege to Read to the relevant DRAM,1: Does not have the privilege Read to the.."
newline
bitfld.long 0x00 23. "RGN7RP,RegionID7 Read Privilege Setting" "0: Has the privilege to Read to the relevant DRAM,1: Does not have the privilege Read to the.."
bitfld.long 0x00 22. "RGN6RP,RegionID6 Read Privilege Setting" "0: Has the privilege to Read to the relevant DRAM,1: Does not have the privilege Read to the.."
newline
bitfld.long 0x00 21. "RGN5RP,RegionID5 Read Privilege Setting" "0: Has the privilege to Read to the relevant DRAM,1: Does not have the privilege Read to the.."
bitfld.long 0x00 20. "RGN4RP,RegionID4 Read Privilege Setting" "0: Has the privilege to Read to the relevant DRAM,1: Does not have the privilege Read to the.."
newline
bitfld.long 0x00 19. "RGN3RP,RegionID3 Read Privilege Setting" "0: Has the privilege to Read to the relevant DRAM,1: Does not have the privilege Read to the.."
bitfld.long 0x00 18. "RGN2RP,RegionID2 Read Privilege Setting" "0: Has the privilege to Read to the relevant DRAM,1: Does not have the privilege Read to the.."
newline
bitfld.long 0x00 17. "RGN1RP,RegionID1 Read Privilege Setting" "0: Has the privilege to Read to the relevant DRAM,1: Does not have the privilege Read to the.."
bitfld.long 0x00 16. "RGN0RP,RegionID0 Read Privilege Setting" "0: Has the privilege to Read to the relevant DRAM,1: Does not have the privilege Read to the.."
newline
bitfld.long 0x00 15. "RGN15WP,RegionID15 Write Privilege Setting" "0: Has the privilege to write to the relevant DRAM,1: Does not have the privilege write to the"
bitfld.long 0x00 14. "RGN14WP,RegionID14 Write Privilege Setting" "0: Has the privilege to write to the relevant DRAM,1: Does not have the privilege write to the"
newline
bitfld.long 0x00 13. "RGN13WP,RegionID13 Write Privilege Setting" "0: Has the privilege to write to the relevant DRAM,1: Does not have the privilege write to the"
bitfld.long 0x00 12. "RGN12WP,RegionID12 Write Privilege Setting" "0: Has the privilege to write to the relevant DRAM,1: Does not have the privilege write to the"
newline
bitfld.long 0x00 11. "RGN11WP,RegionID11 Write Privilege Setting" "0: Has the privilege to write to the relevant DRAM,1: Does not have the privilege write to the"
bitfld.long 0x00 10. "RGN10WP,RegionID10 Write Privilege Setting" "0: Has the privilege to write to the relevant DRAM,1: Does not have the privilege write to the"
newline
bitfld.long 0x00 9. "RGN9WP,RegionID9 Write Privilege Setting" "0: Has the privilege to write to the relevant DRAM,1: Does not have the privilege write to the"
bitfld.long 0x00 8. "RGN8WP,RegionID8 Write Privilege Setting" "0: Has the privilege to write to the relevant DRAM,1: Does not have the privilege write to the"
newline
bitfld.long 0x00 7. "RGN7WP,RegionID7 Write Privilege Setting" "0: Has the privilege to write to the relevant DRAM,1: Does not have the privilege write to the"
bitfld.long 0x00 6. "RGN6WP,RegionID6 Write Privilege Setting" "0: Has the privilege to write to the relevant DRAM,1: Does not have the privilege write to the"
newline
bitfld.long 0x00 5. "RGN5WP,RegionID5 Write Privilege Setting" "0: Has the privilege to write to the relevant DRAM,1: Does not have the privilege write to the"
bitfld.long 0x00 4. "RGN4WP,RegionID4 Write Privilege Setting" "0: Has the privilege to write to the relevant DRAM,1: Does not have the privilege write to the"
newline
bitfld.long 0x00 3. "RGN3WP,RegionID3 Write Privilege Setting" "0: Has the privilege to write to the relevant DRAM,1: Does not have the privilege write to the"
bitfld.long 0x00 2. "RGN2WP,RegionID2 Write Privilege Setting" "0: Has the privilege to write to the relevant DRAM,1: Does not have the privilege write to the"
newline
bitfld.long 0x00 1. "RGN1WP,RegionID1 Write Privilege Setting" "0: Has the privilege to write to the relevant DRAM,1: Does not have the privilege write to the"
bitfld.long 0x00 0. "RGN0WP,RegionID0 Write Privilege Setting" "0: Has the privilege to write to the relevant DRAM,1: Does not have the privilege write to the"
repeat.end
repeat 16. (strings "32" "33" "34" "35" "36" "37" "38" "39" "40" "41" "42" "43" "44" "45" "46" "47" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x6180)++0x03
line.long 0x00 "DPTRGNCR$1,"
bitfld.long 0x00 31. "RGN15RP,RegionID15 Read Privilege Setting" "0: Has the privilege to Read to the relevant DRAM,1: Does not have the privilege Read to the.."
bitfld.long 0x00 30. "RGN14RP,RegionID14 Read Privilege Setting" "0: Has the privilege to Read to the relevant DRAM,1: Does not have the privilege Read to the.."
newline
bitfld.long 0x00 29. "RGN13RP,RegionID13 Read Privilege Setting" "0: Has the privilege to Read to the relevant DRAM,1: Does not have the privilege Read to the.."
bitfld.long 0x00 28. "RGN12RP,RegionID12 Read Privilege Setting" "0: Has the privilege to Read to the relevant DRAM,1: Does not have the privilege Read to the.."
newline
bitfld.long 0x00 27. "RGN11RP,RegionID11 Read Privilege Setting" "0: Has the privilege to Read to the relevant DRAM,1: Does not have the privilege Read to the.."
bitfld.long 0x00 26. "RGN10RP,RegionID10 Read Privilege Setting" "0: Has the privilege to Read to the relevant DRAM,1: Does not have the privilege Read to the.."
newline
bitfld.long 0x00 25. "RGN9RP,RegionID9 Read Privilege Setting" "0: Has the privilege to Read to the relevant DRAM,1: Does not have the privilege Read to the.."
bitfld.long 0x00 24. "RGN8RP,RegionID8 Read Privilege Setting" "0: Has the privilege to Read to the relevant DRAM,1: Does not have the privilege Read to the.."
newline
bitfld.long 0x00 23. "RGN7RP,RegionID7 Read Privilege Setting" "0: Has the privilege to Read to the relevant DRAM,1: Does not have the privilege Read to the.."
bitfld.long 0x00 22. "RGN6RP,RegionID6 Read Privilege Setting" "0: Has the privilege to Read to the relevant DRAM,1: Does not have the privilege Read to the.."
newline
bitfld.long 0x00 21. "RGN5RP,RegionID5 Read Privilege Setting" "0: Has the privilege to Read to the relevant DRAM,1: Does not have the privilege Read to the.."
bitfld.long 0x00 20. "RGN4RP,RegionID4 Read Privilege Setting" "0: Has the privilege to Read to the relevant DRAM,1: Does not have the privilege Read to the.."
newline
bitfld.long 0x00 19. "RGN3RP,RegionID3 Read Privilege Setting" "0: Has the privilege to Read to the relevant DRAM,1: Does not have the privilege Read to the.."
bitfld.long 0x00 18. "RGN2RP,RegionID2 Read Privilege Setting" "0: Has the privilege to Read to the relevant DRAM,1: Does not have the privilege Read to the.."
newline
bitfld.long 0x00 17. "RGN1RP,RegionID1 Read Privilege Setting" "0: Has the privilege to Read to the relevant DRAM,1: Does not have the privilege Read to the.."
bitfld.long 0x00 16. "RGN0RP,RegionID0 Read Privilege Setting" "0: Has the privilege to Read to the relevant DRAM,1: Does not have the privilege Read to the.."
newline
bitfld.long 0x00 15. "RGN15WP,RegionID15 Write Privilege Setting" "0: Has the privilege to write to the relevant DRAM,1: Does not have the privilege write to the"
bitfld.long 0x00 14. "RGN14WP,RegionID14 Write Privilege Setting" "0: Has the privilege to write to the relevant DRAM,1: Does not have the privilege write to the"
newline
bitfld.long 0x00 13. "RGN13WP,RegionID13 Write Privilege Setting" "0: Has the privilege to write to the relevant DRAM,1: Does not have the privilege write to the"
bitfld.long 0x00 12. "RGN12WP,RegionID12 Write Privilege Setting" "0: Has the privilege to write to the relevant DRAM,1: Does not have the privilege write to the"
newline
bitfld.long 0x00 11. "RGN11WP,RegionID11 Write Privilege Setting" "0: Has the privilege to write to the relevant DRAM,1: Does not have the privilege write to the"
bitfld.long 0x00 10. "RGN10WP,RegionID10 Write Privilege Setting" "0: Has the privilege to write to the relevant DRAM,1: Does not have the privilege write to the"
newline
bitfld.long 0x00 9. "RGN9WP,RegionID9 Write Privilege Setting" "0: Has the privilege to write to the relevant DRAM,1: Does not have the privilege write to the"
bitfld.long 0x00 8. "RGN8WP,RegionID8 Write Privilege Setting" "0: Has the privilege to write to the relevant DRAM,1: Does not have the privilege write to the"
newline
bitfld.long 0x00 7. "RGN7WP,RegionID7 Write Privilege Setting" "0: Has the privilege to write to the relevant DRAM,1: Does not have the privilege write to the"
bitfld.long 0x00 6. "RGN6WP,RegionID6 Write Privilege Setting" "0: Has the privilege to write to the relevant DRAM,1: Does not have the privilege write to the"
newline
bitfld.long 0x00 5. "RGN5WP,RegionID5 Write Privilege Setting" "0: Has the privilege to write to the relevant DRAM,1: Does not have the privilege write to the"
bitfld.long 0x00 4. "RGN4WP,RegionID4 Write Privilege Setting" "0: Has the privilege to write to the relevant DRAM,1: Does not have the privilege write to the"
newline
bitfld.long 0x00 3. "RGN3WP,RegionID3 Write Privilege Setting" "0: Has the privilege to write to the relevant DRAM,1: Does not have the privilege write to the"
bitfld.long 0x00 2. "RGN2WP,RegionID2 Write Privilege Setting" "0: Has the privilege to write to the relevant DRAM,1: Does not have the privilege write to the"
newline
bitfld.long 0x00 1. "RGN1WP,RegionID1 Write Privilege Setting" "0: Has the privilege to write to the relevant DRAM,1: Does not have the privilege write to the"
bitfld.long 0x00 0. "RGN0WP,RegionID0 Write Privilege Setting" "0: Has the privilege to write to the relevant DRAM,1: Does not have the privilege write to the"
repeat.end
repeat 16. (strings "48" "49" "50" "51" "52" "53" "54" "55" "56" "57" "58" "59" "60" "61" "62" "63" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x61C0)++0x03
line.long 0x00 "DPTRGNCR$1,"
bitfld.long 0x00 31. "RGN15RP,RegionID15 Read Privilege Setting" "0: Has the privilege to Read to the relevant DRAM,1: Does not have the privilege Read to the.."
bitfld.long 0x00 30. "RGN14RP,RegionID14 Read Privilege Setting" "0: Has the privilege to Read to the relevant DRAM,1: Does not have the privilege Read to the.."
newline
bitfld.long 0x00 29. "RGN13RP,RegionID13 Read Privilege Setting" "0: Has the privilege to Read to the relevant DRAM,1: Does not have the privilege Read to the.."
bitfld.long 0x00 28. "RGN12RP,RegionID12 Read Privilege Setting" "0: Has the privilege to Read to the relevant DRAM,1: Does not have the privilege Read to the.."
newline
bitfld.long 0x00 27. "RGN11RP,RegionID11 Read Privilege Setting" "0: Has the privilege to Read to the relevant DRAM,1: Does not have the privilege Read to the.."
bitfld.long 0x00 26. "RGN10RP,RegionID10 Read Privilege Setting" "0: Has the privilege to Read to the relevant DRAM,1: Does not have the privilege Read to the.."
newline
bitfld.long 0x00 25. "RGN9RP,RegionID9 Read Privilege Setting" "0: Has the privilege to Read to the relevant DRAM,1: Does not have the privilege Read to the.."
bitfld.long 0x00 24. "RGN8RP,RegionID8 Read Privilege Setting" "0: Has the privilege to Read to the relevant DRAM,1: Does not have the privilege Read to the.."
newline
bitfld.long 0x00 23. "RGN7RP,RegionID7 Read Privilege Setting" "0: Has the privilege to Read to the relevant DRAM,1: Does not have the privilege Read to the.."
bitfld.long 0x00 22. "RGN6RP,RegionID6 Read Privilege Setting" "0: Has the privilege to Read to the relevant DRAM,1: Does not have the privilege Read to the.."
newline
bitfld.long 0x00 21. "RGN5RP,RegionID5 Read Privilege Setting" "0: Has the privilege to Read to the relevant DRAM,1: Does not have the privilege Read to the.."
bitfld.long 0x00 20. "RGN4RP,RegionID4 Read Privilege Setting" "0: Has the privilege to Read to the relevant DRAM,1: Does not have the privilege Read to the.."
newline
bitfld.long 0x00 19. "RGN3RP,RegionID3 Read Privilege Setting" "0: Has the privilege to Read to the relevant DRAM,1: Does not have the privilege Read to the.."
bitfld.long 0x00 18. "RGN2RP,RegionID2 Read Privilege Setting" "0: Has the privilege to Read to the relevant DRAM,1: Does not have the privilege Read to the.."
newline
bitfld.long 0x00 17. "RGN1RP,RegionID1 Read Privilege Setting" "0: Has the privilege to Read to the relevant DRAM,1: Does not have the privilege Read to the.."
bitfld.long 0x00 16. "RGN0RP,RegionID0 Read Privilege Setting" "0: Has the privilege to Read to the relevant DRAM,1: Does not have the privilege Read to the.."
newline
bitfld.long 0x00 15. "RGN15WP,RegionID15 Write Privilege Setting" "0: Has the privilege to write to the relevant DRAM,1: Does not have the privilege write to the"
bitfld.long 0x00 14. "RGN14WP,RegionID14 Write Privilege Setting" "0: Has the privilege to write to the relevant DRAM,1: Does not have the privilege write to the"
newline
bitfld.long 0x00 13. "RGN13WP,RegionID13 Write Privilege Setting" "0: Has the privilege to write to the relevant DRAM,1: Does not have the privilege write to the"
bitfld.long 0x00 12. "RGN12WP,RegionID12 Write Privilege Setting" "0: Has the privilege to write to the relevant DRAM,1: Does not have the privilege write to the"
newline
bitfld.long 0x00 11. "RGN11WP,RegionID11 Write Privilege Setting" "0: Has the privilege to write to the relevant DRAM,1: Does not have the privilege write to the"
bitfld.long 0x00 10. "RGN10WP,RegionID10 Write Privilege Setting" "0: Has the privilege to write to the relevant DRAM,1: Does not have the privilege write to the"
newline
bitfld.long 0x00 9. "RGN9WP,RegionID9 Write Privilege Setting" "0: Has the privilege to write to the relevant DRAM,1: Does not have the privilege write to the"
bitfld.long 0x00 8. "RGN8WP,RegionID8 Write Privilege Setting" "0: Has the privilege to write to the relevant DRAM,1: Does not have the privilege write to the"
newline
bitfld.long 0x00 7. "RGN7WP,RegionID7 Write Privilege Setting" "0: Has the privilege to write to the relevant DRAM,1: Does not have the privilege write to the"
bitfld.long 0x00 6. "RGN6WP,RegionID6 Write Privilege Setting" "0: Has the privilege to write to the relevant DRAM,1: Does not have the privilege write to the"
newline
bitfld.long 0x00 5. "RGN5WP,RegionID5 Write Privilege Setting" "0: Has the privilege to write to the relevant DRAM,1: Does not have the privilege write to the"
bitfld.long 0x00 4. "RGN4WP,RegionID4 Write Privilege Setting" "0: Has the privilege to write to the relevant DRAM,1: Does not have the privilege write to the"
newline
bitfld.long 0x00 3. "RGN3WP,RegionID3 Write Privilege Setting" "0: Has the privilege to write to the relevant DRAM,1: Does not have the privilege write to the"
bitfld.long 0x00 2. "RGN2WP,RegionID2 Write Privilege Setting" "0: Has the privilege to write to the relevant DRAM,1: Does not have the privilege write to the"
newline
bitfld.long 0x00 1. "RGN1WP,RegionID1 Write Privilege Setting" "0: Has the privilege to write to the relevant DRAM,1: Does not have the privilege write to the"
bitfld.long 0x00 0. "RGN0WP,RegionID0 Write Privilege Setting" "0: Has the privilege to write to the relevant DRAM,1: Does not have the privilege write to the"
repeat.end
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x6200)++0x03
line.long 0x00 "DPTSECCR$1,"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as 0"
bitfld.long 0x00 11. "SECG0RP,Reserved" "0,1"
newline
bitfld.long 0x00 10. "SECG1RP,Secure Group1 Read Privilege Setting" "0: Has the privilege to read to the relevant DRAM,1: Does not have the privilege read to the.."
bitfld.long 0x00 9. "SECG2RP,Reserved" "0,1"
newline
bitfld.long 0x00 8. "SECG3RP,Secure Group3 Read Privilege Setting" "0: Has the privilege to read to the relevant DRAM,1: Does not have the privilege read to the.."
bitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 3. "SECG0WP,Reserved" "0,1"
bitfld.long 0x00 2. "SECG1WP,Secure Group1 Write Privilege Setting" "0: Has the privilege to write to the relevant DRAM,1: Does not have the privilege write to the"
newline
bitfld.long 0x00 1. "SECG2WP,Reserved" "0,1"
bitfld.long 0x00 0. "SECG3WP,Secure Group3 Write Privilege Setting" "0: Has the privilege to write to the relevant DRAM,1: Does not have the privilege write to the"
repeat.end
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x6240)++0x03
line.long 0x00 "DPTSECCR$1,"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as 0"
bitfld.long 0x00 11. "SECG0RP,Reserved" "0,1"
newline
bitfld.long 0x00 10. "SECG1RP,Secure Group1 Read Privilege Setting" "0: Has the privilege to read to the relevant DRAM,1: Does not have the privilege read to the.."
bitfld.long 0x00 9. "SECG2RP,Reserved" "0,1"
newline
bitfld.long 0x00 8. "SECG3RP,Secure Group3 Read Privilege Setting" "0: Has the privilege to read to the relevant DRAM,1: Does not have the privilege read to the.."
bitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 3. "SECG0WP,Reserved" "0,1"
bitfld.long 0x00 2. "SECG1WP,Secure Group1 Write Privilege Setting" "0: Has the privilege to write to the relevant DRAM,1: Does not have the privilege write to the"
newline
bitfld.long 0x00 1. "SECG2WP,Reserved" "0,1"
bitfld.long 0x00 0. "SECG3WP,Secure Group3 Write Privilege Setting" "0: Has the privilege to write to the relevant DRAM,1: Does not have the privilege write to the"
repeat.end
repeat 16. (strings "32" "33" "34" "35" "36" "37" "38" "39" "40" "41" "42" "43" "44" "45" "46" "47" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x6280)++0x03
line.long 0x00 "DPTSECCR$1,"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as 0"
bitfld.long 0x00 11. "SECG0RP,Reserved" "0,1"
newline
bitfld.long 0x00 10. "SECG1RP,Secure Group1 Read Privilege Setting" "0: Has the privilege to read to the relevant DRAM,1: Does not have the privilege read to the.."
bitfld.long 0x00 9. "SECG2RP,Reserved" "0,1"
newline
bitfld.long 0x00 8. "SECG3RP,Secure Group3 Read Privilege Setting" "0: Has the privilege to read to the relevant DRAM,1: Does not have the privilege read to the.."
bitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 3. "SECG0WP,Reserved" "0,1"
bitfld.long 0x00 2. "SECG1WP,Secure Group1 Write Privilege Setting" "0: Has the privilege to write to the relevant DRAM,1: Does not have the privilege write to the"
newline
bitfld.long 0x00 1. "SECG2WP,Reserved" "0,1"
bitfld.long 0x00 0. "SECG3WP,Secure Group3 Write Privilege Setting" "0: Has the privilege to write to the relevant DRAM,1: Does not have the privilege write to the"
repeat.end
repeat 16. (strings "48" "49" "50" "51" "52" "53" "54" "55" "56" "57" "58" "59" "60" "61" "62" "63" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x62C0)++0x03
line.long 0x00 "DPTSECCR$1,"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as 0"
bitfld.long 0x00 11. "SECG0RP,Reserved" "0,1"
newline
bitfld.long 0x00 10. "SECG1RP,Secure Group1 Read Privilege Setting" "0: Has the privilege to read to the relevant DRAM,1: Does not have the privilege read to the.."
bitfld.long 0x00 9. "SECG2RP,Reserved" "0,1"
newline
bitfld.long 0x00 8. "SECG3RP,Secure Group3 Read Privilege Setting" "0: Has the privilege to read to the relevant DRAM,1: Does not have the privilege read to the.."
bitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 3. "SECG0WP,Reserved" "0,1"
bitfld.long 0x00 2. "SECG1WP,Secure Group1 Write Privilege Setting" "0: Has the privilege to write to the relevant DRAM,1: Does not have the privilege write to the"
newline
bitfld.long 0x00 1. "SECG2WP,Reserved" "0,1"
bitfld.long 0x00 0. "SECG3WP,Secure Group3 Write Privilege Setting" "0: Has the privilege to write to the relevant DRAM,1: Does not have the privilege write to the"
repeat.end
repeat 15. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 )
group.long ($2+0x6300)++0x03
line.long 0x00 "SPTDIVCR$1,"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--19. 1. "DIVADDR_31_12,protection division address is set"
repeat.end
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x6400)++0x03
line.long 0x00 "SPTRGNCR$1,"
bitfld.long 0x00 31. "RGN15RP,RegionID15 Read Privilege Setting" "0: Has the privilege to Read to the relevant,1: Does not have the privilege Read to the.."
bitfld.long 0x00 30. "RGN14RP,RegionID14 Read Privilege Setting" "0: Has the privilege to Read to the relevant,1: Does not have the privilege Read to the.."
newline
bitfld.long 0x00 29. "RGN13RP,RegionID13 Read Privilege Setting" "0: Has the privilege to Read to the relevant,1: Does not have the privilege Read to the.."
bitfld.long 0x00 28. "RGN12RP,RegionID12 Read Privilege Setting" "0: Has the privilege to Read to the relevant,1: Does not have the privilege Read to the.."
newline
bitfld.long 0x00 27. "RGN11RP,RegionID11 Read Privilege Setting" "0: Has the privilege to Read to the relevant,1: Does not have the privilege Read to the.."
bitfld.long 0x00 26. "RGN10RP,RegionID10 Read Privilege Setting" "0: Has the privilege to Read to the relevant,1: Does not have the privilege Read to the.."
newline
bitfld.long 0x00 25. "RGN9RP,RegionID9 Read Privilege Setting" "0: Has the privilege to Read to the relevant,1: Does not have the privilege Read to the.."
bitfld.long 0x00 24. "RGN8RP,RegionID8 Read Privilege Setting" "0: Has the privilege to Read to the relevant,1: Does not have the privilege Read to the.."
newline
bitfld.long 0x00 23. "RGN7RP,RegionID7 Read Privilege Setting" "0: Has the privilege to Read to the relevant,1: Does not have the privilege Read to the.."
bitfld.long 0x00 22. "RGN6RP,RegionID6 Read Privilege Setting" "0: Has the privilege to Read to the relevant,1: Does not have the privilege Read to the.."
newline
bitfld.long 0x00 21. "RGN5RP,RegionID5 Read Privilege Setting" "0: Has the privilege to Read to the relevant,1: Does not have the privilege Read to the.."
bitfld.long 0x00 20. "RGN4RP,RegionID4 Read Privilege Setting" "0: Has the privilege to Read to the relevant,1: Does not have the privilege Read to the.."
newline
bitfld.long 0x00 19. "RGN3RP,RegionID3 Read Privilege Setting" "0: Has the privilege to Read to the relevant,1: Does not have the privilege Read to the.."
bitfld.long 0x00 18. "RGN2RP,RegionID2 Read Privilege Setting" "0: Has the privilege to Read to the relevant,1: Does not have the privilege Read to the.."
newline
bitfld.long 0x00 17. "RGN1RP,RegionID1 Read Privilege Setting" "0: Has the privilege to Read to the relevant,1: Does not have the privilege Read to the.."
bitfld.long 0x00 16. "RGN0RP,RegionID0 Read Privilege Setting" "0: Has the privilege to Read to the relevant,1: Does not have the privilege Read to the.."
newline
bitfld.long 0x00 15. "RGN15WP,RegionID15 Write Privilege Setting" "0: Has the privilege to write to the relevant,1: Does not have the privilege write to the"
bitfld.long 0x00 14. "RGN14WP,RegionID14 Write Privilege Setting" "0: Has the privilege to write to the relevant,1: Does not have the privilege write to the"
newline
bitfld.long 0x00 13. "RGN13WP,RegionID13 Write Privilege Setting" "0: Has the privilege to write to the relevant,1: Does not have the privilege write to the"
bitfld.long 0x00 12. "RGN12WP,RegionID12 Write Privilege Setting" "0: Has the privilege to write to the relevant,1: Does not have the privilege write to the"
newline
bitfld.long 0x00 11. "RGN11WP,RegionID11 Write Privilege Setting" "0: Has the privilege to write to the relevant,1: Does not have the privilege write to the"
bitfld.long 0x00 10. "RGN10WP,RegionID10 Write Privilege Setting" "0: Has the privilege to write to the relevant,1: Does not have the privilege write to the"
newline
bitfld.long 0x00 9. "RGN9WP,RegionID9 Write Privilege Setting" "0: Has the privilege to write to the relevant,1: Does not have the privilege write to the"
bitfld.long 0x00 8. "RGN8WP,RegionID8 Write Privilege Setting" "0: Has the privilege to write to the relevant,1: Does not have the privilege write to the"
newline
bitfld.long 0x00 7. "RGN7WP,RegionID7 Write Privilege Setting" "0: Has the privilege to write to the relevant,1: Does not have the privilege write to the"
bitfld.long 0x00 6. "RGN6WP,RegionID6 Write Privilege Setting" "0: Has the privilege to write to the relevant,1: Does not have the privilege write to the"
newline
bitfld.long 0x00 5. "RGN5WP,RegionID5 Write Privilege Setting" "0: Has the privilege to write to the relevant,1: Does not have the privilege write to the"
bitfld.long 0x00 4. "RGN4WP,RegionID4 Write Privilege Setting" "0: Has the privilege to write to the relevant,1: Does not have the privilege write to the"
newline
bitfld.long 0x00 3. "RGN3WP,RegionID3 Write Privilege Setting" "0: Has the privilege to write to the relevant,1: Does not have the privilege write to the"
bitfld.long 0x00 2. "RGN2WP,RegionID2 Write Privilege Setting" "0: Has the privilege to write to the relevant,1: Does not have the privilege write to the"
newline
bitfld.long 0x00 1. "RGN1WP,RegionID1 Write Privilege Setting" "0: Has the privilege to write to the relevant,1: Does not have the privilege write to the"
bitfld.long 0x00 0. "RGN0WP,RegionID0 Write Privilege Setting" "0: Has the privilege to write to the relevant,1: Does not have the privilege write to the"
repeat.end
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x6500)++0x03
line.long 0x00 "SPTSECCR$1,"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as 0"
bitfld.long 0x00 11. "SECG0RP,Reserved" "0,1"
newline
bitfld.long 0x00 10. "SECG1RP,Secure Group1 Read Privilege Setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the.."
bitfld.long 0x00 9. "SECG2RP,Reserved" "0,1"
newline
bitfld.long 0x00 8. "SECG3RP,Secure Group3 Read Privilege Setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the.."
bitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 3. "SECG0WP,Reserved" "0,1"
bitfld.long 0x00 2. "SECG1WP,Secure Group1 Write Privilege Setting" "0: Has the privilege to write to the relevant,1: Does not have the privilege write to the"
newline
bitfld.long 0x00 1. "SECG2WP,Reserved" "0,1"
bitfld.long 0x00 0. "SECG3WP,Secure Group3 Write Privilege Setting" "0: Has the privilege to write to the relevant,1: Does not have the privilege write to the"
repeat.end
group.long 0x6600++0x03
line.long 0x00 "PTRGNCAUSER,"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are always read as 0"
eventfld.long 0x00 13. "MMU_RGNERR_R,Region ID Error detect of MMU read port" "0: No Error,1: Error"
newline
bitfld.long 0x00 12. "Reserved_12,Reserved These bits are always read as 0" "0,1"
eventfld.long 0x00 11. "CCI_RGNERR_R,Region ID Error detect of CCI read port" "0: No Error,1: Error"
newline
eventfld.long 0x00 10. "CCI_RGNERR_W,Region ID Error detect of CCI write port" "0: No Error,1: Error"
eventfld.long 0x00 9. "PERI_RGNERR_R,Region ID Error detect of PERI read port" "0: No Error,1: Error"
newline
eventfld.long 0x00 8. "PERI_RGNERR_W,Region ID Error detect of PERI write port" "0: No Error,1: Error"
eventfld.long 0x00 7. "MDA1_RGNERR_R,Region ID Error detect of MDA1 read port" "0: No Error,1: Error"
newline
eventfld.long 0x00 6. "MDA1_RGNERR_W,Region ID Error detect of MDA1 write port" "0: No Error,1: Error"
eventfld.long 0x00 5. "MDA0_RGNERR_R,Region ID Error detect of MDA0 read port" "0: No Error,1: Error"
newline
eventfld.long 0x00 4. "MDA0_RGNERR_W,Region ID Error detect of MDA0 write port" "0: No Error,1: Error"
eventfld.long 0x00 3. "U3DG1_RGNERR_R,Region ID Error detect of U3DG1 read port" "0: No Error,1: Error"
newline
eventfld.long 0x00 2. "U3DG1_RGNERR_W,Region ID Error detect of U3DG1 read port" "0: No Error,1: Error"
eventfld.long 0x00 1. "U3DG0_RGNERR_R,Region ID Error detect of U3DG0 read port" "0: No Error,1: Error"
newline
eventfld.long 0x00 0. "U3DG0_RGNERR_W,Region ID Error detect of U3DG0 write port" "0: No Error,1: Error"
group.long 0x6604++0x03
line.long 0x00 "PTSECCAUSER,"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are always read as 0"
eventfld.long 0x00 13. "MMU_SECERR_R,Secure Error detect of MMU read port" "0: No Error,1: Error"
newline
bitfld.long 0x00 12. "Reserved_12,Reserved These bits are always read as 0" "0,1"
eventfld.long 0x00 11. "CCI_SECERR_R,Secure Error detect of CCI read port" "0: No Error,1: Error"
newline
eventfld.long 0x00 10. "CCI_SECERR_W,Secure Error detect of CCI write port" "0: No Error,1: Error"
eventfld.long 0x00 9. "PERI_SECERR_R,Secure Error detect of PERI read port" "0: No Error,1: Error"
newline
eventfld.long 0x00 8. "PERI_SECERR_W,Secure Error detect of PERI write port" "0: No Error,1: Error"
eventfld.long 0x00 7. "MDA1_SECERR_R,Secure Error detect of MDA1 read port" "0: No Error,1: Error"
newline
eventfld.long 0x00 6. "MDA1_SECERR_W,Secure Error detect of MDA1 write port" "0: No Error,1: Error"
eventfld.long 0x00 5. "MDA0_SECERR_R,Secure Error detect of MDA0 read port" "0: No Error,1: Error"
newline
eventfld.long 0x00 4. "MDA0_SECERR_W,Secure Error detect of MDA0 write port" "0: No Error,1: Error"
eventfld.long 0x00 3. "U3DG1_SECERR_R,Secure Error detect of U3DG1 read port" "0: No Error,1: Error"
newline
eventfld.long 0x00 2. "U3DG1_SECERR_W,Secure Error detect of U3DG1 read port" "0: No Error,1: Error"
eventfld.long 0x00 1. "U3DG0_SECERR_R,Secure Error detect of U3DG0 read port" "0: No Error,1: Error"
newline
eventfld.long 0x00 0. "U3DG0_SECERR_W,Secure Error detect of U3DG0 write port" "0: No Error,1: Error"
group.long 0x6608++0x03
line.long 0x00 "PTRGNERRCR,"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are always read as 0"
eventfld.long 0x00 13. "MMU_RGNERR_INJ_R,Region ID Error injection of MMU read port" "0: No Error,1: Error"
newline
eventfld.long 0x00 12. "Reserved_12,Reserved These bits are always read as 0" "0,1"
eventfld.long 0x00 11. "CCI_RGNERR_INJ_R,Region ID Error injection of CCI read port" "0: No Error,1: Error"
newline
eventfld.long 0x00 10. "CCI_RGNERR_INJ_W,Region ID Error injection of CCI write port" "0: No Error,1: Error"
eventfld.long 0x00 9. "PERI_RGNERR_INJ_R,Region ID Error injection of PERI read port" "0: No Error,1: Error"
newline
eventfld.long 0x00 8. "PERI_RGNERR_INJ_W,Region ID Error injection of PERI write port" "0: No Error,1: Error"
eventfld.long 0x00 7. "MDA1_RGNERR_INJ_R,Region ID Error injection of MDA1 read port" "0: No Error,1: Error"
newline
eventfld.long 0x00 6. "MDA1_RGNERR_INJ_W,Region ID Error injection of MDA1 write port" "0: No Error,1: Error"
eventfld.long 0x00 5. "MDA0_RGNERR_INJ_R,Region ID Error injection of MDA0 read port" "0: No Error,1: Error"
newline
eventfld.long 0x00 4. "MDA0_RGNERR_INJ_W,Region ID Error injection of MDA0 write port" "0: No Error,1: Error"
eventfld.long 0x00 3. "U3DG1_RGNERR_INJ_R,Region ID Error injection of U3DG1 read port" "0: No Error,1: Error"
newline
eventfld.long 0x00 2. "U3DG1_RGNERR_INJ_W,Region ID Error injection of U3DG1 read port" "0: No Error,1: Error"
eventfld.long 0x00 1. "U3DG0_RGNERR_INJ_R,Region ID Error injection of U3DG0 read port" "0: No Error,1: Error"
newline
eventfld.long 0x00 0. "U3DG0_RGNERR_INJ_W,Region ID Error injection of U3DG0 write port" "0: No Error,1: Error"
group.long 0x660C++0x03
line.long 0x00 "PTSECERRCR,"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are always read as 0"
bitfld.long 0x00 13. "MMU_SECERR_INJ_R,Secure Error injection of MMU read port" "0: No Error,1: Error"
newline
bitfld.long 0x00 12. "Reserved_12,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 11. "CCI_SECERR_INJ_R,Secure Error injection of CCI read port" "0: No Error,1: Error"
newline
bitfld.long 0x00 10. "CCI_SECERR_INJ_W,Secure Error injection of CCI write port" "0: No Error,1: Error"
bitfld.long 0x00 9. "PERI_SECERR_INJ_R,Secure Error injection of PERI read port" "0: No Error,1: Error"
newline
bitfld.long 0x00 8. "PERI_SECERR_INJ_W,Secure Error injection of PERI write port" "0: No Error,1: Error"
bitfld.long 0x00 7. "MDA1_SECERR_INJ_R,Secure Error injection of MDA1 read port" "0: No Error,1: Error"
newline
bitfld.long 0x00 6. "MDA1_SECERR_INJ_W,Secure Error injection of MDA1 write port" "0: No Error,1: Error"
bitfld.long 0x00 5. "MDA0_SECERR_INJ_R,Secure Error injection of MDA0 read port" "0: No Error,1: Error"
newline
bitfld.long 0x00 4. "MDA0_SECERR_INJ_W,Secure Error injection of MDA0 write port" "0: No Error,1: Error"
bitfld.long 0x00 3. "U3DG1_SECERR_INJ_R,Secure Error injection of U3DG1 read port" "0: No Error,1: Error"
newline
bitfld.long 0x00 2. "U3DG1_SECERR_INJ_W,Secure Error injection of U3DG1 read port" "0: No Error,1: Error"
bitfld.long 0x00 1. "U3DG0_SECERR_INJ_R,Secure Error injection of U3DG0 read port" "0: No Error,1: Error"
newline
bitfld.long 0x00 0. "U3DG0_SECERR_INJ_W,Secure Error injection of U3DG0 write port" "0: No Error,1: Error"
repeat 7. (strings "0" "1" "2" "3" "4" "5" "6" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 )
group.long ($2+0x6610)++0x03
line.long 0x00 "PTRGNINF$1,"
hexmask.long 0x00 0.--31. 1. "ADR_W_37_6,Region ID Error Write Address"
repeat.end
repeat 7. (strings "7" "8" "9" "10" "11" "12" "13" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 )
group.long ($2+0x662C)++0x03
line.long 0x00 "PTRGNINF$1,"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SRCID_W_7_0,Region ID Error Write SRCID"
repeat.end
repeat 7. (strings "14" "15" "16" "17" "18" "19" "20" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 )
group.long ($2+0x6648)++0x03
line.long 0x00 "PTRGNINF$1,"
hexmask.long 0x00 0.--31. 1. "ADR_R_37_6,Region ID Error Read Address"
repeat.end
repeat 7. (strings "21" "22" "23" "24" "25" "26" "27" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 )
group.long ($2+0x6664)++0x03
line.long 0x00 "PTRGNINF$1,"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SRCID_R_7_0,Region ID Error Read SRCID"
repeat.end
repeat 7. (strings "0" "1" "2" "3" "4" "5" "6" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 )
group.long ($2+0x6680)++0x03
line.long 0x00 "PTSECINF$1,"
hexmask.long 0x00 0.--31. 1. "ADR_W_37_6,Secure Error Write Address"
repeat.end
repeat 7. (strings "7" "8" "9" "10" "11" "12" "13" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 )
group.long ($2+0x669C)++0x03
line.long 0x00 "PTSECINF$1,"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SRCID_W_7_0,Secure Error Write SRCID"
repeat.end
repeat 7. (strings "14" "15" "16" "17" "18" "19" "20" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 )
group.long ($2+0x66B8)++0x03
line.long 0x00 "PTSECINF$1,"
hexmask.long 0x00 0.--31. 1. "ADR_R_37_6,Secure Error Read Address"
repeat.end
repeat 7. (strings "21" "22" "23" "24" "25" "26" "27" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 )
group.long ($2+0x66D4)++0x03
line.long 0x00 "PTSECINF$1,"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SRCID_R_7_0,Secure Error Read SRCID"
repeat.end
group.long 0x6700++0x03
line.long 0x00 "EDCCAUSER,"
hexmask.long.word 0x00 22.--31. 1. "Reserved_22,Reserved These bits are always read as 0"
bitfld.long 0x00 21. "PWDATA_EDC_ERR,PWDATA EDC Error detection of APB I/F" "0,1"
newline
bitfld.long 0x00 20. "PADD_EDC_ERR,PADD EDC Error detection of APB I/F" "0,1"
bitfld.long 0x00 19. "Reserved_19,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 18. "NODE_INFERR_W,Node Inforamtion Error of AWch for SlaveBus access" "0,1"
bitfld.long 0x00 17. "NODE_INFERR_R,Node Inforamtion Error of ARch for SlaveBus access" "0,1"
newline
bitfld.long 0x00 16. "Reserved_16,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 15. "BSTID_ERR_R,BSTID error detect of SlaveBus(CCIS) read port" "0,1"
newline
bitfld.long 0x00 14. "RAM_EDC_ERR,EDC error detect of SRAM" "0,1"
bitfld.long 0x00 13. "MMU_EDCERR_R,EDC error detect of MMU read port" "0,1"
newline
bitfld.long 0x00 12. "Reserved_12,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 11. "CCI_EDCERR_R,EDC error detect of CCI read port" "0,1"
newline
bitfld.long 0x00 10. "CCI_EDCERR_W,EDC error detect of CCI write port" "0,1"
bitfld.long 0x00 9. "PERI_EDCERR_R,EDC error detect of PERI read port" "0,1"
newline
bitfld.long 0x00 8. "PERI_EDCERR_W,EDC error detect of PERI write port" "0,1"
bitfld.long 0x00 7. "MDA1_EDCERR_R,EDC error detect of MDA1 read port" "0,1"
newline
bitfld.long 0x00 6. "MDA1_EDCERR_W,EDC error detect of MDA1 write port" "0,1"
bitfld.long 0x00 5. "MDA0_EDCERR_R,EDC error detect of MDA0 read port" "0,1"
newline
bitfld.long 0x00 4. "MDA0_EDCERR_W,EDC error detect of MDA0 write port" "0,1"
bitfld.long 0x00 3. "RGX1_EDCERR_R,EDC error detect of RGX1 read port" "0,1"
newline
bitfld.long 0x00 2. "RGX1_EDCERR_W,EDC error detect of RGX1 write port" "0,1"
bitfld.long 0x00 1. "RGX0_EDCERR_R,EDC error detect of RGX0 read port" "0,1"
newline
bitfld.long 0x00 0. "RGX0_EDCERR_W,EDC error detect of RGX0 write port" "0,1"
group.long 0x6704++0x03
line.long 0x00 "EDCERRCR0,"
bitfld.long 0x00 28.--31. "Reserved_28,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 27. "MMU_EDCINJ_POST_R0,EDC error injection post of MMU read port" "0,1"
newline
bitfld.long 0x00 26. "MMU_EDCINJ_POST_R1,EDC error injection post of MMU read port" "0,1"
bitfld.long 0x00 24.--25. "Reserved_24,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 23. "CCI_EDCINJ_POST_R,EDC error injection post of CCI read port" "0,1"
bitfld.long 0x00 22. "CCI_EDCINJ_PRE_R,EDC error injection pre of CCI read port" "0,1"
newline
bitfld.long 0x00 21. "CCI_EDCINJ_POST_W,EDC error injection post of CCI write port" "0,1"
bitfld.long 0x00 20. "CCI_EDCINJ_PRE_W,EDC error injection pre of CCI write port" "0,1"
newline
bitfld.long 0x00 19. "PERI_EDCINJ_POST_R,EDC error injection post of PERI read port" "0,1"
bitfld.long 0x00 18. "PERI_EDCINJ_PRE_R,EDC error injection pre of PERI read port" "0,1"
newline
bitfld.long 0x00 17. "PERI_EDCINJ_POST_W,EDC error injection post of PERI write port" "0,1"
bitfld.long 0x00 16. "PERI_EDCINJ_PRE_W,EDC error injection pre of PERI write port" "0,1"
newline
bitfld.long 0x00 15. "MDA1_EDCINJ_POST_R,EDC error injection post of MDA1 read port" "0,1"
bitfld.long 0x00 14. "MDA1_EDCINJ_PRE_R,EDC error injection pre of MDA1 read port" "0,1"
newline
bitfld.long 0x00 13. "MDA1_EDCINJ_POST_W,EDC error injection post of MDA1 write port" "0,1"
bitfld.long 0x00 12. "MDA1_EDCINJ_PRE_W,EDC error injection pre of MDA1 write port" "0,1"
newline
bitfld.long 0x00 11. "MDA0_EDCINJ_POST_R,EDC error injection post of MDA0 read port" "0,1"
bitfld.long 0x00 10. "MDA0_EDCINJ_PRE_R,EDC error injection pre of MDA0 read port" "0,1"
newline
bitfld.long 0x00 9. "MDA0_EDCINJ_POST_W,EDC error injection post of MDA0 write port" "0,1"
bitfld.long 0x00 8. "MDA0_EDCINJ_PRE_W,EDC error injection pre of MDA0 write port" "0,1"
newline
bitfld.long 0x00 7. "RGX1_EDCINJ_POST_R,EDC error injection post of RGX1 read port" "0,1"
bitfld.long 0x00 6. "RGX1_EDCINJ_PRE_R,EDC error injection pre of RGX1 read port" "0,1"
newline
bitfld.long 0x00 5. "RGX1_EDCINJ_POST_W,EDC error injection post of RGX1 write port" "0,1"
bitfld.long 0x00 4. "RGX1_EDCINJ_PRE_W,EDC error injection pre of RGX1 write port" "0,1"
newline
bitfld.long 0x00 3. "RGX0_EDCINJ_POST_R,EDC error injection post of RGX0 read port" "0,1"
bitfld.long 0x00 2. "RGX0_EDCINJ_PRE_R,EDC error injection pre of RGX0 read port" "0,1"
newline
bitfld.long 0x00 1. "RGX0_EDCINJ_POST_W,EDC error injection post of RGX0 write port" "0,1"
bitfld.long 0x00 0. "RGX0_EDCINJ_PRE_W,EDC error injection pre of RGX0 write port" "0,1"
group.long 0x6708++0x03
line.long 0x00 "EDCERRCR1,"
hexmask.long 0x00 5.--31. 1. "Reserved_5,Reserved These bits are always read as 0"
bitfld.long 0x00 4. "NODE_ERRINJ_W,Node Info error injection for slave bus write access" "0,1"
newline
bitfld.long 0x00 3. "NODE_ERRINJ_R,Node Info error injection for slave bus read access" "0,1"
bitfld.long 0x00 2. "Reserved_2,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 1. "BSTID_ERRINJ_R,BSTID error injection of SlaveBus(CCIS) read port" "0,1"
bitfld.long 0x00 0. "RAM_EDCINJ,EDC error injection of SRAM" "0,1"
group.long 0x670C++0x03
line.long 0x00 "EDCERRCR2,"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved These bits are always read as 0"
bitfld.long 0x00 3. "PWDATA_EDCINJ_POST,PWDATA EDC error injection post of APB I/F" "0,1"
newline
bitfld.long 0x00 2. "PWDATA_EDCINJ_PRE,PWDATA EDC error injection pre of APB I/F" "0,1"
bitfld.long 0x00 1. "PADD_EDCINJ_POST,PADD EDC error injection post of APB I/F" "0,1"
newline
bitfld.long 0x00 0. "PADD_EDCINJ_PRE,PADD EDC error injection pre of APB I/F" "0,1"
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x6710)++0x03
line.long 0x00 "EDCERRINF$1,"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved"
hexmask.long.byte 0x00 0.--7. 1. "SRCIF_7_0,SRCID[7:0] of EDC Error"
repeat.end
repeat 3. (strings "16" "17" "18" )(list 0x00 0x04 0x08 )
group.long ($2+0x6750)++0x03
line.long 0x00 "EDCERRINF$1,"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved"
hexmask.long.byte 0x00 0.--7. 1. "SRCIF_7_0,SRCID[7:0] of EDC Error"
repeat.end
group.long 0x6800++0x03
line.long 0x00 "DCLSERRCR,"
hexmask.long 0x00 2.--31. 1. "Reserved_2,Reserved These bits are always read as 0"
bitfld.long 0x00 1. "DCLS_INJ_POST,DCLS error injection post" "0,1"
newline
bitfld.long 0x00 0. "DCLS_INJ_PRE,DCLS error injection pre" "0,1"
tree.end
tree "AXI_BUS_INST_3"
base ad:0xE67AC000
repeat 2. (strings "00" "01" )(list 0x0 0x4 )
group.long ($2+0x20)++0x03
line.long 0x00 "CCIQOS$1,Note: This register must be written during statqen bit of QOSCTRL_RAEN register is 0"
bitfld.long 0x00 28.--31. "Reserved_28,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 27. "CCIQOSEN,Set 1'b1 on this bit" "0,1"
hexmask.long 0x00 0.--26. 1. "Reserved_0,Reserved These bits are always read as 0"
repeat.end
repeat 4. (strings "10" "11" "12" "13" )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0x1000)++0x03
line.long 0x00 "CCIQOS$1,Note: This register must be written during statqen bit of QOSCTRL_RAEN register is 0"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CCIQOSEN,Set 1'b1 on this bit" "0,1"
repeat.end
tree.end
tree.end
tree "IPMMU"
tree "IPMMU_INST_0"
base ad:0xEE000000
group.long 0x480548++0x03
line.long 0x00 "IMERRSIDAR__RT0,This register indicates the Error SrcID when EDC error happen in AXI AR channel"
bitfld.long 0x00 31. "CLR," "0,1"
newline
hexmask.long.tbyte 0x00 8.--30. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "SRCID_7_0,Read : SrcID of error transaction"
group.long 0x48054C++0x03
line.long 0x00 "IMERRSIDR__RT0,This register indicates the Error SrcID when EDC error happen in AXI R channel"
bitfld.long 0x00 31. "CLR," "0,1"
newline
hexmask.long.tbyte 0x00 8.--30. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "SRCID_7_0,Read : SrcID of error transaction"
group.long 0x480558++0x03
line.long 0x00 "IMERRSIDNPTWAR__RT0,This register indicates the Error SrcID when EDC error happen in AXI AR channel with no Page Table Walk"
bitfld.long 0x00 31. "CLR," "0,1"
newline
hexmask.long.tbyte 0x00 8.--30. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "SRCID_7_0,Read : SrcID of error transaction"
group.long 0x480560++0x03
line.long 0x00 "IMAPQOS__RT0,This resister controls QoS value that is output from IPMMU(cache) to IPMMU(main) through ARADDR[35:32]"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 0.--3. "APQOS_3_0,Append QoS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x480564++0x03
line.long 0x00 "IMERRSIDRRESP__RT0,This register indicates the Error SrcID when EDC error happen in AXI R(response) channel"
bitfld.long 0x00 31. "CLR," "0,1"
newline
hexmask.long.tbyte 0x00 8.--30. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "SRCID_7_0,Read : SrcID of error transaction"
group.long 0x480568++0x03
line.long 0x00 "IMERRSIDPA__RT0,This register indicates the Error SrcID when EDC error happen in APB address channel"
bitfld.long 0x00 31. "CLR," "0,1"
newline
hexmask.long.tbyte 0x00 8.--30. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "SRCID_7_0,Read : SrcID of error transaction"
group.long 0x48056C++0x03
line.long 0x00 "IMERRSIDPWD__RT0,This register indicates the Error SrcID when EDC error happen in APB write data channel"
bitfld.long 0x00 31. "CLR," "0,1"
newline
hexmask.long.tbyte 0x00 8.--30. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "SRCID_7_0,Read : SrcID of error transaction"
group.long 0x480570++0x03
line.long 0x00 "IMRGID__RT0,Region-ID setting will be available for each IPMMU-hier (each bus hierarchy)"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 0.--3. "RGID_3_0,Region-ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x480574++0x03
line.long 0x00 "IMRGIDEN__RT0,This register is used for setting to protect IMRGID register"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--15. 1. "RGIDEN_15_0,When RGIDEN[PUSER[5:2]]=1 IMRGID[3:0] register can be accessed"
group.long 0x480578++0x03
line.long 0x00 "IMSECGRP__RT0,This register is used for setting to protect IMRGID register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 0. "SECGRP,When PUSER[1]=0 if SECGRP=1 RGID register can be accessed" "0,1"
group.long 0x481500++0x03
line.long 0x00 "IMSCTLR__RT0,This register controls the behavior of IPMMU function"
bitfld.long 0x00 31. "DISWPROT,Read and Write protection of MMU System Control Register and MMU auxiliary Control register" "0: can write IMSCTLR.NSACCEN & IMSCTLR.USE_SECGRP,1: can write/read IMSCTLR.NSACCEN &"
newline
bitfld.long 0x00 30. "NSACCEN,Non-secure access enable for MMU System Control Register and MMU auxiliary Control register" "0: disable non-secure access (default),1: enable non-secure access"
newline
bitfld.long 0x00 29. "DISMMU,Disable IPMMU cache" "0: enable IPMMU cache This bit can be set except,1: disable IPMMU cache"
newline
bitfld.long 0x00 28. "USE_SECGRP,Use security group to judge Secure/Non-secure access Set this bit in IPMMU-DS0 and IPMMU-RT1 0 before using this function" "0,1"
newline
hexmask.long 0x00 0.--27. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x481554++0x03
line.long 0x00 "ISERRINJR__RT0,IPMMU cache"
hexmask.long 0x00 7.--31. 1. "Reserved_7,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 6. "ERRINJ_EDCERR_PWD,Error injection bit for EDC error in APB write datta channel" "0: Clear error injection,1: Enable error injection"
newline
bitfld.long 0x00 5. "ERRINJ_EDCERR_PA,Error injection bit for EDC error in APB address channel" "0: Clear error injection,1: Enable error injection"
newline
bitfld.long 0x00 4. "ERRINJ_EDCERR_RRESP,Error injection bit for EDC error in AXI R response channel" "0: Clear error injection,1: Enable error injection"
newline
bitfld.long 0x00 3. "ERRINJ_EDCERR_NPTW_AR,Error injection bit for EDC error in AXI AR channel (during not Page Table Walk)" "0: Clear error injection,1: Enable error injection"
newline
bitfld.long 0x00 2. "ERRINJ_COMPFAIL,Error injection bit for DCLS error" "0: Clear error injection,1: Enable error injection"
newline
bitfld.long 0x00 1. "ERRINJ_EDCERR_R,Error injection bit for EDC error in AXI R channel" "0: Clear error injection,1: Enable error injection"
newline
bitfld.long 0x00 0. "ERRINJ_EDCERR_AR,Error injection bit for EDC error in AXI AR channel" "0: Clear error injection,1: Enable error injection"
group.long 0x481580++0x03
line.long 0x00 "IMPFMCTR__RT0,"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 12.--13. "MD_1_0,Monitor Mode IPMMU (cache)" "0: Monitor all MMUs,1: Reserved,2: Reserved,3: Monitor only MMUn (specified"
newline
bitfld.long 0x00 8.--11. "SEL_3_0,When MD is B'11 SEL indicates the MMU table number to be monitored" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 2.--7. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 1. "RST,Reset all status and counter values" "0,1"
newline
bitfld.long 0x00 0. "EN,Performance Monitor Enable" "0: Stop to count,1: Start to count All counters stop when"
group.long 0x481590++0x03
line.long 0x00 "IMPFMTOTAL__RT0,"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "TOTAL_23_0,The total number of translation requests"
group.long 0x481594++0x03
line.long 0x00 "IMPFMHIT__RT0,"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "HIT_23_0,The total number of TLB hit requests"
group.long 0x481598++0x03
line.long 0x00 "IMPFMMISS__RT0,"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MISS_23_0,The total number of miss requests"
group.long 0x482200++0x03
line.long 0x00 "IMPCTR__RT0,This register controls the behavior of the PMB function"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--7. "TTSEL_3_0,Translation Table Select Indicates the table number (MMU0  MMU15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 3. "TTEN,TLB Translation Enable" "0: Output PPN as a physical address,1: Output PPN as an intermediate physical address"
newline
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error..,1: Assert an interrupt when an error occurred"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 0. "PMBEN,PMB Enable" "0: PMB disabled,1: PMB enabled"
group.long 0x482208++0x03
line.long 0x00 "IMPSTR__RT0,This register indicates the error status of the address translation by PMB"
hexmask.long 0x00 5.--31. 1. "Reserved_5,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4. "MHIT,Multiple hit Indicate that multiple PMB hits occurred" "0,1"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "TF,Translation Fault This bit is set to 1 when a translation fault occurred during a PMB translation" "0,1"
group.long 0x48220C++0x03
line.long 0x00 "IMPEAR__RT0,This register indicates the address which an address translation error occurred"
hexmask.long 0x00 0.--31. 1. "EAR_31_0,The faulting virtual address is set when an address translation error occurred"
group.long 0x482280++0x03
line.long 0x00 "IMPMBA0__RT0,Note: n= 0 to 15 This register is used for setting the virtual page number"
hexmask.long.byte 0x00 24.--31. 1. "VPN_31_24,Virtual Page Number For 16-Mbyte page VPN[31:24] is used"
newline
hexmask.long.word 0x00 9.--23. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x482284++0x03
line.long 0x00 "IMPMBA1__RT0,Note: n= 0 to 15 This register is used for setting the virtual page number"
hexmask.long.byte 0x00 24.--31. 1. "VPN_31_24,Virtual Page Number For 16-Mbyte page VPN[31:24] is used"
newline
hexmask.long.word 0x00 9.--23. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x482288++0x03
line.long 0x00 "IMPMBA2__RT0,Note: n= 0 to 15 This register is used for setting the virtual page number"
hexmask.long.byte 0x00 24.--31. 1. "VPN_31_24,Virtual Page Number For 16-Mbyte page VPN[31:24] is used"
newline
hexmask.long.word 0x00 9.--23. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x48228C++0x03
line.long 0x00 "IMPMBA3__RT0,Note: n= 0 to 15 This register is used for setting the virtual page number"
hexmask.long.byte 0x00 24.--31. 1. "VPN_31_24,Virtual Page Number For 16-Mbyte page VPN[31:24] is used"
newline
hexmask.long.word 0x00 9.--23. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x482290++0x03
line.long 0x00 "IMPMBA4__RT0,Note: n= 0 to 15 This register is used for setting the virtual page number"
hexmask.long.byte 0x00 24.--31. 1. "VPN_31_24,Virtual Page Number For 16-Mbyte page VPN[31:24] is used"
newline
hexmask.long.word 0x00 9.--23. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x482294++0x03
line.long 0x00 "IMPMBA5__RT0,Note: n= 0 to 15 This register is used for setting the virtual page number"
hexmask.long.byte 0x00 24.--31. 1. "VPN_31_24,Virtual Page Number For 16-Mbyte page VPN[31:24] is used"
newline
hexmask.long.word 0x00 9.--23. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x482298++0x03
line.long 0x00 "IMPMBA6__RT0,Note: n= 0 to 15 This register is used for setting the virtual page number"
hexmask.long.byte 0x00 24.--31. 1. "VPN_31_24,Virtual Page Number For 16-Mbyte page VPN[31:24] is used"
newline
hexmask.long.word 0x00 9.--23. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x48229C++0x03
line.long 0x00 "IMPMBA7__RT0,Note: n= 0 to 15 This register is used for setting the virtual page number"
hexmask.long.byte 0x00 24.--31. 1. "VPN_31_24,Virtual Page Number For 16-Mbyte page VPN[31:24] is used"
newline
hexmask.long.word 0x00 9.--23. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x4822A0++0x03
line.long 0x00 "IMPMBA8__RT0,Note: n= 0 to 15 This register is used for setting the virtual page number"
hexmask.long.byte 0x00 24.--31. 1. "VPN_31_24,Virtual Page Number For 16-Mbyte page VPN[31:24] is used"
newline
hexmask.long.word 0x00 9.--23. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x4822A4++0x03
line.long 0x00 "IMPMBA9__RT0,Note: n= 0 to 15 This register is used for setting the virtual page number"
hexmask.long.byte 0x00 24.--31. 1. "VPN_31_24,Virtual Page Number For 16-Mbyte page VPN[31:24] is used"
newline
hexmask.long.word 0x00 9.--23. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x4822A8++0x03
line.long 0x00 "IMPMBA10__RT0,Note: n= 0 to 15 This register is used for setting the virtual page number"
hexmask.long.byte 0x00 24.--31. 1. "VPN_31_24,Virtual Page Number For 16-Mbyte page VPN[31:24] is used"
newline
hexmask.long.word 0x00 9.--23. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x4822AC++0x03
line.long 0x00 "IMPMBA11__RT0,Note: n= 0 to 15 This register is used for setting the virtual page number"
hexmask.long.byte 0x00 24.--31. 1. "VPN_31_24,Virtual Page Number For 16-Mbyte page VPN[31:24] is used"
newline
hexmask.long.word 0x00 9.--23. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x4822B0++0x03
line.long 0x00 "IMPMBA12__RT0,Note: n= 0 to 15 This register is used for setting the virtual page number"
hexmask.long.byte 0x00 24.--31. 1. "VPN_31_24,Virtual Page Number For 16-Mbyte page VPN[31:24] is used"
newline
hexmask.long.word 0x00 9.--23. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x4822B4++0x03
line.long 0x00 "IMPMBA13__RT0,Note: n= 0 to 15 This register is used for setting the virtual page number"
hexmask.long.byte 0x00 24.--31. 1. "VPN_31_24,Virtual Page Number For 16-Mbyte page VPN[31:24] is used"
newline
hexmask.long.word 0x00 9.--23. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x4822B8++0x03
line.long 0x00 "IMPMBA14__RT0,Note: n= 0 to 15 This register is used for setting the virtual page number"
hexmask.long.byte 0x00 24.--31. 1. "VPN_31_24,Virtual Page Number For 16-Mbyte page VPN[31:24] is used"
newline
hexmask.long.word 0x00 9.--23. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x4822BC++0x03
line.long 0x00 "IMPMBA15__RT0,Note: n= 0 to 15 This register is used for setting the virtual page number"
hexmask.long.byte 0x00 24.--31. 1. "VPN_31_24,Virtual Page Number For 16-Mbyte page VPN[31:24] is used"
newline
hexmask.long.word 0x00 9.--23. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x4822C0++0x03
line.long 0x00 "IMPMBD0__RT0,Note: n= 0 to 15 This register is used for setting the physical page number and the memory size which PMB managed"
hexmask.long.byte 0x00 24.--31. 1. "PPN_31_24,Physical Page Number For 16-Mbyte page PPN[31:24] is used"
newline
hexmask.long.byte 0x00 16.--23. 1. "PPN_39_32,Upper Physical Page Number"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
bitfld.long 0x00 7. "SZ_1,This bit and SZ[0] (bit 4) specify the page size" "0: 16-Mbyte page,1: 64-Mbyte page"
newline
rbitfld.long 0x00 5.--6. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 4. "SZ_0,Page Size See the description of SZ[1] (bit 7)" "0,1"
newline
bitfld.long 0x00 3. "C,Cache bit When this bit is set the request after address translation can be treated as cacheable request" "0,1"
newline
rbitfld.long 0x00 0.--2. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
group.long 0x4822C4++0x03
line.long 0x00 "IMPMBD1__RT0,Note: n= 0 to 15 This register is used for setting the physical page number and the memory size which PMB managed"
hexmask.long.byte 0x00 24.--31. 1. "PPN_31_24,Physical Page Number For 16-Mbyte page PPN[31:24] is used"
newline
hexmask.long.byte 0x00 16.--23. 1. "PPN_39_32,Upper Physical Page Number"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
bitfld.long 0x00 7. "SZ_1,This bit and SZ[0] (bit 4) specify the page size" "0: 16-Mbyte page,1: 64-Mbyte page"
newline
rbitfld.long 0x00 5.--6. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 4. "SZ_0,Page Size See the description of SZ[1] (bit 7)" "0,1"
newline
bitfld.long 0x00 3. "C,Cache bit When this bit is set the request after address translation can be treated as cacheable request" "0,1"
newline
rbitfld.long 0x00 0.--2. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
group.long 0x4822C8++0x03
line.long 0x00 "IMPMBD2__RT0,Note: n= 0 to 15 This register is used for setting the physical page number and the memory size which PMB managed"
hexmask.long.byte 0x00 24.--31. 1. "PPN_31_24,Physical Page Number For 16-Mbyte page PPN[31:24] is used"
newline
hexmask.long.byte 0x00 16.--23. 1. "PPN_39_32,Upper Physical Page Number"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
bitfld.long 0x00 7. "SZ_1,This bit and SZ[0] (bit 4) specify the page size" "0: 16-Mbyte page,1: 64-Mbyte page"
newline
rbitfld.long 0x00 5.--6. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 4. "SZ_0,Page Size See the description of SZ[1] (bit 7)" "0,1"
newline
bitfld.long 0x00 3. "C,Cache bit When this bit is set the request after address translation can be treated as cacheable request" "0,1"
newline
rbitfld.long 0x00 0.--2. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
group.long 0x4822CC++0x03
line.long 0x00 "IMPMBD3__RT0,Note: n= 0 to 15 This register is used for setting the physical page number and the memory size which PMB managed"
hexmask.long.byte 0x00 24.--31. 1. "PPN_31_24,Physical Page Number For 16-Mbyte page PPN[31:24] is used"
newline
hexmask.long.byte 0x00 16.--23. 1. "PPN_39_32,Upper Physical Page Number"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
bitfld.long 0x00 7. "SZ_1,This bit and SZ[0] (bit 4) specify the page size" "0: 16-Mbyte page,1: 64-Mbyte page"
newline
rbitfld.long 0x00 5.--6. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 4. "SZ_0,Page Size See the description of SZ[1] (bit 7)" "0,1"
newline
bitfld.long 0x00 3. "C,Cache bit When this bit is set the request after address translation can be treated as cacheable request" "0,1"
newline
rbitfld.long 0x00 0.--2. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
group.long 0x4822D0++0x03
line.long 0x00 "IMPMBD4__RT0,Note: n= 0 to 15 This register is used for setting the physical page number and the memory size which PMB managed"
hexmask.long.byte 0x00 24.--31. 1. "PPN_31_24,Physical Page Number For 16-Mbyte page PPN[31:24] is used"
newline
hexmask.long.byte 0x00 16.--23. 1. "PPN_39_32,Upper Physical Page Number"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
bitfld.long 0x00 7. "SZ_1,This bit and SZ[0] (bit 4) specify the page size" "0: 16-Mbyte page,1: 64-Mbyte page"
newline
rbitfld.long 0x00 5.--6. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 4. "SZ_0,Page Size See the description of SZ[1] (bit 7)" "0,1"
newline
bitfld.long 0x00 3. "C,Cache bit When this bit is set the request after address translation can be treated as cacheable request" "0,1"
newline
rbitfld.long 0x00 0.--2. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
group.long 0x4822D4++0x03
line.long 0x00 "IMPMBD5__RT0,Note: n= 0 to 15 This register is used for setting the physical page number and the memory size which PMB managed"
hexmask.long.byte 0x00 24.--31. 1. "PPN_31_24,Physical Page Number For 16-Mbyte page PPN[31:24] is used"
newline
hexmask.long.byte 0x00 16.--23. 1. "PPN_39_32,Upper Physical Page Number"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
bitfld.long 0x00 7. "SZ_1,This bit and SZ[0] (bit 4) specify the page size" "0: 16-Mbyte page,1: 64-Mbyte page"
newline
rbitfld.long 0x00 5.--6. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 4. "SZ_0,Page Size See the description of SZ[1] (bit 7)" "0,1"
newline
bitfld.long 0x00 3. "C,Cache bit When this bit is set the request after address translation can be treated as cacheable request" "0,1"
newline
rbitfld.long 0x00 0.--2. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
group.long 0x4822D8++0x03
line.long 0x00 "IMPMBD6__RT0,Note: n= 0 to 15 This register is used for setting the physical page number and the memory size which PMB managed"
hexmask.long.byte 0x00 24.--31. 1. "PPN_31_24,Physical Page Number For 16-Mbyte page PPN[31:24] is used"
newline
hexmask.long.byte 0x00 16.--23. 1. "PPN_39_32,Upper Physical Page Number"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
bitfld.long 0x00 7. "SZ_1,This bit and SZ[0] (bit 4) specify the page size" "0: 16-Mbyte page,1: 64-Mbyte page"
newline
rbitfld.long 0x00 5.--6. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 4. "SZ_0,Page Size See the description of SZ[1] (bit 7)" "0,1"
newline
bitfld.long 0x00 3. "C,Cache bit When this bit is set the request after address translation can be treated as cacheable request" "0,1"
newline
rbitfld.long 0x00 0.--2. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
group.long 0x4822DC++0x03
line.long 0x00 "IMPMBD7__RT0,Note: n= 0 to 15 This register is used for setting the physical page number and the memory size which PMB managed"
hexmask.long.byte 0x00 24.--31. 1. "PPN_31_24,Physical Page Number For 16-Mbyte page PPN[31:24] is used"
newline
hexmask.long.byte 0x00 16.--23. 1. "PPN_39_32,Upper Physical Page Number"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
bitfld.long 0x00 7. "SZ_1,This bit and SZ[0] (bit 4) specify the page size" "0: 16-Mbyte page,1: 64-Mbyte page"
newline
rbitfld.long 0x00 5.--6. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 4. "SZ_0,Page Size See the description of SZ[1] (bit 7)" "0,1"
newline
bitfld.long 0x00 3. "C,Cache bit When this bit is set the request after address translation can be treated as cacheable request" "0,1"
newline
rbitfld.long 0x00 0.--2. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
group.long 0x4822E0++0x03
line.long 0x00 "IMPMBD8__RT0,Note: n= 0 to 15 This register is used for setting the physical page number and the memory size which PMB managed"
hexmask.long.byte 0x00 24.--31. 1. "PPN_31_24,Physical Page Number For 16-Mbyte page PPN[31:24] is used"
newline
hexmask.long.byte 0x00 16.--23. 1. "PPN_39_32,Upper Physical Page Number"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
bitfld.long 0x00 7. "SZ_1,This bit and SZ[0] (bit 4) specify the page size" "0: 16-Mbyte page,1: 64-Mbyte page"
newline
rbitfld.long 0x00 5.--6. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 4. "SZ_0,Page Size See the description of SZ[1] (bit 7)" "0,1"
newline
bitfld.long 0x00 3. "C,Cache bit When this bit is set the request after address translation can be treated as cacheable request" "0,1"
newline
rbitfld.long 0x00 0.--2. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
group.long 0x4822E4++0x03
line.long 0x00 "IMPMBD9__RT0,Note: n= 0 to 15 This register is used for setting the physical page number and the memory size which PMB managed"
hexmask.long.byte 0x00 24.--31. 1. "PPN_31_24,Physical Page Number For 16-Mbyte page PPN[31:24] is used"
newline
hexmask.long.byte 0x00 16.--23. 1. "PPN_39_32,Upper Physical Page Number"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
bitfld.long 0x00 7. "SZ_1,This bit and SZ[0] (bit 4) specify the page size" "0: 16-Mbyte page,1: 64-Mbyte page"
newline
rbitfld.long 0x00 5.--6. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 4. "SZ_0,Page Size See the description of SZ[1] (bit 7)" "0,1"
newline
bitfld.long 0x00 3. "C,Cache bit When this bit is set the request after address translation can be treated as cacheable request" "0,1"
newline
rbitfld.long 0x00 0.--2. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
group.long 0x4822E8++0x03
line.long 0x00 "IMPMBD10__RT0,Note: n= 0 to 15 This register is used for setting the physical page number and the memory size which PMB managed"
hexmask.long.byte 0x00 24.--31. 1. "PPN_31_24,Physical Page Number For 16-Mbyte page PPN[31:24] is used"
newline
hexmask.long.byte 0x00 16.--23. 1. "PPN_39_32,Upper Physical Page Number"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
bitfld.long 0x00 7. "SZ_1,This bit and SZ[0] (bit 4) specify the page size" "0: 16-Mbyte page,1: 64-Mbyte page"
newline
rbitfld.long 0x00 5.--6. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 4. "SZ_0,Page Size See the description of SZ[1] (bit 7)" "0,1"
newline
bitfld.long 0x00 3. "C,Cache bit When this bit is set the request after address translation can be treated as cacheable request" "0,1"
newline
rbitfld.long 0x00 0.--2. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
group.long 0x4822EC++0x03
line.long 0x00 "IMPMBD11__RT0,Note: n= 0 to 15 This register is used for setting the physical page number and the memory size which PMB managed"
hexmask.long.byte 0x00 24.--31. 1. "PPN_31_24,Physical Page Number For 16-Mbyte page PPN[31:24] is used"
newline
hexmask.long.byte 0x00 16.--23. 1. "PPN_39_32,Upper Physical Page Number"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
bitfld.long 0x00 7. "SZ_1,This bit and SZ[0] (bit 4) specify the page size" "0: 16-Mbyte page,1: 64-Mbyte page"
newline
rbitfld.long 0x00 5.--6. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 4. "SZ_0,Page Size See the description of SZ[1] (bit 7)" "0,1"
newline
bitfld.long 0x00 3. "C,Cache bit When this bit is set the request after address translation can be treated as cacheable request" "0,1"
newline
rbitfld.long 0x00 0.--2. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
group.long 0x4822F0++0x03
line.long 0x00 "IMPMBD12__RT0,Note: n= 0 to 15 This register is used for setting the physical page number and the memory size which PMB managed"
hexmask.long.byte 0x00 24.--31. 1. "PPN_31_24,Physical Page Number For 16-Mbyte page PPN[31:24] is used"
newline
hexmask.long.byte 0x00 16.--23. 1. "PPN_39_32,Upper Physical Page Number"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
bitfld.long 0x00 7. "SZ_1,This bit and SZ[0] (bit 4) specify the page size" "0: 16-Mbyte page,1: 64-Mbyte page"
newline
rbitfld.long 0x00 5.--6. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 4. "SZ_0,Page Size See the description of SZ[1] (bit 7)" "0,1"
newline
bitfld.long 0x00 3. "C,Cache bit When this bit is set the request after address translation can be treated as cacheable request" "0,1"
newline
rbitfld.long 0x00 0.--2. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
group.long 0x4822F4++0x03
line.long 0x00 "IMPMBD13__RT0,Note: n= 0 to 15 This register is used for setting the physical page number and the memory size which PMB managed"
hexmask.long.byte 0x00 24.--31. 1. "PPN_31_24,Physical Page Number For 16-Mbyte page PPN[31:24] is used"
newline
hexmask.long.byte 0x00 16.--23. 1. "PPN_39_32,Upper Physical Page Number"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
bitfld.long 0x00 7. "SZ_1,This bit and SZ[0] (bit 4) specify the page size" "0: 16-Mbyte page,1: 64-Mbyte page"
newline
rbitfld.long 0x00 5.--6. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 4. "SZ_0,Page Size See the description of SZ[1] (bit 7)" "0,1"
newline
bitfld.long 0x00 3. "C,Cache bit When this bit is set the request after address translation can be treated as cacheable request" "0,1"
newline
rbitfld.long 0x00 0.--2. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
group.long 0x4822F8++0x03
line.long 0x00 "IMPMBD14__RT0,Note: n= 0 to 15 This register is used for setting the physical page number and the memory size which PMB managed"
hexmask.long.byte 0x00 24.--31. 1. "PPN_31_24,Physical Page Number For 16-Mbyte page PPN[31:24] is used"
newline
hexmask.long.byte 0x00 16.--23. 1. "PPN_39_32,Upper Physical Page Number"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
bitfld.long 0x00 7. "SZ_1,This bit and SZ[0] (bit 4) specify the page size" "0: 16-Mbyte page,1: 64-Mbyte page"
newline
rbitfld.long 0x00 5.--6. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 4. "SZ_0,Page Size See the description of SZ[1] (bit 7)" "0,1"
newline
bitfld.long 0x00 3. "C,Cache bit When this bit is set the request after address translation can be treated as cacheable request" "0,1"
newline
rbitfld.long 0x00 0.--2. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
group.long 0x4822FC++0x03
line.long 0x00 "IMPMBD15__RT0,Note: n= 0 to 15 This register is used for setting the physical page number and the memory size which PMB managed"
hexmask.long.byte 0x00 24.--31. 1. "PPN_31_24,Physical Page Number For 16-Mbyte page PPN[31:24] is used"
newline
hexmask.long.byte 0x00 16.--23. 1. "PPN_39_32,Upper Physical Page Number"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
bitfld.long 0x00 7. "SZ_1,This bit and SZ[0] (bit 4) specify the page size" "0: 16-Mbyte page,1: 64-Mbyte page"
newline
rbitfld.long 0x00 5.--6. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 4. "SZ_0,Page Size See the description of SZ[1] (bit 7)" "0,1"
newline
bitfld.long 0x00 3. "C,Cache bit When this bit is set the request after address translation can be treated as cacheable request" "0,1"
newline
rbitfld.long 0x00 0.--2. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
group.long 0x483300++0x03
line.long 0x00 "IMUCTR0__RT0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x483308++0x03
line.long 0x00 "IMUASID0__RT0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x483310++0x03
line.long 0x00 "IMUCTR1__RT0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x483318++0x03
line.long 0x00 "IMUASID1__RT0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x483320++0x03
line.long 0x00 "IMUCTR2__RT0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x483328++0x03
line.long 0x00 "IMUASID2__RT0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x483330++0x03
line.long 0x00 "IMUCTR3__RT0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x483338++0x03
line.long 0x00 "IMUASID3__RT0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x483340++0x03
line.long 0x00 "IMUCTR4__RT0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x483348++0x03
line.long 0x00 "IMUASID4__RT0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x483350++0x03
line.long 0x00 "IMUCTR5__RT0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x483358++0x03
line.long 0x00 "IMUASID5__RT0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x483360++0x03
line.long 0x00 "IMUCTR6__RT0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x483368++0x03
line.long 0x00 "IMUASID6__RT0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x483370++0x03
line.long 0x00 "IMUCTR7__RT0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x483378++0x03
line.long 0x00 "IMUASID7__RT0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x483380++0x03
line.long 0x00 "IMUCTR8__RT0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x483388++0x03
line.long 0x00 "IMUASID8__RT0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x483390++0x03
line.long 0x00 "IMUCTR9__RT0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x483398++0x03
line.long 0x00 "IMUASID9__RT0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4833A0++0x03
line.long 0x00 "IMUCTR10__RT0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4833A8++0x03
line.long 0x00 "IMUASID10__RT0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4833B0++0x03
line.long 0x00 "IMUCTR11__RT0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4833B8++0x03
line.long 0x00 "IMUASID11__RT0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4833C0++0x03
line.long 0x00 "IMUCTR12__RT0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4833C8++0x03
line.long 0x00 "IMUASID12__RT0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4833D0++0x03
line.long 0x00 "IMUCTR13__RT0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4833D8++0x03
line.long 0x00 "IMUASID13__RT0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4833E0++0x03
line.long 0x00 "IMUCTR14__RT0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4833E8++0x03
line.long 0x00 "IMUASID14__RT0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4833F0++0x03
line.long 0x00 "IMUCTR15__RT0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4833F8++0x03
line.long 0x00 "IMUASID15__RT0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x483400++0x03
line.long 0x00 "IMUCTR16__RT0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x483408++0x03
line.long 0x00 "IMUASID16__RT0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x483410++0x03
line.long 0x00 "IMUCTR17__RT0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x483418++0x03
line.long 0x00 "IMUASID17__RT0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x483420++0x03
line.long 0x00 "IMUCTR18__RT0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x483428++0x03
line.long 0x00 "IMUASID18__RT0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x483430++0x03
line.long 0x00 "IMUCTR19__RT0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x483438++0x03
line.long 0x00 "IMUASID19__RT0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x483440++0x03
line.long 0x00 "IMUCTR20__RT0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x483448++0x03
line.long 0x00 "IMUASID20__RT0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x483450++0x03
line.long 0x00 "IMUCTR21__RT0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x483458++0x03
line.long 0x00 "IMUASID21__RT0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x483460++0x03
line.long 0x00 "IMUCTR22__RT0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x483468++0x03
line.long 0x00 "IMUASID22__RT0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x483470++0x03
line.long 0x00 "IMUCTR23__RT0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x483478++0x03
line.long 0x00 "IMUASID23__RT0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x483480++0x03
line.long 0x00 "IMUCTR24__RT0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x483488++0x03
line.long 0x00 "IMUASID24__RT0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x483490++0x03
line.long 0x00 "IMUCTR25__RT0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x483498++0x03
line.long 0x00 "IMUASID25__RT0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4834A0++0x03
line.long 0x00 "IMUCTR26__RT0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4834A8++0x03
line.long 0x00 "IMUASID26__RT0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4834B0++0x03
line.long 0x00 "IMUCTR27__RT0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4834B8++0x03
line.long 0x00 "IMUASID27__RT0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4834C0++0x03
line.long 0x00 "IMUCTR28__RT0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4834C8++0x03
line.long 0x00 "IMUASID28__RT0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4834D0++0x03
line.long 0x00 "IMUCTR29__RT0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4834D8++0x03
line.long 0x00 "IMUASID29__RT0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4834E0++0x03
line.long 0x00 "IMUCTR30__RT0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4834E8++0x03
line.long 0x00 "IMUASID30__RT0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4834F0++0x03
line.long 0x00 "IMUCTR31__RT0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4834F8++0x03
line.long 0x00 "IMUASID31__RT0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x483600++0x03
line.long 0x00 "IMUCTR32__RT0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x483608++0x03
line.long 0x00 "IMUASID32__RT0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x483610++0x03
line.long 0x00 "IMUCTR33__RT0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x483618++0x03
line.long 0x00 "IMUASID33__RT0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x483620++0x03
line.long 0x00 "IMUCTR34__RT0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x483628++0x03
line.long 0x00 "IMUASID34__RT0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x483630++0x03
line.long 0x00 "IMUCTR35__RT0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x483638++0x03
line.long 0x00 "IMUASID35__RT0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x483640++0x03
line.long 0x00 "IMUCTR36__RT0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x483648++0x03
line.long 0x00 "IMUASID36__RT0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x483650++0x03
line.long 0x00 "IMUCTR37__RT0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x483658++0x03
line.long 0x00 "IMUASID37__RT0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x483660++0x03
line.long 0x00 "IMUCTR38__RT0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x483668++0x03
line.long 0x00 "IMUASID38__RT0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x483670++0x03
line.long 0x00 "IMUCTR39__RT0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x483678++0x03
line.long 0x00 "IMUASID39__RT0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x483680++0x03
line.long 0x00 "IMUCTR40__RT0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x483688++0x03
line.long 0x00 "IMUASID40__RT0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x483690++0x03
line.long 0x00 "IMUCTR41__RT0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x483698++0x03
line.long 0x00 "IMUASID41__RT0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4836A0++0x03
line.long 0x00 "IMUCTR42__RT0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4836A8++0x03
line.long 0x00 "IMUASID42__RT0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4836B0++0x03
line.long 0x00 "IMUCTR43__RT0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4836B8++0x03
line.long 0x00 "IMUASID43__RT0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4836C0++0x03
line.long 0x00 "IMUCTR44__RT0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4836C8++0x03
line.long 0x00 "IMUASID44__RT0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4836D0++0x03
line.long 0x00 "IMUCTR45__RT0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4836D8++0x03
line.long 0x00 "IMUASID45__RT0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4836E0++0x03
line.long 0x00 "IMUCTR46__RT0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4836E8++0x03
line.long 0x00 "IMUASID46__RT0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4836F0++0x03
line.long 0x00 "IMUCTR47__RT0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4836F8++0x03
line.long 0x00 "IMUASID47__RT0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x483700++0x03
line.long 0x00 "IMUCTR48__RT0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x483708++0x03
line.long 0x00 "IMUASID48__RT0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x483710++0x03
line.long 0x00 "IMUCTR49__RT0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x483718++0x03
line.long 0x00 "IMUASID49__RT0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x483720++0x03
line.long 0x00 "IMUCTR50__RT0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x483728++0x03
line.long 0x00 "IMUASID50__RT0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x483730++0x03
line.long 0x00 "IMUCTR51__RT0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x483738++0x03
line.long 0x00 "IMUASID51__RT0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x483740++0x03
line.long 0x00 "IMUCTR52__RT0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x483748++0x03
line.long 0x00 "IMUASID52__RT0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x483750++0x03
line.long 0x00 "IMUCTR53__RT0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x483758++0x03
line.long 0x00 "IMUASID53__RT0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x483760++0x03
line.long 0x00 "IMUCTR54__RT0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x483768++0x03
line.long 0x00 "IMUASID54__RT0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x483770++0x03
line.long 0x00 "IMUCTR55__RT0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x483778++0x03
line.long 0x00 "IMUASID55__RT0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x483780++0x03
line.long 0x00 "IMUCTR56__RT0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x483788++0x03
line.long 0x00 "IMUASID56__RT0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x483790++0x03
line.long 0x00 "IMUCTR57__RT0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x483798++0x03
line.long 0x00 "IMUASID57__RT0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4837A0++0x03
line.long 0x00 "IMUCTR58__RT0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4837A8++0x03
line.long 0x00 "IMUASID58__RT0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4837B0++0x03
line.long 0x00 "IMUCTR59__RT0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4837B8++0x03
line.long 0x00 "IMUASID59__RT0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4837C0++0x03
line.long 0x00 "IMUCTR60__RT0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4837C8++0x03
line.long 0x00 "IMUASID60__RT0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4837D0++0x03
line.long 0x00 "IMUCTR61__RT0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4837D8++0x03
line.long 0x00 "IMUASID61__RT0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4837E0++0x03
line.long 0x00 "IMUCTR62__RT0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4837E8++0x03
line.long 0x00 "IMUASID62__RT0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4837F0++0x03
line.long 0x00 "IMUCTR63__RT0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4837F8++0x03
line.long 0x00 "IMUASID63__RT0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x490000++0x03
line.long 0x00 "IMCTR0__RT0,Note: n= 0 to 15 (IPMMU context) This register controls the behavior of the MMU"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 15. "SEC,Copy of IMSEC.SEC[n]" "0: Behave as non-secure context,1: Behave as secure context"
newline
hexmask.long.word 0x00 3.--14. 1. "Reserved_3,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error occurs,1: Assert an interrupt when an error occurs"
newline
bitfld.long 0x00 1. "FLUSH,TLB Invalidate This bit is automatically cleared to 0" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,MMU Enable" "0: MMU disabled,1: MMU enabled"
group.long 0x490040++0x03
line.long 0x00 "IMSEC__RT0,This register controls the attribute of secure/non-secure for MMU"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--15. 1. "SEC_15_0,SEC[n]=0 : IMCTRn~IMERIDn is Non-secure SEC[n]=1 : IMCTRn~IMERIDn is Secure"
group.long 0x491040++0x03
line.long 0x00 "IMCTR1__RT0,Note: n= 0 to 15 (IPMMU context) This register controls the behavior of the MMU"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 15. "SEC,Copy of IMSEC.SEC[n]" "0: Behave as non-secure context,1: Behave as secure context"
newline
hexmask.long.word 0x00 3.--14. 1. "Reserved_3,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error occurs,1: Assert an interrupt when an error occurs"
newline
bitfld.long 0x00 1. "FLUSH,TLB Invalidate This bit is automatically cleared to 0" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,MMU Enable" "0: MMU disabled,1: MMU enabled"
group.long 0x492080++0x03
line.long 0x00 "IMCTR2__RT0,Note: n= 0 to 15 (IPMMU context) This register controls the behavior of the MMU"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 15. "SEC,Copy of IMSEC.SEC[n]" "0: Behave as non-secure context,1: Behave as secure context"
newline
hexmask.long.word 0x00 3.--14. 1. "Reserved_3,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error occurs,1: Assert an interrupt when an error occurs"
newline
bitfld.long 0x00 1. "FLUSH,TLB Invalidate This bit is automatically cleared to 0" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,MMU Enable" "0: MMU disabled,1: MMU enabled"
group.long 0x4930C0++0x03
line.long 0x00 "IMCTR3__RT0,Note: n= 0 to 15 (IPMMU context) This register controls the behavior of the MMU"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 15. "SEC,Copy of IMSEC.SEC[n]" "0: Behave as non-secure context,1: Behave as secure context"
newline
hexmask.long.word 0x00 3.--14. 1. "Reserved_3,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error occurs,1: Assert an interrupt when an error occurs"
newline
bitfld.long 0x00 1. "FLUSH,TLB Invalidate This bit is automatically cleared to 0" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,MMU Enable" "0: MMU disabled,1: MMU enabled"
group.long 0x494100++0x03
line.long 0x00 "IMCTR4__RT0,Note: n= 0 to 15 (IPMMU context) This register controls the behavior of the MMU"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 15. "SEC,Copy of IMSEC.SEC[n]" "0: Behave as non-secure context,1: Behave as secure context"
newline
hexmask.long.word 0x00 3.--14. 1. "Reserved_3,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error occurs,1: Assert an interrupt when an error occurs"
newline
bitfld.long 0x00 1. "FLUSH,TLB Invalidate This bit is automatically cleared to 0" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,MMU Enable" "0: MMU disabled,1: MMU enabled"
group.long 0x495140++0x03
line.long 0x00 "IMCTR5__RT0,Note: n= 0 to 15 (IPMMU context) This register controls the behavior of the MMU"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 15. "SEC,Copy of IMSEC.SEC[n]" "0: Behave as non-secure context,1: Behave as secure context"
newline
hexmask.long.word 0x00 3.--14. 1. "Reserved_3,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error occurs,1: Assert an interrupt when an error occurs"
newline
bitfld.long 0x00 1. "FLUSH,TLB Invalidate This bit is automatically cleared to 0" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,MMU Enable" "0: MMU disabled,1: MMU enabled"
group.long 0x496180++0x03
line.long 0x00 "IMCTR6__RT0,Note: n= 0 to 15 (IPMMU context) This register controls the behavior of the MMU"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 15. "SEC,Copy of IMSEC.SEC[n]" "0: Behave as non-secure context,1: Behave as secure context"
newline
hexmask.long.word 0x00 3.--14. 1. "Reserved_3,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error occurs,1: Assert an interrupt when an error occurs"
newline
bitfld.long 0x00 1. "FLUSH,TLB Invalidate This bit is automatically cleared to 0" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,MMU Enable" "0: MMU disabled,1: MMU enabled"
group.long 0x4971C0++0x03
line.long 0x00 "IMCTR7__RT0,Note: n= 0 to 15 (IPMMU context) This register controls the behavior of the MMU"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 15. "SEC,Copy of IMSEC.SEC[n]" "0: Behave as non-secure context,1: Behave as secure context"
newline
hexmask.long.word 0x00 3.--14. 1. "Reserved_3,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error occurs,1: Assert an interrupt when an error occurs"
newline
bitfld.long 0x00 1. "FLUSH,TLB Invalidate This bit is automatically cleared to 0" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,MMU Enable" "0: MMU disabled,1: MMU enabled"
group.long 0x498800++0x03
line.long 0x00 "IMCTR8__RT0,Note: n= 0 to 15 (IPMMU context) This register controls the behavior of the MMU"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 15. "SEC,Copy of IMSEC.SEC[n]" "0: Behave as non-secure context,1: Behave as secure context"
newline
hexmask.long.word 0x00 3.--14. 1. "Reserved_3,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error occurs,1: Assert an interrupt when an error occurs"
newline
bitfld.long 0x00 1. "FLUSH,TLB Invalidate This bit is automatically cleared to 0" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,MMU Enable" "0: MMU disabled,1: MMU enabled"
group.long 0x499840++0x03
line.long 0x00 "IMCTR9__RT0,Note: n= 0 to 15 (IPMMU context) This register controls the behavior of the MMU"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 15. "SEC,Copy of IMSEC.SEC[n]" "0: Behave as non-secure context,1: Behave as secure context"
newline
hexmask.long.word 0x00 3.--14. 1. "Reserved_3,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error occurs,1: Assert an interrupt when an error occurs"
newline
bitfld.long 0x00 1. "FLUSH,TLB Invalidate This bit is automatically cleared to 0" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,MMU Enable" "0: MMU disabled,1: MMU enabled"
group.long 0x49A880++0x03
line.long 0x00 "IMCTR10__RT0,Note: n= 0 to 15 (IPMMU context) This register controls the behavior of the MMU"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 15. "SEC,Copy of IMSEC.SEC[n]" "0: Behave as non-secure context,1: Behave as secure context"
newline
hexmask.long.word 0x00 3.--14. 1. "Reserved_3,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error occurs,1: Assert an interrupt when an error occurs"
newline
bitfld.long 0x00 1. "FLUSH,TLB Invalidate This bit is automatically cleared to 0" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,MMU Enable" "0: MMU disabled,1: MMU enabled"
group.long 0x49B8C0++0x03
line.long 0x00 "IMCTR11__RT0,Note: n= 0 to 15 (IPMMU context) This register controls the behavior of the MMU"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 15. "SEC,Copy of IMSEC.SEC[n]" "0: Behave as non-secure context,1: Behave as secure context"
newline
hexmask.long.word 0x00 3.--14. 1. "Reserved_3,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error occurs,1: Assert an interrupt when an error occurs"
newline
bitfld.long 0x00 1. "FLUSH,TLB Invalidate This bit is automatically cleared to 0" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,MMU Enable" "0: MMU disabled,1: MMU enabled"
group.long 0x49C900++0x03
line.long 0x00 "IMCTR12__RT0,Note: n= 0 to 15 (IPMMU context) This register controls the behavior of the MMU"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 15. "SEC,Copy of IMSEC.SEC[n]" "0: Behave as non-secure context,1: Behave as secure context"
newline
hexmask.long.word 0x00 3.--14. 1. "Reserved_3,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error occurs,1: Assert an interrupt when an error occurs"
newline
bitfld.long 0x00 1. "FLUSH,TLB Invalidate This bit is automatically cleared to 0" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,MMU Enable" "0: MMU disabled,1: MMU enabled"
group.long 0x49D940++0x03
line.long 0x00 "IMCTR13__RT0,Note: n= 0 to 15 (IPMMU context) This register controls the behavior of the MMU"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 15. "SEC,Copy of IMSEC.SEC[n]" "0: Behave as non-secure context,1: Behave as secure context"
newline
hexmask.long.word 0x00 3.--14. 1. "Reserved_3,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error occurs,1: Assert an interrupt when an error occurs"
newline
bitfld.long 0x00 1. "FLUSH,TLB Invalidate This bit is automatically cleared to 0" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,MMU Enable" "0: MMU disabled,1: MMU enabled"
group.long 0x49E980++0x03
line.long 0x00 "IMCTR14__RT0,Note: n= 0 to 15 (IPMMU context) This register controls the behavior of the MMU"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 15. "SEC,Copy of IMSEC.SEC[n]" "0: Behave as non-secure context,1: Behave as secure context"
newline
hexmask.long.word 0x00 3.--14. 1. "Reserved_3,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error occurs,1: Assert an interrupt when an error occurs"
newline
bitfld.long 0x00 1. "FLUSH,TLB Invalidate This bit is automatically cleared to 0" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,MMU Enable" "0: MMU disabled,1: MMU enabled"
group.long 0x49F9C0++0x03
line.long 0x00 "IMCTR15__RT0,Note: n= 0 to 15 (IPMMU context) This register controls the behavior of the MMU"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 15. "SEC,Copy of IMSEC.SEC[n]" "0: Behave as non-secure context,1: Behave as secure context"
newline
hexmask.long.word 0x00 3.--14. 1. "Reserved_3,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error occurs,1: Assert an interrupt when an error occurs"
newline
bitfld.long 0x00 1. "FLUSH,TLB Invalidate This bit is automatically cleared to 0" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,MMU Enable" "0: MMU disabled,1: MMU enabled"
group.long 0x4C0548++0x03
line.long 0x00 "IMERRSIDAR__RT1,This register indicates the Error SrcID when EDC error happen in AXI AR channel"
bitfld.long 0x00 31. "CLR," "0,1"
newline
hexmask.long.tbyte 0x00 8.--30. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "SRCID_7_0,Read : SrcID of error transaction"
group.long 0x4C054C++0x03
line.long 0x00 "IMERRSIDR__RT1,This register indicates the Error SrcID when EDC error happen in AXI R channel"
bitfld.long 0x00 31. "CLR," "0,1"
newline
hexmask.long.tbyte 0x00 8.--30. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "SRCID_7_0,Read : SrcID of error transaction"
group.long 0x4C0558++0x03
line.long 0x00 "IMERRSIDNPTWAR__RT1,This register indicates the Error SrcID when EDC error happen in AXI AR channel with no Page Table Walk"
bitfld.long 0x00 31. "CLR," "0,1"
newline
hexmask.long.tbyte 0x00 8.--30. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "SRCID_7_0,Read : SrcID of error transaction"
group.long 0x4C0560++0x03
line.long 0x00 "IMAPQOS__RT1,This resister controls QoS value that is output from IPMMU(cache) to IPMMU(main) through ARADDR[35:32]"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 0.--3. "APQOS_3_0,Append QoS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4C0564++0x03
line.long 0x00 "IMERRSIDRRESP__RT1,This register indicates the Error SrcID when EDC error happen in AXI R(response) channel"
bitfld.long 0x00 31. "CLR," "0,1"
newline
hexmask.long.tbyte 0x00 8.--30. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "SRCID_7_0,Read : SrcID of error transaction"
group.long 0x4C0568++0x03
line.long 0x00 "IMERRSIDPA__RT1,This register indicates the Error SrcID when EDC error happen in APB address channel"
bitfld.long 0x00 31. "CLR," "0,1"
newline
hexmask.long.tbyte 0x00 8.--30. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "SRCID_7_0,Read : SrcID of error transaction"
group.long 0x4C056C++0x03
line.long 0x00 "IMERRSIDPWD__RT1,This register indicates the Error SrcID when EDC error happen in APB write data channel"
bitfld.long 0x00 31. "CLR," "0,1"
newline
hexmask.long.tbyte 0x00 8.--30. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "SRCID_7_0,Read : SrcID of error transaction"
group.long 0x4C0570++0x03
line.long 0x00 "IMRGID__RT1,Region-ID setting will be available for each IPMMU-hier (each bus hierarchy)"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 0.--3. "RGID_3_0,Region-ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4C0574++0x03
line.long 0x00 "IMRGIDEN__RT1,This register is used for setting to protect IMRGID register"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--15. 1. "RGIDEN_15_0,When RGIDEN[PUSER[5:2]]=1 IMRGID[3:0] register can be accessed"
group.long 0x4C0578++0x03
line.long 0x00 "IMSECGRP__RT1,This register is used for setting to protect IMRGID register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 0. "SECGRP,When PUSER[1]=0 if SECGRP=1 RGID register can be accessed" "0,1"
group.long 0x4C1500++0x03
line.long 0x00 "IMSCTLR__RT1,This register controls the behavior of IPMMU function"
bitfld.long 0x00 31. "DISWPROT,Read and Write protection of MMU System Control Register and MMU auxiliary Control register" "0: can write IMSCTLR.NSACCEN & IMSCTLR.USE_SECGRP,1: can write/read IMSCTLR.NSACCEN &"
newline
bitfld.long 0x00 30. "NSACCEN,Non-secure access enable for MMU System Control Register and MMU auxiliary Control register" "0: disable non-secure access (default),1: enable non-secure access"
newline
bitfld.long 0x00 29. "DISMMU,Disable IPMMU cache" "0: enable IPMMU cache This bit can be set except,1: disable IPMMU cache"
newline
bitfld.long 0x00 28. "USE_SECGRP,Use security group to judge Secure/Non-secure access Set this bit in IPMMU-DS0 and IPMMU-RT1 0 before using this function" "0,1"
newline
hexmask.long 0x00 0.--27. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x4C1554++0x03
line.long 0x00 "ISERRINJR__RT1,IPMMU cache"
hexmask.long 0x00 7.--31. 1. "Reserved_7,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 6. "ERRINJ_EDCERR_PWD,Error injection bit for EDC error in APB write datta channel" "0: Clear error injection,1: Enable error injection"
newline
bitfld.long 0x00 5. "ERRINJ_EDCERR_PA,Error injection bit for EDC error in APB address channel" "0: Clear error injection,1: Enable error injection"
newline
bitfld.long 0x00 4. "ERRINJ_EDCERR_RRESP,Error injection bit for EDC error in AXI R response channel" "0: Clear error injection,1: Enable error injection"
newline
bitfld.long 0x00 3. "ERRINJ_EDCERR_NPTW_AR,Error injection bit for EDC error in AXI AR channel (during not Page Table Walk)" "0: Clear error injection,1: Enable error injection"
newline
bitfld.long 0x00 2. "ERRINJ_COMPFAIL,Error injection bit for DCLS error" "0: Clear error injection,1: Enable error injection"
newline
bitfld.long 0x00 1. "ERRINJ_EDCERR_R,Error injection bit for EDC error in AXI R channel" "0: Clear error injection,1: Enable error injection"
newline
bitfld.long 0x00 0. "ERRINJ_EDCERR_AR,Error injection bit for EDC error in AXI AR channel" "0: Clear error injection,1: Enable error injection"
group.long 0x4C1580++0x03
line.long 0x00 "IMPFMCTR__RT1,"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 12.--13. "MD_1_0,Monitor Mode IPMMU (cache)" "0: Monitor all MMUs,1: Reserved,2: Reserved,3: Monitor only MMUn (specified"
newline
bitfld.long 0x00 8.--11. "SEL_3_0,When MD is B'11 SEL indicates the MMU table number to be monitored" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 2.--7. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 1. "RST,Reset all status and counter values" "0,1"
newline
bitfld.long 0x00 0. "EN,Performance Monitor Enable" "0: Stop to count,1: Start to count All counters stop when"
group.long 0x4C1590++0x03
line.long 0x00 "IMPFMTOTAL__RT1,"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "TOTAL_23_0,The total number of translation requests"
group.long 0x4C1594++0x03
line.long 0x00 "IMPFMHIT__RT1,"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "HIT_23_0,The total number of TLB hit requests"
group.long 0x4C1598++0x03
line.long 0x00 "IMPFMMISS__RT1,"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MISS_23_0,The total number of miss requests"
group.long 0x4C2200++0x03
line.long 0x00 "IMPCTR__RT1,This register controls the behavior of the PMB function"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--7. "TTSEL_3_0,Translation Table Select Indicates the table number (MMU0  MMU15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 3. "TTEN,TLB Translation Enable" "0: Output PPN as a physical address,1: Output PPN as an intermediate physical address"
newline
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error..,1: Assert an interrupt when an error occurred"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 0. "PMBEN,PMB Enable" "0: PMB disabled,1: PMB enabled"
group.long 0x4C2208++0x03
line.long 0x00 "IMPSTR__RT1,This register indicates the error status of the address translation by PMB"
hexmask.long 0x00 5.--31. 1. "Reserved_5,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4. "MHIT,Multiple hit Indicate that multiple PMB hits occurred" "0,1"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "TF,Translation Fault This bit is set to 1 when a translation fault occurred during a PMB translation" "0,1"
group.long 0x4C220C++0x03
line.long 0x00 "IMPEAR__RT1,This register indicates the address which an address translation error occurred"
hexmask.long 0x00 0.--31. 1. "EAR_31_0,The faulting virtual address is set when an address translation error occurred"
group.long 0x4C2280++0x03
line.long 0x00 "IMPMBA0__RT1,Note: n= 0 to 15 This register is used for setting the virtual page number"
hexmask.long.byte 0x00 24.--31. 1. "VPN_31_24,Virtual Page Number For 16-Mbyte page VPN[31:24] is used"
newline
hexmask.long.word 0x00 9.--23. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x4C2284++0x03
line.long 0x00 "IMPMBA1__RT1,Note: n= 0 to 15 This register is used for setting the virtual page number"
hexmask.long.byte 0x00 24.--31. 1. "VPN_31_24,Virtual Page Number For 16-Mbyte page VPN[31:24] is used"
newline
hexmask.long.word 0x00 9.--23. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x4C2288++0x03
line.long 0x00 "IMPMBA2__RT1,Note: n= 0 to 15 This register is used for setting the virtual page number"
hexmask.long.byte 0x00 24.--31. 1. "VPN_31_24,Virtual Page Number For 16-Mbyte page VPN[31:24] is used"
newline
hexmask.long.word 0x00 9.--23. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x4C228C++0x03
line.long 0x00 "IMPMBA3__RT1,Note: n= 0 to 15 This register is used for setting the virtual page number"
hexmask.long.byte 0x00 24.--31. 1. "VPN_31_24,Virtual Page Number For 16-Mbyte page VPN[31:24] is used"
newline
hexmask.long.word 0x00 9.--23. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x4C2290++0x03
line.long 0x00 "IMPMBA4__RT1,Note: n= 0 to 15 This register is used for setting the virtual page number"
hexmask.long.byte 0x00 24.--31. 1. "VPN_31_24,Virtual Page Number For 16-Mbyte page VPN[31:24] is used"
newline
hexmask.long.word 0x00 9.--23. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x4C2294++0x03
line.long 0x00 "IMPMBA5__RT1,Note: n= 0 to 15 This register is used for setting the virtual page number"
hexmask.long.byte 0x00 24.--31. 1. "VPN_31_24,Virtual Page Number For 16-Mbyte page VPN[31:24] is used"
newline
hexmask.long.word 0x00 9.--23. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x4C2298++0x03
line.long 0x00 "IMPMBA6__RT1,Note: n= 0 to 15 This register is used for setting the virtual page number"
hexmask.long.byte 0x00 24.--31. 1. "VPN_31_24,Virtual Page Number For 16-Mbyte page VPN[31:24] is used"
newline
hexmask.long.word 0x00 9.--23. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x4C229C++0x03
line.long 0x00 "IMPMBA7__RT1,Note: n= 0 to 15 This register is used for setting the virtual page number"
hexmask.long.byte 0x00 24.--31. 1. "VPN_31_24,Virtual Page Number For 16-Mbyte page VPN[31:24] is used"
newline
hexmask.long.word 0x00 9.--23. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x4C22A0++0x03
line.long 0x00 "IMPMBA8__RT1,Note: n= 0 to 15 This register is used for setting the virtual page number"
hexmask.long.byte 0x00 24.--31. 1. "VPN_31_24,Virtual Page Number For 16-Mbyte page VPN[31:24] is used"
newline
hexmask.long.word 0x00 9.--23. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x4C22A4++0x03
line.long 0x00 "IMPMBA9__RT1,Note: n= 0 to 15 This register is used for setting the virtual page number"
hexmask.long.byte 0x00 24.--31. 1. "VPN_31_24,Virtual Page Number For 16-Mbyte page VPN[31:24] is used"
newline
hexmask.long.word 0x00 9.--23. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x4C22A8++0x03
line.long 0x00 "IMPMBA10__RT1,Note: n= 0 to 15 This register is used for setting the virtual page number"
hexmask.long.byte 0x00 24.--31. 1. "VPN_31_24,Virtual Page Number For 16-Mbyte page VPN[31:24] is used"
newline
hexmask.long.word 0x00 9.--23. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x4C22AC++0x03
line.long 0x00 "IMPMBA11__RT1,Note: n= 0 to 15 This register is used for setting the virtual page number"
hexmask.long.byte 0x00 24.--31. 1. "VPN_31_24,Virtual Page Number For 16-Mbyte page VPN[31:24] is used"
newline
hexmask.long.word 0x00 9.--23. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x4C22B0++0x03
line.long 0x00 "IMPMBA12__RT1,Note: n= 0 to 15 This register is used for setting the virtual page number"
hexmask.long.byte 0x00 24.--31. 1. "VPN_31_24,Virtual Page Number For 16-Mbyte page VPN[31:24] is used"
newline
hexmask.long.word 0x00 9.--23. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x4C22B4++0x03
line.long 0x00 "IMPMBA13__RT1,Note: n= 0 to 15 This register is used for setting the virtual page number"
hexmask.long.byte 0x00 24.--31. 1. "VPN_31_24,Virtual Page Number For 16-Mbyte page VPN[31:24] is used"
newline
hexmask.long.word 0x00 9.--23. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x4C22B8++0x03
line.long 0x00 "IMPMBA14__RT1,Note: n= 0 to 15 This register is used for setting the virtual page number"
hexmask.long.byte 0x00 24.--31. 1. "VPN_31_24,Virtual Page Number For 16-Mbyte page VPN[31:24] is used"
newline
hexmask.long.word 0x00 9.--23. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x4C22BC++0x03
line.long 0x00 "IMPMBA15__RT1,Note: n= 0 to 15 This register is used for setting the virtual page number"
hexmask.long.byte 0x00 24.--31. 1. "VPN_31_24,Virtual Page Number For 16-Mbyte page VPN[31:24] is used"
newline
hexmask.long.word 0x00 9.--23. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x4C22C0++0x03
line.long 0x00 "IMPMBD0__RT1,Note: n= 0 to 15 This register is used for setting the physical page number and the memory size which PMB managed"
hexmask.long.byte 0x00 24.--31. 1. "PPN_31_24,Physical Page Number For 16-Mbyte page PPN[31:24] is used"
newline
hexmask.long.byte 0x00 16.--23. 1. "PPN_39_32,Upper Physical Page Number"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
bitfld.long 0x00 7. "SZ_1,This bit and SZ[0] (bit 4) specify the page size" "0: 16-Mbyte page,1: 64-Mbyte page"
newline
rbitfld.long 0x00 5.--6. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 4. "SZ_0,Page Size See the description of SZ[1] (bit 7)" "0,1"
newline
bitfld.long 0x00 3. "C,Cache bit When this bit is set the request after address translation can be treated as cacheable request" "0,1"
newline
rbitfld.long 0x00 0.--2. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
group.long 0x4C22C4++0x03
line.long 0x00 "IMPMBD1__RT1,Note: n= 0 to 15 This register is used for setting the physical page number and the memory size which PMB managed"
hexmask.long.byte 0x00 24.--31. 1. "PPN_31_24,Physical Page Number For 16-Mbyte page PPN[31:24] is used"
newline
hexmask.long.byte 0x00 16.--23. 1. "PPN_39_32,Upper Physical Page Number"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
bitfld.long 0x00 7. "SZ_1,This bit and SZ[0] (bit 4) specify the page size" "0: 16-Mbyte page,1: 64-Mbyte page"
newline
rbitfld.long 0x00 5.--6. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 4. "SZ_0,Page Size See the description of SZ[1] (bit 7)" "0,1"
newline
bitfld.long 0x00 3. "C,Cache bit When this bit is set the request after address translation can be treated as cacheable request" "0,1"
newline
rbitfld.long 0x00 0.--2. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
group.long 0x4C22C8++0x03
line.long 0x00 "IMPMBD2__RT1,Note: n= 0 to 15 This register is used for setting the physical page number and the memory size which PMB managed"
hexmask.long.byte 0x00 24.--31. 1. "PPN_31_24,Physical Page Number For 16-Mbyte page PPN[31:24] is used"
newline
hexmask.long.byte 0x00 16.--23. 1. "PPN_39_32,Upper Physical Page Number"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
bitfld.long 0x00 7. "SZ_1,This bit and SZ[0] (bit 4) specify the page size" "0: 16-Mbyte page,1: 64-Mbyte page"
newline
rbitfld.long 0x00 5.--6. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 4. "SZ_0,Page Size See the description of SZ[1] (bit 7)" "0,1"
newline
bitfld.long 0x00 3. "C,Cache bit When this bit is set the request after address translation can be treated as cacheable request" "0,1"
newline
rbitfld.long 0x00 0.--2. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
group.long 0x4C22CC++0x03
line.long 0x00 "IMPMBD3__RT1,Note: n= 0 to 15 This register is used for setting the physical page number and the memory size which PMB managed"
hexmask.long.byte 0x00 24.--31. 1. "PPN_31_24,Physical Page Number For 16-Mbyte page PPN[31:24] is used"
newline
hexmask.long.byte 0x00 16.--23. 1. "PPN_39_32,Upper Physical Page Number"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
bitfld.long 0x00 7. "SZ_1,This bit and SZ[0] (bit 4) specify the page size" "0: 16-Mbyte page,1: 64-Mbyte page"
newline
rbitfld.long 0x00 5.--6. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 4. "SZ_0,Page Size See the description of SZ[1] (bit 7)" "0,1"
newline
bitfld.long 0x00 3. "C,Cache bit When this bit is set the request after address translation can be treated as cacheable request" "0,1"
newline
rbitfld.long 0x00 0.--2. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
group.long 0x4C22D0++0x03
line.long 0x00 "IMPMBD4__RT1,Note: n= 0 to 15 This register is used for setting the physical page number and the memory size which PMB managed"
hexmask.long.byte 0x00 24.--31. 1. "PPN_31_24,Physical Page Number For 16-Mbyte page PPN[31:24] is used"
newline
hexmask.long.byte 0x00 16.--23. 1. "PPN_39_32,Upper Physical Page Number"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
bitfld.long 0x00 7. "SZ_1,This bit and SZ[0] (bit 4) specify the page size" "0: 16-Mbyte page,1: 64-Mbyte page"
newline
rbitfld.long 0x00 5.--6. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 4. "SZ_0,Page Size See the description of SZ[1] (bit 7)" "0,1"
newline
bitfld.long 0x00 3. "C,Cache bit When this bit is set the request after address translation can be treated as cacheable request" "0,1"
newline
rbitfld.long 0x00 0.--2. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
group.long 0x4C22D4++0x03
line.long 0x00 "IMPMBD5__RT1,Note: n= 0 to 15 This register is used for setting the physical page number and the memory size which PMB managed"
hexmask.long.byte 0x00 24.--31. 1. "PPN_31_24,Physical Page Number For 16-Mbyte page PPN[31:24] is used"
newline
hexmask.long.byte 0x00 16.--23. 1. "PPN_39_32,Upper Physical Page Number"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
bitfld.long 0x00 7. "SZ_1,This bit and SZ[0] (bit 4) specify the page size" "0: 16-Mbyte page,1: 64-Mbyte page"
newline
rbitfld.long 0x00 5.--6. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 4. "SZ_0,Page Size See the description of SZ[1] (bit 7)" "0,1"
newline
bitfld.long 0x00 3. "C,Cache bit When this bit is set the request after address translation can be treated as cacheable request" "0,1"
newline
rbitfld.long 0x00 0.--2. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
group.long 0x4C22D8++0x03
line.long 0x00 "IMPMBD6__RT1,Note: n= 0 to 15 This register is used for setting the physical page number and the memory size which PMB managed"
hexmask.long.byte 0x00 24.--31. 1. "PPN_31_24,Physical Page Number For 16-Mbyte page PPN[31:24] is used"
newline
hexmask.long.byte 0x00 16.--23. 1. "PPN_39_32,Upper Physical Page Number"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
bitfld.long 0x00 7. "SZ_1,This bit and SZ[0] (bit 4) specify the page size" "0: 16-Mbyte page,1: 64-Mbyte page"
newline
rbitfld.long 0x00 5.--6. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 4. "SZ_0,Page Size See the description of SZ[1] (bit 7)" "0,1"
newline
bitfld.long 0x00 3. "C,Cache bit When this bit is set the request after address translation can be treated as cacheable request" "0,1"
newline
rbitfld.long 0x00 0.--2. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
group.long 0x4C22DC++0x03
line.long 0x00 "IMPMBD7__RT1,Note: n= 0 to 15 This register is used for setting the physical page number and the memory size which PMB managed"
hexmask.long.byte 0x00 24.--31. 1. "PPN_31_24,Physical Page Number For 16-Mbyte page PPN[31:24] is used"
newline
hexmask.long.byte 0x00 16.--23. 1. "PPN_39_32,Upper Physical Page Number"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
bitfld.long 0x00 7. "SZ_1,This bit and SZ[0] (bit 4) specify the page size" "0: 16-Mbyte page,1: 64-Mbyte page"
newline
rbitfld.long 0x00 5.--6. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 4. "SZ_0,Page Size See the description of SZ[1] (bit 7)" "0,1"
newline
bitfld.long 0x00 3. "C,Cache bit When this bit is set the request after address translation can be treated as cacheable request" "0,1"
newline
rbitfld.long 0x00 0.--2. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
group.long 0x4C22E0++0x03
line.long 0x00 "IMPMBD8__RT1,Note: n= 0 to 15 This register is used for setting the physical page number and the memory size which PMB managed"
hexmask.long.byte 0x00 24.--31. 1. "PPN_31_24,Physical Page Number For 16-Mbyte page PPN[31:24] is used"
newline
hexmask.long.byte 0x00 16.--23. 1. "PPN_39_32,Upper Physical Page Number"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
bitfld.long 0x00 7. "SZ_1,This bit and SZ[0] (bit 4) specify the page size" "0: 16-Mbyte page,1: 64-Mbyte page"
newline
rbitfld.long 0x00 5.--6. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 4. "SZ_0,Page Size See the description of SZ[1] (bit 7)" "0,1"
newline
bitfld.long 0x00 3. "C,Cache bit When this bit is set the request after address translation can be treated as cacheable request" "0,1"
newline
rbitfld.long 0x00 0.--2. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
group.long 0x4C22E4++0x03
line.long 0x00 "IMPMBD9__RT1,Note: n= 0 to 15 This register is used for setting the physical page number and the memory size which PMB managed"
hexmask.long.byte 0x00 24.--31. 1. "PPN_31_24,Physical Page Number For 16-Mbyte page PPN[31:24] is used"
newline
hexmask.long.byte 0x00 16.--23. 1. "PPN_39_32,Upper Physical Page Number"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
bitfld.long 0x00 7. "SZ_1,This bit and SZ[0] (bit 4) specify the page size" "0: 16-Mbyte page,1: 64-Mbyte page"
newline
rbitfld.long 0x00 5.--6. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 4. "SZ_0,Page Size See the description of SZ[1] (bit 7)" "0,1"
newline
bitfld.long 0x00 3. "C,Cache bit When this bit is set the request after address translation can be treated as cacheable request" "0,1"
newline
rbitfld.long 0x00 0.--2. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
group.long 0x4C22E8++0x03
line.long 0x00 "IMPMBD10__RT1,Note: n= 0 to 15 This register is used for setting the physical page number and the memory size which PMB managed"
hexmask.long.byte 0x00 24.--31. 1. "PPN_31_24,Physical Page Number For 16-Mbyte page PPN[31:24] is used"
newline
hexmask.long.byte 0x00 16.--23. 1. "PPN_39_32,Upper Physical Page Number"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
bitfld.long 0x00 7. "SZ_1,This bit and SZ[0] (bit 4) specify the page size" "0: 16-Mbyte page,1: 64-Mbyte page"
newline
rbitfld.long 0x00 5.--6. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 4. "SZ_0,Page Size See the description of SZ[1] (bit 7)" "0,1"
newline
bitfld.long 0x00 3. "C,Cache bit When this bit is set the request after address translation can be treated as cacheable request" "0,1"
newline
rbitfld.long 0x00 0.--2. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
group.long 0x4C22EC++0x03
line.long 0x00 "IMPMBD11__RT1,Note: n= 0 to 15 This register is used for setting the physical page number and the memory size which PMB managed"
hexmask.long.byte 0x00 24.--31. 1. "PPN_31_24,Physical Page Number For 16-Mbyte page PPN[31:24] is used"
newline
hexmask.long.byte 0x00 16.--23. 1. "PPN_39_32,Upper Physical Page Number"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
bitfld.long 0x00 7. "SZ_1,This bit and SZ[0] (bit 4) specify the page size" "0: 16-Mbyte page,1: 64-Mbyte page"
newline
rbitfld.long 0x00 5.--6. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 4. "SZ_0,Page Size See the description of SZ[1] (bit 7)" "0,1"
newline
bitfld.long 0x00 3. "C,Cache bit When this bit is set the request after address translation can be treated as cacheable request" "0,1"
newline
rbitfld.long 0x00 0.--2. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
group.long 0x4C22F0++0x03
line.long 0x00 "IMPMBD12__RT1,Note: n= 0 to 15 This register is used for setting the physical page number and the memory size which PMB managed"
hexmask.long.byte 0x00 24.--31. 1. "PPN_31_24,Physical Page Number For 16-Mbyte page PPN[31:24] is used"
newline
hexmask.long.byte 0x00 16.--23. 1. "PPN_39_32,Upper Physical Page Number"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
bitfld.long 0x00 7. "SZ_1,This bit and SZ[0] (bit 4) specify the page size" "0: 16-Mbyte page,1: 64-Mbyte page"
newline
rbitfld.long 0x00 5.--6. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 4. "SZ_0,Page Size See the description of SZ[1] (bit 7)" "0,1"
newline
bitfld.long 0x00 3. "C,Cache bit When this bit is set the request after address translation can be treated as cacheable request" "0,1"
newline
rbitfld.long 0x00 0.--2. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
group.long 0x4C22F4++0x03
line.long 0x00 "IMPMBD13__RT1,Note: n= 0 to 15 This register is used for setting the physical page number and the memory size which PMB managed"
hexmask.long.byte 0x00 24.--31. 1. "PPN_31_24,Physical Page Number For 16-Mbyte page PPN[31:24] is used"
newline
hexmask.long.byte 0x00 16.--23. 1. "PPN_39_32,Upper Physical Page Number"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
bitfld.long 0x00 7. "SZ_1,This bit and SZ[0] (bit 4) specify the page size" "0: 16-Mbyte page,1: 64-Mbyte page"
newline
rbitfld.long 0x00 5.--6. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 4. "SZ_0,Page Size See the description of SZ[1] (bit 7)" "0,1"
newline
bitfld.long 0x00 3. "C,Cache bit When this bit is set the request after address translation can be treated as cacheable request" "0,1"
newline
rbitfld.long 0x00 0.--2. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
group.long 0x4C22F8++0x03
line.long 0x00 "IMPMBD14__RT1,Note: n= 0 to 15 This register is used for setting the physical page number and the memory size which PMB managed"
hexmask.long.byte 0x00 24.--31. 1. "PPN_31_24,Physical Page Number For 16-Mbyte page PPN[31:24] is used"
newline
hexmask.long.byte 0x00 16.--23. 1. "PPN_39_32,Upper Physical Page Number"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
bitfld.long 0x00 7. "SZ_1,This bit and SZ[0] (bit 4) specify the page size" "0: 16-Mbyte page,1: 64-Mbyte page"
newline
rbitfld.long 0x00 5.--6. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 4. "SZ_0,Page Size See the description of SZ[1] (bit 7)" "0,1"
newline
bitfld.long 0x00 3. "C,Cache bit When this bit is set the request after address translation can be treated as cacheable request" "0,1"
newline
rbitfld.long 0x00 0.--2. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
group.long 0x4C22FC++0x03
line.long 0x00 "IMPMBD15__RT1,Note: n= 0 to 15 This register is used for setting the physical page number and the memory size which PMB managed"
hexmask.long.byte 0x00 24.--31. 1. "PPN_31_24,Physical Page Number For 16-Mbyte page PPN[31:24] is used"
newline
hexmask.long.byte 0x00 16.--23. 1. "PPN_39_32,Upper Physical Page Number"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
bitfld.long 0x00 7. "SZ_1,This bit and SZ[0] (bit 4) specify the page size" "0: 16-Mbyte page,1: 64-Mbyte page"
newline
rbitfld.long 0x00 5.--6. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 4. "SZ_0,Page Size See the description of SZ[1] (bit 7)" "0,1"
newline
bitfld.long 0x00 3. "C,Cache bit When this bit is set the request after address translation can be treated as cacheable request" "0,1"
newline
rbitfld.long 0x00 0.--2. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
group.long 0x4C3300++0x03
line.long 0x00 "IMUCTR0__RT1,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4C3308++0x03
line.long 0x00 "IMUASID0__RT1,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4C3310++0x03
line.long 0x00 "IMUCTR1__RT1,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4C3318++0x03
line.long 0x00 "IMUASID1__RT1,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4C3320++0x03
line.long 0x00 "IMUCTR2__RT1,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4C3328++0x03
line.long 0x00 "IMUASID2__RT1,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4C3330++0x03
line.long 0x00 "IMUCTR3__RT1,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4C3338++0x03
line.long 0x00 "IMUASID3__RT1,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4C3340++0x03
line.long 0x00 "IMUCTR4__RT1,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4C3348++0x03
line.long 0x00 "IMUASID4__RT1,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4C3350++0x03
line.long 0x00 "IMUCTR5__RT1,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4C3358++0x03
line.long 0x00 "IMUASID5__RT1,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4C3360++0x03
line.long 0x00 "IMUCTR6__RT1,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4C3368++0x03
line.long 0x00 "IMUASID6__RT1,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4C3370++0x03
line.long 0x00 "IMUCTR7__RT1,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4C3378++0x03
line.long 0x00 "IMUASID7__RT1,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4C3380++0x03
line.long 0x00 "IMUCTR8__RT1,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4C3388++0x03
line.long 0x00 "IMUASID8__RT1,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4C3390++0x03
line.long 0x00 "IMUCTR9__RT1,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4C3398++0x03
line.long 0x00 "IMUASID9__RT1,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4C33A0++0x03
line.long 0x00 "IMUCTR10__RT1,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4C33A8++0x03
line.long 0x00 "IMUASID10__RT1,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4C33B0++0x03
line.long 0x00 "IMUCTR11__RT1,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4C33B8++0x03
line.long 0x00 "IMUASID11__RT1,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4C33C0++0x03
line.long 0x00 "IMUCTR12__RT1,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4C33C8++0x03
line.long 0x00 "IMUASID12__RT1,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4C33D0++0x03
line.long 0x00 "IMUCTR13__RT1,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4C33D8++0x03
line.long 0x00 "IMUASID13__RT1,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4C33E0++0x03
line.long 0x00 "IMUCTR14__RT1,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4C33E8++0x03
line.long 0x00 "IMUASID14__RT1,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4C33F0++0x03
line.long 0x00 "IMUCTR15__RT1,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4C33F8++0x03
line.long 0x00 "IMUASID15__RT1,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4C3400++0x03
line.long 0x00 "IMUCTR16__RT1,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4C3408++0x03
line.long 0x00 "IMUASID16__RT1,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4C3410++0x03
line.long 0x00 "IMUCTR17__RT1,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4C3418++0x03
line.long 0x00 "IMUASID17__RT1,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4C3420++0x03
line.long 0x00 "IMUCTR18__RT1,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4C3428++0x03
line.long 0x00 "IMUASID18__RT1,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4C3430++0x03
line.long 0x00 "IMUCTR19__RT1,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4C3438++0x03
line.long 0x00 "IMUASID19__RT1,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4C3440++0x03
line.long 0x00 "IMUCTR20__RT1,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4C3448++0x03
line.long 0x00 "IMUASID20__RT1,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4C3450++0x03
line.long 0x00 "IMUCTR21__RT1,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4C3458++0x03
line.long 0x00 "IMUASID21__RT1,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4C3460++0x03
line.long 0x00 "IMUCTR22__RT1,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4C3468++0x03
line.long 0x00 "IMUASID22__RT1,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4C3470++0x03
line.long 0x00 "IMUCTR23__RT1,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4C3478++0x03
line.long 0x00 "IMUASID23__RT1,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4C3480++0x03
line.long 0x00 "IMUCTR24__RT1,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4C3488++0x03
line.long 0x00 "IMUASID24__RT1,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4C3490++0x03
line.long 0x00 "IMUCTR25__RT1,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4C3498++0x03
line.long 0x00 "IMUASID25__RT1,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4C34A0++0x03
line.long 0x00 "IMUCTR26__RT1,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4C34A8++0x03
line.long 0x00 "IMUASID26__RT1,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4C34B0++0x03
line.long 0x00 "IMUCTR27__RT1,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4C34B8++0x03
line.long 0x00 "IMUASID27__RT1,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4C34C0++0x03
line.long 0x00 "IMUCTR28__RT1,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4C34C8++0x03
line.long 0x00 "IMUASID28__RT1,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4C34D0++0x03
line.long 0x00 "IMUCTR29__RT1,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4C34D8++0x03
line.long 0x00 "IMUASID29__RT1,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4C34E0++0x03
line.long 0x00 "IMUCTR30__RT1,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4C34E8++0x03
line.long 0x00 "IMUASID30__RT1,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4C34F0++0x03
line.long 0x00 "IMUCTR31__RT1,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4C34F8++0x03
line.long 0x00 "IMUASID31__RT1,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4C3600++0x03
line.long 0x00 "IMUCTR32__RT1,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4C3608++0x03
line.long 0x00 "IMUASID32__RT1,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4C3610++0x03
line.long 0x00 "IMUCTR33__RT1,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4C3618++0x03
line.long 0x00 "IMUASID33__RT1,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4C3620++0x03
line.long 0x00 "IMUCTR34__RT1,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4C3628++0x03
line.long 0x00 "IMUASID34__RT1,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4C3630++0x03
line.long 0x00 "IMUCTR35__RT1,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4C3638++0x03
line.long 0x00 "IMUASID35__RT1,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4C3640++0x03
line.long 0x00 "IMUCTR36__RT1,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4C3648++0x03
line.long 0x00 "IMUASID36__RT1,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4C3650++0x03
line.long 0x00 "IMUCTR37__RT1,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4C3658++0x03
line.long 0x00 "IMUASID37__RT1,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4C3660++0x03
line.long 0x00 "IMUCTR38__RT1,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4C3668++0x03
line.long 0x00 "IMUASID38__RT1,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4C3670++0x03
line.long 0x00 "IMUCTR39__RT1,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4C3678++0x03
line.long 0x00 "IMUASID39__RT1,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4C3680++0x03
line.long 0x00 "IMUCTR40__RT1,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4C3688++0x03
line.long 0x00 "IMUASID40__RT1,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4C3690++0x03
line.long 0x00 "IMUCTR41__RT1,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4C3698++0x03
line.long 0x00 "IMUASID41__RT1,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4C36A0++0x03
line.long 0x00 "IMUCTR42__RT1,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4C36A8++0x03
line.long 0x00 "IMUASID42__RT1,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4C36B0++0x03
line.long 0x00 "IMUCTR43__RT1,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4C36B8++0x03
line.long 0x00 "IMUASID43__RT1,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4C36C0++0x03
line.long 0x00 "IMUCTR44__RT1,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4C36C8++0x03
line.long 0x00 "IMUASID44__RT1,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4C36D0++0x03
line.long 0x00 "IMUCTR45__RT1,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4C36D8++0x03
line.long 0x00 "IMUASID45__RT1,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4C36E0++0x03
line.long 0x00 "IMUCTR46__RT1,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4C36E8++0x03
line.long 0x00 "IMUASID46__RT1,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4C36F0++0x03
line.long 0x00 "IMUCTR47__RT1,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4C36F8++0x03
line.long 0x00 "IMUASID47__RT1,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4C3700++0x03
line.long 0x00 "IMUCTR48__RT1,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4C3708++0x03
line.long 0x00 "IMUASID48__RT1,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4C3710++0x03
line.long 0x00 "IMUCTR49__RT1,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4C3718++0x03
line.long 0x00 "IMUASID49__RT1,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4C3720++0x03
line.long 0x00 "IMUCTR50__RT1,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4C3728++0x03
line.long 0x00 "IMUASID50__RT1,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4C3730++0x03
line.long 0x00 "IMUCTR51__RT1,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4C3738++0x03
line.long 0x00 "IMUASID51__RT1,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4C3740++0x03
line.long 0x00 "IMUCTR52__RT1,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4C3748++0x03
line.long 0x00 "IMUASID52__RT1,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4C3750++0x03
line.long 0x00 "IMUCTR53__RT1,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4C3758++0x03
line.long 0x00 "IMUASID53__RT1,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4C3760++0x03
line.long 0x00 "IMUCTR54__RT1,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4C3768++0x03
line.long 0x00 "IMUASID54__RT1,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4C3770++0x03
line.long 0x00 "IMUCTR55__RT1,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4C3778++0x03
line.long 0x00 "IMUASID55__RT1,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4C3780++0x03
line.long 0x00 "IMUCTR56__RT1,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4C3788++0x03
line.long 0x00 "IMUASID56__RT1,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4C3790++0x03
line.long 0x00 "IMUCTR57__RT1,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4C3798++0x03
line.long 0x00 "IMUASID57__RT1,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4C37A0++0x03
line.long 0x00 "IMUCTR58__RT1,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4C37A8++0x03
line.long 0x00 "IMUASID58__RT1,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4C37B0++0x03
line.long 0x00 "IMUCTR59__RT1,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4C37B8++0x03
line.long 0x00 "IMUASID59__RT1,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4C37C0++0x03
line.long 0x00 "IMUCTR60__RT1,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4C37C8++0x03
line.long 0x00 "IMUASID60__RT1,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4C37D0++0x03
line.long 0x00 "IMUCTR61__RT1,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4C37D8++0x03
line.long 0x00 "IMUASID61__RT1,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4C37E0++0x03
line.long 0x00 "IMUCTR62__RT1,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
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hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4C37E8++0x03
line.long 0x00 "IMUASID62__RT1,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4C37F0++0x03
line.long 0x00 "IMUCTR63__RT1,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
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hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0x4C37F8++0x03
line.long 0x00 "IMUASID63__RT1,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0x4D0000++0x03
line.long 0x00 "IMCTR0__RT1,Note: n= 0 to 15 (IPMMU context) This register controls the behavior of the MMU"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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rbitfld.long 0x00 15. "SEC,Copy of IMSEC.SEC[n]" "0: Behave as non-secure context,1: Behave as secure context"
newline
hexmask.long.word 0x00 3.--14. 1. "Reserved_3,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error occurs,1: Assert an interrupt when an error occurs"
newline
bitfld.long 0x00 1. "FLUSH,TLB Invalidate This bit is automatically cleared to 0" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,MMU Enable" "0: MMU disabled,1: MMU enabled"
group.long 0x4D0040++0x03
line.long 0x00 "IMSEC__RT1,This register controls the attribute of secure/non-secure for MMU"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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hexmask.long.word 0x00 0.--15. 1. "SEC_15_0,SEC[n]=0 : IMCTRn~IMERIDn is Non-secure SEC[n]=1 : IMCTRn~IMERIDn is Secure"
group.long 0x4D1040++0x03
line.long 0x00 "IMCTR1__RT1,Note: n= 0 to 15 (IPMMU context) This register controls the behavior of the MMU"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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rbitfld.long 0x00 15. "SEC,Copy of IMSEC.SEC[n]" "0: Behave as non-secure context,1: Behave as secure context"
newline
hexmask.long.word 0x00 3.--14. 1. "Reserved_3,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error occurs,1: Assert an interrupt when an error occurs"
newline
bitfld.long 0x00 1. "FLUSH,TLB Invalidate This bit is automatically cleared to 0" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,MMU Enable" "0: MMU disabled,1: MMU enabled"
group.long 0x4D2080++0x03
line.long 0x00 "IMCTR2__RT1,Note: n= 0 to 15 (IPMMU context) This register controls the behavior of the MMU"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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rbitfld.long 0x00 15. "SEC,Copy of IMSEC.SEC[n]" "0: Behave as non-secure context,1: Behave as secure context"
newline
hexmask.long.word 0x00 3.--14. 1. "Reserved_3,Reserved These bits are always read as 0"
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bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error occurs,1: Assert an interrupt when an error occurs"
newline
bitfld.long 0x00 1. "FLUSH,TLB Invalidate This bit is automatically cleared to 0" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,MMU Enable" "0: MMU disabled,1: MMU enabled"
group.long 0x4D30C0++0x03
line.long 0x00 "IMCTR3__RT1,Note: n= 0 to 15 (IPMMU context) This register controls the behavior of the MMU"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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rbitfld.long 0x00 15. "SEC,Copy of IMSEC.SEC[n]" "0: Behave as non-secure context,1: Behave as secure context"
newline
hexmask.long.word 0x00 3.--14. 1. "Reserved_3,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error occurs,1: Assert an interrupt when an error occurs"
newline
bitfld.long 0x00 1. "FLUSH,TLB Invalidate This bit is automatically cleared to 0" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,MMU Enable" "0: MMU disabled,1: MMU enabled"
group.long 0x4D4100++0x03
line.long 0x00 "IMCTR4__RT1,Note: n= 0 to 15 (IPMMU context) This register controls the behavior of the MMU"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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rbitfld.long 0x00 15. "SEC,Copy of IMSEC.SEC[n]" "0: Behave as non-secure context,1: Behave as secure context"
newline
hexmask.long.word 0x00 3.--14. 1. "Reserved_3,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error occurs,1: Assert an interrupt when an error occurs"
newline
bitfld.long 0x00 1. "FLUSH,TLB Invalidate This bit is automatically cleared to 0" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,MMU Enable" "0: MMU disabled,1: MMU enabled"
group.long 0x4D5140++0x03
line.long 0x00 "IMCTR5__RT1,Note: n= 0 to 15 (IPMMU context) This register controls the behavior of the MMU"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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rbitfld.long 0x00 15. "SEC,Copy of IMSEC.SEC[n]" "0: Behave as non-secure context,1: Behave as secure context"
newline
hexmask.long.word 0x00 3.--14. 1. "Reserved_3,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error occurs,1: Assert an interrupt when an error occurs"
newline
bitfld.long 0x00 1. "FLUSH,TLB Invalidate This bit is automatically cleared to 0" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,MMU Enable" "0: MMU disabled,1: MMU enabled"
group.long 0x4D6180++0x03
line.long 0x00 "IMCTR6__RT1,Note: n= 0 to 15 (IPMMU context) This register controls the behavior of the MMU"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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rbitfld.long 0x00 15. "SEC,Copy of IMSEC.SEC[n]" "0: Behave as non-secure context,1: Behave as secure context"
newline
hexmask.long.word 0x00 3.--14. 1. "Reserved_3,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error occurs,1: Assert an interrupt when an error occurs"
newline
bitfld.long 0x00 1. "FLUSH,TLB Invalidate This bit is automatically cleared to 0" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,MMU Enable" "0: MMU disabled,1: MMU enabled"
group.long 0x4D71C0++0x03
line.long 0x00 "IMCTR7__RT1,Note: n= 0 to 15 (IPMMU context) This register controls the behavior of the MMU"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 15. "SEC,Copy of IMSEC.SEC[n]" "0: Behave as non-secure context,1: Behave as secure context"
newline
hexmask.long.word 0x00 3.--14. 1. "Reserved_3,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error occurs,1: Assert an interrupt when an error occurs"
newline
bitfld.long 0x00 1. "FLUSH,TLB Invalidate This bit is automatically cleared to 0" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,MMU Enable" "0: MMU disabled,1: MMU enabled"
group.long 0x4D8800++0x03
line.long 0x00 "IMCTR8__RT1,Note: n= 0 to 15 (IPMMU context) This register controls the behavior of the MMU"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 15. "SEC,Copy of IMSEC.SEC[n]" "0: Behave as non-secure context,1: Behave as secure context"
newline
hexmask.long.word 0x00 3.--14. 1. "Reserved_3,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error occurs,1: Assert an interrupt when an error occurs"
newline
bitfld.long 0x00 1. "FLUSH,TLB Invalidate This bit is automatically cleared to 0" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,MMU Enable" "0: MMU disabled,1: MMU enabled"
group.long 0x4D9840++0x03
line.long 0x00 "IMCTR9__RT1,Note: n= 0 to 15 (IPMMU context) This register controls the behavior of the MMU"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 15. "SEC,Copy of IMSEC.SEC[n]" "0: Behave as non-secure context,1: Behave as secure context"
newline
hexmask.long.word 0x00 3.--14. 1. "Reserved_3,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error occurs,1: Assert an interrupt when an error occurs"
newline
bitfld.long 0x00 1. "FLUSH,TLB Invalidate This bit is automatically cleared to 0" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,MMU Enable" "0: MMU disabled,1: MMU enabled"
group.long 0x4DA880++0x03
line.long 0x00 "IMCTR10__RT1,Note: n= 0 to 15 (IPMMU context) This register controls the behavior of the MMU"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 15. "SEC,Copy of IMSEC.SEC[n]" "0: Behave as non-secure context,1: Behave as secure context"
newline
hexmask.long.word 0x00 3.--14. 1. "Reserved_3,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error occurs,1: Assert an interrupt when an error occurs"
newline
bitfld.long 0x00 1. "FLUSH,TLB Invalidate This bit is automatically cleared to 0" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,MMU Enable" "0: MMU disabled,1: MMU enabled"
group.long 0x4DB8C0++0x03
line.long 0x00 "IMCTR11__RT1,Note: n= 0 to 15 (IPMMU context) This register controls the behavior of the MMU"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 15. "SEC,Copy of IMSEC.SEC[n]" "0: Behave as non-secure context,1: Behave as secure context"
newline
hexmask.long.word 0x00 3.--14. 1. "Reserved_3,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error occurs,1: Assert an interrupt when an error occurs"
newline
bitfld.long 0x00 1. "FLUSH,TLB Invalidate This bit is automatically cleared to 0" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,MMU Enable" "0: MMU disabled,1: MMU enabled"
group.long 0x4DC900++0x03
line.long 0x00 "IMCTR12__RT1,Note: n= 0 to 15 (IPMMU context) This register controls the behavior of the MMU"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 15. "SEC,Copy of IMSEC.SEC[n]" "0: Behave as non-secure context,1: Behave as secure context"
newline
hexmask.long.word 0x00 3.--14. 1. "Reserved_3,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error occurs,1: Assert an interrupt when an error occurs"
newline
bitfld.long 0x00 1. "FLUSH,TLB Invalidate This bit is automatically cleared to 0" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,MMU Enable" "0: MMU disabled,1: MMU enabled"
group.long 0x4DD940++0x03
line.long 0x00 "IMCTR13__RT1,Note: n= 0 to 15 (IPMMU context) This register controls the behavior of the MMU"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 15. "SEC,Copy of IMSEC.SEC[n]" "0: Behave as non-secure context,1: Behave as secure context"
newline
hexmask.long.word 0x00 3.--14. 1. "Reserved_3,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error occurs,1: Assert an interrupt when an error occurs"
newline
bitfld.long 0x00 1. "FLUSH,TLB Invalidate This bit is automatically cleared to 0" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,MMU Enable" "0: MMU disabled,1: MMU enabled"
group.long 0x4DE980++0x03
line.long 0x00 "IMCTR14__RT1,Note: n= 0 to 15 (IPMMU context) This register controls the behavior of the MMU"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 15. "SEC,Copy of IMSEC.SEC[n]" "0: Behave as non-secure context,1: Behave as secure context"
newline
hexmask.long.word 0x00 3.--14. 1. "Reserved_3,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error occurs,1: Assert an interrupt when an error occurs"
newline
bitfld.long 0x00 1. "FLUSH,TLB Invalidate This bit is automatically cleared to 0" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,MMU Enable" "0: MMU disabled,1: MMU enabled"
group.long 0x4DF9C0++0x03
line.long 0x00 "IMCTR15__RT1,Note: n= 0 to 15 (IPMMU context) This register controls the behavior of the MMU"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 15. "SEC,Copy of IMSEC.SEC[n]" "0: Behave as non-secure context,1: Behave as secure context"
newline
hexmask.long.word 0x00 3.--14. 1. "Reserved_3,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error occurs,1: Assert an interrupt when an error occurs"
newline
bitfld.long 0x00 1. "FLUSH,TLB Invalidate This bit is automatically cleared to 0" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,MMU Enable" "0: MMU disabled,1: MMU enabled"
group.long 0xD00548++0x03
line.long 0x00 "IMERRSIDAR__DS0,This register indicates the Error SrcID when EDC error happen in AXI AR channel"
bitfld.long 0x00 31. "CLR," "0,1"
newline
hexmask.long.tbyte 0x00 8.--30. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "SRCID_7_0,Read : SrcID of error transaction"
group.long 0xD0054C++0x03
line.long 0x00 "IMERRSIDR__DS0,This register indicates the Error SrcID when EDC error happen in AXI R channel"
bitfld.long 0x00 31. "CLR," "0,1"
newline
hexmask.long.tbyte 0x00 8.--30. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "SRCID_7_0,Read : SrcID of error transaction"
group.long 0xD00558++0x03
line.long 0x00 "IMERRSIDNPTWAR__DS0,This register indicates the Error SrcID when EDC error happen in AXI AR channel with no Page Table Walk"
bitfld.long 0x00 31. "CLR," "0,1"
newline
hexmask.long.tbyte 0x00 8.--30. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "SRCID_7_0,Read : SrcID of error transaction"
group.long 0xD00560++0x03
line.long 0x00 "IMAPQOS__DS0,This resister controls QoS value that is output from IPMMU(cache) to IPMMU(main) through ARADDR[35:32]"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 0.--3. "APQOS_3_0,Append QoS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xD00564++0x03
line.long 0x00 "IMERRSIDRRESP__DS0,This register indicates the Error SrcID when EDC error happen in AXI R(response) channel"
bitfld.long 0x00 31. "CLR," "0,1"
newline
hexmask.long.tbyte 0x00 8.--30. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "SRCID_7_0,Read : SrcID of error transaction"
group.long 0xD00568++0x03
line.long 0x00 "IMERRSIDPA__DS0,This register indicates the Error SrcID when EDC error happen in APB address channel"
bitfld.long 0x00 31. "CLR," "0,1"
newline
hexmask.long.tbyte 0x00 8.--30. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "SRCID_7_0,Read : SrcID of error transaction"
group.long 0xD0056C++0x03
line.long 0x00 "IMERRSIDPWD__DS0,This register indicates the Error SrcID when EDC error happen in APB write data channel"
bitfld.long 0x00 31. "CLR," "0,1"
newline
hexmask.long.tbyte 0x00 8.--30. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "SRCID_7_0,Read : SrcID of error transaction"
group.long 0xD00570++0x03
line.long 0x00 "IMRGID__DS0,Region-ID setting will be available for each IPMMU-hier (each bus hierarchy)"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 0.--3. "RGID_3_0,Region-ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xD00574++0x03
line.long 0x00 "IMRGIDEN__DS0,This register is used for setting to protect IMRGID register"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--15. 1. "RGIDEN_15_0,When RGIDEN[PUSER[5:2]]=1 IMRGID[3:0] register can be accessed"
group.long 0xD00578++0x03
line.long 0x00 "IMSECGRP__DS0,This register is used for setting to protect IMRGID register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 0. "SECGRP,When PUSER[1]=0 if SECGRP=1 RGID register can be accessed" "0,1"
group.long 0xD01500++0x03
line.long 0x00 "IMSCTLR__DS0,This register controls the behavior of IPMMU function"
bitfld.long 0x00 31. "DISWPROT,Read and Write protection of MMU System Control Register and MMU auxiliary Control register" "0: can write IMSCTLR.NSACCEN & IMSCTLR.USE_SECGRP,1: can write/read IMSCTLR.NSACCEN &"
newline
bitfld.long 0x00 30. "NSACCEN,Non-secure access enable for MMU System Control Register and MMU auxiliary Control register" "0: disable non-secure access (default),1: enable non-secure access"
newline
bitfld.long 0x00 29. "DISMMU,Disable IPMMU cache" "0: enable IPMMU cache This bit can be set except,1: disable IPMMU cache"
newline
bitfld.long 0x00 28. "USE_SECGRP,Use security group to judge Secure/Non-secure access Set this bit in IPMMU-DS0 and IPMMU-RT1 0 before using this function" "0,1"
newline
hexmask.long 0x00 0.--27. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0xD01554++0x03
line.long 0x00 "ISERRINJR__DS0,IPMMU cache"
hexmask.long 0x00 7.--31. 1. "Reserved_7,Reserved These bits are always read as 0"
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bitfld.long 0x00 6. "ERRINJ_EDCERR_PWD,Error injection bit for EDC error in APB write datta channel" "0: Clear error injection,1: Enable error injection"
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bitfld.long 0x00 5. "ERRINJ_EDCERR_PA,Error injection bit for EDC error in APB address channel" "0: Clear error injection,1: Enable error injection"
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bitfld.long 0x00 4. "ERRINJ_EDCERR_RRESP,Error injection bit for EDC error in AXI R response channel" "0: Clear error injection,1: Enable error injection"
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bitfld.long 0x00 3. "ERRINJ_EDCERR_NPTW_AR,Error injection bit for EDC error in AXI AR channel (during not Page Table Walk)" "0: Clear error injection,1: Enable error injection"
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bitfld.long 0x00 2. "ERRINJ_COMPFAIL,Error injection bit for DCLS error" "0: Clear error injection,1: Enable error injection"
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bitfld.long 0x00 1. "ERRINJ_EDCERR_R,Error injection bit for EDC error in AXI R channel" "0: Clear error injection,1: Enable error injection"
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bitfld.long 0x00 0. "ERRINJ_EDCERR_AR,Error injection bit for EDC error in AXI AR channel" "0: Clear error injection,1: Enable error injection"
group.long 0xD01580++0x03
line.long 0x00 "IMPFMCTR__DS0,"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are always read as 0"
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bitfld.long 0x00 12.--13. "MD_1_0,Monitor Mode IPMMU (cache)" "0: Monitor all MMUs,1: Reserved,2: Reserved,3: Monitor only MMUn (specified"
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bitfld.long 0x00 8.--11. "SEL_3_0,When MD is B'11 SEL indicates the MMU table number to be monitored" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 2.--7. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 1. "RST,Reset all status and counter values" "0,1"
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bitfld.long 0x00 0. "EN,Performance Monitor Enable" "0: Stop to count,1: Start to count All counters stop when"
group.long 0xD01590++0x03
line.long 0x00 "IMPFMTOTAL__DS0,"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
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hexmask.long.tbyte 0x00 0.--23. 1. "TOTAL_23_0,The total number of translation requests"
group.long 0xD01594++0x03
line.long 0x00 "IMPFMHIT__DS0,"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
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hexmask.long.tbyte 0x00 0.--23. 1. "HIT_23_0,The total number of TLB hit requests"
group.long 0xD01598++0x03
line.long 0x00 "IMPFMMISS__DS0,"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
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hexmask.long.tbyte 0x00 0.--23. 1. "MISS_23_0,The total number of miss requests"
group.long 0xD02200++0x03
line.long 0x00 "IMPCTR__DS0,This register controls the behavior of the PMB function"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--7. "TTSEL_3_0,Translation Table Select Indicates the table number (MMU0  MMU15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 3. "TTEN,TLB Translation Enable" "0: Output PPN as a physical address,1: Output PPN as an intermediate physical address"
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bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error..,1: Assert an interrupt when an error occurred"
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rbitfld.long 0x00 1. "Reserved_1,Reserved This bit is always read as 0" "0,1"
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bitfld.long 0x00 0. "PMBEN,PMB Enable" "0: PMB disabled,1: PMB enabled"
group.long 0xD02208++0x03
line.long 0x00 "IMPSTR__DS0,This register indicates the error status of the address translation by PMB"
hexmask.long 0x00 5.--31. 1. "Reserved_5,Reserved These bits are always read as 0"
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bitfld.long 0x00 4. "MHIT,Multiple hit Indicate that multiple PMB hits occurred" "0,1"
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rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0. "TF,Translation Fault This bit is set to 1 when a translation fault occurred during a PMB translation" "0,1"
group.long 0xD0220C++0x03
line.long 0x00 "IMPEAR__DS0,This register indicates the address which an address translation error occurred"
hexmask.long 0x00 0.--31. 1. "EAR_31_0,The faulting virtual address is set when an address translation error occurred"
group.long 0xD02280++0x03
line.long 0x00 "IMPMBA0__DS0,Note: n= 0 to 15 This register is used for setting the virtual page number"
hexmask.long.byte 0x00 24.--31. 1. "VPN_31_24,Virtual Page Number For 16-Mbyte page VPN[31:24] is used"
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hexmask.long.word 0x00 9.--23. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
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hexmask.long.byte 0x00 0.--7. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0xD02284++0x03
line.long 0x00 "IMPMBA1__DS0,Note: n= 0 to 15 This register is used for setting the virtual page number"
hexmask.long.byte 0x00 24.--31. 1. "VPN_31_24,Virtual Page Number For 16-Mbyte page VPN[31:24] is used"
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hexmask.long.word 0x00 9.--23. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
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hexmask.long.byte 0x00 0.--7. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0xD02288++0x03
line.long 0x00 "IMPMBA2__DS0,Note: n= 0 to 15 This register is used for setting the virtual page number"
hexmask.long.byte 0x00 24.--31. 1. "VPN_31_24,Virtual Page Number For 16-Mbyte page VPN[31:24] is used"
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hexmask.long.word 0x00 9.--23. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
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hexmask.long.byte 0x00 0.--7. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0xD0228C++0x03
line.long 0x00 "IMPMBA3__DS0,Note: n= 0 to 15 This register is used for setting the virtual page number"
hexmask.long.byte 0x00 24.--31. 1. "VPN_31_24,Virtual Page Number For 16-Mbyte page VPN[31:24] is used"
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hexmask.long.word 0x00 9.--23. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
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hexmask.long.byte 0x00 0.--7. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0xD02290++0x03
line.long 0x00 "IMPMBA4__DS0,Note: n= 0 to 15 This register is used for setting the virtual page number"
hexmask.long.byte 0x00 24.--31. 1. "VPN_31_24,Virtual Page Number For 16-Mbyte page VPN[31:24] is used"
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hexmask.long.word 0x00 9.--23. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
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hexmask.long.byte 0x00 0.--7. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0xD02294++0x03
line.long 0x00 "IMPMBA5__DS0,Note: n= 0 to 15 This register is used for setting the virtual page number"
hexmask.long.byte 0x00 24.--31. 1. "VPN_31_24,Virtual Page Number For 16-Mbyte page VPN[31:24] is used"
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hexmask.long.word 0x00 9.--23. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
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hexmask.long.byte 0x00 0.--7. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0xD02298++0x03
line.long 0x00 "IMPMBA6__DS0,Note: n= 0 to 15 This register is used for setting the virtual page number"
hexmask.long.byte 0x00 24.--31. 1. "VPN_31_24,Virtual Page Number For 16-Mbyte page VPN[31:24] is used"
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hexmask.long.word 0x00 9.--23. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
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hexmask.long.byte 0x00 0.--7. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0xD0229C++0x03
line.long 0x00 "IMPMBA7__DS0,Note: n= 0 to 15 This register is used for setting the virtual page number"
hexmask.long.byte 0x00 24.--31. 1. "VPN_31_24,Virtual Page Number For 16-Mbyte page VPN[31:24] is used"
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hexmask.long.word 0x00 9.--23. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
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hexmask.long.byte 0x00 0.--7. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0xD022A0++0x03
line.long 0x00 "IMPMBA8__DS0,Note: n= 0 to 15 This register is used for setting the virtual page number"
hexmask.long.byte 0x00 24.--31. 1. "VPN_31_24,Virtual Page Number For 16-Mbyte page VPN[31:24] is used"
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hexmask.long.word 0x00 9.--23. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
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hexmask.long.byte 0x00 0.--7. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0xD022A4++0x03
line.long 0x00 "IMPMBA9__DS0,Note: n= 0 to 15 This register is used for setting the virtual page number"
hexmask.long.byte 0x00 24.--31. 1. "VPN_31_24,Virtual Page Number For 16-Mbyte page VPN[31:24] is used"
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hexmask.long.word 0x00 9.--23. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
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hexmask.long.byte 0x00 0.--7. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0xD022A8++0x03
line.long 0x00 "IMPMBA10__DS0,Note: n= 0 to 15 This register is used for setting the virtual page number"
hexmask.long.byte 0x00 24.--31. 1. "VPN_31_24,Virtual Page Number For 16-Mbyte page VPN[31:24] is used"
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hexmask.long.word 0x00 9.--23. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
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hexmask.long.byte 0x00 0.--7. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0xD022AC++0x03
line.long 0x00 "IMPMBA11__DS0,Note: n= 0 to 15 This register is used for setting the virtual page number"
hexmask.long.byte 0x00 24.--31. 1. "VPN_31_24,Virtual Page Number For 16-Mbyte page VPN[31:24] is used"
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hexmask.long.word 0x00 9.--23. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
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hexmask.long.byte 0x00 0.--7. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0xD022B0++0x03
line.long 0x00 "IMPMBA12__DS0,Note: n= 0 to 15 This register is used for setting the virtual page number"
hexmask.long.byte 0x00 24.--31. 1. "VPN_31_24,Virtual Page Number For 16-Mbyte page VPN[31:24] is used"
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hexmask.long.word 0x00 9.--23. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
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hexmask.long.byte 0x00 0.--7. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0xD022B4++0x03
line.long 0x00 "IMPMBA13__DS0,Note: n= 0 to 15 This register is used for setting the virtual page number"
hexmask.long.byte 0x00 24.--31. 1. "VPN_31_24,Virtual Page Number For 16-Mbyte page VPN[31:24] is used"
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hexmask.long.word 0x00 9.--23. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
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hexmask.long.byte 0x00 0.--7. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0xD022B8++0x03
line.long 0x00 "IMPMBA14__DS0,Note: n= 0 to 15 This register is used for setting the virtual page number"
hexmask.long.byte 0x00 24.--31. 1. "VPN_31_24,Virtual Page Number For 16-Mbyte page VPN[31:24] is used"
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hexmask.long.word 0x00 9.--23. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
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hexmask.long.byte 0x00 0.--7. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0xD022BC++0x03
line.long 0x00 "IMPMBA15__DS0,Note: n= 0 to 15 This register is used for setting the virtual page number"
hexmask.long.byte 0x00 24.--31. 1. "VPN_31_24,Virtual Page Number For 16-Mbyte page VPN[31:24] is used"
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hexmask.long.word 0x00 9.--23. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
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hexmask.long.byte 0x00 0.--7. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0xD022C0++0x03
line.long 0x00 "IMPMBD0__DS0,Note: n= 0 to 15 This register is used for setting the physical page number and the memory size which PMB managed"
hexmask.long.byte 0x00 24.--31. 1. "PPN_31_24,Physical Page Number For 16-Mbyte page PPN[31:24] is used"
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hexmask.long.byte 0x00 16.--23. 1. "PPN_39_32,Upper Physical Page Number"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
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bitfld.long 0x00 7. "SZ_1,This bit and SZ[0] (bit 4) specify the page size" "0: 16-Mbyte page,1: 64-Mbyte page"
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rbitfld.long 0x00 5.--6. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 4. "SZ_0,Page Size See the description of SZ[1] (bit 7)" "0,1"
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bitfld.long 0x00 3. "C,Cache bit When this bit is set the request after address translation can be treated as cacheable request" "0,1"
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rbitfld.long 0x00 0.--2. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
group.long 0xD022C4++0x03
line.long 0x00 "IMPMBD1__DS0,Note: n= 0 to 15 This register is used for setting the physical page number and the memory size which PMB managed"
hexmask.long.byte 0x00 24.--31. 1. "PPN_31_24,Physical Page Number For 16-Mbyte page PPN[31:24] is used"
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hexmask.long.byte 0x00 16.--23. 1. "PPN_39_32,Upper Physical Page Number"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
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bitfld.long 0x00 7. "SZ_1,This bit and SZ[0] (bit 4) specify the page size" "0: 16-Mbyte page,1: 64-Mbyte page"
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rbitfld.long 0x00 5.--6. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 4. "SZ_0,Page Size See the description of SZ[1] (bit 7)" "0,1"
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bitfld.long 0x00 3. "C,Cache bit When this bit is set the request after address translation can be treated as cacheable request" "0,1"
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rbitfld.long 0x00 0.--2. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
group.long 0xD022C8++0x03
line.long 0x00 "IMPMBD2__DS0,Note: n= 0 to 15 This register is used for setting the physical page number and the memory size which PMB managed"
hexmask.long.byte 0x00 24.--31. 1. "PPN_31_24,Physical Page Number For 16-Mbyte page PPN[31:24] is used"
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hexmask.long.byte 0x00 16.--23. 1. "PPN_39_32,Upper Physical Page Number"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
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bitfld.long 0x00 7. "SZ_1,This bit and SZ[0] (bit 4) specify the page size" "0: 16-Mbyte page,1: 64-Mbyte page"
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rbitfld.long 0x00 5.--6. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 4. "SZ_0,Page Size See the description of SZ[1] (bit 7)" "0,1"
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bitfld.long 0x00 3. "C,Cache bit When this bit is set the request after address translation can be treated as cacheable request" "0,1"
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rbitfld.long 0x00 0.--2. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
group.long 0xD022CC++0x03
line.long 0x00 "IMPMBD3__DS0,Note: n= 0 to 15 This register is used for setting the physical page number and the memory size which PMB managed"
hexmask.long.byte 0x00 24.--31. 1. "PPN_31_24,Physical Page Number For 16-Mbyte page PPN[31:24] is used"
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hexmask.long.byte 0x00 16.--23. 1. "PPN_39_32,Upper Physical Page Number"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
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bitfld.long 0x00 7. "SZ_1,This bit and SZ[0] (bit 4) specify the page size" "0: 16-Mbyte page,1: 64-Mbyte page"
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rbitfld.long 0x00 5.--6. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 4. "SZ_0,Page Size See the description of SZ[1] (bit 7)" "0,1"
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bitfld.long 0x00 3. "C,Cache bit When this bit is set the request after address translation can be treated as cacheable request" "0,1"
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rbitfld.long 0x00 0.--2. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
group.long 0xD022D0++0x03
line.long 0x00 "IMPMBD4__DS0,Note: n= 0 to 15 This register is used for setting the physical page number and the memory size which PMB managed"
hexmask.long.byte 0x00 24.--31. 1. "PPN_31_24,Physical Page Number For 16-Mbyte page PPN[31:24] is used"
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hexmask.long.byte 0x00 16.--23. 1. "PPN_39_32,Upper Physical Page Number"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
bitfld.long 0x00 7. "SZ_1,This bit and SZ[0] (bit 4) specify the page size" "0: 16-Mbyte page,1: 64-Mbyte page"
newline
rbitfld.long 0x00 5.--6. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 4. "SZ_0,Page Size See the description of SZ[1] (bit 7)" "0,1"
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bitfld.long 0x00 3. "C,Cache bit When this bit is set the request after address translation can be treated as cacheable request" "0,1"
newline
rbitfld.long 0x00 0.--2. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
group.long 0xD022D4++0x03
line.long 0x00 "IMPMBD5__DS0,Note: n= 0 to 15 This register is used for setting the physical page number and the memory size which PMB managed"
hexmask.long.byte 0x00 24.--31. 1. "PPN_31_24,Physical Page Number For 16-Mbyte page PPN[31:24] is used"
newline
hexmask.long.byte 0x00 16.--23. 1. "PPN_39_32,Upper Physical Page Number"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
bitfld.long 0x00 7. "SZ_1,This bit and SZ[0] (bit 4) specify the page size" "0: 16-Mbyte page,1: 64-Mbyte page"
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rbitfld.long 0x00 5.--6. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 4. "SZ_0,Page Size See the description of SZ[1] (bit 7)" "0,1"
newline
bitfld.long 0x00 3. "C,Cache bit When this bit is set the request after address translation can be treated as cacheable request" "0,1"
newline
rbitfld.long 0x00 0.--2. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
group.long 0xD022D8++0x03
line.long 0x00 "IMPMBD6__DS0,Note: n= 0 to 15 This register is used for setting the physical page number and the memory size which PMB managed"
hexmask.long.byte 0x00 24.--31. 1. "PPN_31_24,Physical Page Number For 16-Mbyte page PPN[31:24] is used"
newline
hexmask.long.byte 0x00 16.--23. 1. "PPN_39_32,Upper Physical Page Number"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
bitfld.long 0x00 7. "SZ_1,This bit and SZ[0] (bit 4) specify the page size" "0: 16-Mbyte page,1: 64-Mbyte page"
newline
rbitfld.long 0x00 5.--6. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 4. "SZ_0,Page Size See the description of SZ[1] (bit 7)" "0,1"
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bitfld.long 0x00 3. "C,Cache bit When this bit is set the request after address translation can be treated as cacheable request" "0,1"
newline
rbitfld.long 0x00 0.--2. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
group.long 0xD022DC++0x03
line.long 0x00 "IMPMBD7__DS0,Note: n= 0 to 15 This register is used for setting the physical page number and the memory size which PMB managed"
hexmask.long.byte 0x00 24.--31. 1. "PPN_31_24,Physical Page Number For 16-Mbyte page PPN[31:24] is used"
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hexmask.long.byte 0x00 16.--23. 1. "PPN_39_32,Upper Physical Page Number"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
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bitfld.long 0x00 7. "SZ_1,This bit and SZ[0] (bit 4) specify the page size" "0: 16-Mbyte page,1: 64-Mbyte page"
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rbitfld.long 0x00 5.--6. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 4. "SZ_0,Page Size See the description of SZ[1] (bit 7)" "0,1"
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bitfld.long 0x00 3. "C,Cache bit When this bit is set the request after address translation can be treated as cacheable request" "0,1"
newline
rbitfld.long 0x00 0.--2. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
group.long 0xD022E0++0x03
line.long 0x00 "IMPMBD8__DS0,Note: n= 0 to 15 This register is used for setting the physical page number and the memory size which PMB managed"
hexmask.long.byte 0x00 24.--31. 1. "PPN_31_24,Physical Page Number For 16-Mbyte page PPN[31:24] is used"
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hexmask.long.byte 0x00 16.--23. 1. "PPN_39_32,Upper Physical Page Number"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
bitfld.long 0x00 7. "SZ_1,This bit and SZ[0] (bit 4) specify the page size" "0: 16-Mbyte page,1: 64-Mbyte page"
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rbitfld.long 0x00 5.--6. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 4. "SZ_0,Page Size See the description of SZ[1] (bit 7)" "0,1"
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bitfld.long 0x00 3. "C,Cache bit When this bit is set the request after address translation can be treated as cacheable request" "0,1"
newline
rbitfld.long 0x00 0.--2. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
group.long 0xD022E4++0x03
line.long 0x00 "IMPMBD9__DS0,Note: n= 0 to 15 This register is used for setting the physical page number and the memory size which PMB managed"
hexmask.long.byte 0x00 24.--31. 1. "PPN_31_24,Physical Page Number For 16-Mbyte page PPN[31:24] is used"
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hexmask.long.byte 0x00 16.--23. 1. "PPN_39_32,Upper Physical Page Number"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
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bitfld.long 0x00 7. "SZ_1,This bit and SZ[0] (bit 4) specify the page size" "0: 16-Mbyte page,1: 64-Mbyte page"
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rbitfld.long 0x00 5.--6. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 4. "SZ_0,Page Size See the description of SZ[1] (bit 7)" "0,1"
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bitfld.long 0x00 3. "C,Cache bit When this bit is set the request after address translation can be treated as cacheable request" "0,1"
newline
rbitfld.long 0x00 0.--2. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
group.long 0xD022E8++0x03
line.long 0x00 "IMPMBD10__DS0,Note: n= 0 to 15 This register is used for setting the physical page number and the memory size which PMB managed"
hexmask.long.byte 0x00 24.--31. 1. "PPN_31_24,Physical Page Number For 16-Mbyte page PPN[31:24] is used"
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hexmask.long.byte 0x00 16.--23. 1. "PPN_39_32,Upper Physical Page Number"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
bitfld.long 0x00 7. "SZ_1,This bit and SZ[0] (bit 4) specify the page size" "0: 16-Mbyte page,1: 64-Mbyte page"
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rbitfld.long 0x00 5.--6. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 4. "SZ_0,Page Size See the description of SZ[1] (bit 7)" "0,1"
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bitfld.long 0x00 3. "C,Cache bit When this bit is set the request after address translation can be treated as cacheable request" "0,1"
newline
rbitfld.long 0x00 0.--2. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
group.long 0xD022EC++0x03
line.long 0x00 "IMPMBD11__DS0,Note: n= 0 to 15 This register is used for setting the physical page number and the memory size which PMB managed"
hexmask.long.byte 0x00 24.--31. 1. "PPN_31_24,Physical Page Number For 16-Mbyte page PPN[31:24] is used"
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hexmask.long.byte 0x00 16.--23. 1. "PPN_39_32,Upper Physical Page Number"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
bitfld.long 0x00 7. "SZ_1,This bit and SZ[0] (bit 4) specify the page size" "0: 16-Mbyte page,1: 64-Mbyte page"
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rbitfld.long 0x00 5.--6. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 4. "SZ_0,Page Size See the description of SZ[1] (bit 7)" "0,1"
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bitfld.long 0x00 3. "C,Cache bit When this bit is set the request after address translation can be treated as cacheable request" "0,1"
newline
rbitfld.long 0x00 0.--2. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
group.long 0xD022F0++0x03
line.long 0x00 "IMPMBD12__DS0,Note: n= 0 to 15 This register is used for setting the physical page number and the memory size which PMB managed"
hexmask.long.byte 0x00 24.--31. 1. "PPN_31_24,Physical Page Number For 16-Mbyte page PPN[31:24] is used"
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hexmask.long.byte 0x00 16.--23. 1. "PPN_39_32,Upper Physical Page Number"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
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bitfld.long 0x00 7. "SZ_1,This bit and SZ[0] (bit 4) specify the page size" "0: 16-Mbyte page,1: 64-Mbyte page"
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rbitfld.long 0x00 5.--6. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 4. "SZ_0,Page Size See the description of SZ[1] (bit 7)" "0,1"
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bitfld.long 0x00 3. "C,Cache bit When this bit is set the request after address translation can be treated as cacheable request" "0,1"
newline
rbitfld.long 0x00 0.--2. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
group.long 0xD022F4++0x03
line.long 0x00 "IMPMBD13__DS0,Note: n= 0 to 15 This register is used for setting the physical page number and the memory size which PMB managed"
hexmask.long.byte 0x00 24.--31. 1. "PPN_31_24,Physical Page Number For 16-Mbyte page PPN[31:24] is used"
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hexmask.long.byte 0x00 16.--23. 1. "PPN_39_32,Upper Physical Page Number"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
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bitfld.long 0x00 7. "SZ_1,This bit and SZ[0] (bit 4) specify the page size" "0: 16-Mbyte page,1: 64-Mbyte page"
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rbitfld.long 0x00 5.--6. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 4. "SZ_0,Page Size See the description of SZ[1] (bit 7)" "0,1"
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bitfld.long 0x00 3. "C,Cache bit When this bit is set the request after address translation can be treated as cacheable request" "0,1"
newline
rbitfld.long 0x00 0.--2. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
group.long 0xD022F8++0x03
line.long 0x00 "IMPMBD14__DS0,Note: n= 0 to 15 This register is used for setting the physical page number and the memory size which PMB managed"
hexmask.long.byte 0x00 24.--31. 1. "PPN_31_24,Physical Page Number For 16-Mbyte page PPN[31:24] is used"
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hexmask.long.byte 0x00 16.--23. 1. "PPN_39_32,Upper Physical Page Number"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
bitfld.long 0x00 7. "SZ_1,This bit and SZ[0] (bit 4) specify the page size" "0: 16-Mbyte page,1: 64-Mbyte page"
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rbitfld.long 0x00 5.--6. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 4. "SZ_0,Page Size See the description of SZ[1] (bit 7)" "0,1"
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bitfld.long 0x00 3. "C,Cache bit When this bit is set the request after address translation can be treated as cacheable request" "0,1"
newline
rbitfld.long 0x00 0.--2. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
group.long 0xD022FC++0x03
line.long 0x00 "IMPMBD15__DS0,Note: n= 0 to 15 This register is used for setting the physical page number and the memory size which PMB managed"
hexmask.long.byte 0x00 24.--31. 1. "PPN_31_24,Physical Page Number For 16-Mbyte page PPN[31:24] is used"
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hexmask.long.byte 0x00 16.--23. 1. "PPN_39_32,Upper Physical Page Number"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
bitfld.long 0x00 7. "SZ_1,This bit and SZ[0] (bit 4) specify the page size" "0: 16-Mbyte page,1: 64-Mbyte page"
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rbitfld.long 0x00 5.--6. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 4. "SZ_0,Page Size See the description of SZ[1] (bit 7)" "0,1"
newline
bitfld.long 0x00 3. "C,Cache bit When this bit is set the request after address translation can be treated as cacheable request" "0,1"
newline
rbitfld.long 0x00 0.--2. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
group.long 0xD03300++0x03
line.long 0x00 "IMUCTR0__DS0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
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hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD03308++0x03
line.long 0x00 "IMUASID0__DS0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD03310++0x03
line.long 0x00 "IMUCTR1__DS0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
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hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD03318++0x03
line.long 0x00 "IMUASID1__DS0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD03320++0x03
line.long 0x00 "IMUCTR2__DS0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD03328++0x03
line.long 0x00 "IMUASID2__DS0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD03330++0x03
line.long 0x00 "IMUCTR3__DS0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD03338++0x03
line.long 0x00 "IMUASID3__DS0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD03340++0x03
line.long 0x00 "IMUCTR4__DS0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD03348++0x03
line.long 0x00 "IMUASID4__DS0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD03350++0x03
line.long 0x00 "IMUCTR5__DS0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD03358++0x03
line.long 0x00 "IMUASID5__DS0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD03360++0x03
line.long 0x00 "IMUCTR6__DS0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD03368++0x03
line.long 0x00 "IMUASID6__DS0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD03370++0x03
line.long 0x00 "IMUCTR7__DS0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
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hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
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rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD03378++0x03
line.long 0x00 "IMUASID7__DS0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD03380++0x03
line.long 0x00 "IMUCTR8__DS0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
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hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD03388++0x03
line.long 0x00 "IMUASID8__DS0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD03390++0x03
line.long 0x00 "IMUCTR9__DS0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
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hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD03398++0x03
line.long 0x00 "IMUASID9__DS0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD033A0++0x03
line.long 0x00 "IMUCTR10__DS0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
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hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD033A8++0x03
line.long 0x00 "IMUASID10__DS0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD033B0++0x03
line.long 0x00 "IMUCTR11__DS0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD033B8++0x03
line.long 0x00 "IMUASID11__DS0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD033C0++0x03
line.long 0x00 "IMUCTR12__DS0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
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hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD033C8++0x03
line.long 0x00 "IMUASID12__DS0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD033D0++0x03
line.long 0x00 "IMUCTR13__DS0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD033D8++0x03
line.long 0x00 "IMUASID13__DS0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD033E0++0x03
line.long 0x00 "IMUCTR14__DS0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD033E8++0x03
line.long 0x00 "IMUASID14__DS0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD033F0++0x03
line.long 0x00 "IMUCTR15__DS0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD033F8++0x03
line.long 0x00 "IMUASID15__DS0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD03400++0x03
line.long 0x00 "IMUCTR16__DS0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD03408++0x03
line.long 0x00 "IMUASID16__DS0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD03410++0x03
line.long 0x00 "IMUCTR17__DS0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD03418++0x03
line.long 0x00 "IMUASID17__DS0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD03420++0x03
line.long 0x00 "IMUCTR18__DS0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD03428++0x03
line.long 0x00 "IMUASID18__DS0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD03430++0x03
line.long 0x00 "IMUCTR19__DS0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
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hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
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rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
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bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD03438++0x03
line.long 0x00 "IMUASID19__DS0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
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hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD03440++0x03
line.long 0x00 "IMUCTR20__DS0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
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hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
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rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
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bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD03448++0x03
line.long 0x00 "IMUASID20__DS0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
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hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD03450++0x03
line.long 0x00 "IMUCTR21__DS0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
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hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
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rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
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bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD03458++0x03
line.long 0x00 "IMUASID21__DS0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
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hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD03460++0x03
line.long 0x00 "IMUCTR22__DS0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
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hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
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rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
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bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD03468++0x03
line.long 0x00 "IMUASID22__DS0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
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hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD03470++0x03
line.long 0x00 "IMUCTR23__DS0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
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hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
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rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
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bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD03478++0x03
line.long 0x00 "IMUASID23__DS0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
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hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD03480++0x03
line.long 0x00 "IMUCTR24__DS0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
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hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
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rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
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bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD03488++0x03
line.long 0x00 "IMUASID24__DS0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
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hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD03490++0x03
line.long 0x00 "IMUCTR25__DS0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
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hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
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rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
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bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD03498++0x03
line.long 0x00 "IMUASID25__DS0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
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hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD034A0++0x03
line.long 0x00 "IMUCTR26__DS0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
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hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
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rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
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bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD034A8++0x03
line.long 0x00 "IMUASID26__DS0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
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hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD034B0++0x03
line.long 0x00 "IMUCTR27__DS0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
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hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
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rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
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bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD034B8++0x03
line.long 0x00 "IMUASID27__DS0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
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hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD034C0++0x03
line.long 0x00 "IMUCTR28__DS0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
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hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
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rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
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bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD034C8++0x03
line.long 0x00 "IMUASID28__DS0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
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hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD034D0++0x03
line.long 0x00 "IMUCTR29__DS0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
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hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
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rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
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bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD034D8++0x03
line.long 0x00 "IMUASID29__DS0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
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hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD034E0++0x03
line.long 0x00 "IMUCTR30__DS0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
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hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
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bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD034E8++0x03
line.long 0x00 "IMUASID30__DS0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
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hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD034F0++0x03
line.long 0x00 "IMUCTR31__DS0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
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hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
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rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
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bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD034F8++0x03
line.long 0x00 "IMUASID31__DS0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
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hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD03600++0x03
line.long 0x00 "IMUCTR32__DS0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
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hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
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rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
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bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD03608++0x03
line.long 0x00 "IMUASID32__DS0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
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hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD03610++0x03
line.long 0x00 "IMUCTR33__DS0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
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hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
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rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
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bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD03618++0x03
line.long 0x00 "IMUASID33__DS0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
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hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD03620++0x03
line.long 0x00 "IMUCTR34__DS0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
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hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
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rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
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bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD03628++0x03
line.long 0x00 "IMUASID34__DS0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
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hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD03630++0x03
line.long 0x00 "IMUCTR35__DS0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
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hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
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rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD03638++0x03
line.long 0x00 "IMUASID35__DS0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
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hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD03640++0x03
line.long 0x00 "IMUCTR36__DS0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
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hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
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rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD03648++0x03
line.long 0x00 "IMUASID36__DS0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
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hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD03650++0x03
line.long 0x00 "IMUCTR37__DS0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
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hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
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rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD03658++0x03
line.long 0x00 "IMUASID37__DS0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
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hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD03660++0x03
line.long 0x00 "IMUCTR38__DS0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
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hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD03668++0x03
line.long 0x00 "IMUASID38__DS0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
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hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD03670++0x03
line.long 0x00 "IMUCTR39__DS0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
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hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD03678++0x03
line.long 0x00 "IMUASID39__DS0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
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hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD03680++0x03
line.long 0x00 "IMUCTR40__DS0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
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hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
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rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD03688++0x03
line.long 0x00 "IMUASID40__DS0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
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hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD03690++0x03
line.long 0x00 "IMUCTR41__DS0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
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hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD03698++0x03
line.long 0x00 "IMUASID41__DS0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
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hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD036A0++0x03
line.long 0x00 "IMUCTR42__DS0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD036A8++0x03
line.long 0x00 "IMUASID42__DS0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD036B0++0x03
line.long 0x00 "IMUCTR43__DS0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
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hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD036B8++0x03
line.long 0x00 "IMUASID43__DS0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
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hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD036C0++0x03
line.long 0x00 "IMUCTR44__DS0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
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hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
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rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
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bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD036C8++0x03
line.long 0x00 "IMUASID44__DS0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
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hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD036D0++0x03
line.long 0x00 "IMUCTR45__DS0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
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hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
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rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
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bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD036D8++0x03
line.long 0x00 "IMUASID45__DS0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
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hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD036E0++0x03
line.long 0x00 "IMUCTR46__DS0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
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hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
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rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
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bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD036E8++0x03
line.long 0x00 "IMUASID46__DS0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
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hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD036F0++0x03
line.long 0x00 "IMUCTR47__DS0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
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hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
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rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
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bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD036F8++0x03
line.long 0x00 "IMUASID47__DS0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
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hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD03700++0x03
line.long 0x00 "IMUCTR48__DS0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
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hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
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rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
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bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD03708++0x03
line.long 0x00 "IMUASID48__DS0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
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hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD03710++0x03
line.long 0x00 "IMUCTR49__DS0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
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hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
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rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
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bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD03718++0x03
line.long 0x00 "IMUASID49__DS0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
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hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD03720++0x03
line.long 0x00 "IMUCTR50__DS0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
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hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
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rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
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bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD03728++0x03
line.long 0x00 "IMUASID50__DS0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
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hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD03730++0x03
line.long 0x00 "IMUCTR51__DS0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
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hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
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rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
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bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD03738++0x03
line.long 0x00 "IMUASID51__DS0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
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hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD03740++0x03
line.long 0x00 "IMUCTR52__DS0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
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hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
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rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
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bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD03748++0x03
line.long 0x00 "IMUASID52__DS0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
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hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD03750++0x03
line.long 0x00 "IMUCTR53__DS0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
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hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
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rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD03758++0x03
line.long 0x00 "IMUASID53__DS0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
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hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD03760++0x03
line.long 0x00 "IMUCTR54__DS0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
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hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD03768++0x03
line.long 0x00 "IMUASID54__DS0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
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hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD03770++0x03
line.long 0x00 "IMUCTR55__DS0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
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hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD03778++0x03
line.long 0x00 "IMUASID55__DS0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
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hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD03780++0x03
line.long 0x00 "IMUCTR56__DS0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
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hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD03788++0x03
line.long 0x00 "IMUASID56__DS0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
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hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD03790++0x03
line.long 0x00 "IMUCTR57__DS0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
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hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
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rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD03798++0x03
line.long 0x00 "IMUASID57__DS0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD037A0++0x03
line.long 0x00 "IMUCTR58__DS0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
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hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
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rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD037A8++0x03
line.long 0x00 "IMUASID58__DS0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD037B0++0x03
line.long 0x00 "IMUCTR59__DS0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
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hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD037B8++0x03
line.long 0x00 "IMUASID59__DS0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD037C0++0x03
line.long 0x00 "IMUCTR60__DS0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
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hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD037C8++0x03
line.long 0x00 "IMUASID60__DS0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD037D0++0x03
line.long 0x00 "IMUCTR61__DS0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
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hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD037D8++0x03
line.long 0x00 "IMUASID61__DS0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD037E0++0x03
line.long 0x00 "IMUCTR62__DS0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD037E8++0x03
line.long 0x00 "IMUASID62__DS0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD037F0++0x03
line.long 0x00 "IMUCTR63__DS0,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD037F8++0x03
line.long 0x00 "IMUASID63__DS0,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD10000++0x03
line.long 0x00 "IMCTR0__DS0,Note: n= 0 to 15 (IPMMU context) This register controls the behavior of the MMU"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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rbitfld.long 0x00 15. "SEC,Copy of IMSEC.SEC[n]" "0: Behave as non-secure context,1: Behave as secure context"
newline
hexmask.long.word 0x00 3.--14. 1. "Reserved_3,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error occurs,1: Assert an interrupt when an error occurs"
newline
bitfld.long 0x00 1. "FLUSH,TLB Invalidate This bit is automatically cleared to 0" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,MMU Enable" "0: MMU disabled,1: MMU enabled"
group.long 0xD10040++0x03
line.long 0x00 "IMSEC__DS0,This register controls the attribute of secure/non-secure for MMU"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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hexmask.long.word 0x00 0.--15. 1. "SEC_15_0,SEC[n]=0 : IMCTRn~IMERIDn is Non-secure SEC[n]=1 : IMCTRn~IMERIDn is Secure"
group.long 0xD11040++0x03
line.long 0x00 "IMCTR1__DS0,Note: n= 0 to 15 (IPMMU context) This register controls the behavior of the MMU"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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rbitfld.long 0x00 15. "SEC,Copy of IMSEC.SEC[n]" "0: Behave as non-secure context,1: Behave as secure context"
newline
hexmask.long.word 0x00 3.--14. 1. "Reserved_3,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error occurs,1: Assert an interrupt when an error occurs"
newline
bitfld.long 0x00 1. "FLUSH,TLB Invalidate This bit is automatically cleared to 0" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,MMU Enable" "0: MMU disabled,1: MMU enabled"
group.long 0xD12080++0x03
line.long 0x00 "IMCTR2__DS0,Note: n= 0 to 15 (IPMMU context) This register controls the behavior of the MMU"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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rbitfld.long 0x00 15. "SEC,Copy of IMSEC.SEC[n]" "0: Behave as non-secure context,1: Behave as secure context"
newline
hexmask.long.word 0x00 3.--14. 1. "Reserved_3,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error occurs,1: Assert an interrupt when an error occurs"
newline
bitfld.long 0x00 1. "FLUSH,TLB Invalidate This bit is automatically cleared to 0" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,MMU Enable" "0: MMU disabled,1: MMU enabled"
group.long 0xD130C0++0x03
line.long 0x00 "IMCTR3__DS0,Note: n= 0 to 15 (IPMMU context) This register controls the behavior of the MMU"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 15. "SEC,Copy of IMSEC.SEC[n]" "0: Behave as non-secure context,1: Behave as secure context"
newline
hexmask.long.word 0x00 3.--14. 1. "Reserved_3,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error occurs,1: Assert an interrupt when an error occurs"
newline
bitfld.long 0x00 1. "FLUSH,TLB Invalidate This bit is automatically cleared to 0" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,MMU Enable" "0: MMU disabled,1: MMU enabled"
group.long 0xD14100++0x03
line.long 0x00 "IMCTR4__DS0,Note: n= 0 to 15 (IPMMU context) This register controls the behavior of the MMU"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 15. "SEC,Copy of IMSEC.SEC[n]" "0: Behave as non-secure context,1: Behave as secure context"
newline
hexmask.long.word 0x00 3.--14. 1. "Reserved_3,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error occurs,1: Assert an interrupt when an error occurs"
newline
bitfld.long 0x00 1. "FLUSH,TLB Invalidate This bit is automatically cleared to 0" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,MMU Enable" "0: MMU disabled,1: MMU enabled"
group.long 0xD15140++0x03
line.long 0x00 "IMCTR5__DS0,Note: n= 0 to 15 (IPMMU context) This register controls the behavior of the MMU"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 15. "SEC,Copy of IMSEC.SEC[n]" "0: Behave as non-secure context,1: Behave as secure context"
newline
hexmask.long.word 0x00 3.--14. 1. "Reserved_3,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error occurs,1: Assert an interrupt when an error occurs"
newline
bitfld.long 0x00 1. "FLUSH,TLB Invalidate This bit is automatically cleared to 0" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,MMU Enable" "0: MMU disabled,1: MMU enabled"
group.long 0xD16180++0x03
line.long 0x00 "IMCTR6__DS0,Note: n= 0 to 15 (IPMMU context) This register controls the behavior of the MMU"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 15. "SEC,Copy of IMSEC.SEC[n]" "0: Behave as non-secure context,1: Behave as secure context"
newline
hexmask.long.word 0x00 3.--14. 1. "Reserved_3,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error occurs,1: Assert an interrupt when an error occurs"
newline
bitfld.long 0x00 1. "FLUSH,TLB Invalidate This bit is automatically cleared to 0" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,MMU Enable" "0: MMU disabled,1: MMU enabled"
group.long 0xD171C0++0x03
line.long 0x00 "IMCTR7__DS0,Note: n= 0 to 15 (IPMMU context) This register controls the behavior of the MMU"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 15. "SEC,Copy of IMSEC.SEC[n]" "0: Behave as non-secure context,1: Behave as secure context"
newline
hexmask.long.word 0x00 3.--14. 1. "Reserved_3,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error occurs,1: Assert an interrupt when an error occurs"
newline
bitfld.long 0x00 1. "FLUSH,TLB Invalidate This bit is automatically cleared to 0" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,MMU Enable" "0: MMU disabled,1: MMU enabled"
group.long 0xD18800++0x03
line.long 0x00 "IMCTR8__DS0,Note: n= 0 to 15 (IPMMU context) This register controls the behavior of the MMU"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 15. "SEC,Copy of IMSEC.SEC[n]" "0: Behave as non-secure context,1: Behave as secure context"
newline
hexmask.long.word 0x00 3.--14. 1. "Reserved_3,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error occurs,1: Assert an interrupt when an error occurs"
newline
bitfld.long 0x00 1. "FLUSH,TLB Invalidate This bit is automatically cleared to 0" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,MMU Enable" "0: MMU disabled,1: MMU enabled"
group.long 0xD19840++0x03
line.long 0x00 "IMCTR9__DS0,Note: n= 0 to 15 (IPMMU context) This register controls the behavior of the MMU"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 15. "SEC,Copy of IMSEC.SEC[n]" "0: Behave as non-secure context,1: Behave as secure context"
newline
hexmask.long.word 0x00 3.--14. 1. "Reserved_3,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error occurs,1: Assert an interrupt when an error occurs"
newline
bitfld.long 0x00 1. "FLUSH,TLB Invalidate This bit is automatically cleared to 0" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,MMU Enable" "0: MMU disabled,1: MMU enabled"
group.long 0xD1A880++0x03
line.long 0x00 "IMCTR10__DS0,Note: n= 0 to 15 (IPMMU context) This register controls the behavior of the MMU"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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rbitfld.long 0x00 15. "SEC,Copy of IMSEC.SEC[n]" "0: Behave as non-secure context,1: Behave as secure context"
newline
hexmask.long.word 0x00 3.--14. 1. "Reserved_3,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error occurs,1: Assert an interrupt when an error occurs"
newline
bitfld.long 0x00 1. "FLUSH,TLB Invalidate This bit is automatically cleared to 0" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,MMU Enable" "0: MMU disabled,1: MMU enabled"
group.long 0xD1B8C0++0x03
line.long 0x00 "IMCTR11__DS0,Note: n= 0 to 15 (IPMMU context) This register controls the behavior of the MMU"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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rbitfld.long 0x00 15. "SEC,Copy of IMSEC.SEC[n]" "0: Behave as non-secure context,1: Behave as secure context"
newline
hexmask.long.word 0x00 3.--14. 1. "Reserved_3,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error occurs,1: Assert an interrupt when an error occurs"
newline
bitfld.long 0x00 1. "FLUSH,TLB Invalidate This bit is automatically cleared to 0" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,MMU Enable" "0: MMU disabled,1: MMU enabled"
group.long 0xD1C900++0x03
line.long 0x00 "IMCTR12__DS0,Note: n= 0 to 15 (IPMMU context) This register controls the behavior of the MMU"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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rbitfld.long 0x00 15. "SEC,Copy of IMSEC.SEC[n]" "0: Behave as non-secure context,1: Behave as secure context"
newline
hexmask.long.word 0x00 3.--14. 1. "Reserved_3,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error occurs,1: Assert an interrupt when an error occurs"
newline
bitfld.long 0x00 1. "FLUSH,TLB Invalidate This bit is automatically cleared to 0" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,MMU Enable" "0: MMU disabled,1: MMU enabled"
group.long 0xD1D940++0x03
line.long 0x00 "IMCTR13__DS0,Note: n= 0 to 15 (IPMMU context) This register controls the behavior of the MMU"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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rbitfld.long 0x00 15. "SEC,Copy of IMSEC.SEC[n]" "0: Behave as non-secure context,1: Behave as secure context"
newline
hexmask.long.word 0x00 3.--14. 1. "Reserved_3,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error occurs,1: Assert an interrupt when an error occurs"
newline
bitfld.long 0x00 1. "FLUSH,TLB Invalidate This bit is automatically cleared to 0" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,MMU Enable" "0: MMU disabled,1: MMU enabled"
group.long 0xD1E980++0x03
line.long 0x00 "IMCTR14__DS0,Note: n= 0 to 15 (IPMMU context) This register controls the behavior of the MMU"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 15. "SEC,Copy of IMSEC.SEC[n]" "0: Behave as non-secure context,1: Behave as secure context"
newline
hexmask.long.word 0x00 3.--14. 1. "Reserved_3,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error occurs,1: Assert an interrupt when an error occurs"
newline
bitfld.long 0x00 1. "FLUSH,TLB Invalidate This bit is automatically cleared to 0" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,MMU Enable" "0: MMU disabled,1: MMU enabled"
group.long 0xD1F9C0++0x03
line.long 0x00 "IMCTR15__DS0,Note: n= 0 to 15 (IPMMU context) This register controls the behavior of the MMU"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 15. "SEC,Copy of IMSEC.SEC[n]" "0: Behave as non-secure context,1: Behave as secure context"
newline
hexmask.long.word 0x00 3.--14. 1. "Reserved_3,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error occurs,1: Assert an interrupt when an error occurs"
newline
bitfld.long 0x00 1. "FLUSH,TLB Invalidate This bit is automatically cleared to 0" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,MMU Enable" "0: MMU disabled,1: MMU enabled"
group.long 0xD40548++0x03
line.long 0x00 "IMERRSIDAR__HC,This register indicates the Error SrcID when EDC error happen in AXI AR channel"
bitfld.long 0x00 31. "CLR," "0,1"
newline
hexmask.long.tbyte 0x00 8.--30. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "SRCID_7_0,Read : SrcID of error transaction"
group.long 0xD4054C++0x03
line.long 0x00 "IMERRSIDR__HC,This register indicates the Error SrcID when EDC error happen in AXI R channel"
bitfld.long 0x00 31. "CLR," "0,1"
newline
hexmask.long.tbyte 0x00 8.--30. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "SRCID_7_0,Read : SrcID of error transaction"
group.long 0xD40558++0x03
line.long 0x00 "IMERRSIDNPTWAR__HC,This register indicates the Error SrcID when EDC error happen in AXI AR channel with no Page Table Walk"
bitfld.long 0x00 31. "CLR," "0,1"
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hexmask.long.tbyte 0x00 8.--30. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "SRCID_7_0,Read : SrcID of error transaction"
group.long 0xD40560++0x03
line.long 0x00 "IMAPQOS__HC,This resister controls QoS value that is output from IPMMU(cache) to IPMMU(main) through ARADDR[35:32]"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 0.--3. "APQOS_3_0,Append QoS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xD40564++0x03
line.long 0x00 "IMERRSIDRRESP__HC,This register indicates the Error SrcID when EDC error happen in AXI R(response) channel"
bitfld.long 0x00 31. "CLR," "0,1"
newline
hexmask.long.tbyte 0x00 8.--30. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "SRCID_7_0,Read : SrcID of error transaction"
group.long 0xD40568++0x03
line.long 0x00 "IMERRSIDPA__HC,This register indicates the Error SrcID when EDC error happen in APB address channel"
bitfld.long 0x00 31. "CLR," "0,1"
newline
hexmask.long.tbyte 0x00 8.--30. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "SRCID_7_0,Read : SrcID of error transaction"
group.long 0xD4056C++0x03
line.long 0x00 "IMERRSIDPWD__HC,This register indicates the Error SrcID when EDC error happen in APB write data channel"
bitfld.long 0x00 31. "CLR," "0,1"
newline
hexmask.long.tbyte 0x00 8.--30. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "SRCID_7_0,Read : SrcID of error transaction"
group.long 0xD40570++0x03
line.long 0x00 "IMRGID__HC,Region-ID setting will be available for each IPMMU-hier (each bus hierarchy)"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 0.--3. "RGID_3_0,Region-ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xD40574++0x03
line.long 0x00 "IMRGIDEN__HC,This register is used for setting to protect IMRGID register"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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hexmask.long.word 0x00 0.--15. 1. "RGIDEN_15_0,When RGIDEN[PUSER[5:2]]=1 IMRGID[3:0] register can be accessed"
group.long 0xD40578++0x03
line.long 0x00 "IMSECGRP__HC,This register is used for setting to protect IMRGID register"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 0. "SECGRP,When PUSER[1]=0 if SECGRP=1 RGID register can be accessed" "0,1"
group.long 0xD41500++0x03
line.long 0x00 "IMSCTLR__HC,This register controls the behavior of IPMMU function"
bitfld.long 0x00 31. "DISWPROT,Read and Write protection of MMU System Control Register and MMU auxiliary Control register" "0: can write IMSCTLR.NSACCEN & IMSCTLR.USE_SECGRP,1: can write/read IMSCTLR.NSACCEN &"
newline
bitfld.long 0x00 30. "NSACCEN,Non-secure access enable for MMU System Control Register and MMU auxiliary Control register" "0: disable non-secure access (default),1: enable non-secure access"
newline
bitfld.long 0x00 29. "DISMMU,Disable IPMMU cache" "0: enable IPMMU cache This bit can be set except,1: disable IPMMU cache"
newline
bitfld.long 0x00 28. "USE_SECGRP,Use security group to judge Secure/Non-secure access Set this bit in IPMMU-DS0 and IPMMU-RT1 0 before using this function" "0,1"
newline
hexmask.long 0x00 0.--27. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0xD41554++0x03
line.long 0x00 "ISERRINJR__HC,IPMMU cache"
hexmask.long 0x00 7.--31. 1. "Reserved_7,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 6. "ERRINJ_EDCERR_PWD,Error injection bit for EDC error in APB write datta channel" "0: Clear error injection,1: Enable error injection"
newline
bitfld.long 0x00 5. "ERRINJ_EDCERR_PA,Error injection bit for EDC error in APB address channel" "0: Clear error injection,1: Enable error injection"
newline
bitfld.long 0x00 4. "ERRINJ_EDCERR_RRESP,Error injection bit for EDC error in AXI R response channel" "0: Clear error injection,1: Enable error injection"
newline
bitfld.long 0x00 3. "ERRINJ_EDCERR_NPTW_AR,Error injection bit for EDC error in AXI AR channel (during not Page Table Walk)" "0: Clear error injection,1: Enable error injection"
newline
bitfld.long 0x00 2. "ERRINJ_COMPFAIL,Error injection bit for DCLS error" "0: Clear error injection,1: Enable error injection"
newline
bitfld.long 0x00 1. "ERRINJ_EDCERR_R,Error injection bit for EDC error in AXI R channel" "0: Clear error injection,1: Enable error injection"
newline
bitfld.long 0x00 0. "ERRINJ_EDCERR_AR,Error injection bit for EDC error in AXI AR channel" "0: Clear error injection,1: Enable error injection"
group.long 0xD41580++0x03
line.long 0x00 "IMPFMCTR__HC,"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 12.--13. "MD_1_0,Monitor Mode IPMMU (cache)" "0: Monitor all MMUs,1: Reserved,2: Reserved,3: Monitor only MMUn (specified"
newline
bitfld.long 0x00 8.--11. "SEL_3_0,When MD is B'11 SEL indicates the MMU table number to be monitored" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 2.--7. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 1. "RST,Reset all status and counter values" "0,1"
newline
bitfld.long 0x00 0. "EN,Performance Monitor Enable" "0: Stop to count,1: Start to count All counters stop when"
group.long 0xD41590++0x03
line.long 0x00 "IMPFMTOTAL__HC,"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "TOTAL_23_0,The total number of translation requests"
group.long 0xD41594++0x03
line.long 0x00 "IMPFMHIT__HC,"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "HIT_23_0,The total number of TLB hit requests"
group.long 0xD41598++0x03
line.long 0x00 "IMPFMMISS__HC,"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "MISS_23_0,The total number of miss requests"
group.long 0xD42200++0x03
line.long 0x00 "IMPCTR__HC,This register controls the behavior of the PMB function"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--7. "TTSEL_3_0,Translation Table Select Indicates the table number (MMU0  MMU15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 3. "TTEN,TLB Translation Enable" "0: Output PPN as a physical address,1: Output PPN as an intermediate physical address"
newline
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error..,1: Assert an interrupt when an error occurred"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 0. "PMBEN,PMB Enable" "0: PMB disabled,1: PMB enabled"
group.long 0xD42208++0x03
line.long 0x00 "IMPSTR__HC,This register indicates the error status of the address translation by PMB"
hexmask.long 0x00 5.--31. 1. "Reserved_5,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4. "MHIT,Multiple hit Indicate that multiple PMB hits occurred" "0,1"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "TF,Translation Fault This bit is set to 1 when a translation fault occurred during a PMB translation" "0,1"
group.long 0xD4220C++0x03
line.long 0x00 "IMPEAR__HC,This register indicates the address which an address translation error occurred"
hexmask.long 0x00 0.--31. 1. "EAR_31_0,The faulting virtual address is set when an address translation error occurred"
group.long 0xD42280++0x03
line.long 0x00 "IMPMBA0__HC,Note: n= 0 to 15 This register is used for setting the virtual page number"
hexmask.long.byte 0x00 24.--31. 1. "VPN_31_24,Virtual Page Number For 16-Mbyte page VPN[31:24] is used"
newline
hexmask.long.word 0x00 9.--23. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0xD42284++0x03
line.long 0x00 "IMPMBA1__HC,Note: n= 0 to 15 This register is used for setting the virtual page number"
hexmask.long.byte 0x00 24.--31. 1. "VPN_31_24,Virtual Page Number For 16-Mbyte page VPN[31:24] is used"
newline
hexmask.long.word 0x00 9.--23. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0xD42288++0x03
line.long 0x00 "IMPMBA2__HC,Note: n= 0 to 15 This register is used for setting the virtual page number"
hexmask.long.byte 0x00 24.--31. 1. "VPN_31_24,Virtual Page Number For 16-Mbyte page VPN[31:24] is used"
newline
hexmask.long.word 0x00 9.--23. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0xD4228C++0x03
line.long 0x00 "IMPMBA3__HC,Note: n= 0 to 15 This register is used for setting the virtual page number"
hexmask.long.byte 0x00 24.--31. 1. "VPN_31_24,Virtual Page Number For 16-Mbyte page VPN[31:24] is used"
newline
hexmask.long.word 0x00 9.--23. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0xD42290++0x03
line.long 0x00 "IMPMBA4__HC,Note: n= 0 to 15 This register is used for setting the virtual page number"
hexmask.long.byte 0x00 24.--31. 1. "VPN_31_24,Virtual Page Number For 16-Mbyte page VPN[31:24] is used"
newline
hexmask.long.word 0x00 9.--23. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0xD42294++0x03
line.long 0x00 "IMPMBA5__HC,Note: n= 0 to 15 This register is used for setting the virtual page number"
hexmask.long.byte 0x00 24.--31. 1. "VPN_31_24,Virtual Page Number For 16-Mbyte page VPN[31:24] is used"
newline
hexmask.long.word 0x00 9.--23. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0xD42298++0x03
line.long 0x00 "IMPMBA6__HC,Note: n= 0 to 15 This register is used for setting the virtual page number"
hexmask.long.byte 0x00 24.--31. 1. "VPN_31_24,Virtual Page Number For 16-Mbyte page VPN[31:24] is used"
newline
hexmask.long.word 0x00 9.--23. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0xD4229C++0x03
line.long 0x00 "IMPMBA7__HC,Note: n= 0 to 15 This register is used for setting the virtual page number"
hexmask.long.byte 0x00 24.--31. 1. "VPN_31_24,Virtual Page Number For 16-Mbyte page VPN[31:24] is used"
newline
hexmask.long.word 0x00 9.--23. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0xD422A0++0x03
line.long 0x00 "IMPMBA8__HC,Note: n= 0 to 15 This register is used for setting the virtual page number"
hexmask.long.byte 0x00 24.--31. 1. "VPN_31_24,Virtual Page Number For 16-Mbyte page VPN[31:24] is used"
newline
hexmask.long.word 0x00 9.--23. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0xD422A4++0x03
line.long 0x00 "IMPMBA9__HC,Note: n= 0 to 15 This register is used for setting the virtual page number"
hexmask.long.byte 0x00 24.--31. 1. "VPN_31_24,Virtual Page Number For 16-Mbyte page VPN[31:24] is used"
newline
hexmask.long.word 0x00 9.--23. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0xD422A8++0x03
line.long 0x00 "IMPMBA10__HC,Note: n= 0 to 15 This register is used for setting the virtual page number"
hexmask.long.byte 0x00 24.--31. 1. "VPN_31_24,Virtual Page Number For 16-Mbyte page VPN[31:24] is used"
newline
hexmask.long.word 0x00 9.--23. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0xD422AC++0x03
line.long 0x00 "IMPMBA11__HC,Note: n= 0 to 15 This register is used for setting the virtual page number"
hexmask.long.byte 0x00 24.--31. 1. "VPN_31_24,Virtual Page Number For 16-Mbyte page VPN[31:24] is used"
newline
hexmask.long.word 0x00 9.--23. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0xD422B0++0x03
line.long 0x00 "IMPMBA12__HC,Note: n= 0 to 15 This register is used for setting the virtual page number"
hexmask.long.byte 0x00 24.--31. 1. "VPN_31_24,Virtual Page Number For 16-Mbyte page VPN[31:24] is used"
newline
hexmask.long.word 0x00 9.--23. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0xD422B4++0x03
line.long 0x00 "IMPMBA13__HC,Note: n= 0 to 15 This register is used for setting the virtual page number"
hexmask.long.byte 0x00 24.--31. 1. "VPN_31_24,Virtual Page Number For 16-Mbyte page VPN[31:24] is used"
newline
hexmask.long.word 0x00 9.--23. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0xD422B8++0x03
line.long 0x00 "IMPMBA14__HC,Note: n= 0 to 15 This register is used for setting the virtual page number"
hexmask.long.byte 0x00 24.--31. 1. "VPN_31_24,Virtual Page Number For 16-Mbyte page VPN[31:24] is used"
newline
hexmask.long.word 0x00 9.--23. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
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hexmask.long.byte 0x00 0.--7. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0xD422BC++0x03
line.long 0x00 "IMPMBA15__HC,Note: n= 0 to 15 This register is used for setting the virtual page number"
hexmask.long.byte 0x00 24.--31. 1. "VPN_31_24,Virtual Page Number For 16-Mbyte page VPN[31:24] is used"
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hexmask.long.word 0x00 9.--23. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
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hexmask.long.byte 0x00 0.--7. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0xD422C0++0x03
line.long 0x00 "IMPMBD0__HC,Note: n= 0 to 15 This register is used for setting the physical page number and the memory size which PMB managed"
hexmask.long.byte 0x00 24.--31. 1. "PPN_31_24,Physical Page Number For 16-Mbyte page PPN[31:24] is used"
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hexmask.long.byte 0x00 16.--23. 1. "PPN_39_32,Upper Physical Page Number"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
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bitfld.long 0x00 7. "SZ_1,This bit and SZ[0] (bit 4) specify the page size" "0: 16-Mbyte page,1: 64-Mbyte page"
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rbitfld.long 0x00 5.--6. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 4. "SZ_0,Page Size See the description of SZ[1] (bit 7)" "0,1"
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bitfld.long 0x00 3. "C,Cache bit When this bit is set the request after address translation can be treated as cacheable request" "0,1"
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rbitfld.long 0x00 0.--2. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
group.long 0xD422C4++0x03
line.long 0x00 "IMPMBD1__HC,Note: n= 0 to 15 This register is used for setting the physical page number and the memory size which PMB managed"
hexmask.long.byte 0x00 24.--31. 1. "PPN_31_24,Physical Page Number For 16-Mbyte page PPN[31:24] is used"
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hexmask.long.byte 0x00 16.--23. 1. "PPN_39_32,Upper Physical Page Number"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
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bitfld.long 0x00 7. "SZ_1,This bit and SZ[0] (bit 4) specify the page size" "0: 16-Mbyte page,1: 64-Mbyte page"
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rbitfld.long 0x00 5.--6. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 4. "SZ_0,Page Size See the description of SZ[1] (bit 7)" "0,1"
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bitfld.long 0x00 3. "C,Cache bit When this bit is set the request after address translation can be treated as cacheable request" "0,1"
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rbitfld.long 0x00 0.--2. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
group.long 0xD422C8++0x03
line.long 0x00 "IMPMBD2__HC,Note: n= 0 to 15 This register is used for setting the physical page number and the memory size which PMB managed"
hexmask.long.byte 0x00 24.--31. 1. "PPN_31_24,Physical Page Number For 16-Mbyte page PPN[31:24] is used"
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hexmask.long.byte 0x00 16.--23. 1. "PPN_39_32,Upper Physical Page Number"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
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bitfld.long 0x00 7. "SZ_1,This bit and SZ[0] (bit 4) specify the page size" "0: 16-Mbyte page,1: 64-Mbyte page"
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rbitfld.long 0x00 5.--6. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 4. "SZ_0,Page Size See the description of SZ[1] (bit 7)" "0,1"
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bitfld.long 0x00 3. "C,Cache bit When this bit is set the request after address translation can be treated as cacheable request" "0,1"
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rbitfld.long 0x00 0.--2. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
group.long 0xD422CC++0x03
line.long 0x00 "IMPMBD3__HC,Note: n= 0 to 15 This register is used for setting the physical page number and the memory size which PMB managed"
hexmask.long.byte 0x00 24.--31. 1. "PPN_31_24,Physical Page Number For 16-Mbyte page PPN[31:24] is used"
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hexmask.long.byte 0x00 16.--23. 1. "PPN_39_32,Upper Physical Page Number"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
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bitfld.long 0x00 7. "SZ_1,This bit and SZ[0] (bit 4) specify the page size" "0: 16-Mbyte page,1: 64-Mbyte page"
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rbitfld.long 0x00 5.--6. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 4. "SZ_0,Page Size See the description of SZ[1] (bit 7)" "0,1"
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bitfld.long 0x00 3. "C,Cache bit When this bit is set the request after address translation can be treated as cacheable request" "0,1"
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rbitfld.long 0x00 0.--2. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
group.long 0xD422D0++0x03
line.long 0x00 "IMPMBD4__HC,Note: n= 0 to 15 This register is used for setting the physical page number and the memory size which PMB managed"
hexmask.long.byte 0x00 24.--31. 1. "PPN_31_24,Physical Page Number For 16-Mbyte page PPN[31:24] is used"
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hexmask.long.byte 0x00 16.--23. 1. "PPN_39_32,Upper Physical Page Number"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
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bitfld.long 0x00 7. "SZ_1,This bit and SZ[0] (bit 4) specify the page size" "0: 16-Mbyte page,1: 64-Mbyte page"
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rbitfld.long 0x00 5.--6. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 4. "SZ_0,Page Size See the description of SZ[1] (bit 7)" "0,1"
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bitfld.long 0x00 3. "C,Cache bit When this bit is set the request after address translation can be treated as cacheable request" "0,1"
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rbitfld.long 0x00 0.--2. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
group.long 0xD422D4++0x03
line.long 0x00 "IMPMBD5__HC,Note: n= 0 to 15 This register is used for setting the physical page number and the memory size which PMB managed"
hexmask.long.byte 0x00 24.--31. 1. "PPN_31_24,Physical Page Number For 16-Mbyte page PPN[31:24] is used"
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hexmask.long.byte 0x00 16.--23. 1. "PPN_39_32,Upper Physical Page Number"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
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bitfld.long 0x00 7. "SZ_1,This bit and SZ[0] (bit 4) specify the page size" "0: 16-Mbyte page,1: 64-Mbyte page"
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rbitfld.long 0x00 5.--6. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 4. "SZ_0,Page Size See the description of SZ[1] (bit 7)" "0,1"
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bitfld.long 0x00 3. "C,Cache bit When this bit is set the request after address translation can be treated as cacheable request" "0,1"
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rbitfld.long 0x00 0.--2. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
group.long 0xD422D8++0x03
line.long 0x00 "IMPMBD6__HC,Note: n= 0 to 15 This register is used for setting the physical page number and the memory size which PMB managed"
hexmask.long.byte 0x00 24.--31. 1. "PPN_31_24,Physical Page Number For 16-Mbyte page PPN[31:24] is used"
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hexmask.long.byte 0x00 16.--23. 1. "PPN_39_32,Upper Physical Page Number"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
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bitfld.long 0x00 7. "SZ_1,This bit and SZ[0] (bit 4) specify the page size" "0: 16-Mbyte page,1: 64-Mbyte page"
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rbitfld.long 0x00 5.--6. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 4. "SZ_0,Page Size See the description of SZ[1] (bit 7)" "0,1"
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bitfld.long 0x00 3. "C,Cache bit When this bit is set the request after address translation can be treated as cacheable request" "0,1"
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rbitfld.long 0x00 0.--2. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
group.long 0xD422DC++0x03
line.long 0x00 "IMPMBD7__HC,Note: n= 0 to 15 This register is used for setting the physical page number and the memory size which PMB managed"
hexmask.long.byte 0x00 24.--31. 1. "PPN_31_24,Physical Page Number For 16-Mbyte page PPN[31:24] is used"
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hexmask.long.byte 0x00 16.--23. 1. "PPN_39_32,Upper Physical Page Number"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
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bitfld.long 0x00 7. "SZ_1,This bit and SZ[0] (bit 4) specify the page size" "0: 16-Mbyte page,1: 64-Mbyte page"
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rbitfld.long 0x00 5.--6. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 4. "SZ_0,Page Size See the description of SZ[1] (bit 7)" "0,1"
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bitfld.long 0x00 3. "C,Cache bit When this bit is set the request after address translation can be treated as cacheable request" "0,1"
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rbitfld.long 0x00 0.--2. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
group.long 0xD422E0++0x03
line.long 0x00 "IMPMBD8__HC,Note: n= 0 to 15 This register is used for setting the physical page number and the memory size which PMB managed"
hexmask.long.byte 0x00 24.--31. 1. "PPN_31_24,Physical Page Number For 16-Mbyte page PPN[31:24] is used"
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hexmask.long.byte 0x00 16.--23. 1. "PPN_39_32,Upper Physical Page Number"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
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bitfld.long 0x00 7. "SZ_1,This bit and SZ[0] (bit 4) specify the page size" "0: 16-Mbyte page,1: 64-Mbyte page"
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rbitfld.long 0x00 5.--6. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 4. "SZ_0,Page Size See the description of SZ[1] (bit 7)" "0,1"
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bitfld.long 0x00 3. "C,Cache bit When this bit is set the request after address translation can be treated as cacheable request" "0,1"
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rbitfld.long 0x00 0.--2. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
group.long 0xD422E4++0x03
line.long 0x00 "IMPMBD9__HC,Note: n= 0 to 15 This register is used for setting the physical page number and the memory size which PMB managed"
hexmask.long.byte 0x00 24.--31. 1. "PPN_31_24,Physical Page Number For 16-Mbyte page PPN[31:24] is used"
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hexmask.long.byte 0x00 16.--23. 1. "PPN_39_32,Upper Physical Page Number"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
bitfld.long 0x00 7. "SZ_1,This bit and SZ[0] (bit 4) specify the page size" "0: 16-Mbyte page,1: 64-Mbyte page"
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rbitfld.long 0x00 5.--6. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 4. "SZ_0,Page Size See the description of SZ[1] (bit 7)" "0,1"
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bitfld.long 0x00 3. "C,Cache bit When this bit is set the request after address translation can be treated as cacheable request" "0,1"
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rbitfld.long 0x00 0.--2. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
group.long 0xD422E8++0x03
line.long 0x00 "IMPMBD10__HC,Note: n= 0 to 15 This register is used for setting the physical page number and the memory size which PMB managed"
hexmask.long.byte 0x00 24.--31. 1. "PPN_31_24,Physical Page Number For 16-Mbyte page PPN[31:24] is used"
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hexmask.long.byte 0x00 16.--23. 1. "PPN_39_32,Upper Physical Page Number"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
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bitfld.long 0x00 7. "SZ_1,This bit and SZ[0] (bit 4) specify the page size" "0: 16-Mbyte page,1: 64-Mbyte page"
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rbitfld.long 0x00 5.--6. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 4. "SZ_0,Page Size See the description of SZ[1] (bit 7)" "0,1"
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bitfld.long 0x00 3. "C,Cache bit When this bit is set the request after address translation can be treated as cacheable request" "0,1"
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rbitfld.long 0x00 0.--2. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
group.long 0xD422EC++0x03
line.long 0x00 "IMPMBD11__HC,Note: n= 0 to 15 This register is used for setting the physical page number and the memory size which PMB managed"
hexmask.long.byte 0x00 24.--31. 1. "PPN_31_24,Physical Page Number For 16-Mbyte page PPN[31:24] is used"
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hexmask.long.byte 0x00 16.--23. 1. "PPN_39_32,Upper Physical Page Number"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
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bitfld.long 0x00 7. "SZ_1,This bit and SZ[0] (bit 4) specify the page size" "0: 16-Mbyte page,1: 64-Mbyte page"
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rbitfld.long 0x00 5.--6. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 4. "SZ_0,Page Size See the description of SZ[1] (bit 7)" "0,1"
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bitfld.long 0x00 3. "C,Cache bit When this bit is set the request after address translation can be treated as cacheable request" "0,1"
newline
rbitfld.long 0x00 0.--2. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
group.long 0xD422F0++0x03
line.long 0x00 "IMPMBD12__HC,Note: n= 0 to 15 This register is used for setting the physical page number and the memory size which PMB managed"
hexmask.long.byte 0x00 24.--31. 1. "PPN_31_24,Physical Page Number For 16-Mbyte page PPN[31:24] is used"
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hexmask.long.byte 0x00 16.--23. 1. "PPN_39_32,Upper Physical Page Number"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
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bitfld.long 0x00 7. "SZ_1,This bit and SZ[0] (bit 4) specify the page size" "0: 16-Mbyte page,1: 64-Mbyte page"
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rbitfld.long 0x00 5.--6. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 4. "SZ_0,Page Size See the description of SZ[1] (bit 7)" "0,1"
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bitfld.long 0x00 3. "C,Cache bit When this bit is set the request after address translation can be treated as cacheable request" "0,1"
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rbitfld.long 0x00 0.--2. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
group.long 0xD422F4++0x03
line.long 0x00 "IMPMBD13__HC,Note: n= 0 to 15 This register is used for setting the physical page number and the memory size which PMB managed"
hexmask.long.byte 0x00 24.--31. 1. "PPN_31_24,Physical Page Number For 16-Mbyte page PPN[31:24] is used"
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hexmask.long.byte 0x00 16.--23. 1. "PPN_39_32,Upper Physical Page Number"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
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bitfld.long 0x00 7. "SZ_1,This bit and SZ[0] (bit 4) specify the page size" "0: 16-Mbyte page,1: 64-Mbyte page"
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rbitfld.long 0x00 5.--6. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 4. "SZ_0,Page Size See the description of SZ[1] (bit 7)" "0,1"
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bitfld.long 0x00 3. "C,Cache bit When this bit is set the request after address translation can be treated as cacheable request" "0,1"
newline
rbitfld.long 0x00 0.--2. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
group.long 0xD422F8++0x03
line.long 0x00 "IMPMBD14__HC,Note: n= 0 to 15 This register is used for setting the physical page number and the memory size which PMB managed"
hexmask.long.byte 0x00 24.--31. 1. "PPN_31_24,Physical Page Number For 16-Mbyte page PPN[31:24] is used"
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hexmask.long.byte 0x00 16.--23. 1. "PPN_39_32,Upper Physical Page Number"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
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bitfld.long 0x00 7. "SZ_1,This bit and SZ[0] (bit 4) specify the page size" "0: 16-Mbyte page,1: 64-Mbyte page"
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rbitfld.long 0x00 5.--6. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 4. "SZ_0,Page Size See the description of SZ[1] (bit 7)" "0,1"
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bitfld.long 0x00 3. "C,Cache bit When this bit is set the request after address translation can be treated as cacheable request" "0,1"
newline
rbitfld.long 0x00 0.--2. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
group.long 0xD422FC++0x03
line.long 0x00 "IMPMBD15__HC,Note: n= 0 to 15 This register is used for setting the physical page number and the memory size which PMB managed"
hexmask.long.byte 0x00 24.--31. 1. "PPN_31_24,Physical Page Number For 16-Mbyte page PPN[31:24] is used"
newline
hexmask.long.byte 0x00 16.--23. 1. "PPN_39_32,Upper Physical Page Number"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 8. "V,Enable this page translation" "0,1"
newline
bitfld.long 0x00 7. "SZ_1,This bit and SZ[0] (bit 4) specify the page size" "0: 16-Mbyte page,1: 64-Mbyte page"
newline
rbitfld.long 0x00 5.--6. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 4. "SZ_0,Page Size See the description of SZ[1] (bit 7)" "0,1"
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bitfld.long 0x00 3. "C,Cache bit When this bit is set the request after address translation can be treated as cacheable request" "0,1"
newline
rbitfld.long 0x00 0.--2. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
group.long 0xD43300++0x03
line.long 0x00 "IMUCTR0__HC,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
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hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD43308++0x03
line.long 0x00 "IMUASID0__HC,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD43310++0x03
line.long 0x00 "IMUCTR1__HC,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
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hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD43318++0x03
line.long 0x00 "IMUASID1__HC,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD43320++0x03
line.long 0x00 "IMUCTR2__HC,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
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hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD43328++0x03
line.long 0x00 "IMUASID2__HC,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD43330++0x03
line.long 0x00 "IMUCTR3__HC,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
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hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD43338++0x03
line.long 0x00 "IMUASID3__HC,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD43340++0x03
line.long 0x00 "IMUCTR4__HC,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
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hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD43348++0x03
line.long 0x00 "IMUASID4__HC,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD43350++0x03
line.long 0x00 "IMUCTR5__HC,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
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hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD43358++0x03
line.long 0x00 "IMUASID5__HC,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD43360++0x03
line.long 0x00 "IMUCTR6__HC,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD43368++0x03
line.long 0x00 "IMUASID6__HC,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD43370++0x03
line.long 0x00 "IMUCTR7__HC,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD43378++0x03
line.long 0x00 "IMUASID7__HC,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD43380++0x03
line.long 0x00 "IMUCTR8__HC,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD43388++0x03
line.long 0x00 "IMUASID8__HC,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD43390++0x03
line.long 0x00 "IMUCTR9__HC,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD43398++0x03
line.long 0x00 "IMUASID9__HC,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD433A0++0x03
line.long 0x00 "IMUCTR10__HC,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD433A8++0x03
line.long 0x00 "IMUASID10__HC,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD433B0++0x03
line.long 0x00 "IMUCTR11__HC,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD433B8++0x03
line.long 0x00 "IMUASID11__HC,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD433C0++0x03
line.long 0x00 "IMUCTR12__HC,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD433C8++0x03
line.long 0x00 "IMUASID12__HC,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD433D0++0x03
line.long 0x00 "IMUCTR13__HC,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD433D8++0x03
line.long 0x00 "IMUASID13__HC,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD433E0++0x03
line.long 0x00 "IMUCTR14__HC,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
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hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
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rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD433E8++0x03
line.long 0x00 "IMUASID14__HC,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD433F0++0x03
line.long 0x00 "IMUCTR15__HC,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
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hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
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rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD433F8++0x03
line.long 0x00 "IMUASID15__HC,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD43400++0x03
line.long 0x00 "IMUCTR16__HC,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
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hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
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rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD43408++0x03
line.long 0x00 "IMUASID16__HC,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD43410++0x03
line.long 0x00 "IMUCTR17__HC,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
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hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD43418++0x03
line.long 0x00 "IMUASID17__HC,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD43420++0x03
line.long 0x00 "IMUCTR18__HC,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
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hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD43428++0x03
line.long 0x00 "IMUASID18__HC,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD43430++0x03
line.long 0x00 "IMUCTR19__HC,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD43438++0x03
line.long 0x00 "IMUASID19__HC,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD43440++0x03
line.long 0x00 "IMUCTR20__HC,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD43448++0x03
line.long 0x00 "IMUASID20__HC,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD43450++0x03
line.long 0x00 "IMUCTR21__HC,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD43458++0x03
line.long 0x00 "IMUASID21__HC,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD43460++0x03
line.long 0x00 "IMUCTR22__HC,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD43468++0x03
line.long 0x00 "IMUASID22__HC,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD43470++0x03
line.long 0x00 "IMUCTR23__HC,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD43478++0x03
line.long 0x00 "IMUASID23__HC,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD43480++0x03
line.long 0x00 "IMUCTR24__HC,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD43488++0x03
line.long 0x00 "IMUASID24__HC,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD43490++0x03
line.long 0x00 "IMUCTR25__HC,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD43498++0x03
line.long 0x00 "IMUASID25__HC,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD434A0++0x03
line.long 0x00 "IMUCTR26__HC,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
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rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD434A8++0x03
line.long 0x00 "IMUASID26__HC,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD434B0++0x03
line.long 0x00 "IMUCTR27__HC,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
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hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
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rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD434B8++0x03
line.long 0x00 "IMUASID27__HC,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD434C0++0x03
line.long 0x00 "IMUCTR28__HC,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
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hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
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rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD434C8++0x03
line.long 0x00 "IMUASID28__HC,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD434D0++0x03
line.long 0x00 "IMUCTR29__HC,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
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hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD434D8++0x03
line.long 0x00 "IMUASID29__HC,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD434E0++0x03
line.long 0x00 "IMUCTR30__HC,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
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hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD434E8++0x03
line.long 0x00 "IMUASID30__HC,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD434F0++0x03
line.long 0x00 "IMUCTR31__HC,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
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hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD434F8++0x03
line.long 0x00 "IMUASID31__HC,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD43600++0x03
line.long 0x00 "IMUCTR32__HC,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
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hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD43608++0x03
line.long 0x00 "IMUASID32__HC,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
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hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD43610++0x03
line.long 0x00 "IMUCTR33__HC,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD43618++0x03
line.long 0x00 "IMUASID33__HC,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD43620++0x03
line.long 0x00 "IMUCTR34__HC,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD43628++0x03
line.long 0x00 "IMUASID34__HC,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD43630++0x03
line.long 0x00 "IMUCTR35__HC,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD43638++0x03
line.long 0x00 "IMUASID35__HC,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD43640++0x03
line.long 0x00 "IMUCTR36__HC,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD43648++0x03
line.long 0x00 "IMUASID36__HC,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD43650++0x03
line.long 0x00 "IMUCTR37__HC,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD43658++0x03
line.long 0x00 "IMUASID37__HC,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD43660++0x03
line.long 0x00 "IMUCTR38__HC,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD43668++0x03
line.long 0x00 "IMUASID38__HC,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD43670++0x03
line.long 0x00 "IMUCTR39__HC,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD43678++0x03
line.long 0x00 "IMUASID39__HC,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD43680++0x03
line.long 0x00 "IMUCTR40__HC,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD43688++0x03
line.long 0x00 "IMUASID40__HC,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD43690++0x03
line.long 0x00 "IMUCTR41__HC,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD43698++0x03
line.long 0x00 "IMUASID41__HC,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD436A0++0x03
line.long 0x00 "IMUCTR42__HC,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD436A8++0x03
line.long 0x00 "IMUASID42__HC,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD436B0++0x03
line.long 0x00 "IMUCTR43__HC,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD436B8++0x03
line.long 0x00 "IMUASID43__HC,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD436C0++0x03
line.long 0x00 "IMUCTR44__HC,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD436C8++0x03
line.long 0x00 "IMUASID44__HC,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD436D0++0x03
line.long 0x00 "IMUCTR45__HC,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD436D8++0x03
line.long 0x00 "IMUASID45__HC,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD436E0++0x03
line.long 0x00 "IMUCTR46__HC,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD436E8++0x03
line.long 0x00 "IMUASID46__HC,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD436F0++0x03
line.long 0x00 "IMUCTR47__HC,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD436F8++0x03
line.long 0x00 "IMUASID47__HC,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD43700++0x03
line.long 0x00 "IMUCTR48__HC,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD43708++0x03
line.long 0x00 "IMUASID48__HC,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD43710++0x03
line.long 0x00 "IMUCTR49__HC,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD43718++0x03
line.long 0x00 "IMUASID49__HC,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD43720++0x03
line.long 0x00 "IMUCTR50__HC,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD43728++0x03
line.long 0x00 "IMUASID50__HC,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD43730++0x03
line.long 0x00 "IMUCTR51__HC,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD43738++0x03
line.long 0x00 "IMUASID51__HC,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD43740++0x03
line.long 0x00 "IMUCTR52__HC,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
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hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD43748++0x03
line.long 0x00 "IMUASID52__HC,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD43750++0x03
line.long 0x00 "IMUCTR53__HC,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
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hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD43758++0x03
line.long 0x00 "IMUASID53__HC,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD43760++0x03
line.long 0x00 "IMUCTR54__HC,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
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hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD43768++0x03
line.long 0x00 "IMUASID54__HC,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD43770++0x03
line.long 0x00 "IMUCTR55__HC,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD43778++0x03
line.long 0x00 "IMUASID55__HC,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD43780++0x03
line.long 0x00 "IMUCTR56__HC,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD43788++0x03
line.long 0x00 "IMUASID56__HC,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD43790++0x03
line.long 0x00 "IMUCTR57__HC,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD43798++0x03
line.long 0x00 "IMUASID57__HC,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD437A0++0x03
line.long 0x00 "IMUCTR58__HC,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD437A8++0x03
line.long 0x00 "IMUASID58__HC,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD437B0++0x03
line.long 0x00 "IMUCTR59__HC,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD437B8++0x03
line.long 0x00 "IMUASID59__HC,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD437C0++0x03
line.long 0x00 "IMUCTR60__HC,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD437C8++0x03
line.long 0x00 "IMUASID60__HC,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD437D0++0x03
line.long 0x00 "IMUCTR61__HC,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD437D8++0x03
line.long 0x00 "IMUASID61__HC,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD437E0++0x03
line.long 0x00 "IMUCTR62__HC,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD437E8++0x03
line.long 0x00 "IMUASID62__HC,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD437F0++0x03
line.long 0x00 "IMUCTR63__HC,Note: m= 0 to 63 This register controls the behavior of each uTLB"
bitfld.long 0x00 31. "FIXADDEN,Fix the upper 8 bits of physical address Always output the upper 8 bits of physical address as FIXADD[39:32]" "0: Disable FIXADD[39:32],1: Enable FIXADD[39:32] IMUCTRn.FIXADD[39:32]"
newline
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "FIXADD_39_32,When FIXADDEN is 1 the upper 8bit of physical address is FIXADD[39:32]"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 4.--8. "TTSEL_4_0,Translation Table 00000 to" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MMU0 to MMU15 (IPMMU context),16: PMB 10001 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Reserved"
newline
rbitfld.long 0x00 2.--3. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 1. "FLUSH,micro-TLB Invalidate Invalidate all entries in the micro-TLB" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,Address Translation Enable" "0: Disable address translation,1: Enable address translation"
group.long 0xD437F8++0x03
line.long 0x00 "IMUASID63__HC,Note: m= 0 to 63 This register is used for setting ASID of each uTLB"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 8.--15. 1. "ASID1_7_0,ASID1 This field indicates the ASID which the micro-TLB uses in the stage 2 translation"
newline
hexmask.long.byte 0x00 0.--7. 1. "ASID0_7_0,ASID0 This field indicates the ASID which the micro-TLB uses in the stage 1 translation"
group.long 0xD50000++0x03
line.long 0x00 "IMCTR0__HC,Note: n= 0 to 15 (IPMMU context) This register controls the behavior of the MMU"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 15. "SEC,Copy of IMSEC.SEC[n]" "0: Behave as non-secure context,1: Behave as secure context"
newline
hexmask.long.word 0x00 3.--14. 1. "Reserved_3,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error occurs,1: Assert an interrupt when an error occurs"
newline
bitfld.long 0x00 1. "FLUSH,TLB Invalidate This bit is automatically cleared to 0" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,MMU Enable" "0: MMU disabled,1: MMU enabled"
group.long 0xD50040++0x03
line.long 0x00 "IMSEC__HC,This register controls the attribute of secure/non-secure for MMU"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--15. 1. "SEC_15_0,SEC[n]=0 : IMCTRn~IMERIDn is Non-secure SEC[n]=1 : IMCTRn~IMERIDn is Secure"
group.long 0xD51040++0x03
line.long 0x00 "IMCTR1__HC,Note: n= 0 to 15 (IPMMU context) This register controls the behavior of the MMU"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 15. "SEC,Copy of IMSEC.SEC[n]" "0: Behave as non-secure context,1: Behave as secure context"
newline
hexmask.long.word 0x00 3.--14. 1. "Reserved_3,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error occurs,1: Assert an interrupt when an error occurs"
newline
bitfld.long 0x00 1. "FLUSH,TLB Invalidate This bit is automatically cleared to 0" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,MMU Enable" "0: MMU disabled,1: MMU enabled"
group.long 0xD52080++0x03
line.long 0x00 "IMCTR2__HC,Note: n= 0 to 15 (IPMMU context) This register controls the behavior of the MMU"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 15. "SEC,Copy of IMSEC.SEC[n]" "0: Behave as non-secure context,1: Behave as secure context"
newline
hexmask.long.word 0x00 3.--14. 1. "Reserved_3,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error occurs,1: Assert an interrupt when an error occurs"
newline
bitfld.long 0x00 1. "FLUSH,TLB Invalidate This bit is automatically cleared to 0" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,MMU Enable" "0: MMU disabled,1: MMU enabled"
group.long 0xD530C0++0x03
line.long 0x00 "IMCTR3__HC,Note: n= 0 to 15 (IPMMU context) This register controls the behavior of the MMU"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 15. "SEC,Copy of IMSEC.SEC[n]" "0: Behave as non-secure context,1: Behave as secure context"
newline
hexmask.long.word 0x00 3.--14. 1. "Reserved_3,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error occurs,1: Assert an interrupt when an error occurs"
newline
bitfld.long 0x00 1. "FLUSH,TLB Invalidate This bit is automatically cleared to 0" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,MMU Enable" "0: MMU disabled,1: MMU enabled"
group.long 0xD54100++0x03
line.long 0x00 "IMCTR4__HC,Note: n= 0 to 15 (IPMMU context) This register controls the behavior of the MMU"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 15. "SEC,Copy of IMSEC.SEC[n]" "0: Behave as non-secure context,1: Behave as secure context"
newline
hexmask.long.word 0x00 3.--14. 1. "Reserved_3,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error occurs,1: Assert an interrupt when an error occurs"
newline
bitfld.long 0x00 1. "FLUSH,TLB Invalidate This bit is automatically cleared to 0" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,MMU Enable" "0: MMU disabled,1: MMU enabled"
group.long 0xD55140++0x03
line.long 0x00 "IMCTR5__HC,Note: n= 0 to 15 (IPMMU context) This register controls the behavior of the MMU"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 15. "SEC,Copy of IMSEC.SEC[n]" "0: Behave as non-secure context,1: Behave as secure context"
newline
hexmask.long.word 0x00 3.--14. 1. "Reserved_3,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error occurs,1: Assert an interrupt when an error occurs"
newline
bitfld.long 0x00 1. "FLUSH,TLB Invalidate This bit is automatically cleared to 0" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,MMU Enable" "0: MMU disabled,1: MMU enabled"
group.long 0xD56180++0x03
line.long 0x00 "IMCTR6__HC,Note: n= 0 to 15 (IPMMU context) This register controls the behavior of the MMU"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 15. "SEC,Copy of IMSEC.SEC[n]" "0: Behave as non-secure context,1: Behave as secure context"
newline
hexmask.long.word 0x00 3.--14. 1. "Reserved_3,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error occurs,1: Assert an interrupt when an error occurs"
newline
bitfld.long 0x00 1. "FLUSH,TLB Invalidate This bit is automatically cleared to 0" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,MMU Enable" "0: MMU disabled,1: MMU enabled"
group.long 0xD571C0++0x03
line.long 0x00 "IMCTR7__HC,Note: n= 0 to 15 (IPMMU context) This register controls the behavior of the MMU"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 15. "SEC,Copy of IMSEC.SEC[n]" "0: Behave as non-secure context,1: Behave as secure context"
newline
hexmask.long.word 0x00 3.--14. 1. "Reserved_3,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error occurs,1: Assert an interrupt when an error occurs"
newline
bitfld.long 0x00 1. "FLUSH,TLB Invalidate This bit is automatically cleared to 0" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,MMU Enable" "0: MMU disabled,1: MMU enabled"
group.long 0xD58800++0x03
line.long 0x00 "IMCTR8__HC,Note: n= 0 to 15 (IPMMU context) This register controls the behavior of the MMU"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 15. "SEC,Copy of IMSEC.SEC[n]" "0: Behave as non-secure context,1: Behave as secure context"
newline
hexmask.long.word 0x00 3.--14. 1. "Reserved_3,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error occurs,1: Assert an interrupt when an error occurs"
newline
bitfld.long 0x00 1. "FLUSH,TLB Invalidate This bit is automatically cleared to 0" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,MMU Enable" "0: MMU disabled,1: MMU enabled"
group.long 0xD59840++0x03
line.long 0x00 "IMCTR9__HC,Note: n= 0 to 15 (IPMMU context) This register controls the behavior of the MMU"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 15. "SEC,Copy of IMSEC.SEC[n]" "0: Behave as non-secure context,1: Behave as secure context"
newline
hexmask.long.word 0x00 3.--14. 1. "Reserved_3,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error occurs,1: Assert an interrupt when an error occurs"
newline
bitfld.long 0x00 1. "FLUSH,TLB Invalidate This bit is automatically cleared to 0" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,MMU Enable" "0: MMU disabled,1: MMU enabled"
group.long 0xD5A880++0x03
line.long 0x00 "IMCTR10__HC,Note: n= 0 to 15 (IPMMU context) This register controls the behavior of the MMU"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 15. "SEC,Copy of IMSEC.SEC[n]" "0: Behave as non-secure context,1: Behave as secure context"
newline
hexmask.long.word 0x00 3.--14. 1. "Reserved_3,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error occurs,1: Assert an interrupt when an error occurs"
newline
bitfld.long 0x00 1. "FLUSH,TLB Invalidate This bit is automatically cleared to 0" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,MMU Enable" "0: MMU disabled,1: MMU enabled"
group.long 0xD5B8C0++0x03
line.long 0x00 "IMCTR11__HC,Note: n= 0 to 15 (IPMMU context) This register controls the behavior of the MMU"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 15. "SEC,Copy of IMSEC.SEC[n]" "0: Behave as non-secure context,1: Behave as secure context"
newline
hexmask.long.word 0x00 3.--14. 1. "Reserved_3,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error occurs,1: Assert an interrupt when an error occurs"
newline
bitfld.long 0x00 1. "FLUSH,TLB Invalidate This bit is automatically cleared to 0" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,MMU Enable" "0: MMU disabled,1: MMU enabled"
group.long 0xD5C900++0x03
line.long 0x00 "IMCTR12__HC,Note: n= 0 to 15 (IPMMU context) This register controls the behavior of the MMU"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 15. "SEC,Copy of IMSEC.SEC[n]" "0: Behave as non-secure context,1: Behave as secure context"
newline
hexmask.long.word 0x00 3.--14. 1. "Reserved_3,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error occurs,1: Assert an interrupt when an error occurs"
newline
bitfld.long 0x00 1. "FLUSH,TLB Invalidate This bit is automatically cleared to 0" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,MMU Enable" "0: MMU disabled,1: MMU enabled"
group.long 0xD5D940++0x03
line.long 0x00 "IMCTR13__HC,Note: n= 0 to 15 (IPMMU context) This register controls the behavior of the MMU"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 15. "SEC,Copy of IMSEC.SEC[n]" "0: Behave as non-secure context,1: Behave as secure context"
newline
hexmask.long.word 0x00 3.--14. 1. "Reserved_3,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error occurs,1: Assert an interrupt when an error occurs"
newline
bitfld.long 0x00 1. "FLUSH,TLB Invalidate This bit is automatically cleared to 0" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,MMU Enable" "0: MMU disabled,1: MMU enabled"
group.long 0xD5E980++0x03
line.long 0x00 "IMCTR14__HC,Note: n= 0 to 15 (IPMMU context) This register controls the behavior of the MMU"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 15. "SEC,Copy of IMSEC.SEC[n]" "0: Behave as non-secure context,1: Behave as secure context"
newline
hexmask.long.word 0x00 3.--14. 1. "Reserved_3,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error occurs,1: Assert an interrupt when an error occurs"
newline
bitfld.long 0x00 1. "FLUSH,TLB Invalidate This bit is automatically cleared to 0" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,MMU Enable" "0: MMU disabled,1: MMU enabled"
group.long 0xD5F9C0++0x03
line.long 0x00 "IMCTR15__HC,Note: n= 0 to 15 (IPMMU context) This register controls the behavior of the MMU"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 15. "SEC,Copy of IMSEC.SEC[n]" "0: Behave as non-secure context,1: Behave as secure context"
newline
hexmask.long.word 0x00 3.--14. 1. "Reserved_3,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error occurs,1: Assert an interrupt when an error occurs"
newline
bitfld.long 0x00 1. "FLUSH,TLB Invalidate This bit is automatically cleared to 0" "0,1"
newline
bitfld.long 0x00 0. "MMUEN,MMU Enable" "0: MMU disabled,1: MMU enabled"
tree.end
tree "IPMMU_INST_1"
base ad:0xEEFC0000
group.long 0x544++0x03
line.long 0x00 "IMQOS,This register controls the threshold which is queued in the priority requeset FIFO"
hexmask.long.word 0x00 18.--31. 1. "Reserved_18,Reserved These bits are always read as 0"
bitfld.long 0x00 16.--17. "WAITTH_1_0,Limit of wait time by interrupt from normal priority repuest" "0: 1 time,1: 4 times,2: 8 times,3: 16 times"
newline
hexmask.long.word 0x00 4.--15. 1. "Reserved_4,Reserved These bits are always read as 0"
bitfld.long 0x00 0.--3. "QOSTH_3_0,QoS threshold QoS  QOSTH : Normal priority QoS g QOSTH : High priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x548++0x03
line.long 0x00 "IMERRSIDAR,This register indicates the Error SrcID when EDC error happen in AXI AR channel"
bitfld.long 0x00 31. "CLR," "0,1"
hexmask.long.tbyte 0x00 8.--30. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "SRCID_7_0,Read : SrcID of error transaction"
group.long 0x54C++0x03
line.long 0x00 "IMERRSIDR,This register indicates the Error SrcID when EDC error happen in AXI R channel"
bitfld.long 0x00 31. "CLR," "0,1"
hexmask.long.tbyte 0x00 8.--30. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "SRCID_7_0,Read : SrcID of error transaction"
group.long 0x554++0x03
line.long 0x00 "ISERRINJ,This register controls the error injection request of each request of error function"
hexmask.long.tbyte 0x00 10.--31. 1. "Reserved_10,Reserved These bits are always read as 0"
bitfld.long 0x00 9. "ERRINJ_EDCERR_PWD,Error injection bit for EDC error in APB write data channel" "0: Clear error injection,1: Enable error injection"
newline
bitfld.long 0x00 8. "ERRINJ_EDCERR_PA,Error injection bit for EDC error in APB address channel" "0: Clear error injection,1: Enable error injection"
bitfld.long 0x00 7. "ERRINJ_EDCERR_AR2,Error injection bit for EDC error in AXI AR channel (STG~ASID)" "0: Clear error injection,1: Enable error injection"
newline
bitfld.long 0x00 6. "ERRINJ_EDCERR_RRESP,Error injection bit for EDC error in AXI R response channel" "0: Clear error injection,1: Enable error injection"
bitfld.long 0x00 5. "ERRINJ_EDC_R,Error injection bit for EDC error in AXI R channel" "0: Clear error injection,1: Enable error injection"
newline
bitfld.long 0x00 4. "ERRINJ_EDCE_AR,Error injection bit for EDC error in AXI AR channel" "0: Clear error injection,1: Enable error injection"
bitfld.long 0x00 3. "ERRINJ_COMPFAIL,Error injection bit for DCLS error" "0: Clear error injection,1: Enable error injection"
newline
bitfld.long 0x00 2. "ERRINJ_RAMERR,Error injection bit for 1-bit error in TLB-RAM" "0: Clear error injection,1: Enable error injection"
bitfld.long 0x00 1. "ERRINJ_FATALRAMERR,Error injection bit for 2-bit error in TLB-RAM" "0: Clear error injection,1: Enable error injection"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0x55C++0x03
line.long 0x00 "IMERRSIDAR2,This register indicates the Error SrcID when EDC error happen in AXI AR channel (STG~ASID)"
bitfld.long 0x00 31. "CLR," "0,1"
hexmask.long.tbyte 0x00 8.--30. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "SRCID_7_0,Read : SrcID of error transaction"
group.long 0x564++0x03
line.long 0x00 "IMERRSIDRRESP,This register indicates the Error SrcID when EDC error happen in AXI R(response) channel"
bitfld.long 0x00 31. "CLR," "0,1"
hexmask.long.tbyte 0x00 8.--30. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "SRCID_7_0,Read : SrcID of error transaction"
group.long 0x568++0x03
line.long 0x00 "IMERRSIDPA,This register indicates the Error SrcID when EDC error happen in APB address channel"
bitfld.long 0x00 31. "CLR," "0,1"
hexmask.long.tbyte 0x00 8.--30. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "SRCID_7_0,Read : SrcID of error transaction"
group.long 0x56C++0x03
line.long 0x00 "IMERRSIDPWD,This register indicates the Error SrcID when EDC error happen in APB write data channel"
bitfld.long 0x00 31. "CLR," "0,1"
hexmask.long.tbyte 0x00 8.--30. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "SRCID_7_0,Read : SrcID of error transaction"
group.long 0x5C0++0x03
line.long 0x00 "IMRAM0ERRCTR0,This register controls the assertion of the internal TLBRAM(L3) (Long Descriptor Table) error notification signal to MFIS"
bitfld.long 0x00 31. "L3UC15,L3 TLB-RAM15 EDC 2-bit error detect enable" "0: disable error detection,1: enable error detection"
bitfld.long 0x00 30. "L3C15,L3 TLB-RAM15 EDC 1-bit error detect enable" "0: disable error detection,1: enable error detection"
newline
bitfld.long 0x00 29. "L3UC14,L3 TLB-RAM14 EDC 2-bit error detect enable" "0: disable error detection,1: enable error detection"
bitfld.long 0x00 28. "L3C14,L3 TLB-RAM14 EDC 1-bit error detect enable" "0: disable error detection,1: enable error detection"
newline
bitfld.long 0x00 27. "L3UC13,L3 TLB-RAM13 EDC 2-bit error detect enable" "0: disable error detection,1: enable error detection"
bitfld.long 0x00 26. "L3C13,L3 TLB-RAM13 EDC 1-bit error detect enable" "0: disable error detection,1: enable error detection"
newline
bitfld.long 0x00 25. "L3UC12,L3 TLB-RAM12 EDC 2-bit error detect enable" "0: disable error detection,1: enable error detection"
bitfld.long 0x00 24. "L3C12,L3 TLB-RAM12 EDC 1-bit error detect enable" "0: disable error detection,1: enable error detection"
newline
bitfld.long 0x00 23. "L3UC11,L3 TLB-RAM11 EDC 2-bit error detect enable" "0: disable error detection,1: enable error detection"
bitfld.long 0x00 22. "L3C11,L3 TLB-RAM11 EDC 1-bit error detect enable" "0: disable error detection,1: enable error detection"
newline
bitfld.long 0x00 21. "L3UC10,L3 TLB-RAM10 EDC 2-bit error detect enable" "0: disable error detection,1: enable error detection"
bitfld.long 0x00 20. "L3C10,L3 TLB-RAM10 EDC 1-bit error detect enable" "0: disable error detection,1: enable error detection"
newline
bitfld.long 0x00 19. "L3UC9,L3 TLB-RAM9 EDC 2-bit error detect enable" "0: disable error detection,1: enable error detection"
bitfld.long 0x00 18. "L3C9,L3 TLB-RAM9 EDC 1-bit error detect enable" "0: disable error detection,1: enable error detection"
newline
bitfld.long 0x00 17. "L3UC8,L3 TLB-RAM8 EDC 2-bit error detect enable" "0: disable error detection,1: enable error detection"
bitfld.long 0x00 16. "L3C8,L3 TLB-RAM8 EDC 1-bit error detect enable" "0: disable error detection,1: enable error detection"
newline
bitfld.long 0x00 15. "L3UC7,L3 TLB-RAM7 EDC 2-bit error detect enable" "0: disable error detection,1: enable error detection"
bitfld.long 0x00 14. "L3C7,L3 TLB-RAM7 EDC 1-bit error detect enable" "0: disable error detection,1: enable error detection"
newline
bitfld.long 0x00 13. "L3UC6,L3 TLB-RAM6 EDC 2-bit error detect enable" "0: disable error detection,1: enable error detection"
bitfld.long 0x00 12. "L3C6,L3 TLB-RAM6 EDC 1-bit error detect enable" "0: disable error detection,1: enable error detection"
newline
bitfld.long 0x00 11. "L3UC5,L3 TLB-RAM5 EDC 2-bit error detect enable" "0: disable error detection,1: enable error detection"
bitfld.long 0x00 10. "L3C5,L3 TLB-RAM5 EDC 1-bit error detect enable" "0: disable error detection,1: enable error detection"
newline
bitfld.long 0x00 9. "L3UC4,L3 TLB-RAM4 EDC 2-bit error detect enable" "0: disable error detection,1: enable error detection"
bitfld.long 0x00 8. "L3C4,L3 TLB-RAM4 EDC 1-bit error detect enable" "0: disable error detection,1: enable error detection"
newline
bitfld.long 0x00 7. "L3UC3,L3 TLB-RAM3 EDC 2-bit error detect enable" "0: disable error detection,1: enable error detection"
bitfld.long 0x00 6. "L3C3,L3 TLB-RAM3 EDC 1-bit error detect enable" "0: disable error detection,1: enable error detection"
newline
bitfld.long 0x00 5. "L3UC2,L3 TLB-RAM2 EDC 2-bit error detect enable" "0: disable error detection,1: enable error detection"
bitfld.long 0x00 4. "L3C2,L3 TLB-RAM2 EDC 1-bit error detect enable" "0: disable error detection,1: enable error detection"
newline
bitfld.long 0x00 3. "L3UC1,L3 TLB-RAM1 EDC 2-bit error detect enable" "0: disable error detection,1: enable error detection"
bitfld.long 0x00 2. "L3C1,L3 TLB-RAM1 EDC 1-bit error detect enable" "0: disable error detection,1: enable error detection"
newline
bitfld.long 0x00 1. "L3UC0,L3 TLB-RAM0 EDC 2-bit error detect enable" "0: disable error detection,1: enable error detection"
bitfld.long 0x00 0. "L3C0,L3 TLB-RAM0 EDC 1-bit error detect enable" "0: disable error detection,1: enable error detection"
group.long 0x5C4++0x03
line.long 0x00 "IMRAM0ERRCTR1,This register controls the assertion of the internal TLBRAM(L2 L1) (Long Descriptor Table) error notification signal to MFIS"
hexmask.long.word 0x00 18.--31. 1. "Reserved_18,Reserved These bits are always read as 0"
bitfld.long 0x00 17. "L1UC,L1 TLB-RAM EDC 2-bit error detect enable" "0: disable error detection,1: enable error detection"
newline
bitfld.long 0x00 16. "L1C,L1 TLB-RAM EDC 1-biterror detect enable" "0: disable error detection,1: enable error detection"
bitfld.long 0x00 15. "L2UC7,L2 TLB-RAM7 EDC 2-bit error detect enable" "0: disable error detection,1: enable error detection"
newline
bitfld.long 0x00 14. "L2C7,L2 TLB-RAM7 EDC 1-bit error detect enable" "0: disable error detection,1: enable error detection"
bitfld.long 0x00 13. "L2UC6,L2 TLB-RAM6 EDC 2-bit error detect enable" "0: disable error detection,1: enable error detection"
newline
bitfld.long 0x00 12. "L2C6,L2 TLB-RAM6 EDC 1-bit error detect enable" "0: disable error detection,1: enable error detection"
bitfld.long 0x00 11. "L2UC5,L2 TLB-RAM5 EDC 2-bit error detect enable" "0: disable error detection,1: enable error detection"
newline
bitfld.long 0x00 10. "L2C5,L2 TLB-RAM5 EDC 1-bit error detect enable" "0: disable error detection,1: enable error detection"
bitfld.long 0x00 9. "L2UC4,L2 TLB-RAM4 EDC 2-bit error detect enable" "0: disable error detection,1: enable error detection"
newline
bitfld.long 0x00 8. "L2C4,L2 TLB-RAM4 EDC 1-bit error detect enable" "0: disable error detection,1: enable error detection"
bitfld.long 0x00 7. "L2UC3,L2 TLB-RAM3 EDC 2-bit error detect enable" "0: disable error detection,1: enable error detection"
newline
bitfld.long 0x00 6. "L2C3,L2 TLB-RAM3 EDC 1-bit error detect enable" "0: disable error detection,1: enable error detection"
bitfld.long 0x00 5. "L2UC2,L2 TLB-RAM2 EDC 2-bit error detect enable" "0: disable error detection,1: enable error detection"
newline
bitfld.long 0x00 4. "L2C2,L2 TLB-RAM2 EDC 1-bit error detect enable" "0: disable error detection,1: enable error detection"
bitfld.long 0x00 3. "L2UC1,L2 TLB-RAM1 EDC 2-bit error detect enable" "0: disable error detection,1: enable error detection"
newline
bitfld.long 0x00 2. "L2C1,L2 TLB-RAM1 EDC 1-bit error detect enable" "0: disable error detection,1: enable error detection"
bitfld.long 0x00 1. "L2UC0,L2 TLB-RAM0 EDC 2-bit error detect enable" "0: disable error detection,1: enable error detection"
newline
bitfld.long 0x00 0. "L2C0,L2 TLB-RAM0 EDC 1-bit error detect enable" "0: disable error detection,1: enable error detection"
group.long 0x5C8++0x03
line.long 0x00 "IMRAM0ERRSTR0,This register indicates the error status of the internal TLBRAM(L3) (Long Descriptor Table)"
bitfld.long 0x00 31. "L3UC15,L3 TLB-RAM15 EDC 2-bit error status" "0: no error,1: detect error"
bitfld.long 0x00 30. "L3C15,L3 TLB-RAM15 EDC 1-bit error status" "0: no error,1: detect error"
newline
bitfld.long 0x00 29. "L3UC14,L3 TLB-RAM14 EDC 2-bit error status" "0: no error,1: detect error"
bitfld.long 0x00 28. "L3C14,L3 TLB-RAM14 EDC 1-bit error status" "0: no error,1: detect error"
newline
bitfld.long 0x00 27. "L3UC13,L3 TLB-RAM13 EDC 2-bit error status" "0: no error,1: detect error"
bitfld.long 0x00 26. "L3C13,L3 TLB-RAM13 EDC 1-bit error status" "0: no error,1: detect error"
newline
bitfld.long 0x00 25. "L3UC12,L3 TLB-RAM12 EDC 2-bit error status" "0: no error,1: detect error"
bitfld.long 0x00 24. "L3C12,L3 TLB-RAM12 EDC 1-bit error status" "0: no error,1: detect error"
newline
bitfld.long 0x00 23. "L3UC11,L3 TLB-RAM11 EDC 2-bit error status" "0: no error,1: detect error"
bitfld.long 0x00 22. "L3C11,L3 TLB-RAM11 EDC 1-bit error status" "0: no error,1: detect error"
newline
bitfld.long 0x00 21. "L3UC10,L3 TLB-RAM10 EDC 2-bit error status" "0: no error,1: detect error"
bitfld.long 0x00 20. "L3C10,L3 TLB-RAM10 EDC 1-bit error status" "0: no error,1: detect error"
newline
bitfld.long 0x00 19. "L3UC9,L3 TLB-RAM9 EDC 2-bit error status" "0: no error,1: detect error"
bitfld.long 0x00 18. "L3C9,L3 TLB-RAM9 EDC 1-bit error status" "0: no error,1: detect error"
newline
bitfld.long 0x00 17. "L3UC8,L3 TLB-RAM8 EDC 2-bit error status" "0: no error,1: detect error"
bitfld.long 0x00 16. "L3C8,L3 TLB-RAM8 EDC 1-bit error status" "0: no error,1: detect error"
newline
bitfld.long 0x00 15. "L3UC7,L3 TLB-RAM7 EDC 2-bit error status" "0: no error,1: detect error"
bitfld.long 0x00 14. "L3C7,L3 TLB-RAM7 EDC 1-bit error status" "0: no error,1: detect error"
newline
bitfld.long 0x00 13. "L3UC6,L3 TLB-RAM6 EDC 2-bit error status" "0: no error,1: detect error"
bitfld.long 0x00 12. "L3C6,L3 TLB-RAM6 EDC 1-bit error status" "0: no error,1: detect error"
newline
bitfld.long 0x00 11. "L3UC5,L3 TLB-RAM5 EDC 2-bit error status" "0: no error,1: detect error"
bitfld.long 0x00 10. "L3C5,L3 TLB-RAM5 EDC 1-bit error status" "0: no error,1: detect error"
newline
bitfld.long 0x00 9. "L3UC4,L3 TLB-RAM4 EDC 2-bit error status" "0: no error,1: detect error"
bitfld.long 0x00 8. "L3C4,L3 TLB-RAM4 EDC 1-bit error status" "0: no error,1: detect error"
newline
bitfld.long 0x00 7. "L3UC3,L3 TLB-RAM3 EDC 2-bit error status" "0: no error,1: detect error"
bitfld.long 0x00 6. "L3C3,L3 TLB-RAM3 EDC 1-bit error status" "0: no error,1: detect error"
newline
bitfld.long 0x00 5. "L3UC2,L3 TLB-RAM2 EDC 2-bit error status" "0: no error,1: detect error"
bitfld.long 0x00 4. "L3C2,L3 TLB-RAM2 EDC 1-bit error status" "0: no error,1: detect error"
newline
bitfld.long 0x00 3. "L3UC1,L3 TLB-RAM1 EDC 2-bit error status" "0: no error,1: detect error"
bitfld.long 0x00 2. "L3C1,L3 TLB-RAM1 EDC 1-bit error status" "0: no error,1: detect error"
newline
bitfld.long 0x00 1. "L3UC0,L3 TLB-RAM0 EDC 2-bit error status" "0: no error,1: detect error"
bitfld.long 0x00 0. "L3C0,L3 TLB-RAM0 EDC 1-bit error status" "0: no error,1: detect error"
group.long 0x5CC++0x03
line.long 0x00 "IMRAM0ERRSTR1,This register indicates the error status of the internal TLBRAM(L2 L1) (Long Descriptor Table)"
hexmask.long.word 0x00 18.--31. 1. "Reserved_18,Reserved These bits are always read as 0"
bitfld.long 0x00 17. "L1UC,L1 TLB-RAM EDC 2-bit error status" "0: no error,1: detect error"
newline
bitfld.long 0x00 16. "L1C,L1 TLB-RAM EDC 1-bit error status" "0: no error,1: detect error"
bitfld.long 0x00 15. "L2UC7,L2 TLB-RAM7 EDC 2-bit error status" "0: no error,1: detect error"
newline
bitfld.long 0x00 14. "L2C7,L2 TLB-RAM7 EDC 1-bit error status" "0: no error,1: detect error"
bitfld.long 0x00 13. "L2UC6,L2 TLB-RAM6 EDC 2-bit error status" "0: no error,1: detect error"
newline
bitfld.long 0x00 12. "L2C6,L2 TLB-RAM6 EDC 1-bit error status" "0: no error,1: detect error"
bitfld.long 0x00 11. "L2UC5,L2 TLB-RAM5 EDC 2-bit error status" "0: no error,1: detect error"
newline
bitfld.long 0x00 10. "L2C5,L2 TLB-RAM5 EDC 1-bit error status" "0: no error,1: detect error"
bitfld.long 0x00 9. "L2UC4,L2 TLB-RAM4 EDC 2-bit error status" "0: no error,1: detect error"
newline
bitfld.long 0x00 8. "L2C4,L2 TLB-RAM4 EDC 1-bit error status" "0: no error,1: detect error"
bitfld.long 0x00 7. "L2UC3,L2 TLB-RAM3 EDC 2-bit error status" "0: no error,1: detect error"
newline
bitfld.long 0x00 6. "L2C3,L2 TLB-RAM3 EDC 1-bit error status" "0: no error,1: detect error"
bitfld.long 0x00 5. "L2UC2,L2 TLB-RAM2 EDC 2-bit error status" "0: no error,1: detect error"
newline
bitfld.long 0x00 4. "L2C2,L2 TLB-RAM2 EDC 1-bit error status" "0: no error,1: detect error"
bitfld.long 0x00 3. "L2UC1,L2 TLB-RAM1 EDC 2-bit error status" "0: no error,1: detect error"
newline
bitfld.long 0x00 2. "L2C1,L2 TLB-RAM1 EDC 1-bit error status" "0: no error,1: detect error"
bitfld.long 0x00 1. "L2UC0,L2 TLB-RAM0 EDC 2-bit error status" "0: no error,1: detect error"
newline
bitfld.long 0x00 0. "L2C0,L2 TLB-RAM0 EDC 1-bit error status" "0: no error,1: detect error"
group.long 0x5D0++0x03
line.long 0x00 "IMRAM1ERRCTR,This register controls the assertion of the internal TLBRAM (Short Descriptor Table) error notification signal to MFIS"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
bitfld.long 0x00 15. "L2UC7,L2 TLB-RAM7 EDC 2-bit error detect enable" "0: disable error detection,1: enable error detection"
newline
bitfld.long 0x00 14. "L2C7,L2 TLB-RAM7 EDC 1-bit error detect enable" "0: disable error detection,1: enable error detection"
bitfld.long 0x00 13. "L2UC6,L2 TLB-RAM6 EDC 2-bit error detect enable" "0: disable error detection,1: enable error detection"
newline
bitfld.long 0x00 12. "L2C6,L2 TLB-RAM6 EDC 1-bit error detect enable" "0: disable error detection,1: enable error detection"
bitfld.long 0x00 11. "L2UC5,L2 TLB-RAM5 EDC 2-bit error detect enable" "0: disable error detection,1: enable error detection"
newline
bitfld.long 0x00 10. "L2C5,L2 TLB-RAM5 EDC 1-bit error detect enable" "0: disable error detection,1: enable error detection"
bitfld.long 0x00 9. "L2UC4,L2 TLB-RAM4 EDC 2-bit error detect enable" "0: disable error detection,1: enable error detection"
newline
bitfld.long 0x00 8. "L2C4,L2 TLB-RAM4 EDC 1-bit error detect enable" "0: disable error detection,1: enable error detection"
bitfld.long 0x00 7. "L2UC3,L2 TLB-RAM3 EDC 2-bit error detect enable" "0: disable error detection,1: enable error detection"
newline
bitfld.long 0x00 6. "L2C3,L2 TLB-RAM3 EDC 1-bit error detect enable" "0: disable error detection,1: enable error detection"
bitfld.long 0x00 5. "L2UC2,L2 TLB-RAM2 EDC 2-bit error detect enable" "0: disable error detection,1: enable error detection"
newline
bitfld.long 0x00 4. "L2C2,L2 TLB-RAM2 EDC 1-bit error detect enable" "0: disable error detection,1: enable error detection"
bitfld.long 0x00 3. "L2UC1,L2 TLB-RAM1 EDC 2-bit error detect enable" "0: disable error detection,1: enable error detection"
newline
bitfld.long 0x00 2. "L2C1,L2 TLB-RAM1 EDC 1-bit error detect enable" "0: disable error detection,1: enable error detection"
bitfld.long 0x00 1. "L2UC0,L2 TLB-RAM0 EDC 2-bit error detect enable" "0: disable error detection,1: enable error detection"
newline
bitfld.long 0x00 0. "L2C0,L2 TLB-RAM0 EDC 1-bit error detect enable" "0: disable error detection,1: enable error detection"
group.long 0x5D4++0x03
line.long 0x00 "IMRAM1ERRSTR,This register indicates the error status of the internal TLBRAM (Short Descriptor Table)"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
bitfld.long 0x00 15. "L2UC7,L2 TLB-RAM7 EDC 2-bit error status" "0: no error,1: detect error"
newline
bitfld.long 0x00 14. "L2C7,L2 TLB-RAM7 EDC 1-bit error status" "0: no error,1: detect error"
bitfld.long 0x00 13. "L2UC6,L2 TLB-RAM6 EDC 2-bit error status" "0: no error,1: detect error"
newline
bitfld.long 0x00 12. "L2C6,L2 TLB-RAM6 EDC 1-bit error status" "0: no error,1: detect error"
bitfld.long 0x00 11. "L2UC5,L2 TLB-RAM5 EDC 2-bit error status" "0: no error,1: detect error"
newline
bitfld.long 0x00 10. "L2C5,L2 TLB-RAM5 EDC 1-bit error status" "0: no error,1: detect error"
bitfld.long 0x00 9. "L2UC4,L2 TLB-RAM4 EDC 2-bit error status" "0: no error,1: detect error"
newline
bitfld.long 0x00 8. "L2C4,L2 TLB-RAM4 EDC 1-bit error status" "0: no error,1: detect error"
bitfld.long 0x00 7. "L2UC3,L2 TLB-RAM3 EDC 2-bit error status" "0: no error,1: detect error"
newline
bitfld.long 0x00 6. "L2C3,L2 TLB-RAM3 EDC 1-bit error status" "0: no error,1: detect error"
bitfld.long 0x00 5. "L2UC2,L2 TLB-RAM2 EDC 2-bit error status" "0: no error,1: detect error"
newline
bitfld.long 0x00 4. "L2C2,L2 TLB-RAM2 EDC 1-bit error status" "0: no error,1: detect error"
bitfld.long 0x00 3. "L2UC1,L2 TLB-RAM1 EDC 2-bit error status" "0: no error,1: detect error"
newline
bitfld.long 0x00 2. "L2C1,L2 TLB-RAM1 EDC 1-bit error status" "0: no error,1: detect error"
bitfld.long 0x00 1. "L2UC0,L2 TLB-RAM0 EDC 2-bit error status" "0: no error,1: detect error"
newline
bitfld.long 0x00 0. "L2C0,L2 TLB-RAM0 EDC 1-bit error status" "0: no error,1: detect error"
group.long 0x1500++0x03
line.long 0x00 "IMSCTLR,This register controls the behavior of IPMMU function"
bitfld.long 0x00 31. "DISWPROT,Read and Write protection of MMU System Control Register and MMU auxiliary Control register" "0: can write IMSCTLR.NSACCEN & IMSCTLR.USE_SECGRP,1: can write/read IMSCTLR.NSACCEN &"
bitfld.long 0x00 30. "NSACCEN,Non-secure access enable for MMU System Control Register and MMU auxiliary Control register" "0: disable non-secure access (default),1: enable non-secure access"
newline
rbitfld.long 0x00 29. "Reserved_29,Reserved This bit always read as 0" "0,1"
bitfld.long 0x00 28. "USE_SECGRP,Use security group to judge Secure/Non-secure access Set this bit in IPMMU-DS0 and IPMMU-RT1 0 before using this function" "0,1"
newline
hexmask.long 0x00 0.--27. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x1504++0x03
line.long 0x00 "IMSAUXCTLR,This register controls the behavior of IPMMU function"
rbitfld.long 0x00 26.--31. "Reserved_26,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 25. "MHINT40,disable the hint field in long descriptor format" "0: enable the hint field (default),1: disable the hint field Hint feature is only"
newline
bitfld.long 0x00 24. "NMERGE40,disable merge for the adjacent TLB entry in long descriptor format" "0: enable merge for the adjacent TLB entry..,1: disable merge for the adjacent TLB entry"
hexmask.long.byte 0x00 17.--23. 1. "Reserved_17,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 16. "NMERGE32,disable merge for the adjacent TLB entry in short descriptor format" "0: enable merge for the adjacent TLB entry..,1: disable merge for the adjacent TLB entry"
hexmask.long.word 0x00 4.--15. 1. "Reserved_4,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 3. "S2PTE,support stage 2 translation table format" "0: use stage 1 translation table format when stage,1: use stage 2 translation table format when stage"
rbitfld.long 0x00 0.--2. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
group.long 0x1580++0x03
line.long 0x00 "IMPFMCTR,"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are always read as 0"
bitfld.long 0x00 12.--13. "MD_1_0,Monitor Mode IPMMU (main)" "0: Monitor all 40-bit MMUs,1: Monitor all 32-bit MMUs,2: Reserved,3: Monitor only MMUn (specified by the SEL bits)"
newline
bitfld.long 0x00 8.--11. "SEL_3_0,When MD is B'11 SEL indicates the MMU table number to be monitored" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 2.--7. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 1. "RST,Reset all status and counter values" "0,1"
bitfld.long 0x00 0. "EN,Performance Monitor Enable" "0: Stop to count,1: Start to count All counters stop when"
group.long 0x1590++0x03
line.long 0x00 "IMPFMTOTAL,"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TOTAL_23_0,The total number of translation requests"
group.long 0x1594++0x03
line.long 0x00 "IMPFMHIT,"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "HIT_23_0,The total number of TLB hit requests = L3 TLB hit"
group.long 0x1598++0x03
line.long 0x00 "IMPFML3MISS,"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "L3MISS_23_0,The total number of L3 miss requests (not including L2 miss and L1 miss) = L2 TLB hit"
group.long 0x159C++0x03
line.long 0x00 "IMPFML2MISS,"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "L2MISS_23_0,The total number of L2 miss requests (not including L1 miss) = Page Table Walk"
group.long 0x10000++0x03
line.long 0x00 "IMCTR0,Note: n= 0 to 15 (IPMMU context) This register controls the behavior of the MMU"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved These bits are always read as 0" "0,1,2,3"
bitfld.long 0x00 29. "VA64,AArch64 support" "0: VMSAv8-32 mode This register can be set,1: VMSAv8-64 mode"
newline
hexmask.long.word 0x00 18.--28. 1. "Reserved_18,Reserved These bits are always read as 0"
bitfld.long 0x00 17. "TRE,TEX Remap Enable This field is used when EAE is 0" "0: TEX remap disabled,1: TEX remap enabled"
newline
bitfld.long 0x00 16. "AFE,Access Flag Enable" "0: Behave as if AF bit is always set to 1,1: Enable software management of the Access Flag"
rbitfld.long 0x00 15. "SEC,Copy of IMSEC.SEC[n]" "0: Behave as non-secure context,1: Behave as secure context"
newline
hexmask.long.byte 0x00 8.--14. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 4.--7. "RTSEL_3_0,Retranslation Table Select When TREN is 1 RTSEL indicates the table number to retranslate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 3. "TREN,MMU Retranslation Enable" "0: Output PA as a physical address,1: Output PA as an intermediate physical address.."
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error occurs,1: Assert an interrupt when an error occurs"
newline
bitfld.long 0x00 1. "FLUSH,TLB Invalidate This bit is automatically cleared to 0" "0,1"
bitfld.long 0x00 0. "MMUEN,MMU Enable" "0: MMU disabled,1: MMU enabled"
group.long 0x10008++0x03
line.long 0x00 "IMTTBCR0,Note: n= 0 to 15 (IPMMU context) This register controls the attribute of TLB managed by each MMU"
bitfld.long 0x00 31. "EAE,Extended Address Enable" "0: Enable the 32-bit translation system with the,1: Enable the 40-bit translation System with the"
bitfld.long 0x00 30. "PMB,[EAE=0] PMB Enable This bit could be set only 0 when EAE=0" "0: not bypass stage 1 translation when stage 2,1: bypass stage 1 translation when only stage 2"
newline
bitfld.long 0x00 28.--29. "SH1_1_0,Share ability attributes for the memory associated with the translation table walks using TTBR1n" "0: Non-shareable,1: Reserved,2: Outer shareable,3: Inner shareable"
bitfld.long 0x00 26.--27. "ORGN1_1_0,Outer Cache ability attributes for the memory associated with the translation table walks using TTBR1n" "0: Normal memory Outer Non-cacheable,1: Normal memory Outer Write-Back Write-Allocate,2: Normal memory Outer Write-Through Cacheable,3: Normal memory Outer Write-Back no.."
newline
bitfld.long 0x00 24.--25. "IRGN1_1_0,Inner Cache ability attributes for the memory associated with the translation table walks using TTBR1n" "0: Normal memory Inner Non-cacheable,1: Normal memory Inner Write-Back Write-Allocate,2: Normal memory Inner Write-Through Cacheable,3: Normal memory Inner Write-Back no.."
bitfld.long 0x00 23. "PGSZ,[VMSAv8-32 EAE=0] 2nd level Page Size Select" "0: 4KB page granule (default),1: 64KB page granule"
newline
bitfld.long 0x00 22. "SCSZ,[VMSAv8-32 EAE=0] 1st level page size select" "0: Support section size (1MB),1: Support super section size (16MB)"
bitfld.long 0x00 16.--21. "TSZ1_5_0,[VMSAv8-64] TSZ1[5:0] is used for the size offset of the TTBR0n addressed region encoded as a 6-bit unsigned number giving the size of the region as 2^(64-TSZ1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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rbitfld.long 0x00 14.--15. "Reserved_14,Reserved These bits are always read as 0" "0,1,2,3"
bitfld.long 0x00 12.--13. "SH0_1_0,Share ability attributes for the memory associated with the translation table walks using TTBR0n" "0: Non-shareable,1: Reserved,2: Outer shareable,3: Inner shareable"
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bitfld.long 0x00 10.--11. "ORGN0_1_0,Outer Cache ability attributes for the memory associated with the translation table walks using TTBR0n" "0: Normal memory Outer Non-cacheable,1: Normal memory Outer Write-Back Write-Allocate,2: Normal memory Outer Write-Through Cacheable,3: Normal memory Outer Write-Back no.."
bitfld.long 0x00 8.--9. "IRGN0_1_0,Inner Cache ability attributes for the memory associated with the translation table walks using TTBR0n" "0: Normal memory Inner Non-cacheable,1: Normal memory Inner Write-Back Write-Allocate,2: Normal memory Inner Write-Through Cacheable,3: Normal memory Inner Write-Back no.."
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bitfld.long 0x00 6.--7. "SL_1_0,Starting level for translation table walks" "0: Start at third level,1: Start at second level,?..."
bitfld.long 0x00 0.--5. "TSZ0_5_0,[VMSAv8-64]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x10010++0x03
line.long 0x00 "IMTTLBR00,Note: n= 0 to 15 (IPMMU context) This register indicates the base address of the TLB managed by each MMU"
hexmask.long.tbyte 0x00 12.--31. 1. "TTBR_31_12,Bits [31:12] of translation table base address"
hexmask.long.word 0x00 0.--11. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x10014++0x03
line.long 0x00 "IMTTUBR00,Note: n= 0 to 15 (IPMMU context) This register indicates the base address of the TLB managed by each MMU"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "TTBR_39_32,Bits [39:32] of translation table base address This field is used when EAE is 1"
group.long 0x10018++0x03
line.long 0x00 "IMTTLBR10,Note: n= 0 to 15 (IPMMU context) This register indicates the base address of the TLB managed by each MMU"
hexmask.long.tbyte 0x00 12.--31. 1. "TTBR_31_12,Bits [31:12] of translation table base address"
hexmask.long.word 0x00 0.--11. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x1001C++0x03
line.long 0x00 "IMTTUBR10,Note: n= 0 to 15 (IPMMU context) This register indicates the base address of the TLB managed by each MMU"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "TTBR_39_32,Bits [39:32] of translation table base address This field is used when EAE is 1"
group.long 0x10020++0x03
line.long 0x00 "IMSTR0,Note: n= 0 to 15 (IPMMU context) This register indicates the error status of during address translation"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are always read as 0"
bitfld.long 0x00 12.--13. "ERRLVL_1_0,indicate which level of page table walk caused the error" "0: Level1 page table walk,1: Level2 page table walk,2: Level3 page table walk,?..."
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rbitfld.long 0x00 11. "Reserved_11,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 8.--10. "ERRCODE_2_0,Indicate error type" "?,1: Translation Fault,?,?,4: Access Flag Fault / Permission Fault,5: Secure Access Fault Others: reserved,?..."
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rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4. "MHIT,TLB Conflict Fault Indicate that multiple TLB hits occurred" "0,1"
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rbitfld.long 0x00 3. "Reserved_3,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 2. "ABORT,This bit is set to 1 when the IPMMU received an error response during a page table walk" "0,1"
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bitfld.long 0x00 1. "PF,Permission Fault This bit is set to 1 when an access right violation occurred" "0,1"
bitfld.long 0x00 0. "TF,Translation Fault This bit is set to 1 when a translation fault occurred during a page table walk" "0,1"
group.long 0x10028++0x03
line.long 0x00 "IMMAIR00,(Short-descriptor translation format)"
abitfld.long 0x00 24.--31. "NOS7_0,Outer Shareable property mapping for memory attributes n" "0x00=0: Memory region is outer shareable,0x01=1: Memory region is inner shareable"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 19. "NS1,Mapping of S = 1 attribute for Normal memory" "0: Region is not shareable,1: Region is shareable"
bitfld.long 0x00 18. "NS0,Mapping of S = 0 attribute for Normal memory" "0: Region is not shareable,1: Region is shareable"
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bitfld.long 0x00 17. "DS1,Mapping of S = 1 attribute for Device memory" "0: Region is not shareable,1: Region is shareable"
bitfld.long 0x00 16. "DS0,Mapping of S = 0 attribute for Device memory" "0: Region is not shareable,1: Region is shareable"
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bitfld.long 0x00 14.--15. "TR7_1_0,Primary TEX mapping for memory attributes 7" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
bitfld.long 0x00 12.--13. "TR6_1_0,Primary TEX mapping for memory attributes 6" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
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bitfld.long 0x00 10.--11. "TR5_1_0,Primary TEX mapping for memory attributes 5" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
bitfld.long 0x00 8.--9. "TR4_1_0,Primary TEX mapping for memory attributes 4" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
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bitfld.long 0x00 6.--7. "TR3_1_0,Primary TEX mapping for memory attributes 3" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
bitfld.long 0x00 4.--5. "TR2_1_0,Primary TEX mapping for memory attributes 2" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
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bitfld.long 0x00 2.--3. "TR1_1_0,Primary TEX mapping for memory attributes 1" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
bitfld.long 0x00 0.--1. "TR0_1_0,Primary TEX mapping for memory attributes 0" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
group.long 0x1002C++0x03
line.long 0x00 "IMMAIR10,(Short-descriptor translation format)"
bitfld.long 0x00 30.--31. "OR7_1_0,Outer Cacheable property mapping for memory attributes 7" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 28.--29. "OR6_1_0,Outer Cacheable property mapping for memory attributes 6" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 26.--27. "OR5_1_0,Outer Cacheable property mapping for memory attributes 5" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 24.--25. "OR4_1_0,Outer Cacheable property mapping for memory attributes 4" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 22.--23. "OR3_1_0,Outer Cacheable property mapping for memory attributes 3" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 20.--21. "OR2_1_0,Outer Cacheable property mapping for memory attributes 2" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 18.--19. "OR1_1_0,Outer Cacheable property mapping for memory attributes 1" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 16.--17. "OR0_1_0,Outer Cacheable property mapping for memory attributes 0" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 14.--15. "IR7_1_0,Inner Cacheable property mapping for memory attributes 7" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 12.--13. "IR6_1_0,Inner Cacheable property mapping for memory attributes 6" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 10.--11. "IR5_1_0,Inner Cacheable property mapping for memory attributes 5" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 8.--9. "IR4_1_0,Inner Cacheable property mapping for memory attributes 4" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 6.--7. "IR3_1_0,Inner Cacheable property mapping for memory attributes 3" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 4.--5. "IR2_1_0,Inner Cacheable property mapping for memory attributes 2" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 2.--3. "IR1_1_0,Inner Cacheable property mapping for memory attributes 1" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 0.--1. "IR0_1_0,Inner Cacheable property mapping for memory attributes 0" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
group.long 0x10030++0x03
line.long 0x00 "IMELAR0,Note: n= 0 to 15 (IPMMU context) This register indicates the address which an address translation error occurred"
hexmask.long 0x00 0.--31. 1. "EAR_31_0,The faulting virtual address is set when an address translation error occurred"
group.long 0x10034++0x03
line.long 0x00 "IMEUAR0,Note: n= 0 to 15 (IPMMU context) This register indicates the address which an address translation error occurred"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "EAR_39_32,The faulting virtual address is set when an address translation error occurred"
group.long 0x10040++0x03
line.long 0x00 "IMSEC,This register controls the attribute of secure/non-secure for MMU"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
hexmask.long.word 0x00 0.--15. 1. "SEC_15_0,SEC[n]=0 : IMCTRn~IMERIDn is Non-secure SEC[n]=1 : IMCTRn~IMERIDn is Secure"
group.long 0x11040++0x03
line.long 0x00 "IMCTR1,Note: n= 0 to 15 (IPMMU context) This register controls the behavior of the MMU"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved These bits are always read as 0" "0,1,2,3"
bitfld.long 0x00 29. "VA64,AArch64 support" "0: VMSAv8-32 mode This register can be set,1: VMSAv8-64 mode"
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hexmask.long.word 0x00 18.--28. 1. "Reserved_18,Reserved These bits are always read as 0"
bitfld.long 0x00 17. "TRE,TEX Remap Enable This field is used when EAE is 0" "0: TEX remap disabled,1: TEX remap enabled"
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bitfld.long 0x00 16. "AFE,Access Flag Enable" "0: Behave as if AF bit is always set to 1,1: Enable software management of the Access Flag"
rbitfld.long 0x00 15. "SEC,Copy of IMSEC.SEC[n]" "0: Behave as non-secure context,1: Behave as secure context"
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hexmask.long.byte 0x00 8.--14. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 4.--7. "RTSEL_3_0,Retranslation Table Select When TREN is 1 RTSEL indicates the table number to retranslate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 3. "TREN,MMU Retranslation Enable" "0: Output PA as a physical address,1: Output PA as an intermediate physical address.."
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error occurs,1: Assert an interrupt when an error occurs"
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bitfld.long 0x00 1. "FLUSH,TLB Invalidate This bit is automatically cleared to 0" "0,1"
bitfld.long 0x00 0. "MMUEN,MMU Enable" "0: MMU disabled,1: MMU enabled"
group.long 0x11048++0x03
line.long 0x00 "IMTTBCR1,Note: n= 0 to 15 (IPMMU context) This register controls the attribute of TLB managed by each MMU"
bitfld.long 0x00 31. "EAE,Extended Address Enable" "0: Enable the 32-bit translation system with the,1: Enable the 40-bit translation System with the"
bitfld.long 0x00 30. "PMB,[EAE=0] PMB Enable This bit could be set only 0 when EAE=0" "0: not bypass stage 1 translation when stage 2,1: bypass stage 1 translation when only stage 2"
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bitfld.long 0x00 28.--29. "SH1_1_0,Share ability attributes for the memory associated with the translation table walks using TTBR1n" "0: Non-shareable,1: Reserved,2: Outer shareable,3: Inner shareable"
bitfld.long 0x00 26.--27. "ORGN1_1_0,Outer Cache ability attributes for the memory associated with the translation table walks using TTBR1n" "0: Normal memory Outer Non-cacheable,1: Normal memory Outer Write-Back Write-Allocate,2: Normal memory Outer Write-Through Cacheable,3: Normal memory Outer Write-Back no.."
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bitfld.long 0x00 24.--25. "IRGN1_1_0,Inner Cache ability attributes for the memory associated with the translation table walks using TTBR1n" "0: Normal memory Inner Non-cacheable,1: Normal memory Inner Write-Back Write-Allocate,2: Normal memory Inner Write-Through Cacheable,3: Normal memory Inner Write-Back no.."
bitfld.long 0x00 23. "PGSZ,[VMSAv8-32 EAE=0] 2nd level Page Size Select" "0: 4KB page granule (default),1: 64KB page granule"
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bitfld.long 0x00 22. "SCSZ,[VMSAv8-32 EAE=0] 1st level page size select" "0: Support section size (1MB),1: Support super section size (16MB)"
bitfld.long 0x00 16.--21. "TSZ1_5_0,[VMSAv8-64] TSZ1[5:0] is used for the size offset of the TTBR0n addressed region encoded as a 6-bit unsigned number giving the size of the region as 2^(64-TSZ1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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rbitfld.long 0x00 14.--15. "Reserved_14,Reserved These bits are always read as 0" "0,1,2,3"
bitfld.long 0x00 12.--13. "SH0_1_0,Share ability attributes for the memory associated with the translation table walks using TTBR0n" "0: Non-shareable,1: Reserved,2: Outer shareable,3: Inner shareable"
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bitfld.long 0x00 10.--11. "ORGN0_1_0,Outer Cache ability attributes for the memory associated with the translation table walks using TTBR0n" "0: Normal memory Outer Non-cacheable,1: Normal memory Outer Write-Back Write-Allocate,2: Normal memory Outer Write-Through Cacheable,3: Normal memory Outer Write-Back no.."
bitfld.long 0x00 8.--9. "IRGN0_1_0,Inner Cache ability attributes for the memory associated with the translation table walks using TTBR0n" "0: Normal memory Inner Non-cacheable,1: Normal memory Inner Write-Back Write-Allocate,2: Normal memory Inner Write-Through Cacheable,3: Normal memory Inner Write-Back no.."
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bitfld.long 0x00 6.--7. "SL_1_0,Starting level for translation table walks" "0: Start at third level,1: Start at second level,?..."
bitfld.long 0x00 0.--5. "TSZ0_5_0,[VMSAv8-64]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x11050++0x03
line.long 0x00 "IMTTLBR01,Note: n= 0 to 15 (IPMMU context) This register indicates the base address of the TLB managed by each MMU"
hexmask.long.tbyte 0x00 12.--31. 1. "TTBR_31_12,Bits [31:12] of translation table base address"
hexmask.long.word 0x00 0.--11. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x11054++0x03
line.long 0x00 "IMTTUBR01,Note: n= 0 to 15 (IPMMU context) This register indicates the base address of the TLB managed by each MMU"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "TTBR_39_32,Bits [39:32] of translation table base address This field is used when EAE is 1"
group.long 0x11058++0x03
line.long 0x00 "IMTTLBR11,Note: n= 0 to 15 (IPMMU context) This register indicates the base address of the TLB managed by each MMU"
hexmask.long.tbyte 0x00 12.--31. 1. "TTBR_31_12,Bits [31:12] of translation table base address"
hexmask.long.word 0x00 0.--11. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x1105C++0x03
line.long 0x00 "IMTTUBR11,Note: n= 0 to 15 (IPMMU context) This register indicates the base address of the TLB managed by each MMU"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "TTBR_39_32,Bits [39:32] of translation table base address This field is used when EAE is 1"
group.long 0x11060++0x03
line.long 0x00 "IMSTR1,Note: n= 0 to 15 (IPMMU context) This register indicates the error status of during address translation"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are always read as 0"
bitfld.long 0x00 12.--13. "ERRLVL_1_0,indicate which level of page table walk caused the error" "0: Level1 page table walk,1: Level2 page table walk,2: Level3 page table walk,?..."
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rbitfld.long 0x00 11. "Reserved_11,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 8.--10. "ERRCODE_2_0,Indicate error type" "?,1: Translation Fault,?,?,4: Access Flag Fault / Permission Fault,5: Secure Access Fault Others: reserved,?..."
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rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4. "MHIT,TLB Conflict Fault Indicate that multiple TLB hits occurred" "0,1"
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rbitfld.long 0x00 3. "Reserved_3,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 2. "ABORT,This bit is set to 1 when the IPMMU received an error response during a page table walk" "0,1"
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bitfld.long 0x00 1. "PF,Permission Fault This bit is set to 1 when an access right violation occurred" "0,1"
bitfld.long 0x00 0. "TF,Translation Fault This bit is set to 1 when a translation fault occurred during a page table walk" "0,1"
group.long 0x11068++0x03
line.long 0x00 "IMMAIR01,(Short-descriptor translation format)"
abitfld.long 0x00 24.--31. "NOS7_0,Outer Shareable property mapping for memory attributes n" "0x00=0: Memory region is outer shareable,0x01=1: Memory region is inner shareable"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 19. "NS1,Mapping of S = 1 attribute for Normal memory" "0: Region is not shareable,1: Region is shareable"
bitfld.long 0x00 18. "NS0,Mapping of S = 0 attribute for Normal memory" "0: Region is not shareable,1: Region is shareable"
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bitfld.long 0x00 17. "DS1,Mapping of S = 1 attribute for Device memory" "0: Region is not shareable,1: Region is shareable"
bitfld.long 0x00 16. "DS0,Mapping of S = 0 attribute for Device memory" "0: Region is not shareable,1: Region is shareable"
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bitfld.long 0x00 14.--15. "TR7_1_0,Primary TEX mapping for memory attributes 7" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
bitfld.long 0x00 12.--13. "TR6_1_0,Primary TEX mapping for memory attributes 6" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
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bitfld.long 0x00 10.--11. "TR5_1_0,Primary TEX mapping for memory attributes 5" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
bitfld.long 0x00 8.--9. "TR4_1_0,Primary TEX mapping for memory attributes 4" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
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bitfld.long 0x00 6.--7. "TR3_1_0,Primary TEX mapping for memory attributes 3" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
bitfld.long 0x00 4.--5. "TR2_1_0,Primary TEX mapping for memory attributes 2" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
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bitfld.long 0x00 2.--3. "TR1_1_0,Primary TEX mapping for memory attributes 1" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
bitfld.long 0x00 0.--1. "TR0_1_0,Primary TEX mapping for memory attributes 0" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
group.long 0x1106C++0x03
line.long 0x00 "IMMAIR11,(Short-descriptor translation format)"
bitfld.long 0x00 30.--31. "OR7_1_0,Outer Cacheable property mapping for memory attributes 7" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 28.--29. "OR6_1_0,Outer Cacheable property mapping for memory attributes 6" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 26.--27. "OR5_1_0,Outer Cacheable property mapping for memory attributes 5" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 24.--25. "OR4_1_0,Outer Cacheable property mapping for memory attributes 4" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 22.--23. "OR3_1_0,Outer Cacheable property mapping for memory attributes 3" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 20.--21. "OR2_1_0,Outer Cacheable property mapping for memory attributes 2" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 18.--19. "OR1_1_0,Outer Cacheable property mapping for memory attributes 1" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 16.--17. "OR0_1_0,Outer Cacheable property mapping for memory attributes 0" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 14.--15. "IR7_1_0,Inner Cacheable property mapping for memory attributes 7" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 12.--13. "IR6_1_0,Inner Cacheable property mapping for memory attributes 6" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 10.--11. "IR5_1_0,Inner Cacheable property mapping for memory attributes 5" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 8.--9. "IR4_1_0,Inner Cacheable property mapping for memory attributes 4" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 6.--7. "IR3_1_0,Inner Cacheable property mapping for memory attributes 3" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 4.--5. "IR2_1_0,Inner Cacheable property mapping for memory attributes 2" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 2.--3. "IR1_1_0,Inner Cacheable property mapping for memory attributes 1" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 0.--1. "IR0_1_0,Inner Cacheable property mapping for memory attributes 0" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
group.long 0x11070++0x03
line.long 0x00 "IMELAR1,Note: n= 0 to 15 (IPMMU context) This register indicates the address which an address translation error occurred"
hexmask.long 0x00 0.--31. 1. "EAR_31_0,The faulting virtual address is set when an address translation error occurred"
group.long 0x11074++0x03
line.long 0x00 "IMEUAR1,Note: n= 0 to 15 (IPMMU context) This register indicates the address which an address translation error occurred"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "EAR_39_32,The faulting virtual address is set when an address translation error occurred"
group.long 0x12080++0x03
line.long 0x00 "IMCTR2,Note: n= 0 to 15 (IPMMU context) This register controls the behavior of the MMU"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved These bits are always read as 0" "0,1,2,3"
bitfld.long 0x00 29. "VA64,AArch64 support" "0: VMSAv8-32 mode This register can be set,1: VMSAv8-64 mode"
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hexmask.long.word 0x00 18.--28. 1. "Reserved_18,Reserved These bits are always read as 0"
bitfld.long 0x00 17. "TRE,TEX Remap Enable This field is used when EAE is 0" "0: TEX remap disabled,1: TEX remap enabled"
newline
bitfld.long 0x00 16. "AFE,Access Flag Enable" "0: Behave as if AF bit is always set to 1,1: Enable software management of the Access Flag"
rbitfld.long 0x00 15. "SEC,Copy of IMSEC.SEC[n]" "0: Behave as non-secure context,1: Behave as secure context"
newline
hexmask.long.byte 0x00 8.--14. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 4.--7. "RTSEL_3_0,Retranslation Table Select When TREN is 1 RTSEL indicates the table number to retranslate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 3. "TREN,MMU Retranslation Enable" "0: Output PA as a physical address,1: Output PA as an intermediate physical address.."
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error occurs,1: Assert an interrupt when an error occurs"
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bitfld.long 0x00 1. "FLUSH,TLB Invalidate This bit is automatically cleared to 0" "0,1"
bitfld.long 0x00 0. "MMUEN,MMU Enable" "0: MMU disabled,1: MMU enabled"
group.long 0x12088++0x03
line.long 0x00 "IMTTBCR2,Note: n= 0 to 15 (IPMMU context) This register controls the attribute of TLB managed by each MMU"
bitfld.long 0x00 31. "EAE,Extended Address Enable" "0: Enable the 32-bit translation system with the,1: Enable the 40-bit translation System with the"
bitfld.long 0x00 30. "PMB,[EAE=0] PMB Enable This bit could be set only 0 when EAE=0" "0: not bypass stage 1 translation when stage 2,1: bypass stage 1 translation when only stage 2"
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bitfld.long 0x00 28.--29. "SH1_1_0,Share ability attributes for the memory associated with the translation table walks using TTBR1n" "0: Non-shareable,1: Reserved,2: Outer shareable,3: Inner shareable"
bitfld.long 0x00 26.--27. "ORGN1_1_0,Outer Cache ability attributes for the memory associated with the translation table walks using TTBR1n" "0: Normal memory Outer Non-cacheable,1: Normal memory Outer Write-Back Write-Allocate,2: Normal memory Outer Write-Through Cacheable,3: Normal memory Outer Write-Back no.."
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bitfld.long 0x00 24.--25. "IRGN1_1_0,Inner Cache ability attributes for the memory associated with the translation table walks using TTBR1n" "0: Normal memory Inner Non-cacheable,1: Normal memory Inner Write-Back Write-Allocate,2: Normal memory Inner Write-Through Cacheable,3: Normal memory Inner Write-Back no.."
bitfld.long 0x00 23. "PGSZ,[VMSAv8-32 EAE=0] 2nd level Page Size Select" "0: 4KB page granule (default),1: 64KB page granule"
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bitfld.long 0x00 22. "SCSZ,[VMSAv8-32 EAE=0] 1st level page size select" "0: Support section size (1MB),1: Support super section size (16MB)"
bitfld.long 0x00 16.--21. "TSZ1_5_0,[VMSAv8-64] TSZ1[5:0] is used for the size offset of the TTBR0n addressed region encoded as a 6-bit unsigned number giving the size of the region as 2^(64-TSZ1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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rbitfld.long 0x00 14.--15. "Reserved_14,Reserved These bits are always read as 0" "0,1,2,3"
bitfld.long 0x00 12.--13. "SH0_1_0,Share ability attributes for the memory associated with the translation table walks using TTBR0n" "0: Non-shareable,1: Reserved,2: Outer shareable,3: Inner shareable"
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bitfld.long 0x00 10.--11. "ORGN0_1_0,Outer Cache ability attributes for the memory associated with the translation table walks using TTBR0n" "0: Normal memory Outer Non-cacheable,1: Normal memory Outer Write-Back Write-Allocate,2: Normal memory Outer Write-Through Cacheable,3: Normal memory Outer Write-Back no.."
bitfld.long 0x00 8.--9. "IRGN0_1_0,Inner Cache ability attributes for the memory associated with the translation table walks using TTBR0n" "0: Normal memory Inner Non-cacheable,1: Normal memory Inner Write-Back Write-Allocate,2: Normal memory Inner Write-Through Cacheable,3: Normal memory Inner Write-Back no.."
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bitfld.long 0x00 6.--7. "SL_1_0,Starting level for translation table walks" "0: Start at third level,1: Start at second level,?..."
bitfld.long 0x00 0.--5. "TSZ0_5_0,[VMSAv8-64]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x12090++0x03
line.long 0x00 "IMTTLBR02,Note: n= 0 to 15 (IPMMU context) This register indicates the base address of the TLB managed by each MMU"
hexmask.long.tbyte 0x00 12.--31. 1. "TTBR_31_12,Bits [31:12] of translation table base address"
hexmask.long.word 0x00 0.--11. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x12094++0x03
line.long 0x00 "IMTTUBR02,Note: n= 0 to 15 (IPMMU context) This register indicates the base address of the TLB managed by each MMU"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "TTBR_39_32,Bits [39:32] of translation table base address This field is used when EAE is 1"
group.long 0x12098++0x03
line.long 0x00 "IMTTLBR12,Note: n= 0 to 15 (IPMMU context) This register indicates the base address of the TLB managed by each MMU"
hexmask.long.tbyte 0x00 12.--31. 1. "TTBR_31_12,Bits [31:12] of translation table base address"
hexmask.long.word 0x00 0.--11. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x1209C++0x03
line.long 0x00 "IMTTUBR12,Note: n= 0 to 15 (IPMMU context) This register indicates the base address of the TLB managed by each MMU"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "TTBR_39_32,Bits [39:32] of translation table base address This field is used when EAE is 1"
group.long 0x120A0++0x03
line.long 0x00 "IMSTR2,Note: n= 0 to 15 (IPMMU context) This register indicates the error status of during address translation"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are always read as 0"
bitfld.long 0x00 12.--13. "ERRLVL_1_0,indicate which level of page table walk caused the error" "0: Level1 page table walk,1: Level2 page table walk,2: Level3 page table walk,?..."
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rbitfld.long 0x00 11. "Reserved_11,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 8.--10. "ERRCODE_2_0,Indicate error type" "?,1: Translation Fault,?,?,4: Access Flag Fault / Permission Fault,5: Secure Access Fault Others: reserved,?..."
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rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4. "MHIT,TLB Conflict Fault Indicate that multiple TLB hits occurred" "0,1"
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rbitfld.long 0x00 3. "Reserved_3,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 2. "ABORT,This bit is set to 1 when the IPMMU received an error response during a page table walk" "0,1"
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bitfld.long 0x00 1. "PF,Permission Fault This bit is set to 1 when an access right violation occurred" "0,1"
bitfld.long 0x00 0. "TF,Translation Fault This bit is set to 1 when a translation fault occurred during a page table walk" "0,1"
group.long 0x120A8++0x03
line.long 0x00 "IMMAIR02,(Short-descriptor translation format)"
abitfld.long 0x00 24.--31. "NOS7_0,Outer Shareable property mapping for memory attributes n" "0x00=0: Memory region is outer shareable,0x01=1: Memory region is inner shareable"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 19. "NS1,Mapping of S = 1 attribute for Normal memory" "0: Region is not shareable,1: Region is shareable"
bitfld.long 0x00 18. "NS0,Mapping of S = 0 attribute for Normal memory" "0: Region is not shareable,1: Region is shareable"
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bitfld.long 0x00 17. "DS1,Mapping of S = 1 attribute for Device memory" "0: Region is not shareable,1: Region is shareable"
bitfld.long 0x00 16. "DS0,Mapping of S = 0 attribute for Device memory" "0: Region is not shareable,1: Region is shareable"
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bitfld.long 0x00 14.--15. "TR7_1_0,Primary TEX mapping for memory attributes 7" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
bitfld.long 0x00 12.--13. "TR6_1_0,Primary TEX mapping for memory attributes 6" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
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bitfld.long 0x00 10.--11. "TR5_1_0,Primary TEX mapping for memory attributes 5" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
bitfld.long 0x00 8.--9. "TR4_1_0,Primary TEX mapping for memory attributes 4" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
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bitfld.long 0x00 6.--7. "TR3_1_0,Primary TEX mapping for memory attributes 3" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
bitfld.long 0x00 4.--5. "TR2_1_0,Primary TEX mapping for memory attributes 2" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
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bitfld.long 0x00 2.--3. "TR1_1_0,Primary TEX mapping for memory attributes 1" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
bitfld.long 0x00 0.--1. "TR0_1_0,Primary TEX mapping for memory attributes 0" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
group.long 0x120AC++0x03
line.long 0x00 "IMMAIR12,(Short-descriptor translation format)"
bitfld.long 0x00 30.--31. "OR7_1_0,Outer Cacheable property mapping for memory attributes 7" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 28.--29. "OR6_1_0,Outer Cacheable property mapping for memory attributes 6" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 26.--27. "OR5_1_0,Outer Cacheable property mapping for memory attributes 5" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 24.--25. "OR4_1_0,Outer Cacheable property mapping for memory attributes 4" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 22.--23. "OR3_1_0,Outer Cacheable property mapping for memory attributes 3" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 20.--21. "OR2_1_0,Outer Cacheable property mapping for memory attributes 2" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 18.--19. "OR1_1_0,Outer Cacheable property mapping for memory attributes 1" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 16.--17. "OR0_1_0,Outer Cacheable property mapping for memory attributes 0" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 14.--15. "IR7_1_0,Inner Cacheable property mapping for memory attributes 7" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 12.--13. "IR6_1_0,Inner Cacheable property mapping for memory attributes 6" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 10.--11. "IR5_1_0,Inner Cacheable property mapping for memory attributes 5" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 8.--9. "IR4_1_0,Inner Cacheable property mapping for memory attributes 4" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 6.--7. "IR3_1_0,Inner Cacheable property mapping for memory attributes 3" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 4.--5. "IR2_1_0,Inner Cacheable property mapping for memory attributes 2" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 2.--3. "IR1_1_0,Inner Cacheable property mapping for memory attributes 1" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 0.--1. "IR0_1_0,Inner Cacheable property mapping for memory attributes 0" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
group.long 0x120B0++0x03
line.long 0x00 "IMELAR2,Note: n= 0 to 15 (IPMMU context) This register indicates the address which an address translation error occurred"
hexmask.long 0x00 0.--31. 1. "EAR_31_0,The faulting virtual address is set when an address translation error occurred"
group.long 0x120B4++0x03
line.long 0x00 "IMEUAR2,Note: n= 0 to 15 (IPMMU context) This register indicates the address which an address translation error occurred"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "EAR_39_32,The faulting virtual address is set when an address translation error occurred"
group.long 0x130C0++0x03
line.long 0x00 "IMCTR3,Note: n= 0 to 15 (IPMMU context) This register controls the behavior of the MMU"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved These bits are always read as 0" "0,1,2,3"
bitfld.long 0x00 29. "VA64,AArch64 support" "0: VMSAv8-32 mode This register can be set,1: VMSAv8-64 mode"
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hexmask.long.word 0x00 18.--28. 1. "Reserved_18,Reserved These bits are always read as 0"
bitfld.long 0x00 17. "TRE,TEX Remap Enable This field is used when EAE is 0" "0: TEX remap disabled,1: TEX remap enabled"
newline
bitfld.long 0x00 16. "AFE,Access Flag Enable" "0: Behave as if AF bit is always set to 1,1: Enable software management of the Access Flag"
rbitfld.long 0x00 15. "SEC,Copy of IMSEC.SEC[n]" "0: Behave as non-secure context,1: Behave as secure context"
newline
hexmask.long.byte 0x00 8.--14. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 4.--7. "RTSEL_3_0,Retranslation Table Select When TREN is 1 RTSEL indicates the table number to retranslate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 3. "TREN,MMU Retranslation Enable" "0: Output PA as a physical address,1: Output PA as an intermediate physical address.."
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error occurs,1: Assert an interrupt when an error occurs"
newline
bitfld.long 0x00 1. "FLUSH,TLB Invalidate This bit is automatically cleared to 0" "0,1"
bitfld.long 0x00 0. "MMUEN,MMU Enable" "0: MMU disabled,1: MMU enabled"
group.long 0x130C8++0x03
line.long 0x00 "IMTTBCR3,Note: n= 0 to 15 (IPMMU context) This register controls the attribute of TLB managed by each MMU"
bitfld.long 0x00 31. "EAE,Extended Address Enable" "0: Enable the 32-bit translation system with the,1: Enable the 40-bit translation System with the"
bitfld.long 0x00 30. "PMB,[EAE=0] PMB Enable This bit could be set only 0 when EAE=0" "0: not bypass stage 1 translation when stage 2,1: bypass stage 1 translation when only stage 2"
newline
bitfld.long 0x00 28.--29. "SH1_1_0,Share ability attributes for the memory associated with the translation table walks using TTBR1n" "0: Non-shareable,1: Reserved,2: Outer shareable,3: Inner shareable"
bitfld.long 0x00 26.--27. "ORGN1_1_0,Outer Cache ability attributes for the memory associated with the translation table walks using TTBR1n" "0: Normal memory Outer Non-cacheable,1: Normal memory Outer Write-Back Write-Allocate,2: Normal memory Outer Write-Through Cacheable,3: Normal memory Outer Write-Back no.."
newline
bitfld.long 0x00 24.--25. "IRGN1_1_0,Inner Cache ability attributes for the memory associated with the translation table walks using TTBR1n" "0: Normal memory Inner Non-cacheable,1: Normal memory Inner Write-Back Write-Allocate,2: Normal memory Inner Write-Through Cacheable,3: Normal memory Inner Write-Back no.."
bitfld.long 0x00 23. "PGSZ,[VMSAv8-32 EAE=0] 2nd level Page Size Select" "0: 4KB page granule (default),1: 64KB page granule"
newline
bitfld.long 0x00 22. "SCSZ,[VMSAv8-32 EAE=0] 1st level page size select" "0: Support section size (1MB),1: Support super section size (16MB)"
bitfld.long 0x00 16.--21. "TSZ1_5_0,[VMSAv8-64] TSZ1[5:0] is used for the size offset of the TTBR0n addressed region encoded as a 6-bit unsigned number giving the size of the region as 2^(64-TSZ1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 14.--15. "Reserved_14,Reserved These bits are always read as 0" "0,1,2,3"
bitfld.long 0x00 12.--13. "SH0_1_0,Share ability attributes for the memory associated with the translation table walks using TTBR0n" "0: Non-shareable,1: Reserved,2: Outer shareable,3: Inner shareable"
newline
bitfld.long 0x00 10.--11. "ORGN0_1_0,Outer Cache ability attributes for the memory associated with the translation table walks using TTBR0n" "0: Normal memory Outer Non-cacheable,1: Normal memory Outer Write-Back Write-Allocate,2: Normal memory Outer Write-Through Cacheable,3: Normal memory Outer Write-Back no.."
bitfld.long 0x00 8.--9. "IRGN0_1_0,Inner Cache ability attributes for the memory associated with the translation table walks using TTBR0n" "0: Normal memory Inner Non-cacheable,1: Normal memory Inner Write-Back Write-Allocate,2: Normal memory Inner Write-Through Cacheable,3: Normal memory Inner Write-Back no.."
newline
bitfld.long 0x00 6.--7. "SL_1_0,Starting level for translation table walks" "0: Start at third level,1: Start at second level,?..."
bitfld.long 0x00 0.--5. "TSZ0_5_0,[VMSAv8-64]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x130D0++0x03
line.long 0x00 "IMTTLBR03,Note: n= 0 to 15 (IPMMU context) This register indicates the base address of the TLB managed by each MMU"
hexmask.long.tbyte 0x00 12.--31. 1. "TTBR_31_12,Bits [31:12] of translation table base address"
hexmask.long.word 0x00 0.--11. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x130D4++0x03
line.long 0x00 "IMTTUBR03,Note: n= 0 to 15 (IPMMU context) This register indicates the base address of the TLB managed by each MMU"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "TTBR_39_32,Bits [39:32] of translation table base address This field is used when EAE is 1"
group.long 0x130D8++0x03
line.long 0x00 "IMTTLBR13,Note: n= 0 to 15 (IPMMU context) This register indicates the base address of the TLB managed by each MMU"
hexmask.long.tbyte 0x00 12.--31. 1. "TTBR_31_12,Bits [31:12] of translation table base address"
hexmask.long.word 0x00 0.--11. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x130DC++0x03
line.long 0x00 "IMTTUBR13,Note: n= 0 to 15 (IPMMU context) This register indicates the base address of the TLB managed by each MMU"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "TTBR_39_32,Bits [39:32] of translation table base address This field is used when EAE is 1"
group.long 0x130E0++0x03
line.long 0x00 "IMSTR3,Note: n= 0 to 15 (IPMMU context) This register indicates the error status of during address translation"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are always read as 0"
bitfld.long 0x00 12.--13. "ERRLVL_1_0,indicate which level of page table walk caused the error" "0: Level1 page table walk,1: Level2 page table walk,2: Level3 page table walk,?..."
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rbitfld.long 0x00 11. "Reserved_11,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 8.--10. "ERRCODE_2_0,Indicate error type" "?,1: Translation Fault,?,?,4: Access Flag Fault / Permission Fault,5: Secure Access Fault Others: reserved,?..."
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rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4. "MHIT,TLB Conflict Fault Indicate that multiple TLB hits occurred" "0,1"
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rbitfld.long 0x00 3. "Reserved_3,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 2. "ABORT,This bit is set to 1 when the IPMMU received an error response during a page table walk" "0,1"
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bitfld.long 0x00 1. "PF,Permission Fault This bit is set to 1 when an access right violation occurred" "0,1"
bitfld.long 0x00 0. "TF,Translation Fault This bit is set to 1 when a translation fault occurred during a page table walk" "0,1"
group.long 0x130E8++0x03
line.long 0x00 "IMMAIR03,(Short-descriptor translation format)"
abitfld.long 0x00 24.--31. "NOS7_0,Outer Shareable property mapping for memory attributes n" "0x00=0: Memory region is outer shareable,0x01=1: Memory region is inner shareable"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 19. "NS1,Mapping of S = 1 attribute for Normal memory" "0: Region is not shareable,1: Region is shareable"
bitfld.long 0x00 18. "NS0,Mapping of S = 0 attribute for Normal memory" "0: Region is not shareable,1: Region is shareable"
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bitfld.long 0x00 17. "DS1,Mapping of S = 1 attribute for Device memory" "0: Region is not shareable,1: Region is shareable"
bitfld.long 0x00 16. "DS0,Mapping of S = 0 attribute for Device memory" "0: Region is not shareable,1: Region is shareable"
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bitfld.long 0x00 14.--15. "TR7_1_0,Primary TEX mapping for memory attributes 7" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
bitfld.long 0x00 12.--13. "TR6_1_0,Primary TEX mapping for memory attributes 6" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
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bitfld.long 0x00 10.--11. "TR5_1_0,Primary TEX mapping for memory attributes 5" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
bitfld.long 0x00 8.--9. "TR4_1_0,Primary TEX mapping for memory attributes 4" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
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bitfld.long 0x00 6.--7. "TR3_1_0,Primary TEX mapping for memory attributes 3" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
bitfld.long 0x00 4.--5. "TR2_1_0,Primary TEX mapping for memory attributes 2" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
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bitfld.long 0x00 2.--3. "TR1_1_0,Primary TEX mapping for memory attributes 1" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
bitfld.long 0x00 0.--1. "TR0_1_0,Primary TEX mapping for memory attributes 0" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
group.long 0x130EC++0x03
line.long 0x00 "IMMAIR13,(Short-descriptor translation format)"
bitfld.long 0x00 30.--31. "OR7_1_0,Outer Cacheable property mapping for memory attributes 7" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 28.--29. "OR6_1_0,Outer Cacheable property mapping for memory attributes 6" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 26.--27. "OR5_1_0,Outer Cacheable property mapping for memory attributes 5" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 24.--25. "OR4_1_0,Outer Cacheable property mapping for memory attributes 4" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 22.--23. "OR3_1_0,Outer Cacheable property mapping for memory attributes 3" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 20.--21. "OR2_1_0,Outer Cacheable property mapping for memory attributes 2" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 18.--19. "OR1_1_0,Outer Cacheable property mapping for memory attributes 1" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 16.--17. "OR0_1_0,Outer Cacheable property mapping for memory attributes 0" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 14.--15. "IR7_1_0,Inner Cacheable property mapping for memory attributes 7" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 12.--13. "IR6_1_0,Inner Cacheable property mapping for memory attributes 6" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 10.--11. "IR5_1_0,Inner Cacheable property mapping for memory attributes 5" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 8.--9. "IR4_1_0,Inner Cacheable property mapping for memory attributes 4" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 6.--7. "IR3_1_0,Inner Cacheable property mapping for memory attributes 3" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 4.--5. "IR2_1_0,Inner Cacheable property mapping for memory attributes 2" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 2.--3. "IR1_1_0,Inner Cacheable property mapping for memory attributes 1" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 0.--1. "IR0_1_0,Inner Cacheable property mapping for memory attributes 0" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
group.long 0x130F0++0x03
line.long 0x00 "IMELAR3,Note: n= 0 to 15 (IPMMU context) This register indicates the address which an address translation error occurred"
hexmask.long 0x00 0.--31. 1. "EAR_31_0,The faulting virtual address is set when an address translation error occurred"
group.long 0x130F4++0x03
line.long 0x00 "IMEUAR3,Note: n= 0 to 15 (IPMMU context) This register indicates the address which an address translation error occurred"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "EAR_39_32,The faulting virtual address is set when an address translation error occurred"
group.long 0x14100++0x03
line.long 0x00 "IMCTR4,Note: n= 0 to 15 (IPMMU context) This register controls the behavior of the MMU"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved These bits are always read as 0" "0,1,2,3"
bitfld.long 0x00 29. "VA64,AArch64 support" "0: VMSAv8-32 mode This register can be set,1: VMSAv8-64 mode"
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hexmask.long.word 0x00 18.--28. 1. "Reserved_18,Reserved These bits are always read as 0"
bitfld.long 0x00 17. "TRE,TEX Remap Enable This field is used when EAE is 0" "0: TEX remap disabled,1: TEX remap enabled"
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bitfld.long 0x00 16. "AFE,Access Flag Enable" "0: Behave as if AF bit is always set to 1,1: Enable software management of the Access Flag"
rbitfld.long 0x00 15. "SEC,Copy of IMSEC.SEC[n]" "0: Behave as non-secure context,1: Behave as secure context"
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hexmask.long.byte 0x00 8.--14. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 4.--7. "RTSEL_3_0,Retranslation Table Select When TREN is 1 RTSEL indicates the table number to retranslate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 3. "TREN,MMU Retranslation Enable" "0: Output PA as a physical address,1: Output PA as an intermediate physical address.."
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error occurs,1: Assert an interrupt when an error occurs"
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bitfld.long 0x00 1. "FLUSH,TLB Invalidate This bit is automatically cleared to 0" "0,1"
bitfld.long 0x00 0. "MMUEN,MMU Enable" "0: MMU disabled,1: MMU enabled"
group.long 0x14108++0x03
line.long 0x00 "IMTTBCR4,Note: n= 0 to 15 (IPMMU context) This register controls the attribute of TLB managed by each MMU"
bitfld.long 0x00 31. "EAE,Extended Address Enable" "0: Enable the 32-bit translation system with the,1: Enable the 40-bit translation System with the"
bitfld.long 0x00 30. "PMB,[EAE=0] PMB Enable This bit could be set only 0 when EAE=0" "0: not bypass stage 1 translation when stage 2,1: bypass stage 1 translation when only stage 2"
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bitfld.long 0x00 28.--29. "SH1_1_0,Share ability attributes for the memory associated with the translation table walks using TTBR1n" "0: Non-shareable,1: Reserved,2: Outer shareable,3: Inner shareable"
bitfld.long 0x00 26.--27. "ORGN1_1_0,Outer Cache ability attributes for the memory associated with the translation table walks using TTBR1n" "0: Normal memory Outer Non-cacheable,1: Normal memory Outer Write-Back Write-Allocate,2: Normal memory Outer Write-Through Cacheable,3: Normal memory Outer Write-Back no.."
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bitfld.long 0x00 24.--25. "IRGN1_1_0,Inner Cache ability attributes for the memory associated with the translation table walks using TTBR1n" "0: Normal memory Inner Non-cacheable,1: Normal memory Inner Write-Back Write-Allocate,2: Normal memory Inner Write-Through Cacheable,3: Normal memory Inner Write-Back no.."
bitfld.long 0x00 23. "PGSZ,[VMSAv8-32 EAE=0] 2nd level Page Size Select" "0: 4KB page granule (default),1: 64KB page granule"
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bitfld.long 0x00 22. "SCSZ,[VMSAv8-32 EAE=0] 1st level page size select" "0: Support section size (1MB),1: Support super section size (16MB)"
bitfld.long 0x00 16.--21. "TSZ1_5_0,[VMSAv8-64] TSZ1[5:0] is used for the size offset of the TTBR0n addressed region encoded as a 6-bit unsigned number giving the size of the region as 2^(64-TSZ1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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rbitfld.long 0x00 14.--15. "Reserved_14,Reserved These bits are always read as 0" "0,1,2,3"
bitfld.long 0x00 12.--13. "SH0_1_0,Share ability attributes for the memory associated with the translation table walks using TTBR0n" "0: Non-shareable,1: Reserved,2: Outer shareable,3: Inner shareable"
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bitfld.long 0x00 10.--11. "ORGN0_1_0,Outer Cache ability attributes for the memory associated with the translation table walks using TTBR0n" "0: Normal memory Outer Non-cacheable,1: Normal memory Outer Write-Back Write-Allocate,2: Normal memory Outer Write-Through Cacheable,3: Normal memory Outer Write-Back no.."
bitfld.long 0x00 8.--9. "IRGN0_1_0,Inner Cache ability attributes for the memory associated with the translation table walks using TTBR0n" "0: Normal memory Inner Non-cacheable,1: Normal memory Inner Write-Back Write-Allocate,2: Normal memory Inner Write-Through Cacheable,3: Normal memory Inner Write-Back no.."
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bitfld.long 0x00 6.--7. "SL_1_0,Starting level for translation table walks" "0: Start at third level,1: Start at second level,?..."
bitfld.long 0x00 0.--5. "TSZ0_5_0,[VMSAv8-64]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x14110++0x03
line.long 0x00 "IMTTLBR04,Note: n= 0 to 15 (IPMMU context) This register indicates the base address of the TLB managed by each MMU"
hexmask.long.tbyte 0x00 12.--31. 1. "TTBR_31_12,Bits [31:12] of translation table base address"
hexmask.long.word 0x00 0.--11. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x14114++0x03
line.long 0x00 "IMTTUBR04,Note: n= 0 to 15 (IPMMU context) This register indicates the base address of the TLB managed by each MMU"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "TTBR_39_32,Bits [39:32] of translation table base address This field is used when EAE is 1"
group.long 0x14118++0x03
line.long 0x00 "IMTTLBR14,Note: n= 0 to 15 (IPMMU context) This register indicates the base address of the TLB managed by each MMU"
hexmask.long.tbyte 0x00 12.--31. 1. "TTBR_31_12,Bits [31:12] of translation table base address"
hexmask.long.word 0x00 0.--11. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x1411C++0x03
line.long 0x00 "IMTTUBR14,Note: n= 0 to 15 (IPMMU context) This register indicates the base address of the TLB managed by each MMU"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "TTBR_39_32,Bits [39:32] of translation table base address This field is used when EAE is 1"
group.long 0x14120++0x03
line.long 0x00 "IMSTR4,Note: n= 0 to 15 (IPMMU context) This register indicates the error status of during address translation"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are always read as 0"
bitfld.long 0x00 12.--13. "ERRLVL_1_0,indicate which level of page table walk caused the error" "0: Level1 page table walk,1: Level2 page table walk,2: Level3 page table walk,?..."
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rbitfld.long 0x00 11. "Reserved_11,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 8.--10. "ERRCODE_2_0,Indicate error type" "?,1: Translation Fault,?,?,4: Access Flag Fault / Permission Fault,5: Secure Access Fault Others: reserved,?..."
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rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4. "MHIT,TLB Conflict Fault Indicate that multiple TLB hits occurred" "0,1"
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rbitfld.long 0x00 3. "Reserved_3,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 2. "ABORT,This bit is set to 1 when the IPMMU received an error response during a page table walk" "0,1"
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bitfld.long 0x00 1. "PF,Permission Fault This bit is set to 1 when an access right violation occurred" "0,1"
bitfld.long 0x00 0. "TF,Translation Fault This bit is set to 1 when a translation fault occurred during a page table walk" "0,1"
group.long 0x14128++0x03
line.long 0x00 "IMMAIR04,(Short-descriptor translation format)"
abitfld.long 0x00 24.--31. "NOS7_0,Outer Shareable property mapping for memory attributes n" "0x00=0: Memory region is outer shareable,0x01=1: Memory region is inner shareable"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 19. "NS1,Mapping of S = 1 attribute for Normal memory" "0: Region is not shareable,1: Region is shareable"
bitfld.long 0x00 18. "NS0,Mapping of S = 0 attribute for Normal memory" "0: Region is not shareable,1: Region is shareable"
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bitfld.long 0x00 17. "DS1,Mapping of S = 1 attribute for Device memory" "0: Region is not shareable,1: Region is shareable"
bitfld.long 0x00 16. "DS0,Mapping of S = 0 attribute for Device memory" "0: Region is not shareable,1: Region is shareable"
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bitfld.long 0x00 14.--15. "TR7_1_0,Primary TEX mapping for memory attributes 7" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
bitfld.long 0x00 12.--13. "TR6_1_0,Primary TEX mapping for memory attributes 6" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
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bitfld.long 0x00 10.--11. "TR5_1_0,Primary TEX mapping for memory attributes 5" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
bitfld.long 0x00 8.--9. "TR4_1_0,Primary TEX mapping for memory attributes 4" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
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bitfld.long 0x00 6.--7. "TR3_1_0,Primary TEX mapping for memory attributes 3" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
bitfld.long 0x00 4.--5. "TR2_1_0,Primary TEX mapping for memory attributes 2" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
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bitfld.long 0x00 2.--3. "TR1_1_0,Primary TEX mapping for memory attributes 1" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
bitfld.long 0x00 0.--1. "TR0_1_0,Primary TEX mapping for memory attributes 0" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
group.long 0x1412C++0x03
line.long 0x00 "IMMAIR14,(Short-descriptor translation format)"
bitfld.long 0x00 30.--31. "OR7_1_0,Outer Cacheable property mapping for memory attributes 7" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 28.--29. "OR6_1_0,Outer Cacheable property mapping for memory attributes 6" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 26.--27. "OR5_1_0,Outer Cacheable property mapping for memory attributes 5" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 24.--25. "OR4_1_0,Outer Cacheable property mapping for memory attributes 4" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 22.--23. "OR3_1_0,Outer Cacheable property mapping for memory attributes 3" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 20.--21. "OR2_1_0,Outer Cacheable property mapping for memory attributes 2" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 18.--19. "OR1_1_0,Outer Cacheable property mapping for memory attributes 1" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 16.--17. "OR0_1_0,Outer Cacheable property mapping for memory attributes 0" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 14.--15. "IR7_1_0,Inner Cacheable property mapping for memory attributes 7" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 12.--13. "IR6_1_0,Inner Cacheable property mapping for memory attributes 6" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 10.--11. "IR5_1_0,Inner Cacheable property mapping for memory attributes 5" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 8.--9. "IR4_1_0,Inner Cacheable property mapping for memory attributes 4" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 6.--7. "IR3_1_0,Inner Cacheable property mapping for memory attributes 3" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 4.--5. "IR2_1_0,Inner Cacheable property mapping for memory attributes 2" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 2.--3. "IR1_1_0,Inner Cacheable property mapping for memory attributes 1" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 0.--1. "IR0_1_0,Inner Cacheable property mapping for memory attributes 0" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
group.long 0x14130++0x03
line.long 0x00 "IMELAR4,Note: n= 0 to 15 (IPMMU context) This register indicates the address which an address translation error occurred"
hexmask.long 0x00 0.--31. 1. "EAR_31_0,The faulting virtual address is set when an address translation error occurred"
group.long 0x14134++0x03
line.long 0x00 "IMEUAR4,Note: n= 0 to 15 (IPMMU context) This register indicates the address which an address translation error occurred"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "EAR_39_32,The faulting virtual address is set when an address translation error occurred"
group.long 0x15140++0x03
line.long 0x00 "IMCTR5,Note: n= 0 to 15 (IPMMU context) This register controls the behavior of the MMU"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved These bits are always read as 0" "0,1,2,3"
bitfld.long 0x00 29. "VA64,AArch64 support" "0: VMSAv8-32 mode This register can be set,1: VMSAv8-64 mode"
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hexmask.long.word 0x00 18.--28. 1. "Reserved_18,Reserved These bits are always read as 0"
bitfld.long 0x00 17. "TRE,TEX Remap Enable This field is used when EAE is 0" "0: TEX remap disabled,1: TEX remap enabled"
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bitfld.long 0x00 16. "AFE,Access Flag Enable" "0: Behave as if AF bit is always set to 1,1: Enable software management of the Access Flag"
rbitfld.long 0x00 15. "SEC,Copy of IMSEC.SEC[n]" "0: Behave as non-secure context,1: Behave as secure context"
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hexmask.long.byte 0x00 8.--14. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 4.--7. "RTSEL_3_0,Retranslation Table Select When TREN is 1 RTSEL indicates the table number to retranslate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 3. "TREN,MMU Retranslation Enable" "0: Output PA as a physical address,1: Output PA as an intermediate physical address.."
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error occurs,1: Assert an interrupt when an error occurs"
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bitfld.long 0x00 1. "FLUSH,TLB Invalidate This bit is automatically cleared to 0" "0,1"
bitfld.long 0x00 0. "MMUEN,MMU Enable" "0: MMU disabled,1: MMU enabled"
group.long 0x15148++0x03
line.long 0x00 "IMTTBCR5,Note: n= 0 to 15 (IPMMU context) This register controls the attribute of TLB managed by each MMU"
bitfld.long 0x00 31. "EAE,Extended Address Enable" "0: Enable the 32-bit translation system with the,1: Enable the 40-bit translation System with the"
bitfld.long 0x00 30. "PMB,[EAE=0] PMB Enable This bit could be set only 0 when EAE=0" "0: not bypass stage 1 translation when stage 2,1: bypass stage 1 translation when only stage 2"
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bitfld.long 0x00 28.--29. "SH1_1_0,Share ability attributes for the memory associated with the translation table walks using TTBR1n" "0: Non-shareable,1: Reserved,2: Outer shareable,3: Inner shareable"
bitfld.long 0x00 26.--27. "ORGN1_1_0,Outer Cache ability attributes for the memory associated with the translation table walks using TTBR1n" "0: Normal memory Outer Non-cacheable,1: Normal memory Outer Write-Back Write-Allocate,2: Normal memory Outer Write-Through Cacheable,3: Normal memory Outer Write-Back no.."
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bitfld.long 0x00 24.--25. "IRGN1_1_0,Inner Cache ability attributes for the memory associated with the translation table walks using TTBR1n" "0: Normal memory Inner Non-cacheable,1: Normal memory Inner Write-Back Write-Allocate,2: Normal memory Inner Write-Through Cacheable,3: Normal memory Inner Write-Back no.."
bitfld.long 0x00 23. "PGSZ,[VMSAv8-32 EAE=0] 2nd level Page Size Select" "0: 4KB page granule (default),1: 64KB page granule"
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bitfld.long 0x00 22. "SCSZ,[VMSAv8-32 EAE=0] 1st level page size select" "0: Support section size (1MB),1: Support super section size (16MB)"
bitfld.long 0x00 16.--21. "TSZ1_5_0,[VMSAv8-64] TSZ1[5:0] is used for the size offset of the TTBR0n addressed region encoded as a 6-bit unsigned number giving the size of the region as 2^(64-TSZ1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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rbitfld.long 0x00 14.--15. "Reserved_14,Reserved These bits are always read as 0" "0,1,2,3"
bitfld.long 0x00 12.--13. "SH0_1_0,Share ability attributes for the memory associated with the translation table walks using TTBR0n" "0: Non-shareable,1: Reserved,2: Outer shareable,3: Inner shareable"
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bitfld.long 0x00 10.--11. "ORGN0_1_0,Outer Cache ability attributes for the memory associated with the translation table walks using TTBR0n" "0: Normal memory Outer Non-cacheable,1: Normal memory Outer Write-Back Write-Allocate,2: Normal memory Outer Write-Through Cacheable,3: Normal memory Outer Write-Back no.."
bitfld.long 0x00 8.--9. "IRGN0_1_0,Inner Cache ability attributes for the memory associated with the translation table walks using TTBR0n" "0: Normal memory Inner Non-cacheable,1: Normal memory Inner Write-Back Write-Allocate,2: Normal memory Inner Write-Through Cacheable,3: Normal memory Inner Write-Back no.."
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bitfld.long 0x00 6.--7. "SL_1_0,Starting level for translation table walks" "0: Start at third level,1: Start at second level,?..."
bitfld.long 0x00 0.--5. "TSZ0_5_0,[VMSAv8-64]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x15150++0x03
line.long 0x00 "IMTTLBR05,Note: n= 0 to 15 (IPMMU context) This register indicates the base address of the TLB managed by each MMU"
hexmask.long.tbyte 0x00 12.--31. 1. "TTBR_31_12,Bits [31:12] of translation table base address"
hexmask.long.word 0x00 0.--11. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x15154++0x03
line.long 0x00 "IMTTUBR05,Note: n= 0 to 15 (IPMMU context) This register indicates the base address of the TLB managed by each MMU"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "TTBR_39_32,Bits [39:32] of translation table base address This field is used when EAE is 1"
group.long 0x15158++0x03
line.long 0x00 "IMTTLBR15,Note: n= 0 to 15 (IPMMU context) This register indicates the base address of the TLB managed by each MMU"
hexmask.long.tbyte 0x00 12.--31. 1. "TTBR_31_12,Bits [31:12] of translation table base address"
hexmask.long.word 0x00 0.--11. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x1515C++0x03
line.long 0x00 "IMTTUBR15,Note: n= 0 to 15 (IPMMU context) This register indicates the base address of the TLB managed by each MMU"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "TTBR_39_32,Bits [39:32] of translation table base address This field is used when EAE is 1"
group.long 0x15160++0x03
line.long 0x00 "IMSTR5,Note: n= 0 to 15 (IPMMU context) This register indicates the error status of during address translation"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are always read as 0"
bitfld.long 0x00 12.--13. "ERRLVL_1_0,indicate which level of page table walk caused the error" "0: Level1 page table walk,1: Level2 page table walk,2: Level3 page table walk,?..."
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rbitfld.long 0x00 11. "Reserved_11,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 8.--10. "ERRCODE_2_0,Indicate error type" "?,1: Translation Fault,?,?,4: Access Flag Fault / Permission Fault,5: Secure Access Fault Others: reserved,?..."
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rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4. "MHIT,TLB Conflict Fault Indicate that multiple TLB hits occurred" "0,1"
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rbitfld.long 0x00 3. "Reserved_3,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 2. "ABORT,This bit is set to 1 when the IPMMU received an error response during a page table walk" "0,1"
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bitfld.long 0x00 1. "PF,Permission Fault This bit is set to 1 when an access right violation occurred" "0,1"
bitfld.long 0x00 0. "TF,Translation Fault This bit is set to 1 when a translation fault occurred during a page table walk" "0,1"
group.long 0x15168++0x03
line.long 0x00 "IMMAIR05,(Short-descriptor translation format)"
abitfld.long 0x00 24.--31. "NOS7_0,Outer Shareable property mapping for memory attributes n" "0x00=0: Memory region is outer shareable,0x01=1: Memory region is inner shareable"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 19. "NS1,Mapping of S = 1 attribute for Normal memory" "0: Region is not shareable,1: Region is shareable"
bitfld.long 0x00 18. "NS0,Mapping of S = 0 attribute for Normal memory" "0: Region is not shareable,1: Region is shareable"
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bitfld.long 0x00 17. "DS1,Mapping of S = 1 attribute for Device memory" "0: Region is not shareable,1: Region is shareable"
bitfld.long 0x00 16. "DS0,Mapping of S = 0 attribute for Device memory" "0: Region is not shareable,1: Region is shareable"
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bitfld.long 0x00 14.--15. "TR7_1_0,Primary TEX mapping for memory attributes 7" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
bitfld.long 0x00 12.--13. "TR6_1_0,Primary TEX mapping for memory attributes 6" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
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bitfld.long 0x00 10.--11. "TR5_1_0,Primary TEX mapping for memory attributes 5" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
bitfld.long 0x00 8.--9. "TR4_1_0,Primary TEX mapping for memory attributes 4" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
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bitfld.long 0x00 6.--7. "TR3_1_0,Primary TEX mapping for memory attributes 3" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
bitfld.long 0x00 4.--5. "TR2_1_0,Primary TEX mapping for memory attributes 2" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
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bitfld.long 0x00 2.--3. "TR1_1_0,Primary TEX mapping for memory attributes 1" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
bitfld.long 0x00 0.--1. "TR0_1_0,Primary TEX mapping for memory attributes 0" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
group.long 0x1516C++0x03
line.long 0x00 "IMMAIR15,(Short-descriptor translation format)"
bitfld.long 0x00 30.--31. "OR7_1_0,Outer Cacheable property mapping for memory attributes 7" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 28.--29. "OR6_1_0,Outer Cacheable property mapping for memory attributes 6" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 26.--27. "OR5_1_0,Outer Cacheable property mapping for memory attributes 5" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 24.--25. "OR4_1_0,Outer Cacheable property mapping for memory attributes 4" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 22.--23. "OR3_1_0,Outer Cacheable property mapping for memory attributes 3" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 20.--21. "OR2_1_0,Outer Cacheable property mapping for memory attributes 2" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 18.--19. "OR1_1_0,Outer Cacheable property mapping for memory attributes 1" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 16.--17. "OR0_1_0,Outer Cacheable property mapping for memory attributes 0" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 14.--15. "IR7_1_0,Inner Cacheable property mapping for memory attributes 7" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 12.--13. "IR6_1_0,Inner Cacheable property mapping for memory attributes 6" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 10.--11. "IR5_1_0,Inner Cacheable property mapping for memory attributes 5" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 8.--9. "IR4_1_0,Inner Cacheable property mapping for memory attributes 4" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 6.--7. "IR3_1_0,Inner Cacheable property mapping for memory attributes 3" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 4.--5. "IR2_1_0,Inner Cacheable property mapping for memory attributes 2" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 2.--3. "IR1_1_0,Inner Cacheable property mapping for memory attributes 1" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 0.--1. "IR0_1_0,Inner Cacheable property mapping for memory attributes 0" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
group.long 0x15170++0x03
line.long 0x00 "IMELAR5,Note: n= 0 to 15 (IPMMU context) This register indicates the address which an address translation error occurred"
hexmask.long 0x00 0.--31. 1. "EAR_31_0,The faulting virtual address is set when an address translation error occurred"
group.long 0x15174++0x03
line.long 0x00 "IMEUAR5,Note: n= 0 to 15 (IPMMU context) This register indicates the address which an address translation error occurred"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "EAR_39_32,The faulting virtual address is set when an address translation error occurred"
group.long 0x16180++0x03
line.long 0x00 "IMCTR6,Note: n= 0 to 15 (IPMMU context) This register controls the behavior of the MMU"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved These bits are always read as 0" "0,1,2,3"
bitfld.long 0x00 29. "VA64,AArch64 support" "0: VMSAv8-32 mode This register can be set,1: VMSAv8-64 mode"
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hexmask.long.word 0x00 18.--28. 1. "Reserved_18,Reserved These bits are always read as 0"
bitfld.long 0x00 17. "TRE,TEX Remap Enable This field is used when EAE is 0" "0: TEX remap disabled,1: TEX remap enabled"
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bitfld.long 0x00 16. "AFE,Access Flag Enable" "0: Behave as if AF bit is always set to 1,1: Enable software management of the Access Flag"
rbitfld.long 0x00 15. "SEC,Copy of IMSEC.SEC[n]" "0: Behave as non-secure context,1: Behave as secure context"
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hexmask.long.byte 0x00 8.--14. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 4.--7. "RTSEL_3_0,Retranslation Table Select When TREN is 1 RTSEL indicates the table number to retranslate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 3. "TREN,MMU Retranslation Enable" "0: Output PA as a physical address,1: Output PA as an intermediate physical address.."
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error occurs,1: Assert an interrupt when an error occurs"
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bitfld.long 0x00 1. "FLUSH,TLB Invalidate This bit is automatically cleared to 0" "0,1"
bitfld.long 0x00 0. "MMUEN,MMU Enable" "0: MMU disabled,1: MMU enabled"
group.long 0x16188++0x03
line.long 0x00 "IMTTBCR6,Note: n= 0 to 15 (IPMMU context) This register controls the attribute of TLB managed by each MMU"
bitfld.long 0x00 31. "EAE,Extended Address Enable" "0: Enable the 32-bit translation system with the,1: Enable the 40-bit translation System with the"
bitfld.long 0x00 30. "PMB,[EAE=0] PMB Enable This bit could be set only 0 when EAE=0" "0: not bypass stage 1 translation when stage 2,1: bypass stage 1 translation when only stage 2"
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bitfld.long 0x00 28.--29. "SH1_1_0,Share ability attributes for the memory associated with the translation table walks using TTBR1n" "0: Non-shareable,1: Reserved,2: Outer shareable,3: Inner shareable"
bitfld.long 0x00 26.--27. "ORGN1_1_0,Outer Cache ability attributes for the memory associated with the translation table walks using TTBR1n" "0: Normal memory Outer Non-cacheable,1: Normal memory Outer Write-Back Write-Allocate,2: Normal memory Outer Write-Through Cacheable,3: Normal memory Outer Write-Back no.."
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bitfld.long 0x00 24.--25. "IRGN1_1_0,Inner Cache ability attributes for the memory associated with the translation table walks using TTBR1n" "0: Normal memory Inner Non-cacheable,1: Normal memory Inner Write-Back Write-Allocate,2: Normal memory Inner Write-Through Cacheable,3: Normal memory Inner Write-Back no.."
bitfld.long 0x00 23. "PGSZ,[VMSAv8-32 EAE=0] 2nd level Page Size Select" "0: 4KB page granule (default),1: 64KB page granule"
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bitfld.long 0x00 22. "SCSZ,[VMSAv8-32 EAE=0] 1st level page size select" "0: Support section size (1MB),1: Support super section size (16MB)"
bitfld.long 0x00 16.--21. "TSZ1_5_0,[VMSAv8-64] TSZ1[5:0] is used for the size offset of the TTBR0n addressed region encoded as a 6-bit unsigned number giving the size of the region as 2^(64-TSZ1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 14.--15. "Reserved_14,Reserved These bits are always read as 0" "0,1,2,3"
bitfld.long 0x00 12.--13. "SH0_1_0,Share ability attributes for the memory associated with the translation table walks using TTBR0n" "0: Non-shareable,1: Reserved,2: Outer shareable,3: Inner shareable"
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bitfld.long 0x00 10.--11. "ORGN0_1_0,Outer Cache ability attributes for the memory associated with the translation table walks using TTBR0n" "0: Normal memory Outer Non-cacheable,1: Normal memory Outer Write-Back Write-Allocate,2: Normal memory Outer Write-Through Cacheable,3: Normal memory Outer Write-Back no.."
bitfld.long 0x00 8.--9. "IRGN0_1_0,Inner Cache ability attributes for the memory associated with the translation table walks using TTBR0n" "0: Normal memory Inner Non-cacheable,1: Normal memory Inner Write-Back Write-Allocate,2: Normal memory Inner Write-Through Cacheable,3: Normal memory Inner Write-Back no.."
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bitfld.long 0x00 6.--7. "SL_1_0,Starting level for translation table walks" "0: Start at third level,1: Start at second level,?..."
bitfld.long 0x00 0.--5. "TSZ0_5_0,[VMSAv8-64]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x16190++0x03
line.long 0x00 "IMTTLBR06,Note: n= 0 to 15 (IPMMU context) This register indicates the base address of the TLB managed by each MMU"
hexmask.long.tbyte 0x00 12.--31. 1. "TTBR_31_12,Bits [31:12] of translation table base address"
hexmask.long.word 0x00 0.--11. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x16194++0x03
line.long 0x00 "IMTTUBR06,Note: n= 0 to 15 (IPMMU context) This register indicates the base address of the TLB managed by each MMU"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "TTBR_39_32,Bits [39:32] of translation table base address This field is used when EAE is 1"
group.long 0x16198++0x03
line.long 0x00 "IMTTLBR16,Note: n= 0 to 15 (IPMMU context) This register indicates the base address of the TLB managed by each MMU"
hexmask.long.tbyte 0x00 12.--31. 1. "TTBR_31_12,Bits [31:12] of translation table base address"
hexmask.long.word 0x00 0.--11. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x1619C++0x03
line.long 0x00 "IMTTUBR16,Note: n= 0 to 15 (IPMMU context) This register indicates the base address of the TLB managed by each MMU"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "TTBR_39_32,Bits [39:32] of translation table base address This field is used when EAE is 1"
group.long 0x161A0++0x03
line.long 0x00 "IMSTR6,Note: n= 0 to 15 (IPMMU context) This register indicates the error status of during address translation"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are always read as 0"
bitfld.long 0x00 12.--13. "ERRLVL_1_0,indicate which level of page table walk caused the error" "0: Level1 page table walk,1: Level2 page table walk,2: Level3 page table walk,?..."
newline
rbitfld.long 0x00 11. "Reserved_11,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 8.--10. "ERRCODE_2_0,Indicate error type" "?,1: Translation Fault,?,?,4: Access Flag Fault / Permission Fault,5: Secure Access Fault Others: reserved,?..."
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rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4. "MHIT,TLB Conflict Fault Indicate that multiple TLB hits occurred" "0,1"
newline
rbitfld.long 0x00 3. "Reserved_3,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 2. "ABORT,This bit is set to 1 when the IPMMU received an error response during a page table walk" "0,1"
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bitfld.long 0x00 1. "PF,Permission Fault This bit is set to 1 when an access right violation occurred" "0,1"
bitfld.long 0x00 0. "TF,Translation Fault This bit is set to 1 when a translation fault occurred during a page table walk" "0,1"
group.long 0x161A8++0x03
line.long 0x00 "IMMAIR06,(Short-descriptor translation format)"
abitfld.long 0x00 24.--31. "NOS7_0,Outer Shareable property mapping for memory attributes n" "0x00=0: Memory region is outer shareable,0x01=1: Memory region is inner shareable"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 19. "NS1,Mapping of S = 1 attribute for Normal memory" "0: Region is not shareable,1: Region is shareable"
bitfld.long 0x00 18. "NS0,Mapping of S = 0 attribute for Normal memory" "0: Region is not shareable,1: Region is shareable"
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bitfld.long 0x00 17. "DS1,Mapping of S = 1 attribute for Device memory" "0: Region is not shareable,1: Region is shareable"
bitfld.long 0x00 16. "DS0,Mapping of S = 0 attribute for Device memory" "0: Region is not shareable,1: Region is shareable"
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bitfld.long 0x00 14.--15. "TR7_1_0,Primary TEX mapping for memory attributes 7" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
bitfld.long 0x00 12.--13. "TR6_1_0,Primary TEX mapping for memory attributes 6" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
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bitfld.long 0x00 10.--11. "TR5_1_0,Primary TEX mapping for memory attributes 5" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
bitfld.long 0x00 8.--9. "TR4_1_0,Primary TEX mapping for memory attributes 4" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
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bitfld.long 0x00 6.--7. "TR3_1_0,Primary TEX mapping for memory attributes 3" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
bitfld.long 0x00 4.--5. "TR2_1_0,Primary TEX mapping for memory attributes 2" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
newline
bitfld.long 0x00 2.--3. "TR1_1_0,Primary TEX mapping for memory attributes 1" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
bitfld.long 0x00 0.--1. "TR0_1_0,Primary TEX mapping for memory attributes 0" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
group.long 0x161AC++0x03
line.long 0x00 "IMMAIR16,(Short-descriptor translation format)"
bitfld.long 0x00 30.--31. "OR7_1_0,Outer Cacheable property mapping for memory attributes 7" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 28.--29. "OR6_1_0,Outer Cacheable property mapping for memory attributes 6" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
newline
bitfld.long 0x00 26.--27. "OR5_1_0,Outer Cacheable property mapping for memory attributes 5" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 24.--25. "OR4_1_0,Outer Cacheable property mapping for memory attributes 4" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 22.--23. "OR3_1_0,Outer Cacheable property mapping for memory attributes 3" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 20.--21. "OR2_1_0,Outer Cacheable property mapping for memory attributes 2" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 18.--19. "OR1_1_0,Outer Cacheable property mapping for memory attributes 1" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 16.--17. "OR0_1_0,Outer Cacheable property mapping for memory attributes 0" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 14.--15. "IR7_1_0,Inner Cacheable property mapping for memory attributes 7" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 12.--13. "IR6_1_0,Inner Cacheable property mapping for memory attributes 6" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 10.--11. "IR5_1_0,Inner Cacheable property mapping for memory attributes 5" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 8.--9. "IR4_1_0,Inner Cacheable property mapping for memory attributes 4" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 6.--7. "IR3_1_0,Inner Cacheable property mapping for memory attributes 3" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 4.--5. "IR2_1_0,Inner Cacheable property mapping for memory attributes 2" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 2.--3. "IR1_1_0,Inner Cacheable property mapping for memory attributes 1" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 0.--1. "IR0_1_0,Inner Cacheable property mapping for memory attributes 0" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
group.long 0x161B0++0x03
line.long 0x00 "IMELAR6,Note: n= 0 to 15 (IPMMU context) This register indicates the address which an address translation error occurred"
hexmask.long 0x00 0.--31. 1. "EAR_31_0,The faulting virtual address is set when an address translation error occurred"
group.long 0x161B4++0x03
line.long 0x00 "IMEUAR6,Note: n= 0 to 15 (IPMMU context) This register indicates the address which an address translation error occurred"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "EAR_39_32,The faulting virtual address is set when an address translation error occurred"
group.long 0x171C0++0x03
line.long 0x00 "IMCTR7,Note: n= 0 to 15 (IPMMU context) This register controls the behavior of the MMU"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved These bits are always read as 0" "0,1,2,3"
bitfld.long 0x00 29. "VA64,AArch64 support" "0: VMSAv8-32 mode This register can be set,1: VMSAv8-64 mode"
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hexmask.long.word 0x00 18.--28. 1. "Reserved_18,Reserved These bits are always read as 0"
bitfld.long 0x00 17. "TRE,TEX Remap Enable This field is used when EAE is 0" "0: TEX remap disabled,1: TEX remap enabled"
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bitfld.long 0x00 16. "AFE,Access Flag Enable" "0: Behave as if AF bit is always set to 1,1: Enable software management of the Access Flag"
rbitfld.long 0x00 15. "SEC,Copy of IMSEC.SEC[n]" "0: Behave as non-secure context,1: Behave as secure context"
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hexmask.long.byte 0x00 8.--14. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 4.--7. "RTSEL_3_0,Retranslation Table Select When TREN is 1 RTSEL indicates the table number to retranslate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 3. "TREN,MMU Retranslation Enable" "0: Output PA as a physical address,1: Output PA as an intermediate physical address.."
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error occurs,1: Assert an interrupt when an error occurs"
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bitfld.long 0x00 1. "FLUSH,TLB Invalidate This bit is automatically cleared to 0" "0,1"
bitfld.long 0x00 0. "MMUEN,MMU Enable" "0: MMU disabled,1: MMU enabled"
group.long 0x171C8++0x03
line.long 0x00 "IMTTBCR7,Note: n= 0 to 15 (IPMMU context) This register controls the attribute of TLB managed by each MMU"
bitfld.long 0x00 31. "EAE,Extended Address Enable" "0: Enable the 32-bit translation system with the,1: Enable the 40-bit translation System with the"
bitfld.long 0x00 30. "PMB,[EAE=0] PMB Enable This bit could be set only 0 when EAE=0" "0: not bypass stage 1 translation when stage 2,1: bypass stage 1 translation when only stage 2"
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bitfld.long 0x00 28.--29. "SH1_1_0,Share ability attributes for the memory associated with the translation table walks using TTBR1n" "0: Non-shareable,1: Reserved,2: Outer shareable,3: Inner shareable"
bitfld.long 0x00 26.--27. "ORGN1_1_0,Outer Cache ability attributes for the memory associated with the translation table walks using TTBR1n" "0: Normal memory Outer Non-cacheable,1: Normal memory Outer Write-Back Write-Allocate,2: Normal memory Outer Write-Through Cacheable,3: Normal memory Outer Write-Back no.."
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bitfld.long 0x00 24.--25. "IRGN1_1_0,Inner Cache ability attributes for the memory associated with the translation table walks using TTBR1n" "0: Normal memory Inner Non-cacheable,1: Normal memory Inner Write-Back Write-Allocate,2: Normal memory Inner Write-Through Cacheable,3: Normal memory Inner Write-Back no.."
bitfld.long 0x00 23. "PGSZ,[VMSAv8-32 EAE=0] 2nd level Page Size Select" "0: 4KB page granule (default),1: 64KB page granule"
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bitfld.long 0x00 22. "SCSZ,[VMSAv8-32 EAE=0] 1st level page size select" "0: Support section size (1MB),1: Support super section size (16MB)"
bitfld.long 0x00 16.--21. "TSZ1_5_0,[VMSAv8-64] TSZ1[5:0] is used for the size offset of the TTBR0n addressed region encoded as a 6-bit unsigned number giving the size of the region as 2^(64-TSZ1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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rbitfld.long 0x00 14.--15. "Reserved_14,Reserved These bits are always read as 0" "0,1,2,3"
bitfld.long 0x00 12.--13. "SH0_1_0,Share ability attributes for the memory associated with the translation table walks using TTBR0n" "0: Non-shareable,1: Reserved,2: Outer shareable,3: Inner shareable"
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bitfld.long 0x00 10.--11. "ORGN0_1_0,Outer Cache ability attributes for the memory associated with the translation table walks using TTBR0n" "0: Normal memory Outer Non-cacheable,1: Normal memory Outer Write-Back Write-Allocate,2: Normal memory Outer Write-Through Cacheable,3: Normal memory Outer Write-Back no.."
bitfld.long 0x00 8.--9. "IRGN0_1_0,Inner Cache ability attributes for the memory associated with the translation table walks using TTBR0n" "0: Normal memory Inner Non-cacheable,1: Normal memory Inner Write-Back Write-Allocate,2: Normal memory Inner Write-Through Cacheable,3: Normal memory Inner Write-Back no.."
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bitfld.long 0x00 6.--7. "SL_1_0,Starting level for translation table walks" "0: Start at third level,1: Start at second level,?..."
bitfld.long 0x00 0.--5. "TSZ0_5_0,[VMSAv8-64]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x171D0++0x03
line.long 0x00 "IMTTLBR07,Note: n= 0 to 15 (IPMMU context) This register indicates the base address of the TLB managed by each MMU"
hexmask.long.tbyte 0x00 12.--31. 1. "TTBR_31_12,Bits [31:12] of translation table base address"
hexmask.long.word 0x00 0.--11. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x171D4++0x03
line.long 0x00 "IMTTUBR07,Note: n= 0 to 15 (IPMMU context) This register indicates the base address of the TLB managed by each MMU"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "TTBR_39_32,Bits [39:32] of translation table base address This field is used when EAE is 1"
group.long 0x171D8++0x03
line.long 0x00 "IMTTLBR17,Note: n= 0 to 15 (IPMMU context) This register indicates the base address of the TLB managed by each MMU"
hexmask.long.tbyte 0x00 12.--31. 1. "TTBR_31_12,Bits [31:12] of translation table base address"
hexmask.long.word 0x00 0.--11. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x171DC++0x03
line.long 0x00 "IMTTUBR17,Note: n= 0 to 15 (IPMMU context) This register indicates the base address of the TLB managed by each MMU"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "TTBR_39_32,Bits [39:32] of translation table base address This field is used when EAE is 1"
group.long 0x171E0++0x03
line.long 0x00 "IMSTR7,Note: n= 0 to 15 (IPMMU context) This register indicates the error status of during address translation"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are always read as 0"
bitfld.long 0x00 12.--13. "ERRLVL_1_0,indicate which level of page table walk caused the error" "0: Level1 page table walk,1: Level2 page table walk,2: Level3 page table walk,?..."
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rbitfld.long 0x00 11. "Reserved_11,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 8.--10. "ERRCODE_2_0,Indicate error type" "?,1: Translation Fault,?,?,4: Access Flag Fault / Permission Fault,5: Secure Access Fault Others: reserved,?..."
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rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4. "MHIT,TLB Conflict Fault Indicate that multiple TLB hits occurred" "0,1"
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rbitfld.long 0x00 3. "Reserved_3,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 2. "ABORT,This bit is set to 1 when the IPMMU received an error response during a page table walk" "0,1"
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bitfld.long 0x00 1. "PF,Permission Fault This bit is set to 1 when an access right violation occurred" "0,1"
bitfld.long 0x00 0. "TF,Translation Fault This bit is set to 1 when a translation fault occurred during a page table walk" "0,1"
group.long 0x171E8++0x03
line.long 0x00 "IMMAIR07,(Short-descriptor translation format)"
abitfld.long 0x00 24.--31. "NOS7_0,Outer Shareable property mapping for memory attributes n" "0x00=0: Memory region is outer shareable,0x01=1: Memory region is inner shareable"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 19. "NS1,Mapping of S = 1 attribute for Normal memory" "0: Region is not shareable,1: Region is shareable"
bitfld.long 0x00 18. "NS0,Mapping of S = 0 attribute for Normal memory" "0: Region is not shareable,1: Region is shareable"
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bitfld.long 0x00 17. "DS1,Mapping of S = 1 attribute for Device memory" "0: Region is not shareable,1: Region is shareable"
bitfld.long 0x00 16. "DS0,Mapping of S = 0 attribute for Device memory" "0: Region is not shareable,1: Region is shareable"
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bitfld.long 0x00 14.--15. "TR7_1_0,Primary TEX mapping for memory attributes 7" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
bitfld.long 0x00 12.--13. "TR6_1_0,Primary TEX mapping for memory attributes 6" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
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bitfld.long 0x00 10.--11. "TR5_1_0,Primary TEX mapping for memory attributes 5" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
bitfld.long 0x00 8.--9. "TR4_1_0,Primary TEX mapping for memory attributes 4" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
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bitfld.long 0x00 6.--7. "TR3_1_0,Primary TEX mapping for memory attributes 3" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
bitfld.long 0x00 4.--5. "TR2_1_0,Primary TEX mapping for memory attributes 2" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
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bitfld.long 0x00 2.--3. "TR1_1_0,Primary TEX mapping for memory attributes 1" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
bitfld.long 0x00 0.--1. "TR0_1_0,Primary TEX mapping for memory attributes 0" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
group.long 0x171EC++0x03
line.long 0x00 "IMMAIR17,(Short-descriptor translation format)"
bitfld.long 0x00 30.--31. "OR7_1_0,Outer Cacheable property mapping for memory attributes 7" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 28.--29. "OR6_1_0,Outer Cacheable property mapping for memory attributes 6" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 26.--27. "OR5_1_0,Outer Cacheable property mapping for memory attributes 5" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 24.--25. "OR4_1_0,Outer Cacheable property mapping for memory attributes 4" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 22.--23. "OR3_1_0,Outer Cacheable property mapping for memory attributes 3" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 20.--21. "OR2_1_0,Outer Cacheable property mapping for memory attributes 2" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 18.--19. "OR1_1_0,Outer Cacheable property mapping for memory attributes 1" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 16.--17. "OR0_1_0,Outer Cacheable property mapping for memory attributes 0" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 14.--15. "IR7_1_0,Inner Cacheable property mapping for memory attributes 7" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 12.--13. "IR6_1_0,Inner Cacheable property mapping for memory attributes 6" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 10.--11. "IR5_1_0,Inner Cacheable property mapping for memory attributes 5" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 8.--9. "IR4_1_0,Inner Cacheable property mapping for memory attributes 4" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 6.--7. "IR3_1_0,Inner Cacheable property mapping for memory attributes 3" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 4.--5. "IR2_1_0,Inner Cacheable property mapping for memory attributes 2" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 2.--3. "IR1_1_0,Inner Cacheable property mapping for memory attributes 1" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 0.--1. "IR0_1_0,Inner Cacheable property mapping for memory attributes 0" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
group.long 0x171F0++0x03
line.long 0x00 "IMELAR7,Note: n= 0 to 15 (IPMMU context) This register indicates the address which an address translation error occurred"
hexmask.long 0x00 0.--31. 1. "EAR_31_0,The faulting virtual address is set when an address translation error occurred"
group.long 0x171F4++0x03
line.long 0x00 "IMEUAR7,Note: n= 0 to 15 (IPMMU context) This register indicates the address which an address translation error occurred"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "EAR_39_32,The faulting virtual address is set when an address translation error occurred"
group.long 0x18800++0x03
line.long 0x00 "IMCTR8,Note: n= 0 to 15 (IPMMU context) This register controls the behavior of the MMU"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved These bits are always read as 0" "0,1,2,3"
bitfld.long 0x00 29. "VA64,AArch64 support" "0: VMSAv8-32 mode This register can be set,1: VMSAv8-64 mode"
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hexmask.long.word 0x00 18.--28. 1. "Reserved_18,Reserved These bits are always read as 0"
bitfld.long 0x00 17. "TRE,TEX Remap Enable This field is used when EAE is 0" "0: TEX remap disabled,1: TEX remap enabled"
newline
bitfld.long 0x00 16. "AFE,Access Flag Enable" "0: Behave as if AF bit is always set to 1,1: Enable software management of the Access Flag"
rbitfld.long 0x00 15. "SEC,Copy of IMSEC.SEC[n]" "0: Behave as non-secure context,1: Behave as secure context"
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hexmask.long.byte 0x00 8.--14. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 4.--7. "RTSEL_3_0,Retranslation Table Select When TREN is 1 RTSEL indicates the table number to retranslate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 3. "TREN,MMU Retranslation Enable" "0: Output PA as a physical address,1: Output PA as an intermediate physical address.."
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error occurs,1: Assert an interrupt when an error occurs"
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bitfld.long 0x00 1. "FLUSH,TLB Invalidate This bit is automatically cleared to 0" "0,1"
bitfld.long 0x00 0. "MMUEN,MMU Enable" "0: MMU disabled,1: MMU enabled"
group.long 0x18808++0x03
line.long 0x00 "IMTTBCR8,Note: n= 0 to 15 (IPMMU context) This register controls the attribute of TLB managed by each MMU"
bitfld.long 0x00 31. "EAE,Extended Address Enable" "0: Enable the 32-bit translation system with the,1: Enable the 40-bit translation System with the"
bitfld.long 0x00 30. "PMB,[EAE=0] PMB Enable This bit could be set only 0 when EAE=0" "0: not bypass stage 1 translation when stage 2,1: bypass stage 1 translation when only stage 2"
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bitfld.long 0x00 28.--29. "SH1_1_0,Share ability attributes for the memory associated with the translation table walks using TTBR1n" "0: Non-shareable,1: Reserved,2: Outer shareable,3: Inner shareable"
bitfld.long 0x00 26.--27. "ORGN1_1_0,Outer Cache ability attributes for the memory associated with the translation table walks using TTBR1n" "0: Normal memory Outer Non-cacheable,1: Normal memory Outer Write-Back Write-Allocate,2: Normal memory Outer Write-Through Cacheable,3: Normal memory Outer Write-Back no.."
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bitfld.long 0x00 24.--25. "IRGN1_1_0,Inner Cache ability attributes for the memory associated with the translation table walks using TTBR1n" "0: Normal memory Inner Non-cacheable,1: Normal memory Inner Write-Back Write-Allocate,2: Normal memory Inner Write-Through Cacheable,3: Normal memory Inner Write-Back no.."
bitfld.long 0x00 23. "PGSZ,[VMSAv8-32 EAE=0] 2nd level Page Size Select" "0: 4KB page granule (default),1: 64KB page granule"
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bitfld.long 0x00 22. "SCSZ,[VMSAv8-32 EAE=0] 1st level page size select" "0: Support section size (1MB),1: Support super section size (16MB)"
bitfld.long 0x00 16.--21. "TSZ1_5_0,[VMSAv8-64] TSZ1[5:0] is used for the size offset of the TTBR0n addressed region encoded as a 6-bit unsigned number giving the size of the region as 2^(64-TSZ1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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rbitfld.long 0x00 14.--15. "Reserved_14,Reserved These bits are always read as 0" "0,1,2,3"
bitfld.long 0x00 12.--13. "SH0_1_0,Share ability attributes for the memory associated with the translation table walks using TTBR0n" "0: Non-shareable,1: Reserved,2: Outer shareable,3: Inner shareable"
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bitfld.long 0x00 10.--11. "ORGN0_1_0,Outer Cache ability attributes for the memory associated with the translation table walks using TTBR0n" "0: Normal memory Outer Non-cacheable,1: Normal memory Outer Write-Back Write-Allocate,2: Normal memory Outer Write-Through Cacheable,3: Normal memory Outer Write-Back no.."
bitfld.long 0x00 8.--9. "IRGN0_1_0,Inner Cache ability attributes for the memory associated with the translation table walks using TTBR0n" "0: Normal memory Inner Non-cacheable,1: Normal memory Inner Write-Back Write-Allocate,2: Normal memory Inner Write-Through Cacheable,3: Normal memory Inner Write-Back no.."
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bitfld.long 0x00 6.--7. "SL_1_0,Starting level for translation table walks" "0: Start at third level,1: Start at second level,?..."
bitfld.long 0x00 0.--5. "TSZ0_5_0,[VMSAv8-64]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x18810++0x03
line.long 0x00 "IMTTLBR08,Note: n= 0 to 15 (IPMMU context) This register indicates the base address of the TLB managed by each MMU"
hexmask.long.tbyte 0x00 12.--31. 1. "TTBR_31_12,Bits [31:12] of translation table base address"
hexmask.long.word 0x00 0.--11. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x18814++0x03
line.long 0x00 "IMTTUBR08,Note: n= 0 to 15 (IPMMU context) This register indicates the base address of the TLB managed by each MMU"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "TTBR_39_32,Bits [39:32] of translation table base address This field is used when EAE is 1"
group.long 0x18818++0x03
line.long 0x00 "IMTTLBR18,Note: n= 0 to 15 (IPMMU context) This register indicates the base address of the TLB managed by each MMU"
hexmask.long.tbyte 0x00 12.--31. 1. "TTBR_31_12,Bits [31:12] of translation table base address"
hexmask.long.word 0x00 0.--11. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x1881C++0x03
line.long 0x00 "IMTTUBR18,Note: n= 0 to 15 (IPMMU context) This register indicates the base address of the TLB managed by each MMU"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "TTBR_39_32,Bits [39:32] of translation table base address This field is used when EAE is 1"
group.long 0x18820++0x03
line.long 0x00 "IMSTR8,Note: n= 0 to 15 (IPMMU context) This register indicates the error status of during address translation"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are always read as 0"
bitfld.long 0x00 12.--13. "ERRLVL_1_0,indicate which level of page table walk caused the error" "0: Level1 page table walk,1: Level2 page table walk,2: Level3 page table walk,?..."
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rbitfld.long 0x00 11. "Reserved_11,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 8.--10. "ERRCODE_2_0,Indicate error type" "?,1: Translation Fault,?,?,4: Access Flag Fault / Permission Fault,5: Secure Access Fault Others: reserved,?..."
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rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4. "MHIT,TLB Conflict Fault Indicate that multiple TLB hits occurred" "0,1"
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rbitfld.long 0x00 3. "Reserved_3,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 2. "ABORT,This bit is set to 1 when the IPMMU received an error response during a page table walk" "0,1"
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bitfld.long 0x00 1. "PF,Permission Fault This bit is set to 1 when an access right violation occurred" "0,1"
bitfld.long 0x00 0. "TF,Translation Fault This bit is set to 1 when a translation fault occurred during a page table walk" "0,1"
group.long 0x18828++0x03
line.long 0x00 "IMMAIR08,(Short-descriptor translation format)"
abitfld.long 0x00 24.--31. "NOS7_0,Outer Shareable property mapping for memory attributes n" "0x00=0: Memory region is outer shareable,0x01=1: Memory region is inner shareable"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 19. "NS1,Mapping of S = 1 attribute for Normal memory" "0: Region is not shareable,1: Region is shareable"
bitfld.long 0x00 18. "NS0,Mapping of S = 0 attribute for Normal memory" "0: Region is not shareable,1: Region is shareable"
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bitfld.long 0x00 17. "DS1,Mapping of S = 1 attribute for Device memory" "0: Region is not shareable,1: Region is shareable"
bitfld.long 0x00 16. "DS0,Mapping of S = 0 attribute for Device memory" "0: Region is not shareable,1: Region is shareable"
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bitfld.long 0x00 14.--15. "TR7_1_0,Primary TEX mapping for memory attributes 7" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
bitfld.long 0x00 12.--13. "TR6_1_0,Primary TEX mapping for memory attributes 6" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
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bitfld.long 0x00 10.--11. "TR5_1_0,Primary TEX mapping for memory attributes 5" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
bitfld.long 0x00 8.--9. "TR4_1_0,Primary TEX mapping for memory attributes 4" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
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bitfld.long 0x00 6.--7. "TR3_1_0,Primary TEX mapping for memory attributes 3" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
bitfld.long 0x00 4.--5. "TR2_1_0,Primary TEX mapping for memory attributes 2" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
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bitfld.long 0x00 2.--3. "TR1_1_0,Primary TEX mapping for memory attributes 1" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
bitfld.long 0x00 0.--1. "TR0_1_0,Primary TEX mapping for memory attributes 0" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
group.long 0x1882C++0x03
line.long 0x00 "IMMAIR18,(Short-descriptor translation format)"
bitfld.long 0x00 30.--31. "OR7_1_0,Outer Cacheable property mapping for memory attributes 7" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 28.--29. "OR6_1_0,Outer Cacheable property mapping for memory attributes 6" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 26.--27. "OR5_1_0,Outer Cacheable property mapping for memory attributes 5" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 24.--25. "OR4_1_0,Outer Cacheable property mapping for memory attributes 4" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 22.--23. "OR3_1_0,Outer Cacheable property mapping for memory attributes 3" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 20.--21. "OR2_1_0,Outer Cacheable property mapping for memory attributes 2" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 18.--19. "OR1_1_0,Outer Cacheable property mapping for memory attributes 1" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 16.--17. "OR0_1_0,Outer Cacheable property mapping for memory attributes 0" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 14.--15. "IR7_1_0,Inner Cacheable property mapping for memory attributes 7" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 12.--13. "IR6_1_0,Inner Cacheable property mapping for memory attributes 6" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 10.--11. "IR5_1_0,Inner Cacheable property mapping for memory attributes 5" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 8.--9. "IR4_1_0,Inner Cacheable property mapping for memory attributes 4" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 6.--7. "IR3_1_0,Inner Cacheable property mapping for memory attributes 3" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 4.--5. "IR2_1_0,Inner Cacheable property mapping for memory attributes 2" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 2.--3. "IR1_1_0,Inner Cacheable property mapping for memory attributes 1" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 0.--1. "IR0_1_0,Inner Cacheable property mapping for memory attributes 0" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
group.long 0x18830++0x03
line.long 0x00 "IMELAR8,Note: n= 0 to 15 (IPMMU context) This register indicates the address which an address translation error occurred"
hexmask.long 0x00 0.--31. 1. "EAR_31_0,The faulting virtual address is set when an address translation error occurred"
group.long 0x18834++0x03
line.long 0x00 "IMEUAR8,Note: n= 0 to 15 (IPMMU context) This register indicates the address which an address translation error occurred"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "EAR_39_32,The faulting virtual address is set when an address translation error occurred"
group.long 0x19840++0x03
line.long 0x00 "IMCTR9,Note: n= 0 to 15 (IPMMU context) This register controls the behavior of the MMU"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved These bits are always read as 0" "0,1,2,3"
bitfld.long 0x00 29. "VA64,AArch64 support" "0: VMSAv8-32 mode This register can be set,1: VMSAv8-64 mode"
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hexmask.long.word 0x00 18.--28. 1. "Reserved_18,Reserved These bits are always read as 0"
bitfld.long 0x00 17. "TRE,TEX Remap Enable This field is used when EAE is 0" "0: TEX remap disabled,1: TEX remap enabled"
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bitfld.long 0x00 16. "AFE,Access Flag Enable" "0: Behave as if AF bit is always set to 1,1: Enable software management of the Access Flag"
rbitfld.long 0x00 15. "SEC,Copy of IMSEC.SEC[n]" "0: Behave as non-secure context,1: Behave as secure context"
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hexmask.long.byte 0x00 8.--14. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 4.--7. "RTSEL_3_0,Retranslation Table Select When TREN is 1 RTSEL indicates the table number to retranslate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 3. "TREN,MMU Retranslation Enable" "0: Output PA as a physical address,1: Output PA as an intermediate physical address.."
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error occurs,1: Assert an interrupt when an error occurs"
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bitfld.long 0x00 1. "FLUSH,TLB Invalidate This bit is automatically cleared to 0" "0,1"
bitfld.long 0x00 0. "MMUEN,MMU Enable" "0: MMU disabled,1: MMU enabled"
group.long 0x19848++0x03
line.long 0x00 "IMTTBCR9,Note: n= 0 to 15 (IPMMU context) This register controls the attribute of TLB managed by each MMU"
bitfld.long 0x00 31. "EAE,Extended Address Enable" "0: Enable the 32-bit translation system with the,1: Enable the 40-bit translation System with the"
bitfld.long 0x00 30. "PMB,[EAE=0] PMB Enable This bit could be set only 0 when EAE=0" "0: not bypass stage 1 translation when stage 2,1: bypass stage 1 translation when only stage 2"
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bitfld.long 0x00 28.--29. "SH1_1_0,Share ability attributes for the memory associated with the translation table walks using TTBR1n" "0: Non-shareable,1: Reserved,2: Outer shareable,3: Inner shareable"
bitfld.long 0x00 26.--27. "ORGN1_1_0,Outer Cache ability attributes for the memory associated with the translation table walks using TTBR1n" "0: Normal memory Outer Non-cacheable,1: Normal memory Outer Write-Back Write-Allocate,2: Normal memory Outer Write-Through Cacheable,3: Normal memory Outer Write-Back no.."
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bitfld.long 0x00 24.--25. "IRGN1_1_0,Inner Cache ability attributes for the memory associated with the translation table walks using TTBR1n" "0: Normal memory Inner Non-cacheable,1: Normal memory Inner Write-Back Write-Allocate,2: Normal memory Inner Write-Through Cacheable,3: Normal memory Inner Write-Back no.."
bitfld.long 0x00 23. "PGSZ,[VMSAv8-32 EAE=0] 2nd level Page Size Select" "0: 4KB page granule (default),1: 64KB page granule"
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bitfld.long 0x00 22. "SCSZ,[VMSAv8-32 EAE=0] 1st level page size select" "0: Support section size (1MB),1: Support super section size (16MB)"
bitfld.long 0x00 16.--21. "TSZ1_5_0,[VMSAv8-64] TSZ1[5:0] is used for the size offset of the TTBR0n addressed region encoded as a 6-bit unsigned number giving the size of the region as 2^(64-TSZ1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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rbitfld.long 0x00 14.--15. "Reserved_14,Reserved These bits are always read as 0" "0,1,2,3"
bitfld.long 0x00 12.--13. "SH0_1_0,Share ability attributes for the memory associated with the translation table walks using TTBR0n" "0: Non-shareable,1: Reserved,2: Outer shareable,3: Inner shareable"
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bitfld.long 0x00 10.--11. "ORGN0_1_0,Outer Cache ability attributes for the memory associated with the translation table walks using TTBR0n" "0: Normal memory Outer Non-cacheable,1: Normal memory Outer Write-Back Write-Allocate,2: Normal memory Outer Write-Through Cacheable,3: Normal memory Outer Write-Back no.."
bitfld.long 0x00 8.--9. "IRGN0_1_0,Inner Cache ability attributes for the memory associated with the translation table walks using TTBR0n" "0: Normal memory Inner Non-cacheable,1: Normal memory Inner Write-Back Write-Allocate,2: Normal memory Inner Write-Through Cacheable,3: Normal memory Inner Write-Back no.."
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bitfld.long 0x00 6.--7. "SL_1_0,Starting level for translation table walks" "0: Start at third level,1: Start at second level,?..."
bitfld.long 0x00 0.--5. "TSZ0_5_0,[VMSAv8-64]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x19850++0x03
line.long 0x00 "IMTTLBR09,Note: n= 0 to 15 (IPMMU context) This register indicates the base address of the TLB managed by each MMU"
hexmask.long.tbyte 0x00 12.--31. 1. "TTBR_31_12,Bits [31:12] of translation table base address"
hexmask.long.word 0x00 0.--11. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x19854++0x03
line.long 0x00 "IMTTUBR09,Note: n= 0 to 15 (IPMMU context) This register indicates the base address of the TLB managed by each MMU"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "TTBR_39_32,Bits [39:32] of translation table base address This field is used when EAE is 1"
group.long 0x19858++0x03
line.long 0x00 "IMTTLBR19,Note: n= 0 to 15 (IPMMU context) This register indicates the base address of the TLB managed by each MMU"
hexmask.long.tbyte 0x00 12.--31. 1. "TTBR_31_12,Bits [31:12] of translation table base address"
hexmask.long.word 0x00 0.--11. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x1985C++0x03
line.long 0x00 "IMTTUBR19,Note: n= 0 to 15 (IPMMU context) This register indicates the base address of the TLB managed by each MMU"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "TTBR_39_32,Bits [39:32] of translation table base address This field is used when EAE is 1"
group.long 0x19860++0x03
line.long 0x00 "IMSTR9,Note: n= 0 to 15 (IPMMU context) This register indicates the error status of during address translation"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are always read as 0"
bitfld.long 0x00 12.--13. "ERRLVL_1_0,indicate which level of page table walk caused the error" "0: Level1 page table walk,1: Level2 page table walk,2: Level3 page table walk,?..."
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rbitfld.long 0x00 11. "Reserved_11,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 8.--10. "ERRCODE_2_0,Indicate error type" "?,1: Translation Fault,?,?,4: Access Flag Fault / Permission Fault,5: Secure Access Fault Others: reserved,?..."
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4. "MHIT,TLB Conflict Fault Indicate that multiple TLB hits occurred" "0,1"
newline
rbitfld.long 0x00 3. "Reserved_3,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 2. "ABORT,This bit is set to 1 when the IPMMU received an error response during a page table walk" "0,1"
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bitfld.long 0x00 1. "PF,Permission Fault This bit is set to 1 when an access right violation occurred" "0,1"
bitfld.long 0x00 0. "TF,Translation Fault This bit is set to 1 when a translation fault occurred during a page table walk" "0,1"
group.long 0x19868++0x03
line.long 0x00 "IMMAIR09,(Short-descriptor translation format)"
abitfld.long 0x00 24.--31. "NOS7_0,Outer Shareable property mapping for memory attributes n" "0x00=0: Memory region is outer shareable,0x01=1: Memory region is inner shareable"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 19. "NS1,Mapping of S = 1 attribute for Normal memory" "0: Region is not shareable,1: Region is shareable"
bitfld.long 0x00 18. "NS0,Mapping of S = 0 attribute for Normal memory" "0: Region is not shareable,1: Region is shareable"
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bitfld.long 0x00 17. "DS1,Mapping of S = 1 attribute for Device memory" "0: Region is not shareable,1: Region is shareable"
bitfld.long 0x00 16. "DS0,Mapping of S = 0 attribute for Device memory" "0: Region is not shareable,1: Region is shareable"
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bitfld.long 0x00 14.--15. "TR7_1_0,Primary TEX mapping for memory attributes 7" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
bitfld.long 0x00 12.--13. "TR6_1_0,Primary TEX mapping for memory attributes 6" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
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bitfld.long 0x00 10.--11. "TR5_1_0,Primary TEX mapping for memory attributes 5" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
bitfld.long 0x00 8.--9. "TR4_1_0,Primary TEX mapping for memory attributes 4" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
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bitfld.long 0x00 6.--7. "TR3_1_0,Primary TEX mapping for memory attributes 3" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
bitfld.long 0x00 4.--5. "TR2_1_0,Primary TEX mapping for memory attributes 2" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
newline
bitfld.long 0x00 2.--3. "TR1_1_0,Primary TEX mapping for memory attributes 1" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
bitfld.long 0x00 0.--1. "TR0_1_0,Primary TEX mapping for memory attributes 0" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
group.long 0x1986C++0x03
line.long 0x00 "IMMAIR19,(Short-descriptor translation format)"
bitfld.long 0x00 30.--31. "OR7_1_0,Outer Cacheable property mapping for memory attributes 7" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 28.--29. "OR6_1_0,Outer Cacheable property mapping for memory attributes 6" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
newline
bitfld.long 0x00 26.--27. "OR5_1_0,Outer Cacheable property mapping for memory attributes 5" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 24.--25. "OR4_1_0,Outer Cacheable property mapping for memory attributes 4" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 22.--23. "OR3_1_0,Outer Cacheable property mapping for memory attributes 3" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 20.--21. "OR2_1_0,Outer Cacheable property mapping for memory attributes 2" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
newline
bitfld.long 0x00 18.--19. "OR1_1_0,Outer Cacheable property mapping for memory attributes 1" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 16.--17. "OR0_1_0,Outer Cacheable property mapping for memory attributes 0" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
newline
bitfld.long 0x00 14.--15. "IR7_1_0,Inner Cacheable property mapping for memory attributes 7" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 12.--13. "IR6_1_0,Inner Cacheable property mapping for memory attributes 6" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
newline
bitfld.long 0x00 10.--11. "IR5_1_0,Inner Cacheable property mapping for memory attributes 5" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 8.--9. "IR4_1_0,Inner Cacheable property mapping for memory attributes 4" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
newline
bitfld.long 0x00 6.--7. "IR3_1_0,Inner Cacheable property mapping for memory attributes 3" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 4.--5. "IR2_1_0,Inner Cacheable property mapping for memory attributes 2" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 2.--3. "IR1_1_0,Inner Cacheable property mapping for memory attributes 1" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 0.--1. "IR0_1_0,Inner Cacheable property mapping for memory attributes 0" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
group.long 0x19870++0x03
line.long 0x00 "IMELAR9,Note: n= 0 to 15 (IPMMU context) This register indicates the address which an address translation error occurred"
hexmask.long 0x00 0.--31. 1. "EAR_31_0,The faulting virtual address is set when an address translation error occurred"
group.long 0x19874++0x03
line.long 0x00 "IMEUAR9,Note: n= 0 to 15 (IPMMU context) This register indicates the address which an address translation error occurred"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "EAR_39_32,The faulting virtual address is set when an address translation error occurred"
group.long 0x1A880++0x03
line.long 0x00 "IMCTR10,Note: n= 0 to 15 (IPMMU context) This register controls the behavior of the MMU"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved These bits are always read as 0" "0,1,2,3"
bitfld.long 0x00 29. "VA64,AArch64 support" "0: VMSAv8-32 mode This register can be set,1: VMSAv8-64 mode"
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hexmask.long.word 0x00 18.--28. 1. "Reserved_18,Reserved These bits are always read as 0"
bitfld.long 0x00 17. "TRE,TEX Remap Enable This field is used when EAE is 0" "0: TEX remap disabled,1: TEX remap enabled"
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bitfld.long 0x00 16. "AFE,Access Flag Enable" "0: Behave as if AF bit is always set to 1,1: Enable software management of the Access Flag"
rbitfld.long 0x00 15. "SEC,Copy of IMSEC.SEC[n]" "0: Behave as non-secure context,1: Behave as secure context"
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hexmask.long.byte 0x00 8.--14. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 4.--7. "RTSEL_3_0,Retranslation Table Select When TREN is 1 RTSEL indicates the table number to retranslate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 3. "TREN,MMU Retranslation Enable" "0: Output PA as a physical address,1: Output PA as an intermediate physical address.."
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error occurs,1: Assert an interrupt when an error occurs"
newline
bitfld.long 0x00 1. "FLUSH,TLB Invalidate This bit is automatically cleared to 0" "0,1"
bitfld.long 0x00 0. "MMUEN,MMU Enable" "0: MMU disabled,1: MMU enabled"
group.long 0x1A888++0x03
line.long 0x00 "IMTTBCR10,Note: n= 0 to 15 (IPMMU context) This register controls the attribute of TLB managed by each MMU"
bitfld.long 0x00 31. "EAE,Extended Address Enable" "0: Enable the 32-bit translation system with the,1: Enable the 40-bit translation System with the"
bitfld.long 0x00 30. "PMB,[EAE=0] PMB Enable This bit could be set only 0 when EAE=0" "0: not bypass stage 1 translation when stage 2,1: bypass stage 1 translation when only stage 2"
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bitfld.long 0x00 28.--29. "SH1_1_0,Share ability attributes for the memory associated with the translation table walks using TTBR1n" "0: Non-shareable,1: Reserved,2: Outer shareable,3: Inner shareable"
bitfld.long 0x00 26.--27. "ORGN1_1_0,Outer Cache ability attributes for the memory associated with the translation table walks using TTBR1n" "0: Normal memory Outer Non-cacheable,1: Normal memory Outer Write-Back Write-Allocate,2: Normal memory Outer Write-Through Cacheable,3: Normal memory Outer Write-Back no.."
newline
bitfld.long 0x00 24.--25. "IRGN1_1_0,Inner Cache ability attributes for the memory associated with the translation table walks using TTBR1n" "0: Normal memory Inner Non-cacheable,1: Normal memory Inner Write-Back Write-Allocate,2: Normal memory Inner Write-Through Cacheable,3: Normal memory Inner Write-Back no.."
bitfld.long 0x00 23. "PGSZ,[VMSAv8-32 EAE=0] 2nd level Page Size Select" "0: 4KB page granule (default),1: 64KB page granule"
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bitfld.long 0x00 22. "SCSZ,[VMSAv8-32 EAE=0] 1st level page size select" "0: Support section size (1MB),1: Support super section size (16MB)"
bitfld.long 0x00 16.--21. "TSZ1_5_0,[VMSAv8-64] TSZ1[5:0] is used for the size offset of the TTBR0n addressed region encoded as a 6-bit unsigned number giving the size of the region as 2^(64-TSZ1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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rbitfld.long 0x00 14.--15. "Reserved_14,Reserved These bits are always read as 0" "0,1,2,3"
bitfld.long 0x00 12.--13. "SH0_1_0,Share ability attributes for the memory associated with the translation table walks using TTBR0n" "0: Non-shareable,1: Reserved,2: Outer shareable,3: Inner shareable"
newline
bitfld.long 0x00 10.--11. "ORGN0_1_0,Outer Cache ability attributes for the memory associated with the translation table walks using TTBR0n" "0: Normal memory Outer Non-cacheable,1: Normal memory Outer Write-Back Write-Allocate,2: Normal memory Outer Write-Through Cacheable,3: Normal memory Outer Write-Back no.."
bitfld.long 0x00 8.--9. "IRGN0_1_0,Inner Cache ability attributes for the memory associated with the translation table walks using TTBR0n" "0: Normal memory Inner Non-cacheable,1: Normal memory Inner Write-Back Write-Allocate,2: Normal memory Inner Write-Through Cacheable,3: Normal memory Inner Write-Back no.."
newline
bitfld.long 0x00 6.--7. "SL_1_0,Starting level for translation table walks" "0: Start at third level,1: Start at second level,?..."
bitfld.long 0x00 0.--5. "TSZ0_5_0,[VMSAv8-64]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x1A890++0x03
line.long 0x00 "IMTTLBR010,Note: n= 0 to 15 (IPMMU context) This register indicates the base address of the TLB managed by each MMU"
hexmask.long.tbyte 0x00 12.--31. 1. "TTBR_31_12,Bits [31:12] of translation table base address"
hexmask.long.word 0x00 0.--11. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x1A894++0x03
line.long 0x00 "IMTTUBR010,Note: n= 0 to 15 (IPMMU context) This register indicates the base address of the TLB managed by each MMU"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "TTBR_39_32,Bits [39:32] of translation table base address This field is used when EAE is 1"
group.long 0x1A898++0x03
line.long 0x00 "IMTTLBR110,Note: n= 0 to 15 (IPMMU context) This register indicates the base address of the TLB managed by each MMU"
hexmask.long.tbyte 0x00 12.--31. 1. "TTBR_31_12,Bits [31:12] of translation table base address"
hexmask.long.word 0x00 0.--11. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x1A89C++0x03
line.long 0x00 "IMTTUBR110,Note: n= 0 to 15 (IPMMU context) This register indicates the base address of the TLB managed by each MMU"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "TTBR_39_32,Bits [39:32] of translation table base address This field is used when EAE is 1"
group.long 0x1A8A0++0x03
line.long 0x00 "IMSTR10,Note: n= 0 to 15 (IPMMU context) This register indicates the error status of during address translation"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are always read as 0"
bitfld.long 0x00 12.--13. "ERRLVL_1_0,indicate which level of page table walk caused the error" "0: Level1 page table walk,1: Level2 page table walk,2: Level3 page table walk,?..."
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rbitfld.long 0x00 11. "Reserved_11,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 8.--10. "ERRCODE_2_0,Indicate error type" "?,1: Translation Fault,?,?,4: Access Flag Fault / Permission Fault,5: Secure Access Fault Others: reserved,?..."
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4. "MHIT,TLB Conflict Fault Indicate that multiple TLB hits occurred" "0,1"
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rbitfld.long 0x00 3. "Reserved_3,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 2. "ABORT,This bit is set to 1 when the IPMMU received an error response during a page table walk" "0,1"
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bitfld.long 0x00 1. "PF,Permission Fault This bit is set to 1 when an access right violation occurred" "0,1"
bitfld.long 0x00 0. "TF,Translation Fault This bit is set to 1 when a translation fault occurred during a page table walk" "0,1"
group.long 0x1A8A8++0x03
line.long 0x00 "IMMAIR010,(Short-descriptor translation format)"
abitfld.long 0x00 24.--31. "NOS7_0,Outer Shareable property mapping for memory attributes n" "0x00=0: Memory region is outer shareable,0x01=1: Memory region is inner shareable"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 19. "NS1,Mapping of S = 1 attribute for Normal memory" "0: Region is not shareable,1: Region is shareable"
bitfld.long 0x00 18. "NS0,Mapping of S = 0 attribute for Normal memory" "0: Region is not shareable,1: Region is shareable"
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bitfld.long 0x00 17. "DS1,Mapping of S = 1 attribute for Device memory" "0: Region is not shareable,1: Region is shareable"
bitfld.long 0x00 16. "DS0,Mapping of S = 0 attribute for Device memory" "0: Region is not shareable,1: Region is shareable"
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bitfld.long 0x00 14.--15. "TR7_1_0,Primary TEX mapping for memory attributes 7" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
bitfld.long 0x00 12.--13. "TR6_1_0,Primary TEX mapping for memory attributes 6" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
newline
bitfld.long 0x00 10.--11. "TR5_1_0,Primary TEX mapping for memory attributes 5" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
bitfld.long 0x00 8.--9. "TR4_1_0,Primary TEX mapping for memory attributes 4" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
newline
bitfld.long 0x00 6.--7. "TR3_1_0,Primary TEX mapping for memory attributes 3" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
bitfld.long 0x00 4.--5. "TR2_1_0,Primary TEX mapping for memory attributes 2" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
newline
bitfld.long 0x00 2.--3. "TR1_1_0,Primary TEX mapping for memory attributes 1" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
bitfld.long 0x00 0.--1. "TR0_1_0,Primary TEX mapping for memory attributes 0" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
group.long 0x1A8AC++0x03
line.long 0x00 "IMMAIR110,(Short-descriptor translation format)"
bitfld.long 0x00 30.--31. "OR7_1_0,Outer Cacheable property mapping for memory attributes 7" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 28.--29. "OR6_1_0,Outer Cacheable property mapping for memory attributes 6" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 26.--27. "OR5_1_0,Outer Cacheable property mapping for memory attributes 5" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 24.--25. "OR4_1_0,Outer Cacheable property mapping for memory attributes 4" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 22.--23. "OR3_1_0,Outer Cacheable property mapping for memory attributes 3" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 20.--21. "OR2_1_0,Outer Cacheable property mapping for memory attributes 2" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 18.--19. "OR1_1_0,Outer Cacheable property mapping for memory attributes 1" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 16.--17. "OR0_1_0,Outer Cacheable property mapping for memory attributes 0" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 14.--15. "IR7_1_0,Inner Cacheable property mapping for memory attributes 7" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 12.--13. "IR6_1_0,Inner Cacheable property mapping for memory attributes 6" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 10.--11. "IR5_1_0,Inner Cacheable property mapping for memory attributes 5" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 8.--9. "IR4_1_0,Inner Cacheable property mapping for memory attributes 4" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
newline
bitfld.long 0x00 6.--7. "IR3_1_0,Inner Cacheable property mapping for memory attributes 3" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 4.--5. "IR2_1_0,Inner Cacheable property mapping for memory attributes 2" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
newline
bitfld.long 0x00 2.--3. "IR1_1_0,Inner Cacheable property mapping for memory attributes 1" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 0.--1. "IR0_1_0,Inner Cacheable property mapping for memory attributes 0" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
group.long 0x1A8B0++0x03
line.long 0x00 "IMELAR10,Note: n= 0 to 15 (IPMMU context) This register indicates the address which an address translation error occurred"
hexmask.long 0x00 0.--31. 1. "EAR_31_0,The faulting virtual address is set when an address translation error occurred"
group.long 0x1A8B4++0x03
line.long 0x00 "IMEUAR10,Note: n= 0 to 15 (IPMMU context) This register indicates the address which an address translation error occurred"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "EAR_39_32,The faulting virtual address is set when an address translation error occurred"
group.long 0x1B8C0++0x03
line.long 0x00 "IMCTR11,Note: n= 0 to 15 (IPMMU context) This register controls the behavior of the MMU"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved These bits are always read as 0" "0,1,2,3"
bitfld.long 0x00 29. "VA64,AArch64 support" "0: VMSAv8-32 mode This register can be set,1: VMSAv8-64 mode"
newline
hexmask.long.word 0x00 18.--28. 1. "Reserved_18,Reserved These bits are always read as 0"
bitfld.long 0x00 17. "TRE,TEX Remap Enable This field is used when EAE is 0" "0: TEX remap disabled,1: TEX remap enabled"
newline
bitfld.long 0x00 16. "AFE,Access Flag Enable" "0: Behave as if AF bit is always set to 1,1: Enable software management of the Access Flag"
rbitfld.long 0x00 15. "SEC,Copy of IMSEC.SEC[n]" "0: Behave as non-secure context,1: Behave as secure context"
newline
hexmask.long.byte 0x00 8.--14. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 4.--7. "RTSEL_3_0,Retranslation Table Select When TREN is 1 RTSEL indicates the table number to retranslate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 3. "TREN,MMU Retranslation Enable" "0: Output PA as a physical address,1: Output PA as an intermediate physical address.."
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error occurs,1: Assert an interrupt when an error occurs"
newline
bitfld.long 0x00 1. "FLUSH,TLB Invalidate This bit is automatically cleared to 0" "0,1"
bitfld.long 0x00 0. "MMUEN,MMU Enable" "0: MMU disabled,1: MMU enabled"
group.long 0x1B8C8++0x03
line.long 0x00 "IMTTBCR11,Note: n= 0 to 15 (IPMMU context) This register controls the attribute of TLB managed by each MMU"
bitfld.long 0x00 31. "EAE,Extended Address Enable" "0: Enable the 32-bit translation system with the,1: Enable the 40-bit translation System with the"
bitfld.long 0x00 30. "PMB,[EAE=0] PMB Enable This bit could be set only 0 when EAE=0" "0: not bypass stage 1 translation when stage 2,1: bypass stage 1 translation when only stage 2"
newline
bitfld.long 0x00 28.--29. "SH1_1_0,Share ability attributes for the memory associated with the translation table walks using TTBR1n" "0: Non-shareable,1: Reserved,2: Outer shareable,3: Inner shareable"
bitfld.long 0x00 26.--27. "ORGN1_1_0,Outer Cache ability attributes for the memory associated with the translation table walks using TTBR1n" "0: Normal memory Outer Non-cacheable,1: Normal memory Outer Write-Back Write-Allocate,2: Normal memory Outer Write-Through Cacheable,3: Normal memory Outer Write-Back no.."
newline
bitfld.long 0x00 24.--25. "IRGN1_1_0,Inner Cache ability attributes for the memory associated with the translation table walks using TTBR1n" "0: Normal memory Inner Non-cacheable,1: Normal memory Inner Write-Back Write-Allocate,2: Normal memory Inner Write-Through Cacheable,3: Normal memory Inner Write-Back no.."
bitfld.long 0x00 23. "PGSZ,[VMSAv8-32 EAE=0] 2nd level Page Size Select" "0: 4KB page granule (default),1: 64KB page granule"
newline
bitfld.long 0x00 22. "SCSZ,[VMSAv8-32 EAE=0] 1st level page size select" "0: Support section size (1MB),1: Support super section size (16MB)"
bitfld.long 0x00 16.--21. "TSZ1_5_0,[VMSAv8-64] TSZ1[5:0] is used for the size offset of the TTBR0n addressed region encoded as a 6-bit unsigned number giving the size of the region as 2^(64-TSZ1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 14.--15. "Reserved_14,Reserved These bits are always read as 0" "0,1,2,3"
bitfld.long 0x00 12.--13. "SH0_1_0,Share ability attributes for the memory associated with the translation table walks using TTBR0n" "0: Non-shareable,1: Reserved,2: Outer shareable,3: Inner shareable"
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bitfld.long 0x00 10.--11. "ORGN0_1_0,Outer Cache ability attributes for the memory associated with the translation table walks using TTBR0n" "0: Normal memory Outer Non-cacheable,1: Normal memory Outer Write-Back Write-Allocate,2: Normal memory Outer Write-Through Cacheable,3: Normal memory Outer Write-Back no.."
bitfld.long 0x00 8.--9. "IRGN0_1_0,Inner Cache ability attributes for the memory associated with the translation table walks using TTBR0n" "0: Normal memory Inner Non-cacheable,1: Normal memory Inner Write-Back Write-Allocate,2: Normal memory Inner Write-Through Cacheable,3: Normal memory Inner Write-Back no.."
newline
bitfld.long 0x00 6.--7. "SL_1_0,Starting level for translation table walks" "0: Start at third level,1: Start at second level,?..."
bitfld.long 0x00 0.--5. "TSZ0_5_0,[VMSAv8-64]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x1B8D0++0x03
line.long 0x00 "IMTTLBR011,Note: n= 0 to 15 (IPMMU context) This register indicates the base address of the TLB managed by each MMU"
hexmask.long.tbyte 0x00 12.--31. 1. "TTBR_31_12,Bits [31:12] of translation table base address"
hexmask.long.word 0x00 0.--11. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x1B8D4++0x03
line.long 0x00 "IMTTUBR011,Note: n= 0 to 15 (IPMMU context) This register indicates the base address of the TLB managed by each MMU"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "TTBR_39_32,Bits [39:32] of translation table base address This field is used when EAE is 1"
group.long 0x1B8D8++0x03
line.long 0x00 "IMTTLBR111,Note: n= 0 to 15 (IPMMU context) This register indicates the base address of the TLB managed by each MMU"
hexmask.long.tbyte 0x00 12.--31. 1. "TTBR_31_12,Bits [31:12] of translation table base address"
hexmask.long.word 0x00 0.--11. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x1B8DC++0x03
line.long 0x00 "IMTTUBR111,Note: n= 0 to 15 (IPMMU context) This register indicates the base address of the TLB managed by each MMU"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "TTBR_39_32,Bits [39:32] of translation table base address This field is used when EAE is 1"
group.long 0x1B8E0++0x03
line.long 0x00 "IMSTR11,Note: n= 0 to 15 (IPMMU context) This register indicates the error status of during address translation"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are always read as 0"
bitfld.long 0x00 12.--13. "ERRLVL_1_0,indicate which level of page table walk caused the error" "0: Level1 page table walk,1: Level2 page table walk,2: Level3 page table walk,?..."
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rbitfld.long 0x00 11. "Reserved_11,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 8.--10. "ERRCODE_2_0,Indicate error type" "?,1: Translation Fault,?,?,4: Access Flag Fault / Permission Fault,5: Secure Access Fault Others: reserved,?..."
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rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4. "MHIT,TLB Conflict Fault Indicate that multiple TLB hits occurred" "0,1"
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rbitfld.long 0x00 3. "Reserved_3,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 2. "ABORT,This bit is set to 1 when the IPMMU received an error response during a page table walk" "0,1"
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bitfld.long 0x00 1. "PF,Permission Fault This bit is set to 1 when an access right violation occurred" "0,1"
bitfld.long 0x00 0. "TF,Translation Fault This bit is set to 1 when a translation fault occurred during a page table walk" "0,1"
group.long 0x1B8E8++0x03
line.long 0x00 "IMMAIR011,(Short-descriptor translation format)"
abitfld.long 0x00 24.--31. "NOS7_0,Outer Shareable property mapping for memory attributes n" "0x00=0: Memory region is outer shareable,0x01=1: Memory region is inner shareable"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 19. "NS1,Mapping of S = 1 attribute for Normal memory" "0: Region is not shareable,1: Region is shareable"
bitfld.long 0x00 18. "NS0,Mapping of S = 0 attribute for Normal memory" "0: Region is not shareable,1: Region is shareable"
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bitfld.long 0x00 17. "DS1,Mapping of S = 1 attribute for Device memory" "0: Region is not shareable,1: Region is shareable"
bitfld.long 0x00 16. "DS0,Mapping of S = 0 attribute for Device memory" "0: Region is not shareable,1: Region is shareable"
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bitfld.long 0x00 14.--15. "TR7_1_0,Primary TEX mapping for memory attributes 7" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
bitfld.long 0x00 12.--13. "TR6_1_0,Primary TEX mapping for memory attributes 6" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
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bitfld.long 0x00 10.--11. "TR5_1_0,Primary TEX mapping for memory attributes 5" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
bitfld.long 0x00 8.--9. "TR4_1_0,Primary TEX mapping for memory attributes 4" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
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bitfld.long 0x00 6.--7. "TR3_1_0,Primary TEX mapping for memory attributes 3" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
bitfld.long 0x00 4.--5. "TR2_1_0,Primary TEX mapping for memory attributes 2" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
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bitfld.long 0x00 2.--3. "TR1_1_0,Primary TEX mapping for memory attributes 1" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
bitfld.long 0x00 0.--1. "TR0_1_0,Primary TEX mapping for memory attributes 0" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
group.long 0x1B8EC++0x03
line.long 0x00 "IMMAIR111,(Short-descriptor translation format)"
bitfld.long 0x00 30.--31. "OR7_1_0,Outer Cacheable property mapping for memory attributes 7" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 28.--29. "OR6_1_0,Outer Cacheable property mapping for memory attributes 6" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 26.--27. "OR5_1_0,Outer Cacheable property mapping for memory attributes 5" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 24.--25. "OR4_1_0,Outer Cacheable property mapping for memory attributes 4" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 22.--23. "OR3_1_0,Outer Cacheable property mapping for memory attributes 3" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 20.--21. "OR2_1_0,Outer Cacheable property mapping for memory attributes 2" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 18.--19. "OR1_1_0,Outer Cacheable property mapping for memory attributes 1" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 16.--17. "OR0_1_0,Outer Cacheable property mapping for memory attributes 0" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 14.--15. "IR7_1_0,Inner Cacheable property mapping for memory attributes 7" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 12.--13. "IR6_1_0,Inner Cacheable property mapping for memory attributes 6" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 10.--11. "IR5_1_0,Inner Cacheable property mapping for memory attributes 5" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 8.--9. "IR4_1_0,Inner Cacheable property mapping for memory attributes 4" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 6.--7. "IR3_1_0,Inner Cacheable property mapping for memory attributes 3" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 4.--5. "IR2_1_0,Inner Cacheable property mapping for memory attributes 2" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 2.--3. "IR1_1_0,Inner Cacheable property mapping for memory attributes 1" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 0.--1. "IR0_1_0,Inner Cacheable property mapping for memory attributes 0" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
group.long 0x1B8F0++0x03
line.long 0x00 "IMELAR11,Note: n= 0 to 15 (IPMMU context) This register indicates the address which an address translation error occurred"
hexmask.long 0x00 0.--31. 1. "EAR_31_0,The faulting virtual address is set when an address translation error occurred"
group.long 0x1B8F4++0x03
line.long 0x00 "IMEUAR11,Note: n= 0 to 15 (IPMMU context) This register indicates the address which an address translation error occurred"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "EAR_39_32,The faulting virtual address is set when an address translation error occurred"
group.long 0x1C900++0x03
line.long 0x00 "IMCTR12,Note: n= 0 to 15 (IPMMU context) This register controls the behavior of the MMU"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved These bits are always read as 0" "0,1,2,3"
bitfld.long 0x00 29. "VA64,AArch64 support" "0: VMSAv8-32 mode This register can be set,1: VMSAv8-64 mode"
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hexmask.long.word 0x00 18.--28. 1. "Reserved_18,Reserved These bits are always read as 0"
bitfld.long 0x00 17. "TRE,TEX Remap Enable This field is used when EAE is 0" "0: TEX remap disabled,1: TEX remap enabled"
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bitfld.long 0x00 16. "AFE,Access Flag Enable" "0: Behave as if AF bit is always set to 1,1: Enable software management of the Access Flag"
rbitfld.long 0x00 15. "SEC,Copy of IMSEC.SEC[n]" "0: Behave as non-secure context,1: Behave as secure context"
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hexmask.long.byte 0x00 8.--14. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 4.--7. "RTSEL_3_0,Retranslation Table Select When TREN is 1 RTSEL indicates the table number to retranslate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 3. "TREN,MMU Retranslation Enable" "0: Output PA as a physical address,1: Output PA as an intermediate physical address.."
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error occurs,1: Assert an interrupt when an error occurs"
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bitfld.long 0x00 1. "FLUSH,TLB Invalidate This bit is automatically cleared to 0" "0,1"
bitfld.long 0x00 0. "MMUEN,MMU Enable" "0: MMU disabled,1: MMU enabled"
group.long 0x1C908++0x03
line.long 0x00 "IMTTBCR12,Note: n= 0 to 15 (IPMMU context) This register controls the attribute of TLB managed by each MMU"
bitfld.long 0x00 31. "EAE,Extended Address Enable" "0: Enable the 32-bit translation system with the,1: Enable the 40-bit translation System with the"
bitfld.long 0x00 30. "PMB,[EAE=0] PMB Enable This bit could be set only 0 when EAE=0" "0: not bypass stage 1 translation when stage 2,1: bypass stage 1 translation when only stage 2"
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bitfld.long 0x00 28.--29. "SH1_1_0,Share ability attributes for the memory associated with the translation table walks using TTBR1n" "0: Non-shareable,1: Reserved,2: Outer shareable,3: Inner shareable"
bitfld.long 0x00 26.--27. "ORGN1_1_0,Outer Cache ability attributes for the memory associated with the translation table walks using TTBR1n" "0: Normal memory Outer Non-cacheable,1: Normal memory Outer Write-Back Write-Allocate,2: Normal memory Outer Write-Through Cacheable,3: Normal memory Outer Write-Back no.."
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bitfld.long 0x00 24.--25. "IRGN1_1_0,Inner Cache ability attributes for the memory associated with the translation table walks using TTBR1n" "0: Normal memory Inner Non-cacheable,1: Normal memory Inner Write-Back Write-Allocate,2: Normal memory Inner Write-Through Cacheable,3: Normal memory Inner Write-Back no.."
bitfld.long 0x00 23. "PGSZ,[VMSAv8-32 EAE=0] 2nd level Page Size Select" "0: 4KB page granule (default),1: 64KB page granule"
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bitfld.long 0x00 22. "SCSZ,[VMSAv8-32 EAE=0] 1st level page size select" "0: Support section size (1MB),1: Support super section size (16MB)"
bitfld.long 0x00 16.--21. "TSZ1_5_0,[VMSAv8-64] TSZ1[5:0] is used for the size offset of the TTBR0n addressed region encoded as a 6-bit unsigned number giving the size of the region as 2^(64-TSZ1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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rbitfld.long 0x00 14.--15. "Reserved_14,Reserved These bits are always read as 0" "0,1,2,3"
bitfld.long 0x00 12.--13. "SH0_1_0,Share ability attributes for the memory associated with the translation table walks using TTBR0n" "0: Non-shareable,1: Reserved,2: Outer shareable,3: Inner shareable"
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bitfld.long 0x00 10.--11. "ORGN0_1_0,Outer Cache ability attributes for the memory associated with the translation table walks using TTBR0n" "0: Normal memory Outer Non-cacheable,1: Normal memory Outer Write-Back Write-Allocate,2: Normal memory Outer Write-Through Cacheable,3: Normal memory Outer Write-Back no.."
bitfld.long 0x00 8.--9. "IRGN0_1_0,Inner Cache ability attributes for the memory associated with the translation table walks using TTBR0n" "0: Normal memory Inner Non-cacheable,1: Normal memory Inner Write-Back Write-Allocate,2: Normal memory Inner Write-Through Cacheable,3: Normal memory Inner Write-Back no.."
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bitfld.long 0x00 6.--7. "SL_1_0,Starting level for translation table walks" "0: Start at third level,1: Start at second level,?..."
bitfld.long 0x00 0.--5. "TSZ0_5_0,[VMSAv8-64]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x1C910++0x03
line.long 0x00 "IMTTLBR012,Note: n= 0 to 15 (IPMMU context) This register indicates the base address of the TLB managed by each MMU"
hexmask.long.tbyte 0x00 12.--31. 1. "TTBR_31_12,Bits [31:12] of translation table base address"
hexmask.long.word 0x00 0.--11. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x1C914++0x03
line.long 0x00 "IMTTUBR012,Note: n= 0 to 15 (IPMMU context) This register indicates the base address of the TLB managed by each MMU"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "TTBR_39_32,Bits [39:32] of translation table base address This field is used when EAE is 1"
group.long 0x1C918++0x03
line.long 0x00 "IMTTLBR112,Note: n= 0 to 15 (IPMMU context) This register indicates the base address of the TLB managed by each MMU"
hexmask.long.tbyte 0x00 12.--31. 1. "TTBR_31_12,Bits [31:12] of translation table base address"
hexmask.long.word 0x00 0.--11. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x1C91C++0x03
line.long 0x00 "IMTTUBR112,Note: n= 0 to 15 (IPMMU context) This register indicates the base address of the TLB managed by each MMU"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "TTBR_39_32,Bits [39:32] of translation table base address This field is used when EAE is 1"
group.long 0x1C920++0x03
line.long 0x00 "IMSTR12,Note: n= 0 to 15 (IPMMU context) This register indicates the error status of during address translation"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are always read as 0"
bitfld.long 0x00 12.--13. "ERRLVL_1_0,indicate which level of page table walk caused the error" "0: Level1 page table walk,1: Level2 page table walk,2: Level3 page table walk,?..."
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rbitfld.long 0x00 11. "Reserved_11,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 8.--10. "ERRCODE_2_0,Indicate error type" "?,1: Translation Fault,?,?,4: Access Flag Fault / Permission Fault,5: Secure Access Fault Others: reserved,?..."
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4. "MHIT,TLB Conflict Fault Indicate that multiple TLB hits occurred" "0,1"
newline
rbitfld.long 0x00 3. "Reserved_3,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 2. "ABORT,This bit is set to 1 when the IPMMU received an error response during a page table walk" "0,1"
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bitfld.long 0x00 1. "PF,Permission Fault This bit is set to 1 when an access right violation occurred" "0,1"
bitfld.long 0x00 0. "TF,Translation Fault This bit is set to 1 when a translation fault occurred during a page table walk" "0,1"
group.long 0x1C928++0x03
line.long 0x00 "IMMAIR012,(Short-descriptor translation format)"
abitfld.long 0x00 24.--31. "NOS7_0,Outer Shareable property mapping for memory attributes n" "0x00=0: Memory region is outer shareable,0x01=1: Memory region is inner shareable"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 19. "NS1,Mapping of S = 1 attribute for Normal memory" "0: Region is not shareable,1: Region is shareable"
bitfld.long 0x00 18. "NS0,Mapping of S = 0 attribute for Normal memory" "0: Region is not shareable,1: Region is shareable"
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bitfld.long 0x00 17. "DS1,Mapping of S = 1 attribute for Device memory" "0: Region is not shareable,1: Region is shareable"
bitfld.long 0x00 16. "DS0,Mapping of S = 0 attribute for Device memory" "0: Region is not shareable,1: Region is shareable"
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bitfld.long 0x00 14.--15. "TR7_1_0,Primary TEX mapping for memory attributes 7" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
bitfld.long 0x00 12.--13. "TR6_1_0,Primary TEX mapping for memory attributes 6" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
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bitfld.long 0x00 10.--11. "TR5_1_0,Primary TEX mapping for memory attributes 5" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
bitfld.long 0x00 8.--9. "TR4_1_0,Primary TEX mapping for memory attributes 4" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
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bitfld.long 0x00 6.--7. "TR3_1_0,Primary TEX mapping for memory attributes 3" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
bitfld.long 0x00 4.--5. "TR2_1_0,Primary TEX mapping for memory attributes 2" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
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bitfld.long 0x00 2.--3. "TR1_1_0,Primary TEX mapping for memory attributes 1" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
bitfld.long 0x00 0.--1. "TR0_1_0,Primary TEX mapping for memory attributes 0" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
group.long 0x1C92C++0x03
line.long 0x00 "IMMAIR112,(Short-descriptor translation format)"
bitfld.long 0x00 30.--31. "OR7_1_0,Outer Cacheable property mapping for memory attributes 7" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 28.--29. "OR6_1_0,Outer Cacheable property mapping for memory attributes 6" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 26.--27. "OR5_1_0,Outer Cacheable property mapping for memory attributes 5" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 24.--25. "OR4_1_0,Outer Cacheable property mapping for memory attributes 4" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 22.--23. "OR3_1_0,Outer Cacheable property mapping for memory attributes 3" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 20.--21. "OR2_1_0,Outer Cacheable property mapping for memory attributes 2" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 18.--19. "OR1_1_0,Outer Cacheable property mapping for memory attributes 1" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 16.--17. "OR0_1_0,Outer Cacheable property mapping for memory attributes 0" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 14.--15. "IR7_1_0,Inner Cacheable property mapping for memory attributes 7" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 12.--13. "IR6_1_0,Inner Cacheable property mapping for memory attributes 6" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 10.--11. "IR5_1_0,Inner Cacheable property mapping for memory attributes 5" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 8.--9. "IR4_1_0,Inner Cacheable property mapping for memory attributes 4" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 6.--7. "IR3_1_0,Inner Cacheable property mapping for memory attributes 3" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 4.--5. "IR2_1_0,Inner Cacheable property mapping for memory attributes 2" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 2.--3. "IR1_1_0,Inner Cacheable property mapping for memory attributes 1" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 0.--1. "IR0_1_0,Inner Cacheable property mapping for memory attributes 0" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
group.long 0x1C930++0x03
line.long 0x00 "IMELAR12,Note: n= 0 to 15 (IPMMU context) This register indicates the address which an address translation error occurred"
hexmask.long 0x00 0.--31. 1. "EAR_31_0,The faulting virtual address is set when an address translation error occurred"
group.long 0x1C934++0x03
line.long 0x00 "IMEUAR12,Note: n= 0 to 15 (IPMMU context) This register indicates the address which an address translation error occurred"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "EAR_39_32,The faulting virtual address is set when an address translation error occurred"
group.long 0x1D940++0x03
line.long 0x00 "IMCTR13,Note: n= 0 to 15 (IPMMU context) This register controls the behavior of the MMU"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved These bits are always read as 0" "0,1,2,3"
bitfld.long 0x00 29. "VA64,AArch64 support" "0: VMSAv8-32 mode This register can be set,1: VMSAv8-64 mode"
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hexmask.long.word 0x00 18.--28. 1. "Reserved_18,Reserved These bits are always read as 0"
bitfld.long 0x00 17. "TRE,TEX Remap Enable This field is used when EAE is 0" "0: TEX remap disabled,1: TEX remap enabled"
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bitfld.long 0x00 16. "AFE,Access Flag Enable" "0: Behave as if AF bit is always set to 1,1: Enable software management of the Access Flag"
rbitfld.long 0x00 15. "SEC,Copy of IMSEC.SEC[n]" "0: Behave as non-secure context,1: Behave as secure context"
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hexmask.long.byte 0x00 8.--14. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 4.--7. "RTSEL_3_0,Retranslation Table Select When TREN is 1 RTSEL indicates the table number to retranslate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 3. "TREN,MMU Retranslation Enable" "0: Output PA as a physical address,1: Output PA as an intermediate physical address.."
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error occurs,1: Assert an interrupt when an error occurs"
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bitfld.long 0x00 1. "FLUSH,TLB Invalidate This bit is automatically cleared to 0" "0,1"
bitfld.long 0x00 0. "MMUEN,MMU Enable" "0: MMU disabled,1: MMU enabled"
group.long 0x1D948++0x03
line.long 0x00 "IMTTBCR13,Note: n= 0 to 15 (IPMMU context) This register controls the attribute of TLB managed by each MMU"
bitfld.long 0x00 31. "EAE,Extended Address Enable" "0: Enable the 32-bit translation system with the,1: Enable the 40-bit translation System with the"
bitfld.long 0x00 30. "PMB,[EAE=0] PMB Enable This bit could be set only 0 when EAE=0" "0: not bypass stage 1 translation when stage 2,1: bypass stage 1 translation when only stage 2"
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bitfld.long 0x00 28.--29. "SH1_1_0,Share ability attributes for the memory associated with the translation table walks using TTBR1n" "0: Non-shareable,1: Reserved,2: Outer shareable,3: Inner shareable"
bitfld.long 0x00 26.--27. "ORGN1_1_0,Outer Cache ability attributes for the memory associated with the translation table walks using TTBR1n" "0: Normal memory Outer Non-cacheable,1: Normal memory Outer Write-Back Write-Allocate,2: Normal memory Outer Write-Through Cacheable,3: Normal memory Outer Write-Back no.."
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bitfld.long 0x00 24.--25. "IRGN1_1_0,Inner Cache ability attributes for the memory associated with the translation table walks using TTBR1n" "0: Normal memory Inner Non-cacheable,1: Normal memory Inner Write-Back Write-Allocate,2: Normal memory Inner Write-Through Cacheable,3: Normal memory Inner Write-Back no.."
bitfld.long 0x00 23. "PGSZ,[VMSAv8-32 EAE=0] 2nd level Page Size Select" "0: 4KB page granule (default),1: 64KB page granule"
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bitfld.long 0x00 22. "SCSZ,[VMSAv8-32 EAE=0] 1st level page size select" "0: Support section size (1MB),1: Support super section size (16MB)"
bitfld.long 0x00 16.--21. "TSZ1_5_0,[VMSAv8-64] TSZ1[5:0] is used for the size offset of the TTBR0n addressed region encoded as a 6-bit unsigned number giving the size of the region as 2^(64-TSZ1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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rbitfld.long 0x00 14.--15. "Reserved_14,Reserved These bits are always read as 0" "0,1,2,3"
bitfld.long 0x00 12.--13. "SH0_1_0,Share ability attributes for the memory associated with the translation table walks using TTBR0n" "0: Non-shareable,1: Reserved,2: Outer shareable,3: Inner shareable"
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bitfld.long 0x00 10.--11. "ORGN0_1_0,Outer Cache ability attributes for the memory associated with the translation table walks using TTBR0n" "0: Normal memory Outer Non-cacheable,1: Normal memory Outer Write-Back Write-Allocate,2: Normal memory Outer Write-Through Cacheable,3: Normal memory Outer Write-Back no.."
bitfld.long 0x00 8.--9. "IRGN0_1_0,Inner Cache ability attributes for the memory associated with the translation table walks using TTBR0n" "0: Normal memory Inner Non-cacheable,1: Normal memory Inner Write-Back Write-Allocate,2: Normal memory Inner Write-Through Cacheable,3: Normal memory Inner Write-Back no.."
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bitfld.long 0x00 6.--7. "SL_1_0,Starting level for translation table walks" "0: Start at third level,1: Start at second level,?..."
bitfld.long 0x00 0.--5. "TSZ0_5_0,[VMSAv8-64]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x1D950++0x03
line.long 0x00 "IMTTLBR013,Note: n= 0 to 15 (IPMMU context) This register indicates the base address of the TLB managed by each MMU"
hexmask.long.tbyte 0x00 12.--31. 1. "TTBR_31_12,Bits [31:12] of translation table base address"
hexmask.long.word 0x00 0.--11. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x1D954++0x03
line.long 0x00 "IMTTUBR013,Note: n= 0 to 15 (IPMMU context) This register indicates the base address of the TLB managed by each MMU"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "TTBR_39_32,Bits [39:32] of translation table base address This field is used when EAE is 1"
group.long 0x1D958++0x03
line.long 0x00 "IMTTLBR113,Note: n= 0 to 15 (IPMMU context) This register indicates the base address of the TLB managed by each MMU"
hexmask.long.tbyte 0x00 12.--31. 1. "TTBR_31_12,Bits [31:12] of translation table base address"
hexmask.long.word 0x00 0.--11. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x1D95C++0x03
line.long 0x00 "IMTTUBR113,Note: n= 0 to 15 (IPMMU context) This register indicates the base address of the TLB managed by each MMU"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "TTBR_39_32,Bits [39:32] of translation table base address This field is used when EAE is 1"
group.long 0x1D960++0x03
line.long 0x00 "IMSTR13,Note: n= 0 to 15 (IPMMU context) This register indicates the error status of during address translation"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are always read as 0"
bitfld.long 0x00 12.--13. "ERRLVL_1_0,indicate which level of page table walk caused the error" "0: Level1 page table walk,1: Level2 page table walk,2: Level3 page table walk,?..."
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rbitfld.long 0x00 11. "Reserved_11,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 8.--10. "ERRCODE_2_0,Indicate error type" "?,1: Translation Fault,?,?,4: Access Flag Fault / Permission Fault,5: Secure Access Fault Others: reserved,?..."
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rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4. "MHIT,TLB Conflict Fault Indicate that multiple TLB hits occurred" "0,1"
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rbitfld.long 0x00 3. "Reserved_3,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 2. "ABORT,This bit is set to 1 when the IPMMU received an error response during a page table walk" "0,1"
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bitfld.long 0x00 1. "PF,Permission Fault This bit is set to 1 when an access right violation occurred" "0,1"
bitfld.long 0x00 0. "TF,Translation Fault This bit is set to 1 when a translation fault occurred during a page table walk" "0,1"
group.long 0x1D968++0x03
line.long 0x00 "IMMAIR013,(Short-descriptor translation format)"
abitfld.long 0x00 24.--31. "NOS7_0,Outer Shareable property mapping for memory attributes n" "0x00=0: Memory region is outer shareable,0x01=1: Memory region is inner shareable"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 19. "NS1,Mapping of S = 1 attribute for Normal memory" "0: Region is not shareable,1: Region is shareable"
bitfld.long 0x00 18. "NS0,Mapping of S = 0 attribute for Normal memory" "0: Region is not shareable,1: Region is shareable"
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bitfld.long 0x00 17. "DS1,Mapping of S = 1 attribute for Device memory" "0: Region is not shareable,1: Region is shareable"
bitfld.long 0x00 16. "DS0,Mapping of S = 0 attribute for Device memory" "0: Region is not shareable,1: Region is shareable"
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bitfld.long 0x00 14.--15. "TR7_1_0,Primary TEX mapping for memory attributes 7" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
bitfld.long 0x00 12.--13. "TR6_1_0,Primary TEX mapping for memory attributes 6" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
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bitfld.long 0x00 10.--11. "TR5_1_0,Primary TEX mapping for memory attributes 5" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
bitfld.long 0x00 8.--9. "TR4_1_0,Primary TEX mapping for memory attributes 4" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
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bitfld.long 0x00 6.--7. "TR3_1_0,Primary TEX mapping for memory attributes 3" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
bitfld.long 0x00 4.--5. "TR2_1_0,Primary TEX mapping for memory attributes 2" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
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bitfld.long 0x00 2.--3. "TR1_1_0,Primary TEX mapping for memory attributes 1" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
bitfld.long 0x00 0.--1. "TR0_1_0,Primary TEX mapping for memory attributes 0" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
group.long 0x1D96C++0x03
line.long 0x00 "IMMAIR113,(Short-descriptor translation format)"
bitfld.long 0x00 30.--31. "OR7_1_0,Outer Cacheable property mapping for memory attributes 7" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 28.--29. "OR6_1_0,Outer Cacheable property mapping for memory attributes 6" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 26.--27. "OR5_1_0,Outer Cacheable property mapping for memory attributes 5" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 24.--25. "OR4_1_0,Outer Cacheable property mapping for memory attributes 4" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 22.--23. "OR3_1_0,Outer Cacheable property mapping for memory attributes 3" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 20.--21. "OR2_1_0,Outer Cacheable property mapping for memory attributes 2" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 18.--19. "OR1_1_0,Outer Cacheable property mapping for memory attributes 1" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 16.--17. "OR0_1_0,Outer Cacheable property mapping for memory attributes 0" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 14.--15. "IR7_1_0,Inner Cacheable property mapping for memory attributes 7" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 12.--13. "IR6_1_0,Inner Cacheable property mapping for memory attributes 6" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 10.--11. "IR5_1_0,Inner Cacheable property mapping for memory attributes 5" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 8.--9. "IR4_1_0,Inner Cacheable property mapping for memory attributes 4" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 6.--7. "IR3_1_0,Inner Cacheable property mapping for memory attributes 3" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 4.--5. "IR2_1_0,Inner Cacheable property mapping for memory attributes 2" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 2.--3. "IR1_1_0,Inner Cacheable property mapping for memory attributes 1" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 0.--1. "IR0_1_0,Inner Cacheable property mapping for memory attributes 0" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
group.long 0x1D970++0x03
line.long 0x00 "IMELAR13,Note: n= 0 to 15 (IPMMU context) This register indicates the address which an address translation error occurred"
hexmask.long 0x00 0.--31. 1. "EAR_31_0,The faulting virtual address is set when an address translation error occurred"
group.long 0x1D974++0x03
line.long 0x00 "IMEUAR13,Note: n= 0 to 15 (IPMMU context) This register indicates the address which an address translation error occurred"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "EAR_39_32,The faulting virtual address is set when an address translation error occurred"
group.long 0x1E980++0x03
line.long 0x00 "IMCTR14,Note: n= 0 to 15 (IPMMU context) This register controls the behavior of the MMU"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved These bits are always read as 0" "0,1,2,3"
bitfld.long 0x00 29. "VA64,AArch64 support" "0: VMSAv8-32 mode This register can be set,1: VMSAv8-64 mode"
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hexmask.long.word 0x00 18.--28. 1. "Reserved_18,Reserved These bits are always read as 0"
bitfld.long 0x00 17. "TRE,TEX Remap Enable This field is used when EAE is 0" "0: TEX remap disabled,1: TEX remap enabled"
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bitfld.long 0x00 16. "AFE,Access Flag Enable" "0: Behave as if AF bit is always set to 1,1: Enable software management of the Access Flag"
rbitfld.long 0x00 15. "SEC,Copy of IMSEC.SEC[n]" "0: Behave as non-secure context,1: Behave as secure context"
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hexmask.long.byte 0x00 8.--14. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 4.--7. "RTSEL_3_0,Retranslation Table Select When TREN is 1 RTSEL indicates the table number to retranslate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 3. "TREN,MMU Retranslation Enable" "0: Output PA as a physical address,1: Output PA as an intermediate physical address.."
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error occurs,1: Assert an interrupt when an error occurs"
newline
bitfld.long 0x00 1. "FLUSH,TLB Invalidate This bit is automatically cleared to 0" "0,1"
bitfld.long 0x00 0. "MMUEN,MMU Enable" "0: MMU disabled,1: MMU enabled"
group.long 0x1E988++0x03
line.long 0x00 "IMTTBCR14,Note: n= 0 to 15 (IPMMU context) This register controls the attribute of TLB managed by each MMU"
bitfld.long 0x00 31. "EAE,Extended Address Enable" "0: Enable the 32-bit translation system with the,1: Enable the 40-bit translation System with the"
bitfld.long 0x00 30. "PMB,[EAE=0] PMB Enable This bit could be set only 0 when EAE=0" "0: not bypass stage 1 translation when stage 2,1: bypass stage 1 translation when only stage 2"
newline
bitfld.long 0x00 28.--29. "SH1_1_0,Share ability attributes for the memory associated with the translation table walks using TTBR1n" "0: Non-shareable,1: Reserved,2: Outer shareable,3: Inner shareable"
bitfld.long 0x00 26.--27. "ORGN1_1_0,Outer Cache ability attributes for the memory associated with the translation table walks using TTBR1n" "0: Normal memory Outer Non-cacheable,1: Normal memory Outer Write-Back Write-Allocate,2: Normal memory Outer Write-Through Cacheable,3: Normal memory Outer Write-Back no.."
newline
bitfld.long 0x00 24.--25. "IRGN1_1_0,Inner Cache ability attributes for the memory associated with the translation table walks using TTBR1n" "0: Normal memory Inner Non-cacheable,1: Normal memory Inner Write-Back Write-Allocate,2: Normal memory Inner Write-Through Cacheable,3: Normal memory Inner Write-Back no.."
bitfld.long 0x00 23. "PGSZ,[VMSAv8-32 EAE=0] 2nd level Page Size Select" "0: 4KB page granule (default),1: 64KB page granule"
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bitfld.long 0x00 22. "SCSZ,[VMSAv8-32 EAE=0] 1st level page size select" "0: Support section size (1MB),1: Support super section size (16MB)"
bitfld.long 0x00 16.--21. "TSZ1_5_0,[VMSAv8-64] TSZ1[5:0] is used for the size offset of the TTBR0n addressed region encoded as a 6-bit unsigned number giving the size of the region as 2^(64-TSZ1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 14.--15. "Reserved_14,Reserved These bits are always read as 0" "0,1,2,3"
bitfld.long 0x00 12.--13. "SH0_1_0,Share ability attributes for the memory associated with the translation table walks using TTBR0n" "0: Non-shareable,1: Reserved,2: Outer shareable,3: Inner shareable"
newline
bitfld.long 0x00 10.--11. "ORGN0_1_0,Outer Cache ability attributes for the memory associated with the translation table walks using TTBR0n" "0: Normal memory Outer Non-cacheable,1: Normal memory Outer Write-Back Write-Allocate,2: Normal memory Outer Write-Through Cacheable,3: Normal memory Outer Write-Back no.."
bitfld.long 0x00 8.--9. "IRGN0_1_0,Inner Cache ability attributes for the memory associated with the translation table walks using TTBR0n" "0: Normal memory Inner Non-cacheable,1: Normal memory Inner Write-Back Write-Allocate,2: Normal memory Inner Write-Through Cacheable,3: Normal memory Inner Write-Back no.."
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bitfld.long 0x00 6.--7. "SL_1_0,Starting level for translation table walks" "0: Start at third level,1: Start at second level,?..."
bitfld.long 0x00 0.--5. "TSZ0_5_0,[VMSAv8-64]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x1E990++0x03
line.long 0x00 "IMTTLBR014,Note: n= 0 to 15 (IPMMU context) This register indicates the base address of the TLB managed by each MMU"
hexmask.long.tbyte 0x00 12.--31. 1. "TTBR_31_12,Bits [31:12] of translation table base address"
hexmask.long.word 0x00 0.--11. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x1E994++0x03
line.long 0x00 "IMTTUBR014,Note: n= 0 to 15 (IPMMU context) This register indicates the base address of the TLB managed by each MMU"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "TTBR_39_32,Bits [39:32] of translation table base address This field is used when EAE is 1"
group.long 0x1E998++0x03
line.long 0x00 "IMTTLBR114,Note: n= 0 to 15 (IPMMU context) This register indicates the base address of the TLB managed by each MMU"
hexmask.long.tbyte 0x00 12.--31. 1. "TTBR_31_12,Bits [31:12] of translation table base address"
hexmask.long.word 0x00 0.--11. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x1E99C++0x03
line.long 0x00 "IMTTUBR114,Note: n= 0 to 15 (IPMMU context) This register indicates the base address of the TLB managed by each MMU"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "TTBR_39_32,Bits [39:32] of translation table base address This field is used when EAE is 1"
group.long 0x1E9A0++0x03
line.long 0x00 "IMSTR14,Note: n= 0 to 15 (IPMMU context) This register indicates the error status of during address translation"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are always read as 0"
bitfld.long 0x00 12.--13. "ERRLVL_1_0,indicate which level of page table walk caused the error" "0: Level1 page table walk,1: Level2 page table walk,2: Level3 page table walk,?..."
newline
rbitfld.long 0x00 11. "Reserved_11,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 8.--10. "ERRCODE_2_0,Indicate error type" "?,1: Translation Fault,?,?,4: Access Flag Fault / Permission Fault,5: Secure Access Fault Others: reserved,?..."
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4. "MHIT,TLB Conflict Fault Indicate that multiple TLB hits occurred" "0,1"
newline
rbitfld.long 0x00 3. "Reserved_3,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 2. "ABORT,This bit is set to 1 when the IPMMU received an error response during a page table walk" "0,1"
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bitfld.long 0x00 1. "PF,Permission Fault This bit is set to 1 when an access right violation occurred" "0,1"
bitfld.long 0x00 0. "TF,Translation Fault This bit is set to 1 when a translation fault occurred during a page table walk" "0,1"
group.long 0x1E9A8++0x03
line.long 0x00 "IMMAIR014,(Short-descriptor translation format)"
abitfld.long 0x00 24.--31. "NOS7_0,Outer Shareable property mapping for memory attributes n" "0x00=0: Memory region is outer shareable,0x01=1: Memory region is inner shareable"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 19. "NS1,Mapping of S = 1 attribute for Normal memory" "0: Region is not shareable,1: Region is shareable"
bitfld.long 0x00 18. "NS0,Mapping of S = 0 attribute for Normal memory" "0: Region is not shareable,1: Region is shareable"
newline
bitfld.long 0x00 17. "DS1,Mapping of S = 1 attribute for Device memory" "0: Region is not shareable,1: Region is shareable"
bitfld.long 0x00 16. "DS0,Mapping of S = 0 attribute for Device memory" "0: Region is not shareable,1: Region is shareable"
newline
bitfld.long 0x00 14.--15. "TR7_1_0,Primary TEX mapping for memory attributes 7" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
bitfld.long 0x00 12.--13. "TR6_1_0,Primary TEX mapping for memory attributes 6" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
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bitfld.long 0x00 10.--11. "TR5_1_0,Primary TEX mapping for memory attributes 5" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
bitfld.long 0x00 8.--9. "TR4_1_0,Primary TEX mapping for memory attributes 4" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
newline
bitfld.long 0x00 6.--7. "TR3_1_0,Primary TEX mapping for memory attributes 3" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
bitfld.long 0x00 4.--5. "TR2_1_0,Primary TEX mapping for memory attributes 2" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
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bitfld.long 0x00 2.--3. "TR1_1_0,Primary TEX mapping for memory attributes 1" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
bitfld.long 0x00 0.--1. "TR0_1_0,Primary TEX mapping for memory attributes 0" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
group.long 0x1E9AC++0x03
line.long 0x00 "IMMAIR114,(Short-descriptor translation format)"
bitfld.long 0x00 30.--31. "OR7_1_0,Outer Cacheable property mapping for memory attributes 7" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 28.--29. "OR6_1_0,Outer Cacheable property mapping for memory attributes 6" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 26.--27. "OR5_1_0,Outer Cacheable property mapping for memory attributes 5" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 24.--25. "OR4_1_0,Outer Cacheable property mapping for memory attributes 4" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 22.--23. "OR3_1_0,Outer Cacheable property mapping for memory attributes 3" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 20.--21. "OR2_1_0,Outer Cacheable property mapping for memory attributes 2" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 18.--19. "OR1_1_0,Outer Cacheable property mapping for memory attributes 1" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 16.--17. "OR0_1_0,Outer Cacheable property mapping for memory attributes 0" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 14.--15. "IR7_1_0,Inner Cacheable property mapping for memory attributes 7" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 12.--13. "IR6_1_0,Inner Cacheable property mapping for memory attributes 6" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 10.--11. "IR5_1_0,Inner Cacheable property mapping for memory attributes 5" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 8.--9. "IR4_1_0,Inner Cacheable property mapping for memory attributes 4" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 6.--7. "IR3_1_0,Inner Cacheable property mapping for memory attributes 3" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 4.--5. "IR2_1_0,Inner Cacheable property mapping for memory attributes 2" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 2.--3. "IR1_1_0,Inner Cacheable property mapping for memory attributes 1" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 0.--1. "IR0_1_0,Inner Cacheable property mapping for memory attributes 0" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
group.long 0x1E9B0++0x03
line.long 0x00 "IMELAR14,Note: n= 0 to 15 (IPMMU context) This register indicates the address which an address translation error occurred"
hexmask.long 0x00 0.--31. 1. "EAR_31_0,The faulting virtual address is set when an address translation error occurred"
group.long 0x1E9B4++0x03
line.long 0x00 "IMEUAR14,Note: n= 0 to 15 (IPMMU context) This register indicates the address which an address translation error occurred"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "EAR_39_32,The faulting virtual address is set when an address translation error occurred"
group.long 0x1F9C0++0x03
line.long 0x00 "IMCTR15,Note: n= 0 to 15 (IPMMU context) This register controls the behavior of the MMU"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved These bits are always read as 0" "0,1,2,3"
bitfld.long 0x00 29. "VA64,AArch64 support" "0: VMSAv8-32 mode This register can be set,1: VMSAv8-64 mode"
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hexmask.long.word 0x00 18.--28. 1. "Reserved_18,Reserved These bits are always read as 0"
bitfld.long 0x00 17. "TRE,TEX Remap Enable This field is used when EAE is 0" "0: TEX remap disabled,1: TEX remap enabled"
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bitfld.long 0x00 16. "AFE,Access Flag Enable" "0: Behave as if AF bit is always set to 1,1: Enable software management of the Access Flag"
rbitfld.long 0x00 15. "SEC,Copy of IMSEC.SEC[n]" "0: Behave as non-secure context,1: Behave as secure context"
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hexmask.long.byte 0x00 8.--14. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 4.--7. "RTSEL_3_0,Retranslation Table Select When TREN is 1 RTSEL indicates the table number to retranslate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 3. "TREN,MMU Retranslation Enable" "0: Output PA as a physical address,1: Output PA as an intermediate physical address.."
bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: Dont assert an interrupt when an error occurs,1: Assert an interrupt when an error occurs"
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bitfld.long 0x00 1. "FLUSH,TLB Invalidate This bit is automatically cleared to 0" "0,1"
bitfld.long 0x00 0. "MMUEN,MMU Enable" "0: MMU disabled,1: MMU enabled"
group.long 0x1F9C8++0x03
line.long 0x00 "IMTTBCR15,Note: n= 0 to 15 (IPMMU context) This register controls the attribute of TLB managed by each MMU"
bitfld.long 0x00 31. "EAE,Extended Address Enable" "0: Enable the 32-bit translation system with the,1: Enable the 40-bit translation System with the"
bitfld.long 0x00 30. "PMB,[EAE=0] PMB Enable This bit could be set only 0 when EAE=0" "0: not bypass stage 1 translation when stage 2,1: bypass stage 1 translation when only stage 2"
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bitfld.long 0x00 28.--29. "SH1_1_0,Share ability attributes for the memory associated with the translation table walks using TTBR1n" "0: Non-shareable,1: Reserved,2: Outer shareable,3: Inner shareable"
bitfld.long 0x00 26.--27. "ORGN1_1_0,Outer Cache ability attributes for the memory associated with the translation table walks using TTBR1n" "0: Normal memory Outer Non-cacheable,1: Normal memory Outer Write-Back Write-Allocate,2: Normal memory Outer Write-Through Cacheable,3: Normal memory Outer Write-Back no.."
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bitfld.long 0x00 24.--25. "IRGN1_1_0,Inner Cache ability attributes for the memory associated with the translation table walks using TTBR1n" "0: Normal memory Inner Non-cacheable,1: Normal memory Inner Write-Back Write-Allocate,2: Normal memory Inner Write-Through Cacheable,3: Normal memory Inner Write-Back no.."
bitfld.long 0x00 23. "PGSZ,[VMSAv8-32 EAE=0] 2nd level Page Size Select" "0: 4KB page granule (default),1: 64KB page granule"
newline
bitfld.long 0x00 22. "SCSZ,[VMSAv8-32 EAE=0] 1st level page size select" "0: Support section size (1MB),1: Support super section size (16MB)"
bitfld.long 0x00 16.--21. "TSZ1_5_0,[VMSAv8-64] TSZ1[5:0] is used for the size offset of the TTBR0n addressed region encoded as a 6-bit unsigned number giving the size of the region as 2^(64-TSZ1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 14.--15. "Reserved_14,Reserved These bits are always read as 0" "0,1,2,3"
bitfld.long 0x00 12.--13. "SH0_1_0,Share ability attributes for the memory associated with the translation table walks using TTBR0n" "0: Non-shareable,1: Reserved,2: Outer shareable,3: Inner shareable"
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bitfld.long 0x00 10.--11. "ORGN0_1_0,Outer Cache ability attributes for the memory associated with the translation table walks using TTBR0n" "0: Normal memory Outer Non-cacheable,1: Normal memory Outer Write-Back Write-Allocate,2: Normal memory Outer Write-Through Cacheable,3: Normal memory Outer Write-Back no.."
bitfld.long 0x00 8.--9. "IRGN0_1_0,Inner Cache ability attributes for the memory associated with the translation table walks using TTBR0n" "0: Normal memory Inner Non-cacheable,1: Normal memory Inner Write-Back Write-Allocate,2: Normal memory Inner Write-Through Cacheable,3: Normal memory Inner Write-Back no.."
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bitfld.long 0x00 6.--7. "SL_1_0,Starting level for translation table walks" "0: Start at third level,1: Start at second level,?..."
bitfld.long 0x00 0.--5. "TSZ0_5_0,[VMSAv8-64]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x1F9D0++0x03
line.long 0x00 "IMTTLBR015,Note: n= 0 to 15 (IPMMU context) This register indicates the base address of the TLB managed by each MMU"
hexmask.long.tbyte 0x00 12.--31. 1. "TTBR_31_12,Bits [31:12] of translation table base address"
hexmask.long.word 0x00 0.--11. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x1F9D4++0x03
line.long 0x00 "IMTTUBR015,Note: n= 0 to 15 (IPMMU context) This register indicates the base address of the TLB managed by each MMU"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "TTBR_39_32,Bits [39:32] of translation table base address This field is used when EAE is 1"
group.long 0x1F9D8++0x03
line.long 0x00 "IMTTLBR115,Note: n= 0 to 15 (IPMMU context) This register indicates the base address of the TLB managed by each MMU"
hexmask.long.tbyte 0x00 12.--31. 1. "TTBR_31_12,Bits [31:12] of translation table base address"
hexmask.long.word 0x00 0.--11. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x1F9DC++0x03
line.long 0x00 "IMTTUBR115,Note: n= 0 to 15 (IPMMU context) This register indicates the base address of the TLB managed by each MMU"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "TTBR_39_32,Bits [39:32] of translation table base address This field is used when EAE is 1"
group.long 0x1F9E0++0x03
line.long 0x00 "IMSTR15,Note: n= 0 to 15 (IPMMU context) This register indicates the error status of during address translation"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved These bits are always read as 0"
bitfld.long 0x00 12.--13. "ERRLVL_1_0,indicate which level of page table walk caused the error" "0: Level1 page table walk,1: Level2 page table walk,2: Level3 page table walk,?..."
newline
rbitfld.long 0x00 11. "Reserved_11,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 8.--10. "ERRCODE_2_0,Indicate error type" "?,1: Translation Fault,?,?,4: Access Flag Fault / Permission Fault,5: Secure Access Fault Others: reserved,?..."
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4. "MHIT,TLB Conflict Fault Indicate that multiple TLB hits occurred" "0,1"
newline
rbitfld.long 0x00 3. "Reserved_3,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 2. "ABORT,This bit is set to 1 when the IPMMU received an error response during a page table walk" "0,1"
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bitfld.long 0x00 1. "PF,Permission Fault This bit is set to 1 when an access right violation occurred" "0,1"
bitfld.long 0x00 0. "TF,Translation Fault This bit is set to 1 when a translation fault occurred during a page table walk" "0,1"
group.long 0x1F9E8++0x03
line.long 0x00 "IMMAIR015,(Short-descriptor translation format)"
abitfld.long 0x00 24.--31. "NOS7_0,Outer Shareable property mapping for memory attributes n" "0x00=0: Memory region is outer shareable,0x01=1: Memory region is inner shareable"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 19. "NS1,Mapping of S = 1 attribute for Normal memory" "0: Region is not shareable,1: Region is shareable"
bitfld.long 0x00 18. "NS0,Mapping of S = 0 attribute for Normal memory" "0: Region is not shareable,1: Region is shareable"
newline
bitfld.long 0x00 17. "DS1,Mapping of S = 1 attribute for Device memory" "0: Region is not shareable,1: Region is shareable"
bitfld.long 0x00 16. "DS0,Mapping of S = 0 attribute for Device memory" "0: Region is not shareable,1: Region is shareable"
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bitfld.long 0x00 14.--15. "TR7_1_0,Primary TEX mapping for memory attributes 7" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
bitfld.long 0x00 12.--13. "TR6_1_0,Primary TEX mapping for memory attributes 6" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
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bitfld.long 0x00 10.--11. "TR5_1_0,Primary TEX mapping for memory attributes 5" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
bitfld.long 0x00 8.--9. "TR4_1_0,Primary TEX mapping for memory attributes 4" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
newline
bitfld.long 0x00 6.--7. "TR3_1_0,Primary TEX mapping for memory attributes 3" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
bitfld.long 0x00 4.--5. "TR2_1_0,Primary TEX mapping for memory attributes 2" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
newline
bitfld.long 0x00 2.--3. "TR1_1_0,Primary TEX mapping for memory attributes 1" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
bitfld.long 0x00 0.--1. "TR0_1_0,Primary TEX mapping for memory attributes 0" "0: Strongly-ordered,1: Device,2: Normal memory,3: Reserved"
group.long 0x1F9EC++0x03
line.long 0x00 "IMMAIR115,(Short-descriptor translation format)"
bitfld.long 0x00 30.--31. "OR7_1_0,Outer Cacheable property mapping for memory attributes 7" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 28.--29. "OR6_1_0,Outer Cacheable property mapping for memory attributes 6" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
newline
bitfld.long 0x00 26.--27. "OR5_1_0,Outer Cacheable property mapping for memory attributes 5" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 24.--25. "OR4_1_0,Outer Cacheable property mapping for memory attributes 4" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 22.--23. "OR3_1_0,Outer Cacheable property mapping for memory attributes 3" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 20.--21. "OR2_1_0,Outer Cacheable property mapping for memory attributes 2" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
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bitfld.long 0x00 18.--19. "OR1_1_0,Outer Cacheable property mapping for memory attributes 1" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 16.--17. "OR0_1_0,Outer Cacheable property mapping for memory attributes 0" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
newline
bitfld.long 0x00 14.--15. "IR7_1_0,Inner Cacheable property mapping for memory attributes 7" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 12.--13. "IR6_1_0,Inner Cacheable property mapping for memory attributes 6" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
newline
bitfld.long 0x00 10.--11. "IR5_1_0,Inner Cacheable property mapping for memory attributes 5" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 8.--9. "IR4_1_0,Inner Cacheable property mapping for memory attributes 4" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
newline
bitfld.long 0x00 6.--7. "IR3_1_0,Inner Cacheable property mapping for memory attributes 3" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 4.--5. "IR2_1_0,Inner Cacheable property mapping for memory attributes 2" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
newline
bitfld.long 0x00 2.--3. "IR1_1_0,Inner Cacheable property mapping for memory attributes 1" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
bitfld.long 0x00 0.--1. "IR0_1_0,Inner Cacheable property mapping for memory attributes 0" "0: Region is non-cacheable,1: Region is write-back write-allocate,2: Region is write-through no write-allocate,3: Region is write-back no write-allocate"
group.long 0x1F9F0++0x03
line.long 0x00 "IMELAR15,Note: n= 0 to 15 (IPMMU context) This register indicates the address which an address translation error occurred"
hexmask.long 0x00 0.--31. 1. "EAR_31_0,The faulting virtual address is set when an address translation error occurred"
group.long 0x1F9F4++0x03
line.long 0x00 "IMEUAR15,Note: n= 0 to 15 (IPMMU context) This register indicates the address which an address translation error occurred"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "EAR_39_32,The faulting virtual address is set when an address translation error occurred"
tree.end
tree.end
tree "DMAC"
tree "DMAC_INST_0"
base ad:0xFFD60000
group.word 0x60++0x01
line.word 0x00 "RDMOR_0,DMOR is a 16-bit readable/writable register which control master enable and specifies the priority level of all DMA channels"
rbitfld.word 0x00 10.--15. "Reserved_10,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.word 0x00 8.--9. "PR_1_0,Priority Mode Select the priority level between channels when there are transfer requests for multiple channels simultaneously" "0: CH0 > CH1 > CH2 > & > CH15,?,?,3: Round-robin mode Other than above"
newline
rbitfld.word 0x00 3.--7. "Reserved_3,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.word 0x00 2. "AE,Address Error Flag Indicates that an address error interrupt occurred during DMA transfer" "0: No SYS-DMAC address error interrupt [Clearing,1: SYS-DMAC address error interrupt occurs during"
newline
rbitfld.word 0x00 1. "Reserved_1,Reserved This bit is always read as 0" "0,1"
newline
bitfld.word 0x00 0. "DME,DMA Master Enable Enables or disables DMA transfers on all channels" "0: Disables DMA transfers on all channels,1: Enables DMA transfers on all channels"
group.long 0xA0++0x03
line.long 0x00 "RDMDPSEC_0,DPSEC is a 32-bit readable/writeable register that controls the secure attribute of Descriptor Memory"
bitfld.long 0x00 31. "DPSEC,Secure attribute setting of Descriptor memory Specify the secure attribute of address spaces of Descriptor memory" "0: nonsecure attribute,1: secure attribute"
newline
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.long.word 0x00 16.--24. 1. "DPSECA_8_0,Secure attribute base address of Descriptor memory Specify the secure attribute base address of Descriptor memory"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--8. 1. "DPSECM_8_0,Secure attribute base address mask of Descriptor memory Specify the secure attribute base address mask of Descriptor memory"
group.long 0xA4++0x03
line.long 0x00 "RDMBUFMODE_0,BUFMODE is a 32-bit readable/writeable register that controls the partial outstanding function mode"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 0. "BUFMODE,Partial OS enable" "0: Normal OS Ch0-15 256Bx2outst,1: Partial OS Ch0-3 256Bx4outst CH4-7 256Bx2outst"
group.long 0xC0++0x03
line.long 0x00 "RDMERRDET_0,"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 0. "ERROR_DETECT,Secure Error" "0: No Error,1: Secure Error write 1"
group.long 0xC4++0x03
line.long 0x00 "RDMERRADR_0,"
hexmask.long 0x00 0.--31. 1. "ERROR_ADDR_31_0,Secure Error APB address clear by write 1 to ERROR_DETECT_OUT"
group.long 0xC8++0x03
line.long 0x00 "RDMERRPID_0,"
hexmask.long 0x00 0.--31. 1. "ERROR_PID_31_0,Secure error APB ID clear by write 1 to ERROR_DETECT_OUT"
group.long 0xCC++0x03
line.long 0x00 "RDMADRFB_0,ADRFB is 32-bit readable/writable register that specify the control of address feedback of DPRAM"
bitfld.long 0x00 31. "ADDRFB_EN,Address Feedback Enable" "0: Disable and,1: Enable"
newline
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.long.word 0x00 16.--24. 1. "REF_A_8_0,Reference address when comparing"
newline
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 1. "P_ADDRFB_ERR_POST,Address Feedback Post-Fault injection" "0: No fault injection,1: Fault injection"
newline
bitfld.long 0x00 0. "P_ADDRFB_ERR_PRE,Address Feedback Pre-Fault injection" "0: No fault injection,1: Fault injection"
group.long 0xD0++0x03
line.long 0x00 "RDMAPBEDC_0,APBEDC is 32-bit readable/writable register that specify the control APBEDC injection and EDC error status"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 19. "PWDATA_PUBLIC_ERR,PUBLIC PWDATA EDC error status" "0: normal,1: Error"
newline
rbitfld.long 0x00 18. "PADDR_PUBLIC_ERR,PUBLIC PADDR EDC error status" "0: normal,1: Error"
newline
rbitfld.long 0x00 17. "PWDATA_CH_ERR,CH PWDATA EDC error status" "0: normal,1: Error"
newline
rbitfld.long 0x00 16. "PADDR_CH_ERR,CH PWDATA EDC error status" "0: normal,1: Error"
newline
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 1. "P_APBPUBLIC_ERR,PUBLIC APB I/F Fault injection" "0: No fault injection Read always be 0,1: Fault injection"
newline
bitfld.long 0x00 0. "P_APBCH_ERR,CH APB I/F Fault injection" "0: No fault injection Read always be 0,1: Fault injection"
group.long 0xD4++0x03
line.long 0x00 "RDMAPB_CH_PADDR_0,APB_CH_PADDR is 32-bit readable register that specify the EDC error information"
hexmask.long 0x00 0.--31. 1. "PADDR_31_0,CH EDC error PADDR information"
group.long 0xD8++0x03
line.long 0x00 "RDMAPB_CH_PWDATA_0,APB_CH_PWDATA is 32-bit readable register that specify the EDC error information"
hexmask.long 0x00 0.--31. 1. "PWDATA_31_0,CH EDC error PADDR information"
group.long 0xDC++0x03
line.long 0x00 "RDMAPB_PUBLIC_PADDR_0,APB_PUBLIC_PADDR is 32-bit readable register that specify the EDC error information"
hexmask.long 0x00 0.--31. 1. "PADDR_31_0,PUBLIC EDC error PADDR information"
group.long 0xE0++0x03
line.long 0x00 "RDMAPB_PUBLIC_PWDATA_0,APB_PUBLIC_PWDATA is 32-bit readable register that specify the EDC error information"
hexmask.long 0x00 0.--31. 1. "PWDATA_31_0,PUBLIC EDC error PADDR information"
group.long 0xF0++0x03
line.long 0x00 "RDMCMP_STAUS_0,DMCMP_STATUS is 32-bit readable/writable register that specify the control of DCLS comparison and error status"
bitfld.long 0x00 31. "EN,DCLS compare enable" "0: Disable and Clear error,1: Enable and detect"
newline
bitfld.long 0x00 30. "P_ERR_POST,Post-Fault Injection" "0: Disable Fault injection,1: Fault Injection (Pseudo error)"
newline
hexmask.long.word 0x00 17.--29. 1. "Reserved_17,Reserved"
newline
bitfld.long 0x00 16. "P_ERR_PRE,Pre-Fault Injection" "0: Disable Fault injection,1: Fault Injection (Pseudo error)"
newline
hexmask.long.word 0x00 5.--15. 1. "Reserved_5,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 4. "E_PERI,Error status on PERI AXI I/F" "0,1"
newline
rbitfld.long 0x00 3. "E_MEM,Error status on MEM AXI I/F" "0,1"
newline
rbitfld.long 0x00 2. "E_BUS,Error status on BUS AXI I/F" "0,1"
newline
rbitfld.long 0x00 1. "E_APB,Error status on APB I/F" "0,1"
newline
rbitfld.long 0x00 0. "E_OTH,Error status on other signals" "0,1"
group.long 0xF4++0x03
line.long 0x00 "RDMRATE_RD_0,RRATE_RD is 32-bit readable/writable register that specify the control of rate control of BUS I/F"
bitfld.long 0x00 31. "RATE_RD_ACCESS_CNT_EN,Rate Control for read Enable" "0: Disable,1: Enable"
newline
hexmask.long.tbyte 0x00 8.--30. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "RATE_RD_ACCESS_CNT,Rate Control counter setting for read transaction Period of time of a transaction =(CNT + 1) * 2 + 3 (clock cycle) 0-2"
group.long 0xF8++0x03
line.long 0x00 "RDMRATE_WR_0,RRATE_WR is 32-bit readable/writable register that specify the control of rate control of BUS I/F"
bitfld.long 0x00 31. "RATE_WR_ACCESS_CNT_EN,Rate Control for write Enable" "0: Disable,1: Enable"
newline
hexmask.long.tbyte 0x00 8.--30. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "RATE_WR_ACCESS_CNT,Rate Control counter setting for write transaction Period of time of a transaction =(CNT + 1) * 2 + 3 (clock cycle) 0-2"
tree.end
tree "DMAC_INST_1"
base ad:0xFFD61000
group.word 0x60++0x01
line.word 0x00 "RDMOR_1,DMOR is a 16-bit readable/writable register which control master enable and specifies the priority level of all DMA channels"
rbitfld.word 0x00 10.--15. "Reserved_10,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.word 0x00 8.--9. "PR_1_0,Priority Mode Select the priority level between channels when there are transfer requests for multiple channels simultaneously" "0: CH0 > CH1 > CH2 > & > CH15,?,?,3: Round-robin mode Other than above"
newline
rbitfld.word 0x00 3.--7. "Reserved_3,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.word 0x00 2. "AE,Address Error Flag Indicates that an address error interrupt occurred during DMA transfer" "0: No SYS-DMAC address error interrupt [Clearing,1: SYS-DMAC address error interrupt occurs during"
newline
rbitfld.word 0x00 1. "Reserved_1,Reserved This bit is always read as 0" "0,1"
newline
bitfld.word 0x00 0. "DME,DMA Master Enable Enables or disables DMA transfers on all channels" "0: Disables DMA transfers on all channels,1: Enables DMA transfers on all channels"
group.long 0xA0++0x03
line.long 0x00 "RDMDPSEC_1,DPSEC is a 32-bit readable/writeable register that controls the secure attribute of Descriptor Memory"
bitfld.long 0x00 31. "DPSEC,Secure attribute setting of Descriptor memory Specify the secure attribute of address spaces of Descriptor memory" "0: nonsecure attribute,1: secure attribute"
newline
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.long.word 0x00 16.--24. 1. "DPSECA_8_0,Secure attribute base address of Descriptor memory Specify the secure attribute base address of Descriptor memory"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--8. 1. "DPSECM_8_0,Secure attribute base address mask of Descriptor memory Specify the secure attribute base address mask of Descriptor memory"
group.long 0xA4++0x03
line.long 0x00 "RDMBUFMODE_1,BUFMODE is a 32-bit readable/writeable register that controls the partial outstanding function mode"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 0. "BUFMODE,Partial OS enable" "0: Normal OS Ch0-15 256Bx2outst,1: Partial OS Ch0-3 256Bx4outst CH4-7 256Bx2outst"
group.long 0xC0++0x03
line.long 0x00 "RDMERRDET_1,"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 0. "ERROR_DETECT,Secure Error" "0: No Error,1: Secure Error write 1"
group.long 0xC4++0x03
line.long 0x00 "RDMERRADR_1,"
hexmask.long 0x00 0.--31. 1. "ERROR_ADDR_31_0,Secure Error APB address clear by write 1 to ERROR_DETECT_OUT"
group.long 0xC8++0x03
line.long 0x00 "RDMERRPID_1,"
hexmask.long 0x00 0.--31. 1. "ERROR_PID_31_0,Secure error APB ID clear by write 1 to ERROR_DETECT_OUT"
group.long 0xCC++0x03
line.long 0x00 "RDMADRFB_1,ADRFB is 32-bit readable/writable register that specify the control of address feedback of DPRAM"
bitfld.long 0x00 31. "ADDRFB_EN,Address Feedback Enable" "0: Disable and,1: Enable"
newline
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.long.word 0x00 16.--24. 1. "REF_A_8_0,Reference address when comparing"
newline
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 1. "P_ADDRFB_ERR_POST,Address Feedback Post-Fault injection" "0: No fault injection,1: Fault injection"
newline
bitfld.long 0x00 0. "P_ADDRFB_ERR_PRE,Address Feedback Pre-Fault injection" "0: No fault injection,1: Fault injection"
group.long 0xD0++0x03
line.long 0x00 "RDMAPBEDC_1,APBEDC is 32-bit readable/writable register that specify the control APBEDC injection and EDC error status"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 19. "PWDATA_PUBLIC_ERR,PUBLIC PWDATA EDC error status" "0: normal,1: Error"
newline
rbitfld.long 0x00 18. "PADDR_PUBLIC_ERR,PUBLIC PADDR EDC error status" "0: normal,1: Error"
newline
rbitfld.long 0x00 17. "PWDATA_CH_ERR,CH PWDATA EDC error status" "0: normal,1: Error"
newline
rbitfld.long 0x00 16. "PADDR_CH_ERR,CH PWDATA EDC error status" "0: normal,1: Error"
newline
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 1. "P_APBPUBLIC_ERR,PUBLIC APB I/F Fault injection" "0: No fault injection Read always be 0,1: Fault injection"
newline
bitfld.long 0x00 0. "P_APBCH_ERR,CH APB I/F Fault injection" "0: No fault injection Read always be 0,1: Fault injection"
group.long 0xD4++0x03
line.long 0x00 "RDMAPB_CH_PADDR_1,APB_CH_PADDR is 32-bit readable register that specify the EDC error information"
hexmask.long 0x00 0.--31. 1. "PADDR_31_0,CH EDC error PADDR information"
group.long 0xD8++0x03
line.long 0x00 "RDMAPB_CH_PWDATA_1,APB_CH_PWDATA is 32-bit readable register that specify the EDC error information"
hexmask.long 0x00 0.--31. 1. "PWDATA_31_0,CH EDC error PADDR information"
group.long 0xDC++0x03
line.long 0x00 "RDMAPB_PUBLIC_PADDR_1,APB_PUBLIC_PADDR is 32-bit readable register that specify the EDC error information"
hexmask.long 0x00 0.--31. 1. "PADDR_31_0,PUBLIC EDC error PADDR information"
group.long 0xE0++0x03
line.long 0x00 "RDMAPB_PUBLIC_PWDATA_1,APB_PUBLIC_PWDATA is 32-bit readable register that specify the EDC error information"
hexmask.long 0x00 0.--31. 1. "PWDATA_31_0,PUBLIC EDC error PADDR information"
group.long 0xF0++0x03
line.long 0x00 "RDMCMP_STAUS_1,DMCMP_STATUS is 32-bit readable/writable register that specify the control of DCLS comparison and error status"
bitfld.long 0x00 31. "EN,DCLS compare enable" "0: Disable and Clear error,1: Enable and detect"
newline
bitfld.long 0x00 30. "P_ERR_POST,Post-Fault Injection" "0: Disable Fault injection,1: Fault Injection (Pseudo error)"
newline
hexmask.long.word 0x00 17.--29. 1. "Reserved_17,Reserved"
newline
bitfld.long 0x00 16. "P_ERR_PRE,Pre-Fault Injection" "0: Disable Fault injection,1: Fault Injection (Pseudo error)"
newline
hexmask.long.word 0x00 5.--15. 1. "Reserved_5,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 4. "E_PERI,Error status on PERI AXI I/F" "0,1"
newline
rbitfld.long 0x00 3. "E_MEM,Error status on MEM AXI I/F" "0,1"
newline
rbitfld.long 0x00 2. "E_BUS,Error status on BUS AXI I/F" "0,1"
newline
rbitfld.long 0x00 1. "E_APB,Error status on APB I/F" "0,1"
newline
rbitfld.long 0x00 0. "E_OTH,Error status on other signals" "0,1"
group.long 0xF4++0x03
line.long 0x00 "RDMRATE_RD_1,RRATE_RD is 32-bit readable/writable register that specify the control of rate control of BUS I/F"
bitfld.long 0x00 31. "RATE_RD_ACCESS_CNT_EN,Rate Control for read Enable" "0: Disable,1: Enable"
newline
hexmask.long.tbyte 0x00 8.--30. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "RATE_RD_ACCESS_CNT,Rate Control counter setting for read transaction Period of time of a transaction =(CNT + 1) * 2 + 3 (clock cycle) 0-2"
group.long 0xF8++0x03
line.long 0x00 "RDMRATE_WR_1,RRATE_WR is 32-bit readable/writable register that specify the control of rate control of BUS I/F"
bitfld.long 0x00 31. "RATE_WR_ACCESS_CNT_EN,Rate Control for write Enable" "0: Disable,1: Enable"
newline
hexmask.long.tbyte 0x00 8.--30. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "RATE_WR_ACCESS_CNT,Rate Control counter setting for write transaction Period of time of a transaction =(CNT + 1) * 2 + 3 (clock cycle) 0-2"
tree.end
tree "DMAC_INST_2"
base ad:0xFFD62000
group.word 0x60++0x01
line.word 0x00 "RDMOR_2,DMOR is a 16-bit readable/writable register which control master enable and specifies the priority level of all DMA channels"
rbitfld.word 0x00 10.--15. "Reserved_10,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.word 0x00 8.--9. "PR_1_0,Priority Mode Select the priority level between channels when there are transfer requests for multiple channels simultaneously" "0: CH0 > CH1 > CH2 > & > CH15,?,?,3: Round-robin mode Other than above"
newline
rbitfld.word 0x00 3.--7. "Reserved_3,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.word 0x00 2. "AE,Address Error Flag Indicates that an address error interrupt occurred during DMA transfer" "0: No SYS-DMAC address error interrupt [Clearing,1: SYS-DMAC address error interrupt occurs during"
newline
rbitfld.word 0x00 1. "Reserved_1,Reserved This bit is always read as 0" "0,1"
newline
bitfld.word 0x00 0. "DME,DMA Master Enable Enables or disables DMA transfers on all channels" "0: Disables DMA transfers on all channels,1: Enables DMA transfers on all channels"
group.long 0xA0++0x03
line.long 0x00 "RDMDPSEC_2,DPSEC is a 32-bit readable/writeable register that controls the secure attribute of Descriptor Memory"
bitfld.long 0x00 31. "DPSEC,Secure attribute setting of Descriptor memory Specify the secure attribute of address spaces of Descriptor memory" "0: nonsecure attribute,1: secure attribute"
newline
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.long.word 0x00 16.--24. 1. "DPSECA_8_0,Secure attribute base address of Descriptor memory Specify the secure attribute base address of Descriptor memory"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--8. 1. "DPSECM_8_0,Secure attribute base address mask of Descriptor memory Specify the secure attribute base address mask of Descriptor memory"
group.long 0xA4++0x03
line.long 0x00 "RDMBUFMODE_2,BUFMODE is a 32-bit readable/writeable register that controls the partial outstanding function mode"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 0. "BUFMODE,Partial OS enable" "0: Normal OS Ch0-15 256Bx2outst,1: Partial OS Ch0-3 256Bx4outst CH4-7 256Bx2outst"
group.long 0xC0++0x03
line.long 0x00 "RDMERRDET_2,"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 0. "ERROR_DETECT,Secure Error" "0: No Error,1: Secure Error write 1"
group.long 0xC4++0x03
line.long 0x00 "RDMERRADR_2,"
hexmask.long 0x00 0.--31. 1. "ERROR_ADDR_31_0,Secure Error APB address clear by write 1 to ERROR_DETECT_OUT"
group.long 0xC8++0x03
line.long 0x00 "RDMERRPID_2,"
hexmask.long 0x00 0.--31. 1. "ERROR_PID_31_0,Secure error APB ID clear by write 1 to ERROR_DETECT_OUT"
group.long 0xCC++0x03
line.long 0x00 "RDMADRFB_2,ADRFB is 32-bit readable/writable register that specify the control of address feedback of DPRAM"
bitfld.long 0x00 31. "ADDRFB_EN,Address Feedback Enable" "0: Disable and,1: Enable"
newline
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.long.word 0x00 16.--24. 1. "REF_A_8_0,Reference address when comparing"
newline
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 1. "P_ADDRFB_ERR_POST,Address Feedback Post-Fault injection" "0: No fault injection,1: Fault injection"
newline
bitfld.long 0x00 0. "P_ADDRFB_ERR_PRE,Address Feedback Pre-Fault injection" "0: No fault injection,1: Fault injection"
group.long 0xD0++0x03
line.long 0x00 "RDMAPBEDC_2,APBEDC is 32-bit readable/writable register that specify the control APBEDC injection and EDC error status"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 19. "PWDATA_PUBLIC_ERR,PUBLIC PWDATA EDC error status" "0: normal,1: Error"
newline
rbitfld.long 0x00 18. "PADDR_PUBLIC_ERR,PUBLIC PADDR EDC error status" "0: normal,1: Error"
newline
rbitfld.long 0x00 17. "PWDATA_CH_ERR,CH PWDATA EDC error status" "0: normal,1: Error"
newline
rbitfld.long 0x00 16. "PADDR_CH_ERR,CH PWDATA EDC error status" "0: normal,1: Error"
newline
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 1. "P_APBPUBLIC_ERR,PUBLIC APB I/F Fault injection" "0: No fault injection Read always be 0,1: Fault injection"
newline
bitfld.long 0x00 0. "P_APBCH_ERR,CH APB I/F Fault injection" "0: No fault injection Read always be 0,1: Fault injection"
group.long 0xD4++0x03
line.long 0x00 "RDMAPB_CH_PADDR_2,APB_CH_PADDR is 32-bit readable register that specify the EDC error information"
hexmask.long 0x00 0.--31. 1. "PADDR_31_0,CH EDC error PADDR information"
group.long 0xD8++0x03
line.long 0x00 "RDMAPB_CH_PWDATA_2,APB_CH_PWDATA is 32-bit readable register that specify the EDC error information"
hexmask.long 0x00 0.--31. 1. "PWDATA_31_0,CH EDC error PADDR information"
group.long 0xDC++0x03
line.long 0x00 "RDMAPB_PUBLIC_PADDR_2,APB_PUBLIC_PADDR is 32-bit readable register that specify the EDC error information"
hexmask.long 0x00 0.--31. 1. "PADDR_31_0,PUBLIC EDC error PADDR information"
group.long 0xE0++0x03
line.long 0x00 "RDMAPB_PUBLIC_PWDATA_2,APB_PUBLIC_PWDATA is 32-bit readable register that specify the EDC error information"
hexmask.long 0x00 0.--31. 1. "PWDATA_31_0,PUBLIC EDC error PADDR information"
group.long 0xF0++0x03
line.long 0x00 "RDMCMP_STAUS_2,DMCMP_STATUS is 32-bit readable/writable register that specify the control of DCLS comparison and error status"
bitfld.long 0x00 31. "EN,DCLS compare enable" "0: Disable and Clear error,1: Enable and detect"
newline
bitfld.long 0x00 30. "P_ERR_POST,Post-Fault Injection" "0: Disable Fault injection,1: Fault Injection (Pseudo error)"
newline
hexmask.long.word 0x00 17.--29. 1. "Reserved_17,Reserved"
newline
bitfld.long 0x00 16. "P_ERR_PRE,Pre-Fault Injection" "0: Disable Fault injection,1: Fault Injection (Pseudo error)"
newline
hexmask.long.word 0x00 5.--15. 1. "Reserved_5,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 4. "E_PERI,Error status on PERI AXI I/F" "0,1"
newline
rbitfld.long 0x00 3. "E_MEM,Error status on MEM AXI I/F" "0,1"
newline
rbitfld.long 0x00 2. "E_BUS,Error status on BUS AXI I/F" "0,1"
newline
rbitfld.long 0x00 1. "E_APB,Error status on APB I/F" "0,1"
newline
rbitfld.long 0x00 0. "E_OTH,Error status on other signals" "0,1"
group.long 0xF4++0x03
line.long 0x00 "RDMRATE_RD_2,RRATE_RD is 32-bit readable/writable register that specify the control of rate control of BUS I/F"
bitfld.long 0x00 31. "RATE_RD_ACCESS_CNT_EN,Rate Control for read Enable" "0: Disable,1: Enable"
newline
hexmask.long.tbyte 0x00 8.--30. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "RATE_RD_ACCESS_CNT,Rate Control counter setting for read transaction Period of time of a transaction =(CNT + 1) * 2 + 3 (clock cycle) 0-2"
group.long 0xF8++0x03
line.long 0x00 "RDMRATE_WR_2,RRATE_WR is 32-bit readable/writable register that specify the control of rate control of BUS I/F"
bitfld.long 0x00 31. "RATE_WR_ACCESS_CNT_EN,Rate Control for write Enable" "0: Disable,1: Enable"
newline
hexmask.long.tbyte 0x00 8.--30. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "RATE_WR_ACCESS_CNT,Rate Control counter setting for write transaction Period of time of a transaction =(CNT + 1) * 2 + 3 (clock cycle) 0-2"
tree.end
tree "DMAC_INST_3"
base ad:0xFFD63000
group.word 0x60++0x01
line.word 0x00 "RDMOR_3,DMOR is a 16-bit readable/writable register which control master enable and specifies the priority level of all DMA channels"
rbitfld.word 0x00 10.--15. "Reserved_10,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.word 0x00 8.--9. "PR_1_0,Priority Mode Select the priority level between channels when there are transfer requests for multiple channels simultaneously" "0: CH0 > CH1 > CH2 > & > CH15,?,?,3: Round-robin mode Other than above"
newline
rbitfld.word 0x00 3.--7. "Reserved_3,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.word 0x00 2. "AE,Address Error Flag Indicates that an address error interrupt occurred during DMA transfer" "0: No SYS-DMAC address error interrupt [Clearing,1: SYS-DMAC address error interrupt occurs during"
newline
rbitfld.word 0x00 1. "Reserved_1,Reserved This bit is always read as 0" "0,1"
newline
bitfld.word 0x00 0. "DME,DMA Master Enable Enables or disables DMA transfers on all channels" "0: Disables DMA transfers on all channels,1: Enables DMA transfers on all channels"
group.long 0xA0++0x03
line.long 0x00 "RDMDPSEC_3,DPSEC is a 32-bit readable/writeable register that controls the secure attribute of Descriptor Memory"
bitfld.long 0x00 31. "DPSEC,Secure attribute setting of Descriptor memory Specify the secure attribute of address spaces of Descriptor memory" "0: nonsecure attribute,1: secure attribute"
newline
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.long.word 0x00 16.--24. 1. "DPSECA_8_0,Secure attribute base address of Descriptor memory Specify the secure attribute base address of Descriptor memory"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--8. 1. "DPSECM_8_0,Secure attribute base address mask of Descriptor memory Specify the secure attribute base address mask of Descriptor memory"
group.long 0xA4++0x03
line.long 0x00 "RDMBUFMODE_3,BUFMODE is a 32-bit readable/writeable register that controls the partial outstanding function mode"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 0. "BUFMODE,Partial OS enable" "0: Normal OS Ch0-15 256Bx2outst,1: Partial OS Ch0-3 256Bx4outst CH4-7 256Bx2outst"
group.long 0xC0++0x03
line.long 0x00 "RDMERRDET_3,"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 0. "ERROR_DETECT,Secure Error" "0: No Error,1: Secure Error write 1"
group.long 0xC4++0x03
line.long 0x00 "RDMERRADR_3,"
hexmask.long 0x00 0.--31. 1. "ERROR_ADDR_31_0,Secure Error APB address clear by write 1 to ERROR_DETECT_OUT"
group.long 0xC8++0x03
line.long 0x00 "RDMERRPID_3,"
hexmask.long 0x00 0.--31. 1. "ERROR_PID_31_0,Secure error APB ID clear by write 1 to ERROR_DETECT_OUT"
group.long 0xCC++0x03
line.long 0x00 "RDMADRFB_3,ADRFB is 32-bit readable/writable register that specify the control of address feedback of DPRAM"
bitfld.long 0x00 31. "ADDRFB_EN,Address Feedback Enable" "0: Disable and,1: Enable"
newline
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.long.word 0x00 16.--24. 1. "REF_A_8_0,Reference address when comparing"
newline
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 1. "P_ADDRFB_ERR_POST,Address Feedback Post-Fault injection" "0: No fault injection,1: Fault injection"
newline
bitfld.long 0x00 0. "P_ADDRFB_ERR_PRE,Address Feedback Pre-Fault injection" "0: No fault injection,1: Fault injection"
group.long 0xD0++0x03
line.long 0x00 "RDMAPBEDC_3,APBEDC is 32-bit readable/writable register that specify the control APBEDC injection and EDC error status"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 19. "PWDATA_PUBLIC_ERR,PUBLIC PWDATA EDC error status" "0: normal,1: Error"
newline
rbitfld.long 0x00 18. "PADDR_PUBLIC_ERR,PUBLIC PADDR EDC error status" "0: normal,1: Error"
newline
rbitfld.long 0x00 17. "PWDATA_CH_ERR,CH PWDATA EDC error status" "0: normal,1: Error"
newline
rbitfld.long 0x00 16. "PADDR_CH_ERR,CH PWDATA EDC error status" "0: normal,1: Error"
newline
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 1. "P_APBPUBLIC_ERR,PUBLIC APB I/F Fault injection" "0: No fault injection Read always be 0,1: Fault injection"
newline
bitfld.long 0x00 0. "P_APBCH_ERR,CH APB I/F Fault injection" "0: No fault injection Read always be 0,1: Fault injection"
group.long 0xD4++0x03
line.long 0x00 "RDMAPB_CH_PADDR_3,APB_CH_PADDR is 32-bit readable register that specify the EDC error information"
hexmask.long 0x00 0.--31. 1. "PADDR_31_0,CH EDC error PADDR information"
group.long 0xD8++0x03
line.long 0x00 "RDMAPB_CH_PWDATA_3,APB_CH_PWDATA is 32-bit readable register that specify the EDC error information"
hexmask.long 0x00 0.--31. 1. "PWDATA_31_0,CH EDC error PADDR information"
group.long 0xDC++0x03
line.long 0x00 "RDMAPB_PUBLIC_PADDR_3,APB_PUBLIC_PADDR is 32-bit readable register that specify the EDC error information"
hexmask.long 0x00 0.--31. 1. "PADDR_31_0,PUBLIC EDC error PADDR information"
group.long 0xE0++0x03
line.long 0x00 "RDMAPB_PUBLIC_PWDATA_3,APB_PUBLIC_PWDATA is 32-bit readable register that specify the EDC error information"
hexmask.long 0x00 0.--31. 1. "PWDATA_31_0,PUBLIC EDC error PADDR information"
group.long 0xF0++0x03
line.long 0x00 "RDMCMP_STAUS_3,DMCMP_STATUS is 32-bit readable/writable register that specify the control of DCLS comparison and error status"
bitfld.long 0x00 31. "EN,DCLS compare enable" "0: Disable and Clear error,1: Enable and detect"
newline
bitfld.long 0x00 30. "P_ERR_POST,Post-Fault Injection" "0: Disable Fault injection,1: Fault Injection (Pseudo error)"
newline
hexmask.long.word 0x00 17.--29. 1. "Reserved_17,Reserved"
newline
bitfld.long 0x00 16. "P_ERR_PRE,Pre-Fault Injection" "0: Disable Fault injection,1: Fault Injection (Pseudo error)"
newline
hexmask.long.word 0x00 5.--15. 1. "Reserved_5,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 4. "E_PERI,Error status on PERI AXI I/F" "0,1"
newline
rbitfld.long 0x00 3. "E_MEM,Error status on MEM AXI I/F" "0,1"
newline
rbitfld.long 0x00 2. "E_BUS,Error status on BUS AXI I/F" "0,1"
newline
rbitfld.long 0x00 1. "E_APB,Error status on APB I/F" "0,1"
newline
rbitfld.long 0x00 0. "E_OTH,Error status on other signals" "0,1"
group.long 0xF4++0x03
line.long 0x00 "RDMRATE_RD_3,RRATE_RD is 32-bit readable/writable register that specify the control of rate control of BUS I/F"
bitfld.long 0x00 31. "RATE_RD_ACCESS_CNT_EN,Rate Control for read Enable" "0: Disable,1: Enable"
newline
hexmask.long.tbyte 0x00 8.--30. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "RATE_RD_ACCESS_CNT,Rate Control counter setting for read transaction Period of time of a transaction =(CNT + 1) * 2 + 3 (clock cycle) 0-2"
group.long 0xF8++0x03
line.long 0x00 "RDMRATE_WR_3,RRATE_WR is 32-bit readable/writable register that specify the control of rate control of BUS I/F"
bitfld.long 0x00 31. "RATE_WR_ACCESS_CNT_EN,Rate Control for write Enable" "0: Disable,1: Enable"
newline
hexmask.long.tbyte 0x00 8.--30. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "RATE_WR_ACCESS_CNT,Rate Control counter setting for write transaction Period of time of a transaction =(CNT + 1) * 2 + 3 (clock cycle) 0-2"
tree.end
tree "DMAC_INST_4"
base ad:0xFFC10000
group.long 0x00++0x03
line.long 0x00 "RDMSAR_0_0,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0x04++0x03
line.long 0x00 "RDMDAR_0_0,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0x08++0x03
line.long 0x00 "RDMTCR_0_0,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0x0C++0x03
line.long 0x00 "RDMCHCR_0_0,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
newline
bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
newline
rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
newline
bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
newline
bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
newline
bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
newline
bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0x10++0x03
line.long 0x00 "RDMFIXSAR_0_0,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0x14++0x03
line.long 0x00 "RDMFIXDAR_0_0,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0x18++0x03
line.long 0x00 "RDMTCRB_0_0,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0x1C++0x03
line.long 0x00 "RDMCHCRB_0_0,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
newline
bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
newline
rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
newline
rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
newline
bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0x28++0x03
line.long 0x00 "RDMTSR_0_0,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0x38++0x03
line.long 0x00 "RDMTSRB_0_0,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0x40++0x01
line.word 0x00 "RDMRS_0_0,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0x48++0x03
line.long 0x00 "RDMBUFCR_0_0,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
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rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0x50++0x03
line.long 0x00 "RDMDPBASE_0_0,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0x54++0x03
line.long 0x00 "RDMDPCR_0_0,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x58++0x03
line.long 0x00 "RDMDPEVTCR_0_0,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
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bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
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bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x5C++0x03
line.long 0x00 "RDMDPEVTCNT_0_0,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
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hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0x60++0x03
line.long 0x00 "RDMFIXDPBASE_0_0,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0x64++0x03
line.long 0x00 "RDMDREQOS_0_0,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0x78++0x03
line.long 0x00 "RDMREGIONID_0_0,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x80++0x03
line.long 0x00 "RDMCHID_0_0,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB0++0x03
line.long 0x00 "RDMSEC_0_0,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0x100++0x03
line.long 0x00 "RDMCHCLR_0_0,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0x110++0x03
line.long 0x00 "RDMISTA_0_0,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
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hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0x1000++0x03
line.long 0x00 "RDMSAR_0_1,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0x1004++0x03
line.long 0x00 "RDMDAR_0_1,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0x1008++0x03
line.long 0x00 "RDMTCR_0_1,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0x100C++0x03
line.long 0x00 "RDMCHCR_0_1,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
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bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
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rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
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bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
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bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
newline
bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
newline
bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0x1010++0x03
line.long 0x00 "RDMFIXSAR_0_1,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0x1014++0x03
line.long 0x00 "RDMFIXDAR_0_1,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0x1018++0x03
line.long 0x00 "RDMTCRB_0_1,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0x101C++0x03
line.long 0x00 "RDMCHCRB_0_1,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
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bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
newline
rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
newline
rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
newline
bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0x1028++0x03
line.long 0x00 "RDMTSR_0_1,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0x1038++0x03
line.long 0x00 "RDMTSRB_0_1,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0x1040++0x01
line.word 0x00 "RDMRS_0_1,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0x1048++0x03
line.long 0x00 "RDMBUFCR_0_1,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
newline
rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0x1050++0x03
line.long 0x00 "RDMDPBASE_0_1,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0x1054++0x03
line.long 0x00 "RDMDPCR_0_1,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1058++0x03
line.long 0x00 "RDMDPEVTCR_0_1,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
newline
bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x105C++0x03
line.long 0x00 "RDMDPEVTCNT_0_1,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
newline
hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0x1060++0x03
line.long 0x00 "RDMFIXDPBASE_0_1,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0x1064++0x03
line.long 0x00 "RDMDREQOS_0_1,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0x1078++0x03
line.long 0x00 "RDMREGIONID_0_1,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1080++0x03
line.long 0x00 "RDMCHID_0_1,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x10B0++0x03
line.long 0x00 "RDMSEC_0_1,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0x1100++0x03
line.long 0x00 "RDMCHCLR_0_1,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0x1110++0x03
line.long 0x00 "RDMISTA_0_1,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
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hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0x2000++0x03
line.long 0x00 "RDMSAR_0_2,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0x2004++0x03
line.long 0x00 "RDMDAR_0_2,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0x2008++0x03
line.long 0x00 "RDMTCR_0_2,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0x200C++0x03
line.long 0x00 "RDMCHCR_0_2,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
newline
bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
newline
rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
newline
bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
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bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
newline
bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
newline
bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0x2010++0x03
line.long 0x00 "RDMFIXSAR_0_2,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0x2014++0x03
line.long 0x00 "RDMFIXDAR_0_2,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0x2018++0x03
line.long 0x00 "RDMTCRB_0_2,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0x201C++0x03
line.long 0x00 "RDMCHCRB_0_2,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
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bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
newline
rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
newline
rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
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bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0x2028++0x03
line.long 0x00 "RDMTSR_0_2,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0x2038++0x03
line.long 0x00 "RDMTSRB_0_2,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0x2040++0x01
line.word 0x00 "RDMRS_0_2,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0x2048++0x03
line.long 0x00 "RDMBUFCR_0_2,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
newline
rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0x2050++0x03
line.long 0x00 "RDMDPBASE_0_2,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0x2054++0x03
line.long 0x00 "RDMDPCR_0_2,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x2058++0x03
line.long 0x00 "RDMDPEVTCR_0_2,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
newline
bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x205C++0x03
line.long 0x00 "RDMDPEVTCNT_0_2,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
newline
hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0x2060++0x03
line.long 0x00 "RDMFIXDPBASE_0_2,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0x2064++0x03
line.long 0x00 "RDMDREQOS_0_2,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0x2078++0x03
line.long 0x00 "RDMREGIONID_0_2,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x2080++0x03
line.long 0x00 "RDMCHID_0_2,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x20B0++0x03
line.long 0x00 "RDMSEC_0_2,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0x2100++0x03
line.long 0x00 "RDMCHCLR_0_2,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0x2110++0x03
line.long 0x00 "RDMISTA_0_2,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
newline
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0x3000++0x03
line.long 0x00 "RDMSAR_0_3,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0x3004++0x03
line.long 0x00 "RDMDAR_0_3,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0x3008++0x03
line.long 0x00 "RDMTCR_0_3,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0x300C++0x03
line.long 0x00 "RDMCHCR_0_3,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
newline
bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
newline
rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
newline
bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
newline
bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
newline
bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
newline
bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0x3010++0x03
line.long 0x00 "RDMFIXSAR_0_3,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0x3014++0x03
line.long 0x00 "RDMFIXDAR_0_3,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0x3018++0x03
line.long 0x00 "RDMTCRB_0_3,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0x301C++0x03
line.long 0x00 "RDMCHCRB_0_3,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
newline
bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
newline
rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
newline
rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
newline
bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0x3028++0x03
line.long 0x00 "RDMTSR_0_3,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0x3038++0x03
line.long 0x00 "RDMTSRB_0_3,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0x3040++0x01
line.word 0x00 "RDMRS_0_3,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0x3048++0x03
line.long 0x00 "RDMBUFCR_0_3,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
newline
rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0x3050++0x03
line.long 0x00 "RDMDPBASE_0_3,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0x3054++0x03
line.long 0x00 "RDMDPCR_0_3,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x3058++0x03
line.long 0x00 "RDMDPEVTCR_0_3,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
newline
bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x305C++0x03
line.long 0x00 "RDMDPEVTCNT_0_3,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
newline
hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0x3060++0x03
line.long 0x00 "RDMFIXDPBASE_0_3,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0x3064++0x03
line.long 0x00 "RDMDREQOS_0_3,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0x3078++0x03
line.long 0x00 "RDMREGIONID_0_3,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x3080++0x03
line.long 0x00 "RDMCHID_0_3,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x30B0++0x03
line.long 0x00 "RDMSEC_0_3,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0x3100++0x03
line.long 0x00 "RDMCHCLR_0_3,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0x3110++0x03
line.long 0x00 "RDMISTA_0_3,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
newline
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0x4000++0x03
line.long 0x00 "RDMSAR_0_4,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0x4004++0x03
line.long 0x00 "RDMDAR_0_4,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0x4008++0x03
line.long 0x00 "RDMTCR_0_4,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0x400C++0x03
line.long 0x00 "RDMCHCR_0_4,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
newline
bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
newline
rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
newline
bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
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bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
newline
bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
newline
bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0x4010++0x03
line.long 0x00 "RDMFIXSAR_0_4,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0x4014++0x03
line.long 0x00 "RDMFIXDAR_0_4,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0x4018++0x03
line.long 0x00 "RDMTCRB_0_4,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0x401C++0x03
line.long 0x00 "RDMCHCRB_0_4,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
newline
bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
newline
rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
newline
rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
newline
bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0x4028++0x03
line.long 0x00 "RDMTSR_0_4,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0x4038++0x03
line.long 0x00 "RDMTSRB_0_4,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0x4040++0x01
line.word 0x00 "RDMRS_0_4,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0x4048++0x03
line.long 0x00 "RDMBUFCR_0_4,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
newline
rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0x4050++0x03
line.long 0x00 "RDMDPBASE_0_4,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0x4054++0x03
line.long 0x00 "RDMDPCR_0_4,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4058++0x03
line.long 0x00 "RDMDPEVTCR_0_4,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
newline
bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x405C++0x03
line.long 0x00 "RDMDPEVTCNT_0_4,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
newline
hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0x4060++0x03
line.long 0x00 "RDMFIXDPBASE_0_4,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0x4064++0x03
line.long 0x00 "RDMDREQOS_0_4,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0x4078++0x03
line.long 0x00 "RDMREGIONID_0_4,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4080++0x03
line.long 0x00 "RDMCHID_0_4,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x40B0++0x03
line.long 0x00 "RDMSEC_0_4,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0x4100++0x03
line.long 0x00 "RDMCHCLR_0_4,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0x4110++0x03
line.long 0x00 "RDMISTA_0_4,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
newline
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0x5000++0x03
line.long 0x00 "RDMSAR_0_5,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0x5004++0x03
line.long 0x00 "RDMDAR_0_5,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0x5008++0x03
line.long 0x00 "RDMTCR_0_5,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0x500C++0x03
line.long 0x00 "RDMCHCR_0_5,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
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bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
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rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
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bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
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bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
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bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
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bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0x5010++0x03
line.long 0x00 "RDMFIXSAR_0_5,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0x5014++0x03
line.long 0x00 "RDMFIXDAR_0_5,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0x5018++0x03
line.long 0x00 "RDMTCRB_0_5,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0x501C++0x03
line.long 0x00 "RDMCHCRB_0_5,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
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bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
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rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
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rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
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bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0x5028++0x03
line.long 0x00 "RDMTSR_0_5,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0x5038++0x03
line.long 0x00 "RDMTSRB_0_5,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0x5040++0x01
line.word 0x00 "RDMRS_0_5,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0x5048++0x03
line.long 0x00 "RDMBUFCR_0_5,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
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rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0x5050++0x03
line.long 0x00 "RDMDPBASE_0_5,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0x5054++0x03
line.long 0x00 "RDMDPCR_0_5,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x5058++0x03
line.long 0x00 "RDMDPEVTCR_0_5,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
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bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
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bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x505C++0x03
line.long 0x00 "RDMDPEVTCNT_0_5,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
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hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0x5060++0x03
line.long 0x00 "RDMFIXDPBASE_0_5,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0x5064++0x03
line.long 0x00 "RDMDREQOS_0_5,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0x5078++0x03
line.long 0x00 "RDMREGIONID_0_5,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x5080++0x03
line.long 0x00 "RDMCHID_0_5,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x50B0++0x03
line.long 0x00 "RDMSEC_0_5,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0x5100++0x03
line.long 0x00 "RDMCHCLR_0_5,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0x5110++0x03
line.long 0x00 "RDMISTA_0_5,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
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hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0x6000++0x03
line.long 0x00 "RDMSAR_0_6,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0x6004++0x03
line.long 0x00 "RDMDAR_0_6,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0x6008++0x03
line.long 0x00 "RDMTCR_0_6,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0x600C++0x03
line.long 0x00 "RDMCHCR_0_6,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
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bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
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rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
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bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
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bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
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bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
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bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0x6010++0x03
line.long 0x00 "RDMFIXSAR_0_6,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0x6014++0x03
line.long 0x00 "RDMFIXDAR_0_6,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0x6018++0x03
line.long 0x00 "RDMTCRB_0_6,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0x601C++0x03
line.long 0x00 "RDMCHCRB_0_6,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
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bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
newline
rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
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rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
newline
bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0x6028++0x03
line.long 0x00 "RDMTSR_0_6,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0x6038++0x03
line.long 0x00 "RDMTSRB_0_6,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0x6040++0x01
line.word 0x00 "RDMRS_0_6,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0x6048++0x03
line.long 0x00 "RDMBUFCR_0_6,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
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rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0x6050++0x03
line.long 0x00 "RDMDPBASE_0_6,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0x6054++0x03
line.long 0x00 "RDMDPCR_0_6,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x6058++0x03
line.long 0x00 "RDMDPEVTCR_0_6,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
newline
bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x605C++0x03
line.long 0x00 "RDMDPEVTCNT_0_6,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
newline
hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0x6060++0x03
line.long 0x00 "RDMFIXDPBASE_0_6,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0x6064++0x03
line.long 0x00 "RDMDREQOS_0_6,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0x6078++0x03
line.long 0x00 "RDMREGIONID_0_6,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x6080++0x03
line.long 0x00 "RDMCHID_0_6,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x60B0++0x03
line.long 0x00 "RDMSEC_0_6,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0x6100++0x03
line.long 0x00 "RDMCHCLR_0_6,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0x6110++0x03
line.long 0x00 "RDMISTA_0_6,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
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hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0x7000++0x03
line.long 0x00 "RDMSAR_0_7,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0x7004++0x03
line.long 0x00 "RDMDAR_0_7,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0x7008++0x03
line.long 0x00 "RDMTCR_0_7,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0x700C++0x03
line.long 0x00 "RDMCHCR_0_7,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
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bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
newline
rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
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bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
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bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
newline
bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
newline
bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0x7010++0x03
line.long 0x00 "RDMFIXSAR_0_7,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0x7014++0x03
line.long 0x00 "RDMFIXDAR_0_7,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0x7018++0x03
line.long 0x00 "RDMTCRB_0_7,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0x701C++0x03
line.long 0x00 "RDMCHCRB_0_7,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
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bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
newline
rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
newline
rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
newline
bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0x7028++0x03
line.long 0x00 "RDMTSR_0_7,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0x7038++0x03
line.long 0x00 "RDMTSRB_0_7,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0x7040++0x01
line.word 0x00 "RDMRS_0_7,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0x7048++0x03
line.long 0x00 "RDMBUFCR_0_7,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
newline
rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0x7050++0x03
line.long 0x00 "RDMDPBASE_0_7,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0x7054++0x03
line.long 0x00 "RDMDPCR_0_7,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x7058++0x03
line.long 0x00 "RDMDPEVTCR_0_7,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
newline
bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x705C++0x03
line.long 0x00 "RDMDPEVTCNT_0_7,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
newline
hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0x7060++0x03
line.long 0x00 "RDMFIXDPBASE_0_7,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0x7064++0x03
line.long 0x00 "RDMDREQOS_0_7,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0x7078++0x03
line.long 0x00 "RDMREGIONID_0_7,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x7080++0x03
line.long 0x00 "RDMCHID_0_7,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x70B0++0x03
line.long 0x00 "RDMSEC_0_7,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0x7100++0x03
line.long 0x00 "RDMCHCLR_0_7,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0x7110++0x03
line.long 0x00 "RDMISTA_0_7,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
newline
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0x8000++0x03
line.long 0x00 "RDMSAR_0_8,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0x8004++0x03
line.long 0x00 "RDMDAR_0_8,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0x8008++0x03
line.long 0x00 "RDMTCR_0_8,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0x800C++0x03
line.long 0x00 "RDMCHCR_0_8,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
newline
bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
newline
rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
newline
bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
newline
bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
newline
bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
newline
bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0x8010++0x03
line.long 0x00 "RDMFIXSAR_0_8,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0x8014++0x03
line.long 0x00 "RDMFIXDAR_0_8,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0x8018++0x03
line.long 0x00 "RDMTCRB_0_8,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0x801C++0x03
line.long 0x00 "RDMCHCRB_0_8,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
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bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
newline
rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
newline
rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
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bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0x8028++0x03
line.long 0x00 "RDMTSR_0_8,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0x8038++0x03
line.long 0x00 "RDMTSRB_0_8,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0x8040++0x01
line.word 0x00 "RDMRS_0_8,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0x8048++0x03
line.long 0x00 "RDMBUFCR_0_8,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
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rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0x8050++0x03
line.long 0x00 "RDMDPBASE_0_8,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0x8054++0x03
line.long 0x00 "RDMDPCR_0_8,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8058++0x03
line.long 0x00 "RDMDPEVTCR_0_8,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
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bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x805C++0x03
line.long 0x00 "RDMDPEVTCNT_0_8,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
newline
hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0x8060++0x03
line.long 0x00 "RDMFIXDPBASE_0_8,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0x8064++0x03
line.long 0x00 "RDMDREQOS_0_8,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0x8078++0x03
line.long 0x00 "RDMREGIONID_0_8,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8080++0x03
line.long 0x00 "RDMCHID_0_8,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x80B0++0x03
line.long 0x00 "RDMSEC_0_8,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0x8100++0x03
line.long 0x00 "RDMCHCLR_0_8,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0x8110++0x03
line.long 0x00 "RDMISTA_0_8,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
newline
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0x9000++0x03
line.long 0x00 "RDMSAR_0_9,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0x9004++0x03
line.long 0x00 "RDMDAR_0_9,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0x9008++0x03
line.long 0x00 "RDMTCR_0_9,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0x900C++0x03
line.long 0x00 "RDMCHCR_0_9,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
newline
bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
newline
rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
newline
bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
newline
bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
newline
bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
newline
bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0x9010++0x03
line.long 0x00 "RDMFIXSAR_0_9,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0x9014++0x03
line.long 0x00 "RDMFIXDAR_0_9,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0x9018++0x03
line.long 0x00 "RDMTCRB_0_9,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0x901C++0x03
line.long 0x00 "RDMCHCRB_0_9,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
newline
bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
newline
rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
newline
rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
newline
bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0x9028++0x03
line.long 0x00 "RDMTSR_0_9,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0x9038++0x03
line.long 0x00 "RDMTSRB_0_9,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0x9040++0x01
line.word 0x00 "RDMRS_0_9,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0x9048++0x03
line.long 0x00 "RDMBUFCR_0_9,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
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rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0x9050++0x03
line.long 0x00 "RDMDPBASE_0_9,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0x9054++0x03
line.long 0x00 "RDMDPCR_0_9,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x9058++0x03
line.long 0x00 "RDMDPEVTCR_0_9,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
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bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
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bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x905C++0x03
line.long 0x00 "RDMDPEVTCNT_0_9,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
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hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0x9060++0x03
line.long 0x00 "RDMFIXDPBASE_0_9,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0x9064++0x03
line.long 0x00 "RDMDREQOS_0_9,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0x9078++0x03
line.long 0x00 "RDMREGIONID_0_9,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x9080++0x03
line.long 0x00 "RDMCHID_0_9,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x90B0++0x03
line.long 0x00 "RDMSEC_0_9,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0x9100++0x03
line.long 0x00 "RDMCHCLR_0_9,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0x9110++0x03
line.long 0x00 "RDMISTA_0_9,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
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hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0xA000++0x03
line.long 0x00 "RDMSAR_0_10,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0xA004++0x03
line.long 0x00 "RDMDAR_0_10,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0xA008++0x03
line.long 0x00 "RDMTCR_0_10,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0xA00C++0x03
line.long 0x00 "RDMCHCR_0_10,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
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bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
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rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
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bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
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bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
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bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
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bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0xA010++0x03
line.long 0x00 "RDMFIXSAR_0_10,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0xA014++0x03
line.long 0x00 "RDMFIXDAR_0_10,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0xA018++0x03
line.long 0x00 "RDMTCRB_0_10,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0xA01C++0x03
line.long 0x00 "RDMCHCRB_0_10,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
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bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
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rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
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rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
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bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0xA028++0x03
line.long 0x00 "RDMTSR_0_10,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0xA038++0x03
line.long 0x00 "RDMTSRB_0_10,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0xA040++0x01
line.word 0x00 "RDMRS_0_10,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0xA048++0x03
line.long 0x00 "RDMBUFCR_0_10,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
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rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0xA050++0x03
line.long 0x00 "RDMDPBASE_0_10,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0xA054++0x03
line.long 0x00 "RDMDPCR_0_10,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA058++0x03
line.long 0x00 "RDMDPEVTCR_0_10,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
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bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xA05C++0x03
line.long 0x00 "RDMDPEVTCNT_0_10,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
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hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0xA060++0x03
line.long 0x00 "RDMFIXDPBASE_0_10,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0xA064++0x03
line.long 0x00 "RDMDREQOS_0_10,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0xA078++0x03
line.long 0x00 "RDMREGIONID_0_10,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA080++0x03
line.long 0x00 "RDMCHID_0_10,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA0B0++0x03
line.long 0x00 "RDMSEC_0_10,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0xA100++0x03
line.long 0x00 "RDMCHCLR_0_10,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0xA110++0x03
line.long 0x00 "RDMISTA_0_10,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
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hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0xB000++0x03
line.long 0x00 "RDMSAR_0_11,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0xB004++0x03
line.long 0x00 "RDMDAR_0_11,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0xB008++0x03
line.long 0x00 "RDMTCR_0_11,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0xB00C++0x03
line.long 0x00 "RDMCHCR_0_11,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
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bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
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rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
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bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
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bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
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bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
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bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0xB010++0x03
line.long 0x00 "RDMFIXSAR_0_11,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0xB014++0x03
line.long 0x00 "RDMFIXDAR_0_11,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0xB018++0x03
line.long 0x00 "RDMTCRB_0_11,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0xB01C++0x03
line.long 0x00 "RDMCHCRB_0_11,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
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bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
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rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
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rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
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bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0xB028++0x03
line.long 0x00 "RDMTSR_0_11,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0xB038++0x03
line.long 0x00 "RDMTSRB_0_11,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0xB040++0x01
line.word 0x00 "RDMRS_0_11,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0xB048++0x03
line.long 0x00 "RDMBUFCR_0_11,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
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rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0xB050++0x03
line.long 0x00 "RDMDPBASE_0_11,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0xB054++0x03
line.long 0x00 "RDMDPCR_0_11,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB058++0x03
line.long 0x00 "RDMDPEVTCR_0_11,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
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bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
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bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xB05C++0x03
line.long 0x00 "RDMDPEVTCNT_0_11,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
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hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0xB060++0x03
line.long 0x00 "RDMFIXDPBASE_0_11,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0xB064++0x03
line.long 0x00 "RDMDREQOS_0_11,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0xB078++0x03
line.long 0x00 "RDMREGIONID_0_11,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB080++0x03
line.long 0x00 "RDMCHID_0_11,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB0B0++0x03
line.long 0x00 "RDMSEC_0_11,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0xB100++0x03
line.long 0x00 "RDMCHCLR_0_11,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0xB110++0x03
line.long 0x00 "RDMISTA_0_11,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
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hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0xC000++0x03
line.long 0x00 "RDMSAR_0_12,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0xC004++0x03
line.long 0x00 "RDMDAR_0_12,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0xC008++0x03
line.long 0x00 "RDMTCR_0_12,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0xC00C++0x03
line.long 0x00 "RDMCHCR_0_12,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
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bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
newline
rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
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bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
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bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
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bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
newline
bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0xC010++0x03
line.long 0x00 "RDMFIXSAR_0_12,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0xC014++0x03
line.long 0x00 "RDMFIXDAR_0_12,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0xC018++0x03
line.long 0x00 "RDMTCRB_0_12,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0xC01C++0x03
line.long 0x00 "RDMCHCRB_0_12,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
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bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
newline
rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
newline
rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
newline
bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0xC028++0x03
line.long 0x00 "RDMTSR_0_12,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0xC038++0x03
line.long 0x00 "RDMTSRB_0_12,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0xC040++0x01
line.word 0x00 "RDMRS_0_12,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0xC048++0x03
line.long 0x00 "RDMBUFCR_0_12,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
newline
rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0xC050++0x03
line.long 0x00 "RDMDPBASE_0_12,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0xC054++0x03
line.long 0x00 "RDMDPCR_0_12,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC058++0x03
line.long 0x00 "RDMDPEVTCR_0_12,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
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bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
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bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xC05C++0x03
line.long 0x00 "RDMDPEVTCNT_0_12,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
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hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0xC060++0x03
line.long 0x00 "RDMFIXDPBASE_0_12,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0xC064++0x03
line.long 0x00 "RDMDREQOS_0_12,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0xC078++0x03
line.long 0x00 "RDMREGIONID_0_12,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC080++0x03
line.long 0x00 "RDMCHID_0_12,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC0B0++0x03
line.long 0x00 "RDMSEC_0_12,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0xC100++0x03
line.long 0x00 "RDMCHCLR_0_12,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0xC110++0x03
line.long 0x00 "RDMISTA_0_12,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
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hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0xD000++0x03
line.long 0x00 "RDMSAR_0_13,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0xD004++0x03
line.long 0x00 "RDMDAR_0_13,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0xD008++0x03
line.long 0x00 "RDMTCR_0_13,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0xD00C++0x03
line.long 0x00 "RDMCHCR_0_13,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
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bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
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rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
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bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
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bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
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bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
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bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0xD010++0x03
line.long 0x00 "RDMFIXSAR_0_13,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0xD014++0x03
line.long 0x00 "RDMFIXDAR_0_13,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0xD018++0x03
line.long 0x00 "RDMTCRB_0_13,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0xD01C++0x03
line.long 0x00 "RDMCHCRB_0_13,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
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bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
newline
rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
newline
rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
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bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0xD028++0x03
line.long 0x00 "RDMTSR_0_13,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0xD038++0x03
line.long 0x00 "RDMTSRB_0_13,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0xD040++0x01
line.word 0x00 "RDMRS_0_13,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0xD048++0x03
line.long 0x00 "RDMBUFCR_0_13,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
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rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0xD050++0x03
line.long 0x00 "RDMDPBASE_0_13,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0xD054++0x03
line.long 0x00 "RDMDPCR_0_13,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xD058++0x03
line.long 0x00 "RDMDPEVTCR_0_13,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
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bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xD05C++0x03
line.long 0x00 "RDMDPEVTCNT_0_13,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
newline
hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0xD060++0x03
line.long 0x00 "RDMFIXDPBASE_0_13,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0xD064++0x03
line.long 0x00 "RDMDREQOS_0_13,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0xD078++0x03
line.long 0x00 "RDMREGIONID_0_13,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xD080++0x03
line.long 0x00 "RDMCHID_0_13,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xD0B0++0x03
line.long 0x00 "RDMSEC_0_13,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0xD100++0x03
line.long 0x00 "RDMCHCLR_0_13,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0xD110++0x03
line.long 0x00 "RDMISTA_0_13,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
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hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0xE000++0x03
line.long 0x00 "RDMSAR_0_14,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0xE004++0x03
line.long 0x00 "RDMDAR_0_14,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0xE008++0x03
line.long 0x00 "RDMTCR_0_14,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0xE00C++0x03
line.long 0x00 "RDMCHCR_0_14,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
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bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
newline
rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
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bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
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bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
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bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
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bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0xE010++0x03
line.long 0x00 "RDMFIXSAR_0_14,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0xE014++0x03
line.long 0x00 "RDMFIXDAR_0_14,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0xE018++0x03
line.long 0x00 "RDMTCRB_0_14,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0xE01C++0x03
line.long 0x00 "RDMCHCRB_0_14,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
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bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
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rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
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rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
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bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0xE028++0x03
line.long 0x00 "RDMTSR_0_14,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0xE038++0x03
line.long 0x00 "RDMTSRB_0_14,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0xE040++0x01
line.word 0x00 "RDMRS_0_14,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0xE048++0x03
line.long 0x00 "RDMBUFCR_0_14,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
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rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0xE050++0x03
line.long 0x00 "RDMDPBASE_0_14,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0xE054++0x03
line.long 0x00 "RDMDPCR_0_14,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xE058++0x03
line.long 0x00 "RDMDPEVTCR_0_14,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
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bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
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bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xE05C++0x03
line.long 0x00 "RDMDPEVTCNT_0_14,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
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hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0xE060++0x03
line.long 0x00 "RDMFIXDPBASE_0_14,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0xE064++0x03
line.long 0x00 "RDMDREQOS_0_14,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0xE078++0x03
line.long 0x00 "RDMREGIONID_0_14,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xE080++0x03
line.long 0x00 "RDMCHID_0_14,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xE0B0++0x03
line.long 0x00 "RDMSEC_0_14,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0xE100++0x03
line.long 0x00 "RDMCHCLR_0_14,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0xE110++0x03
line.long 0x00 "RDMISTA_0_14,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
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hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0xF000++0x03
line.long 0x00 "RDMSAR_0_15,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0xF004++0x03
line.long 0x00 "RDMDAR_0_15,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0xF008++0x03
line.long 0x00 "RDMTCR_0_15,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0xF00C++0x03
line.long 0x00 "RDMCHCR_0_15,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
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bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
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rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
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bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
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bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
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bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
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bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0xF010++0x03
line.long 0x00 "RDMFIXSAR_0_15,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0xF014++0x03
line.long 0x00 "RDMFIXDAR_0_15,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0xF018++0x03
line.long 0x00 "RDMTCRB_0_15,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0xF01C++0x03
line.long 0x00 "RDMCHCRB_0_15,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
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bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
newline
rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
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rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
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bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0xF028++0x03
line.long 0x00 "RDMTSR_0_15,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0xF038++0x03
line.long 0x00 "RDMTSRB_0_15,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0xF040++0x01
line.word 0x00 "RDMRS_0_15,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0xF048++0x03
line.long 0x00 "RDMBUFCR_0_15,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
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rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0xF050++0x03
line.long 0x00 "RDMDPBASE_0_15,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0xF054++0x03
line.long 0x00 "RDMDPCR_0_15,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xF058++0x03
line.long 0x00 "RDMDPEVTCR_0_15,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
newline
bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xF05C++0x03
line.long 0x00 "RDMDPEVTCNT_0_15,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
newline
hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0xF060++0x03
line.long 0x00 "RDMFIXDPBASE_0_15,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0xF064++0x03
line.long 0x00 "RDMDREQOS_0_15,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0xF078++0x03
line.long 0x00 "RDMREGIONID_0_15,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xF080++0x03
line.long 0x00 "RDMCHID_0_15,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xF0B0++0x03
line.long 0x00 "RDMSEC_0_15,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0xF100++0x03
line.long 0x00 "RDMCHCLR_0_15,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0xF110++0x03
line.long 0x00 "RDMISTA_0_15,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
newline
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
tree.end
tree "DMAC_INST_5"
base ad:0xFFC20000
group.long 0x00++0x03
line.long 0x00 "RDMSAR_1_0,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0x04++0x03
line.long 0x00 "RDMDAR_1_0,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0x08++0x03
line.long 0x00 "RDMTCR_1_0,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0x0C++0x03
line.long 0x00 "RDMCHCR_1_0,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
newline
bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
newline
rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
newline
bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
newline
bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
newline
bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
newline
bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0x10++0x03
line.long 0x00 "RDMFIXSAR_1_0,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0x14++0x03
line.long 0x00 "RDMFIXDAR_1_0,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0x18++0x03
line.long 0x00 "RDMTCRB_1_0,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0x1C++0x03
line.long 0x00 "RDMCHCRB_1_0,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
newline
bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
newline
rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
newline
rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
newline
bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0x28++0x03
line.long 0x00 "RDMTSR_1_0,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0x38++0x03
line.long 0x00 "RDMTSRB_1_0,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0x40++0x01
line.word 0x00 "RDMRS_1_0,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0x48++0x03
line.long 0x00 "RDMBUFCR_1_0,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
newline
rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0x50++0x03
line.long 0x00 "RDMDPBASE_1_0,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0x54++0x03
line.long 0x00 "RDMDPCR_1_0,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x58++0x03
line.long 0x00 "RDMDPEVTCR_1_0,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
newline
bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x5C++0x03
line.long 0x00 "RDMDPEVTCNT_1_0,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
newline
hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0x60++0x03
line.long 0x00 "RDMFIXDPBASE_1_0,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0x64++0x03
line.long 0x00 "RDMDREQOS_1_0,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0x78++0x03
line.long 0x00 "RDMREGIONID_1_0,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x80++0x03
line.long 0x00 "RDMCHID_1_0,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB0++0x03
line.long 0x00 "RDMSEC_1_0,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0x100++0x03
line.long 0x00 "RDMCHCLR_1_0,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0x110++0x03
line.long 0x00 "RDMISTA_1_0,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
newline
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0x1000++0x03
line.long 0x00 "RDMSAR_1_1,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0x1004++0x03
line.long 0x00 "RDMDAR_1_1,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0x1008++0x03
line.long 0x00 "RDMTCR_1_1,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0x100C++0x03
line.long 0x00 "RDMCHCR_1_1,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
newline
bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
newline
rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
newline
bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
newline
bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
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bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
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bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0x1010++0x03
line.long 0x00 "RDMFIXSAR_1_1,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0x1014++0x03
line.long 0x00 "RDMFIXDAR_1_1,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0x1018++0x03
line.long 0x00 "RDMTCRB_1_1,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0x101C++0x03
line.long 0x00 "RDMCHCRB_1_1,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
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bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
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rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
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rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
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bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0x1028++0x03
line.long 0x00 "RDMTSR_1_1,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0x1038++0x03
line.long 0x00 "RDMTSRB_1_1,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0x1040++0x01
line.word 0x00 "RDMRS_1_1,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0x1048++0x03
line.long 0x00 "RDMBUFCR_1_1,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
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rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0x1050++0x03
line.long 0x00 "RDMDPBASE_1_1,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0x1054++0x03
line.long 0x00 "RDMDPCR_1_1,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1058++0x03
line.long 0x00 "RDMDPEVTCR_1_1,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
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bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
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bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x105C++0x03
line.long 0x00 "RDMDPEVTCNT_1_1,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
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hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0x1060++0x03
line.long 0x00 "RDMFIXDPBASE_1_1,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0x1064++0x03
line.long 0x00 "RDMDREQOS_1_1,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0x1078++0x03
line.long 0x00 "RDMREGIONID_1_1,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1080++0x03
line.long 0x00 "RDMCHID_1_1,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x10B0++0x03
line.long 0x00 "RDMSEC_1_1,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0x1100++0x03
line.long 0x00 "RDMCHCLR_1_1,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0x1110++0x03
line.long 0x00 "RDMISTA_1_1,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
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hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0x2000++0x03
line.long 0x00 "RDMSAR_1_2,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0x2004++0x03
line.long 0x00 "RDMDAR_1_2,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0x2008++0x03
line.long 0x00 "RDMTCR_1_2,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0x200C++0x03
line.long 0x00 "RDMCHCR_1_2,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
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bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
newline
rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
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bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
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bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
newline
bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
newline
bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0x2010++0x03
line.long 0x00 "RDMFIXSAR_1_2,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0x2014++0x03
line.long 0x00 "RDMFIXDAR_1_2,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0x2018++0x03
line.long 0x00 "RDMTCRB_1_2,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0x201C++0x03
line.long 0x00 "RDMCHCRB_1_2,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
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bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
newline
rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
newline
rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
newline
bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0x2028++0x03
line.long 0x00 "RDMTSR_1_2,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0x2038++0x03
line.long 0x00 "RDMTSRB_1_2,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0x2040++0x01
line.word 0x00 "RDMRS_1_2,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0x2048++0x03
line.long 0x00 "RDMBUFCR_1_2,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
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rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0x2050++0x03
line.long 0x00 "RDMDPBASE_1_2,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0x2054++0x03
line.long 0x00 "RDMDPCR_1_2,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x2058++0x03
line.long 0x00 "RDMDPEVTCR_1_2,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
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bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
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bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x205C++0x03
line.long 0x00 "RDMDPEVTCNT_1_2,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
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hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0x2060++0x03
line.long 0x00 "RDMFIXDPBASE_1_2,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0x2064++0x03
line.long 0x00 "RDMDREQOS_1_2,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0x2078++0x03
line.long 0x00 "RDMREGIONID_1_2,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x2080++0x03
line.long 0x00 "RDMCHID_1_2,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x20B0++0x03
line.long 0x00 "RDMSEC_1_2,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0x2100++0x03
line.long 0x00 "RDMCHCLR_1_2,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0x2110++0x03
line.long 0x00 "RDMISTA_1_2,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
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hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0x3000++0x03
line.long 0x00 "RDMSAR_1_3,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0x3004++0x03
line.long 0x00 "RDMDAR_1_3,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0x3008++0x03
line.long 0x00 "RDMTCR_1_3,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0x300C++0x03
line.long 0x00 "RDMCHCR_1_3,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
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bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
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rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
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bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
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bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
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bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
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bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0x3010++0x03
line.long 0x00 "RDMFIXSAR_1_3,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0x3014++0x03
line.long 0x00 "RDMFIXDAR_1_3,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0x3018++0x03
line.long 0x00 "RDMTCRB_1_3,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0x301C++0x03
line.long 0x00 "RDMCHCRB_1_3,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
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bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
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rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
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rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
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bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0x3028++0x03
line.long 0x00 "RDMTSR_1_3,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0x3038++0x03
line.long 0x00 "RDMTSRB_1_3,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0x3040++0x01
line.word 0x00 "RDMRS_1_3,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0x3048++0x03
line.long 0x00 "RDMBUFCR_1_3,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
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rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0x3050++0x03
line.long 0x00 "RDMDPBASE_1_3,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0x3054++0x03
line.long 0x00 "RDMDPCR_1_3,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x3058++0x03
line.long 0x00 "RDMDPEVTCR_1_3,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
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bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x305C++0x03
line.long 0x00 "RDMDPEVTCNT_1_3,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
newline
hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0x3060++0x03
line.long 0x00 "RDMFIXDPBASE_1_3,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0x3064++0x03
line.long 0x00 "RDMDREQOS_1_3,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0x3078++0x03
line.long 0x00 "RDMREGIONID_1_3,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x3080++0x03
line.long 0x00 "RDMCHID_1_3,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x30B0++0x03
line.long 0x00 "RDMSEC_1_3,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0x3100++0x03
line.long 0x00 "RDMCHCLR_1_3,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0x3110++0x03
line.long 0x00 "RDMISTA_1_3,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
newline
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0x4000++0x03
line.long 0x00 "RDMSAR_1_4,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0x4004++0x03
line.long 0x00 "RDMDAR_1_4,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0x4008++0x03
line.long 0x00 "RDMTCR_1_4,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0x400C++0x03
line.long 0x00 "RDMCHCR_1_4,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
newline
bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
newline
rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
newline
bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
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bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
newline
bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
newline
bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0x4010++0x03
line.long 0x00 "RDMFIXSAR_1_4,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0x4014++0x03
line.long 0x00 "RDMFIXDAR_1_4,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0x4018++0x03
line.long 0x00 "RDMTCRB_1_4,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0x401C++0x03
line.long 0x00 "RDMCHCRB_1_4,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
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bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
newline
rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
newline
rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
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bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0x4028++0x03
line.long 0x00 "RDMTSR_1_4,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0x4038++0x03
line.long 0x00 "RDMTSRB_1_4,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0x4040++0x01
line.word 0x00 "RDMRS_1_4,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0x4048++0x03
line.long 0x00 "RDMBUFCR_1_4,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
newline
rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0x4050++0x03
line.long 0x00 "RDMDPBASE_1_4,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0x4054++0x03
line.long 0x00 "RDMDPCR_1_4,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4058++0x03
line.long 0x00 "RDMDPEVTCR_1_4,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
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bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x405C++0x03
line.long 0x00 "RDMDPEVTCNT_1_4,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
newline
hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0x4060++0x03
line.long 0x00 "RDMFIXDPBASE_1_4,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0x4064++0x03
line.long 0x00 "RDMDREQOS_1_4,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0x4078++0x03
line.long 0x00 "RDMREGIONID_1_4,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4080++0x03
line.long 0x00 "RDMCHID_1_4,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x40B0++0x03
line.long 0x00 "RDMSEC_1_4,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0x4100++0x03
line.long 0x00 "RDMCHCLR_1_4,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0x4110++0x03
line.long 0x00 "RDMISTA_1_4,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
newline
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0x5000++0x03
line.long 0x00 "RDMSAR_1_5,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0x5004++0x03
line.long 0x00 "RDMDAR_1_5,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0x5008++0x03
line.long 0x00 "RDMTCR_1_5,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0x500C++0x03
line.long 0x00 "RDMCHCR_1_5,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
newline
bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
newline
rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
newline
bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
newline
bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
newline
bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
newline
bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0x5010++0x03
line.long 0x00 "RDMFIXSAR_1_5,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0x5014++0x03
line.long 0x00 "RDMFIXDAR_1_5,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0x5018++0x03
line.long 0x00 "RDMTCRB_1_5,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0x501C++0x03
line.long 0x00 "RDMCHCRB_1_5,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
newline
bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
newline
rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
newline
rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
newline
bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0x5028++0x03
line.long 0x00 "RDMTSR_1_5,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0x5038++0x03
line.long 0x00 "RDMTSRB_1_5,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0x5040++0x01
line.word 0x00 "RDMRS_1_5,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0x5048++0x03
line.long 0x00 "RDMBUFCR_1_5,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
newline
rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0x5050++0x03
line.long 0x00 "RDMDPBASE_1_5,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0x5054++0x03
line.long 0x00 "RDMDPCR_1_5,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x5058++0x03
line.long 0x00 "RDMDPEVTCR_1_5,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
newline
bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x505C++0x03
line.long 0x00 "RDMDPEVTCNT_1_5,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
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hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0x5060++0x03
line.long 0x00 "RDMFIXDPBASE_1_5,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0x5064++0x03
line.long 0x00 "RDMDREQOS_1_5,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0x5078++0x03
line.long 0x00 "RDMREGIONID_1_5,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x5080++0x03
line.long 0x00 "RDMCHID_1_5,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x50B0++0x03
line.long 0x00 "RDMSEC_1_5,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0x5100++0x03
line.long 0x00 "RDMCHCLR_1_5,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0x5110++0x03
line.long 0x00 "RDMISTA_1_5,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
newline
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0x6000++0x03
line.long 0x00 "RDMSAR_1_6,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0x6004++0x03
line.long 0x00 "RDMDAR_1_6,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0x6008++0x03
line.long 0x00 "RDMTCR_1_6,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0x600C++0x03
line.long 0x00 "RDMCHCR_1_6,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
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bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
newline
rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
newline
bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
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bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
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bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
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bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0x6010++0x03
line.long 0x00 "RDMFIXSAR_1_6,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0x6014++0x03
line.long 0x00 "RDMFIXDAR_1_6,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0x6018++0x03
line.long 0x00 "RDMTCRB_1_6,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0x601C++0x03
line.long 0x00 "RDMCHCRB_1_6,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
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bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
newline
rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
newline
rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
newline
bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0x6028++0x03
line.long 0x00 "RDMTSR_1_6,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0x6038++0x03
line.long 0x00 "RDMTSRB_1_6,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0x6040++0x01
line.word 0x00 "RDMRS_1_6,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0x6048++0x03
line.long 0x00 "RDMBUFCR_1_6,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
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rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0x6050++0x03
line.long 0x00 "RDMDPBASE_1_6,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0x6054++0x03
line.long 0x00 "RDMDPCR_1_6,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x6058++0x03
line.long 0x00 "RDMDPEVTCR_1_6,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
newline
bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x605C++0x03
line.long 0x00 "RDMDPEVTCNT_1_6,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
newline
hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0x6060++0x03
line.long 0x00 "RDMFIXDPBASE_1_6,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0x6064++0x03
line.long 0x00 "RDMDREQOS_1_6,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0x6078++0x03
line.long 0x00 "RDMREGIONID_1_6,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x6080++0x03
line.long 0x00 "RDMCHID_1_6,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x60B0++0x03
line.long 0x00 "RDMSEC_1_6,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0x6100++0x03
line.long 0x00 "RDMCHCLR_1_6,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0x6110++0x03
line.long 0x00 "RDMISTA_1_6,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
newline
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0x7000++0x03
line.long 0x00 "RDMSAR_1_7,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0x7004++0x03
line.long 0x00 "RDMDAR_1_7,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0x7008++0x03
line.long 0x00 "RDMTCR_1_7,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0x700C++0x03
line.long 0x00 "RDMCHCR_1_7,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
newline
bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
newline
rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
newline
bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
newline
bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
newline
bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
newline
bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0x7010++0x03
line.long 0x00 "RDMFIXSAR_1_7,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0x7014++0x03
line.long 0x00 "RDMFIXDAR_1_7,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0x7018++0x03
line.long 0x00 "RDMTCRB_1_7,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0x701C++0x03
line.long 0x00 "RDMCHCRB_1_7,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
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bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
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rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
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rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
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bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0x7028++0x03
line.long 0x00 "RDMTSR_1_7,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0x7038++0x03
line.long 0x00 "RDMTSRB_1_7,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0x7040++0x01
line.word 0x00 "RDMRS_1_7,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0x7048++0x03
line.long 0x00 "RDMBUFCR_1_7,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
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rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0x7050++0x03
line.long 0x00 "RDMDPBASE_1_7,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0x7054++0x03
line.long 0x00 "RDMDPCR_1_7,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x7058++0x03
line.long 0x00 "RDMDPEVTCR_1_7,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
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bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
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bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x705C++0x03
line.long 0x00 "RDMDPEVTCNT_1_7,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
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hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0x7060++0x03
line.long 0x00 "RDMFIXDPBASE_1_7,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0x7064++0x03
line.long 0x00 "RDMDREQOS_1_7,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0x7078++0x03
line.long 0x00 "RDMREGIONID_1_7,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x7080++0x03
line.long 0x00 "RDMCHID_1_7,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x70B0++0x03
line.long 0x00 "RDMSEC_1_7,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0x7100++0x03
line.long 0x00 "RDMCHCLR_1_7,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0x7110++0x03
line.long 0x00 "RDMISTA_1_7,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
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hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0x8000++0x03
line.long 0x00 "RDMSAR_1_8,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0x8004++0x03
line.long 0x00 "RDMDAR_1_8,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0x8008++0x03
line.long 0x00 "RDMTCR_1_8,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0x800C++0x03
line.long 0x00 "RDMCHCR_1_8,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
newline
bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
newline
rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
newline
bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
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bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
newline
bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
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bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0x8010++0x03
line.long 0x00 "RDMFIXSAR_1_8,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0x8014++0x03
line.long 0x00 "RDMFIXDAR_1_8,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0x8018++0x03
line.long 0x00 "RDMTCRB_1_8,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0x801C++0x03
line.long 0x00 "RDMCHCRB_1_8,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
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bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
newline
rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
newline
rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
newline
bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0x8028++0x03
line.long 0x00 "RDMTSR_1_8,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0x8038++0x03
line.long 0x00 "RDMTSRB_1_8,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0x8040++0x01
line.word 0x00 "RDMRS_1_8,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0x8048++0x03
line.long 0x00 "RDMBUFCR_1_8,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
newline
rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0x8050++0x03
line.long 0x00 "RDMDPBASE_1_8,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0x8054++0x03
line.long 0x00 "RDMDPCR_1_8,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8058++0x03
line.long 0x00 "RDMDPEVTCR_1_8,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
newline
bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x805C++0x03
line.long 0x00 "RDMDPEVTCNT_1_8,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
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hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0x8060++0x03
line.long 0x00 "RDMFIXDPBASE_1_8,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0x8064++0x03
line.long 0x00 "RDMDREQOS_1_8,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0x8078++0x03
line.long 0x00 "RDMREGIONID_1_8,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8080++0x03
line.long 0x00 "RDMCHID_1_8,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x80B0++0x03
line.long 0x00 "RDMSEC_1_8,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0x8100++0x03
line.long 0x00 "RDMCHCLR_1_8,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0x8110++0x03
line.long 0x00 "RDMISTA_1_8,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
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hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0x9000++0x03
line.long 0x00 "RDMSAR_1_9,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0x9004++0x03
line.long 0x00 "RDMDAR_1_9,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0x9008++0x03
line.long 0x00 "RDMTCR_1_9,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0x900C++0x03
line.long 0x00 "RDMCHCR_1_9,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
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bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
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rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
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bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
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bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
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bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
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bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0x9010++0x03
line.long 0x00 "RDMFIXSAR_1_9,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0x9014++0x03
line.long 0x00 "RDMFIXDAR_1_9,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0x9018++0x03
line.long 0x00 "RDMTCRB_1_9,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0x901C++0x03
line.long 0x00 "RDMCHCRB_1_9,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
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bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
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rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
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rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
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bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0x9028++0x03
line.long 0x00 "RDMTSR_1_9,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0x9038++0x03
line.long 0x00 "RDMTSRB_1_9,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0x9040++0x01
line.word 0x00 "RDMRS_1_9,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0x9048++0x03
line.long 0x00 "RDMBUFCR_1_9,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
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rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0x9050++0x03
line.long 0x00 "RDMDPBASE_1_9,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0x9054++0x03
line.long 0x00 "RDMDPCR_1_9,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x9058++0x03
line.long 0x00 "RDMDPEVTCR_1_9,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
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bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x905C++0x03
line.long 0x00 "RDMDPEVTCNT_1_9,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
newline
hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0x9060++0x03
line.long 0x00 "RDMFIXDPBASE_1_9,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0x9064++0x03
line.long 0x00 "RDMDREQOS_1_9,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0x9078++0x03
line.long 0x00 "RDMREGIONID_1_9,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x9080++0x03
line.long 0x00 "RDMCHID_1_9,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x90B0++0x03
line.long 0x00 "RDMSEC_1_9,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0x9100++0x03
line.long 0x00 "RDMCHCLR_1_9,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0x9110++0x03
line.long 0x00 "RDMISTA_1_9,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
newline
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0xA000++0x03
line.long 0x00 "RDMSAR_1_10,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0xA004++0x03
line.long 0x00 "RDMDAR_1_10,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0xA008++0x03
line.long 0x00 "RDMTCR_1_10,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0xA00C++0x03
line.long 0x00 "RDMCHCR_1_10,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
newline
bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
newline
rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
newline
bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
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bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
newline
bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
newline
bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0xA010++0x03
line.long 0x00 "RDMFIXSAR_1_10,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0xA014++0x03
line.long 0x00 "RDMFIXDAR_1_10,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0xA018++0x03
line.long 0x00 "RDMTCRB_1_10,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0xA01C++0x03
line.long 0x00 "RDMCHCRB_1_10,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
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bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
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rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
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rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
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bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0xA028++0x03
line.long 0x00 "RDMTSR_1_10,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0xA038++0x03
line.long 0x00 "RDMTSRB_1_10,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0xA040++0x01
line.word 0x00 "RDMRS_1_10,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0xA048++0x03
line.long 0x00 "RDMBUFCR_1_10,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
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rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0xA050++0x03
line.long 0x00 "RDMDPBASE_1_10,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0xA054++0x03
line.long 0x00 "RDMDPCR_1_10,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA058++0x03
line.long 0x00 "RDMDPEVTCR_1_10,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
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bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
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bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xA05C++0x03
line.long 0x00 "RDMDPEVTCNT_1_10,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
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hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0xA060++0x03
line.long 0x00 "RDMFIXDPBASE_1_10,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0xA064++0x03
line.long 0x00 "RDMDREQOS_1_10,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0xA078++0x03
line.long 0x00 "RDMREGIONID_1_10,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA080++0x03
line.long 0x00 "RDMCHID_1_10,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA0B0++0x03
line.long 0x00 "RDMSEC_1_10,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0xA100++0x03
line.long 0x00 "RDMCHCLR_1_10,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0xA110++0x03
line.long 0x00 "RDMISTA_1_10,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
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hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0xB000++0x03
line.long 0x00 "RDMSAR_1_11,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0xB004++0x03
line.long 0x00 "RDMDAR_1_11,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0xB008++0x03
line.long 0x00 "RDMTCR_1_11,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0xB00C++0x03
line.long 0x00 "RDMCHCR_1_11,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
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bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
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rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
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bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
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bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
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bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
newline
bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0xB010++0x03
line.long 0x00 "RDMFIXSAR_1_11,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0xB014++0x03
line.long 0x00 "RDMFIXDAR_1_11,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0xB018++0x03
line.long 0x00 "RDMTCRB_1_11,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0xB01C++0x03
line.long 0x00 "RDMCHCRB_1_11,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
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bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
newline
rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
newline
rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
newline
bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0xB028++0x03
line.long 0x00 "RDMTSR_1_11,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0xB038++0x03
line.long 0x00 "RDMTSRB_1_11,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0xB040++0x01
line.word 0x00 "RDMRS_1_11,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0xB048++0x03
line.long 0x00 "RDMBUFCR_1_11,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
newline
rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0xB050++0x03
line.long 0x00 "RDMDPBASE_1_11,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0xB054++0x03
line.long 0x00 "RDMDPCR_1_11,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB058++0x03
line.long 0x00 "RDMDPEVTCR_1_11,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
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bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xB05C++0x03
line.long 0x00 "RDMDPEVTCNT_1_11,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
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hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0xB060++0x03
line.long 0x00 "RDMFIXDPBASE_1_11,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0xB064++0x03
line.long 0x00 "RDMDREQOS_1_11,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0xB078++0x03
line.long 0x00 "RDMREGIONID_1_11,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB080++0x03
line.long 0x00 "RDMCHID_1_11,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB0B0++0x03
line.long 0x00 "RDMSEC_1_11,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0xB100++0x03
line.long 0x00 "RDMCHCLR_1_11,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0xB110++0x03
line.long 0x00 "RDMISTA_1_11,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
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hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0xC000++0x03
line.long 0x00 "RDMSAR_1_12,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0xC004++0x03
line.long 0x00 "RDMDAR_1_12,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0xC008++0x03
line.long 0x00 "RDMTCR_1_12,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0xC00C++0x03
line.long 0x00 "RDMCHCR_1_12,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
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bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
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rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
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bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
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bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
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bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
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bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0xC010++0x03
line.long 0x00 "RDMFIXSAR_1_12,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0xC014++0x03
line.long 0x00 "RDMFIXDAR_1_12,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0xC018++0x03
line.long 0x00 "RDMTCRB_1_12,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0xC01C++0x03
line.long 0x00 "RDMCHCRB_1_12,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
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bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
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rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
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rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
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bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0xC028++0x03
line.long 0x00 "RDMTSR_1_12,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0xC038++0x03
line.long 0x00 "RDMTSRB_1_12,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0xC040++0x01
line.word 0x00 "RDMRS_1_12,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0xC048++0x03
line.long 0x00 "RDMBUFCR_1_12,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
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rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0xC050++0x03
line.long 0x00 "RDMDPBASE_1_12,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0xC054++0x03
line.long 0x00 "RDMDPCR_1_12,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC058++0x03
line.long 0x00 "RDMDPEVTCR_1_12,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
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bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
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bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xC05C++0x03
line.long 0x00 "RDMDPEVTCNT_1_12,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
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hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0xC060++0x03
line.long 0x00 "RDMFIXDPBASE_1_12,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0xC064++0x03
line.long 0x00 "RDMDREQOS_1_12,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0xC078++0x03
line.long 0x00 "RDMREGIONID_1_12,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC080++0x03
line.long 0x00 "RDMCHID_1_12,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC0B0++0x03
line.long 0x00 "RDMSEC_1_12,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0xC100++0x03
line.long 0x00 "RDMCHCLR_1_12,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0xC110++0x03
line.long 0x00 "RDMISTA_1_12,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
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hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0xD000++0x03
line.long 0x00 "RDMSAR_1_13,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0xD004++0x03
line.long 0x00 "RDMDAR_1_13,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0xD008++0x03
line.long 0x00 "RDMTCR_1_13,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0xD00C++0x03
line.long 0x00 "RDMCHCR_1_13,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
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bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
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rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
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bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
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bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
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bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
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bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0xD010++0x03
line.long 0x00 "RDMFIXSAR_1_13,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0xD014++0x03
line.long 0x00 "RDMFIXDAR_1_13,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0xD018++0x03
line.long 0x00 "RDMTCRB_1_13,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0xD01C++0x03
line.long 0x00 "RDMCHCRB_1_13,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
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bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
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rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
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rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
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bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0xD028++0x03
line.long 0x00 "RDMTSR_1_13,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0xD038++0x03
line.long 0x00 "RDMTSRB_1_13,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0xD040++0x01
line.word 0x00 "RDMRS_1_13,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0xD048++0x03
line.long 0x00 "RDMBUFCR_1_13,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
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rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0xD050++0x03
line.long 0x00 "RDMDPBASE_1_13,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0xD054++0x03
line.long 0x00 "RDMDPCR_1_13,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xD058++0x03
line.long 0x00 "RDMDPEVTCR_1_13,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
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bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
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bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xD05C++0x03
line.long 0x00 "RDMDPEVTCNT_1_13,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
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hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0xD060++0x03
line.long 0x00 "RDMFIXDPBASE_1_13,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0xD064++0x03
line.long 0x00 "RDMDREQOS_1_13,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0xD078++0x03
line.long 0x00 "RDMREGIONID_1_13,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xD080++0x03
line.long 0x00 "RDMCHID_1_13,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xD0B0++0x03
line.long 0x00 "RDMSEC_1_13,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0xD100++0x03
line.long 0x00 "RDMCHCLR_1_13,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0xD110++0x03
line.long 0x00 "RDMISTA_1_13,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
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hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0xE000++0x03
line.long 0x00 "RDMSAR_1_14,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0xE004++0x03
line.long 0x00 "RDMDAR_1_14,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0xE008++0x03
line.long 0x00 "RDMTCR_1_14,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0xE00C++0x03
line.long 0x00 "RDMCHCR_1_14,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
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bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
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rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
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bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
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bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
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bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
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bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0xE010++0x03
line.long 0x00 "RDMFIXSAR_1_14,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0xE014++0x03
line.long 0x00 "RDMFIXDAR_1_14,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0xE018++0x03
line.long 0x00 "RDMTCRB_1_14,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0xE01C++0x03
line.long 0x00 "RDMCHCRB_1_14,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
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bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
newline
rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
newline
rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
newline
bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0xE028++0x03
line.long 0x00 "RDMTSR_1_14,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0xE038++0x03
line.long 0x00 "RDMTSRB_1_14,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0xE040++0x01
line.word 0x00 "RDMRS_1_14,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0xE048++0x03
line.long 0x00 "RDMBUFCR_1_14,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
newline
rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0xE050++0x03
line.long 0x00 "RDMDPBASE_1_14,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0xE054++0x03
line.long 0x00 "RDMDPCR_1_14,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xE058++0x03
line.long 0x00 "RDMDPEVTCR_1_14,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
newline
bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xE05C++0x03
line.long 0x00 "RDMDPEVTCNT_1_14,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
newline
hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0xE060++0x03
line.long 0x00 "RDMFIXDPBASE_1_14,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0xE064++0x03
line.long 0x00 "RDMDREQOS_1_14,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0xE078++0x03
line.long 0x00 "RDMREGIONID_1_14,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xE080++0x03
line.long 0x00 "RDMCHID_1_14,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xE0B0++0x03
line.long 0x00 "RDMSEC_1_14,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0xE100++0x03
line.long 0x00 "RDMCHCLR_1_14,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0xE110++0x03
line.long 0x00 "RDMISTA_1_14,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
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hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0xF000++0x03
line.long 0x00 "RDMSAR_1_15,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0xF004++0x03
line.long 0x00 "RDMDAR_1_15,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0xF008++0x03
line.long 0x00 "RDMTCR_1_15,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0xF00C++0x03
line.long 0x00 "RDMCHCR_1_15,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
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bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
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rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
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bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
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bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
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bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
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bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0xF010++0x03
line.long 0x00 "RDMFIXSAR_1_15,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0xF014++0x03
line.long 0x00 "RDMFIXDAR_1_15,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0xF018++0x03
line.long 0x00 "RDMTCRB_1_15,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0xF01C++0x03
line.long 0x00 "RDMCHCRB_1_15,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
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bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
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rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
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rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
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bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0xF028++0x03
line.long 0x00 "RDMTSR_1_15,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0xF038++0x03
line.long 0x00 "RDMTSRB_1_15,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0xF040++0x01
line.word 0x00 "RDMRS_1_15,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0xF048++0x03
line.long 0x00 "RDMBUFCR_1_15,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
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rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0xF050++0x03
line.long 0x00 "RDMDPBASE_1_15,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0xF054++0x03
line.long 0x00 "RDMDPCR_1_15,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xF058++0x03
line.long 0x00 "RDMDPEVTCR_1_15,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
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bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xF05C++0x03
line.long 0x00 "RDMDPEVTCNT_1_15,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
newline
hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0xF060++0x03
line.long 0x00 "RDMFIXDPBASE_1_15,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0xF064++0x03
line.long 0x00 "RDMDREQOS_1_15,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0xF078++0x03
line.long 0x00 "RDMREGIONID_1_15,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xF080++0x03
line.long 0x00 "RDMCHID_1_15,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xF0B0++0x03
line.long 0x00 "RDMSEC_1_15,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0xF100++0x03
line.long 0x00 "RDMCHCLR_1_15,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0xF110++0x03
line.long 0x00 "RDMISTA_1_15,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
newline
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
tree.end
tree "DMAC_INST_6"
base ad:0xFFD70000
group.long 0x00++0x03
line.long 0x00 "RDMSAR_2_0,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0x04++0x03
line.long 0x00 "RDMDAR_2_0,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0x08++0x03
line.long 0x00 "RDMTCR_2_0,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0x0C++0x03
line.long 0x00 "RDMCHCR_2_0,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
newline
bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
newline
rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
newline
bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
newline
bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
newline
bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
newline
bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0x10++0x03
line.long 0x00 "RDMFIXSAR_2_0,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0x14++0x03
line.long 0x00 "RDMFIXDAR_2_0,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0x18++0x03
line.long 0x00 "RDMTCRB_2_0,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0x1C++0x03
line.long 0x00 "RDMCHCRB_2_0,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
newline
bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
newline
rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
newline
rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
newline
bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0x28++0x03
line.long 0x00 "RDMTSR_2_0,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0x38++0x03
line.long 0x00 "RDMTSRB_2_0,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0x40++0x01
line.word 0x00 "RDMRS_2_0,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0x48++0x03
line.long 0x00 "RDMBUFCR_2_0,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
newline
rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0x50++0x03
line.long 0x00 "RDMDPBASE_2_0,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0x54++0x03
line.long 0x00 "RDMDPCR_2_0,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x58++0x03
line.long 0x00 "RDMDPEVTCR_2_0,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
newline
bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x5C++0x03
line.long 0x00 "RDMDPEVTCNT_2_0,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
newline
hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0x60++0x03
line.long 0x00 "RDMFIXDPBASE_2_0,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0x64++0x03
line.long 0x00 "RDMDREQOS_2_0,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0x78++0x03
line.long 0x00 "RDMREGIONID_2_0,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x80++0x03
line.long 0x00 "RDMCHID_2_0,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB0++0x03
line.long 0x00 "RDMSEC_2_0,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0x100++0x03
line.long 0x00 "RDMCHCLR_2_0,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0x110++0x03
line.long 0x00 "RDMISTA_2_0,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
newline
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0x1000++0x03
line.long 0x00 "RDMSAR_2_1,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0x1004++0x03
line.long 0x00 "RDMDAR_2_1,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0x1008++0x03
line.long 0x00 "RDMTCR_2_1,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0x100C++0x03
line.long 0x00 "RDMCHCR_2_1,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
newline
bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
newline
rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
newline
bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
newline
bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
newline
bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
newline
bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0x1010++0x03
line.long 0x00 "RDMFIXSAR_2_1,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0x1014++0x03
line.long 0x00 "RDMFIXDAR_2_1,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0x1018++0x03
line.long 0x00 "RDMTCRB_2_1,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0x101C++0x03
line.long 0x00 "RDMCHCRB_2_1,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
newline
bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
newline
rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
newline
rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
newline
bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0x1028++0x03
line.long 0x00 "RDMTSR_2_1,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0x1038++0x03
line.long 0x00 "RDMTSRB_2_1,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0x1040++0x01
line.word 0x00 "RDMRS_2_1,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0x1048++0x03
line.long 0x00 "RDMBUFCR_2_1,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
newline
rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0x1050++0x03
line.long 0x00 "RDMDPBASE_2_1,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0x1054++0x03
line.long 0x00 "RDMDPCR_2_1,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1058++0x03
line.long 0x00 "RDMDPEVTCR_2_1,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
newline
bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x105C++0x03
line.long 0x00 "RDMDPEVTCNT_2_1,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
newline
hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0x1060++0x03
line.long 0x00 "RDMFIXDPBASE_2_1,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0x1064++0x03
line.long 0x00 "RDMDREQOS_2_1,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0x1078++0x03
line.long 0x00 "RDMREGIONID_2_1,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1080++0x03
line.long 0x00 "RDMCHID_2_1,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x10B0++0x03
line.long 0x00 "RDMSEC_2_1,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0x1100++0x03
line.long 0x00 "RDMCHCLR_2_1,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0x1110++0x03
line.long 0x00 "RDMISTA_2_1,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
newline
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0x2000++0x03
line.long 0x00 "RDMSAR_2_2,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0x2004++0x03
line.long 0x00 "RDMDAR_2_2,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0x2008++0x03
line.long 0x00 "RDMTCR_2_2,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0x200C++0x03
line.long 0x00 "RDMCHCR_2_2,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
newline
bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
newline
rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
newline
bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
newline
bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
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bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
newline
bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0x2010++0x03
line.long 0x00 "RDMFIXSAR_2_2,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0x2014++0x03
line.long 0x00 "RDMFIXDAR_2_2,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0x2018++0x03
line.long 0x00 "RDMTCRB_2_2,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0x201C++0x03
line.long 0x00 "RDMCHCRB_2_2,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
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bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
newline
rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
newline
rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
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bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0x2028++0x03
line.long 0x00 "RDMTSR_2_2,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0x2038++0x03
line.long 0x00 "RDMTSRB_2_2,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0x2040++0x01
line.word 0x00 "RDMRS_2_2,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0x2048++0x03
line.long 0x00 "RDMBUFCR_2_2,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
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rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0x2050++0x03
line.long 0x00 "RDMDPBASE_2_2,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0x2054++0x03
line.long 0x00 "RDMDPCR_2_2,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x2058++0x03
line.long 0x00 "RDMDPEVTCR_2_2,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
newline
bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x205C++0x03
line.long 0x00 "RDMDPEVTCNT_2_2,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
newline
hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0x2060++0x03
line.long 0x00 "RDMFIXDPBASE_2_2,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0x2064++0x03
line.long 0x00 "RDMDREQOS_2_2,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0x2078++0x03
line.long 0x00 "RDMREGIONID_2_2,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x2080++0x03
line.long 0x00 "RDMCHID_2_2,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x20B0++0x03
line.long 0x00 "RDMSEC_2_2,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0x2100++0x03
line.long 0x00 "RDMCHCLR_2_2,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0x2110++0x03
line.long 0x00 "RDMISTA_2_2,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
newline
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0x3000++0x03
line.long 0x00 "RDMSAR_2_3,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0x3004++0x03
line.long 0x00 "RDMDAR_2_3,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0x3008++0x03
line.long 0x00 "RDMTCR_2_3,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0x300C++0x03
line.long 0x00 "RDMCHCR_2_3,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
newline
bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
newline
rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
newline
bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
newline
bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
newline
bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
newline
bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0x3010++0x03
line.long 0x00 "RDMFIXSAR_2_3,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0x3014++0x03
line.long 0x00 "RDMFIXDAR_2_3,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0x3018++0x03
line.long 0x00 "RDMTCRB_2_3,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0x301C++0x03
line.long 0x00 "RDMCHCRB_2_3,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
newline
bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
newline
rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
newline
rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
newline
bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0x3028++0x03
line.long 0x00 "RDMTSR_2_3,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0x3038++0x03
line.long 0x00 "RDMTSRB_2_3,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0x3040++0x01
line.word 0x00 "RDMRS_2_3,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0x3048++0x03
line.long 0x00 "RDMBUFCR_2_3,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
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rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0x3050++0x03
line.long 0x00 "RDMDPBASE_2_3,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0x3054++0x03
line.long 0x00 "RDMDPCR_2_3,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x3058++0x03
line.long 0x00 "RDMDPEVTCR_2_3,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
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bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x305C++0x03
line.long 0x00 "RDMDPEVTCNT_2_3,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
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hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0x3060++0x03
line.long 0x00 "RDMFIXDPBASE_2_3,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0x3064++0x03
line.long 0x00 "RDMDREQOS_2_3,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0x3078++0x03
line.long 0x00 "RDMREGIONID_2_3,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x3080++0x03
line.long 0x00 "RDMCHID_2_3,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x30B0++0x03
line.long 0x00 "RDMSEC_2_3,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0x3100++0x03
line.long 0x00 "RDMCHCLR_2_3,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0x3110++0x03
line.long 0x00 "RDMISTA_2_3,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
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hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0x4000++0x03
line.long 0x00 "RDMSAR_2_4,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0x4004++0x03
line.long 0x00 "RDMDAR_2_4,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0x4008++0x03
line.long 0x00 "RDMTCR_2_4,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0x400C++0x03
line.long 0x00 "RDMCHCR_2_4,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
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bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
newline
rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
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bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
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bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
newline
bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
newline
bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0x4010++0x03
line.long 0x00 "RDMFIXSAR_2_4,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0x4014++0x03
line.long 0x00 "RDMFIXDAR_2_4,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0x4018++0x03
line.long 0x00 "RDMTCRB_2_4,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0x401C++0x03
line.long 0x00 "RDMCHCRB_2_4,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
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bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
newline
rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
newline
rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
newline
bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0x4028++0x03
line.long 0x00 "RDMTSR_2_4,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0x4038++0x03
line.long 0x00 "RDMTSRB_2_4,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0x4040++0x01
line.word 0x00 "RDMRS_2_4,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0x4048++0x03
line.long 0x00 "RDMBUFCR_2_4,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
newline
rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0x4050++0x03
line.long 0x00 "RDMDPBASE_2_4,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0x4054++0x03
line.long 0x00 "RDMDPCR_2_4,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4058++0x03
line.long 0x00 "RDMDPEVTCR_2_4,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
newline
bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x405C++0x03
line.long 0x00 "RDMDPEVTCNT_2_4,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
newline
hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0x4060++0x03
line.long 0x00 "RDMFIXDPBASE_2_4,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0x4064++0x03
line.long 0x00 "RDMDREQOS_2_4,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0x4078++0x03
line.long 0x00 "RDMREGIONID_2_4,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4080++0x03
line.long 0x00 "RDMCHID_2_4,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x40B0++0x03
line.long 0x00 "RDMSEC_2_4,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0x4100++0x03
line.long 0x00 "RDMCHCLR_2_4,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0x4110++0x03
line.long 0x00 "RDMISTA_2_4,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
newline
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0x5000++0x03
line.long 0x00 "RDMSAR_2_5,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0x5004++0x03
line.long 0x00 "RDMDAR_2_5,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0x5008++0x03
line.long 0x00 "RDMTCR_2_5,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0x500C++0x03
line.long 0x00 "RDMCHCR_2_5,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
newline
bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
newline
rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
newline
bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
newline
bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
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bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
newline
bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0x5010++0x03
line.long 0x00 "RDMFIXSAR_2_5,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0x5014++0x03
line.long 0x00 "RDMFIXDAR_2_5,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0x5018++0x03
line.long 0x00 "RDMTCRB_2_5,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0x501C++0x03
line.long 0x00 "RDMCHCRB_2_5,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
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bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
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rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
newline
rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
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bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0x5028++0x03
line.long 0x00 "RDMTSR_2_5,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0x5038++0x03
line.long 0x00 "RDMTSRB_2_5,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0x5040++0x01
line.word 0x00 "RDMRS_2_5,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0x5048++0x03
line.long 0x00 "RDMBUFCR_2_5,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
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rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0x5050++0x03
line.long 0x00 "RDMDPBASE_2_5,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0x5054++0x03
line.long 0x00 "RDMDPCR_2_5,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x5058++0x03
line.long 0x00 "RDMDPEVTCR_2_5,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
newline
bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x505C++0x03
line.long 0x00 "RDMDPEVTCNT_2_5,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
newline
hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0x5060++0x03
line.long 0x00 "RDMFIXDPBASE_2_5,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0x5064++0x03
line.long 0x00 "RDMDREQOS_2_5,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0x5078++0x03
line.long 0x00 "RDMREGIONID_2_5,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x5080++0x03
line.long 0x00 "RDMCHID_2_5,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x50B0++0x03
line.long 0x00 "RDMSEC_2_5,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0x5100++0x03
line.long 0x00 "RDMCHCLR_2_5,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0x5110++0x03
line.long 0x00 "RDMISTA_2_5,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
newline
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0x6000++0x03
line.long 0x00 "RDMSAR_2_6,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0x6004++0x03
line.long 0x00 "RDMDAR_2_6,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0x6008++0x03
line.long 0x00 "RDMTCR_2_6,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0x600C++0x03
line.long 0x00 "RDMCHCR_2_6,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
newline
bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
newline
rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
newline
bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
newline
bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
newline
bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
newline
bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0x6010++0x03
line.long 0x00 "RDMFIXSAR_2_6,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0x6014++0x03
line.long 0x00 "RDMFIXDAR_2_6,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0x6018++0x03
line.long 0x00 "RDMTCRB_2_6,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0x601C++0x03
line.long 0x00 "RDMCHCRB_2_6,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
newline
bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
newline
rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
newline
rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
newline
bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0x6028++0x03
line.long 0x00 "RDMTSR_2_6,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0x6038++0x03
line.long 0x00 "RDMTSRB_2_6,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0x6040++0x01
line.word 0x00 "RDMRS_2_6,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0x6048++0x03
line.long 0x00 "RDMBUFCR_2_6,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
newline
rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0x6050++0x03
line.long 0x00 "RDMDPBASE_2_6,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0x6054++0x03
line.long 0x00 "RDMDPCR_2_6,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x6058++0x03
line.long 0x00 "RDMDPEVTCR_2_6,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
newline
bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x605C++0x03
line.long 0x00 "RDMDPEVTCNT_2_6,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
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hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0x6060++0x03
line.long 0x00 "RDMFIXDPBASE_2_6,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0x6064++0x03
line.long 0x00 "RDMDREQOS_2_6,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0x6078++0x03
line.long 0x00 "RDMREGIONID_2_6,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x6080++0x03
line.long 0x00 "RDMCHID_2_6,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x60B0++0x03
line.long 0x00 "RDMSEC_2_6,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0x6100++0x03
line.long 0x00 "RDMCHCLR_2_6,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0x6110++0x03
line.long 0x00 "RDMISTA_2_6,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
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hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0x7000++0x03
line.long 0x00 "RDMSAR_2_7,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0x7004++0x03
line.long 0x00 "RDMDAR_2_7,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0x7008++0x03
line.long 0x00 "RDMTCR_2_7,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0x700C++0x03
line.long 0x00 "RDMCHCR_2_7,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
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bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
newline
rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
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bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
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bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
newline
bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
newline
bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0x7010++0x03
line.long 0x00 "RDMFIXSAR_2_7,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0x7014++0x03
line.long 0x00 "RDMFIXDAR_2_7,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0x7018++0x03
line.long 0x00 "RDMTCRB_2_7,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0x701C++0x03
line.long 0x00 "RDMCHCRB_2_7,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
newline
bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
newline
rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
newline
rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
newline
bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0x7028++0x03
line.long 0x00 "RDMTSR_2_7,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0x7038++0x03
line.long 0x00 "RDMTSRB_2_7,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0x7040++0x01
line.word 0x00 "RDMRS_2_7,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0x7048++0x03
line.long 0x00 "RDMBUFCR_2_7,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
newline
rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0x7050++0x03
line.long 0x00 "RDMDPBASE_2_7,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0x7054++0x03
line.long 0x00 "RDMDPCR_2_7,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x7058++0x03
line.long 0x00 "RDMDPEVTCR_2_7,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
newline
bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x705C++0x03
line.long 0x00 "RDMDPEVTCNT_2_7,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
newline
hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0x7060++0x03
line.long 0x00 "RDMFIXDPBASE_2_7,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0x7064++0x03
line.long 0x00 "RDMDREQOS_2_7,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0x7078++0x03
line.long 0x00 "RDMREGIONID_2_7,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x7080++0x03
line.long 0x00 "RDMCHID_2_7,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x70B0++0x03
line.long 0x00 "RDMSEC_2_7,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0x7100++0x03
line.long 0x00 "RDMCHCLR_2_7,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0x7110++0x03
line.long 0x00 "RDMISTA_2_7,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
newline
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0x8000++0x03
line.long 0x00 "RDMSAR_2_8,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0x8004++0x03
line.long 0x00 "RDMDAR_2_8,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0x8008++0x03
line.long 0x00 "RDMTCR_2_8,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0x800C++0x03
line.long 0x00 "RDMCHCR_2_8,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
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bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
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rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
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bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
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bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
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bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
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bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0x8010++0x03
line.long 0x00 "RDMFIXSAR_2_8,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0x8014++0x03
line.long 0x00 "RDMFIXDAR_2_8,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0x8018++0x03
line.long 0x00 "RDMTCRB_2_8,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0x801C++0x03
line.long 0x00 "RDMCHCRB_2_8,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
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bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
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rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
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rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
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bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0x8028++0x03
line.long 0x00 "RDMTSR_2_8,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0x8038++0x03
line.long 0x00 "RDMTSRB_2_8,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0x8040++0x01
line.word 0x00 "RDMRS_2_8,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0x8048++0x03
line.long 0x00 "RDMBUFCR_2_8,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
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rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0x8050++0x03
line.long 0x00 "RDMDPBASE_2_8,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0x8054++0x03
line.long 0x00 "RDMDPCR_2_8,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8058++0x03
line.long 0x00 "RDMDPEVTCR_2_8,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
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bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
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bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x805C++0x03
line.long 0x00 "RDMDPEVTCNT_2_8,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
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hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0x8060++0x03
line.long 0x00 "RDMFIXDPBASE_2_8,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0x8064++0x03
line.long 0x00 "RDMDREQOS_2_8,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0x8078++0x03
line.long 0x00 "RDMREGIONID_2_8,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8080++0x03
line.long 0x00 "RDMCHID_2_8,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x80B0++0x03
line.long 0x00 "RDMSEC_2_8,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0x8100++0x03
line.long 0x00 "RDMCHCLR_2_8,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0x8110++0x03
line.long 0x00 "RDMISTA_2_8,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
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hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0x9000++0x03
line.long 0x00 "RDMSAR_2_9,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0x9004++0x03
line.long 0x00 "RDMDAR_2_9,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0x9008++0x03
line.long 0x00 "RDMTCR_2_9,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0x900C++0x03
line.long 0x00 "RDMCHCR_2_9,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
newline
bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
newline
rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
newline
bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
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bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
newline
bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
newline
bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0x9010++0x03
line.long 0x00 "RDMFIXSAR_2_9,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0x9014++0x03
line.long 0x00 "RDMFIXDAR_2_9,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0x9018++0x03
line.long 0x00 "RDMTCRB_2_9,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0x901C++0x03
line.long 0x00 "RDMCHCRB_2_9,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
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bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
newline
rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
newline
rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
newline
bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0x9028++0x03
line.long 0x00 "RDMTSR_2_9,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0x9038++0x03
line.long 0x00 "RDMTSRB_2_9,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0x9040++0x01
line.word 0x00 "RDMRS_2_9,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0x9048++0x03
line.long 0x00 "RDMBUFCR_2_9,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
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rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0x9050++0x03
line.long 0x00 "RDMDPBASE_2_9,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0x9054++0x03
line.long 0x00 "RDMDPCR_2_9,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x9058++0x03
line.long 0x00 "RDMDPEVTCR_2_9,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
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bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
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bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x905C++0x03
line.long 0x00 "RDMDPEVTCNT_2_9,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
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hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0x9060++0x03
line.long 0x00 "RDMFIXDPBASE_2_9,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0x9064++0x03
line.long 0x00 "RDMDREQOS_2_9,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0x9078++0x03
line.long 0x00 "RDMREGIONID_2_9,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x9080++0x03
line.long 0x00 "RDMCHID_2_9,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x90B0++0x03
line.long 0x00 "RDMSEC_2_9,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0x9100++0x03
line.long 0x00 "RDMCHCLR_2_9,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0x9110++0x03
line.long 0x00 "RDMISTA_2_9,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
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hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0xA000++0x03
line.long 0x00 "RDMSAR_2_10,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0xA004++0x03
line.long 0x00 "RDMDAR_2_10,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0xA008++0x03
line.long 0x00 "RDMTCR_2_10,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0xA00C++0x03
line.long 0x00 "RDMCHCR_2_10,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
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bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
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rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
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bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
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bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
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bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
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bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0xA010++0x03
line.long 0x00 "RDMFIXSAR_2_10,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0xA014++0x03
line.long 0x00 "RDMFIXDAR_2_10,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0xA018++0x03
line.long 0x00 "RDMTCRB_2_10,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0xA01C++0x03
line.long 0x00 "RDMCHCRB_2_10,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
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bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
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rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
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rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
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bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0xA028++0x03
line.long 0x00 "RDMTSR_2_10,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0xA038++0x03
line.long 0x00 "RDMTSRB_2_10,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0xA040++0x01
line.word 0x00 "RDMRS_2_10,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0xA048++0x03
line.long 0x00 "RDMBUFCR_2_10,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
newline
rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0xA050++0x03
line.long 0x00 "RDMDPBASE_2_10,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0xA054++0x03
line.long 0x00 "RDMDPCR_2_10,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA058++0x03
line.long 0x00 "RDMDPEVTCR_2_10,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
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bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xA05C++0x03
line.long 0x00 "RDMDPEVTCNT_2_10,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
newline
hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0xA060++0x03
line.long 0x00 "RDMFIXDPBASE_2_10,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0xA064++0x03
line.long 0x00 "RDMDREQOS_2_10,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0xA078++0x03
line.long 0x00 "RDMREGIONID_2_10,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA080++0x03
line.long 0x00 "RDMCHID_2_10,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA0B0++0x03
line.long 0x00 "RDMSEC_2_10,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0xA100++0x03
line.long 0x00 "RDMCHCLR_2_10,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0xA110++0x03
line.long 0x00 "RDMISTA_2_10,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
newline
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0xB000++0x03
line.long 0x00 "RDMSAR_2_11,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0xB004++0x03
line.long 0x00 "RDMDAR_2_11,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0xB008++0x03
line.long 0x00 "RDMTCR_2_11,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0xB00C++0x03
line.long 0x00 "RDMCHCR_2_11,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
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bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
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rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
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bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
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bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
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bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
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bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0xB010++0x03
line.long 0x00 "RDMFIXSAR_2_11,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0xB014++0x03
line.long 0x00 "RDMFIXDAR_2_11,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0xB018++0x03
line.long 0x00 "RDMTCRB_2_11,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0xB01C++0x03
line.long 0x00 "RDMCHCRB_2_11,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
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bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
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rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
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rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
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bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0xB028++0x03
line.long 0x00 "RDMTSR_2_11,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0xB038++0x03
line.long 0x00 "RDMTSRB_2_11,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0xB040++0x01
line.word 0x00 "RDMRS_2_11,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0xB048++0x03
line.long 0x00 "RDMBUFCR_2_11,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
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rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0xB050++0x03
line.long 0x00 "RDMDPBASE_2_11,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0xB054++0x03
line.long 0x00 "RDMDPCR_2_11,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB058++0x03
line.long 0x00 "RDMDPEVTCR_2_11,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
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bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
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bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xB05C++0x03
line.long 0x00 "RDMDPEVTCNT_2_11,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
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hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0xB060++0x03
line.long 0x00 "RDMFIXDPBASE_2_11,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0xB064++0x03
line.long 0x00 "RDMDREQOS_2_11,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0xB078++0x03
line.long 0x00 "RDMREGIONID_2_11,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB080++0x03
line.long 0x00 "RDMCHID_2_11,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB0B0++0x03
line.long 0x00 "RDMSEC_2_11,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0xB100++0x03
line.long 0x00 "RDMCHCLR_2_11,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0xB110++0x03
line.long 0x00 "RDMISTA_2_11,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
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hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0xC000++0x03
line.long 0x00 "RDMSAR_2_12,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0xC004++0x03
line.long 0x00 "RDMDAR_2_12,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0xC008++0x03
line.long 0x00 "RDMTCR_2_12,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0xC00C++0x03
line.long 0x00 "RDMCHCR_2_12,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
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bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
newline
rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
newline
bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
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bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
newline
bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
newline
bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0xC010++0x03
line.long 0x00 "RDMFIXSAR_2_12,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0xC014++0x03
line.long 0x00 "RDMFIXDAR_2_12,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0xC018++0x03
line.long 0x00 "RDMTCRB_2_12,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0xC01C++0x03
line.long 0x00 "RDMCHCRB_2_12,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
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bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
newline
rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
newline
rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
newline
bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0xC028++0x03
line.long 0x00 "RDMTSR_2_12,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0xC038++0x03
line.long 0x00 "RDMTSRB_2_12,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0xC040++0x01
line.word 0x00 "RDMRS_2_12,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0xC048++0x03
line.long 0x00 "RDMBUFCR_2_12,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
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rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0xC050++0x03
line.long 0x00 "RDMDPBASE_2_12,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0xC054++0x03
line.long 0x00 "RDMDPCR_2_12,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC058++0x03
line.long 0x00 "RDMDPEVTCR_2_12,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
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bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
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bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xC05C++0x03
line.long 0x00 "RDMDPEVTCNT_2_12,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
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hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0xC060++0x03
line.long 0x00 "RDMFIXDPBASE_2_12,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0xC064++0x03
line.long 0x00 "RDMDREQOS_2_12,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0xC078++0x03
line.long 0x00 "RDMREGIONID_2_12,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC080++0x03
line.long 0x00 "RDMCHID_2_12,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC0B0++0x03
line.long 0x00 "RDMSEC_2_12,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0xC100++0x03
line.long 0x00 "RDMCHCLR_2_12,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0xC110++0x03
line.long 0x00 "RDMISTA_2_12,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
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hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0xD000++0x03
line.long 0x00 "RDMSAR_2_13,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0xD004++0x03
line.long 0x00 "RDMDAR_2_13,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0xD008++0x03
line.long 0x00 "RDMTCR_2_13,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0xD00C++0x03
line.long 0x00 "RDMCHCR_2_13,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
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bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
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rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
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bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
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bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
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bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
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bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0xD010++0x03
line.long 0x00 "RDMFIXSAR_2_13,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0xD014++0x03
line.long 0x00 "RDMFIXDAR_2_13,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0xD018++0x03
line.long 0x00 "RDMTCRB_2_13,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0xD01C++0x03
line.long 0x00 "RDMCHCRB_2_13,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
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bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
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rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
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rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
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bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0xD028++0x03
line.long 0x00 "RDMTSR_2_13,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0xD038++0x03
line.long 0x00 "RDMTSRB_2_13,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0xD040++0x01
line.word 0x00 "RDMRS_2_13,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0xD048++0x03
line.long 0x00 "RDMBUFCR_2_13,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
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rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0xD050++0x03
line.long 0x00 "RDMDPBASE_2_13,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0xD054++0x03
line.long 0x00 "RDMDPCR_2_13,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xD058++0x03
line.long 0x00 "RDMDPEVTCR_2_13,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
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bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
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bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xD05C++0x03
line.long 0x00 "RDMDPEVTCNT_2_13,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
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hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0xD060++0x03
line.long 0x00 "RDMFIXDPBASE_2_13,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0xD064++0x03
line.long 0x00 "RDMDREQOS_2_13,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0xD078++0x03
line.long 0x00 "RDMREGIONID_2_13,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xD080++0x03
line.long 0x00 "RDMCHID_2_13,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xD0B0++0x03
line.long 0x00 "RDMSEC_2_13,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0xD100++0x03
line.long 0x00 "RDMCHCLR_2_13,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0xD110++0x03
line.long 0x00 "RDMISTA_2_13,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
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hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0xE000++0x03
line.long 0x00 "RDMSAR_2_14,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0xE004++0x03
line.long 0x00 "RDMDAR_2_14,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0xE008++0x03
line.long 0x00 "RDMTCR_2_14,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0xE00C++0x03
line.long 0x00 "RDMCHCR_2_14,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
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bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
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rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
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bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
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bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
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bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
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bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0xE010++0x03
line.long 0x00 "RDMFIXSAR_2_14,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0xE014++0x03
line.long 0x00 "RDMFIXDAR_2_14,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0xE018++0x03
line.long 0x00 "RDMTCRB_2_14,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0xE01C++0x03
line.long 0x00 "RDMCHCRB_2_14,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
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bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
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rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
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rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
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bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0xE028++0x03
line.long 0x00 "RDMTSR_2_14,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0xE038++0x03
line.long 0x00 "RDMTSRB_2_14,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0xE040++0x01
line.word 0x00 "RDMRS_2_14,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0xE048++0x03
line.long 0x00 "RDMBUFCR_2_14,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
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rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0xE050++0x03
line.long 0x00 "RDMDPBASE_2_14,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0xE054++0x03
line.long 0x00 "RDMDPCR_2_14,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xE058++0x03
line.long 0x00 "RDMDPEVTCR_2_14,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
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bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
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bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xE05C++0x03
line.long 0x00 "RDMDPEVTCNT_2_14,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
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hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0xE060++0x03
line.long 0x00 "RDMFIXDPBASE_2_14,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0xE064++0x03
line.long 0x00 "RDMDREQOS_2_14,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0xE078++0x03
line.long 0x00 "RDMREGIONID_2_14,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xE080++0x03
line.long 0x00 "RDMCHID_2_14,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xE0B0++0x03
line.long 0x00 "RDMSEC_2_14,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0xE100++0x03
line.long 0x00 "RDMCHCLR_2_14,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0xE110++0x03
line.long 0x00 "RDMISTA_2_14,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
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hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0xF000++0x03
line.long 0x00 "RDMSAR_2_15,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0xF004++0x03
line.long 0x00 "RDMDAR_2_15,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0xF008++0x03
line.long 0x00 "RDMTCR_2_15,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0xF00C++0x03
line.long 0x00 "RDMCHCR_2_15,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
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bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
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rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
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bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
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bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
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bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
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bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0xF010++0x03
line.long 0x00 "RDMFIXSAR_2_15,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0xF014++0x03
line.long 0x00 "RDMFIXDAR_2_15,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0xF018++0x03
line.long 0x00 "RDMTCRB_2_15,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0xF01C++0x03
line.long 0x00 "RDMCHCRB_2_15,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
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bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
newline
rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
newline
rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
newline
bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0xF028++0x03
line.long 0x00 "RDMTSR_2_15,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0xF038++0x03
line.long 0x00 "RDMTSRB_2_15,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0xF040++0x01
line.word 0x00 "RDMRS_2_15,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0xF048++0x03
line.long 0x00 "RDMBUFCR_2_15,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
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rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0xF050++0x03
line.long 0x00 "RDMDPBASE_2_15,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0xF054++0x03
line.long 0x00 "RDMDPCR_2_15,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xF058++0x03
line.long 0x00 "RDMDPEVTCR_2_15,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
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bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
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bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xF05C++0x03
line.long 0x00 "RDMDPEVTCNT_2_15,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
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hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0xF060++0x03
line.long 0x00 "RDMFIXDPBASE_2_15,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0xF064++0x03
line.long 0x00 "RDMDREQOS_2_15,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0xF078++0x03
line.long 0x00 "RDMREGIONID_2_15,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xF080++0x03
line.long 0x00 "RDMCHID_2_15,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xF0B0++0x03
line.long 0x00 "RDMSEC_2_15,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0xF100++0x03
line.long 0x00 "RDMCHCLR_2_15,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0xF110++0x03
line.long 0x00 "RDMISTA_2_15,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
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hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
tree.end
tree "DMAC_INST_7"
base ad:0xFFD80000
group.long 0x00++0x03
line.long 0x00 "RDMSAR_3_0,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0x04++0x03
line.long 0x00 "RDMDAR_3_0,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0x08++0x03
line.long 0x00 "RDMTCR_3_0,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0x0C++0x03
line.long 0x00 "RDMCHCR_3_0,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
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bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
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rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
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bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
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bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
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bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
newline
bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0x10++0x03
line.long 0x00 "RDMFIXSAR_3_0,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0x14++0x03
line.long 0x00 "RDMFIXDAR_3_0,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0x18++0x03
line.long 0x00 "RDMTCRB_3_0,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0x1C++0x03
line.long 0x00 "RDMCHCRB_3_0,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
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bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
newline
rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
newline
rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
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bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0x28++0x03
line.long 0x00 "RDMTSR_3_0,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0x38++0x03
line.long 0x00 "RDMTSRB_3_0,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0x40++0x01
line.word 0x00 "RDMRS_3_0,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0x48++0x03
line.long 0x00 "RDMBUFCR_3_0,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
newline
rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0x50++0x03
line.long 0x00 "RDMDPBASE_3_0,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0x54++0x03
line.long 0x00 "RDMDPCR_3_0,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x58++0x03
line.long 0x00 "RDMDPEVTCR_3_0,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
newline
bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x5C++0x03
line.long 0x00 "RDMDPEVTCNT_3_0,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
newline
hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0x60++0x03
line.long 0x00 "RDMFIXDPBASE_3_0,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0x64++0x03
line.long 0x00 "RDMDREQOS_3_0,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0x78++0x03
line.long 0x00 "RDMREGIONID_3_0,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x80++0x03
line.long 0x00 "RDMCHID_3_0,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB0++0x03
line.long 0x00 "RDMSEC_3_0,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0x100++0x03
line.long 0x00 "RDMCHCLR_3_0,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0x110++0x03
line.long 0x00 "RDMISTA_3_0,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
newline
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0x1000++0x03
line.long 0x00 "RDMSAR_3_1,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0x1004++0x03
line.long 0x00 "RDMDAR_3_1,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0x1008++0x03
line.long 0x00 "RDMTCR_3_1,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0x100C++0x03
line.long 0x00 "RDMCHCR_3_1,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
newline
bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
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rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
newline
bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
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bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
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bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
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bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0x1010++0x03
line.long 0x00 "RDMFIXSAR_3_1,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0x1014++0x03
line.long 0x00 "RDMFIXDAR_3_1,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0x1018++0x03
line.long 0x00 "RDMTCRB_3_1,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0x101C++0x03
line.long 0x00 "RDMCHCRB_3_1,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
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bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
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rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
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rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
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bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0x1028++0x03
line.long 0x00 "RDMTSR_3_1,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0x1038++0x03
line.long 0x00 "RDMTSRB_3_1,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0x1040++0x01
line.word 0x00 "RDMRS_3_1,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0x1048++0x03
line.long 0x00 "RDMBUFCR_3_1,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
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rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0x1050++0x03
line.long 0x00 "RDMDPBASE_3_1,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0x1054++0x03
line.long 0x00 "RDMDPCR_3_1,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1058++0x03
line.long 0x00 "RDMDPEVTCR_3_1,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
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bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
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bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x105C++0x03
line.long 0x00 "RDMDPEVTCNT_3_1,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
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hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0x1060++0x03
line.long 0x00 "RDMFIXDPBASE_3_1,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0x1064++0x03
line.long 0x00 "RDMDREQOS_3_1,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0x1078++0x03
line.long 0x00 "RDMREGIONID_3_1,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1080++0x03
line.long 0x00 "RDMCHID_3_1,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x10B0++0x03
line.long 0x00 "RDMSEC_3_1,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0x1100++0x03
line.long 0x00 "RDMCHCLR_3_1,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0x1110++0x03
line.long 0x00 "RDMISTA_3_1,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
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hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0x2000++0x03
line.long 0x00 "RDMSAR_3_2,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0x2004++0x03
line.long 0x00 "RDMDAR_3_2,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0x2008++0x03
line.long 0x00 "RDMTCR_3_2,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0x200C++0x03
line.long 0x00 "RDMCHCR_3_2,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
newline
bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
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rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
newline
bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
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bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
newline
bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
newline
bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0x2010++0x03
line.long 0x00 "RDMFIXSAR_3_2,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0x2014++0x03
line.long 0x00 "RDMFIXDAR_3_2,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0x2018++0x03
line.long 0x00 "RDMTCRB_3_2,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0x201C++0x03
line.long 0x00 "RDMCHCRB_3_2,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
newline
bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
newline
rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
newline
rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
newline
bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0x2028++0x03
line.long 0x00 "RDMTSR_3_2,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0x2038++0x03
line.long 0x00 "RDMTSRB_3_2,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0x2040++0x01
line.word 0x00 "RDMRS_3_2,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0x2048++0x03
line.long 0x00 "RDMBUFCR_3_2,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
newline
rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0x2050++0x03
line.long 0x00 "RDMDPBASE_3_2,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0x2054++0x03
line.long 0x00 "RDMDPCR_3_2,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x2058++0x03
line.long 0x00 "RDMDPEVTCR_3_2,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
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bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
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bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x205C++0x03
line.long 0x00 "RDMDPEVTCNT_3_2,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
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hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0x2060++0x03
line.long 0x00 "RDMFIXDPBASE_3_2,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0x2064++0x03
line.long 0x00 "RDMDREQOS_3_2,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0x2078++0x03
line.long 0x00 "RDMREGIONID_3_2,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x2080++0x03
line.long 0x00 "RDMCHID_3_2,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x20B0++0x03
line.long 0x00 "RDMSEC_3_2,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0x2100++0x03
line.long 0x00 "RDMCHCLR_3_2,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0x2110++0x03
line.long 0x00 "RDMISTA_3_2,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
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hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0x3000++0x03
line.long 0x00 "RDMSAR_3_3,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0x3004++0x03
line.long 0x00 "RDMDAR_3_3,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0x3008++0x03
line.long 0x00 "RDMTCR_3_3,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0x300C++0x03
line.long 0x00 "RDMCHCR_3_3,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
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bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
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rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
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bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
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bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
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bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
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bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0x3010++0x03
line.long 0x00 "RDMFIXSAR_3_3,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0x3014++0x03
line.long 0x00 "RDMFIXDAR_3_3,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0x3018++0x03
line.long 0x00 "RDMTCRB_3_3,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0x301C++0x03
line.long 0x00 "RDMCHCRB_3_3,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
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bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
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rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
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rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
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bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0x3028++0x03
line.long 0x00 "RDMTSR_3_3,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0x3038++0x03
line.long 0x00 "RDMTSRB_3_3,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0x3040++0x01
line.word 0x00 "RDMRS_3_3,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0x3048++0x03
line.long 0x00 "RDMBUFCR_3_3,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
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rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0x3050++0x03
line.long 0x00 "RDMDPBASE_3_3,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0x3054++0x03
line.long 0x00 "RDMDPCR_3_3,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x3058++0x03
line.long 0x00 "RDMDPEVTCR_3_3,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
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bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x305C++0x03
line.long 0x00 "RDMDPEVTCNT_3_3,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
newline
hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0x3060++0x03
line.long 0x00 "RDMFIXDPBASE_3_3,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0x3064++0x03
line.long 0x00 "RDMDREQOS_3_3,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0x3078++0x03
line.long 0x00 "RDMREGIONID_3_3,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x3080++0x03
line.long 0x00 "RDMCHID_3_3,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x30B0++0x03
line.long 0x00 "RDMSEC_3_3,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0x3100++0x03
line.long 0x00 "RDMCHCLR_3_3,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0x3110++0x03
line.long 0x00 "RDMISTA_3_3,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
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hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0x4000++0x03
line.long 0x00 "RDMSAR_3_4,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0x4004++0x03
line.long 0x00 "RDMDAR_3_4,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0x4008++0x03
line.long 0x00 "RDMTCR_3_4,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0x400C++0x03
line.long 0x00 "RDMCHCR_3_4,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
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bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
newline
rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
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bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
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bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
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bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
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bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0x4010++0x03
line.long 0x00 "RDMFIXSAR_3_4,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0x4014++0x03
line.long 0x00 "RDMFIXDAR_3_4,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0x4018++0x03
line.long 0x00 "RDMTCRB_3_4,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0x401C++0x03
line.long 0x00 "RDMCHCRB_3_4,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
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bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
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rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
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rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
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bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0x4028++0x03
line.long 0x00 "RDMTSR_3_4,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0x4038++0x03
line.long 0x00 "RDMTSRB_3_4,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0x4040++0x01
line.word 0x00 "RDMRS_3_4,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0x4048++0x03
line.long 0x00 "RDMBUFCR_3_4,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
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rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0x4050++0x03
line.long 0x00 "RDMDPBASE_3_4,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0x4054++0x03
line.long 0x00 "RDMDPCR_3_4,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4058++0x03
line.long 0x00 "RDMDPEVTCR_3_4,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
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bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
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bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x405C++0x03
line.long 0x00 "RDMDPEVTCNT_3_4,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
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hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0x4060++0x03
line.long 0x00 "RDMFIXDPBASE_3_4,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0x4064++0x03
line.long 0x00 "RDMDREQOS_3_4,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0x4078++0x03
line.long 0x00 "RDMREGIONID_3_4,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4080++0x03
line.long 0x00 "RDMCHID_3_4,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x40B0++0x03
line.long 0x00 "RDMSEC_3_4,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0x4100++0x03
line.long 0x00 "RDMCHCLR_3_4,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0x4110++0x03
line.long 0x00 "RDMISTA_3_4,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
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hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0x5000++0x03
line.long 0x00 "RDMSAR_3_5,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0x5004++0x03
line.long 0x00 "RDMDAR_3_5,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0x5008++0x03
line.long 0x00 "RDMTCR_3_5,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0x500C++0x03
line.long 0x00 "RDMCHCR_3_5,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
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bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
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rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
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bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
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bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
newline
bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
newline
bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0x5010++0x03
line.long 0x00 "RDMFIXSAR_3_5,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0x5014++0x03
line.long 0x00 "RDMFIXDAR_3_5,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0x5018++0x03
line.long 0x00 "RDMTCRB_3_5,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0x501C++0x03
line.long 0x00 "RDMCHCRB_3_5,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
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bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
newline
rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
newline
rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
newline
bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0x5028++0x03
line.long 0x00 "RDMTSR_3_5,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0x5038++0x03
line.long 0x00 "RDMTSRB_3_5,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0x5040++0x01
line.word 0x00 "RDMRS_3_5,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0x5048++0x03
line.long 0x00 "RDMBUFCR_3_5,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
newline
rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0x5050++0x03
line.long 0x00 "RDMDPBASE_3_5,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0x5054++0x03
line.long 0x00 "RDMDPCR_3_5,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x5058++0x03
line.long 0x00 "RDMDPEVTCR_3_5,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
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bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
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bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x505C++0x03
line.long 0x00 "RDMDPEVTCNT_3_5,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
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hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0x5060++0x03
line.long 0x00 "RDMFIXDPBASE_3_5,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0x5064++0x03
line.long 0x00 "RDMDREQOS_3_5,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0x5078++0x03
line.long 0x00 "RDMREGIONID_3_5,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x5080++0x03
line.long 0x00 "RDMCHID_3_5,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x50B0++0x03
line.long 0x00 "RDMSEC_3_5,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0x5100++0x03
line.long 0x00 "RDMCHCLR_3_5,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0x5110++0x03
line.long 0x00 "RDMISTA_3_5,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
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hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0x6000++0x03
line.long 0x00 "RDMSAR_3_6,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0x6004++0x03
line.long 0x00 "RDMDAR_3_6,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0x6008++0x03
line.long 0x00 "RDMTCR_3_6,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0x600C++0x03
line.long 0x00 "RDMCHCR_3_6,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
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bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
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rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
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bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
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bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
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bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
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bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0x6010++0x03
line.long 0x00 "RDMFIXSAR_3_6,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0x6014++0x03
line.long 0x00 "RDMFIXDAR_3_6,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0x6018++0x03
line.long 0x00 "RDMTCRB_3_6,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0x601C++0x03
line.long 0x00 "RDMCHCRB_3_6,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
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bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
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rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
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rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
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bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0x6028++0x03
line.long 0x00 "RDMTSR_3_6,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0x6038++0x03
line.long 0x00 "RDMTSRB_3_6,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0x6040++0x01
line.word 0x00 "RDMRS_3_6,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0x6048++0x03
line.long 0x00 "RDMBUFCR_3_6,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
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rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0x6050++0x03
line.long 0x00 "RDMDPBASE_3_6,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0x6054++0x03
line.long 0x00 "RDMDPCR_3_6,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x6058++0x03
line.long 0x00 "RDMDPEVTCR_3_6,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
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bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x605C++0x03
line.long 0x00 "RDMDPEVTCNT_3_6,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
newline
hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0x6060++0x03
line.long 0x00 "RDMFIXDPBASE_3_6,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0x6064++0x03
line.long 0x00 "RDMDREQOS_3_6,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0x6078++0x03
line.long 0x00 "RDMREGIONID_3_6,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x6080++0x03
line.long 0x00 "RDMCHID_3_6,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x60B0++0x03
line.long 0x00 "RDMSEC_3_6,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0x6100++0x03
line.long 0x00 "RDMCHCLR_3_6,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0x6110++0x03
line.long 0x00 "RDMISTA_3_6,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
newline
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0x7000++0x03
line.long 0x00 "RDMSAR_3_7,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0x7004++0x03
line.long 0x00 "RDMDAR_3_7,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0x7008++0x03
line.long 0x00 "RDMTCR_3_7,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0x700C++0x03
line.long 0x00 "RDMCHCR_3_7,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
newline
bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
newline
rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
newline
bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
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bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
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bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
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bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0x7010++0x03
line.long 0x00 "RDMFIXSAR_3_7,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0x7014++0x03
line.long 0x00 "RDMFIXDAR_3_7,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0x7018++0x03
line.long 0x00 "RDMTCRB_3_7,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0x701C++0x03
line.long 0x00 "RDMCHCRB_3_7,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
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bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
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rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
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rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
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bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0x7028++0x03
line.long 0x00 "RDMTSR_3_7,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0x7038++0x03
line.long 0x00 "RDMTSRB_3_7,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0x7040++0x01
line.word 0x00 "RDMRS_3_7,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0x7048++0x03
line.long 0x00 "RDMBUFCR_3_7,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
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rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0x7050++0x03
line.long 0x00 "RDMDPBASE_3_7,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0x7054++0x03
line.long 0x00 "RDMDPCR_3_7,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x7058++0x03
line.long 0x00 "RDMDPEVTCR_3_7,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
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bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
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bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x705C++0x03
line.long 0x00 "RDMDPEVTCNT_3_7,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
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hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0x7060++0x03
line.long 0x00 "RDMFIXDPBASE_3_7,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0x7064++0x03
line.long 0x00 "RDMDREQOS_3_7,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0x7078++0x03
line.long 0x00 "RDMREGIONID_3_7,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x7080++0x03
line.long 0x00 "RDMCHID_3_7,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x70B0++0x03
line.long 0x00 "RDMSEC_3_7,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0x7100++0x03
line.long 0x00 "RDMCHCLR_3_7,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0x7110++0x03
line.long 0x00 "RDMISTA_3_7,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
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hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0x8000++0x03
line.long 0x00 "RDMSAR_3_8,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0x8004++0x03
line.long 0x00 "RDMDAR_3_8,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0x8008++0x03
line.long 0x00 "RDMTCR_3_8,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0x800C++0x03
line.long 0x00 "RDMCHCR_3_8,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
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bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
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rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
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bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
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bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
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bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
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bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0x8010++0x03
line.long 0x00 "RDMFIXSAR_3_8,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0x8014++0x03
line.long 0x00 "RDMFIXDAR_3_8,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0x8018++0x03
line.long 0x00 "RDMTCRB_3_8,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0x801C++0x03
line.long 0x00 "RDMCHCRB_3_8,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
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bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
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rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
newline
rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
newline
bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0x8028++0x03
line.long 0x00 "RDMTSR_3_8,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0x8038++0x03
line.long 0x00 "RDMTSRB_3_8,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0x8040++0x01
line.word 0x00 "RDMRS_3_8,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0x8048++0x03
line.long 0x00 "RDMBUFCR_3_8,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
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rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0x8050++0x03
line.long 0x00 "RDMDPBASE_3_8,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0x8054++0x03
line.long 0x00 "RDMDPCR_3_8,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8058++0x03
line.long 0x00 "RDMDPEVTCR_3_8,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
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bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
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bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x805C++0x03
line.long 0x00 "RDMDPEVTCNT_3_8,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
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hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0x8060++0x03
line.long 0x00 "RDMFIXDPBASE_3_8,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0x8064++0x03
line.long 0x00 "RDMDREQOS_3_8,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0x8078++0x03
line.long 0x00 "RDMREGIONID_3_8,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8080++0x03
line.long 0x00 "RDMCHID_3_8,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x80B0++0x03
line.long 0x00 "RDMSEC_3_8,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0x8100++0x03
line.long 0x00 "RDMCHCLR_3_8,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0x8110++0x03
line.long 0x00 "RDMISTA_3_8,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
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hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0x9000++0x03
line.long 0x00 "RDMSAR_3_9,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0x9004++0x03
line.long 0x00 "RDMDAR_3_9,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0x9008++0x03
line.long 0x00 "RDMTCR_3_9,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0x900C++0x03
line.long 0x00 "RDMCHCR_3_9,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
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bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
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rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
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bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
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bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
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bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
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bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0x9010++0x03
line.long 0x00 "RDMFIXSAR_3_9,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0x9014++0x03
line.long 0x00 "RDMFIXDAR_3_9,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0x9018++0x03
line.long 0x00 "RDMTCRB_3_9,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0x901C++0x03
line.long 0x00 "RDMCHCRB_3_9,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
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bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
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rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
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rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
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bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0x9028++0x03
line.long 0x00 "RDMTSR_3_9,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0x9038++0x03
line.long 0x00 "RDMTSRB_3_9,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0x9040++0x01
line.word 0x00 "RDMRS_3_9,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0x9048++0x03
line.long 0x00 "RDMBUFCR_3_9,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
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rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0x9050++0x03
line.long 0x00 "RDMDPBASE_3_9,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0x9054++0x03
line.long 0x00 "RDMDPCR_3_9,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x9058++0x03
line.long 0x00 "RDMDPEVTCR_3_9,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
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bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
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bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x905C++0x03
line.long 0x00 "RDMDPEVTCNT_3_9,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
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hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0x9060++0x03
line.long 0x00 "RDMFIXDPBASE_3_9,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0x9064++0x03
line.long 0x00 "RDMDREQOS_3_9,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0x9078++0x03
line.long 0x00 "RDMREGIONID_3_9,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x9080++0x03
line.long 0x00 "RDMCHID_3_9,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x90B0++0x03
line.long 0x00 "RDMSEC_3_9,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0x9100++0x03
line.long 0x00 "RDMCHCLR_3_9,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0x9110++0x03
line.long 0x00 "RDMISTA_3_9,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
newline
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0xA000++0x03
line.long 0x00 "RDMSAR_3_10,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0xA004++0x03
line.long 0x00 "RDMDAR_3_10,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0xA008++0x03
line.long 0x00 "RDMTCR_3_10,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0xA00C++0x03
line.long 0x00 "RDMCHCR_3_10,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
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bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
newline
rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
newline
bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
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bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
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bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
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bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0xA010++0x03
line.long 0x00 "RDMFIXSAR_3_10,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0xA014++0x03
line.long 0x00 "RDMFIXDAR_3_10,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0xA018++0x03
line.long 0x00 "RDMTCRB_3_10,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0xA01C++0x03
line.long 0x00 "RDMCHCRB_3_10,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
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bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
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rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
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rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
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bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0xA028++0x03
line.long 0x00 "RDMTSR_3_10,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0xA038++0x03
line.long 0x00 "RDMTSRB_3_10,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0xA040++0x01
line.word 0x00 "RDMRS_3_10,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0xA048++0x03
line.long 0x00 "RDMBUFCR_3_10,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
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rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0xA050++0x03
line.long 0x00 "RDMDPBASE_3_10,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0xA054++0x03
line.long 0x00 "RDMDPCR_3_10,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA058++0x03
line.long 0x00 "RDMDPEVTCR_3_10,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
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bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
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bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xA05C++0x03
line.long 0x00 "RDMDPEVTCNT_3_10,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
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hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0xA060++0x03
line.long 0x00 "RDMFIXDPBASE_3_10,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0xA064++0x03
line.long 0x00 "RDMDREQOS_3_10,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0xA078++0x03
line.long 0x00 "RDMREGIONID_3_10,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA080++0x03
line.long 0x00 "RDMCHID_3_10,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA0B0++0x03
line.long 0x00 "RDMSEC_3_10,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0xA100++0x03
line.long 0x00 "RDMCHCLR_3_10,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0xA110++0x03
line.long 0x00 "RDMISTA_3_10,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
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hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0xB000++0x03
line.long 0x00 "RDMSAR_3_11,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0xB004++0x03
line.long 0x00 "RDMDAR_3_11,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0xB008++0x03
line.long 0x00 "RDMTCR_3_11,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0xB00C++0x03
line.long 0x00 "RDMCHCR_3_11,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
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bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
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rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
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bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
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bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
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bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
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bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0xB010++0x03
line.long 0x00 "RDMFIXSAR_3_11,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0xB014++0x03
line.long 0x00 "RDMFIXDAR_3_11,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0xB018++0x03
line.long 0x00 "RDMTCRB_3_11,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0xB01C++0x03
line.long 0x00 "RDMCHCRB_3_11,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
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bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
newline
rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
newline
rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
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bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0xB028++0x03
line.long 0x00 "RDMTSR_3_11,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0xB038++0x03
line.long 0x00 "RDMTSRB_3_11,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0xB040++0x01
line.word 0x00 "RDMRS_3_11,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0xB048++0x03
line.long 0x00 "RDMBUFCR_3_11,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
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rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0xB050++0x03
line.long 0x00 "RDMDPBASE_3_11,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0xB054++0x03
line.long 0x00 "RDMDPCR_3_11,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB058++0x03
line.long 0x00 "RDMDPEVTCR_3_11,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
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bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
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bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xB05C++0x03
line.long 0x00 "RDMDPEVTCNT_3_11,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
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hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0xB060++0x03
line.long 0x00 "RDMFIXDPBASE_3_11,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0xB064++0x03
line.long 0x00 "RDMDREQOS_3_11,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0xB078++0x03
line.long 0x00 "RDMREGIONID_3_11,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB080++0x03
line.long 0x00 "RDMCHID_3_11,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB0B0++0x03
line.long 0x00 "RDMSEC_3_11,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0xB100++0x03
line.long 0x00 "RDMCHCLR_3_11,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0xB110++0x03
line.long 0x00 "RDMISTA_3_11,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
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hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0xC000++0x03
line.long 0x00 "RDMSAR_3_12,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0xC004++0x03
line.long 0x00 "RDMDAR_3_12,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0xC008++0x03
line.long 0x00 "RDMTCR_3_12,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0xC00C++0x03
line.long 0x00 "RDMCHCR_3_12,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
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bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
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rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
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bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
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bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
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bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
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bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0xC010++0x03
line.long 0x00 "RDMFIXSAR_3_12,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0xC014++0x03
line.long 0x00 "RDMFIXDAR_3_12,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0xC018++0x03
line.long 0x00 "RDMTCRB_3_12,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0xC01C++0x03
line.long 0x00 "RDMCHCRB_3_12,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
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bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
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rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
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rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
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bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0xC028++0x03
line.long 0x00 "RDMTSR_3_12,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0xC038++0x03
line.long 0x00 "RDMTSRB_3_12,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0xC040++0x01
line.word 0x00 "RDMRS_3_12,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0xC048++0x03
line.long 0x00 "RDMBUFCR_3_12,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
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rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0xC050++0x03
line.long 0x00 "RDMDPBASE_3_12,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0xC054++0x03
line.long 0x00 "RDMDPCR_3_12,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC058++0x03
line.long 0x00 "RDMDPEVTCR_3_12,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
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bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xC05C++0x03
line.long 0x00 "RDMDPEVTCNT_3_12,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
newline
hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0xC060++0x03
line.long 0x00 "RDMFIXDPBASE_3_12,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0xC064++0x03
line.long 0x00 "RDMDREQOS_3_12,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0xC078++0x03
line.long 0x00 "RDMREGIONID_3_12,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC080++0x03
line.long 0x00 "RDMCHID_3_12,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC0B0++0x03
line.long 0x00 "RDMSEC_3_12,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0xC100++0x03
line.long 0x00 "RDMCHCLR_3_12,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0xC110++0x03
line.long 0x00 "RDMISTA_3_12,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
newline
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0xD000++0x03
line.long 0x00 "RDMSAR_3_13,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0xD004++0x03
line.long 0x00 "RDMDAR_3_13,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0xD008++0x03
line.long 0x00 "RDMTCR_3_13,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0xD00C++0x03
line.long 0x00 "RDMCHCR_3_13,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
newline
bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
newline
rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
newline
bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
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bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
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bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
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bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0xD010++0x03
line.long 0x00 "RDMFIXSAR_3_13,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0xD014++0x03
line.long 0x00 "RDMFIXDAR_3_13,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0xD018++0x03
line.long 0x00 "RDMTCRB_3_13,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0xD01C++0x03
line.long 0x00 "RDMCHCRB_3_13,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
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bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
newline
rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
newline
rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
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bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0xD028++0x03
line.long 0x00 "RDMTSR_3_13,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0xD038++0x03
line.long 0x00 "RDMTSRB_3_13,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0xD040++0x01
line.word 0x00 "RDMRS_3_13,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0xD048++0x03
line.long 0x00 "RDMBUFCR_3_13,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
newline
rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0xD050++0x03
line.long 0x00 "RDMDPBASE_3_13,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0xD054++0x03
line.long 0x00 "RDMDPCR_3_13,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xD058++0x03
line.long 0x00 "RDMDPEVTCR_3_13,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
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bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xD05C++0x03
line.long 0x00 "RDMDPEVTCNT_3_13,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
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hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0xD060++0x03
line.long 0x00 "RDMFIXDPBASE_3_13,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0xD064++0x03
line.long 0x00 "RDMDREQOS_3_13,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0xD078++0x03
line.long 0x00 "RDMREGIONID_3_13,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xD080++0x03
line.long 0x00 "RDMCHID_3_13,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xD0B0++0x03
line.long 0x00 "RDMSEC_3_13,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0xD100++0x03
line.long 0x00 "RDMCHCLR_3_13,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0xD110++0x03
line.long 0x00 "RDMISTA_3_13,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
newline
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0xE000++0x03
line.long 0x00 "RDMSAR_3_14,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0xE004++0x03
line.long 0x00 "RDMDAR_3_14,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0xE008++0x03
line.long 0x00 "RDMTCR_3_14,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0xE00C++0x03
line.long 0x00 "RDMCHCR_3_14,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
newline
bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
newline
rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
newline
bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
newline
bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
newline
bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
newline
bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0xE010++0x03
line.long 0x00 "RDMFIXSAR_3_14,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0xE014++0x03
line.long 0x00 "RDMFIXDAR_3_14,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0xE018++0x03
line.long 0x00 "RDMTCRB_3_14,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0xE01C++0x03
line.long 0x00 "RDMCHCRB_3_14,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
newline
bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
newline
rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
newline
rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
newline
bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0xE028++0x03
line.long 0x00 "RDMTSR_3_14,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0xE038++0x03
line.long 0x00 "RDMTSRB_3_14,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0xE040++0x01
line.word 0x00 "RDMRS_3_14,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0xE048++0x03
line.long 0x00 "RDMBUFCR_3_14,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
newline
rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0xE050++0x03
line.long 0x00 "RDMDPBASE_3_14,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0xE054++0x03
line.long 0x00 "RDMDPCR_3_14,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xE058++0x03
line.long 0x00 "RDMDPEVTCR_3_14,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
newline
bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xE05C++0x03
line.long 0x00 "RDMDPEVTCNT_3_14,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
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hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0xE060++0x03
line.long 0x00 "RDMFIXDPBASE_3_14,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0xE064++0x03
line.long 0x00 "RDMDREQOS_3_14,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0xE078++0x03
line.long 0x00 "RDMREGIONID_3_14,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xE080++0x03
line.long 0x00 "RDMCHID_3_14,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xE0B0++0x03
line.long 0x00 "RDMSEC_3_14,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0xE100++0x03
line.long 0x00 "RDMCHCLR_3_14,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0xE110++0x03
line.long 0x00 "RDMISTA_3_14,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
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hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0xF000++0x03
line.long 0x00 "RDMSAR_3_15,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0xF004++0x03
line.long 0x00 "RDMDAR_3_15,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0xF008++0x03
line.long 0x00 "RDMTCR_3_15,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0xF00C++0x03
line.long 0x00 "RDMCHCR_3_15,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
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bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
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rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
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bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
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bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
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bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
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bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0xF010++0x03
line.long 0x00 "RDMFIXSAR_3_15,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0xF014++0x03
line.long 0x00 "RDMFIXDAR_3_15,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0xF018++0x03
line.long 0x00 "RDMTCRB_3_15,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0xF01C++0x03
line.long 0x00 "RDMCHCRB_3_15,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
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bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
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rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
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rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
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bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0xF028++0x03
line.long 0x00 "RDMTSR_3_15,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0xF038++0x03
line.long 0x00 "RDMTSRB_3_15,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0xF040++0x01
line.word 0x00 "RDMRS_3_15,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0xF048++0x03
line.long 0x00 "RDMBUFCR_3_15,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
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rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0xF050++0x03
line.long 0x00 "RDMDPBASE_3_15,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0xF054++0x03
line.long 0x00 "RDMDPCR_3_15,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xF058++0x03
line.long 0x00 "RDMDPEVTCR_3_15,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
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bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
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bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xF05C++0x03
line.long 0x00 "RDMDPEVTCNT_3_15,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
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hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0xF060++0x03
line.long 0x00 "RDMFIXDPBASE_3_15,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0xF064++0x03
line.long 0x00 "RDMDREQOS_3_15,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0xF078++0x03
line.long 0x00 "RDMREGIONID_3_15,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xF080++0x03
line.long 0x00 "RDMCHID_3_15,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xF0B0++0x03
line.long 0x00 "RDMSEC_3_15,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0xF100++0x03
line.long 0x00 "RDMCHCLR_3_15,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0xF110++0x03
line.long 0x00 "RDMISTA_3_15,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
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hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
tree.end
tree "DMAC_INST_8"
base ad:0xE7350000
group.word 0x60++0x01
line.word 0x00 "SDMOR_1,DMOR is a 16-bit readable/writable register which control master enable and specifies the priority level of all DMA channels"
rbitfld.word 0x00 10.--15. "Reserved_10,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.word 0x00 8.--9. "PR_1_0,Priority Mode Select the priority level between channels when there are transfer requests for multiple channels simultaneously" "0: CH0 > CH1 > CH2 > & > CH15,?,?,3: Round-robin mode Other than above"
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rbitfld.word 0x00 3.--7. "Reserved_3,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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rbitfld.word 0x00 2. "AE,Address Error Flag Indicates that an address error interrupt occurred during DMA transfer" "0: No SYS-DMAC address error interrupt [Clearing,1: SYS-DMAC address error interrupt occurs during"
newline
rbitfld.word 0x00 1. "Reserved_1,Reserved This bit is always read as 0" "0,1"
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bitfld.word 0x00 0. "DME,DMA Master Enable Enables or disables DMA transfers on all channels" "0: Disables DMA transfers on all channels,1: Enables DMA transfers on all channels"
group.long 0xA0++0x03
line.long 0x00 "SDMDPSEC_1,DPSEC is a 32-bit readable/writeable register that controls the secure attribute of Descriptor Memory"
bitfld.long 0x00 31. "DPSEC,Secure attribute setting of Descriptor memory Specify the secure attribute of address spaces of Descriptor memory" "0: nonsecure attribute,1: secure attribute"
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rbitfld.long 0x00 25.--30. "Reserved_25,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.word 0x00 16.--24. 1. "DPSECA_8_0,Secure attribute base address of Descriptor memory Specify the secure attribute base address of Descriptor memory"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
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hexmask.long.word 0x00 0.--8. 1. "DPSECM_8_0,Secure attribute base address mask of Descriptor memory Specify the secure attribute base address mask of Descriptor memory"
group.long 0xA4++0x03
line.long 0x00 "SDMBUFMODE_1,BUFMODE is a 32-bit readable/writeable register that controls the partial outstanding function mode"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
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bitfld.long 0x00 0. "BUFMODE,Partial OS enable" "0: Normal OS Ch0-15 256Bx2outst,1: Partial OS Ch0-3 256Bx4outst CH4-7 256Bx2outst"
group.long 0xC0++0x03
line.long 0x00 "SDMERRDET_1,"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
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bitfld.long 0x00 0. "ERROR_DETECT,Secure Error" "0: No Error,1: Secure Error write 1"
group.long 0xC4++0x03
line.long 0x00 "SDMERRADR_1,"
hexmask.long 0x00 0.--31. 1. "ERROR_ADDR_31_0,Secure Error APB address clear by write 1 to ERROR_DETECT_OUT"
group.long 0xC8++0x03
line.long 0x00 "SDMERRPID_1,"
hexmask.long 0x00 0.--31. 1. "ERROR_PID_31_0,Secure error APB ID clear by write 1 to ERROR_DETECT_OUT"
group.long 0xCC++0x03
line.long 0x00 "SDMADRFB_1,ADRFB is 32-bit readable/writable register that specify the control of address feedback of DPRAM"
bitfld.long 0x00 31. "ADDRFB_EN,Address Feedback Enable" "0: Disable and,1: Enable"
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rbitfld.long 0x00 25.--30. "Reserved_25,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.word 0x00 16.--24. 1. "REF_A_8_0,Reference address when comparing"
newline
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 1. "P_ADDRFB_ERR_POST,Address Feedback Post-Fault injection" "0: No fault injection,1: Fault injection"
newline
bitfld.long 0x00 0. "P_ADDRFB_ERR_PRE,Address Feedback Pre-Fault injection" "0: No fault injection,1: Fault injection"
group.long 0xD0++0x03
line.long 0x00 "SDMAPBEDC_1,APBEDC is 32-bit readable/writable register that specify the control APBEDC injection and EDC error status"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 19. "PWDATA_PUBLIC_ERR,PUBLIC PWDATA EDC error status" "0: normal,1: Error"
newline
rbitfld.long 0x00 18. "PADDR_PUBLIC_ERR,PUBLIC PADDR EDC error status" "0: normal,1: Error"
newline
rbitfld.long 0x00 17. "PWDATA_CH_ERR,CH PWDATA EDC error status" "0: normal,1: Error"
newline
rbitfld.long 0x00 16. "PADDR_CH_ERR,CH PWDATA EDC error status" "0: normal,1: Error"
newline
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 1. "P_APBPUBLIC_ERR,PUBLIC APB I/F Fault injection" "0: No fault injection Read always be 0,1: Fault injection"
newline
bitfld.long 0x00 0. "P_APBCH_ERR,CH APB I/F Fault injection" "0: No fault injection Read always be 0,1: Fault injection"
group.long 0xD4++0x03
line.long 0x00 "SDMAPB_CH_PADDR_1,APB_CH_PADDR is 32-bit readable register that specify the EDC error information"
hexmask.long 0x00 0.--31. 1. "PADDR_31_0,CH EDC error PADDR information"
group.long 0xD8++0x03
line.long 0x00 "SDMAPB_CH_PWDATA_1,APB_CH_PWDATA is 32-bit readable register that specify the EDC error information"
hexmask.long 0x00 0.--31. 1. "PWDATA_31_0,CH EDC error PADDR information"
group.long 0xDC++0x03
line.long 0x00 "SDMAPB_PUBLIC_PADDR_1,APB_PUBLIC_PADDR is 32-bit readable register that specify the EDC error information"
hexmask.long 0x00 0.--31. 1. "PADDR_31_0,PUBLIC EDC error PADDR information"
group.long 0xE0++0x03
line.long 0x00 "SDMAPB_PUBLIC_PWDATA_1,APB_PUBLIC_PWDATA is 32-bit readable register that specify the EDC error information"
hexmask.long 0x00 0.--31. 1. "PWDATA_31_0,PUBLIC EDC error PADDR information"
group.long 0xF0++0x03
line.long 0x00 "SDMDMCMP_STAUS_1,DMCMP_STATUS is 32-bit readable/writable register that specify the control of DCLS comparison and error status"
bitfld.long 0x00 31. "EN,DCLS compare enable" "0: Disable and Clear error,1: Enable and detect"
newline
bitfld.long 0x00 30. "P_ERR_POST,Post-Fault Injection" "0: Disable Fault injection,1: Fault Injection (Pseudo error)"
newline
hexmask.long.word 0x00 17.--29. 1. "Reserved_17,Reserved"
newline
bitfld.long 0x00 16. "P_ERR_PRE,Pre-Fault Injection" "0: Disable Fault injection,1: Fault Injection (Pseudo error)"
newline
hexmask.long.word 0x00 5.--15. 1. "Reserved_5,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 4. "E_PERI,Error status on PERI AXI I/F" "0,1"
newline
rbitfld.long 0x00 3. "E_MEM,Error status on MEM AXI I/F" "0,1"
newline
rbitfld.long 0x00 2. "E_BUS,Error status on BUS AXI I/F" "0,1"
newline
rbitfld.long 0x00 1. "E_APB,Error status on APB I/F" "0,1"
newline
rbitfld.long 0x00 0. "E_OTH,Error status on other signals" "0,1"
group.long 0xF4++0x03
line.long 0x00 "SDMRATE_RD_1,RRATE_RD is 32-bit readable/writable register that specify the control of rate control of BUS I/F"
bitfld.long 0x00 31. "RATE_RD_ACCESS_CNT_EN,Rate Control for read Enable" "0: Disable,1: Enable"
newline
hexmask.long.tbyte 0x00 8.--30. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "RATE_RD_ACCESS_CNT,Rate Control counter setting for read transaction Period of time of a transaction =(CNT + 1) * 2 + 3 (clock cycle) 0-2"
group.long 0xF8++0x03
line.long 0x00 "SDMRATE_WR_1,RRATE_WR is 32-bit readable/writable register that specify the control of rate control of BUS I/F"
bitfld.long 0x00 31. "RATE_WR_ACCESS_CNT_EN,Rate Control for write Enable" "0: Disable,1: Enable"
newline
hexmask.long.tbyte 0x00 8.--30. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "RATE_WR_ACCESS_CNT,Rate Control counter setting for write transaction Period of time of a transaction =(CNT + 1) * 2 + 3 (clock cycle) 0-2"
tree.end
tree "DMAC_INST_9"
base ad:0xE7351000
group.word 0x60++0x01
line.word 0x00 "SDMOR_2,DMOR is a 16-bit readable/writable register which control master enable and specifies the priority level of all DMA channels"
rbitfld.word 0x00 10.--15. "Reserved_10,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.word 0x00 8.--9. "PR_1_0,Priority Mode Select the priority level between channels when there are transfer requests for multiple channels simultaneously" "0: CH0 > CH1 > CH2 > & > CH15,?,?,3: Round-robin mode Other than above"
newline
rbitfld.word 0x00 3.--7. "Reserved_3,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.word 0x00 2. "AE,Address Error Flag Indicates that an address error interrupt occurred during DMA transfer" "0: No SYS-DMAC address error interrupt [Clearing,1: SYS-DMAC address error interrupt occurs during"
newline
rbitfld.word 0x00 1. "Reserved_1,Reserved This bit is always read as 0" "0,1"
newline
bitfld.word 0x00 0. "DME,DMA Master Enable Enables or disables DMA transfers on all channels" "0: Disables DMA transfers on all channels,1: Enables DMA transfers on all channels"
group.long 0xA0++0x03
line.long 0x00 "SDMDPSEC_2,DPSEC is a 32-bit readable/writeable register that controls the secure attribute of Descriptor Memory"
bitfld.long 0x00 31. "DPSEC,Secure attribute setting of Descriptor memory Specify the secure attribute of address spaces of Descriptor memory" "0: nonsecure attribute,1: secure attribute"
newline
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.long.word 0x00 16.--24. 1. "DPSECA_8_0,Secure attribute base address of Descriptor memory Specify the secure attribute base address of Descriptor memory"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--8. 1. "DPSECM_8_0,Secure attribute base address mask of Descriptor memory Specify the secure attribute base address mask of Descriptor memory"
group.long 0xA4++0x03
line.long 0x00 "SDMBUFMODE_2,BUFMODE is a 32-bit readable/writeable register that controls the partial outstanding function mode"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 0. "BUFMODE,Partial OS enable" "0: Normal OS Ch0-15 256Bx2outst,1: Partial OS Ch0-3 256Bx4outst CH4-7 256Bx2outst"
group.long 0xC0++0x03
line.long 0x00 "SDMERRDET_2,"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 0. "ERROR_DETECT,Secure Error" "0: No Error,1: Secure Error write 1"
group.long 0xC4++0x03
line.long 0x00 "SDMERRADR_2,"
hexmask.long 0x00 0.--31. 1. "ERROR_ADDR_31_0,Secure Error APB address clear by write 1 to ERROR_DETECT_OUT"
group.long 0xC8++0x03
line.long 0x00 "SDMERRPID_2,"
hexmask.long 0x00 0.--31. 1. "ERROR_PID_31_0,Secure error APB ID clear by write 1 to ERROR_DETECT_OUT"
group.long 0xCC++0x03
line.long 0x00 "SDMADRFB_2,ADRFB is 32-bit readable/writable register that specify the control of address feedback of DPRAM"
bitfld.long 0x00 31. "ADDRFB_EN,Address Feedback Enable" "0: Disable and,1: Enable"
newline
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.long.word 0x00 16.--24. 1. "REF_A_8_0,Reference address when comparing"
newline
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 1. "P_ADDRFB_ERR_POST,Address Feedback Post-Fault injection" "0: No fault injection,1: Fault injection"
newline
bitfld.long 0x00 0. "P_ADDRFB_ERR_PRE,Address Feedback Pre-Fault injection" "0: No fault injection,1: Fault injection"
group.long 0xD0++0x03
line.long 0x00 "SDMAPBEDC_2,APBEDC is 32-bit readable/writable register that specify the control APBEDC injection and EDC error status"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 19. "PWDATA_PUBLIC_ERR,PUBLIC PWDATA EDC error status" "0: normal,1: Error"
newline
rbitfld.long 0x00 18. "PADDR_PUBLIC_ERR,PUBLIC PADDR EDC error status" "0: normal,1: Error"
newline
rbitfld.long 0x00 17. "PWDATA_CH_ERR,CH PWDATA EDC error status" "0: normal,1: Error"
newline
rbitfld.long 0x00 16. "PADDR_CH_ERR,CH PWDATA EDC error status" "0: normal,1: Error"
newline
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 1. "P_APBPUBLIC_ERR,PUBLIC APB I/F Fault injection" "0: No fault injection Read always be 0,1: Fault injection"
newline
bitfld.long 0x00 0. "P_APBCH_ERR,CH APB I/F Fault injection" "0: No fault injection Read always be 0,1: Fault injection"
group.long 0xD4++0x03
line.long 0x00 "SDMAPB_CH_PADDR_2,APB_CH_PADDR is 32-bit readable register that specify the EDC error information"
hexmask.long 0x00 0.--31. 1. "PADDR_31_0,CH EDC error PADDR information"
group.long 0xD8++0x03
line.long 0x00 "SDMAPB_CH_PWDATA_2,APB_CH_PWDATA is 32-bit readable register that specify the EDC error information"
hexmask.long 0x00 0.--31. 1. "PWDATA_31_0,CH EDC error PADDR information"
group.long 0xDC++0x03
line.long 0x00 "SDMAPB_PUBLIC_PADDR_2,APB_PUBLIC_PADDR is 32-bit readable register that specify the EDC error information"
hexmask.long 0x00 0.--31. 1. "PADDR_31_0,PUBLIC EDC error PADDR information"
group.long 0xE0++0x03
line.long 0x00 "SDMAPB_PUBLIC_PWDATA_2,APB_PUBLIC_PWDATA is 32-bit readable register that specify the EDC error information"
hexmask.long 0x00 0.--31. 1. "PWDATA_31_0,PUBLIC EDC error PADDR information"
group.long 0xF0++0x03
line.long 0x00 "SDMDMCMP_STAUS_2,DMCMP_STATUS is 32-bit readable/writable register that specify the control of DCLS comparison and error status"
bitfld.long 0x00 31. "EN,DCLS compare enable" "0: Disable and Clear error,1: Enable and detect"
newline
bitfld.long 0x00 30. "P_ERR_POST,Post-Fault Injection" "0: Disable Fault injection,1: Fault Injection (Pseudo error)"
newline
hexmask.long.word 0x00 17.--29. 1. "Reserved_17,Reserved"
newline
bitfld.long 0x00 16. "P_ERR_PRE,Pre-Fault Injection" "0: Disable Fault injection,1: Fault Injection (Pseudo error)"
newline
hexmask.long.word 0x00 5.--15. 1. "Reserved_5,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 4. "E_PERI,Error status on PERI AXI I/F" "0,1"
newline
rbitfld.long 0x00 3. "E_MEM,Error status on MEM AXI I/F" "0,1"
newline
rbitfld.long 0x00 2. "E_BUS,Error status on BUS AXI I/F" "0,1"
newline
rbitfld.long 0x00 1. "E_APB,Error status on APB I/F" "0,1"
newline
rbitfld.long 0x00 0. "E_OTH,Error status on other signals" "0,1"
group.long 0xF4++0x03
line.long 0x00 "SDMRATE_RD_2,RRATE_RD is 32-bit readable/writable register that specify the control of rate control of BUS I/F"
bitfld.long 0x00 31. "RATE_RD_ACCESS_CNT_EN,Rate Control for read Enable" "0: Disable,1: Enable"
newline
hexmask.long.tbyte 0x00 8.--30. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "RATE_RD_ACCESS_CNT,Rate Control counter setting for read transaction Period of time of a transaction =(CNT + 1) * 2 + 3 (clock cycle) 0-2"
group.long 0xF8++0x03
line.long 0x00 "SDMRATE_WR_2,RRATE_WR is 32-bit readable/writable register that specify the control of rate control of BUS I/F"
bitfld.long 0x00 31. "RATE_WR_ACCESS_CNT_EN,Rate Control for write Enable" "0: Disable,1: Enable"
newline
hexmask.long.tbyte 0x00 8.--30. 1. "Reserved_8,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "RATE_WR_ACCESS_CNT,Rate Control counter setting for write transaction Period of time of a transaction =(CNT + 1) * 2 + 3 (clock cycle) 0-2"
tree.end
tree "DMAC_INST_10"
base ad:0xE7300000
group.long 0x00++0x03
line.long 0x00 "SDMSAR_1_0,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0x04++0x03
line.long 0x00 "SDMDAR_1_0,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0x08++0x03
line.long 0x00 "SDMTCR_1_0,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0x0C++0x03
line.long 0x00 "SDMCHCR_1_0,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
newline
bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
newline
rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
newline
bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
newline
bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
newline
bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
newline
bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0x10++0x03
line.long 0x00 "SDMFIXSAR_1_0,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0x14++0x03
line.long 0x00 "SDMFIXDAR_1_0,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0x18++0x03
line.long 0x00 "SDMTCRB_1_0,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0x1C++0x03
line.long 0x00 "SDMCHCRB_1_0,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
newline
bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
newline
rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
newline
rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
newline
bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0x28++0x03
line.long 0x00 "SDMTSR_1_0,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0x38++0x03
line.long 0x00 "SDMTSRB_1_0,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0x40++0x01
line.word 0x00 "SDMRS_1_0,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0x48++0x03
line.long 0x00 "SDMBUFCR_1_0,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
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rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0x50++0x03
line.long 0x00 "SDMDPBASE_1_0,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0x54++0x03
line.long 0x00 "SDMDPCR_1_0,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x58++0x03
line.long 0x00 "SDMDPEVTCR_1_0,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
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bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
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bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x5C++0x03
line.long 0x00 "SDMDPEVTCNT_1_0,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
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hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0x60++0x03
line.long 0x00 "SDMFIXDPBASE_1_0,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0x64++0x03
line.long 0x00 "SDMDREQOS_1_0,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0x78++0x03
line.long 0x00 "SDMREGIONID_1_0,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x80++0x03
line.long 0x00 "SDMCHID_1_0,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB0++0x03
line.long 0x00 "SDMSEC_1_0,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0x100++0x03
line.long 0x00 "SDMCHCLR_1_0,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0x110++0x03
line.long 0x00 "SDMISTA_1_0,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
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hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0x1000++0x03
line.long 0x00 "SDMSAR_1_1,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0x1004++0x03
line.long 0x00 "SDMDAR_1_1,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0x1008++0x03
line.long 0x00 "SDMTCR_1_1,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0x100C++0x03
line.long 0x00 "SDMCHCR_1_1,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
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bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
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rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
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bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
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bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
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bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
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bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0x1010++0x03
line.long 0x00 "SDMFIXSAR_1_1,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0x1014++0x03
line.long 0x00 "SDMFIXDAR_1_1,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0x1018++0x03
line.long 0x00 "SDMTCRB_1_1,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0x101C++0x03
line.long 0x00 "SDMCHCRB_1_1,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
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bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
newline
rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
newline
rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
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bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0x1028++0x03
line.long 0x00 "SDMTSR_1_1,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0x1038++0x03
line.long 0x00 "SDMTSRB_1_1,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0x1040++0x01
line.word 0x00 "SDMRS_1_1,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0x1048++0x03
line.long 0x00 "SDMBUFCR_1_1,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
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rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0x1050++0x03
line.long 0x00 "SDMDPBASE_1_1,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0x1054++0x03
line.long 0x00 "SDMDPCR_1_1,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1058++0x03
line.long 0x00 "SDMDPEVTCR_1_1,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
newline
bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x105C++0x03
line.long 0x00 "SDMDPEVTCNT_1_1,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
newline
hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0x1060++0x03
line.long 0x00 "SDMFIXDPBASE_1_1,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0x1064++0x03
line.long 0x00 "SDMDREQOS_1_1,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0x1078++0x03
line.long 0x00 "SDMREGIONID_1_1,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1080++0x03
line.long 0x00 "SDMCHID_1_1,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x10B0++0x03
line.long 0x00 "SDMSEC_1_1,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0x1100++0x03
line.long 0x00 "SDMCHCLR_1_1,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0x1110++0x03
line.long 0x00 "SDMISTA_1_1,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
newline
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0x2000++0x03
line.long 0x00 "SDMSAR_1_2,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0x2004++0x03
line.long 0x00 "SDMDAR_1_2,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0x2008++0x03
line.long 0x00 "SDMTCR_1_2,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0x200C++0x03
line.long 0x00 "SDMCHCR_1_2,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
newline
bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
newline
rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
newline
bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
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bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
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bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
newline
bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0x2010++0x03
line.long 0x00 "SDMFIXSAR_1_2,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0x2014++0x03
line.long 0x00 "SDMFIXDAR_1_2,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0x2018++0x03
line.long 0x00 "SDMTCRB_1_2,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0x201C++0x03
line.long 0x00 "SDMCHCRB_1_2,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
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bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
newline
rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
newline
rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
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bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0x2028++0x03
line.long 0x00 "SDMTSR_1_2,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0x2038++0x03
line.long 0x00 "SDMTSRB_1_2,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0x2040++0x01
line.word 0x00 "SDMRS_1_2,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0x2048++0x03
line.long 0x00 "SDMBUFCR_1_2,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
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rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0x2050++0x03
line.long 0x00 "SDMDPBASE_1_2,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0x2054++0x03
line.long 0x00 "SDMDPCR_1_2,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x2058++0x03
line.long 0x00 "SDMDPEVTCR_1_2,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
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bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x205C++0x03
line.long 0x00 "SDMDPEVTCNT_1_2,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
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hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0x2060++0x03
line.long 0x00 "SDMFIXDPBASE_1_2,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0x2064++0x03
line.long 0x00 "SDMDREQOS_1_2,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0x2078++0x03
line.long 0x00 "SDMREGIONID_1_2,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x2080++0x03
line.long 0x00 "SDMCHID_1_2,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x20B0++0x03
line.long 0x00 "SDMSEC_1_2,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0x2100++0x03
line.long 0x00 "SDMCHCLR_1_2,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0x2110++0x03
line.long 0x00 "SDMISTA_1_2,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
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hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0x3000++0x03
line.long 0x00 "SDMSAR_1_3,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0x3004++0x03
line.long 0x00 "SDMDAR_1_3,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0x3008++0x03
line.long 0x00 "SDMTCR_1_3,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0x300C++0x03
line.long 0x00 "SDMCHCR_1_3,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
newline
bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
newline
rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
newline
bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
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bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
newline
bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
newline
bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0x3010++0x03
line.long 0x00 "SDMFIXSAR_1_3,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0x3014++0x03
line.long 0x00 "SDMFIXDAR_1_3,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0x3018++0x03
line.long 0x00 "SDMTCRB_1_3,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0x301C++0x03
line.long 0x00 "SDMCHCRB_1_3,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
newline
bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
newline
rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
newline
rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
newline
bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0x3028++0x03
line.long 0x00 "SDMTSR_1_3,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0x3038++0x03
line.long 0x00 "SDMTSRB_1_3,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0x3040++0x01
line.word 0x00 "SDMRS_1_3,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0x3048++0x03
line.long 0x00 "SDMBUFCR_1_3,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
newline
rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0x3050++0x03
line.long 0x00 "SDMDPBASE_1_3,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0x3054++0x03
line.long 0x00 "SDMDPCR_1_3,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x3058++0x03
line.long 0x00 "SDMDPEVTCR_1_3,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
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bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
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bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x305C++0x03
line.long 0x00 "SDMDPEVTCNT_1_3,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
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hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0x3060++0x03
line.long 0x00 "SDMFIXDPBASE_1_3,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0x3064++0x03
line.long 0x00 "SDMDREQOS_1_3,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0x3078++0x03
line.long 0x00 "SDMREGIONID_1_3,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x3080++0x03
line.long 0x00 "SDMCHID_1_3,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x30B0++0x03
line.long 0x00 "SDMSEC_1_3,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0x3100++0x03
line.long 0x00 "SDMCHCLR_1_3,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0x3110++0x03
line.long 0x00 "SDMISTA_1_3,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
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hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0x4000++0x03
line.long 0x00 "SDMSAR_1_4,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0x4004++0x03
line.long 0x00 "SDMDAR_1_4,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0x4008++0x03
line.long 0x00 "SDMTCR_1_4,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0x400C++0x03
line.long 0x00 "SDMCHCR_1_4,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
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bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
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rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
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bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
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bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
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bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
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bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0x4010++0x03
line.long 0x00 "SDMFIXSAR_1_4,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0x4014++0x03
line.long 0x00 "SDMFIXDAR_1_4,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0x4018++0x03
line.long 0x00 "SDMTCRB_1_4,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0x401C++0x03
line.long 0x00 "SDMCHCRB_1_4,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
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bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
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rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
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rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
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bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0x4028++0x03
line.long 0x00 "SDMTSR_1_4,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0x4038++0x03
line.long 0x00 "SDMTSRB_1_4,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0x4040++0x01
line.word 0x00 "SDMRS_1_4,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0x4048++0x03
line.long 0x00 "SDMBUFCR_1_4,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
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rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0x4050++0x03
line.long 0x00 "SDMDPBASE_1_4,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0x4054++0x03
line.long 0x00 "SDMDPCR_1_4,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4058++0x03
line.long 0x00 "SDMDPEVTCR_1_4,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
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bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
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bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x405C++0x03
line.long 0x00 "SDMDPEVTCNT_1_4,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
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hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0x4060++0x03
line.long 0x00 "SDMFIXDPBASE_1_4,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0x4064++0x03
line.long 0x00 "SDMDREQOS_1_4,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0x4078++0x03
line.long 0x00 "SDMREGIONID_1_4,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4080++0x03
line.long 0x00 "SDMCHID_1_4,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x40B0++0x03
line.long 0x00 "SDMSEC_1_4,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0x4100++0x03
line.long 0x00 "SDMCHCLR_1_4,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0x4110++0x03
line.long 0x00 "SDMISTA_1_4,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
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hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0x5000++0x03
line.long 0x00 "SDMSAR_1_5,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0x5004++0x03
line.long 0x00 "SDMDAR_1_5,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0x5008++0x03
line.long 0x00 "SDMTCR_1_5,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0x500C++0x03
line.long 0x00 "SDMCHCR_1_5,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
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bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
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rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
newline
bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
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bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
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bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
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bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0x5010++0x03
line.long 0x00 "SDMFIXSAR_1_5,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0x5014++0x03
line.long 0x00 "SDMFIXDAR_1_5,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0x5018++0x03
line.long 0x00 "SDMTCRB_1_5,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0x501C++0x03
line.long 0x00 "SDMCHCRB_1_5,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
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bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
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rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
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rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
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bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0x5028++0x03
line.long 0x00 "SDMTSR_1_5,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0x5038++0x03
line.long 0x00 "SDMTSRB_1_5,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0x5040++0x01
line.word 0x00 "SDMRS_1_5,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0x5048++0x03
line.long 0x00 "SDMBUFCR_1_5,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
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rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0x5050++0x03
line.long 0x00 "SDMDPBASE_1_5,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0x5054++0x03
line.long 0x00 "SDMDPCR_1_5,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x5058++0x03
line.long 0x00 "SDMDPEVTCR_1_5,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
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bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
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bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x505C++0x03
line.long 0x00 "SDMDPEVTCNT_1_5,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
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hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0x5060++0x03
line.long 0x00 "SDMFIXDPBASE_1_5,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0x5064++0x03
line.long 0x00 "SDMDREQOS_1_5,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0x5078++0x03
line.long 0x00 "SDMREGIONID_1_5,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x5080++0x03
line.long 0x00 "SDMCHID_1_5,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x50B0++0x03
line.long 0x00 "SDMSEC_1_5,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0x5100++0x03
line.long 0x00 "SDMCHCLR_1_5,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0x5110++0x03
line.long 0x00 "SDMISTA_1_5,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
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hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0x6000++0x03
line.long 0x00 "SDMSAR_1_6,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0x6004++0x03
line.long 0x00 "SDMDAR_1_6,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0x6008++0x03
line.long 0x00 "SDMTCR_1_6,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0x600C++0x03
line.long 0x00 "SDMCHCR_1_6,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
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bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
newline
rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
newline
bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
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bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
newline
bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
newline
bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0x6010++0x03
line.long 0x00 "SDMFIXSAR_1_6,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0x6014++0x03
line.long 0x00 "SDMFIXDAR_1_6,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0x6018++0x03
line.long 0x00 "SDMTCRB_1_6,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0x601C++0x03
line.long 0x00 "SDMCHCRB_1_6,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
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bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
newline
rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
newline
rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
newline
bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0x6028++0x03
line.long 0x00 "SDMTSR_1_6,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0x6038++0x03
line.long 0x00 "SDMTSRB_1_6,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0x6040++0x01
line.word 0x00 "SDMRS_1_6,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0x6048++0x03
line.long 0x00 "SDMBUFCR_1_6,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
newline
rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0x6050++0x03
line.long 0x00 "SDMDPBASE_1_6,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0x6054++0x03
line.long 0x00 "SDMDPCR_1_6,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x6058++0x03
line.long 0x00 "SDMDPEVTCR_1_6,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
newline
bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x605C++0x03
line.long 0x00 "SDMDPEVTCNT_1_6,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
newline
hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0x6060++0x03
line.long 0x00 "SDMFIXDPBASE_1_6,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0x6064++0x03
line.long 0x00 "SDMDREQOS_1_6,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0x6078++0x03
line.long 0x00 "SDMREGIONID_1_6,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x6080++0x03
line.long 0x00 "SDMCHID_1_6,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x60B0++0x03
line.long 0x00 "SDMSEC_1_6,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0x6100++0x03
line.long 0x00 "SDMCHCLR_1_6,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0x6110++0x03
line.long 0x00 "SDMISTA_1_6,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
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hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0x7000++0x03
line.long 0x00 "SDMSAR_1_7,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0x7004++0x03
line.long 0x00 "SDMDAR_1_7,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0x7008++0x03
line.long 0x00 "SDMTCR_1_7,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0x700C++0x03
line.long 0x00 "SDMCHCR_1_7,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
newline
bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
newline
rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
newline
bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
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bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
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bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
newline
bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0x7010++0x03
line.long 0x00 "SDMFIXSAR_1_7,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0x7014++0x03
line.long 0x00 "SDMFIXDAR_1_7,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0x7018++0x03
line.long 0x00 "SDMTCRB_1_7,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0x701C++0x03
line.long 0x00 "SDMCHCRB_1_7,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
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bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
newline
rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
newline
rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
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bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0x7028++0x03
line.long 0x00 "SDMTSR_1_7,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0x7038++0x03
line.long 0x00 "SDMTSRB_1_7,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0x7040++0x01
line.word 0x00 "SDMRS_1_7,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0x7048++0x03
line.long 0x00 "SDMBUFCR_1_7,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
newline
rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0x7050++0x03
line.long 0x00 "SDMDPBASE_1_7,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0x7054++0x03
line.long 0x00 "SDMDPCR_1_7,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x7058++0x03
line.long 0x00 "SDMDPEVTCR_1_7,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
newline
bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x705C++0x03
line.long 0x00 "SDMDPEVTCNT_1_7,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
newline
hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0x7060++0x03
line.long 0x00 "SDMFIXDPBASE_1_7,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0x7064++0x03
line.long 0x00 "SDMDREQOS_1_7,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0x7078++0x03
line.long 0x00 "SDMREGIONID_1_7,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x7080++0x03
line.long 0x00 "SDMCHID_1_7,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x70B0++0x03
line.long 0x00 "SDMSEC_1_7,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0x7100++0x03
line.long 0x00 "SDMCHCLR_1_7,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0x7110++0x03
line.long 0x00 "SDMISTA_1_7,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
newline
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0x8000++0x03
line.long 0x00 "SDMSAR_1_8,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0x8004++0x03
line.long 0x00 "SDMDAR_1_8,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0x8008++0x03
line.long 0x00 "SDMTCR_1_8,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0x800C++0x03
line.long 0x00 "SDMCHCR_1_8,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
newline
bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
newline
rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
newline
bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
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bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
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bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
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bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0x8010++0x03
line.long 0x00 "SDMFIXSAR_1_8,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0x8014++0x03
line.long 0x00 "SDMFIXDAR_1_8,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0x8018++0x03
line.long 0x00 "SDMTCRB_1_8,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0x801C++0x03
line.long 0x00 "SDMCHCRB_1_8,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
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bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
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rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
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rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
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bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0x8028++0x03
line.long 0x00 "SDMTSR_1_8,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0x8038++0x03
line.long 0x00 "SDMTSRB_1_8,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0x8040++0x01
line.word 0x00 "SDMRS_1_8,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0x8048++0x03
line.long 0x00 "SDMBUFCR_1_8,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
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rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0x8050++0x03
line.long 0x00 "SDMDPBASE_1_8,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0x8054++0x03
line.long 0x00 "SDMDPCR_1_8,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8058++0x03
line.long 0x00 "SDMDPEVTCR_1_8,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
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bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
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bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x805C++0x03
line.long 0x00 "SDMDPEVTCNT_1_8,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
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hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0x8060++0x03
line.long 0x00 "SDMFIXDPBASE_1_8,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0x8064++0x03
line.long 0x00 "SDMDREQOS_1_8,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0x8078++0x03
line.long 0x00 "SDMREGIONID_1_8,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8080++0x03
line.long 0x00 "SDMCHID_1_8,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x80B0++0x03
line.long 0x00 "SDMSEC_1_8,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0x8100++0x03
line.long 0x00 "SDMCHCLR_1_8,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0x8110++0x03
line.long 0x00 "SDMISTA_1_8,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
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hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0x9000++0x03
line.long 0x00 "SDMSAR_1_9,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0x9004++0x03
line.long 0x00 "SDMDAR_1_9,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0x9008++0x03
line.long 0x00 "SDMTCR_1_9,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0x900C++0x03
line.long 0x00 "SDMCHCR_1_9,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
newline
bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
newline
rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
newline
bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
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bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
newline
bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
newline
bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0x9010++0x03
line.long 0x00 "SDMFIXSAR_1_9,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0x9014++0x03
line.long 0x00 "SDMFIXDAR_1_9,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0x9018++0x03
line.long 0x00 "SDMTCRB_1_9,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0x901C++0x03
line.long 0x00 "SDMCHCRB_1_9,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
newline
bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
newline
rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
newline
rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
newline
bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0x9028++0x03
line.long 0x00 "SDMTSR_1_9,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0x9038++0x03
line.long 0x00 "SDMTSRB_1_9,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0x9040++0x01
line.word 0x00 "SDMRS_1_9,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0x9048++0x03
line.long 0x00 "SDMBUFCR_1_9,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
newline
rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0x9050++0x03
line.long 0x00 "SDMDPBASE_1_9,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0x9054++0x03
line.long 0x00 "SDMDPCR_1_9,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x9058++0x03
line.long 0x00 "SDMDPEVTCR_1_9,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
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bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
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bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x905C++0x03
line.long 0x00 "SDMDPEVTCNT_1_9,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
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hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0x9060++0x03
line.long 0x00 "SDMFIXDPBASE_1_9,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0x9064++0x03
line.long 0x00 "SDMDREQOS_1_9,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0x9078++0x03
line.long 0x00 "SDMREGIONID_1_9,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x9080++0x03
line.long 0x00 "SDMCHID_1_9,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x90B0++0x03
line.long 0x00 "SDMSEC_1_9,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0x9100++0x03
line.long 0x00 "SDMCHCLR_1_9,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0x9110++0x03
line.long 0x00 "SDMISTA_1_9,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
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hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0xA000++0x03
line.long 0x00 "SDMSAR_1_10,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0xA004++0x03
line.long 0x00 "SDMDAR_1_10,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0xA008++0x03
line.long 0x00 "SDMTCR_1_10,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0xA00C++0x03
line.long 0x00 "SDMCHCR_1_10,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
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bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
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rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
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bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
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bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
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bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
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bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0xA010++0x03
line.long 0x00 "SDMFIXSAR_1_10,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0xA014++0x03
line.long 0x00 "SDMFIXDAR_1_10,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0xA018++0x03
line.long 0x00 "SDMTCRB_1_10,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0xA01C++0x03
line.long 0x00 "SDMCHCRB_1_10,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
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bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
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rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
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rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
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bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0xA028++0x03
line.long 0x00 "SDMTSR_1_10,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0xA038++0x03
line.long 0x00 "SDMTSRB_1_10,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0xA040++0x01
line.word 0x00 "SDMRS_1_10,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0xA048++0x03
line.long 0x00 "SDMBUFCR_1_10,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
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rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0xA050++0x03
line.long 0x00 "SDMDPBASE_1_10,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0xA054++0x03
line.long 0x00 "SDMDPCR_1_10,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA058++0x03
line.long 0x00 "SDMDPEVTCR_1_10,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
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bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
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bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xA05C++0x03
line.long 0x00 "SDMDPEVTCNT_1_10,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
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hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0xA060++0x03
line.long 0x00 "SDMFIXDPBASE_1_10,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0xA064++0x03
line.long 0x00 "SDMDREQOS_1_10,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0xA078++0x03
line.long 0x00 "SDMREGIONID_1_10,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA080++0x03
line.long 0x00 "SDMCHID_1_10,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA0B0++0x03
line.long 0x00 "SDMSEC_1_10,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0xA100++0x03
line.long 0x00 "SDMCHCLR_1_10,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0xA110++0x03
line.long 0x00 "SDMISTA_1_10,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
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hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0xB000++0x03
line.long 0x00 "SDMSAR_1_11,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0xB004++0x03
line.long 0x00 "SDMDAR_1_11,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0xB008++0x03
line.long 0x00 "SDMTCR_1_11,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0xB00C++0x03
line.long 0x00 "SDMCHCR_1_11,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
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bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
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rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
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bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
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bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
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bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
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bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0xB010++0x03
line.long 0x00 "SDMFIXSAR_1_11,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0xB014++0x03
line.long 0x00 "SDMFIXDAR_1_11,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0xB018++0x03
line.long 0x00 "SDMTCRB_1_11,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0xB01C++0x03
line.long 0x00 "SDMCHCRB_1_11,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
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bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
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rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
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rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
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bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0xB028++0x03
line.long 0x00 "SDMTSR_1_11,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0xB038++0x03
line.long 0x00 "SDMTSRB_1_11,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0xB040++0x01
line.word 0x00 "SDMRS_1_11,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0xB048++0x03
line.long 0x00 "SDMBUFCR_1_11,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
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rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0xB050++0x03
line.long 0x00 "SDMDPBASE_1_11,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0xB054++0x03
line.long 0x00 "SDMDPCR_1_11,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB058++0x03
line.long 0x00 "SDMDPEVTCR_1_11,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
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bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
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bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xB05C++0x03
line.long 0x00 "SDMDPEVTCNT_1_11,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
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hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0xB060++0x03
line.long 0x00 "SDMFIXDPBASE_1_11,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0xB064++0x03
line.long 0x00 "SDMDREQOS_1_11,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0xB078++0x03
line.long 0x00 "SDMREGIONID_1_11,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB080++0x03
line.long 0x00 "SDMCHID_1_11,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB0B0++0x03
line.long 0x00 "SDMSEC_1_11,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0xB100++0x03
line.long 0x00 "SDMCHCLR_1_11,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0xB110++0x03
line.long 0x00 "SDMISTA_1_11,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
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hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0xC000++0x03
line.long 0x00 "SDMSAR_1_12,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0xC004++0x03
line.long 0x00 "SDMDAR_1_12,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0xC008++0x03
line.long 0x00 "SDMTCR_1_12,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0xC00C++0x03
line.long 0x00 "SDMCHCR_1_12,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
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bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
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rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
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bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
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bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
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bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
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bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0xC010++0x03
line.long 0x00 "SDMFIXSAR_1_12,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0xC014++0x03
line.long 0x00 "SDMFIXDAR_1_12,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0xC018++0x03
line.long 0x00 "SDMTCRB_1_12,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0xC01C++0x03
line.long 0x00 "SDMCHCRB_1_12,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
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bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
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rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
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rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
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bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0xC028++0x03
line.long 0x00 "SDMTSR_1_12,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0xC038++0x03
line.long 0x00 "SDMTSRB_1_12,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0xC040++0x01
line.word 0x00 "SDMRS_1_12,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0xC048++0x03
line.long 0x00 "SDMBUFCR_1_12,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
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rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0xC050++0x03
line.long 0x00 "SDMDPBASE_1_12,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0xC054++0x03
line.long 0x00 "SDMDPCR_1_12,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC058++0x03
line.long 0x00 "SDMDPEVTCR_1_12,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
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bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
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bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xC05C++0x03
line.long 0x00 "SDMDPEVTCNT_1_12,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
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hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0xC060++0x03
line.long 0x00 "SDMFIXDPBASE_1_12,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0xC064++0x03
line.long 0x00 "SDMDREQOS_1_12,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0xC078++0x03
line.long 0x00 "SDMREGIONID_1_12,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC080++0x03
line.long 0x00 "SDMCHID_1_12,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC0B0++0x03
line.long 0x00 "SDMSEC_1_12,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0xC100++0x03
line.long 0x00 "SDMCHCLR_1_12,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0xC110++0x03
line.long 0x00 "SDMISTA_1_12,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
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hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0xD000++0x03
line.long 0x00 "SDMSAR_1_13,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0xD004++0x03
line.long 0x00 "SDMDAR_1_13,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0xD008++0x03
line.long 0x00 "SDMTCR_1_13,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0xD00C++0x03
line.long 0x00 "SDMCHCR_1_13,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
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bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
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rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
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bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
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bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
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bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
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bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0xD010++0x03
line.long 0x00 "SDMFIXSAR_1_13,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0xD014++0x03
line.long 0x00 "SDMFIXDAR_1_13,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0xD018++0x03
line.long 0x00 "SDMTCRB_1_13,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0xD01C++0x03
line.long 0x00 "SDMCHCRB_1_13,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
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bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
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rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
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rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
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bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0xD028++0x03
line.long 0x00 "SDMTSR_1_13,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0xD038++0x03
line.long 0x00 "SDMTSRB_1_13,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0xD040++0x01
line.word 0x00 "SDMRS_1_13,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0xD048++0x03
line.long 0x00 "SDMBUFCR_1_13,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
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rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0xD050++0x03
line.long 0x00 "SDMDPBASE_1_13,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0xD054++0x03
line.long 0x00 "SDMDPCR_1_13,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xD058++0x03
line.long 0x00 "SDMDPEVTCR_1_13,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
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bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
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bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xD05C++0x03
line.long 0x00 "SDMDPEVTCNT_1_13,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
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hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0xD060++0x03
line.long 0x00 "SDMFIXDPBASE_1_13,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0xD064++0x03
line.long 0x00 "SDMDREQOS_1_13,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0xD078++0x03
line.long 0x00 "SDMREGIONID_1_13,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xD080++0x03
line.long 0x00 "SDMCHID_1_13,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xD0B0++0x03
line.long 0x00 "SDMSEC_1_13,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0xD100++0x03
line.long 0x00 "SDMCHCLR_1_13,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0xD110++0x03
line.long 0x00 "SDMISTA_1_13,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
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hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0xE000++0x03
line.long 0x00 "SDMSAR_1_14,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0xE004++0x03
line.long 0x00 "SDMDAR_1_14,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0xE008++0x03
line.long 0x00 "SDMTCR_1_14,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0xE00C++0x03
line.long 0x00 "SDMCHCR_1_14,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
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bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
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rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
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bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
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bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
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bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
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bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0xE010++0x03
line.long 0x00 "SDMFIXSAR_1_14,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0xE014++0x03
line.long 0x00 "SDMFIXDAR_1_14,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0xE018++0x03
line.long 0x00 "SDMTCRB_1_14,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0xE01C++0x03
line.long 0x00 "SDMCHCRB_1_14,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
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bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
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rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
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rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
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bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0xE028++0x03
line.long 0x00 "SDMTSR_1_14,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0xE038++0x03
line.long 0x00 "SDMTSRB_1_14,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0xE040++0x01
line.word 0x00 "SDMRS_1_14,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0xE048++0x03
line.long 0x00 "SDMBUFCR_1_14,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
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rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0xE050++0x03
line.long 0x00 "SDMDPBASE_1_14,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0xE054++0x03
line.long 0x00 "SDMDPCR_1_14,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xE058++0x03
line.long 0x00 "SDMDPEVTCR_1_14,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
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bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
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bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xE05C++0x03
line.long 0x00 "SDMDPEVTCNT_1_14,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
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hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0xE060++0x03
line.long 0x00 "SDMFIXDPBASE_1_14,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0xE064++0x03
line.long 0x00 "SDMDREQOS_1_14,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0xE078++0x03
line.long 0x00 "SDMREGIONID_1_14,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xE080++0x03
line.long 0x00 "SDMCHID_1_14,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xE0B0++0x03
line.long 0x00 "SDMSEC_1_14,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0xE100++0x03
line.long 0x00 "SDMCHCLR_1_14,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0xE110++0x03
line.long 0x00 "SDMISTA_1_14,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
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hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0xF000++0x03
line.long 0x00 "SDMSAR_1_15,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0xF004++0x03
line.long 0x00 "SDMDAR_1_15,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0xF008++0x03
line.long 0x00 "SDMTCR_1_15,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0xF00C++0x03
line.long 0x00 "SDMCHCR_1_15,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
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bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
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rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
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bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
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bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
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bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
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bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0xF010++0x03
line.long 0x00 "SDMFIXSAR_1_15,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0xF014++0x03
line.long 0x00 "SDMFIXDAR_1_15,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0xF018++0x03
line.long 0x00 "SDMTCRB_1_15,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0xF01C++0x03
line.long 0x00 "SDMCHCRB_1_15,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
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bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
newline
rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
newline
rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
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bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0xF028++0x03
line.long 0x00 "SDMTSR_1_15,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0xF038++0x03
line.long 0x00 "SDMTSRB_1_15,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0xF040++0x01
line.word 0x00 "SDMRS_1_15,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0xF048++0x03
line.long 0x00 "SDMBUFCR_1_15,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
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rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0xF050++0x03
line.long 0x00 "SDMDPBASE_1_15,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0xF054++0x03
line.long 0x00 "SDMDPCR_1_15,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xF058++0x03
line.long 0x00 "SDMDPEVTCR_1_15,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
newline
bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xF05C++0x03
line.long 0x00 "SDMDPEVTCNT_1_15,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
newline
hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0xF060++0x03
line.long 0x00 "SDMFIXDPBASE_1_15,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0xF064++0x03
line.long 0x00 "SDMDREQOS_1_15,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0xF078++0x03
line.long 0x00 "SDMREGIONID_1_15,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xF080++0x03
line.long 0x00 "SDMCHID_1_15,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xF0B0++0x03
line.long 0x00 "SDMSEC_1_15,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0xF100++0x03
line.long 0x00 "SDMCHCLR_1_15,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0xF110++0x03
line.long 0x00 "SDMISTA_1_15,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
newline
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
tree.end
tree "DMAC_INST_11"
base ad:0xE7310000
group.long 0x00++0x03
line.long 0x00 "SDMSAR_2_0,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0x04++0x03
line.long 0x00 "SDMDAR_2_0,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0x08++0x03
line.long 0x00 "SDMTCR_2_0,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0x0C++0x03
line.long 0x00 "SDMCHCR_2_0,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
newline
bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
newline
rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
newline
bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
newline
bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
newline
bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
newline
bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0x10++0x03
line.long 0x00 "SDMFIXSAR_2_0,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0x14++0x03
line.long 0x00 "SDMFIXDAR_2_0,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0x18++0x03
line.long 0x00 "SDMTCRB_2_0,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0x1C++0x03
line.long 0x00 "SDMCHCRB_2_0,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
newline
bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
newline
rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
newline
rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
newline
bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0x28++0x03
line.long 0x00 "SDMTSR_2_0,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0x38++0x03
line.long 0x00 "SDMTSRB_2_0,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0x40++0x01
line.word 0x00 "SDMRS_2_0,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0x48++0x03
line.long 0x00 "SDMBUFCR_2_0,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
newline
rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0x50++0x03
line.long 0x00 "SDMDPBASE_2_0,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0x54++0x03
line.long 0x00 "SDMDPCR_2_0,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x58++0x03
line.long 0x00 "SDMDPEVTCR_2_0,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
newline
bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x5C++0x03
line.long 0x00 "SDMDPEVTCNT_2_0,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
newline
hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0x60++0x03
line.long 0x00 "SDMFIXDPBASE_2_0,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0x64++0x03
line.long 0x00 "SDMDREQOS_2_0,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0x78++0x03
line.long 0x00 "SDMREGIONID_2_0,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x80++0x03
line.long 0x00 "SDMCHID_2_0,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB0++0x03
line.long 0x00 "SDMSEC_2_0,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0x100++0x03
line.long 0x00 "SDMCHCLR_2_0,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0x110++0x03
line.long 0x00 "SDMISTA_2_0,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
newline
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0x1000++0x03
line.long 0x00 "SDMSAR_2_1,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0x1004++0x03
line.long 0x00 "SDMDAR_2_1,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0x1008++0x03
line.long 0x00 "SDMTCR_2_1,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0x100C++0x03
line.long 0x00 "SDMCHCR_2_1,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
newline
bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
newline
rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
newline
bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
newline
bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
newline
bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
newline
bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0x1010++0x03
line.long 0x00 "SDMFIXSAR_2_1,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0x1014++0x03
line.long 0x00 "SDMFIXDAR_2_1,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0x1018++0x03
line.long 0x00 "SDMTCRB_2_1,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0x101C++0x03
line.long 0x00 "SDMCHCRB_2_1,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
newline
bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
newline
rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
newline
rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
newline
bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0x1028++0x03
line.long 0x00 "SDMTSR_2_1,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0x1038++0x03
line.long 0x00 "SDMTSRB_2_1,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0x1040++0x01
line.word 0x00 "SDMRS_2_1,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0x1048++0x03
line.long 0x00 "SDMBUFCR_2_1,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
newline
rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0x1050++0x03
line.long 0x00 "SDMDPBASE_2_1,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0x1054++0x03
line.long 0x00 "SDMDPCR_2_1,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1058++0x03
line.long 0x00 "SDMDPEVTCR_2_1,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
newline
bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x105C++0x03
line.long 0x00 "SDMDPEVTCNT_2_1,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
newline
hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0x1060++0x03
line.long 0x00 "SDMFIXDPBASE_2_1,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0x1064++0x03
line.long 0x00 "SDMDREQOS_2_1,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0x1078++0x03
line.long 0x00 "SDMREGIONID_2_1,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1080++0x03
line.long 0x00 "SDMCHID_2_1,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x10B0++0x03
line.long 0x00 "SDMSEC_2_1,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0x1100++0x03
line.long 0x00 "SDMCHCLR_2_1,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0x1110++0x03
line.long 0x00 "SDMISTA_2_1,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
newline
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0x2000++0x03
line.long 0x00 "SDMSAR_2_2,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0x2004++0x03
line.long 0x00 "SDMDAR_2_2,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0x2008++0x03
line.long 0x00 "SDMTCR_2_2,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0x200C++0x03
line.long 0x00 "SDMCHCR_2_2,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
newline
bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
newline
rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
newline
bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
newline
bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
newline
bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
newline
bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0x2010++0x03
line.long 0x00 "SDMFIXSAR_2_2,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0x2014++0x03
line.long 0x00 "SDMFIXDAR_2_2,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0x2018++0x03
line.long 0x00 "SDMTCRB_2_2,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0x201C++0x03
line.long 0x00 "SDMCHCRB_2_2,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
newline
bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
newline
rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
newline
rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
newline
bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0x2028++0x03
line.long 0x00 "SDMTSR_2_2,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0x2038++0x03
line.long 0x00 "SDMTSRB_2_2,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0x2040++0x01
line.word 0x00 "SDMRS_2_2,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0x2048++0x03
line.long 0x00 "SDMBUFCR_2_2,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
newline
rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0x2050++0x03
line.long 0x00 "SDMDPBASE_2_2,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0x2054++0x03
line.long 0x00 "SDMDPCR_2_2,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x2058++0x03
line.long 0x00 "SDMDPEVTCR_2_2,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
newline
bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x205C++0x03
line.long 0x00 "SDMDPEVTCNT_2_2,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
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hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0x2060++0x03
line.long 0x00 "SDMFIXDPBASE_2_2,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0x2064++0x03
line.long 0x00 "SDMDREQOS_2_2,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0x2078++0x03
line.long 0x00 "SDMREGIONID_2_2,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x2080++0x03
line.long 0x00 "SDMCHID_2_2,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x20B0++0x03
line.long 0x00 "SDMSEC_2_2,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0x2100++0x03
line.long 0x00 "SDMCHCLR_2_2,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0x2110++0x03
line.long 0x00 "SDMISTA_2_2,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
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hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0x3000++0x03
line.long 0x00 "SDMSAR_2_3,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0x3004++0x03
line.long 0x00 "SDMDAR_2_3,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0x3008++0x03
line.long 0x00 "SDMTCR_2_3,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0x300C++0x03
line.long 0x00 "SDMCHCR_2_3,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
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bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
newline
rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
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bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
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bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
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bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
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bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0x3010++0x03
line.long 0x00 "SDMFIXSAR_2_3,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0x3014++0x03
line.long 0x00 "SDMFIXDAR_2_3,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0x3018++0x03
line.long 0x00 "SDMTCRB_2_3,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0x301C++0x03
line.long 0x00 "SDMCHCRB_2_3,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
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bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
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rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
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rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
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bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0x3028++0x03
line.long 0x00 "SDMTSR_2_3,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0x3038++0x03
line.long 0x00 "SDMTSRB_2_3,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0x3040++0x01
line.word 0x00 "SDMRS_2_3,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0x3048++0x03
line.long 0x00 "SDMBUFCR_2_3,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
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rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0x3050++0x03
line.long 0x00 "SDMDPBASE_2_3,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0x3054++0x03
line.long 0x00 "SDMDPCR_2_3,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x3058++0x03
line.long 0x00 "SDMDPEVTCR_2_3,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
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bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x305C++0x03
line.long 0x00 "SDMDPEVTCNT_2_3,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
newline
hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0x3060++0x03
line.long 0x00 "SDMFIXDPBASE_2_3,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0x3064++0x03
line.long 0x00 "SDMDREQOS_2_3,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0x3078++0x03
line.long 0x00 "SDMREGIONID_2_3,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x3080++0x03
line.long 0x00 "SDMCHID_2_3,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x30B0++0x03
line.long 0x00 "SDMSEC_2_3,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0x3100++0x03
line.long 0x00 "SDMCHCLR_2_3,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0x3110++0x03
line.long 0x00 "SDMISTA_2_3,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
newline
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0x4000++0x03
line.long 0x00 "SDMSAR_2_4,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0x4004++0x03
line.long 0x00 "SDMDAR_2_4,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0x4008++0x03
line.long 0x00 "SDMTCR_2_4,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0x400C++0x03
line.long 0x00 "SDMCHCR_2_4,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
newline
bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
newline
rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
newline
bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
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bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
newline
bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
newline
bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0x4010++0x03
line.long 0x00 "SDMFIXSAR_2_4,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0x4014++0x03
line.long 0x00 "SDMFIXDAR_2_4,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0x4018++0x03
line.long 0x00 "SDMTCRB_2_4,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0x401C++0x03
line.long 0x00 "SDMCHCRB_2_4,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
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bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
newline
rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
newline
rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
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bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0x4028++0x03
line.long 0x00 "SDMTSR_2_4,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0x4038++0x03
line.long 0x00 "SDMTSRB_2_4,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0x4040++0x01
line.word 0x00 "SDMRS_2_4,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0x4048++0x03
line.long 0x00 "SDMBUFCR_2_4,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
newline
rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0x4050++0x03
line.long 0x00 "SDMDPBASE_2_4,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0x4054++0x03
line.long 0x00 "SDMDPCR_2_4,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4058++0x03
line.long 0x00 "SDMDPEVTCR_2_4,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
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bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
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bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x405C++0x03
line.long 0x00 "SDMDPEVTCNT_2_4,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
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hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0x4060++0x03
line.long 0x00 "SDMFIXDPBASE_2_4,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0x4064++0x03
line.long 0x00 "SDMDREQOS_2_4,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0x4078++0x03
line.long 0x00 "SDMREGIONID_2_4,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4080++0x03
line.long 0x00 "SDMCHID_2_4,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x40B0++0x03
line.long 0x00 "SDMSEC_2_4,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0x4100++0x03
line.long 0x00 "SDMCHCLR_2_4,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0x4110++0x03
line.long 0x00 "SDMISTA_2_4,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
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hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0x5000++0x03
line.long 0x00 "SDMSAR_2_5,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0x5004++0x03
line.long 0x00 "SDMDAR_2_5,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0x5008++0x03
line.long 0x00 "SDMTCR_2_5,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0x500C++0x03
line.long 0x00 "SDMCHCR_2_5,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
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bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
newline
rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
newline
bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
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bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
newline
bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
newline
bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0x5010++0x03
line.long 0x00 "SDMFIXSAR_2_5,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0x5014++0x03
line.long 0x00 "SDMFIXDAR_2_5,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0x5018++0x03
line.long 0x00 "SDMTCRB_2_5,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0x501C++0x03
line.long 0x00 "SDMCHCRB_2_5,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
newline
bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
newline
rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
newline
rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
newline
bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0x5028++0x03
line.long 0x00 "SDMTSR_2_5,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0x5038++0x03
line.long 0x00 "SDMTSRB_2_5,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0x5040++0x01
line.word 0x00 "SDMRS_2_5,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0x5048++0x03
line.long 0x00 "SDMBUFCR_2_5,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
newline
rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0x5050++0x03
line.long 0x00 "SDMDPBASE_2_5,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0x5054++0x03
line.long 0x00 "SDMDPCR_2_5,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x5058++0x03
line.long 0x00 "SDMDPEVTCR_2_5,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
newline
bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x505C++0x03
line.long 0x00 "SDMDPEVTCNT_2_5,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
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hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0x5060++0x03
line.long 0x00 "SDMFIXDPBASE_2_5,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0x5064++0x03
line.long 0x00 "SDMDREQOS_2_5,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0x5078++0x03
line.long 0x00 "SDMREGIONID_2_5,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x5080++0x03
line.long 0x00 "SDMCHID_2_5,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x50B0++0x03
line.long 0x00 "SDMSEC_2_5,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0x5100++0x03
line.long 0x00 "SDMCHCLR_2_5,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0x5110++0x03
line.long 0x00 "SDMISTA_2_5,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
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hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0x6000++0x03
line.long 0x00 "SDMSAR_2_6,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0x6004++0x03
line.long 0x00 "SDMDAR_2_6,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0x6008++0x03
line.long 0x00 "SDMTCR_2_6,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0x600C++0x03
line.long 0x00 "SDMCHCR_2_6,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
newline
bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
newline
rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
newline
bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
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bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
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bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
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bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0x6010++0x03
line.long 0x00 "SDMFIXSAR_2_6,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0x6014++0x03
line.long 0x00 "SDMFIXDAR_2_6,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0x6018++0x03
line.long 0x00 "SDMTCRB_2_6,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0x601C++0x03
line.long 0x00 "SDMCHCRB_2_6,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
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bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
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rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
newline
rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
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bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0x6028++0x03
line.long 0x00 "SDMTSR_2_6,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0x6038++0x03
line.long 0x00 "SDMTSRB_2_6,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0x6040++0x01
line.word 0x00 "SDMRS_2_6,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0x6048++0x03
line.long 0x00 "SDMBUFCR_2_6,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
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rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0x6050++0x03
line.long 0x00 "SDMDPBASE_2_6,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0x6054++0x03
line.long 0x00 "SDMDPCR_2_6,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x6058++0x03
line.long 0x00 "SDMDPEVTCR_2_6,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
newline
bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x605C++0x03
line.long 0x00 "SDMDPEVTCNT_2_6,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
newline
hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0x6060++0x03
line.long 0x00 "SDMFIXDPBASE_2_6,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0x6064++0x03
line.long 0x00 "SDMDREQOS_2_6,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0x6078++0x03
line.long 0x00 "SDMREGIONID_2_6,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x6080++0x03
line.long 0x00 "SDMCHID_2_6,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x60B0++0x03
line.long 0x00 "SDMSEC_2_6,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0x6100++0x03
line.long 0x00 "SDMCHCLR_2_6,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0x6110++0x03
line.long 0x00 "SDMISTA_2_6,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
newline
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0x7000++0x03
line.long 0x00 "SDMSAR_2_7,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0x7004++0x03
line.long 0x00 "SDMDAR_2_7,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0x7008++0x03
line.long 0x00 "SDMTCR_2_7,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0x700C++0x03
line.long 0x00 "SDMCHCR_2_7,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
newline
bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
newline
rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
newline
bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
newline
bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
newline
bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
newline
bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0x7010++0x03
line.long 0x00 "SDMFIXSAR_2_7,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0x7014++0x03
line.long 0x00 "SDMFIXDAR_2_7,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0x7018++0x03
line.long 0x00 "SDMTCRB_2_7,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0x701C++0x03
line.long 0x00 "SDMCHCRB_2_7,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
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bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
newline
rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
newline
rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
newline
bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0x7028++0x03
line.long 0x00 "SDMTSR_2_7,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0x7038++0x03
line.long 0x00 "SDMTSRB_2_7,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0x7040++0x01
line.word 0x00 "SDMRS_2_7,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0x7048++0x03
line.long 0x00 "SDMBUFCR_2_7,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
newline
rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0x7050++0x03
line.long 0x00 "SDMDPBASE_2_7,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0x7054++0x03
line.long 0x00 "SDMDPCR_2_7,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x7058++0x03
line.long 0x00 "SDMDPEVTCR_2_7,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
newline
bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x705C++0x03
line.long 0x00 "SDMDPEVTCNT_2_7,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
newline
hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0x7060++0x03
line.long 0x00 "SDMFIXDPBASE_2_7,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0x7064++0x03
line.long 0x00 "SDMDREQOS_2_7,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0x7078++0x03
line.long 0x00 "SDMREGIONID_2_7,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x7080++0x03
line.long 0x00 "SDMCHID_2_7,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x70B0++0x03
line.long 0x00 "SDMSEC_2_7,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0x7100++0x03
line.long 0x00 "SDMCHCLR_2_7,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0x7110++0x03
line.long 0x00 "SDMISTA_2_7,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
newline
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0x8000++0x03
line.long 0x00 "SDMSAR_2_8,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0x8004++0x03
line.long 0x00 "SDMDAR_2_8,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0x8008++0x03
line.long 0x00 "SDMTCR_2_8,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0x800C++0x03
line.long 0x00 "SDMCHCR_2_8,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
newline
bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
newline
rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
newline
bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
newline
bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
newline
bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
newline
bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0x8010++0x03
line.long 0x00 "SDMFIXSAR_2_8,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0x8014++0x03
line.long 0x00 "SDMFIXDAR_2_8,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0x8018++0x03
line.long 0x00 "SDMTCRB_2_8,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0x801C++0x03
line.long 0x00 "SDMCHCRB_2_8,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
newline
bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
newline
rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
newline
rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
newline
bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0x8028++0x03
line.long 0x00 "SDMTSR_2_8,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0x8038++0x03
line.long 0x00 "SDMTSRB_2_8,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0x8040++0x01
line.word 0x00 "SDMRS_2_8,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0x8048++0x03
line.long 0x00 "SDMBUFCR_2_8,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
newline
rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0x8050++0x03
line.long 0x00 "SDMDPBASE_2_8,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0x8054++0x03
line.long 0x00 "SDMDPCR_2_8,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8058++0x03
line.long 0x00 "SDMDPEVTCR_2_8,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
newline
bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x805C++0x03
line.long 0x00 "SDMDPEVTCNT_2_8,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
newline
hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0x8060++0x03
line.long 0x00 "SDMFIXDPBASE_2_8,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0x8064++0x03
line.long 0x00 "SDMDREQOS_2_8,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0x8078++0x03
line.long 0x00 "SDMREGIONID_2_8,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8080++0x03
line.long 0x00 "SDMCHID_2_8,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x80B0++0x03
line.long 0x00 "SDMSEC_2_8,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0x8100++0x03
line.long 0x00 "SDMCHCLR_2_8,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0x8110++0x03
line.long 0x00 "SDMISTA_2_8,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
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hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0x9000++0x03
line.long 0x00 "SDMSAR_2_9,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0x9004++0x03
line.long 0x00 "SDMDAR_2_9,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0x9008++0x03
line.long 0x00 "SDMTCR_2_9,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0x900C++0x03
line.long 0x00 "SDMCHCR_2_9,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
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bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
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rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
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bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
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bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
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bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
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bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0x9010++0x03
line.long 0x00 "SDMFIXSAR_2_9,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0x9014++0x03
line.long 0x00 "SDMFIXDAR_2_9,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0x9018++0x03
line.long 0x00 "SDMTCRB_2_9,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0x901C++0x03
line.long 0x00 "SDMCHCRB_2_9,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
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bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
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rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
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rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
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bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0x9028++0x03
line.long 0x00 "SDMTSR_2_9,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0x9038++0x03
line.long 0x00 "SDMTSRB_2_9,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0x9040++0x01
line.word 0x00 "SDMRS_2_9,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0x9048++0x03
line.long 0x00 "SDMBUFCR_2_9,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
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rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0x9050++0x03
line.long 0x00 "SDMDPBASE_2_9,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0x9054++0x03
line.long 0x00 "SDMDPCR_2_9,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x9058++0x03
line.long 0x00 "SDMDPEVTCR_2_9,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
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bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
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bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x905C++0x03
line.long 0x00 "SDMDPEVTCNT_2_9,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
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hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0x9060++0x03
line.long 0x00 "SDMFIXDPBASE_2_9,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0x9064++0x03
line.long 0x00 "SDMDREQOS_2_9,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0x9078++0x03
line.long 0x00 "SDMREGIONID_2_9,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x9080++0x03
line.long 0x00 "SDMCHID_2_9,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x90B0++0x03
line.long 0x00 "SDMSEC_2_9,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0x9100++0x03
line.long 0x00 "SDMCHCLR_2_9,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0x9110++0x03
line.long 0x00 "SDMISTA_2_9,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
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hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0xA000++0x03
line.long 0x00 "SDMSAR_2_10,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0xA004++0x03
line.long 0x00 "SDMDAR_2_10,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0xA008++0x03
line.long 0x00 "SDMTCR_2_10,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0xA00C++0x03
line.long 0x00 "SDMCHCR_2_10,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
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bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
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rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
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bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
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bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
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bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
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bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0xA010++0x03
line.long 0x00 "SDMFIXSAR_2_10,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0xA014++0x03
line.long 0x00 "SDMFIXDAR_2_10,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0xA018++0x03
line.long 0x00 "SDMTCRB_2_10,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0xA01C++0x03
line.long 0x00 "SDMCHCRB_2_10,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
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bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
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rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
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rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
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bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0xA028++0x03
line.long 0x00 "SDMTSR_2_10,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0xA038++0x03
line.long 0x00 "SDMTSRB_2_10,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0xA040++0x01
line.word 0x00 "SDMRS_2_10,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0xA048++0x03
line.long 0x00 "SDMBUFCR_2_10,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
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rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0xA050++0x03
line.long 0x00 "SDMDPBASE_2_10,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0xA054++0x03
line.long 0x00 "SDMDPCR_2_10,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA058++0x03
line.long 0x00 "SDMDPEVTCR_2_10,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
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bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
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bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xA05C++0x03
line.long 0x00 "SDMDPEVTCNT_2_10,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
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hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0xA060++0x03
line.long 0x00 "SDMFIXDPBASE_2_10,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0xA064++0x03
line.long 0x00 "SDMDREQOS_2_10,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0xA078++0x03
line.long 0x00 "SDMREGIONID_2_10,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA080++0x03
line.long 0x00 "SDMCHID_2_10,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA0B0++0x03
line.long 0x00 "SDMSEC_2_10,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0xA100++0x03
line.long 0x00 "SDMCHCLR_2_10,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0xA110++0x03
line.long 0x00 "SDMISTA_2_10,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
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hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0xB000++0x03
line.long 0x00 "SDMSAR_2_11,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0xB004++0x03
line.long 0x00 "SDMDAR_2_11,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0xB008++0x03
line.long 0x00 "SDMTCR_2_11,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0xB00C++0x03
line.long 0x00 "SDMCHCR_2_11,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
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bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
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rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
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bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
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bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
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bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
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bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0xB010++0x03
line.long 0x00 "SDMFIXSAR_2_11,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0xB014++0x03
line.long 0x00 "SDMFIXDAR_2_11,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0xB018++0x03
line.long 0x00 "SDMTCRB_2_11,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0xB01C++0x03
line.long 0x00 "SDMCHCRB_2_11,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
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bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
newline
rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
newline
rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
newline
bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0xB028++0x03
line.long 0x00 "SDMTSR_2_11,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0xB038++0x03
line.long 0x00 "SDMTSRB_2_11,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0xB040++0x01
line.word 0x00 "SDMRS_2_11,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0xB048++0x03
line.long 0x00 "SDMBUFCR_2_11,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
newline
rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0xB050++0x03
line.long 0x00 "SDMDPBASE_2_11,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0xB054++0x03
line.long 0x00 "SDMDPCR_2_11,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB058++0x03
line.long 0x00 "SDMDPEVTCR_2_11,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
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bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xB05C++0x03
line.long 0x00 "SDMDPEVTCNT_2_11,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
newline
hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0xB060++0x03
line.long 0x00 "SDMFIXDPBASE_2_11,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0xB064++0x03
line.long 0x00 "SDMDREQOS_2_11,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0xB078++0x03
line.long 0x00 "SDMREGIONID_2_11,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB080++0x03
line.long 0x00 "SDMCHID_2_11,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB0B0++0x03
line.long 0x00 "SDMSEC_2_11,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0xB100++0x03
line.long 0x00 "SDMCHCLR_2_11,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0xB110++0x03
line.long 0x00 "SDMISTA_2_11,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
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hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0xC000++0x03
line.long 0x00 "SDMSAR_2_12,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0xC004++0x03
line.long 0x00 "SDMDAR_2_12,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0xC008++0x03
line.long 0x00 "SDMTCR_2_12,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0xC00C++0x03
line.long 0x00 "SDMCHCR_2_12,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
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bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
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rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
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bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
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bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
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bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
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bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0xC010++0x03
line.long 0x00 "SDMFIXSAR_2_12,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0xC014++0x03
line.long 0x00 "SDMFIXDAR_2_12,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0xC018++0x03
line.long 0x00 "SDMTCRB_2_12,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0xC01C++0x03
line.long 0x00 "SDMCHCRB_2_12,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
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bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
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rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
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rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
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bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0xC028++0x03
line.long 0x00 "SDMTSR_2_12,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0xC038++0x03
line.long 0x00 "SDMTSRB_2_12,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0xC040++0x01
line.word 0x00 "SDMRS_2_12,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0xC048++0x03
line.long 0x00 "SDMBUFCR_2_12,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
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rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0xC050++0x03
line.long 0x00 "SDMDPBASE_2_12,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0xC054++0x03
line.long 0x00 "SDMDPCR_2_12,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC058++0x03
line.long 0x00 "SDMDPEVTCR_2_12,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
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bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
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bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xC05C++0x03
line.long 0x00 "SDMDPEVTCNT_2_12,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
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hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0xC060++0x03
line.long 0x00 "SDMFIXDPBASE_2_12,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0xC064++0x03
line.long 0x00 "SDMDREQOS_2_12,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0xC078++0x03
line.long 0x00 "SDMREGIONID_2_12,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC080++0x03
line.long 0x00 "SDMCHID_2_12,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC0B0++0x03
line.long 0x00 "SDMSEC_2_12,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0xC100++0x03
line.long 0x00 "SDMCHCLR_2_12,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0xC110++0x03
line.long 0x00 "SDMISTA_2_12,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
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hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0xD000++0x03
line.long 0x00 "SDMSAR_2_13,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0xD004++0x03
line.long 0x00 "SDMDAR_2_13,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0xD008++0x03
line.long 0x00 "SDMTCR_2_13,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0xD00C++0x03
line.long 0x00 "SDMCHCR_2_13,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
newline
bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
newline
rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
newline
bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
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bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
newline
bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
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bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0xD010++0x03
line.long 0x00 "SDMFIXSAR_2_13,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0xD014++0x03
line.long 0x00 "SDMFIXDAR_2_13,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0xD018++0x03
line.long 0x00 "SDMTCRB_2_13,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0xD01C++0x03
line.long 0x00 "SDMCHCRB_2_13,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
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bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
newline
rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
newline
rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
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bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0xD028++0x03
line.long 0x00 "SDMTSR_2_13,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0xD038++0x03
line.long 0x00 "SDMTSRB_2_13,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0xD040++0x01
line.word 0x00 "SDMRS_2_13,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0xD048++0x03
line.long 0x00 "SDMBUFCR_2_13,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
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rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0xD050++0x03
line.long 0x00 "SDMDPBASE_2_13,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0xD054++0x03
line.long 0x00 "SDMDPCR_2_13,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xD058++0x03
line.long 0x00 "SDMDPEVTCR_2_13,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
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bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
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bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xD05C++0x03
line.long 0x00 "SDMDPEVTCNT_2_13,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
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hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0xD060++0x03
line.long 0x00 "SDMFIXDPBASE_2_13,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0xD064++0x03
line.long 0x00 "SDMDREQOS_2_13,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0xD078++0x03
line.long 0x00 "SDMREGIONID_2_13,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xD080++0x03
line.long 0x00 "SDMCHID_2_13,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xD0B0++0x03
line.long 0x00 "SDMSEC_2_13,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0xD100++0x03
line.long 0x00 "SDMCHCLR_2_13,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0xD110++0x03
line.long 0x00 "SDMISTA_2_13,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
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hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0xE000++0x03
line.long 0x00 "SDMSAR_2_14,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0xE004++0x03
line.long 0x00 "SDMDAR_2_14,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0xE008++0x03
line.long 0x00 "SDMTCR_2_14,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0xE00C++0x03
line.long 0x00 "SDMCHCR_2_14,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
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bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
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rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
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bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
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bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
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bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
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bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0xE010++0x03
line.long 0x00 "SDMFIXSAR_2_14,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0xE014++0x03
line.long 0x00 "SDMFIXDAR_2_14,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0xE018++0x03
line.long 0x00 "SDMTCRB_2_14,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0xE01C++0x03
line.long 0x00 "SDMCHCRB_2_14,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
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bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
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rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
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rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
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bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0xE028++0x03
line.long 0x00 "SDMTSR_2_14,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0xE038++0x03
line.long 0x00 "SDMTSRB_2_14,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0xE040++0x01
line.word 0x00 "SDMRS_2_14,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0xE048++0x03
line.long 0x00 "SDMBUFCR_2_14,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
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rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0xE050++0x03
line.long 0x00 "SDMDPBASE_2_14,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0xE054++0x03
line.long 0x00 "SDMDPCR_2_14,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xE058++0x03
line.long 0x00 "SDMDPEVTCR_2_14,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
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bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
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bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xE05C++0x03
line.long 0x00 "SDMDPEVTCNT_2_14,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
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hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0xE060++0x03
line.long 0x00 "SDMFIXDPBASE_2_14,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0xE064++0x03
line.long 0x00 "SDMDREQOS_2_14,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0xE078++0x03
line.long 0x00 "SDMREGIONID_2_14,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xE080++0x03
line.long 0x00 "SDMCHID_2_14,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xE0B0++0x03
line.long 0x00 "SDMSEC_2_14,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0xE100++0x03
line.long 0x00 "SDMCHCLR_2_14,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0xE110++0x03
line.long 0x00 "SDMISTA_2_14,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
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hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
group.long 0xF000++0x03
line.long 0x00 "SDMSAR_2_15,SAR is 32-bit readable/writable register that specify the source address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "SAR_31_0,the source address of a DMA transfer"
group.long 0xF004++0x03
line.long 0x00 "SDMDAR_2_15,DAR is 32-bit readable/writable register that specify the destination address of a DMA transfer"
hexmask.long 0x00 0.--31. 1. "DAR_31_0,the destination address of a DMA transfer"
group.long 0xF008++0x03
line.long 0x00 "SDMTCR_2_15,TCR register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCR_23_0,SYS-DMAC includes DATA buffer and Read/Write are behaving independently"
group.long 0xF00C++0x03
line.long 0x00 "SDMCHCR_2_15,CHCR register is 32-bit readable/writable register that controls the DMA transfer mode"
bitfld.long 0x00 31. "CAE,Address error flag Indicates that the address error interruption occurred in the DMA transfer" "0,1"
bitfld.long 0x00 30. "CAIE,Channel address error interrupt enable Specifies whether an interrupt request is generated to CPU ass occurrence of address error" "0: Interrupt request disabled,1: Interrupt request enabled"
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bitfld.long 0x00 28.--29. "DPM_1_0,Descriptor operating mode Specifies whether Descriptor is enabled or disabled and its operational mode" "0: disable (Normal mode),1: enable (Descriptor normal mode),2: enable (Descriptor repeat mode),3: enable (Descriptor Read-out Interrupt Mode"
bitfld.long 0x00 24.--27. "RPT_3_0,Descriptor Setting Update Specify the parameters to be updated from the descriptor memory" "0: Disabled,1: Enabled,?..."
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rbitfld.long 0x00 23. "WAIT,Descriptor WAIT status" "0: Normal Processing,1: WAIT/Suspend"
bitfld.long 0x00 22. "DPB,Descriptor start bit Specifies configuration to be loaded at beginning of Descriptor" "0: Starts from SAR DAR TCR,1: Starting after Descriptor Read-out"
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bitfld.long 0x00 20.--21. "TS_3_2,DMA transfer size DMA transfer size is set up together with TS[1:0]" "0: Byte units transfer,1: Word (2-byte) units transfer,2: Longword (4-byte) units transfer,3: 16-byte units transfer"
bitfld.long 0x00 19. "DSE,Descriptor step end When DSIE bit is set to 1 and Descriptor is enabled DSE bit is set to 1 at the termination of DMA transfer" "0: DMA transfer is still running or terminated,1: Termination of one step of Descriptor"
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bitfld.long 0x00 18. "DSIE,Descriptor step end interrupt enable Specifies whether an interrupt request is generated to CPU at the time of termination of one step of Descriptor" "0: Interrupt request is disabled,1: Interrupt request is enabled"
rbitfld.long 0x00 16.--17. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 14.--15. "DM_1_0,Destination address mode Specify whether the DMA destination address is incremented or fixed and the amount of increment" "0: Fixed destination address,1: Destination address is incremented + 1 in byte,2: Destination address is decremented  1 in byte,3: Setting Prohibited"
bitfld.long 0x00 12.--13. "SM_1_0,Source Address Mode Specify whether the DMA source address is incremented or fixed and the amount of increment" "0: Fixed source address,1: Source address is incremented + 1 in byte units,2: Source address is decremented  1 in byte units,3: Setting Prohibited"
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bitfld.long 0x00 8.--11. "RS_3_0,Resource selection Specify which transfer requests will be sent to the RT-DMAC" "0: Setting prohibited,?,?,?,4: Auto request,?,?,?,8: Selected by DMA extended resource selector,?..."
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 3.--4. "TS_1_0,DMA transfer size" "0,1,2,3"
bitfld.long 0x00 2. "IE,Interrupt enabling Specifies whether or not an interrupt request is generated to CPU at the termination of DMA transfer" "0: Interrupt request is disabled,1: Interrupt request is enabled"
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bitfld.long 0x00 1. "TE,Transfer end flag The TE bit is set to 1 when data transfer ends when TCR becomes 0" "0,1"
bitfld.long 0x00 0. "DE,DMA Enable Enables or disables the DMA transfer" "0,1"
group.long 0xF010++0x03
line.long 0x00 "SDMFIXSAR_2_15,FIXSAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits source address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "SAR_39_32,MSB 8-bits of the 40-bits source address of a DMA transfer"
group.long 0xF014++0x03
line.long 0x00 "SDMFIXDAR_2_15,FIXDAR is 32-bit readable/writable register that specify the MSB 8-bits of the 40-bits destination address of a DMA transfer"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DAR_39_32,MSB 8-bits of the 40-bits destination address of a DMA transfer"
group.long 0xF018++0x03
line.long 0x00 "SDMTCRB_2_15,TCRB register is 32-bit readable/writable register that specify the number of times of DMA transfer"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "TCRB_23_0,The number of times of DMA transfer is 1 when the setting is H'0000 0001 16 777 215 when H'00FF FFFF is set (the maximum)"
group.long 0xF01C++0x03
line.long 0x00 "SDMCHCRB_2_15,CHCRB registers are 32-bit readable/writable registers that control the DMA transfer mode"
hexmask.long.byte 0x00 24.--31. 1. "DCNT_7_0,Descriptor number of step Specify the number of descriptor steps with DCNT + 1"
hexmask.long.byte 0x00 16.--23. 1. "DPTR_7_0,Descriptor pointer If it reads the position of Descriptor read into next can be checked"
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bitfld.long 0x00 15. "DRST,Descriptor reset Reset Descriptor pointer" "0,1"
bitfld.long 0x00 14. "DREQOSEN,DREQ Outstanding Enable" "0: Disable (Legacy),1: Enable"
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rbitfld.long 0x00 11.--13. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "DSIEEN,Descriptor DSIE Enable" "0: DSIE setting prohibit,1: DSIE setting enable"
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rbitfld.long 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 8. "DTS,Descriptor Byte Size Transfer" "0: CHCR.TS size,1: Byte Size"
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bitfld.long 0x00 4.--7. "SLM_3_0,DMA Transfer Slow Speed mode Specifies the number of times by clock (ZS) cycle that DMA transfer is kept waiting after single DMA transfer" "0: normal mode,?,?,?,?,?,?,?,8: once in 256 clock cycle,9: once in 512 clock cycle,10: once in 1024 clock cycle,?,?,?,?,15: once in 32768 clock cycle Other than above"
bitfld.long 0x00 0.--3. "PRI_3_0,Channel Request Priority Setting These bits set the priority of the channel request" "0: Lowest priority,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Highest priority"
group.long 0xF028++0x03
line.long 0x00 "SDMTSR_2_15,TSRS register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSR_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.long 0xF038++0x03
line.long 0x00 "SDMTSRB_2_15,TSRB register is 32-bit readable/writable register that specify the total size of DMA transfer"
hexmask.long 0x00 0.--31. 1. "TSRB_31_0,The total size of DMA transfer is 1-byte when the setting is H'0000 0001 4 294 967 295-byte when H'FFFF FFFF is set and 4 294 967 296-byte (the maximum) when H'0000 0000 is set"
group.word 0xF040++0x01
line.word 0x00 "SDMRS_2_15,The DMRS registers are 16-bit readable/writable registers that specify the peripheral module as the source of the DMA transfer request for each channel"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 2.--7. "MID_5_0,DMA Request Source Adoption MID[5] to MID[0] (MID) Refer to table 30.5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.word 0x00 0.--1. "RID_1_0,DMA Request Source Adoption RID[1] and RID[0] (RID) Refer to table 30.5" "0,1,2,3"
group.long 0xF048++0x03
line.long 0x00 "SDMBUFCR_2_15,BUFCR register is 32-bit readable/writable register that controls the upper limit of buffer and burst unit to the SDRAM"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long.word 0x00 16.--24. 1. "MBU_8_0,Maximum burst unit to SDRAM This register is effective to SDRAM access and all except for that is control of the transmission size unit"
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rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "ULB_10_0,Upper limit of buffer This register controls the upper limit value of the buffering"
group.long 0xF050++0x03
line.long 0x00 "SDMDPBASE_2_15,DPBASE specifies base address of Descriptor"
hexmask.long 0x00 4.--31. 1. "DPBASE_31_4,Base address of Descriptor Place each stage of the descriptor memory on a 16-byte boundary"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0. "SEL,Descriptor memory selection bit Select the memory to be used as descriptor memory" "0: Setting Prohibited,1: Built-in memory or External memory is used"
group.long 0xF054++0x03
line.long 0x00 "SDMDPCR_2_15,DPCR register is 32-bit readable/writable register that controls the timing which will output descriptor read-out interruption at descriptor mode 3"
hexmask.long.byte 0x00 24.--31. 1. "DIPT_7_0,DIPT extend to 12bits to support descriptor entries up to 4096"
rbitfld.long 0x00 20.--23. "Reserved_20,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "DIPT_11_8,DIPT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "DCNT_11_8,DCNT extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 0.--3. "DPTR_11_8,DPTR extend to 12bits to support descriptor entries up to 4096" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xF058++0x03
line.long 0x00 "SDMDPEVTCR_2_15,DPEVTCR register is 32-bit readable/writable register that controls the event handling for descriptor processing"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "RST,Initialize event counter Write 1 to initialize" "0,1"
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bitfld.long 0x00 6. "EXEN,Watching external event is enable" "0,1"
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
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bitfld.long 0x00 0.--4. "EVTID_4_0,Select external event id SYS-DMAC module have [31:0] EVENT input port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xF05C++0x03
line.long 0x00 "SDMDPEVTCNT_2_15,DPEVTCNT register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
rbitfld.long 0x00 7. "OV,Event Counter Overflow flag" "0: not overflow,1: Overflow If event counter reaches"
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hexmask.long.byte 0x00 0.--6. 1. "EVTCNT_6_0,Event Counter When writing counter increment(regardless of written value) When reading return current event counter value"
group.long 0xF060++0x03
line.long 0x00 "SDMFIXDPBASE_2_15,DPBASE specifies base address of Descriptor"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DPBASE_39_32,Base address of Descriptor"
group.long 0xF064++0x03
line.long 0x00 "SDMDREQOS_2_15,DREQOS register is 32-bit readable/writable register that specify the counter for event handling"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DREQOS_7_0,DREQ Outstanding"
group.long 0xF078++0x03
line.long 0x00 "SDMREGIONID_2_15,REGIONID register is 32-bit readable/writable register that specify Region ID for security access"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
bitfld.long 0x00 0.--3. "REGIONID,Region ID for each channel the value will set to AR/AW USER_OUT[5:2] of MEM/BUS/PERI I/F The allowable setting value is determined by REGION_ID_ENABLE from BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xF080++0x03
line.long 0x00 "SDMCHID_2_15,CHID register is 32-bit readable register that specify CH ID"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved"
rbitfld.long 0x00 0.--3. "CHID,Current Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xF0B0++0x03
line.long 0x00 "SDMSEC_2_15,DMSEC is a 32-bit readable/writeable register that controls the secure attribute of each channel"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "S,Current channel secure mode setting" "0: nonsecure mode,1: secure mode"
group.long 0xF100++0x03
line.long 0x00 "SDMCHCLR_2_15,CHCLR registers are 32-bit writable registers that initialize in the channel unit"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CLR,All registers in the channel can be cleared by writing in these bits" "0: Ignored,1: Channel registers"
group.long 0xF110++0x03
line.long 0x00 "SDMISTA_2_15,DMISTA is 32-bit readable register which indicates interrupt signal status of each channel"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
rbitfld.long 0x00 16. "OV,Event counter overflow status of channel 0: Event counter overflow not exist" "0: Event counter overflow not exist,1: Event counter overflow exist"
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hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
rbitfld.long 0x00 0. "I,Interrupt status of channel 0: Interrupt not exist" "0: Interrupt not exist,1: Interrupt exist"
tree.end
tree.end
tree "DBSC4"
base ad:0xE6790000
group.long 0x00++0x03
line.long 0x00 "DBSYSCONF0,Note:This register should be accessed in 32-bit units"
hexmask.long.tbyte 0x00 11.--31. 1. "Reserved_11,Reserved.These bits are always read as 0"
bitfld.long 0x00 8.--10. "mch,The number of channels of the memory for each logic 1ch is specified" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 3.--7. "Reserved_3,Reserved.These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--2. "pch,The number of physical for each logic 1ch channels is specified" "0,1,2,3,4,5,6,7"
group.long 0x04++0x03
line.long 0x00 "DBSYSCONF1,Note:This register must only be written from within the activation sequence (see section 33.4.1 Activation Sequence)"
hexmask.long 0x00 2.--31. 1. "Reserved_2,Reserved.These bits are always read as 0"
bitfld.long 0x00 0.--1. "freqratio,Frequency Ratio Setting" "0,1,2,3"
group.long 0x08++0x03
line.long 0x00 "DBSYSCONF1A,"
hexmask.long 0x00 2.--31. 1. "Reserved_2,Reserved.These bits are always read as 0"
bitfld.long 0x00 0.--1. "freqratioa,Frequency Ratio Setting" "0,1,2,3"
group.long 0x0C++0x03
line.long 0x00 "DBSYSCONF2,"
hexmask.long 0x00 3.--31. 1. "Reserved_3,Reserved.These bits are always read as 0"
bitfld.long 0x00 0.--2. "sli_schmdd,DDR Interface selection" "0,1,2,3,4,5,6,7"
group.long 0x10++0x03
line.long 0x00 "DBPHYCONF0,Note:This register must only be written from within the activation sequence (see section 33.4.1 Activation Sequence)"
hexmask.long.tbyte 0x00 9.--31. 1. "Reserved_9,Reserved.These bits are always read as 0"
rbitfld.long 0x00 8. "Reserved_8,Reserved" "0,1"
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rbitfld.long 0x00 2.--7. "Reserved_2,Reserved.These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "phytype,PHY Type These bits specify the PHY type" "0,1,2,3"
group.long 0x14++0x03
line.long 0x00 "DBSYSCONF2A,"
hexmask.long.tbyte 0x00 9.--31. 1. "Reserved_9,Reserved.These bits are always read as 0"
bitfld.long 0x00 3.--8. "chpos,Channel position" "?,?,?,?,?,?,?,?,8: Address[8],9: Address[9],10: Address[10],11: Address[11],12: Address[12] Settings other,?..."
newline
bitfld.long 0x00 0.--2. "sli_schmda,DDR Interface selection" "0,1,2,3,4,5,6,7"
group.long 0x20++0x03
line.long 0x00 "DBMEMKIND,Note:This register must only be written from within the activation sequence (see section 33.4.1 Activation Sequence)"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved.These bits are always read as 0"
bitfld.long 0x00 0.--3. "ddcg,SDRAM Type These bits can set the type of SDRAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x24++0x03
line.long 0x00 "DBMEMKINDA,"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved.These bits are always read as 0"
bitfld.long 0x00 0.--3. "ddcga,SDRAM Type These bits can set the type of SDRAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x30++0x03
line.long 0x00 "DBMEMCONF00,Note:This register must only be written from within the activation sequence (see section 33.4.1 Activation Sequence)"
bitfld.long 0x00 30.--31. "dens00,Channel 0 Rank 0 Memory Density Type Specify the density type of the memory to be connected to rank 0 of channel 0" "0: 2^n type,1: 2^n ? 3 type Settings,?..."
rbitfld.long 0x00 29. "Reserved_29,Reserved.These bits are always read as 0" "0,1"
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bitfld.long 0x00 24.--28. "awrw00,Channel 0 Rank 0 Row Address Bit width Specify the width in bits of row addresses of rank 0 of channel 0" "0: 16 bits Settings other than,?,?,?,?,?,?,?,?,?,?,?,12: 12 bits 0,13: 13 bits,?..."
rbitfld.long 0x00 19.--23. "Reserved_19,Reserved.These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 16.--18. "awbk00,Channel 0 Rank 0 Number of Banks Specify the number of banks of rank 0 of channel 0" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved.These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "awcl00,Channel 0 Rank 0 Column Address Bit Width Specify the width in bits of column addresses of rank 0 of channel 0" "?,?,?,?,?,?,?,?,?,9: 9 bits,10: 10 bits,?,?,?,?,15: 15 bits Settings"
rbitfld.long 0x00 2.--7. "Reserved_2,Reserved.These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 0.--1. "dw00,Channel 0 Rank 0 Memory External Data Bus Width Specify the width of the external data bus of rank 0 of channel 0" "?,1: 16 bits,2: 32 bits Settings,?..."
group.long 0x34++0x03
line.long 0x00 "DBMEMCONF01,Notes:1.This register must only be written from within the activation sequence (see section 33.4.1 Activation Sequence)"
bitfld.long 0x00 30.--31. "dens01,Channel 0 Rank 1 Memory Density Type Specify the density type of the memory to be connected to rank 1 of channel 0" "0: 2^n type,1: 2^n ? 3 type Settings,?..."
rbitfld.long 0x00 29. "Reserved_29,Reserved.These bits are always read as 0" "0,1"
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bitfld.long 0x00 24.--28. "awrw01,Channel 0 Rank 1 Row Address Bit Width Specify the width in bits of row addresses of rank 1 of channel 0" "0: 16 bits Settings other than,?,?,?,?,?,?,?,?,?,?,?,12: 12 bits 0,13: 13 bits,?..."
rbitfld.long 0x00 19.--23. "Reserved_19,Reserved.These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 16.--18. "awbk01,Channel 0 Rank 1 Number of Banks Specify the number of banks of rank 1 of channel 0" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved.These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "awcl01,Channel 0 Rank 1 Column Address Bit Width Specify the width in bits of column addresses of rank 1 of channel 0" "?,?,?,?,?,?,?,?,?,9: 9 bits,10: 10 bits,?,?,?,?,15: 15 bits Settings"
rbitfld.long 0x00 2.--7. "Reserved_2,Reserved.These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0.--1. "dw01,Channel 0 Rank 1 External Data Bus Width Specify the width of the external data bus of rank 1 of channel 0" "0,1,2,3"
group.long 0x40++0x03
line.long 0x00 "DBMEMCONF10,Notes:1.This register must only be written from within the activation sequence (see section 33.4.1 Activation Sequence)"
bitfld.long 0x00 30.--31. "dens10,Channel 1 Rank 0 Memory Density Type Specify the density type of the memory to be connected to rank 0 of channel 1" "0: 2^n type,1: 2^n ? 3 type Settings,?..."
rbitfld.long 0x00 29. "Reserved_29,Reserved.These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 24.--28. "awrw10,Channel 1 Rank 0 Row Address Bit Width Specify the width in bits of row addresses of rank 0 of channel 1" "0: 16 bits Settings other than,?,?,?,?,?,?,?,?,?,?,?,12: 12 bits 0,13: 13 bits,?..."
rbitfld.long 0x00 19.--23. "Reserved_19,Reserved.These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 16.--18. "awbk10,Channel 1 Rank 0 Number of Banks Specify the number of banks of rank 0 of channel 1" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved.These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "awcl10,Channel 1 Rank 0 Column Address Bit Width Specify the width in bits of column addresses of rank 0 of channel 1" "?,?,?,?,?,?,?,?,?,9: 9 bits,10: 10 bits,?,?,?,?,15: 15 bits Settings"
rbitfld.long 0x00 2.--7. "Reserved_2,Reserved.These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0.--1. "dw10,Channel 1 Rank 0 External Data Bus Width Specify the width of the external data bus of rank 0 of channel 1" "0,1,2,3"
group.long 0x44++0x03
line.long 0x00 "DBMEMCONF11,Notes:1.This register must only be written from within the activation sequence (see section 33.4.1 Activation Sequence)"
bitfld.long 0x00 30.--31. "dens11,Channel 1 Rank 1 Memory Density Type Specify the density type of the memory to be connected to rank 1 of channel 1" "0: 2^n type,1: 2^n ? 3 type Settings,?..."
rbitfld.long 0x00 29. "Reserved_29,Reserved.These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 24.--28. "awrw11,Channel 1 Rank 1 Row Address Bit Width Specify the width in bits of row addresses of rank 1 of channel 1" "0: 16 bits Settings other than,?,?,?,?,?,?,?,?,?,?,?,12: 12 bits 0,13: 13 bits,?..."
rbitfld.long 0x00 19.--23. "Reserved_19,Reserved.These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 16.--18. "awbk11,Channel 1 Rank 1 Number of Banks Specify the number of banks of rank 1 of channel 1" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved.These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "awcl11,Channel 1 Rank 1 Column Address Bit Width Specify the width in bits of column addresses of rank 1 of channel 1" "?,?,?,?,?,?,?,?,?,9: 9 bits,10: 10 bits,?,?,?,?,15: 15 bits Settings"
rbitfld.long 0x00 2.--7. "Reserved_2,Reserved.These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0.--1. "dw11,Channel 1 Rank 1 External Data Bus Width Specify the width of the external data bus of rank 1 of channel 1" "?,1: 16 bits,2: 32 bits Settings,?..."
group.long 0x70++0x03
line.long 0x00 "DBMEMCONF00A,Note:This register must only be written from within the activation sequence (see section 33.4.1 Activation Sequence)"
bitfld.long 0x00 30.--31. "dens00a,Channel 0 Rank 0 Memory Density Type Specify the density type of the memory to be connected to rank 0 of channel 0" "0: 2^n type,1: 2^n ? 3 type Settings,?..."
rbitfld.long 0x00 29. "Reserved_29,Reserved.These bits are always read as 0" "0,1"
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bitfld.long 0x00 24.--28. "awrw00a,Channel 0 Rank 0 Row Address Bit width Specify the width in bits of row addresses of rank 0 of channel 0" "0: 16 bits Settings other than,?,?,?,?,?,?,?,?,?,?,?,12: 12 bits 0,13: 13 bits,?..."
rbitfld.long 0x00 19.--23. "Reserved_19,Reserved.These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 16.--18. "awbk00a,Channel 0 Rank 0 Number of Banks Specify the number of banks of rank 0 of channel 0" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved.These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "awcl00a,Channel 0 Rank 0 Column Address Bit Width Specify the width in bits of column addresses of rank 0 of channel 0" "?,?,?,?,?,?,?,?,?,9: 9 bits,10: 10 bits,?,?,?,?,15: 15 bits Settings"
rbitfld.long 0x00 2.--7. "Reserved_2,Reserved.These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0.--1. "dw00a,Channel 0 Rank 0 Memory External Data Bus Width Specify the width of the external data bus of rank 0 of channel 0" "?,1: 16 bits,2: 32 bits Settings,?..."
group.long 0x74++0x03
line.long 0x00 "DBMEMCONF01A,Notes:1.This register must only be written from within the activation sequence (see section 33.4.1 Activation Sequence)"
bitfld.long 0x00 30.--31. "dens01a,Channel 0 Rank 1 Memory Density Type Specify the density type of the memory to be connected to rank 1 of channel 0" "0: 2^n type,1: 2^n ? 3 type Settings,?..."
rbitfld.long 0x00 29. "Reserved_29,Reserved.These bits are always read as 0" "0,1"
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bitfld.long 0x00 24.--28. "awrw01a,Channel 0 Rank 1 Row Address Bit Width Specify the width in bits of row addresses of rank 1 of channel 0" "0: 16 bits Settings other than,?,?,?,?,?,?,?,?,?,?,?,12: 12 bits 0,13: 13 bits,?..."
rbitfld.long 0x00 19.--23. "Reserved_19,Reserved.These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 16.--18. "awbk01a,Channel 0 Rank 1 Number of Banks Specify the number of banks of rank 1 of channel 0" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved.These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "awcl01a,Channel 0 Rank 1 Column Address Bit Width Specify the width in bits of column addresses of rank 1 of channel 0" "?,?,?,?,?,?,?,?,?,9: 9 bits,10: 10 bits,?,?,?,?,15: 15 bits Settings"
rbitfld.long 0x00 2.--7. "Reserved_2,Reserved.These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0.--1. "dw01a,Channel 0 Rank 1 External Data Bus Width Specify the width of the external data bus of rank 1 of channel 0" "?,1: 16 bits,2: 32 bits Settings,?..."
group.long 0x80++0x03
line.long 0x00 "DBMEMCONF10A,Notes:1.This register must only be written from within the activation sequence (see section 33.4.1 Activation Sequence)"
bitfld.long 0x00 30.--31. "dens10a,Channel 1 Rank 0 Memory Density Type Specify the density type of the memory to be connected to rank 0 of channel 1" "0: 2^n type,1: 2^n ? 3 type Settings,?..."
rbitfld.long 0x00 29. "Reserved_29,Reserved.These bits are always read as 0" "0,1"
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bitfld.long 0x00 24.--28. "awrw10a,Channel 1 Rank 0 Row Address Bit width Specify the width in bits of row addresses of rank 0 of channel 1" "0: 16 bits Settings other than,?,?,?,?,?,?,?,?,?,?,?,12: 12 bits 0,13: 13 bits,?..."
rbitfld.long 0x00 19.--23. "Reserved_19,Reserved.These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 16.--18. "awbk10a,Channel 1 Rank 0 Number of Banks Specify the number of banks of rank 0 of channel 1" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved.These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "awcl10a,Channel 1 Rank 0 Column Address Bit Width Specify the width in bits of column addresses of rank 0 of channel 1" "?,?,?,?,?,?,?,?,?,9: 9 bits,10: 10 bits,?,?,?,?,15: 15 bits Settings"
rbitfld.long 0x00 2.--7. "Reserved_2,Reserved.These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0.--1. "dw10a,Channel 1 Rank 0 Memory External Data Bus Width Specify the width of the external data bus of rank 0 of channel 1" "0,1,2,3"
group.long 0x84++0x03
line.long 0x00 "DBMEMCONF11A,Notes:1.This register must only be written from within the activation sequence (see section 33.4.1 Activation Sequence)"
bitfld.long 0x00 30.--31. "dens11a,Channel 1 Rank 1 Memory Density Type Specify the density type of the memory to be connected to rank 1 of channel 1" "0: 2^n type,1: 2^n ? 3 type Settings,?..."
rbitfld.long 0x00 29. "Reserved_29,Reserved.These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 24.--28. "awrw11a,Channel 1 Rank 1 Row Address Bit Width Specify the width in bits of row addresses of rank 1 of channel 1" "0: 16 bits Settings other than,?,?,?,?,?,?,?,?,?,?,?,12: 12 bits 0,13: 13 bits,?..."
rbitfld.long 0x00 19.--23. "Reserved_19,Reserved.These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 16.--18. "awbk11a,Channel 1 Rank 1 Number of Banks Specify the number of banks of rank 1 of channel 1" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved.These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "awcl11a,Channel 1 Rank 1 Column Address Bit Width Specify the width in bits of column addresses of rank 1 of channel 1" "?,?,?,?,?,?,?,?,?,9: 9 bits,10: 10 bits,?,?,?,?,15: 15 bits Settings"
rbitfld.long 0x00 2.--7. "Reserved_2,Reserved.These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0.--1. "dw11a,Channel 1 Rank 1 External Data Bus Width Specify the width of the external data bus of rank 1 of channel 1" "?,1: 16 bits,2: 32 bits Settings,?..."
group.long 0x100++0x03
line.long 0x00 "DBSYSCNT0,"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved.These bits are always read as 0"
hexmask.long.word 0x00 0.--15. 1. "reglock,Register Write Enable Pattern H'1234: Register write enable"
group.long 0x108++0x03
line.long 0x00 "DBSYSCNT0A,"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved.These bits are always read as 0"
hexmask.long.word 0x00 0.--15. 1. "reglocka,Register Write Enable Pattern H'1234: Register write enable"
group.long 0x200++0x03
line.long 0x00 "DBACEN,Note:This register must only be written from within the activation sequence (see section 33.4.1 Activation Sequence)"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved.These bits are always read as 0"
bitfld.long 0x00 0. "accen,SDRAM Access Enable This bit enables data access to the SDRAM" "0: Disables access to the SDRAM,1: Enables access to the SDRAM"
group.long 0x204++0x03
line.long 0x00 "DBRFEN,Note:This register must only be written from within the activation sequence (see section 33.4.1 Activation Sequence)"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved.These bits are always read as 0"
rbitfld.long 0x00 16. "Reserved_16,Reserved" "0,1"
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hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved.These bits are always read as 0"
bitfld.long 0x00 0. "arfen,Auto-Refresh Enable This bit starts or stops auto-refreshing" "0: Stops the auto-refresh function,1: Starts the auto-refresh function"
group.long 0x208++0x03
line.long 0x00 "DBCMD,Notes: 1"
hexmask.long.byte 0x00 24.--31. 1. "opc,Operation Code Specify the type of command to be issued"
bitfld.long 0x00 20.--23. "ch,Channel Specification Specify the channel to be subject to the operation" "0: Channel 0,1: Channel 1,?,?,?,?,?,?,8: All channels Settings,?..."
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rbitfld.long 0x00 19. "Reserved_19,Reserved.These bits are always read as 0" "0,1"
bitfld.long 0x00 16.--18. "rank,Rank Specification Specify the rank to be subject to the operation" "0: Rank 0,1: Rank 1,?,?,4: All ranks,?..."
newline
hexmask.long.word 0x00 0.--15. 1. "arg,Argument The meaning of these bits differs according to the operation code specified in the OPC bits"
group.long 0x210++0x03
line.long 0x00 "DBWAIT,"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved.These bits are always read as 0"
bitfld.long 0x00 0. "busy,Operation Completion Waiting Indicates whether the command specified by using the DBCMD register is currently being issued" "0: The command specified by using the DBCMD,1: The command specified by using the DBCMD"
group.long 0x300++0x03
line.long 0x00 "DBTR0,Notes:1.The setting is in cycles of the SDRAM operating clock"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved.These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "cl,CL/RL (CAS Latency/Read Latency) These bits are for setting the CAS latency of the SDRAM"
group.long 0x304++0x03
line.long 0x00 "DBTR1,Notes:1.The setting is in cycles of the SDRAM operating clock"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved.These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "cwl,CWL/WL (CAS Write Latency/Write Latency) These bits are for setting the CAS-write latency of the SDRAM"
group.long 0x308++0x03
line.long 0x00 "DBTR2,Notes:1.The setting is in cycles of the SDRAM operating clock"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved.These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "al,AL (AditiveLatency) These bits are for setting the additive latency of the SDRAM"
group.long 0x30C++0x03
line.long 0x00 "DBTR3,Notes:1.The setting is in cycles of the SDRAM operating clock"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved.These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "trcd,tRCD (ACT to internal read or write delay time/RAS-to-CAS delay) These bits set the minimum interval from an ACT command to a READ/WRITE command"
group.long 0x310++0x03
line.long 0x00 "DBTR4,Notes:1.The setting is in cycles of the SDRAM operating clock"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved.These bits are always read as 0"
hexmask.long.byte 0x00 16.--23. 1. "trpa,tRP/tRPab (PRE command period/Row precharge time (all banks)) These bits set the minimum interval from a PRE ALL (precharge all banks) command to an ACT/REF command"
newline
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved.These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "trp,tRP/tRPpb (PRE command period/Row precharge time (single bank)) These bits set the minimum interval from a PRE (precharge) command to an ACT/REF command"
group.long 0x314++0x03
line.long 0x00 "DBTR5,Notes:1.The setting is in cycles of the SDRAM operating clock"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved.These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "trc,tRC (ACT to ACT or REF command period/ACTIVATE-to-ACTIVATE command period (same bank)) These bits set the minimum interval from one ACT command to another ACT command (for the same bank) or to a REF command"
group.long 0x318++0x03
line.long 0x00 "DBTR6,Notes:1.The setting is in cycles of the SDRAM operating clock"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved.These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "tras,tRAS (ACT to PRE command period/Row active time) These bits set the minimum interval from an ACT command to a PRE command"
group.long 0x31C++0x03
line.long 0x00 "DBTR7,Notes:1.The setting is in cycles of the SDRAM operating clock"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved.These bits are always read as 0"
hexmask.long.byte 0x00 16.--23. 1. "trrd_s,tRRD (ACTIVE to ACTIVE command period/Active bank-A to active bank-B) These bits set the minimum interval between ACT commands issued for different banks"
newline
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved.These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "trrd,tRRD (ACTIVE to ACTIVE command period/Active bank-A to active bank-B) These bits set the minimum interval between ACT commands issued for different banks"
group.long 0x320++0x03
line.long 0x00 "DBTR8,Notes:1.The setting is in cycles of the SDRAM operating clock"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved.These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "tfaw,tFAW (Four activate window/Four-bank ACTIVATE window) These bits set the length of the four activate window"
group.long 0x324++0x03
line.long 0x00 "DBTR9,Notes:1.The setting is in cycles of the SDRAM operating clock"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved.These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "trdpr,tRTP/nRTP (Internal READ Command to PRECHARGE Command delay/Internal READ to PRECHARGE command delay) These bits set the minimum interval from a READ command to a PRE command"
group.long 0x328++0x03
line.long 0x00 "DBTR10,Notes: 1.The setting is in cycles of the SDRAM operating clock"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved.These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "twr,WR/nWR (WRITE recovery time) These bits set the write-recovery period"
group.long 0x32C++0x03
line.long 0x00 "DBTR11,Notes: 1.The setting is in cycles of the SDRAM operating clock"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved.These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "trdwr,Read-to-Write Interval These bits set the minimum interval from a READ command to a WRITE command"
group.long 0x330++0x03
line.long 0x00 "DBTR12,Notes: 1.The setting is in cycles of the SDRAM operating clock"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved.These bits are always read as 0"
hexmask.long.byte 0x00 16.--23. 1. "twrrd_s,Write-to-Read interval These bits set the minimum interval from a WRITE command to a READ command"
newline
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved.These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "twrrd,Write-to-Read interval These bits set the minimum interval from a WRITE command to a READ command"
group.long 0x334++0x03
line.long 0x00 "DBTR13,"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved"
hexmask.long.word 0x00 0.--15. 1. "trfc,tRFC/tRFCab (REF command to ACT or REF command time/Refresh Cycle Time (All Banks)) These bits set the minimum interval from a REF (refresh) command to an ACT/REF command for all banks"
group.long 0x338++0x03
line.long 0x00 "DBTR14,Notes:1.The setting is in cycles of the SDRAM operating clock"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved.These bits are always read as 0"
hexmask.long.byte 0x00 16.--23. 1. "tckehdll,tXPDLL (Exit Precharge Power Down with DLL frozen to commands requiring a locked DLL) These bits set the minimum interval from a PD Exit command to a further valid command that requires the DLL to be locked in"
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hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved.These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "tckeh,tXP (Exit Power Down with DLL on to any valid command Exit Precharge Power Down with DLL frozen to commands not requiring a locked DLL/Exit power- down to next valid command delay) These bits set the minimum interval from a PD Exit command to a.."
group.long 0x33C++0x03
line.long 0x00 "DBTR15,Notes:1.The setting is in cycles of the SDRAM operating clock"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved.These bits are always read as 0"
hexmask.long.byte 0x00 16.--23. 1. "tckesr,tCKESR/tSR (Minimum CKE low width for Self Refresh entry to exit timing/Minimum Self-Refresh Time (Entry to Exit)) These bits set the minimum time from the time the CKE signal goes low until it goes high in self-refresh operations"
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hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved.These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "tckel,tCKE (CKE minimum pulse width) These bits set the minimum time from the time the CKE signal goes low until it goes high in power-down operations"
group.long 0x340++0x03
line.long 0x00 "DBTR16,Notes:1.The setting is in cycles of the SDRAM operating clock"
hexmask.long.byte 0x00 24.--31. 1. "dqienltncy,dqienltncy Setting These bits set the latency from issuing of a read command to the PHY unit until the dfi_rddata_en signal is output"
hexmask.long.byte 0x00 16.--23. 1. "dql,dqltncy Setting These bits set the latency from issuing of a read command to the PHY unit until the read data is returned from the PHY unit"
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hexmask.long.byte 0x00 8.--15. 1. "dqenltncy,dqenltncy Setting These bits set the latency from issuing of a write command to the PHY unit until the dfi_wrdata_en signal is output"
hexmask.long.byte 0x00 0.--7. 1. "wdql,wdqltncy Setting These bits set the latency from issuing of a write command until the write data is output"
group.long 0x344++0x03
line.long 0x00 "DBTR17,Notes:1.The setting is in cycles of the SDRAM operating clock"
hexmask.long.byte 0x00 24.--31. 1. "tmodrd,tMRR (MODE REGISTER READ command period) These bits set the minimum interval from an MRR (mode register read) command to a next command"
hexmask.long.byte 0x00 16.--23. 1. "tmod,tMOD/tMRD (Mode Register Set command update delay/Mode register set command delay) These bits set the minimum interval from an MRS (mode register set) or MRW (mode register write) command to a next command"
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hexmask.long.word 0x00 0.--15. 1. "Reserved_0,Reserved.These bits are always read as 0"
group.long 0x348++0x03
line.long 0x00 "DBTR18,Notes:1.The setting is in cycles of the SDRAM operating clock"
rbitfld.long 0x00 27.--31. "Reserved_27,Reserved.These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 24.--26. "rodtl,ODT Assert Period Setting in Reading These bits set the assert period of the ODT signal (py_odt) that is output to the PHY unit when a read command is output" "0: BL/2 cycles,1: BL/2 + 1 cycles,?,?,?,?,?,7: BL/2 + 7 cycles"
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rbitfld.long 0x00 19.--23. "Reserved_19,Reserved.These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "rodta,ODT Assert Start Timing Setting in Reading These bits set the assert start timing for the ODT signal (py_odt) that is output to the PHY unit when a read command is output" "0: Simultaneous with the read command,1: 1 cycle after the read command,2: 2 cycles after the read command,3: 3 cycles after the read command Settings other,?..."
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rbitfld.long 0x00 11.--15. "Reserved_11,Reserved.These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "wodtl,ODT Assert Period Setting in Writing These bits set the assert period of the ODT signal (py_odt) that is output to the PHY unit when a write command is output" "0: BL/2 cycles,1: BL/2 + 1 cycles,?,?,?,?,?,7: BL/2 + 7 cycles"
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rbitfld.long 0x00 3.--7. "Reserved_3,Reserved.These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--2. "wodta,ODT Assert Start Timing Setting in Writing These bits set the assert start timing for the ODT signal (py_odt) that is output to the PHY unit when a write command is output" "0: Simultaneous with the write command,1: 1 cycle after the write command,2: 2 cycles after the write command,3: 3 cycles after the write command Settings other,?..."
group.long 0x34C++0x03
line.long 0x00 "DBTR19,Note:This register should be setting the value which provided by Renesas"
hexmask.long.word 0x00 16.--31. 1. "tzqcl,tZQoper (Normal operation Full calibration time) These bits specify the minimum interval from a ZQCL (long calibration) command to the next command"
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved.These bits are always read as 0"
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hexmask.long.byte 0x00 0.--7. 1. "tzqcs,tZQCS (Normal operation Short calibration time) These bits specify the minimum interval from a ZQCS (short calibration) command to the next command"
group.long 0x350++0x03
line.long 0x00 "DBTR20,Notes:1.The setting is in cycles of the SDRAM operating clock"
hexmask.long.word 0x00 16.--31. 1. "txsdll,tXSDLL (Exit Self Refresh to commands requiring a locked DLL) These bits set the minimum interval from an SRX command to a further valid command that requires the DLL to be locked in"
hexmask.long.word 0x00 0.--15. 1. "txs,tXS/tXSR (Exit Self Refresh to commands not requiring a locked DLL/SELF REFRESH exit to next valid command delay) These bits set the minimum interval from an SRX command to a further valid command that does not require the DLL to be locked in"
group.long 0x354++0x03
line.long 0x00 "DBTR21,Notes:1.The setting is in cycles of the SDRAM operating clock"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved.These bits are always read as 0"
hexmask.long.byte 0x00 16.--23. 1. "tccd_s,tCCD (CAS# to CAS# command delay/CAS-to-CAS delay) These bits set the minimum interval from a READ command to the next READ command or from a WRITE command to the next WRITE command issued for the same page"
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hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved.These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "tccd,tCCD (CAS# to CAS# command delay/CAS-to-CAS delay) These bits set the minimum interval from a READ command to the next READ command or from a WRITE command to the next WRITE command issued for the same page"
group.long 0x358++0x03
line.long 0x00 "DBTR22,Notes:1.The setting is in cycles of the SDRAM operating clock"
hexmask.long.word 0x00 16.--31. 1. "tzqcal,tZQCAL (ZQ calibration time) These bits specify the ZQ calibration time (tZQCAL) in cycles"
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved.These bits are always read as 0"
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hexmask.long.byte 0x00 0.--7. 1. "tzqlat,tZQLAT (ZQCAL latch quiet time) These bits specify the ZQ calibration latch time (tZQLAT) in cycles"
group.long 0x35C++0x03
line.long 0x00 "DBTR23,Notes:1.The setting is in cycles of the SDRAM operating clock"
hexmask.long 0x00 2.--31. 1. "Reserved_2,Reserved.These bits are always read as 0"
bitfld.long 0x00 0.--1. "rrspc,RD to RD Interval Limitation These bits specify RD to RD intervals that are not expected to occur" "0: No limitation (i.e all intervals >= TCCD_S may,1: (TCCD_S + 1) never occurs,2: (TCCD_S + 1) and (TCCD_S + 2) never occur,3: (TCCD_S + 1) (TCCD_S + 2) and (TCCD_S + 3).."
group.long 0x360++0x03
line.long 0x00 "DBTR24,Notes:1.The setting is in cycles of the SDRAM operating clock"
hexmask.long.byte 0x00 24.--31. 1. "rdcsgap,dfi_rddata_cs gap These bits specify the dfi_rddata_cs gap value"
hexmask.long.byte 0x00 16.--23. 1. "rdcslat,dfi_rddata_cs latency These bits specify the dfi_rddata_cs latency value"
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hexmask.long.byte 0x00 8.--15. 1. "wrcsgap,dfi_wrdata_cs gap These bits specify the dfi_wrdata_cs gap value"
hexmask.long.byte 0x00 0.--7. 1. "wrcslat,dfi_wrdata_cs latency These bits specify the dfi_wrdata_cs latency value"
group.long 0x364++0x03
line.long 0x00 "DBTR25,Notes:1.The setting is in cycles of the SDRAM operating clock"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved.These bits are always read as 0"
hexmask.long.byte 0x00 16.--23. 1. "twdqlvldis,DFI twdqlvl disable These bits specify the minimum period from last RD command to dfi_wdqlvl_en negation"
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hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved.These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "twdqlvlen,DFI twdqlvl enable"
group.long 0x368++0x03
line.long 0x00 "DBTR26,Notes:1.The setting is in cycles of the SDRAM operating clock"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved.These bits are always read as 0"
hexmask.long.word 0x00 0.--15. 1. "tdqsosc,DQS Interval Timer Run Time Setting (LPDDR4 MR23) These bits specify dQS interval timer run time setting in MR23 Register"
group.long 0x400++0x03
line.long 0x00 "DBBL,Note:This register must only be written from within the activation sequence (see section 33.4.1 Activation Sequence)"
hexmask.long 0x00 2.--31. 1. "Reserved_2,Reserved.These bits are always read as 0"
bitfld.long 0x00 0.--1. "bl,Burst Length These bits specify the burst length of SDRAM" "0: Fixed to 8,?,2: Fixed to 16 Settings other,?..."
group.long 0x404++0x03
line.long 0x00 "DBBLA,Note:This register must only be written from within the activation sequence (see section 33.4.1 Activation Sequence)"
hexmask.long 0x00 2.--31. 1. "Reserved_2,Reserved.These bits are always read as 0"
bitfld.long 0x00 0.--1. "bla,Burst Length These bits specify the burst length of SDRAM" "0: Fixed to 8,?,2: Fixed to 16 Settings other,?..."
group.long 0x414++0x03
line.long 0x00 "DBRFCNF1,Notes:1.The setting is in cycles of the SDRAM operating clock"
hexmask.long.word 0x00 16.--31. 1. "refpmax,Maximum Pulling-in Number of Refresh Commands Setting These bits set the maximum number of refresh commands (pulling-in number) accumulated by auto-refresh"
hexmask.long.word 0x00 0.--15. 1. "refint,tREFI (Average periodic refresh interval/Average Refresh Interval) These bits (This bit field) set the average interval for issuing of refresh commands"
group.long 0x418++0x03
line.long 0x00 "DBRFCNF2,Notes:1.This register must only be written from within the activation sequence (see section 33.4.1 Activation Sequence)"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved.These bits are always read as 0"
bitfld.long 0x00 16.--19. "refpmin,Minimum Pulling-in Number of Refresh Commands Setting These bits set the minimum number of refresh commands (pulling-in number) accumulated by auto-refresh" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved.These bits are always read as 0"
bitfld.long 0x00 0.--1. "refints,Average Refresh Interval Adjustment When this bit is 0 the average interval (in cycles) is the value set in the REFINT bits" "0: Average interval is REFINT,1: Average interval is 1/2 REFINT,?..."
group.long 0x424++0x03
line.long 0x00 "DBCALCNF,Notes:1.When CALINT = 0 calibration is executed (ZQCS command is issued) only once after auto-refresh executed immediately after 1 is written to the CALEN bit no calibration is executed after that"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved.These bits are always read as 0"
bitfld.long 0x00 24. "calen,SDRAM Calibration Enable While this bit is set to 1 calibration of SDRAM is executed at regular intervals" "0: SDRAM calibration is disabled,1: SDRAM calibration is enabled"
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hexmask.long.byte 0x00 17.--23. 1. "Reserved_17,Reserved.These bits are always read as 0"
rbitfld.long 0x00 16. "Reserved_16,Reserved" "0,1"
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hexmask.long.word 0x00 0.--15. 1. "calint,SDRAM Calibration Frequency These bits adjust the frequency of SDRAM calibration"
group.long 0x438++0x03
line.long 0x00 "DBRNK2,Notes:1.The setting is in cycles of the SDRAM operating clock"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved.These bits are always read as 0"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "Reserved_8,Additional Restriction on READ-READ Interval between Different Ranks for Channel 2" "0: No cycles are added to the minimum command,1: 1 cycle is added to the minimum command..,?,?,?,?,?,?,?,?,?,?,?,?,?,15: 15 cycles are added to the minimum command"
rbitfld.long 0x00 4.--7. "rkrr1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "rkrr0,Additional Restriction on READ-READ Interval between Different Ranks for Channel 0" "0: No cycles are added to the minimum command,1: 1 cycle is added to the minimum command..,?,?,?,?,?,?,?,?,?,?,?,?,?,15: 15 cycles are added to the minimum command"
group.long 0x43C++0x03
line.long 0x00 "DBRNK3,Notes:1.The setting is in cycles of the SDRAM operating clock"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved.These bits are always read as 0"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 8.--11. "Reserved_8,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "rkrw1,Additional Restriction on READ-WRITE Interval between Different Ranks for Channel 1" "0: No cycles are added to the minimum command,1: 1 cycle is added to the minimum command..,?,?,?,?,?,?,?,?,?,?,?,?,?,15: 15 cycles are added to the minimum command"
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bitfld.long 0x00 0.--3. "rkrw0,Additional Restriction on READ-WRITE Interval between Different Ranks for Channel 0" "0: No cycles are added to the minimum command,1: 1 cycle is added to the minimum command..,?,?,?,?,?,?,?,?,?,?,?,?,?,15: 15 cycles are added to the minimum command"
group.long 0x440++0x03
line.long 0x00 "DBRNK4,Notes:1.The setting is in cycles of the SDRAM operating clock"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved.These bits are always read as 0"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 8.--11. "Reserved_8,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "rkwr1,Additional Restriction on WRITE-READ Interval between Different Ranks for Channel 1" "0: No cycles are added to the minimum command,1: 1 cycle is added to the minimum command..,?,?,?,?,?,?,?,?,?,?,?,?,?,15: 15 cycles are added to the minimum command"
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bitfld.long 0x00 0.--3. "rkwr0,Additional Restriction on WRITE-READ Interval between Different Ranks for Channel 0" "0: No cycles are added to the minimum command,1: 1 cycle is added to the minimum command..,?,?,?,?,?,?,?,?,?,?,?,?,?,15: 15 cycles are added to the minimum command"
group.long 0x444++0x03
line.long 0x00 "DBRNK5,Notes:1.The setting is in cycles of the SDRAM operating clock"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved.These bits are always read as 0"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 8.--11. "Reserved_8,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "rkww1,Additional Restriction on WRITE-WRITE Interval between Different Ranks for Channel 1" "0: No cycles are added to the minimum command,1: 1 cycle is added to the minimum command..,?,?,?,?,?,?,?,?,?,?,?,?,?,15: 15 cycles are added to the minimum command"
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bitfld.long 0x00 0.--3. "rkww0,Additional Restriction on WRITE-WRITE Interval between Different Ranks for Channel 0" "0: No cycles are added to the minimum command,1: 1 cycle is added to the minimum command..,?,?,?,?,?,?,?,?,?,?,?,?,?,15: 15 cycles are added to the minimum command"
group.long 0x460++0x03
line.long 0x00 "DBODT0,"
rbitfld.long 0x00 28.--31. "Reserved_28,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 24.--27. "Reserved_24,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 20.--23. "rodtout01,ODT Output Level in Reading from Rank 1 for Channel 0 Setting These bits set the output levels of the ODT signals for each rank during reading from rank 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "rodtout00,ODT Output Level in Reading from Rank 0 for Channel 0 Setting These bits set the output levels of the ODT signals for each rank during reading from rank 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 12.--15. "Reserved_12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 8.--11. "Reserved_8,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. "wodtout01,ODT Output Level in Writing to Rank 1 for Channel 0 Setting These bits set the output levels of the ODT signals for each rank during writing to rank 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "wodtout00,ODT Output Level in Writing to Rank 0 for Channel 0 Setting These bits set the output levels of the ODT signals for each rank during writing to rank 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x464++0x03
line.long 0x00 "DBODT1,"
rbitfld.long 0x00 28.--31. "Reserved_28,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 24.--27. "Reserved_24,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 20.--23. "rodtout11,ODT Output Level in Reading from Rank 1 for Channel 1 Setting These bits set the output levels of the ODT signals for each rank during reading from rank 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "rodtout10,ODT Output Level in Reading from Rank 0 for Channel 1 Setting These bits set the output levels of the ODT signals for each rank during reading from rank 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 12.--15. "Reserved_12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 8.--11. "Reserved_8,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. "wodtout11,ODT Output Level in Writing to Rank 1 for Channel 1 Setting These bits set the output levels of the ODT signals for each rank during writing to rank 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "wodtout10,ODT Output Level in Writing to Rank 0 for Channel 1 Setting These bits set the output levels of the ODT signals for each rank during writing to rank 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x518++0x03
line.long 0x00 "DBDBICNT,Notes:1.This register must only be written from within the activation sequence (see section 33.4.1 Activation Sequence)"
hexmask.long 0x00 2.--31. 1. "Reserved_2,Reserved.These bits are always read as 0"
bitfld.long 0x00 1. "dbirden,Read DBI Setting This bit makes a setting for the read data bus inversion (DBI)" "0: Read DBI function is disabled,1: Read DBI function is enabled"
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bitfld.long 0x00 0. "dbiwren,Write DBI Setting This bit makes a setting for the write data bus inversion (DBI)" "0: Write DBI function is disabled,1: Write DBI function is enabled"
group.long 0x520++0x03
line.long 0x00 "DBDFIPMSTRCNF,Notes:1.This register must only be written from within the activation sequence (see section 33.4.1 Activation Sequence)"
hexmask.long 0x00 6.--31. 1. "Reserved_6,Reserved.These bits are always read as 0"
bitfld.long 0x00 4.--5. "wtmode,DFI PHY Master receive mode" "0,1,2,3"
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rbitfld.long 0x00 1.--3. "Reserved_1,Reserved.These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "pmstren,DFI PHY Master Control" "0,1"
group.long 0x52C++0x03
line.long 0x00 "DBDFICUPDCNF,Notes: 1.Writing this register should only be performed when the following conditions are met"
hexmask.long.byte 0x00 24.--31. 1. "cupdreqmax,Maximum of Control Update Request Assert Period These bits is specified maximum of control update request assert period"
hexmask.long.byte 0x00 16.--23. 1. "cupdreqmin,Minimum of Control Update Request Assert Period These bits is specified minimum of control update request assert period"
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hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved.These bits are always read as 0"
bitfld.long 0x00 0. "cupden,Control Update Interface Enable" "0: Disable,1: Enable"
group.long 0x600++0x03
line.long 0x00 "DBDFISTAT0,"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved.These bits are always read as 0"
bitfld.long 0x00 0. "dfiinitcompl0,DFIINITCOMPL for Channel 0" "0,1"
group.long 0x604++0x03
line.long 0x00 "DBDFICNT0,Note:This register must only be written from within the activation sequence (see section 33.4.1 Activation Sequence)"
rbitfld.long 0x00 29.--31. "Reserved_29,Reserved.These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24.--28. "dfifrequency0,FREQUENCY for Channel 0 The value of these bits is output as the dfi_frequency signal of DFI status interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x00 16.--23. 1. "dfibytedis0,BYTEDIS for Channel 0 The value of these bits is output as the dfi_data_byte_disable signal of DFI status interface"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved.These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "dficlkdis0,CLKDIS for Channel 0 The value of these bits is output as the dfi_dram_clk_disable signal of DFI status interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 6.--7. "Reserved_6,Reserved.These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 4.--5. "dfifreqratio0,FREQRATIO for Channel 0 The value of these bits is output as the dfi_freq_ratio signal of DFI status interface" "0,1,2,3"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved.These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0. "dfiinitstart0,INITSTART for Channel 0 The value of these bits is output as the dfi_init_start signal of DFI status interface" "0,1"
group.long 0x610++0x03
line.long 0x00 "DBPDCNT00,Notes: 1.This register must only be written from within the activation sequence (see section 33.4.1 Activation Sequence)"
hexmask.long 0x00 0.--31. 1. "cntreg00,DDR-PHY Control Signals 0 for Channel 0"
group.long 0x614++0x03
line.long 0x00 "DBPDCNT01,Notes: 1.This register must only be written from within the activation sequence (see section 33.4.1 Activation Sequence)"
hexmask.long 0x00 0.--31. 1. "cntreg01,DDR-PHY Control Signals 1 for Channel 0"
group.long 0x618++0x03
line.long 0x00 "DBPDCNT02,Notes: 1.This register must only be written from within the activation sequence (see section 33.4.1 Activation Sequence)"
hexmask.long 0x00 0.--31. 1. "cntreg02,DDR-PHY Control Signals 2 for Channel 0"
group.long 0x61C++0x03
line.long 0x00 "DBPDCNT03,Notes: 1.This register must only be written from within the activation sequence (see section 33.4.1 Activation Sequence)"
hexmask.long 0x00 0.--31. 1. "cntreg03,DDR-PHY Control Signals 3 for Channel 0"
group.long 0x620++0x03
line.long 0x00 "DBPDLK0,Note:This register must only be written from within the activation sequence (see section 33.4.1 Activation Sequence)"
hexmask.long 0x00 0.--31. 1. "plock0,PHY Unit Access Lock Setting for Channel 0 Setting this register to H'0000 A55A allows access to the PHY unit register"
group.long 0x624++0x03
line.long 0x00 "DBPDRGA0,Note:This register must only be written from within the activation sequence (see section 33.4.1 Activation Sequence)"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved.These bits are always read as 0"
abitfld.long 0x00 0.--15. "pra0,PHY Unit Register Address for Channel 0 [Other than R-Car V3H and R-Car M3-N] PRA0[15:0]: PHY Unit Register Address for Channel 0 The address set in this register is used in access (for setting or referring to values) to the internal registers of.." "0x0000=0: Incomplete,0x0001=1: Complete (Read) Clear"
group.long 0x628++0x03
line.long 0x00 "DBPDRGD0,Note:This register must only be written from within the activation sequence (see section 33.4.1 Activation Sequence)"
hexmask.long 0x00 0.--31. 1. "prd0,PHY Unit Registers Access for channel 0 The values in registers of the PHY0 unit are readable and writable"
group.long 0x630++0x03
line.long 0x00 "DBPDSTAT00,"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved.These bits are always read as 0"
rbitfld.long 0x00 8.--12. "freqchgreqtype0,Frequency change request type for DDR-PHY Channel 0 This bit field is used to monitor the freq_change_req_type signal from DDR-PHY Channel 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x00 1.--7. 1. "Reserved_1,Reserved.These bits are always read as 0"
rbitfld.long 0x00 0. "freqchgreq0,Frequency change request for DDR-PHY Channel 0 This bit field is used to monitor the freq_change_req signal from DDR-PHY Channel 0" "0,1"
group.long 0x634++0x03
line.long 0x00 "DBPDSTAT01,"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved.These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "cntstat01,This register is reflected py_statreg0[7:0] signal"
group.long 0x640++0x03
line.long 0x00 "DBDFISTAT1,"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved.These bits are always read as 0"
bitfld.long 0x00 0. "dfiinitcompl1,DFIINITCOMPL for Channel 1" "0,1"
group.long 0x644++0x03
line.long 0x00 "DBDFICNT1,Note:This register must only be written from within the activation sequence (see section 33.4.1 Activation Sequence)"
rbitfld.long 0x00 29.--31. "Reserved_29,Reserved.These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24.--28. "dfifrequency1,FREQUENCY for Channel 1 The value of these bits is output as the dfi_frequency signal of DFI status interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x00 16.--23. 1. "dfibytedis1,BYTEDIS for Channel 1 The value of these bits is output as the dfi_data_byte_disable signal of DFI status interface"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved.These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "dficlkdis1,CLKDIS for Channel 1 The value of these bits is output as the dfi_dram_clk_disable signal of DFI status interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 6.--7. "Reserved_6,Reserved.These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 4.--5. "dfifreqratio1,FREQRATIO for Channel 1 The value of these bits is output as the dfi_freq_ratio signal of DFI status interface" "0,1,2,3"
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved.These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0. "dfiinitstart1,INITSTART for Channel 1 The value of these bits is output as the dfi_init_start signal of DFI status interface" "0,1"
group.long 0x650++0x03
line.long 0x00 "DBPDCNT10,Notes: 1.This register must only be written from within the activation sequence (see section 33.4.1 Activation Sequence)"
hexmask.long 0x00 0.--31. 1. "cntreg10,DDR-PHY Control Signals 0 for Channel 1"
group.long 0x654++0x03
line.long 0x00 "DBPDCNT11,Notes: 1.This register must only be written from within the activation sequence (see section 33.4.1 Activation Sequence)"
hexmask.long 0x00 0.--31. 1. "cntreg11,DDR-PHY Control Signals 1 for Channel 1"
group.long 0x658++0x03
line.long 0x00 "DBPDCNT12,Notes: 1.This register must only be written from within the activation sequence (see section 33.4.1 Activation Sequence)"
hexmask.long 0x00 0.--31. 1. "cntreg12,DDR-PHY Control Signals 2 for Channel 1"
group.long 0x65C++0x03
line.long 0x00 "DBPDCNT13,Notes: 1.This register must only be written from within the activation sequence (see section 33.4.1 Activation Sequence)"
hexmask.long 0x00 0.--31. 1. "cntreg13,DDR-PHY Control Signals 3 for Channel 1"
group.long 0x660++0x03
line.long 0x00 "DBPDLK1,Note:This register must only be written from within the activation sequence (see section 33.4.1 Activation Sequence)"
hexmask.long 0x00 0.--31. 1. "plock1,PHY Unit Access Lock Setting for Channel 1 Setting this register to H'0000 A55A allows access to the PHY unit register"
group.long 0x664++0x03
line.long 0x00 "DBPDRGA1,Note:This register must only be written from within the activation sequence (see section 33.4.1 Activation Sequence)"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved.These bits are always read as 0"
hexmask.long.word 0x00 0.--15. 1. "pra1,PHY Unit Register Address for Channel 1 The address set in this register is used in access (for setting or referring to values) to the internal registers of the PHY unit"
group.long 0x668++0x03
line.long 0x00 "DBPDRGD1,Note:This register must only be written from within the activation sequence (see section 33.4.1 Activation Sequence)"
hexmask.long 0x00 0.--31. 1. "prd1,PHY Unit Registers Access for channel 1 The values in registers of the PHY1 unit are readable and writable"
group.long 0x670++0x03
line.long 0x00 "DBPDSTAT10,"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved.These bits are always read as 0"
rbitfld.long 0x00 8.--12. "freqchgreqtype1,Frequency change request type for DDR-PHY Channel 1 This bit field is used to monitor the freq_change_req_type signal from DDR-PHY Channel 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x00 1.--7. 1. "Reserved_1,Reserved.These bits are always read as 0"
rbitfld.long 0x00 0. "freqchgreq1,Frequency change request for DDR-PHY Channel 1 This bit field is used to monitor the freq_change_req signal from DDR-PHY Channel 1" "0,1"
group.long 0x674++0x03
line.long 0x00 "DBPDSTAT11,"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved.These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "cntstat11,This register is reflected py_statre1[7:0] signal"
group.long 0x804++0x03
line.long 0x00 "DBBUS0CNF1,Note:This register must only be written from within the activation sequence (see section 33.4.1 Activation Sequence)"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved.These bits are always read as 0"
rbitfld.long 0x00 8.--13. "Reserved_8,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 2.--7. "bkadp,Bank Interleave Mode Setting" "0: 256byte boundary,1: 512byte boundary,?,?,?,?,?,?,?,?,10: 1Kbyte boundary,11: 2Kbyte boundary This bit field should be,?..."
bitfld.long 0x00 0.--1. "bkadm,Bank Address Mode These bits are used to set the method for assigning the SDRAM banks to the logical address space i.e" "0: The whole logical address space is regarded as,1: Setting prohibited,2: Setting prohibited,3: One for bank 0 one for bank 1 one for banks 2"
group.long 0x904++0x03
line.long 0x00 "DBCAM0CNF1,Notes: 1.This register must only be written from within the activation sequence (see section 33.4.1 Activation Sequence)"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved.These bits are always read as 0"
hexmask.long.byte 0x00 16.--23. 1. "wbkwait,Writeback Wait Set H'4 on these bits"
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bitfld.long 0x00 12.--15. "swpinpri3,Swap-In Priority Threshold 3 Restriction: SWPINPRI3 > SWPINPRI2 > SWPINPRI1 > 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "swpinpri2,Swap-In Priority Threshold 2 Restriction: SWPINPRI3 > SWPINPRI2 > SWPINPRI1 > 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. "swpinpri1,Swap-In Priority Threshold 1 Restriction: SWPINPRI3 > SWPINPRI2 > SWPINPRI1 > 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "swpinpri1f,Swap-In Priority Threshold 1F Set H'8 on these bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x908++0x03
line.long 0x00 "DBCAM0CNF2,Notes: 1.This register must only be written from within the activation sequence (see section 33.4.1 Activation Sequence)"
hexmask.long.tbyte 0x00 10.--31. 1. "Reserved_10,Reserved.These bits are always read as 0"
bitfld.long 0x00 8.--9. "fillunit,Read Fill Minimum Size These bits set the minimum size of the read request to SDRAM" "0: 64 bytes,1: 128 bytes,2: 256 bytes,?..."
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bitfld.long 0x00 4.--7. "fcdirtymax,Swap-In Threshold Restriction: FCDIRTYMIN < FCDIRTYMAX Set H'F on these bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "fcdirtymin,Swap-Out Threshold Restriction: FCDIRTYMIN < FCDIRTYMAX Set H'4 on these bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x90C++0x03
line.long 0x00 "DBCAM0CNF3,Notes: 1.This register must only be written from within the activation sequence (see section 33.4.1 Activation Sequence)"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved.These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "rdfull,Read Queue Full Threshold setting Set H'00 on these bits"
group.long 0x940++0x03
line.long 0x00 "DBCAM0CTRL0,"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved.These bits are always read as 0"
bitfld.long 0x00 0. "camflush,CAM Flush This bit is set to flush dirty cache data to DDR memory" "0: No flush,1: Flush"
group.long 0x980++0x03
line.long 0x00 "DBCAM0STAT0,"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved.These bits are always read as 0"
bitfld.long 0x00 0. "camempty0,CAM0 Empty This bit indicates whether data exists in cache 0 (CAM0)" "0: Data exists in cache 0,1: Data is empty in cache 0 Writing to these bits"
group.long 0x9FC++0x03
line.long 0x00 "DBBCAMDIS,Notes:1.This register must only be written from within the activation sequence (see section 33.4.1 Activation Sequence)"
hexmask.long 0x00 6.--31. 1. "Reserved_6,Reserved.These bits are always read as 0"
rbitfld.long 0x00 5. "Reserved_5,Reserved" "0,1"
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rbitfld.long 0x00 4. "Reserved_4,Reserved" "0,1"
rbitfld.long 0x00 3. "Reserved_3,Reserved" "0,1"
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rbitfld.long 0x00 2. "allocmd,Reserved" "0,1"
bitfld.long 0x00 1. "scamdis,SubCAM Disable" "0: enable,1: disable"
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bitfld.long 0x00 0. "resrdis,Response Right Disable" "0: Control of the response right is enabled,1: Control of the response right is disabled"
group.long 0x1000++0x03
line.long 0x00 "DBSCHCNT0,Notes:1.This register must only be written from within the activation sequence (see section 33.4.1 Activation Sequence)"
rbitfld.long 0x00 26.--31. "Reserved_26,Reserved.These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 24.--25. "scqosckps,Prescaler Setting for QoS counter" "0,1,2,3"
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rbitfld.long 0x00 20.--23. "Reserved_20,Reserved.These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "scqtzen,Quantization Bit Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x00 6.--15. 1. "Reserved_6,Reserved.These bits are always read as 0"
bitfld.long 0x00 5. "scszen,Burst Size Based Scheduling Enable" "0,1"
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bitfld.long 0x00 4. "scbaen,Bank Miss Based Scheduling Enable" "0,1"
rbitfld.long 0x00 3. "Reserved_3,Reserved" "0,1"
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bitfld.long 0x00 2. "scpgen,Page Hit Based Scheduling Enable" "0,1"
bitfld.long 0x00 1. "scrwen,Read/Write Based Scheduling Enable" "0,1"
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bitfld.long 0x00 0. "scqosen,QoS Level Based Scheduling Enable" "0,1"
group.long 0x1004++0x03
line.long 0x00 "DBSCHCNT1,Notes:1.This register must only be written from within the activation sequence (see section 33.4.1 Activation Sequence)"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved.These bits are always read as 0"
rbitfld.long 0x00 12.--15. "Reserved_12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 8.--11. "Reserved_8,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "schch1,Channel Number for Physical Channel 1 Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "schch0,Channel Number for Physical Channel 0 Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1010++0x03
line.long 0x00 "DBSCHSZ0,Notes:This register must only be written from within the activation sequence (see section 33.4.1 Activation Sequence)"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved.These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "szth,Size Miss Threshold Setting"
group.long 0x1020++0x03
line.long 0x00 "DBSCHRW0,Notes:This register must only be written from within the activation sequence (see section 33.4.1 Activation Sequence)"
bitfld.long 0x00 28.--31. "rdstptol3,Stop Tolerance for Read Period on Quantization Leve 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "rdstptol2,Stop Tolerance for Read Period on Quantization Leve 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 20.--23. "rdstptol1,Stop Tolerance for Read Period on Quantization Leve 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "rdstptol0,Stop Tolerance for Read Period on Quantization Leve 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12.--15. "wrstptol3,Stop Tolerance for Write Period on Quantization Leve 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "wrstptol2,Stop Tolerance for Write Period on Quantization Leve 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. "wrstptol1,Stop Tolerance for Write Period on Quantization Leve 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "wrstptol0,Stop Tolerance for Write Period on Quantization Leve 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1024++0x03
line.long 0x00 "DBSCHRW1,Notes:This register must only be written from within the activation sequence (see section 33.4.1 Activation Sequence)"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved.These bits are always read as 0"
hexmask.long.byte 0x00 16.--23. 1. "scbadec,Reserved"
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hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved"
hexmask.long.byte 0x00 0.--7. 1. "sctrfcab,REF to ACT/REF for All Banks Interval Setting for scheduler These bits set the minimum interval from a REF (refresh) command to an ACT/REF command for all banks"
group.long 0x1030++0x03
line.long 0x00 "DBSCHQOS00,Notes:1.Notes:This register must only be written from within the activation sequence (see section 33.4.1 Activation Sequence)"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved.These bits are always read as 0"
hexmask.long.word 0x00 0.--15. 1. "qos0ini,QoS Level 0 Counter Initial Value Setting"
group.long 0x1034++0x03
line.long 0x00 "DBSCHQOS01,Notes:1.Notes:This register must only be written from within the activation sequence (see section 33.4.1 Activation Sequence)"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved.These bits are always read as 0"
hexmask.long.word 0x00 0.--15. 1. "qos0th0,QoS Level 0 Threshold 0 Setting"
group.long 0x1038++0x03
line.long 0x00 "DBSCHQOS02,Notes:1.Notes:This register must only be written from within the activation sequence (see section 33.4.1 Activation Sequence)"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved.These bits are always read as 0"
hexmask.long.word 0x00 0.--15. 1. "qos0th1,QoS Level 0 Threshold 1 Setting"
group.long 0x103C++0x03
line.long 0x00 "DBSCHQOS03,Notes:1.Notes:This register must only be written from within the activation sequence (see section 33.4.1 Activation Sequence)"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved.These bits are always read as 0"
hexmask.long.word 0x00 0.--15. 1. "qos0th2,QoS Level 0 Threshold 2 Setting"
group.long 0x1070++0x03
line.long 0x00 "DBSCHQOS40,Notes:1:This register must only be written from within the activation sequence (see section 33.4.1 Activation Sequence)"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved.These bits are always read as 0"
hexmask.long.word 0x00 0.--15. 1. "qos4ini,QoS Level 4 Counter Initial Value Setting"
group.long 0x1074++0x03
line.long 0x00 "DBSCHQOS41,Notes:1.This register must only be written from within the activation sequence (see section 33.4.1 Activation Sequence)"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved.These bits are always read as 0"
hexmask.long.word 0x00 0.--15. 1. "qos4th0,QoS Level 4 Threshold 0 Setting"
group.long 0x1078++0x03
line.long 0x00 "DBSCHQOS42,Notes:1.This register must only be written from within the activation sequence (see section 33.4.1 Activation Sequence)"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved.These bits are always read as 0"
hexmask.long.word 0x00 0.--15. 1. "qos4th1,QoS Level 4 Threshold 1 Setting"
group.long 0x107C++0x03
line.long 0x00 "DBSCHQOS43,Notes:1.This register must only be written from within the activation sequence (see section 33.4.1 Activation Sequence)"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved.These bits are always read as 0"
hexmask.long.word 0x00 0.--15. 1. "qos4th2,QoS Level 4 Threshold 2 Setting"
group.long 0x10C0++0x03
line.long 0x00 "DBSCHQOS90,Notes:1.This register must only be written from within the activation sequence (see section 33.4.1 Activation Sequence)"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved.These bits are always read as 0"
hexmask.long.word 0x00 0.--15. 1. "qos9ini,QoS Level 9 Counter Initial Value Setting"
group.long 0x10C4++0x03
line.long 0x00 "DBSCHQOS91,Notes:1.This register must only be written from within the activation sequence (see section 33.4.1 Activation Sequence)"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved.These bits are always read as 0"
hexmask.long.word 0x00 0.--15. 1. "qos9th0,QoS Level 9 Threshold 0 Setting"
group.long 0x10C8++0x03
line.long 0x00 "DBSCHQOS92,Notes:1.This register must only be written from within the activation sequence (see section 33.4.1 Activation Sequence)"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved.These bits are always read as 0"
hexmask.long.word 0x00 0.--15. 1. "qos9th1,QoS Level 9 Threshold 1 Setting"
group.long 0x10CC++0x03
line.long 0x00 "DBSCHQOS93,Notes:1.This register must only be written from within the activation sequence (see section 33.4.1 Activation Sequence)"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved.These bits are always read as 0"
hexmask.long.word 0x00 0.--15. 1. "qos9th2,QoS Level 9 Threshold 2 Setting"
group.long 0x10F0++0x03
line.long 0x00 "DBSCHQOS120,Notes:1.This register must only be written from within the activation sequence (see section 33.4.1 Activation Sequence)"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved.These bits are always read as 0"
hexmask.long.word 0x00 0.--15. 1. "qos12ini,QoS Level 12 Counter Initial Value Setting"
group.long 0x10F4++0x03
line.long 0x00 "DBSCHQOS121,Notes:1.This register must only be written from within the activation sequence (see section 33.4.1 Activation Sequence)"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved.These bits are always read as 0"
hexmask.long.word 0x00 0.--15. 1. "qos12th0,QoS Level 12 Threshold 0 Setting"
group.long 0x10F8++0x03
line.long 0x00 "DBSCHQOS122,Notes:1.This register must only be written from within the activation sequence (see section 33.4.1 Activation Sequence)"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved.These bits are always read as 0"
hexmask.long.word 0x00 0.--15. 1. "qos12th1,QoS Level 12 Threshold 1 Setting"
group.long 0x10FC++0x03
line.long 0x00 "DBSCHQOS123,Notes:1.This register must only be written from within the activation sequence (see section 33.4.1 Activation Sequence)"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved.These bits are always read as 0"
hexmask.long.word 0x00 0.--15. 1. "qos12th2,QoS Level 12 Threshold 2 Setting"
group.long 0x1100++0x03
line.long 0x00 "DBSCHQOS130,Notes:1.This register must only be written from within the activation sequence (see section 33.4.1 Activation Sequence)"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved.These bits are always read as 0"
hexmask.long.word 0x00 0.--15. 1. "qos13ini,QoS Level 13 Counter Initial Value Setting"
group.long 0x1104++0x03
line.long 0x00 "DBSCHQOS131,Notes:1.This register must only be written from within the activation sequence (see section 33.4.1 Activation Sequence)"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved.These bits are always read as 0"
hexmask.long.word 0x00 0.--15. 1. "qos13th0,QoS Level 13 Threshold 0 Setting"
group.long 0x1108++0x03
line.long 0x00 "DBSCHQOS132,Notes:1.This register must only be written from within the activation sequence (see section 33.4.1 Activation Sequence)"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved.These bits are always read as 0"
hexmask.long.word 0x00 0.--15. 1. "qos13th1,QoS Level 13 Threshold 1 Setting"
group.long 0x110C++0x03
line.long 0x00 "DBSCHQOS133,Notes:1.This register must only be written from within the activation sequence (see section 33.4.1 Activation Sequence)"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved.These bits are always read as 0"
hexmask.long.word 0x00 0.--15. 1. "qos13th2,QoS Level 13 Threshold 2 Setting"
group.long 0x1110++0x03
line.long 0x00 "DBSCHQOS140,Notes:1.This register must only be written from within the activation sequence (see section 33.4.1 Activation Sequence)"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved.These bits are always read as 0"
hexmask.long.word 0x00 0.--15. 1. "qos14ini,QoS Level 14 Counter Initial Value Setting"
group.long 0x1114++0x03
line.long 0x00 "DBSCHQOS141,Notes:1.This register must only be written from within the activation sequence (see section 33.4.1 Activation Sequence)"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved.These bits are always read as 0"
hexmask.long.word 0x00 0.--15. 1. "qos14th0,QoS Level 14 Threshold 0 Setting"
group.long 0x1118++0x03
line.long 0x00 "DBSCHQOS142,Notes:1.This register must only be written from within the activation sequence (see section 33.4.1 Activation Sequence)"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved.These bits are always read as 0"
hexmask.long.word 0x00 0.--15. 1. "qos14th1,QoS Level 14 Threshold 1 Setting"
group.long 0x111C++0x03
line.long 0x00 "DBSCHQOS143,Notes:1.This register must only be written from within the activation sequence (see section 33.4.1 Activation Sequence)"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved.These bits are always read as 0"
hexmask.long.word 0x00 0.--15. 1. "qos14th2,QoS Level 14 Threshold 2 Setting"
group.long 0x1120++0x03
line.long 0x00 "DBSCHQOS150,Notes:1.This register must only be written from within the activation sequence (see section 33.4.1 Activation Sequence)"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved.These bits are always read as 0"
hexmask.long.word 0x00 0.--15. 1. "qos15ini,QoS Level 15 Counter Initial Value Setting"
group.long 0x1124++0x03
line.long 0x00 "DBSCHQOS151,Notes:1.This register must only be written from within the activation sequence (see section 33.4.1 Activation Sequence)"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved.These bits are always read as 0"
hexmask.long.word 0x00 0.--15. 1. "qos15th0,QoS Level 15 Threshold 0 Setting"
group.long 0x1128++0x03
line.long 0x00 "DBSCHQOS152,Notes:1.This register must only be written from within the activation sequence (see section 33.4.1 Activation Sequence)"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved.These bits are always read as 0"
hexmask.long.word 0x00 0.--15. 1. "qos15th1,QoS Level 15 Threshold 1 Setting"
group.long 0x112C++0x03
line.long 0x00 "DBSCHQOS153,Notes:1.This register must only be written from within the activation sequence (see section 33.4.1 Activation Sequence)"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved.These bits are always read as 0"
hexmask.long.word 0x00 0.--15. 1. "qos15th2,QoS Level 15 Threshold 2 Setting"
group.long 0x1700++0x03
line.long 0x00 "DBSCHFCTST0,Note:This register must only be written from within the activation sequence (see section 33.4.1 Activation Sequence)"
hexmask.long.byte 0x00 24.--31. 1. "scactact,ACT to ACT Interval Setting for scheduler These bits set the interval cycles from ACT command to ACT command (DBTR5:TRC) in SDRAM"
hexmask.long.byte 0x00 16.--23. 1. "scrdact,RD to ACT Interval Setting for scheduler These bits set the interval cycles from RD command to ACT command (DBTR9:TRDPR + DBTR4:TRP) in SDRAM"
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hexmask.long.byte 0x00 8.--15. 1. "scwract,WR to ACT Interval Setting for scheduler These bits set the interval cycles from WR command to ACT command ([LPDDR4] DBTR1:CWL + 8 + 1 + DBTR10:TWR + DBTR4:TRP [DDR3] DBTR1:CWL +4 + DBTR10:TWR + DBTR4:TRP) in SDRAM"
hexmask.long.byte 0x00 0.--7. 1. "scpreact,PRE to ACT Interval Setting for scheduler These bits set the interval cycles from PRE command to ACT command (DBTR4:TRP) in SDRAM"
group.long 0x1708++0x03
line.long 0x00 "DBSCHFCTST1,Note:This register must only be written from within the activation sequence (see section 33.4.1 Activation Sequence)"
hexmask.long.byte 0x00 24.--31. 1. "scrdwr,RD to WR Interval Setting for scheduler These bits set the interval cycles from RD command to WR command (DBTR11:TRDWR) in SDRAM"
hexmask.long.byte 0x00 16.--23. 1. "scwrrd,WR to RD Interval Setting for scheduler These bits set the interval cycles from WR command to RD command (DBTR12:TWRRD) in SDRAM"
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hexmask.long.byte 0x00 8.--15. 1. "scactrdwr,ACT to RD/WR Interval Setting for scheduler These bits set the interval cycles from ACT command to RD/WR command (DBTR3:TRCD) in SDRAM"
hexmask.long.byte 0x00 0.--7. 1. "scasyncofs,Asynchronous stage offset Setting This bit field should be set the value which provided by Renesas"
group.long 0x170C++0x03
line.long 0x00 "DBSCHFCTST2,Notes: 1.This register must only be written from within the activation sequence (see section 33.4.1 Activation Sequence)"
bitfld.long 0x00 28.--31. "wrperi3,Write Priority Period setting on Quantization Level 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "wrperi2,Write Priority Period setting on Quantization Level 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 20.--23. "wrperi1,Write Priority Period setting on Quantization Level 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "wrperi0,Write Priority Period setting on Quantization Level 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12.--15. "rdperi3,Read Priority Period setting on Quantization Level 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "rdperi2,Read Priority Period setting on Quantization Level 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. "rdperi1,Read Priority Period setting on Quantization Level 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "rdperi0,Read Priority Period setting on Quantization Level 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1710++0x03
line.long 0x00 "DBSCHTR0,Notes:1.This register must only be written from within the activation sequence (see section 33.4.1 Activation Sequence)"
hexmask.long.byte 0x00 24.--31. 1. "scdt3,Data Transfer Cycle Setting for 256 Bytes Data"
hexmask.long.byte 0x00 16.--23. 1. "scdt2,Data Transfer Cycle Setting for 192 Bytes Data"
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hexmask.long.byte 0x00 8.--15. 1. "scdt1,Data Transfer Cycle Setting for 128 Bytes Data"
hexmask.long.byte 0x00 0.--7. 1. "scdt0,Data Transfer Cycle Setting for 64 Bytes Data"
group.long 0x1800++0x03
line.long 0x00 "DBMRRDR0,Note:This register is applicable only for LPDDR4 SDRAM"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved.These bits are always read as 0"
hexmask.long.byte 0x00 8.--15. 1. "mrrdr01,MRR Read Data for Channel 0/A/Rank 1 These bits reflect the values of the OP bits read by the most recently issued MRR command for rank 1 of memory channel 0/A by using the manual command-issuing register"
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hexmask.long.byte 0x00 0.--7. 1. "mrrdr00,MRR Read Data for Channel 0/A/Rank 0 These bits reflect the values of the OP bits read by the most recently issued MRR command for rank 0 of memory channel 0/A by using the manual command-issuing register"
group.long 0x1804++0x03
line.long 0x00 "DBMRRDR1,Note:This register is applicable only for LPDDR4 SDRAM"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved.These bits are always read as 0"
hexmask.long.byte 0x00 8.--15. 1. "mrrdr11,MRR Read Data for Channel 0/B/Rank 1 These bits reflect the values of the OP bits read by the most recently issued MRR command for rank 1 of memory channel 0/B by using the manual command-issuing register"
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hexmask.long.byte 0x00 0.--7. 1. "mrrdr10,MRR Read Data for Channel 0/B/Rank 0 These bits reflect the values of the OP bits read by the most recently issued MRR command for rank 0 of memory channel 0/B by using the manual command-issuing register"
group.long 0x1820++0x03
line.long 0x00 "DBDTMP0,"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.byte 0x00 16.--23. 1. "Reserved_16,Reserved"
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hexmask.long.byte 0x00 8.--15. 1. "dtmp01,Ch.0/Rank1 MRR temperature data"
hexmask.long.byte 0x00 0.--7. 1. "dtmp00,Ch.0/Rank0MRR temperature data"
group.long 0x1824++0x03
line.long 0x00 "DBDTMP1,"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.byte 0x00 16.--23. 1. "Reserved_16,Reserved"
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hexmask.long.byte 0x00 8.--15. 1. "dtmp11,Ch.1/Rank1 MRR temperature data"
hexmask.long.byte 0x00 0.--7. 1. "dtmp10,Ch.1/Rank0MRR temperature data"
group.long 0x1840++0x03
line.long 0x00 "DBDQSOSC00,Notes:1.To access this register only read from the register while access to SDRAM is disabled (i.e. the ACCEN bit in the DBACEN register is 0)"
hexmask.long.word 0x00 16.--31. 1. "dqsosc01,Ch.0/Rank1 MRR dqs osc read data"
hexmask.long.word 0x00 0.--15. 1. "dqsosc00,Ch.0/Rank0 MRR dqs osc read data"
group.long 0x1848++0x03
line.long 0x00 "DBDQSOSC10,Notes:1.To access this register only read from the register while access to SDRAM is disabled (i.e. the ACCEN bit in the DBACEN register is 0)"
hexmask.long.word 0x00 16.--31. 1. "dqsosc11,Ch.1/Rank1 MRR dqs osc read data"
hexmask.long.word 0x00 0.--15. 1. "dqsosc10,Ch.1/Rank0 MRR dqs osc read data"
group.long 0x1880++0x03
line.long 0x00 "DBOSCTHH00,Notes:1.This register must only be written from within the activation sequence (see section 33.4.1 Activation Sequence)"
hexmask.long.word 0x00 16.--31. 1. "oscthh01,Ch.0/Rank1 dqs osc threshhold(High)"
hexmask.long.word 0x00 0.--15. 1. "oscthh00,Ch.0/Rank0 dqs osc threshhold(High)"
group.long 0x1888++0x03
line.long 0x00 "DBOSCTHH10,Notes:1.This register must only be written from within the activation sequence (see section 33.4.1 Activation Sequence)"
hexmask.long.word 0x00 16.--31. 1. "oscthh11,Ch.1/Rank1 dqs osc threshhold(High)"
hexmask.long.word 0x00 0.--15. 1. "oscthh10,Ch.1/Rank0 dqs osc threshhold(High)"
group.long 0x18C0++0x03
line.long 0x00 "DBOSCTHL00,Notes:1.This register must only be written from within the activation sequence (see section 33.4.1 Activation Sequence)"
hexmask.long.word 0x00 16.--31. 1. "oscthl01,Ch.0/Rank1 dqs osc threshhold(Low)"
hexmask.long.word 0x00 0.--15. 1. "oscthl00,Ch.0/Rank0 dqs osc threshhold(Low)"
group.long 0x18C8++0x03
line.long 0x00 "DBOSCTHL10,Notes:1.This register must only be written from within the activation sequence (see section 33.4.1 Activation Sequence)"
hexmask.long.word 0x00 16.--31. 1. "oscthl11,Ch.1/Rank1 dqs osc threshhold(Low)"
hexmask.long.word 0x00 0.--15. 1. "oscthl10,Ch.1/Rank0 dqs osc threshhold(Low)"
group.long 0x7000++0x03
line.long 0x00 "DBFSINTXXX00A,"
bitfld.long 0x00 31. "intexdclaxa,Comparator error of DCLS for clk_axi group Interrupt indication" "0,1"
bitfld.long 0x00 30. "intexdclsra,Comparator error of DCLS group sram interrupt indication" "0,1"
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hexmask.long.tbyte 0x00 11.--29. 1. "Reserved_11,Reserved.These bits are always read as 0"
bitfld.long 0x00 10. "intodasbda,OrderID error in AXI64 Bch clk_dbs side Interrupt indication" "0,1"
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bitfld.long 0x00 9. "intodasrda,OrderID error in AXI64 Rch clk_dbs side Interrupt indication" "0,1"
bitfld.long 0x00 8. "intodasbxa,OrderID error in AXI64 Bch clk_axi side Interrupt indication" "0,1"
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bitfld.long 0x00 7. "intodasrxa,OrderID error in AXI64 Rch clk_axi side Interrupt indication" "0,1"
bitfld.long 0x00 6. "intodaswxa,OrderID error in AXI64 Wch clk_axi side Interrupt indication" "0,1"
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bitfld.long 0x00 5. "intodasawa,OrderID error in AXI64 AWch clk_axi side Interrupt indication" "0,1"
bitfld.long 0x00 4. "intodasara,OrderID error in AXI64 ARch clk_axi side Interrupt indication" "0,1"
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rbitfld.long 0x00 3. "Reserved_3,Reserved.These bits are always read as 0" "0,1"
bitfld.long 0x00 2. "intdxaswxa,EDC error in AXSM W Ch clk_axi domain Interrupt indication" "0,1"
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bitfld.long 0x00 1. "intdxasawa,EDC error in AXSM AW Ch clk_axi domain Interrupt indication" "0,1"
bitfld.long 0x00 0. "intdxasara,EDC error in AXSM AR Ch clk_axi domain Interrupt indication" "0,1"
group.long 0x7004++0x03
line.long 0x00 "DBFSINTXXX01A,"
hexmask.long.word 0x00 23.--31. 1. "Reserved_23,Reserved.These bits are always read as 0"
rbitfld.long 0x00 22. "Reserved_22,Reserved" "0,1"
newline
rbitfld.long 0x00 21. "Reserved_21,Reserved" "0,1"
rbitfld.long 0x00 20. "Reserved_20,Reserved" "0,1"
newline
rbitfld.long 0x00 19. "Reserved_19,Reserved" "0,1"
rbitfld.long 0x00 18. "Reserved_18,Reserved" "0,1"
newline
rbitfld.long 0x00 17. "Reserved_17,Reserved" "0,1"
rbitfld.long 0x00 16. "Reserved_16,Reserved" "0,1"
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hexmask.long.word 0x00 7.--15. 1. "Reserved_7,Reserved.These bits are always read as 0"
bitfld.long 0x00 6. "intnomem0a,No mem error in address decoder of dbsccore0 interrupt indication" "0,1"
newline
bitfld.long 0x00 5. "intedbccr0a,Cache RAM duplication error interrupt indication for dbsccore0" "0,1"
rbitfld.long 0x00 4. "Reserved_4,Reserved" "0,1"
newline
bitfld.long 0x00 3. "intdxamawx0a,EDC error in AXMM W Ch Interrupt indication for dbsccore0" "0,1"
bitfld.long 0x00 2. "intdxamaw0a,EDC error in AXMM AW Ch Interrupt indication for dbsccore0" "0,1"
newline
bitfld.long 0x00 1. "intdxamar0a,EDC error in AXMM AR Ch Interrupt indication for dbsccore0" "0,1"
bitfld.long 0x00 0. "intepdvaxi0a,POST error in AXI domain interrupt indication for dbsccore0" "0,1"
group.long 0x7008++0x03
line.long 0x00 "DBFSINTXXX02A,"
hexmask.long.byte 0x00 24.--31. 1. "intcmbcsr0a,ECC error (multi: over 2bit error) for SystemRAM RMW Interrupt indication for dbsccore0"
hexmask.long.byte 0x00 16.--23. 1. "intcdbcsr0a,ECC error (detect: 1bit error & correct) for SystemRAM RMW Interrupt indication for dbsccore0"
newline
hexmask.long.byte 0x00 8.--15. 1. "intcmbcrr0a,ECC error (multi: over 2bit error) for read response Interrupt indication for dbsccore0"
hexmask.long.byte 0x00 0.--7. 1. "intcdbcrr0a,ECC error (detect: 1bit error & correct) for read response Interrupt indication for dbsccore0"
group.long 0x700C++0x03
line.long 0x00 "DBFSINTXXX03A,"
hexmask.long 0x00 0.--31. 1. "intcdbcdr0a,ECC error (detect: 1bit error & correct) for DRAM RMW interrupt indication for dbsccore0"
group.long 0x7010++0x03
line.long 0x00 "DBFSINTXXX04A,"
hexmask.long 0x00 0.--31. 1. "intcmbcdr0a,ECC error (multi: over 2bit error) for DRAM RMW interrupt indication for dbsccore0"
group.long 0x7020++0x03
line.long 0x00 "DBFSINTXXX08A,"
hexmask.long.word 0x00 19.--31. 1. "Reserved_19,Reserved.These bits are always read as 0"
rbitfld.long 0x00 18. "Reserved_18,Reserved" "0,1"
newline
rbitfld.long 0x00 17. "Reserved_17,Reserved" "0,1"
rbitfld.long 0x00 16. "Reserved_16,Reserved" "0,1"
newline
hexmask.long.word 0x00 3.--15. 1. "Reserved_3,Reserved.These bits are always read as 0"
bitfld.long 0x00 2. "intexbcdr0a,ECC error injection for ECC checker for DRAM RMW interrupt indication for dbsccore0" "0,1"
newline
bitfld.long 0x00 1. "intexbcsr0a,ECC error injection for ECC checker for SystemRAM RMW Interrupt indication for dbsccore0" "0,1"
bitfld.long 0x00 0. "intexbcrr0a,ECC error injection for ECC checker for read response Interrupt indication for dbsccore0" "0,1"
group.long 0x7024++0x03
line.long 0x00 "DBFSINTXXX09A,"
rbitfld.long 0x00 26.--31. "Reserved_26,Reserved.These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 25. "Reserved_25,Reserved" "0,1"
newline
rbitfld.long 0x00 24. "Reserved_24,Reserved" "0,1"
rbitfld.long 0x00 18.--23. "Reserved_18,Reserved.These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 17. "Reserved_17,Reserved" "0,1"
rbitfld.long 0x00 16. "Reserved_16,Reserved" "0,1"
newline
rbitfld.long 0x00 10.--15. "Reserved_10,Reserved.These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 9. "intoddvard1a,OrderID error of isbus async read ch" "0,1"
newline
bitfld.long 0x00 8. "intdxdvard1a,EDC error of isbus async read ch" "0,1"
rbitfld.long 0x00 2.--7. "Reserved_2,Reserved.These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 1. "intoddvard0a,OrderID error of isbus async read ch" "0,1"
bitfld.long 0x00 0. "intdxdvard0a,EDC error of isbus async read ch" "0,1"
group.long 0x7028++0x03
line.long 0x00 "DBFSINTXXX10A,"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved.These bits are always read as 0"
hexmask.long.word 0x00 0.--15. 1. "intxxasynsba,Async sideband errors in axi domain"
group.long 0x7040++0x03
line.long 0x00 "DBFSINTCLR00A,"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved.These bits are always read as 0"
bitfld.long 0x00 0. "icldclsa,Clear safety error interrupt signal (level) for clk_axi domain" "0,1"
group.long 0x7080++0x03
line.long 0x00 "DBFSINTENB00A,"
bitfld.long 0x00 31. "ienexdclaxa,Comparator error of DCLS for clk_axi group Interrupt enable bit" "0,1"
bitfld.long 0x00 30. "ienexdclsra,Comparator error of DCLS group sram interrupt enable bit" "0,1"
newline
hexmask.long.tbyte 0x00 11.--29. 1. "Reserved_11,Reserved.These bits are always read as 0"
bitfld.long 0x00 10. "ienodasbda,OrderID error in AXI64 Bch clk_dbs side Interrupt enable bit" "0,1"
newline
bitfld.long 0x00 9. "ienodasrda,OrderID error in AXI64 Rch clk_dbs side Interrupt enable bit" "0,1"
bitfld.long 0x00 8. "ienodasbxa,OrderID error in AXI64 Bch clk_axi side Interrupt enable bit" "0,1"
newline
bitfld.long 0x00 7. "ienodasrxa,OrderID error in AXI64 Rch clk_axi side Interrupt enable bit" "0,1"
bitfld.long 0x00 6. "ienodaswxa,OrderID error in AXI64 Wch clk_axi side Interrupt enable bit" "0,1"
newline
bitfld.long 0x00 5. "ienodasawa,OrderID error in AXI64 AWch clk_axi side Interrupt enable bit" "0,1"
bitfld.long 0x00 4. "ienodasara,OrderID error in AXI64 ARch clk_axi side Interrupt enable bit" "0,1"
newline
rbitfld.long 0x00 3. "Reserved_3,Reserved.These bits are always read as 0" "0,1"
bitfld.long 0x00 2. "iendxaswxa,EDC error in AXSM W Ch clk_axi domain Interrupt enable bit" "0,1"
newline
bitfld.long 0x00 1. "iendxasawa,EDC error in AXSM AW Ch clk_axi domain Interrupt enable bit" "0,1"
bitfld.long 0x00 0. "iendxasara,EDC error in AXSM AR Ch clk_axi domain Interrupt enable bit" "0,1"
group.long 0x7084++0x03
line.long 0x00 "DBFSINTENB01A,"
hexmask.long.word 0x00 23.--31. 1. "Reserved_23,Reserved.These bits are always read as 0"
rbitfld.long 0x00 22. "Reserved_22,Reserved" "0,1"
newline
rbitfld.long 0x00 21. "Reserved_21,Reserved" "0,1"
rbitfld.long 0x00 20. "Reserved_20,Reserved" "0,1"
newline
rbitfld.long 0x00 19. "Reserved_19,Reserved" "0,1"
rbitfld.long 0x00 18. "Reserved_18,Reserved" "0,1"
newline
rbitfld.long 0x00 17. "Reserved_17,Reserved" "0,1"
rbitfld.long 0x00 16. "Reserved_16,Reserved" "0,1"
newline
hexmask.long.word 0x00 7.--15. 1. "Reserved_7,Reserved.These bits are always read as 0"
bitfld.long 0x00 6. "iennomem0a,No mem error in address decoder of dbsccore0 interrupt enable bit" "0,1"
newline
bitfld.long 0x00 5. "ienedbccr0a,Cache RAM duplication error interrupt enable bit for dbsccore0" "0,1"
bitfld.long 0x00 4. "iencxfcprd0a,ECC error in FCPRD for core0 Interrupt enable bit for dbsccore0" "0,1"
newline
bitfld.long 0x00 3. "iendxamawx0a,EDC error in AXMM W Ch Interrupt enable bit for dbsccore0" "0,1"
bitfld.long 0x00 2. "iendxamaw0a,EDC error in AXMM AW Ch Interrupt enable bit for dbsccore0" "0,1"
newline
bitfld.long 0x00 1. "iendxamar0a,EDC error in AXMM AR Ch Interrupt enable bit for dbsccore0" "0,1"
bitfld.long 0x00 0. "ienepdvaxi0a,POST error in AXI domain interrupt enable bit for dbsccore0" "0,1"
group.long 0x7088++0x03
line.long 0x00 "DBFSINTENB02A,"
hexmask.long.byte 0x00 24.--31. 1. "iencmbcsr0a,ECC error (multi: over 2bit error) for SystemRAM RMW Interrupt enable bit for dbsccore0"
hexmask.long.byte 0x00 16.--23. 1. "iencdbcsr0a,ECC error (detect: 1bit error & correct) for SystemRAM RMW Interrupt enable bit for dbsccore0"
newline
hexmask.long.byte 0x00 8.--15. 1. "iencmbcrr0a,ECC error (multi: over 2bit error) for read response Interrupt enable bit for dbsccore0"
hexmask.long.byte 0x00 0.--7. 1. "iencdbcrr0a,ECC error (detect: 1bit error & correct) for read response Interrupt enable bit for dbsccore0"
group.long 0x708C++0x03
line.long 0x00 "DBFSINTENB03A,"
hexmask.long 0x00 0.--31. 1. "iencdbcdr0a,ECC error (detect: 1bit error & correct) for DRAM RMW interrupt enable bit for dbsccore0"
group.long 0x7090++0x03
line.long 0x00 "DBFSINTENB04A,"
hexmask.long 0x00 0.--31. 1. "iencmbcdr0a,ECC error (multi: over 2bit error) for DRAM RMW interrupt enable bit for dbsccore0"
group.long 0x70A0++0x03
line.long 0x00 "DBFSINTENB08A,"
hexmask.long.word 0x00 19.--31. 1. "Reserved_19,Reserved.These bits are always read as 0"
rbitfld.long 0x00 18. "Reserved_18,Reserved" "0,1"
newline
rbitfld.long 0x00 17. "Reserved_17,Reserved" "0,1"
rbitfld.long 0x00 16. "Reserved_16,Reserved" "0,1"
newline
hexmask.long.word 0x00 3.--15. 1. "Reserved_3,Reserved.These bits are always read as 0"
bitfld.long 0x00 2. "ienexbcdr0a,ECC error injection for ECC checker for DRAM RMW interrupt enable bit for dbsccore0" "0,1"
newline
bitfld.long 0x00 1. "ienexbcsr0a,ECC error injection for ECC checker for SystemRAM RMW Interrupt enable bit for dbsccore0" "0,1"
bitfld.long 0x00 0. "ienexbcrr0a,ECC error injection for ECC checker for read response Interrupt enable bit for dbsccore0" "0,1"
group.long 0x70A4++0x03
line.long 0x00 "DBFSINTENB09A,"
rbitfld.long 0x00 26.--31. "Reserved_26,Reserved.These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 25. "Reserved_25,Reserved" "0,1"
newline
rbitfld.long 0x00 24. "Reserved_24,Reserved" "0,1"
rbitfld.long 0x00 18.--23. "Reserved_18,Reserved.These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 17. "Reserved_17,Reserved" "0,1"
rbitfld.long 0x00 16. "Reserved_16,Reserved" "0,1"
newline
rbitfld.long 0x00 10.--15. "Reserved_10,Reserved.These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 9. "ienoddvard1a,OrderID error of isbus async read ch" "0,1"
newline
bitfld.long 0x00 8. "iendxdvard1a,EDC error of isbus async read ch" "0,1"
rbitfld.long 0x00 2.--7. "Reserved_2,Reserved.These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 1. "ienoddvard0a,OrderID error of isbus async read ch" "0,1"
bitfld.long 0x00 0. "iendxdvard0a,EDC error of isbus async read ch" "0,1"
group.long 0x70A8++0x03
line.long 0x00 "DBFSINTENB10A,"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved.These bits are always read as 0"
hexmask.long.word 0x00 0.--15. 1. "ienxxasynsba,Async sideband errors interrupt enable in axi domain"
group.long 0x7100++0x03
line.long 0x00 "DBFSINJECT00A,"
bitfld.long 0x00 31. "ijtexdclaxa,Comparator error of DCLS for clk_axi group Interrupt injection mode" "0,1"
bitfld.long 0x00 30. "ijtexdclsra,Comparator error of DCLS for sram Interrupt injection mode" "0,1"
newline
hexmask.long.tbyte 0x00 11.--29. 1. "Reserved_11,Reserved.These bits are always read as 0"
bitfld.long 0x00 10. "ijtodasbda,OrderID error in AXI64 Bch clk_dbs side Interrupt injection mode" "0,1"
newline
bitfld.long 0x00 9. "ijtodasrda,OrderID error in AXI64 Rch clk_dbs side Interrupt injection mode" "0,1"
bitfld.long 0x00 8. "ijtodasbxa,OrderID error in AXI64 Bch clk_axi side Interrupt injection mode" "0,1"
newline
bitfld.long 0x00 7. "ijtodasrxa,OrderID error in AXI64 Rch clk_axi side Interrupt injection mode" "0,1"
bitfld.long 0x00 6. "ijtodaswxa,OrderID error in AXI64 Wch clk_axi side Interrupt injection mode" "0,1"
newline
bitfld.long 0x00 5. "ijtodasawa,OrderID error in AXI64 AWch clk_axi side Interrupt injection mode" "0,1"
bitfld.long 0x00 4. "ijtodasara,OrderID error in AXI64 ARch clk_axi side Interrupt injection mode" "0,1"
newline
rbitfld.long 0x00 3. "Reserved_3,Reserved.These bits are always read as 0" "0,1"
bitfld.long 0x00 2. "ijtdxaswxa,EDC error in AXSM W Ch clk_axi domain Interrupt injection mode" "0,1"
newline
bitfld.long 0x00 1. "ijtdxasawa,EDC error in AXSM AW Ch clk_axi domain Interrupt injection mode" "0,1"
bitfld.long 0x00 0. "ijtdxasara,EDC error in AXSM AR Ch clk_axi domain Interrupt injection mode" "0,1"
group.long 0x7104++0x03
line.long 0x00 "DBFSINJECT01A,"
hexmask.long.word 0x00 23.--31. 1. "Reserved_23,Reserved.These bits are always read as 0"
rbitfld.long 0x00 22. "Reserved_22,Reserved" "0,1"
newline
rbitfld.long 0x00 21. "Reserved_21,Reserved" "0,1"
rbitfld.long 0x00 20. "Reserved_20,Reserved" "0,1"
newline
rbitfld.long 0x00 19. "Reserved_19,Reserved" "0,1"
rbitfld.long 0x00 18. "Reserved_18,Reserved" "0,1"
newline
rbitfld.long 0x00 17. "Reserved_17,Reserved" "0,1"
rbitfld.long 0x00 16. "Reserved_16,Reserved" "0,1"
newline
hexmask.long.word 0x00 7.--15. 1. "Reserved_7,Reserved.These bits are always read as 0"
bitfld.long 0x00 6. "ijtnomem0a,No mem error in address decoder of dbsccore0 interrupt injection mode" "0,1"
newline
bitfld.long 0x00 5. "ijtedbccr0a,Cache RAM duplication error interrupt injection mode for dbsccore0" "0,1"
bitfld.long 0x00 4. "ijtcxfcprd0a,CRC error in FCPRD for core0 Interrupt injection mode for dbsccore0" "0,1"
newline
bitfld.long 0x00 3. "ijtdxamawx0a,EDC error in AXMM W Ch Interrupt injection mode for dbsccore0" "0,1"
bitfld.long 0x00 2. "ijtdxamaw0a,EDC error in AXMM AW Ch Interrupt injection mode for dbsccore0" "0,1"
newline
bitfld.long 0x00 1. "ijtdxamar0a,EDC error in AXMM AR Ch Interrupt injection mode for dbsccore0" "0,1"
bitfld.long 0x00 0. "ijtepdvaxi0a,POST error in AXI domain interrupt injection mode for dbsccore0" "0,1"
group.long 0x7108++0x03
line.long 0x00 "DBFSINJECT02A,"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved.These bits are always read as 0"
bitfld.long 0x00 24. "ijtcmbcsr0a,ECC error (multi: over 2bit error) for SystemRAM RMW Interrupt injection mode for dbsccore0" "0,1"
newline
hexmask.long.byte 0x00 17.--23. 1. "Reserved_17,Reserved.These bits are always read as 0"
bitfld.long 0x00 16. "ijtcdbcsr0a,ECC error (detect: 1bit error & correct) for SystemRAM RMW Interrupt injection mode for dbsccore0" "0,1"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved.These bits are always read as 0"
bitfld.long 0x00 8. "ijtcmbcrr0a,ECC error (multi: over 2bit error) for read response Interrupt injection mode for dbsccore0" "0,1"
newline
hexmask.long.byte 0x00 1.--7. 1. "Reserved_1,Reserved.These bits are always read as 0"
bitfld.long 0x00 0. "ijtcdbcrr0a,ECC error (detect: 1bit error & correct) for read response Interrupt injection mode for dbsccore0" "0,1"
group.long 0x710C++0x03
line.long 0x00 "DBFSINJECT03A,"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved.These bits are always read as 0"
bitfld.long 0x00 0. "ijtcdbcdr0a,ECC error (detect: 1bit error & correct) for DRAM RMW interrupt injection mode for dbsccore0" "0,1"
group.long 0x7110++0x03
line.long 0x00 "DBFSINJECT04A,"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved.These bits are always read as 0"
bitfld.long 0x00 0. "ijtcmbcdr0a,ECC error (multi: over 2bit error) for DRAM RMW interrupt injection mode for dbsccore0" "0,1"
group.long 0x7124++0x03
line.long 0x00 "DBFSINJECT09A,"
rbitfld.long 0x00 26.--31. "Reserved_26,Reserved.These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 25. "Reserved_25,Reserved" "0,1"
newline
rbitfld.long 0x00 24. "Reserved_24,Reserved" "0,1"
rbitfld.long 0x00 18.--23. "Reserved_18,Reserved.These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 17. "Reserved_17,Reserved" "0,1"
rbitfld.long 0x00 16. "Reserved_16,Reserved" "0,1"
newline
rbitfld.long 0x00 10.--15. "Reserved_10,Reserved.These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 9. "ijtoddvard1a,OrderID error of isbus async read ch" "0,1"
newline
bitfld.long 0x00 8. "ijtdxdvard1a,EDC error of isbus async read ch" "0,1"
rbitfld.long 0x00 2.--7. "Reserved_2,Reserved.These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 1. "ijtoddvard0a,OrderID error of isbus async read ch" "0,1"
bitfld.long 0x00 0. "ijtdxdvard0a,EDC error of isbus async read ch" "0,1"
group.long 0x7128++0x03
line.long 0x00 "DBFSINJECT10A,"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved.These bits are always read as 0"
hexmask.long.word 0x00 0.--15. 1. "ijtxxasynsba,Async sideband errors interrupt injection mode"
group.long 0x7200++0x03
line.long 0x00 "DBFSINTCNT00A,"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved.These bits are always read as 0"
hexmask.long.byte 0x00 16.--23. 1. "cntdxaswxa,EDC error in AXSM W Ch clk_axi domain Interrupt counter mode"
newline
hexmask.long.byte 0x00 8.--15. 1. "cntdxasawa,EDC error in AXSM AW Ch clk_axi domain Interrupt counter mode"
hexmask.long.byte 0x00 0.--7. 1. "cntdxasara,EDC error in AXSM AR Ch clk_axi domain Interrupt counter mode"
group.long 0x7204++0x03
line.long 0x00 "DBFSINTCNT01A,"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,reserved"
hexmask.long.byte 0x00 16.--23. 1. "cntdxamawx0a,EDC error in AXMM W Ch Interrupt counter for dbsccore0"
newline
hexmask.long.byte 0x00 8.--15. 1. "cntdxamaw0a,EDC error in AXMM AW Ch Interrupt counter for dbsccore0"
hexmask.long.byte 0x00 0.--7. 1. "cntdxamar0a,EDC error in AXMM AR Ch Interrupt counter for dbsccore0"
group.long 0x720C++0x03
line.long 0x00 "DBFSINTCNT03A,"
hexmask.long.byte 0x00 24.--31. 1. "cntcmbcsr0a,ECC error (multi: over 2bit error) for SystemRAM RMW Interrupt counter mode for dbsccore0"
hexmask.long.byte 0x00 16.--23. 1. "cntcdbcsr0a,ECC error (detect: 1bit error & correct) for SystemRAM RMW Interrupt counter mode for dbsccore0"
newline
hexmask.long.byte 0x00 8.--15. 1. "cntcmbcrr0a,ECC error (multi: over 2bit error) for read response Interrupt counter mode for dbsccore0"
hexmask.long.byte 0x00 0.--7. 1. "cntcdbcrr0a,ECC error (detect: 1bit error & correct) for read response Interrupt counter mode for dbsccore0"
group.long 0x7210++0x03
line.long 0x00 "DBFSINTCNT04A,"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved.These bits are always read as 0"
hexmask.long.byte 0x00 8.--15. 1. "cntcmbcdr0a,ECC error (multi: over 2bit error) for DRAM RMW interrupt counter for dbsccore0"
newline
hexmask.long.byte 0x00 0.--7. 1. "cntcdbcdr0a,ECC error (detect: 1bit error & correct) for DRAM RMW interrupt counter for dbsccore0"
group.long 0x721C++0x03
line.long 0x00 "DBFSINTCNT07A,"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved"
hexmask.long.byte 0x00 16.--23. 1. "Reserved_16,Reserved"
newline
hexmask.long.byte 0x00 8.--15. 1. "cntdxdvard1a,EDC error of isbus async read ch"
hexmask.long.byte 0x00 0.--7. 1. "cntdxdvard0a,EDC error of isbus async read ch"
group.long 0x7400++0x03
line.long 0x00 "DBFSCONFAXI0,"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved.These bits are always read as 0"
rbitfld.long 0x00 13. "Reserved_13,Reserved" "0,1"
newline
rbitfld.long 0x00 12. "Reserved_12,Reserved" "0,1"
rbitfld.long 0x00 10.--11. "Reserved_10,Reserved.These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 9. "drameccen01,ECC protection enable for DDR access for rank1 on dbsccore0" "0,1"
bitfld.long 0x00 8. "drameccen00,ECC protection enable for DDR access for rank0 on dbsccore0" "0,1"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved.These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4. "srameccdis,ECC protection disable for SysRAM access" "0,1"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved.These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "errcrctdis,Error correction disable" "0,1"
group.long 0x7410++0x03
line.long 0x00 "DBFSECCIJTCHK,"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved.These bits are always read as 0"
hexmask.long.word 0x00 0.--13. 1. "eccijtchk,ECC check bits for error injection"
group.long 0x7414++0x03
line.long 0x00 "DBFSECCIJTERRL,"
hexmask.long 0x00 0.--31. 1. "eccijterrl,Invert any 64bit data and 14 check bits (Low bit side)"
group.long 0x7418++0x03
line.long 0x00 "DBFSECCIJTERRM,"
hexmask.long 0x00 0.--31. 1. "eccijterrm,Invert any 64bit data and 14 check bits (Middle bit side)"
group.long 0x741C++0x03
line.long 0x00 "DBFSECCIJTERRH,"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved.These bits are always read as 0"
hexmask.long.word 0x00 0.--13. 1. "eccijterrh,Invert any 64bit data and 14 check bits (High bit side)"
group.long 0x7430++0x03
line.long 0x00 "DBFSECCIJTADRL0,"
hexmask.long 0x00 0.--31. 1. "eccijtadrl0,Specific address register for error injection for ECC chk.(LSB side)"
group.long 0x7434++0x03
line.long 0x00 "DBFSECCIJTADRH0,"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved.These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "eccijtadrh0,Specific address register for error injection for ECC chk.(MSB side)"
group.long 0x7438++0x03
line.long 0x00 "DBFSECCIJTDATL0,"
hexmask.long 0x00 0.--31. 1. "eccijtdatl0,Data for error injection(LSB side)"
group.long 0x743C++0x03
line.long 0x00 "DBFSECCIJTDATH0,"
hexmask.long 0x00 0.--31. 1. "eccijtdath0,Data for error injection(MSB side)"
group.long 0x7450++0x03
line.long 0x00 "DBFSDRAMECCAREA00,"
hexmask.long 0x00 0.--31. 1. "drameccarea00,ECC protection area for rank0 on dbsccore0"
group.long 0x7454++0x03
line.long 0x00 "DBFSDRAMECCAREA01,"
hexmask.long 0x00 0.--31. 1. "drameccarea01,ECC protection area for rank1 on dbsccore0"
group.long 0x7480++0x03
line.long 0x00 "DBFSCTRLAXI0,"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved.These bits are always read as 0"
bitfld.long 0x00 0. "postenaxi,Start POST for asynchronous bridge in devcnt" "0,1"
group.long 0x74A0++0x03
line.long 0x00 "DBFSCTRLBCAM0A,"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved.These bits are always read as 0"
bitfld.long 0x00 0. "bcijtreq,Error injection for ECC of RMW" "0,1"
group.long 0x74A4++0x03
line.long 0x00 "DBFSCTRLBCAM1A,"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved.These bits are always read as 0"
bitfld.long 0x00 0. "bcijtaddr,Enable of Error injection mode" "0,1"
group.long 0x7510++0x03
line.long 0x00 "DBFSMNDEA0LA,"
hexmask.long 0x00 0.--31. 1. "mndea0la,Nomem error (decode error) address LSB bits of dbsccore0"
group.long 0x7514++0x03
line.long 0x00 "DBFSMNDEA0HA,"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved.These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "mndea0ha,Nomem error (decode error) address MSB bits of dbsccore0"
group.long 0x7518++0x03
line.long 0x00 "DBFSMNDESID0A,"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved.These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "mndesid0a,Nomem error (decode error) source ID of dbsccore0"
group.long 0x751C++0x03
line.long 0x00 "DBFSMNEDCSID0A,"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved.These bits are always read as 0"
hexmask.long.byte 0x00 16.--23. 1. "mnedcsidwx0a,EDC error source ID for W channel of dbsccore0"
newline
hexmask.long.byte 0x00 8.--15. 1. "mnedcsidaw0a,EDC error source ID for AW channel of dbsccore0"
hexmask.long.byte 0x00 0.--7. 1. "mnedcsidar0a,EDC error source ID for AR channel of dbsccore0"
group.long 0x7600++0x03
line.long 0x00 "DBFSCTRL00A,"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved.These bits are always read as 0"
bitfld.long 0x00 0. "srainidis,System-RAM initialization disable" "0,1"
group.long 0x7604++0x03
line.long 0x00 "DBFSCTRL01A,"
hexmask.long 0x00 2.--31. 1. "Reserved_2,Reserved.These bits are always read as 0"
rbitfld.long 0x00 1. "Reserved_1,Reserved" "0,1"
newline
bitfld.long 0x00 0. "ddrinistart0,DDR initialization start trigger for dbsccore0 (1-shot pulse clear right after asserting)" "0,1"
group.long 0x7640++0x03
line.long 0x00 "DBFSCONF00A,"
hexmask.long 0x00 2.--31. 1. "Reserved_2,Reserved.These bits are always read as 0"
bitfld.long 0x00 0.--1. "ddrinirank0,DDR initialization area rank address for dbsccore 0" "0,1,2,3"
group.long 0x7644++0x03
line.long 0x00 "DBFSCONF01A,"
hexmask.long 0x00 0.--31. 1. "ddriniareas0,DDR initialization area start row address for dbsccore0"
group.long 0x7654++0x03
line.long 0x00 "DBFSCONF05A,"
hexmask.long 0x00 0.--31. 1. "ddriniareae0,DDR initialization area end row address for dbsccore0"
group.long 0x7680++0x03
line.long 0x00 "DBFSSTAT00A,"
hexmask.long 0x00 2.--31. 1. "Reserved_2,Reserved"
rbitfld.long 0x00 1. "Reserved_1,Reserved" "0,1"
newline
bitfld.long 0x00 0. "srainiend0,System-RAM initialization completion of dbsccore0" "0,1"
group.long 0x7684++0x03
line.long 0x00 "DBFSSTAT01A,"
hexmask.long 0x00 2.--31. 1. "Reserved_2,Reserved"
rbitfld.long 0x00 1. "Reserved_1,Reserved" "0,1"
newline
bitfld.long 0x00 0. "ddriniend0,DRAM initialization completion of dbsccore0" "0,1"
group.long 0x7688++0x03
line.long 0x00 "DBFSSTAT02A,"
hexmask.long 0x00 2.--31. 1. "Reserved_2,Reserved.These bits are always read as 0"
rbitfld.long 0x00 1. "Reserved_1,Reserved" "0,1"
newline
bitfld.long 0x00 0. "bceccempty0,Status register for dbsccore0" "0,1"
group.long 0x7800++0x03
line.long 0x00 "DBFSINTXXX00D,"
hexmask.long 0x00 7.--31. 1. "Reserved_7,Reserved.These bits are always read as 0"
bitfld.long 0x00 6. "intodaswxd,OrderID error in AXI64 Wch clk_axi side Interrupt indication" "0,1"
newline
bitfld.long 0x00 5. "intodasawd,OrderID error in AXI64 AWch clk_axi side Interrupt indication" "0,1"
bitfld.long 0x00 4. "intodasard,OrderID error in AXI64 ARch clk_axi side Interrupt indication" "0,1"
newline
rbitfld.long 0x00 3. "Reserved_3,Reserved.These bits are always read as 0" "0,1"
bitfld.long 0x00 2. "intdxaswxd,EDC error in AXSM W Ch clk_axi domain Interrupt indication" "0,1"
newline
bitfld.long 0x00 1. "intdxasawd,EDC error in AXSM AW Ch clk_axi domain Interrupt indication" "0,1"
bitfld.long 0x00 0. "intdxasard,EDC error in AXSM AR Ch clk_axi domain Interrupt indication" "0,1"
group.long 0x7804++0x03
line.long 0x00 "DBFSINTXXX01D,"
bitfld.long 0x00 31. "intexdcld1d,Comparator error of DCLS group dbs1 interrupt indication for memory channel 1" "0,1"
bitfld.long 0x00 30. "intpxpyrif1d,Parity error for PHY-Register I/F (rdata) for memory channel1" "0,1"
newline
rbitfld.long 0x00 26.--29. "Reserved_26,Reserved.These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 25. "intoddvawr1d,OrderID error of isbus async write ch" "0,1"
newline
bitfld.long 0x00 24. "intoddvacq1d,OrderID error of isbus async address (command queue) ch" "0,1"
bitfld.long 0x00 23. "intdxdvawr1d,EDC error of isbus async write ch" "0,1"
newline
bitfld.long 0x00 22. "intdxdvacq1d,EDC error of isbus async address (command queue) ch" "0,1"
bitfld.long 0x00 21. "intoddvphy1d,OrderID error in DFI DDR PHY interrupt indication for memory channel 1" "0,1"
newline
bitfld.long 0x00 20. "intoddvdbs1d,OrderID error in DFI DBSC interrupt indication for memory channel 1" "0,1"
bitfld.long 0x00 19. "intdxdvphy1d,EDC error in DFI DDR PHY interrupt indication for memory channel 1" "0,1"
newline
bitfld.long 0x00 18. "intdxdvdbs1d,EDC error in DFI DBSC interrupt indication for memory channel 1" "0,1"
bitfld.long 0x00 17. "intepdvphy1d,POST error in ddrf interrupt indication for memory channel 1" "0,1"
newline
bitfld.long 0x00 16. "intepdvdbs1d,POST error in DBSC domain interrupt indication for memory channel 1" "0,1"
bitfld.long 0x00 15. "intexdcld0d,Comparator error of DCLS group dbs0 interrupt indication for memory channel 0" "0,1"
newline
bitfld.long 0x00 14. "intpxpyrif0d,Parity error for PHY-Register I/F (rdata) for memory channel 0" "0,1"
rbitfld.long 0x00 10.--13. "Reserved_10,Reserved.These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 9. "intoddvawr0d,OrderID error of isbus async write ch" "0,1"
bitfld.long 0x00 8. "intoddvacq0d,OrderID error of isbus async address (command queue) ch" "0,1"
newline
bitfld.long 0x00 7. "intdxdvawr0d,EDC error of isbus async write ch" "0,1"
bitfld.long 0x00 6. "intdxdvacq0d,EDC error of isbus async address (command queue) ch" "0,1"
newline
bitfld.long 0x00 5. "intoddvphy0d,OrderID error in DFI DDR PHY interrupt indication for memory channel 0" "0,1"
bitfld.long 0x00 4. "intoddvdbs0d,OrderID error in DFI DBSC interrupt indication for memory channel 0" "0,1"
newline
bitfld.long 0x00 3. "intdxdvphy0d,EDC error in DFI DDR PHY interrupt indication for memory channel 0" "0,1"
bitfld.long 0x00 2. "intdxdvdbs0d,EDC error in DFI DBSC interrupt indication for memory channel 0" "0,1"
newline
bitfld.long 0x00 1. "intepdvphy0d,POST error in ddrf interrupt indication for memory channel 0" "0,1"
bitfld.long 0x00 0. "intepdvdbs0d,POST error in DBSC domain interrupt indication for memory channel 0" "0,1"
group.long 0x780C++0x03
line.long 0x00 "DBFSINTXXX03D,"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved.These bits are always read as 0"
hexmask.long.word 0x00 0.--15. 1. "intxxasynsbd,Async sideband errors in dbs domain"
group.long 0x7840++0x03
line.long 0x00 "DBFSINTCLR00D,"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved.These bits are always read as 0"
bitfld.long 0x00 0. "icldclsd,Clear safety error interrupt signal (level) for clk_dbsc domain" "0,1"
group.long 0x7880++0x03
line.long 0x00 "DBFSINTENB00D,"
hexmask.long 0x00 7.--31. 1. "Reserved_7,Reserved.These bits are always read as 0"
bitfld.long 0x00 6. "ienodaswxd,OrderID error in AXI64 Wch clk_axi side interrupt enable" "0,1"
newline
bitfld.long 0x00 5. "ienodasawd,OrderID error in AXI64 AWch clk_axi side interrupt enable" "0,1"
bitfld.long 0x00 4. "ienodasard,OrderID error in AXI64 ARch clk_axi side interrupt enable" "0,1"
newline
rbitfld.long 0x00 3. "Reserved_3,Reserved.These bits are always read as 0" "0,1"
bitfld.long 0x00 2. "iendxaswxd,EDC error in AXSM W Ch clk_axi domain interrupt enable" "0,1"
newline
bitfld.long 0x00 1. "iendxasawd,EDC error in AXSM AW Ch clk_axi domain interrupt enable" "0,1"
bitfld.long 0x00 0. "iendxasard,EDC error in AXSM AR Ch clk_axi domain interrupt enable" "0,1"
group.long 0x7884++0x03
line.long 0x00 "DBFSINTENB01D,"
bitfld.long 0x00 31. "ienexdcld1d,Comparator error of DCLS group interrupt enable for memory channel 1" "0,1"
bitfld.long 0x00 30. "ienpxpyrif1d,Parity error for PHY-Register I/F (rdata) for memory channel1" "0,1"
newline
rbitfld.long 0x00 26.--29. "Reserved_26,Reserved.These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 25. "ienoddvawr1d,OrderID error of isbus async write ch" "0,1"
newline
bitfld.long 0x00 24. "ienoddvacq1d,OrderID error of isbus async address (command queue) ch" "0,1"
bitfld.long 0x00 23. "iendxdvawr1d,EDC error of isbus async write ch" "0,1"
newline
bitfld.long 0x00 22. "iendxdvacq1d,EDC error of isbus async address (command queue) ch" "0,1"
bitfld.long 0x00 21. "ienoddvphy1d,OrderID error in DFI DDR PHY interrupt enable bit for memory channel 1" "0,1"
newline
bitfld.long 0x00 20. "ienoddvdbs1d,OrderID error in DFI DBSC interrupt enable bit for memory channel 1" "0,1"
bitfld.long 0x00 19. "iendxdvphy1d,EDC error in DFI DDR PHY interrupt enable bit for memory channel 1" "0,1"
newline
bitfld.long 0x00 18. "iendxdvdbs1d,EDC error in DFI DBSC interrupt enable bit for memory channel 1" "0,1"
bitfld.long 0x00 17. "ienepdvphy1d,POST error in ddrf interrupt enable bit for memory channel 1" "0,1"
newline
bitfld.long 0x00 16. "ienepdvdbs1d,POST error in DBSC domain interrupt enable bit for memory channel 1" "0,1"
bitfld.long 0x00 15. "ienexdcld0d,Comparator error of DCLS group interrupt enable for memory channel 0" "0,1"
newline
bitfld.long 0x00 14. "ienpxpyrif0d,Parity error for PHY-Register I/F (rdata) for memory channel0" "0,1"
rbitfld.long 0x00 10.--13. "Reserved_10,Reserved.These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 9. "ienoddvawr0d,OrderID error of isbus async write ch" "0,1"
bitfld.long 0x00 8. "ienoddvacq0d,OrderID error of isbus async address (command queue) ch" "0,1"
newline
bitfld.long 0x00 7. "iendxdvawr0d,EDC error of isbus async write ch" "0,1"
bitfld.long 0x00 6. "iendxdvacq0d,EDC error of isbus async address (command queue) ch" "0,1"
newline
bitfld.long 0x00 5. "ienoddvphy0d,OrderID error in DFI DDR PHY interrupt enable bit for memory channel 0" "0,1"
bitfld.long 0x00 4. "ienoddvdbs0d,OrderID error in DFI DBSC interrupt enable bit for memory channel 0" "0,1"
newline
bitfld.long 0x00 3. "iendxdvphy0d,EDC error in DFI DDR PHY interrupt enable bit for memory channel 0" "0,1"
bitfld.long 0x00 2. "iendxdvdbs0d,EDC error in DFI DBSC interrupt enable bit for memory channel 0" "0,1"
newline
bitfld.long 0x00 1. "ienepdvphy0d,POST error in ddrf interrupt enable bit for memory channel 0" "0,1"
bitfld.long 0x00 0. "ienepdvdbs0d,POST error in DBSC domain interrupt enable bit for memory channel 0" "0,1"
group.long 0x788C++0x03
line.long 0x00 "DBFSINTENB03D,"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved.These bits are always read as 0"
hexmask.long.word 0x00 0.--15. 1. "ienxxasynsbd,Async sideband errors interrupt enable in dbs domain"
group.long 0x7900++0x03
line.long 0x00 "DBFSINJECT00D,"
hexmask.long 0x00 7.--31. 1. "Reserved_7,Reserved.These bits are always read as 0"
bitfld.long 0x00 6. "ijtodaswxd,OrderID error in AXI64 Wch clk_axi side interrupt injection mode" "0,1"
newline
bitfld.long 0x00 5. "ijtodasawd,OrderID error in AXI64 AWch clk_axi side interrupt injection mode" "0,1"
bitfld.long 0x00 4. "ijtodasard,OrderID error in AXI64 ARch clk_axi side interrupt injection mode" "0,1"
newline
rbitfld.long 0x00 3. "Reserved_3,Reserved.These bits are always read as 0" "0,1"
bitfld.long 0x00 2. "ijtdxaswxd,EDC error in AXSM W Ch clk_axi domain interrupt injection mode" "0,1"
newline
bitfld.long 0x00 1. "ijtdxasawd,EDC error in AXSM AW Ch clk_axi domain interrupt injection mode" "0,1"
bitfld.long 0x00 0. "ijtdxasard,EDC error in AXSM AR Ch clk_axi domain interrupt injection mode" "0,1"
group.long 0x7904++0x03
line.long 0x00 "DBFSINJECT01D,"
bitfld.long 0x00 31. "ijtexdcld1d,Comparator error of DCLS group dbs1 interrupt injection mode" "0,1"
bitfld.long 0x00 30. "ijtpxpyrif1d,Parity error for PHY-Register I/F (rdata) for memory channel 1" "0,1"
newline
rbitfld.long 0x00 26.--29. "Reserved_26,Reserved.These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 25. "ijtoddvawr1d,OrderID error of isbus async write ch" "0,1"
newline
bitfld.long 0x00 24. "ijtoddvacq1d,OrderID error of isbus async address (command queue) ch" "0,1"
bitfld.long 0x00 23. "ijtdxdvawr1d,EDC error of isbus async write ch" "0,1"
newline
bitfld.long 0x00 22. "ijtdxdvacq1d,EDC error of isbus async address (command queue) ch" "0,1"
bitfld.long 0x00 21. "ijtoddvphy1d,OrderID error in DFI DDR PHY interrupt injection for memory channel 1" "0,1"
newline
bitfld.long 0x00 20. "ijtoddvdbs1d,OrderID error in DFI DBSC interrupt injection for memory channel 1" "0,1"
bitfld.long 0x00 19. "ijtdxdvphy1d,EDC error in DFI DDR PHY interrupt injection for memory channel 1" "0,1"
newline
bitfld.long 0x00 18. "ijtdxdvdbs1d,EDC error in DFI DBSC interrupt injection for memory channel 1" "0,1"
bitfld.long 0x00 17. "ijtepdvphy1d,POST error in ddrf interrupt injection for memory channel 1" "0,1"
newline
bitfld.long 0x00 16. "ijtepdvdbs1d,POST error in DBSC domain interrupt injection for memory channel 1" "0,1"
bitfld.long 0x00 15. "ijtexdcld0d,Comparator error of DCLS group dbs0 interrupt injection mode" "0,1"
newline
bitfld.long 0x00 14. "ijtpxpyrif0d,Parity error for PHY-Register I/F (rdata) for memory channel 0" "0,1"
rbitfld.long 0x00 10.--13. "Reserved_10,Reserved.These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 9. "ijtoddvawr0d,OrderID error of isbus async write ch" "0,1"
bitfld.long 0x00 8. "ijtoddvacq0d,OrderID error of isbus async address (command queue) ch" "0,1"
newline
bitfld.long 0x00 7. "ijtdxdvawr0d,EDC error of isbus async write ch" "0,1"
bitfld.long 0x00 6. "ijtdxdvacq0d,EDC error of isbus async address (command queue) ch" "0,1"
newline
bitfld.long 0x00 5. "ijtoddvphy0d,OrderID error in DFI DDR PHY interrupt injection mode for memory channel 0" "0,1"
bitfld.long 0x00 4. "ijtoddvdbs0d,OrderID error in DFI DBSC interrupt injection mode for memory channel 0" "0,1"
newline
bitfld.long 0x00 3. "ijtdxdvphy0d,EDC error in DFI DDR PHY interrupt injection mode for memory channel 0" "0,1"
bitfld.long 0x00 2. "ijtdxdvdbs0d,EDC error in DFI DBSC interrupt injection mode for memory channel 0" "0,1"
newline
bitfld.long 0x00 1. "ijtepdvphy0d,POST error in ddrf interrupt injection mode for memory channel 0" "0,1"
bitfld.long 0x00 0. "ijtepdvdbs0d,POST error in DBSC domain interrupt injection mode for memory channel 0" "0,1"
group.long 0x790C++0x03
line.long 0x00 "DBFSINJECT03D,"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved.These bits are always read as 0"
hexmask.long.word 0x00 0.--15. 1. "ijtxxasynsbd,Async sideband errors interrupt injection mode in dbs domain"
group.long 0x7A00++0x03
line.long 0x00 "DBFSINTCNT00D,"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved.These bits are always read as 0"
hexmask.long.byte 0x00 16.--23. 1. "cntdxaswxd,EDC error in AXSM W Ch clk_axi domain interrupt counter"
newline
hexmask.long.byte 0x00 8.--15. 1. "cntdxasawd,EDC error in AXSM AW Ch clk_axi domain interrupt counter"
hexmask.long.byte 0x00 0.--7. 1. "cntdxasard,EDC error in AXSM AR Ch clk_axi domain interrupt counter"
group.long 0x7A04++0x03
line.long 0x00 "DBFSINTCNT01D,"
hexmask.long.byte 0x00 24.--31. 1. "cntdxdvawr0d,EDC error of isbus async write ch"
hexmask.long.byte 0x00 16.--23. 1. "cntdxdvacq0d,EDC error of isbus async address (command queue) ch"
newline
hexmask.long.byte 0x00 8.--15. 1. "cntdxdvphy0d,EDC error in DFI DDR PHY interrupt counter for memory channel 0"
hexmask.long.byte 0x00 0.--7. 1. "cntdxdvdbs0d,EDC error in DFI DBSC interrupt counter for memory channel 0"
group.long 0x7A08++0x03
line.long 0x00 "DBFSINTCNT02D,"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved.These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "cntpxpyrif0d,Parity error interrupt counter for PHY-Register I/F (rdata) for memory channel0"
group.long 0x7A0C++0x03
line.long 0x00 "DBFSINTCNT03D,"
hexmask.long.byte 0x00 24.--31. 1. "cntdxdvawr1d,EDC error of isbus async write ch"
hexmask.long.byte 0x00 16.--23. 1. "cntdxdvacq1d,EDC error of isbus async address (command queue) ch"
newline
hexmask.long.byte 0x00 8.--15. 1. "cntdxdvphy1d,EDC error in DFI DDR PHY interrupt counter for memory channel 1"
hexmask.long.byte 0x00 0.--7. 1. "cntdxdvdbs1d,EDC error in DFI DBSC interrupt counter for memory channel 1"
group.long 0x7A10++0x03
line.long 0x00 "DBFSINTCNT04D,"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved.These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "cntpxpyrif1d,Parity error interrupt counter for PHY-Register I/F (rdata) for memory channel1"
group.long 0x7C00++0x03
line.long 0x00 "DBFSCONFDBS0,"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved.These bits are always read as 0"
bitfld.long 0x00 0. "protendbs,Enable of Protection between dbsc and DDR PHY" "0,1"
group.long 0x7C80++0x03
line.long 0x00 "DBFSCTRLDBS0,"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved.These bits are always read as 0"
bitfld.long 0x00 0. "postendbs,Start POST for asynchronous bridge in ddrf" "0,1"
tree.end
tree "RT_SRAM"
base ad:0xFFE90000
group.long 0x00++0x03
line.long 0x00 "SECDIV0D,Function: The boundary address setting of the secure region"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DIVADDR,Protection division address [19:12] is set"
group.long 0x04++0x03
line.long 0x00 "SECDIV1D,Function: The boundary address setting of the secure region"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DIVADDR,Protection division address [19:12] is set"
group.long 0x08++0x03
line.long 0x00 "SECDIV2D,Function: The boundary address setting of the secure region"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DIVADDR,Protection division address [19:12] is set"
group.long 0x0C++0x03
line.long 0x00 "SECDIV3D,Function: The boundary address setting of the secure region"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DIVADDR,Protection division address [19:12] is set"
group.long 0x10++0x03
line.long 0x00 "SECDIV4D,Function: The boundary address setting of the secure region"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DIVADDR,Protection division address [19:12] is set"
group.long 0x14++0x03
line.long 0x00 "SECDIV5D,Function: The boundary address setting of the secure region"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DIVADDR,Protection division address [19:12] is set"
group.long 0x18++0x03
line.long 0x00 "SECDIV6D,Function: The boundary address setting of the secure region"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DIVADDR,Protection division address [19:12] is set"
group.long 0x1C++0x03
line.long 0x00 "SECDIV7D,Function: The boundary address setting of the secure region"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DIVADDR,Protection division address [19:12] is set"
group.long 0x20++0x03
line.long 0x00 "SECDIV8D,Function: The boundary address setting of the secure region"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DIVADDR,Protection division address [19:12] is set"
group.long 0x24++0x03
line.long 0x00 "SECDIV9D,Function: The boundary address setting of the secure region"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DIVADDR,Protection division address [19:12] is set"
group.long 0x28++0x03
line.long 0x00 "SECDIV10D,Function: The boundary address setting of the secure region"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DIVADDR,Protection division address [19:12] is set"
group.long 0x2C++0x03
line.long 0x00 "SECDIV11D,Function: The boundary address setting of the secure region"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DIVADDR,Protection division address [19:12] is set"
group.long 0x30++0x03
line.long 0x00 "SECDIV12D,Function: The boundary address setting of the secure region"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DIVADDR,Protection division address [19:12] is set"
group.long 0x34++0x03
line.long 0x00 "SECDIV13D,Function: The boundary address setting of the secure region"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DIVADDR,Protection division address [19:12] is set"
group.long 0x38++0x03
line.long 0x00 "SECDIV14D,Function: The boundary address setting of the secure region"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "DIVADDR,Protection division address [19:12] is set"
group.long 0x40++0x03
line.long 0x00 "SECCTRR0D,Function: Privilege setting of each secure region"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
bitfld.long 0x00 19. "SECG0RP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 18. "SECG1RP,Public Group Read Privilege Setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 17. "SECG2RP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 16. "SECG3RP,Secure Group Read Privilege Setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 15. "SAFG0RP,Region15 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 14. "SAFG1RP,Region14 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 13. "SAFG2RP,Region13 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 12. "SAFG3RP,Region12 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 11. "SAFG4RP,Region11 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 10. "SAFG5RP,Region10 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 9. "SAFG6RP,Region9 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 8. "SAFG7RP,Region8 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 7. "SAFG8RP,Region7 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 6. "SAFG9RP,Region6 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 5. "SAFG10RP,Region5 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 4. "SAFG11RP,Region4 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 3. "SAFG12RP,Region3 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 2. "SAFG13RP,Region2 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 1. "SAFG14RP,Region1 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 0. "SAFG15RP,Region0 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
group.long 0x44++0x03
line.long 0x00 "SECCTRR1D,Function: Privilege setting of each secure region"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
bitfld.long 0x00 19. "SECG0RP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 18. "SECG1RP,Public Group Read Privilege Setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 17. "SECG2RP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 16. "SECG3RP,Secure Group Read Privilege Setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 15. "SAFG0RP,Region15 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 14. "SAFG1RP,Region14 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 13. "SAFG2RP,Region13 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 12. "SAFG3RP,Region12 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 11. "SAFG4RP,Region11 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 10. "SAFG5RP,Region10 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 9. "SAFG6RP,Region9 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 8. "SAFG7RP,Region8 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 7. "SAFG8RP,Region7 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 6. "SAFG9RP,Region6 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 5. "SAFG10RP,Region5 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 4. "SAFG11RP,Region4 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 3. "SAFG12RP,Region3 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 2. "SAFG13RP,Region2 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 1. "SAFG14RP,Region1 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 0. "SAFG15RP,Region0 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
group.long 0x48++0x03
line.long 0x00 "SECCTRR2D,Function: Privilege setting of each secure region"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
bitfld.long 0x00 19. "SECG0RP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 18. "SECG1RP,Public Group Read Privilege Setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 17. "SECG2RP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 16. "SECG3RP,Secure Group Read Privilege Setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 15. "SAFG0RP,Region15 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 14. "SAFG1RP,Region14 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 13. "SAFG2RP,Region13 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 12. "SAFG3RP,Region12 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 11. "SAFG4RP,Region11 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 10. "SAFG5RP,Region10 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 9. "SAFG6RP,Region9 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 8. "SAFG7RP,Region8 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 7. "SAFG8RP,Region7 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 6. "SAFG9RP,Region6 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 5. "SAFG10RP,Region5 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 4. "SAFG11RP,Region4 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 3. "SAFG12RP,Region3 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 2. "SAFG13RP,Region2 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 1. "SAFG14RP,Region1 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 0. "SAFG15RP,Region0 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
group.long 0x4C++0x03
line.long 0x00 "SECCTRR3D,Function: Privilege setting of each secure region"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
bitfld.long 0x00 19. "SECG0RP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 18. "SECG1RP,Public Group Read Privilege Setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 17. "SECG2RP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 16. "SECG3RP,Secure Group Read Privilege Setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 15. "SAFG0RP,Region15 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 14. "SAFG1RP,Region14 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 13. "SAFG2RP,Region13 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 12. "SAFG3RP,Region12 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 11. "SAFG4RP,Region11 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 10. "SAFG5RP,Region10 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 9. "SAFG6RP,Region9 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 8. "SAFG7RP,Region8 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 7. "SAFG8RP,Region7 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 6. "SAFG9RP,Region6 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 5. "SAFG10RP,Region5 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 4. "SAFG11RP,Region4 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 3. "SAFG12RP,Region3 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 2. "SAFG13RP,Region2 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 1. "SAFG14RP,Region1 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 0. "SAFG15RP,Region0 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
group.long 0x50++0x03
line.long 0x00 "SECCTRR4D,Function: Privilege setting of each secure region"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
bitfld.long 0x00 19. "SECG0RP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 18. "SECG1RP,Public Group Read Privilege Setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 17. "SECG2RP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 16. "SECG3RP,Secure Group Read Privilege Setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 15. "SAFG0RP,Region15 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 14. "SAFG1RP,Region14 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 13. "SAFG2RP,Region13 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 12. "SAFG3RP,Region12 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 11. "SAFG4RP,Region11 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 10. "SAFG5RP,Region10 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 9. "SAFG6RP,Region9 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 8. "SAFG7RP,Region8 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 7. "SAFG8RP,Region7 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 6. "SAFG9RP,Region6 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 5. "SAFG10RP,Region5 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 4. "SAFG11RP,Region4 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 3. "SAFG12RP,Region3 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 2. "SAFG13RP,Region2 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 1. "SAFG14RP,Region1 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 0. "SAFG15RP,Region0 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
group.long 0x54++0x03
line.long 0x00 "SECCTRR5D,Function: Privilege setting of each secure region"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
bitfld.long 0x00 19. "SECG0RP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 18. "SECG1RP,Public Group Read Privilege Setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 17. "SECG2RP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 16. "SECG3RP,Secure Group Read Privilege Setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 15. "SAFG0RP,Region15 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 14. "SAFG1RP,Region14 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 13. "SAFG2RP,Region13 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 12. "SAFG3RP,Region12 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 11. "SAFG4RP,Region11 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 10. "SAFG5RP,Region10 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 9. "SAFG6RP,Region9 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 8. "SAFG7RP,Region8 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 7. "SAFG8RP,Region7 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 6. "SAFG9RP,Region6 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 5. "SAFG10RP,Region5 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 4. "SAFG11RP,Region4 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 3. "SAFG12RP,Region3 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 2. "SAFG13RP,Region2 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 1. "SAFG14RP,Region1 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 0. "SAFG15RP,Region0 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
group.long 0x58++0x03
line.long 0x00 "SECCTRR6D,Function: Privilege setting of each secure region"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
bitfld.long 0x00 19. "SECG0RP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 18. "SECG1RP,Public Group Read Privilege Setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 17. "SECG2RP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 16. "SECG3RP,Secure Group Read Privilege Setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 15. "SAFG0RP,Region15 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 14. "SAFG1RP,Region14 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 13. "SAFG2RP,Region13 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 12. "SAFG3RP,Region12 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 11. "SAFG4RP,Region11 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 10. "SAFG5RP,Region10 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 9. "SAFG6RP,Region9 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 8. "SAFG7RP,Region8 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 7. "SAFG8RP,Region7 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 6. "SAFG9RP,Region6 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 5. "SAFG10RP,Region5 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 4. "SAFG11RP,Region4 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 3. "SAFG12RP,Region3 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 2. "SAFG13RP,Region2 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 1. "SAFG14RP,Region1 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 0. "SAFG15RP,Region0 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
group.long 0x5C++0x03
line.long 0x00 "SECCTRR7D,Function: Privilege setting of each secure region"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
bitfld.long 0x00 19. "SECG0RP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 18. "SECG1RP,Public Group Read Privilege Setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 17. "SECG2RP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 16. "SECG3RP,Secure Group Read Privilege Setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 15. "SAFG0RP,Region15 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 14. "SAFG1RP,Region14 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 13. "SAFG2RP,Region13 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 12. "SAFG3RP,Region12 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 11. "SAFG4RP,Region11 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 10. "SAFG5RP,Region10 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 9. "SAFG6RP,Region9 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 8. "SAFG7RP,Region8 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 7. "SAFG8RP,Region7 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 6. "SAFG9RP,Region6 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 5. "SAFG10RP,Region5 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 4. "SAFG11RP,Region4 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 3. "SAFG12RP,Region3 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 2. "SAFG13RP,Region2 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 1. "SAFG14RP,Region1 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 0. "SAFG15RP,Region0 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
group.long 0x60++0x03
line.long 0x00 "SECCTRR8D,Function: Privilege setting of each secure region"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
bitfld.long 0x00 19. "SECG0RP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 18. "SECG1RP,Public Group Read Privilege Setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 17. "SECG2RP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 16. "SECG3RP,Secure Group Read Privilege Setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 15. "SAFG0RP,Region15 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 14. "SAFG1RP,Region14 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 13. "SAFG2RP,Region13 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 12. "SAFG3RP,Region12 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 11. "SAFG4RP,Region11 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 10. "SAFG5RP,Region10 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 9. "SAFG6RP,Region9 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 8. "SAFG7RP,Region8 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 7. "SAFG8RP,Region7 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 6. "SAFG9RP,Region6 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 5. "SAFG10RP,Region5 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 4. "SAFG11RP,Region4 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 3. "SAFG12RP,Region3 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 2. "SAFG13RP,Region2 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 1. "SAFG14RP,Region1 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 0. "SAFG15RP,Region0 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
group.long 0x64++0x03
line.long 0x00 "SECCTRR9D,Function: Privilege setting of each secure region"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
bitfld.long 0x00 19. "SECG0RP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 18. "SECG1RP,Public Group Read Privilege Setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 17. "SECG2RP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 16. "SECG3RP,Secure Group Read Privilege Setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 15. "SAFG0RP,Region15 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 14. "SAFG1RP,Region14 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 13. "SAFG2RP,Region13 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 12. "SAFG3RP,Region12 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 11. "SAFG4RP,Region11 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 10. "SAFG5RP,Region10 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 9. "SAFG6RP,Region9 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 8. "SAFG7RP,Region8 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 7. "SAFG8RP,Region7 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 6. "SAFG9RP,Region6 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 5. "SAFG10RP,Region5 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 4. "SAFG11RP,Region4 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 3. "SAFG12RP,Region3 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 2. "SAFG13RP,Region2 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 1. "SAFG14RP,Region1 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 0. "SAFG15RP,Region0 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
group.long 0x68++0x03
line.long 0x00 "SECCTRR10D,Function: Privilege setting of each secure region"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
bitfld.long 0x00 19. "SECG0RP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 18. "SECG1RP,Public Group Read Privilege Setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 17. "SECG2RP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 16. "SECG3RP,Secure Group Read Privilege Setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 15. "SAFG0RP,Region15 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 14. "SAFG1RP,Region14 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 13. "SAFG2RP,Region13 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 12. "SAFG3RP,Region12 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 11. "SAFG4RP,Region11 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 10. "SAFG5RP,Region10 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 9. "SAFG6RP,Region9 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 8. "SAFG7RP,Region8 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 7. "SAFG8RP,Region7 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 6. "SAFG9RP,Region6 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 5. "SAFG10RP,Region5 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 4. "SAFG11RP,Region4 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 3. "SAFG12RP,Region3 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 2. "SAFG13RP,Region2 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 1. "SAFG14RP,Region1 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 0. "SAFG15RP,Region0 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
group.long 0x6C++0x03
line.long 0x00 "SECCTRR11D,Function: Privilege setting of each secure region"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
bitfld.long 0x00 19. "SECG0RP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 18. "SECG1RP,Public Group Read Privilege Setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 17. "SECG2RP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 16. "SECG3RP,Secure Group Read Privilege Setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 15. "SAFG0RP,Region15 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 14. "SAFG1RP,Region14 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 13. "SAFG2RP,Region13 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 12. "SAFG3RP,Region12 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 11. "SAFG4RP,Region11 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 10. "SAFG5RP,Region10 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 9. "SAFG6RP,Region9 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 8. "SAFG7RP,Region8 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 7. "SAFG8RP,Region7 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 6. "SAFG9RP,Region6 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 5. "SAFG10RP,Region5 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 4. "SAFG11RP,Region4 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 3. "SAFG12RP,Region3 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 2. "SAFG13RP,Region2 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 1. "SAFG14RP,Region1 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 0. "SAFG15RP,Region0 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
group.long 0x70++0x03
line.long 0x00 "SECCTRR12D,Function: Privilege setting of each secure region"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
bitfld.long 0x00 19. "SECG0RP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 18. "SECG1RP,Public Group Read Privilege Setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 17. "SECG2RP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 16. "SECG3RP,Secure Group Read Privilege Setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 15. "SAFG0RP,Region15 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 14. "SAFG1RP,Region14 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 13. "SAFG2RP,Region13 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 12. "SAFG3RP,Region12 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 11. "SAFG4RP,Region11 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 10. "SAFG5RP,Region10 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 9. "SAFG6RP,Region9 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 8. "SAFG7RP,Region8 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 7. "SAFG8RP,Region7 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 6. "SAFG9RP,Region6 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 5. "SAFG10RP,Region5 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 4. "SAFG11RP,Region4 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 3. "SAFG12RP,Region3 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 2. "SAFG13RP,Region2 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 1. "SAFG14RP,Region1 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 0. "SAFG15RP,Region0 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
group.long 0x74++0x03
line.long 0x00 "SECCTRR13D,Function: Privilege setting of each secure region"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
bitfld.long 0x00 19. "SECG0RP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 18. "SECG1RP,Public Group Read Privilege Setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 17. "SECG2RP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 16. "SECG3RP,Secure Group Read Privilege Setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 15. "SAFG0RP,Region15 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 14. "SAFG1RP,Region14 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 13. "SAFG2RP,Region13 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 12. "SAFG3RP,Region12 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 11. "SAFG4RP,Region11 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 10. "SAFG5RP,Region10 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 9. "SAFG6RP,Region9 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 8. "SAFG7RP,Region8 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 7. "SAFG8RP,Region7 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 6. "SAFG9RP,Region6 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 5. "SAFG10RP,Region5 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 4. "SAFG11RP,Region4 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 3. "SAFG12RP,Region3 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 2. "SAFG13RP,Region2 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 1. "SAFG14RP,Region1 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 0. "SAFG15RP,Region0 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
group.long 0x78++0x03
line.long 0x00 "SECCTRR14D,Function: Privilege setting of each secure region"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
bitfld.long 0x00 19. "SECG0RP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 18. "SECG1RP,Public Group Read Privilege Setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 17. "SECG2RP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 16. "SECG3RP,Secure Group Read Privilege Setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 15. "SAFG0RP,Region15 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 14. "SAFG1RP,Region14 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 13. "SAFG2RP,Region13 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 12. "SAFG3RP,Region12 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 11. "SAFG4RP,Region11 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 10. "SAFG5RP,Region10 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 9. "SAFG6RP,Region9 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 8. "SAFG7RP,Region8 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 7. "SAFG8RP,Region7 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 6. "SAFG9RP,Region6 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 5. "SAFG10RP,Region5 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 4. "SAFG11RP,Region4 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 3. "SAFG12RP,Region3 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 2. "SAFG13RP,Region2 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 1. "SAFG14RP,Region1 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 0. "SAFG15RP,Region0 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
group.long 0x7C++0x03
line.long 0x00 "SECCTRR15D,Function: Privilege setting of each secure region"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
bitfld.long 0x00 19. "SECG0RP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 18. "SECG1RP,Public Group Read Privilege Setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 17. "SECG2RP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 16. "SECG3RP,Secure Group Read Privilege Setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 15. "SAFG0RP,Region15 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 14. "SAFG1RP,Region14 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 13. "SAFG2RP,Region13 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 12. "SAFG3RP,Region12 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 11. "SAFG4RP,Region11 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 10. "SAFG5RP,Region10 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 9. "SAFG6RP,Region9 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 8. "SAFG7RP,Region8 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 7. "SAFG8RP,Region7 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 6. "SAFG9RP,Region6 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 5. "SAFG10RP,Region5 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 4. "SAFG11RP,Region4 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 3. "SAFG12RP,Region3 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 2. "SAFG13RP,Region2 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 1. "SAFG14RP,Region1 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 0. "SAFG15RP,Region0 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
group.long 0x340++0x03
line.long 0x00 "SECCTRW0D,Function: Privilege setting of each secure region"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
bitfld.long 0x00 19. "SECG0WP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 18. "SECG1WP,Public Group Write Privilege Setting" "0: Has the privilege to Write to the relevant,1: Does not have the privilege Write to the"
bitfld.long 0x00 17. "SECG2WP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 16. "SECG3WP,Secure Group Write Privilege Setting" "0: Has the privilege to Write to the relevant,1: Does not have the privilege Write to the"
bitfld.long 0x00 15. "SAFG0WP,Region15 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 14. "SAFG1WP,Region14 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 13. "SAFG2WP,Region13 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 12. "SAFG3WP,Region12 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 11. "SAFG4WP,Region11 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 10. "SAFG5WP,Region10 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 9. "SAFG6WP,Region9 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 8. "SAFG7WP,Region8 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 7. "SAFG8WP,Region7 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 6. "SAFG9WP,Region6 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 5. "SAFG10WP,Region5 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 4. "SAFG11WP,Region4 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 3. "SAFG12WP,Region3 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 2. "SAFG13WP,Region2 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 1. "SAFG14WP,Region1 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 0. "SAFG15WP,Region0 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
group.long 0x344++0x03
line.long 0x00 "SECCTRW1D,Function: Privilege setting of each secure region"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
bitfld.long 0x00 19. "SECG0WP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 18. "SECG1WP,Public Group Write Privilege Setting" "0: Has the privilege to Write to the relevant,1: Does not have the privilege Write to the"
bitfld.long 0x00 17. "SECG2WP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 16. "SECG3WP,Secure Group Write Privilege Setting" "0: Has the privilege to Write to the relevant,1: Does not have the privilege Write to the"
bitfld.long 0x00 15. "SAFG0WP,Region15 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 14. "SAFG1WP,Region14 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 13. "SAFG2WP,Region13 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 12. "SAFG3WP,Region12 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 11. "SAFG4WP,Region11 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 10. "SAFG5WP,Region10 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 9. "SAFG6WP,Region9 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 8. "SAFG7WP,Region8 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 7. "SAFG8WP,Region7 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 6. "SAFG9WP,Region6 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 5. "SAFG10WP,Region5 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 4. "SAFG11WP,Region4 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 3. "SAFG12WP,Region3 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 2. "SAFG13WP,Region2 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 1. "SAFG14WP,Region1 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 0. "SAFG15WP,Region0 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
group.long 0x348++0x03
line.long 0x00 "SECCTRW2D,Function: Privilege setting of each secure region"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
bitfld.long 0x00 19. "SECG0WP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 18. "SECG1WP,Public Group Write Privilege Setting" "0: Has the privilege to Write to the relevant,1: Does not have the privilege Write to the"
bitfld.long 0x00 17. "SECG2WP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 16. "SECG3WP,Secure Group Write Privilege Setting" "0: Has the privilege to Write to the relevant,1: Does not have the privilege Write to the"
bitfld.long 0x00 15. "SAFG0WP,Region15 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 14. "SAFG1WP,Region14 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 13. "SAFG2WP,Region13 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 12. "SAFG3WP,Region12 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 11. "SAFG4WP,Region11 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 10. "SAFG5WP,Region10 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 9. "SAFG6WP,Region9 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 8. "SAFG7WP,Region8 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 7. "SAFG8WP,Region7 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 6. "SAFG9WP,Region6 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 5. "SAFG10WP,Region5 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 4. "SAFG11WP,Region4 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 3. "SAFG12WP,Region3 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 2. "SAFG13WP,Region2 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 1. "SAFG14WP,Region1 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 0. "SAFG15WP,Region0 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
group.long 0x34C++0x03
line.long 0x00 "SECCTRW3D,Function: Privilege setting of each secure region"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
bitfld.long 0x00 19. "SECG0WP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 18. "SECG1WP,Public Group Write Privilege Setting" "0: Has the privilege to Write to the relevant,1: Does not have the privilege Write to the"
bitfld.long 0x00 17. "SECG2WP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 16. "SECG3WP,Secure Group Write Privilege Setting" "0: Has the privilege to Write to the relevant,1: Does not have the privilege Write to the"
bitfld.long 0x00 15. "SAFG0WP,Region15 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 14. "SAFG1WP,Region14 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 13. "SAFG2WP,Region13 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 12. "SAFG3WP,Region12 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 11. "SAFG4WP,Region11 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 10. "SAFG5WP,Region10 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 9. "SAFG6WP,Region9 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 8. "SAFG7WP,Region8 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 7. "SAFG8WP,Region7 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 6. "SAFG9WP,Region6 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 5. "SAFG10WP,Region5 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 4. "SAFG11WP,Region4 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 3. "SAFG12WP,Region3 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 2. "SAFG13WP,Region2 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 1. "SAFG14WP,Region1 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 0. "SAFG15WP,Region0 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
group.long 0x350++0x03
line.long 0x00 "SECCTRW4D,Function: Privilege setting of each secure region"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
bitfld.long 0x00 19. "SECG0WP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 18. "SECG1WP,Public Group Write Privilege Setting" "0: Has the privilege to Write to the relevant,1: Does not have the privilege Write to the"
bitfld.long 0x00 17. "SECG2WP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 16. "SECG3WP,Secure Group Write Privilege Setting" "0: Has the privilege to Write to the relevant,1: Does not have the privilege Write to the"
bitfld.long 0x00 15. "SAFG0WP,Region15 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 14. "SAFG1WP,Region14 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 13. "SAFG2WP,Region13 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 12. "SAFG3WP,Region12 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 11. "SAFG4WP,Region11 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 10. "SAFG5WP,Region10 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 9. "SAFG6WP,Region9 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 8. "SAFG7WP,Region8 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 7. "SAFG8WP,Region7 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 6. "SAFG9WP,Region6 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 5. "SAFG10WP,Region5 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 4. "SAFG11WP,Region4 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 3. "SAFG12WP,Region3 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 2. "SAFG13WP,Region2 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 1. "SAFG14WP,Region1 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 0. "SAFG15WP,Region0 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
group.long 0x354++0x03
line.long 0x00 "SECCTRW5D,Function: Privilege setting of each secure region"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
bitfld.long 0x00 19. "SECG0WP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 18. "SECG1WP,Public Group Write Privilege Setting" "0: Has the privilege to Write to the relevant,1: Does not have the privilege Write to the"
bitfld.long 0x00 17. "SECG2WP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 16. "SECG3WP,Secure Group Write Privilege Setting" "0: Has the privilege to Write to the relevant,1: Does not have the privilege Write to the"
bitfld.long 0x00 15. "SAFG0WP,Region15 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 14. "SAFG1WP,Region14 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 13. "SAFG2WP,Region13 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 12. "SAFG3WP,Region12 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 11. "SAFG4WP,Region11 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 10. "SAFG5WP,Region10 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 9. "SAFG6WP,Region9 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 8. "SAFG7WP,Region8 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 7. "SAFG8WP,Region7 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 6. "SAFG9WP,Region6 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 5. "SAFG10WP,Region5 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 4. "SAFG11WP,Region4 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 3. "SAFG12WP,Region3 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 2. "SAFG13WP,Region2 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 1. "SAFG14WP,Region1 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 0. "SAFG15WP,Region0 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
group.long 0x358++0x03
line.long 0x00 "SECCTRW6D,Function: Privilege setting of each secure region"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
bitfld.long 0x00 19. "SECG0WP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 18. "SECG1WP,Public Group Write Privilege Setting" "0: Has the privilege to Write to the relevant,1: Does not have the privilege Write to the"
bitfld.long 0x00 17. "SECG2WP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 16. "SECG3WP,Secure Group Write Privilege Setting" "0: Has the privilege to Write to the relevant,1: Does not have the privilege Write to the"
bitfld.long 0x00 15. "SAFG0WP,Region15 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 14. "SAFG1WP,Region14 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 13. "SAFG2WP,Region13 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 12. "SAFG3WP,Region12 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 11. "SAFG4WP,Region11 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 10. "SAFG5WP,Region10 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 9. "SAFG6WP,Region9 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 8. "SAFG7WP,Region8 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 7. "SAFG8WP,Region7 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 6. "SAFG9WP,Region6 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 5. "SAFG10WP,Region5 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 4. "SAFG11WP,Region4 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 3. "SAFG12WP,Region3 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 2. "SAFG13WP,Region2 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 1. "SAFG14WP,Region1 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 0. "SAFG15WP,Region0 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
group.long 0x35C++0x03
line.long 0x00 "SECCTRW7D,Function: Privilege setting of each secure region"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
bitfld.long 0x00 19. "SECG0WP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 18. "SECG1WP,Public Group Write Privilege Setting" "0: Has the privilege to Write to the relevant,1: Does not have the privilege Write to the"
bitfld.long 0x00 17. "SECG2WP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 16. "SECG3WP,Secure Group Write Privilege Setting" "0: Has the privilege to Write to the relevant,1: Does not have the privilege Write to the"
bitfld.long 0x00 15. "SAFG0WP,Region15 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 14. "SAFG1WP,Region14 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 13. "SAFG2WP,Region13 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 12. "SAFG3WP,Region12 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 11. "SAFG4WP,Region11 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 10. "SAFG5WP,Region10 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 9. "SAFG6WP,Region9 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 8. "SAFG7WP,Region8 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 7. "SAFG8WP,Region7 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 6. "SAFG9WP,Region6 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 5. "SAFG10WP,Region5 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 4. "SAFG11WP,Region4 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 3. "SAFG12WP,Region3 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 2. "SAFG13WP,Region2 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 1. "SAFG14WP,Region1 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 0. "SAFG15WP,Region0 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
group.long 0x360++0x03
line.long 0x00 "SECCTRW8D,Function: Privilege setting of each secure region"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
bitfld.long 0x00 19. "SECG0WP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 18. "SECG1WP,Public Group Write Privilege Setting" "0: Has the privilege to Write to the relevant,1: Does not have the privilege Write to the"
bitfld.long 0x00 17. "SECG2WP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 16. "SECG3WP,Secure Group Write Privilege Setting" "0: Has the privilege to Write to the relevant,1: Does not have the privilege Write to the"
bitfld.long 0x00 15. "SAFG0WP,Region15 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 14. "SAFG1WP,Region14 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 13. "SAFG2WP,Region13 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 12. "SAFG3WP,Region12 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 11. "SAFG4WP,Region11 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 10. "SAFG5WP,Region10 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 9. "SAFG6WP,Region9 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 8. "SAFG7WP,Region8 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 7. "SAFG8WP,Region7 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 6. "SAFG9WP,Region6 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 5. "SAFG10WP,Region5 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 4. "SAFG11WP,Region4 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 3. "SAFG12WP,Region3 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 2. "SAFG13WP,Region2 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 1. "SAFG14WP,Region1 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 0. "SAFG15WP,Region0 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
group.long 0x364++0x03
line.long 0x00 "SECCTRW9D,Function: Privilege setting of each secure region"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
bitfld.long 0x00 19. "SECG0WP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 18. "SECG1WP,Public Group Write Privilege Setting" "0: Has the privilege to Write to the relevant,1: Does not have the privilege Write to the"
bitfld.long 0x00 17. "SECG2WP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 16. "SECG3WP,Secure Group Write Privilege Setting" "0: Has the privilege to Write to the relevant,1: Does not have the privilege Write to the"
bitfld.long 0x00 15. "SAFG0WP,Region15 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 14. "SAFG1WP,Region14 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 13. "SAFG2WP,Region13 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 12. "SAFG3WP,Region12 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 11. "SAFG4WP,Region11 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 10. "SAFG5WP,Region10 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 9. "SAFG6WP,Region9 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 8. "SAFG7WP,Region8 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 7. "SAFG8WP,Region7 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 6. "SAFG9WP,Region6 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 5. "SAFG10WP,Region5 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 4. "SAFG11WP,Region4 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 3. "SAFG12WP,Region3 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 2. "SAFG13WP,Region2 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 1. "SAFG14WP,Region1 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 0. "SAFG15WP,Region0 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
group.long 0x368++0x03
line.long 0x00 "SECCTRW10D,Function: Privilege setting of each secure region"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
bitfld.long 0x00 19. "SECG0WP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 18. "SECG1WP,Public Group Write Privilege Setting" "0: Has the privilege to Write to the relevant,1: Does not have the privilege Write to the"
bitfld.long 0x00 17. "SECG2WP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 16. "SECG3WP,Secure Group Write Privilege Setting" "0: Has the privilege to Write to the relevant,1: Does not have the privilege Write to the"
bitfld.long 0x00 15. "SAFG0WP,Region15 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 14. "SAFG1WP,Region14 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 13. "SAFG2WP,Region13 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 12. "SAFG3WP,Region12 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 11. "SAFG4WP,Region11 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 10. "SAFG5WP,Region10 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 9. "SAFG6WP,Region9 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 8. "SAFG7WP,Region8 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 7. "SAFG8WP,Region7 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 6. "SAFG9WP,Region6 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 5. "SAFG10WP,Region5 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 4. "SAFG11WP,Region4 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 3. "SAFG12WP,Region3 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 2. "SAFG13WP,Region2 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 1. "SAFG14WP,Region1 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 0. "SAFG15WP,Region0 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
group.long 0x36C++0x03
line.long 0x00 "SECCTRW11D,Function: Privilege setting of each secure region"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
bitfld.long 0x00 19. "SECG0WP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 18. "SECG1WP,Public Group Write Privilege Setting" "0: Has the privilege to Write to the relevant,1: Does not have the privilege Write to the"
bitfld.long 0x00 17. "SECG2WP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 16. "SECG3WP,Secure Group Write Privilege Setting" "0: Has the privilege to Write to the relevant,1: Does not have the privilege Write to the"
bitfld.long 0x00 15. "SAFG0WP,Region15 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 14. "SAFG1WP,Region14 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 13. "SAFG2WP,Region13 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 12. "SAFG3WP,Region12 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 11. "SAFG4WP,Region11 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 10. "SAFG5WP,Region10 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 9. "SAFG6WP,Region9 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 8. "SAFG7WP,Region8 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 7. "SAFG8WP,Region7 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 6. "SAFG9WP,Region6 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 5. "SAFG10WP,Region5 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 4. "SAFG11WP,Region4 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 3. "SAFG12WP,Region3 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 2. "SAFG13WP,Region2 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 1. "SAFG14WP,Region1 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 0. "SAFG15WP,Region0 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
group.long 0x370++0x03
line.long 0x00 "SECCTRW12D,Function: Privilege setting of each secure region"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
bitfld.long 0x00 19. "SECG0WP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 18. "SECG1WP,Public Group Write Privilege Setting" "0: Has the privilege to Write to the relevant,1: Does not have the privilege Write to the"
bitfld.long 0x00 17. "SECG2WP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 16. "SECG3WP,Secure Group Write Privilege Setting" "0: Has the privilege to Write to the relevant,1: Does not have the privilege Write to the"
bitfld.long 0x00 15. "SAFG0WP,Region15 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 14. "SAFG1WP,Region14 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 13. "SAFG2WP,Region13 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 12. "SAFG3WP,Region12 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 11. "SAFG4WP,Region11 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 10. "SAFG5WP,Region10 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 9. "SAFG6WP,Region9 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 8. "SAFG7WP,Region8 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 7. "SAFG8WP,Region7 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 6. "SAFG9WP,Region6 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 5. "SAFG10WP,Region5 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 4. "SAFG11WP,Region4 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 3. "SAFG12WP,Region3 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 2. "SAFG13WP,Region2 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 1. "SAFG14WP,Region1 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 0. "SAFG15WP,Region0 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
group.long 0x374++0x03
line.long 0x00 "SECCTRW13D,Function: Privilege setting of each secure region"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
bitfld.long 0x00 19. "SECG0WP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 18. "SECG1WP,Public Group Write Privilege Setting" "0: Has the privilege to Write to the relevant,1: Does not have the privilege Write to the"
bitfld.long 0x00 17. "SECG2WP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 16. "SECG3WP,Secure Group Write Privilege Setting" "0: Has the privilege to Write to the relevant,1: Does not have the privilege Write to the"
bitfld.long 0x00 15. "SAFG0WP,Region15 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 14. "SAFG1WP,Region14 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 13. "SAFG2WP,Region13 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 12. "SAFG3WP,Region12 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 11. "SAFG4WP,Region11 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 10. "SAFG5WP,Region10 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 9. "SAFG6WP,Region9 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 8. "SAFG7WP,Region8 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 7. "SAFG8WP,Region7 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 6. "SAFG9WP,Region6 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 5. "SAFG10WP,Region5 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 4. "SAFG11WP,Region4 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 3. "SAFG12WP,Region3 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 2. "SAFG13WP,Region2 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 1. "SAFG14WP,Region1 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 0. "SAFG15WP,Region0 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
group.long 0x378++0x03
line.long 0x00 "SECCTRW14D,Function: Privilege setting of each secure region"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
bitfld.long 0x00 19. "SECG0WP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 18. "SECG1WP,Public Group Write Privilege Setting" "0: Has the privilege to Write to the relevant,1: Does not have the privilege Write to the"
bitfld.long 0x00 17. "SECG2WP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 16. "SECG3WP,Secure Group Write Privilege Setting" "0: Has the privilege to Write to the relevant,1: Does not have the privilege Write to the"
bitfld.long 0x00 15. "SAFG0WP,Region15 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 14. "SAFG1WP,Region14 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 13. "SAFG2WP,Region13 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 12. "SAFG3WP,Region12 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 11. "SAFG4WP,Region11 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 10. "SAFG5WP,Region10 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 9. "SAFG6WP,Region9 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 8. "SAFG7WP,Region8 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 7. "SAFG8WP,Region7 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 6. "SAFG9WP,Region6 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 5. "SAFG10WP,Region5 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 4. "SAFG11WP,Region4 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 3. "SAFG12WP,Region3 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 2. "SAFG13WP,Region2 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 1. "SAFG14WP,Region1 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 0. "SAFG15WP,Region0 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
group.long 0x37C++0x03
line.long 0x00 "SECCTRW15D,Function: Privilege setting of each secure region"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
bitfld.long 0x00 19. "SECG0WP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 18. "SECG1WP,Public Group Write Privilege Setting" "0: Has the privilege to Write to the relevant,1: Does not have the privilege Write to the"
bitfld.long 0x00 17. "SECG2WP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 16. "SECG3WP,Secure Group Write Privilege Setting" "0: Has the privilege to Write to the relevant,1: Does not have the privilege Write to the"
bitfld.long 0x00 15. "SAFG0WP,Region15 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 14. "SAFG1WP,Region14 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 13. "SAFG2WP,Region13 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 12. "SAFG3WP,Region12 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 11. "SAFG4WP,Region11 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 10. "SAFG5WP,Region10 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 9. "SAFG6WP,Region9 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 8. "SAFG7WP,Region8 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 7. "SAFG8WP,Region7 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 6. "SAFG9WP,Region6 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 5. "SAFG10WP,Region5 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 4. "SAFG11WP,Region4 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 3. "SAFG12WP,Region3 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 2. "SAFG13WP,Region2 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 1. "SAFG14WP,Region1 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 0. "SAFG15WP,Region0 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
group.long 0x20A0++0x03
line.long 0x00 "ICUSECCAUSE,Function: Secure error cause by ICUMX"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
bitfld.long 0x00 16. "LOCK,ICUMX secure error cause and information is locked" "0,1"
newline
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved These bits are always read as 0"
bitfld.long 0x00 1. "SECERR_R,Secure error detect of read port" "0,1"
newline
bitfld.long 0x00 0. "SECERR_W,Secure error detect of write port" "0,1"
group.long 0x20A4++0x03
line.long 0x00 "ICUSAFCAUSE,"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
bitfld.long 0x00 16. "LOCK,Safety error cause and information is locked" "0,1"
newline
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved These bits are always read as 0"
bitfld.long 0x00 1. "SAFERR_R,Safety error detect of read port" "0,1"
newline
bitfld.long 0x00 0. "SAFERR_W,Safety error detect of write port" "0,1"
group.long 0x20A8++0x03
line.long 0x00 "ICUSECERRINF0,Function: Secure error information (error ID) by ICUMX"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long 0x00 0.--24. 1. "SECERRID,Secure error axid Write 1 to ICUSECCAUSE.LOCK for clear"
group.long 0x20AC++0x03
line.long 0x00 "ICUSECERRINF1,Function: Secure error information (error address) by ICUMX"
hexmask.long 0x00 0.--31. 1. "SECERRADDR,Secure error axaddr [31:0] Write 1 to ICUSECCAUSE.LOCK for clear"
group.long 0x20B0++0x03
line.long 0x00 "ICUSAFERRINF0,"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long 0x00 0.--24. 1. "SAFERRID,Safety error axid Write 1 to ICUSAFCAUSER.LOCK for clear"
group.long 0x20B4++0x03
line.long 0x00 "ICUSAFERRINF1,"
hexmask.long 0x00 0.--31. 1. "SAFERRADDR,Safety error axaddr [31:0] Write 1 to ICUSAFCAUSER.LOCK for clear"
group.long 0x2104++0x03
line.long 0x00 "ICUERRBUSCAUSE,"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "ECC_OVF,ECC 1bit/2bit EAB Overflow" "0: No ECC 1bit/2bit EAB Overflow Write by,1: Clear this bit"
newline
bitfld.long 0x00 6. "ECC_RD_DED,ECC Error detect of Memory Read Data (DED/2bit)" "0: No ECC 2bit Error Write by,1: Clear this bit"
bitfld.long 0x00 5. "ECC_RD_SED,ECC Error detect of Memory Read Data (SED/1bit)" "0: No ECC 1bit Error Write by,1: Clear this bit"
newline
bitfld.long 0x00 4. "EDC_WR,EDC Error detect of AXI2RAM Internal Write Data" "0: No Internal Write data ECC Error Write by,1: Clear this bit"
rbitfld.long 0x00 3. "Reserved_3,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 2. "EDC_W,EDC Error detect of AXI W channel 1: AXI Wch EDC error" "0: No AXI Wch EDC error Write by,1: Clear this bit"
bitfld.long 0x00 1. "EDC_AW,EDC Error detect of AXI AW channel 1: AXI AWch EDC error" "0: No AXI AWch EDC error Write by,1: Clear this bit"
newline
bitfld.long 0x00 0. "EDC_AR,EDC Error detect of AXI AR channel 1: AXI ARch EDC error" "0: No AXI ARch EDC error Write by,1: Clear this bit"
group.long 0x2110++0x03
line.long 0x00 "ICUERRBUSINF0,Function: EDC error information (error ID) of ICUMX"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long 0x00 0.--24. 1. "ICUERRBUSID,EDC error axid"
group.long 0x2114++0x03
line.long 0x00 "ICUERRBUSINF1,Function: EDC Error Information (error address) excluding by ICUMX"
hexmask.long 0x00 0.--31. 1. "ICUERRBUSADDR,EDC error axaddr"
group.long 0x2188++0x03
line.long 0x00 "ICUAFBERRCAUSE,"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "AFB_ERR,Address Feedback Error when ICUMX accessing" "0: No Address feedback error Write by,1: Clear this bit"
group.long 0x2194++0x03
line.long 0x00 "ICUAFBERRINF0,Function: AFB error information (error ID) of ICUMX"
rbitfld.long 0x00 27.--31. "Reserved_27,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rbitfld.long 0x00 25.--26. "VMCID,VMC ID of AFB error" "0: VMC0,1: VMC1,2: VMC2,3: VMC3"
newline
hexmask.long 0x00 0.--24. 1. "AFBERRID,AFB error axid when ICUMX accessing"
group.long 0x2198++0x03
line.long 0x00 "ICUAFBERRINF1,Function: AFB Error Information (error address) of ICUMX"
hexmask.long 0x00 0.--31. 1. "AFBERRADDR,AFB error axaddr when ICUMX accessing"
group.long 0x2200++0x03
line.long 0x00 "MEM_INIT,Function: Initialization request for the memory"
bitfld.long 0x00 31. "LOCK,Software Reset Lock" "0: Unlock(SWRESET bit writable),1: Lock(SWRESET bit cannot write)"
hexmask.long 0x00 1.--30. 1. "Reserved_1,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 0. "INIT,(*1) Initial value depend on MEMINIT_ENABLE_SYSRAM" "0,1"
group.long 0x4080++0x03
line.long 0x00 "SECCAUSE,Function: Secure error cause excluding by ICUMX"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
bitfld.long 0x00 16. "LOCK,Secure error cause and information is locked" "0,1"
newline
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved These bits are always read as 0"
bitfld.long 0x00 1. "SECERR_R,Secure error detects of read port" "0,1"
newline
bitfld.long 0x00 0. "SECERR_W,Secure error detects of write port" "0,1"
group.long 0x4084++0x03
line.long 0x00 "SAFCAUSE,"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,"
bitfld.long 0x00 16. "LOCK,Safety error cause and information is locked" "0,1"
newline
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,"
bitfld.long 0x00 1. "SAFERR_R,Safety error detect of read port" "0,1"
newline
bitfld.long 0x00 0. "SAFERR_W,Safety error detect of write port" "0,1"
group.long 0x4088++0x03
line.long 0x00 "SECERRINF0,Function: Secure error information (error ID) excluding by ICUMX"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long 0x00 0.--24. 1. "SECERRID,Secure error axid Write 1 to SECCAUSE.LOCK for clear"
group.long 0x408C++0x03
line.long 0x00 "SECERRINF1,Function: Secure Error Information (error address) excluding by ICUMX"
hexmask.long 0x00 0.--31. 1. "SECERRADDR,Secure error axaddr [31:0] Write 1 to SECCAUSE.LOCK for clear"
group.long 0x4090++0x03
line.long 0x00 "SAFERRINF0,"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long 0x00 0.--24. 1. "SAFERRID,Safety error axid Write 1 to SAFCAUSER.LOCK for clear"
group.long 0x4094++0x03
line.long 0x00 "SAFERRINF1,"
hexmask.long 0x00 0.--31. 1. "SAFERRADDR,Safety error axaddr [31:0] Write 1 to SAFCAUSER.LOCK for clear"
group.long 0x4100++0x03
line.long 0x00 "ERRBUSCAUSE,"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "ECC_OVF,ECC 1bit/2bit EAB Overflow" "0: No ECC 1bit/2bit EAB Overflow Write by,1: Clear this bit"
newline
bitfld.long 0x00 6. "ECC_RD_DED,ECC Error detect of Memory Read Data (DED/2bit)" "0: No ECC 2bit Error Write by,1: Clear this bit"
bitfld.long 0x00 5. "ECC_RD_SED,ECC Error detect of Memory Read Data (SED/1bit)" "0: No ECC 1bit Error Write by,1: Clear this bit"
newline
bitfld.long 0x00 4. "EDC_WR,EDC Error detect of AXI2RAM Internal Write Data" "0: No Internal Write data ECC Error Write by,1: Clear this bit"
rbitfld.long 0x00 3. "Reserved_3,Reserved These bits are always read as 0" "0,1"
newline
bitfld.long 0x00 2. "EDC_W,EDC Error detect of AXI W channel 1: AXI Wch EDC error" "0: No AXI Wch EDC error Write by,1: Clear this bit"
bitfld.long 0x00 1. "EDC_AW,EDC Error detect of AXI AW channel 1: AXI AWch EDC error" "0: No AXI AWch EDC error Write by,1: Clear this bit"
newline
bitfld.long 0x00 0. "EDC_AR,EDC Error detect of AXI AR channel 1: AXI ARch EDC error" "0: No AXI ARch EDC error Write by,1: Clear this bit"
group.long 0x4108++0x03
line.long 0x00 "ERRBUSINF0,Function: EDC error information (error ID) excluding by ICUMX"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as 0"
hexmask.long 0x00 0.--24. 1. "ERRBUSID,EDC error axid"
group.long 0x410C++0x03
line.long 0x00 "ERRBUSINF1,Function: EDC Error Information (error address) excluding by ICUMX"
hexmask.long 0x00 0.--31. 1. "ERRBUSADDR,EDC error axaddr"
group.long 0x4120++0x03
line.long 0x00 "ECC_CONTROL,"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "ECC_ENABLE,Read Data ECC correction Enable" "0: Disable,1: Enable"
group.long 0x4124++0x03
line.long 0x00 "EDC_OFF_NO_ECC,"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "EDC_OFF_NO_ECC,Enable ECC value written to Memory when EDC disable" "0: ECC value written to memory,1: ECC value not written to memory"
group.long 0x4128++0x03
line.long 0x00 "ECCINFO,"
hexmask.long.word 0x00 18.--31. 1. "Reserved_18,Reserved These bits are always read as 0"
rbitfld.long 0x00 17. "Reserved_17,EAB info valid" "0: N/A,1: VALID"
newline
rbitfld.long 0x00 15.--16. "VMC_ID,Corresponding VMC number" "0: VMC0,1: VMC1,2: VMC2,3: VMC3"
hexmask.long.word 0x00 0.--14. 1. "ECC_ADDR,ECC 1bit/2bit error ram address"
group.long 0x4130++0x03
line.long 0x00 "APBERRCAUSE,"
hexmask.long 0x00 2.--31. 1. "Reserved_2,Reserved These bits are always read as 0"
bitfld.long 0x00 1. "EDC_WDAT,APB WDATA EDC Error detect" "0: No APB WDATA EDC error Write by,1: Clear this bit"
newline
bitfld.long 0x00 0. "EDC_ADR,APB ADDR EDC Error detect" "0: No APB ADDR EDC error Write by,1: Clear this bit"
group.long 0x4134++0x03
line.long 0x00 "APBERRINF0,Function: EDC error information (error ID) excluding by ICUMX"
hexmask.long 0x00 0.--31. 1. "ERR_ADR,APB EDC error ADDRESS"
group.long 0x4138++0x03
line.long 0x00 "APBERRINF1,Function: EDC Error Information (error address) excluding by ICUMX"
hexmask.long 0x00 0.--31. 1. "ERR_WDAT,APB EDC error WDATA"
group.long 0x4180++0x03
line.long 0x00 "AFBERR,"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "EN_AFB_ERR,AFB Error detect Enable" "0: Not detect Address feedback error,1: Detect Address feedback error"
group.long 0x4184++0x03
line.long 0x00 "AFBERRCAUSE,"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "AFB_ERR,Address Feedback Error excluding ICUMX access" "0: No Address feedback error Write by,1: Clear this bit"
group.long 0x418C++0x03
line.long 0x00 "AFBERRINF0,Function: AFB error information (error ID) excluding by ICUMX"
rbitfld.long 0x00 27.--31. "Reserved_27,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rbitfld.long 0x00 25.--26. "VMCID,VMC ID of AFB error" "0: VMC0,1: VMC1,2: VMC2,3: VMC3"
newline
hexmask.long 0x00 0.--24. 1. "AFBERRID,AFB error axid excluding ICUMX access"
group.long 0x4190++0x03
line.long 0x00 "AFBERRINF1,Function: AFB Error Information (error address) excluding by ICUMX"
hexmask.long 0x00 0.--31. 1. "AFBERRADDR,AFB error axaddr excluding ICUMX access"
group.long 0x4300++0x03
line.long 0x00 "DUMMY_ERROR,"
hexmask.long.word 0x00 23.--31. 1. "Reserved_23,Reserved These bits are always read as 0"
bitfld.long 0x00 22. "DMY_ICU_AFB_ERR,ICU Address Feedback Fault Injection 0 normal 1 Pseudo Error" "0,1"
newline
rbitfld.long 0x00 21. "Reserved_21,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 20. "DMY_ICU_SECERR_p,ERR_AXI2RAM_ICU_SECERR_p" "0,1"
newline
bitfld.long 0x00 19. "DMY_ICU_SAFERR_p,ERR_AXI2RAM_ICU_SAFERR_p" "0,1"
bitfld.long 0x00 18. "DMY_ICU_ECC_2BIT,ERR_AXI2RAM_ICU_ECC_2BIT" "0,1"
newline
bitfld.long 0x00 17. "DMY_ICU_ECC_1BIT,ERR_AXI2RAM_ICU_ECC_1BIT" "0,1"
bitfld.long 0x00 16. "DMY_ICU_EDC,ERR_AXI2RAM_ICU_EDC" "0,1"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
bitfld.long 0x00 8. "dmcmp_err_inj,DCLS compare Fault Injection 0 normal 1 Pseudo Error" "0,1"
newline
bitfld.long 0x00 7. "DMY_APB_ERR,APB EDC Fault Injection 0 normal 1 Pseudo Error" "0,1"
bitfld.long 0x00 6. "DMY_AFB_ERR,Address Feedback Fault Injection 0 normal 1 Pseudo Error" "0,1"
newline
rbitfld.long 0x00 5. "Reserved_5,Reserved These bits are always read as 0" "0,1"
bitfld.long 0x00 4. "DMY_SECERR_p,Pulse ERR_AXI2RAM_SECERR_p" "0,1"
newline
bitfld.long 0x00 3. "DMY_SAFERR_p,ERR_AXI2RAM_SAFERR_p" "0,1"
bitfld.long 0x00 2. "DMY_ECC_2BIT,ERR_AXI2RAM_ECC_2BIT" "0,1"
newline
bitfld.long 0x00 1. "DMY_ECC_1BIT,ERR_AXI2RAM_ECC_1BIT" "0,1"
bitfld.long 0x00 0. "DMY_EDC,ERR_AXI2RAM_EDC" "0,1"
group.long 0x4304++0x03
line.long 0x00 "DMCMP,"
bitfld.long 0x00 31. "compare_enable,DCLS compare enable" "0: Disable and Clear,1: Enable"
hexmask.long.tbyte 0x00 13.--30. 1. "Reserved_13,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 12. "AXI_AR_CMP_ERR,DCLS AXI ARch Compare Error(Secretive)" "0: No Error Set,1: Error"
rbitfld.long 0x00 11. "AXI_AW_CMP_ERR,DCLS AXI AWch Compare Error(Secretive)" "0: No Error Set,1: Error"
newline
rbitfld.long 0x00 10. "AXI_W_CMP_ERR,DCLS AXI Wch Compare Error(Secretive)" "0: No Error Set,1: Error"
rbitfld.long 0x00 9. "AXI_B_CMP_ERR,DCLS AXI Bch Compare Error(Secretive)" "0: No Error Set,1: Error"
newline
rbitfld.long 0x00 8. "AXI_R_CMP_ERR,DCLS AXI Rch Compare Error(Secretive)" "0: No Error Set,1: Error"
rbitfld.long 0x00 7. "VMC0_CMP_ERR,DCLS VMC0 Compare Error(Secretive)" "0: No Error Set,1: Error"
newline
rbitfld.long 0x00 6. "VMC1_CMP_ERR,DCLS VMC1 Compare Error(Secretive)" "0: No Error Set,1: Error"
rbitfld.long 0x00 5. "VMC2_CMP_ERR,DCLS VMC2 Compare Error(Secretive)" "0: No Error Set,1: Error"
newline
rbitfld.long 0x00 4. "VMC3_CMP_ERR,DCLS VMC3 Compare Error(Secretive)" "0: No Error Set,1: Error"
rbitfld.long 0x00 3. "AXI_CMP_ERR,DCLS AXI bus Compare Error" "0: No Error Set,1: Error"
newline
rbitfld.long 0x00 2. "VMC_CMP_ERR,DCLS VMC Compare Error" "0: No Error Set,1: Error"
rbitfld.long 0x00 1. "APB_CMP_ERR,DCLS APB bus Compare Error" "0: No Error Set,1: Error"
newline
rbitfld.long 0x00 0. "REG_CMP_ERR,DCLS Register Compare Error" "0: No Error Set,1: Error"
tree.end
tree "RT_VRAM"
base ad:0xFFEC0000
group.long 0x00++0x03
line.long 0x00 "SECDIV0D,Function: The boundary address setting of the secure region"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--19. 1. "DIVADDR_31_12,Protection division address offset [31:12] is set"
group.long 0x04++0x03
line.long 0x00 "SECDIV1D,Function: The boundary address setting of the secure region"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--19. 1. "DIVADDR_31_12,Protection division address offset [31:12] is set"
group.long 0x08++0x03
line.long 0x00 "SECDIV2D,Function: The boundary address setting of the secure region"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--19. 1. "DIVADDR_31_12,Protection division address offset [31:12] is set"
group.long 0x0C++0x03
line.long 0x00 "SECDIV3D,Function: The boundary address setting of the secure region"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--19. 1. "DIVADDR_31_12,Protection division address offset [31:12] is set"
group.long 0x10++0x03
line.long 0x00 "SECDIV4D,Function: The boundary address setting of the secure region"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--19. 1. "DIVADDR_31_12,Protection division address offset [31:12] is set"
group.long 0x14++0x03
line.long 0x00 "SECDIV5D,Function: The boundary address setting of the secure region"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--19. 1. "DIVADDR_31_12,Protection division address offset [31:12] is set"
group.long 0x18++0x03
line.long 0x00 "SECDIV6D,Function: The boundary address setting of the secure region"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--19. 1. "DIVADDR_31_12,Protection division address offset [31:12] is set"
group.long 0x1C++0x03
line.long 0x00 "SECDIV7D,Function: The boundary address setting of the secure region"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--19. 1. "DIVADDR_31_12,Protection division address offset [31:12] is set"
group.long 0x20++0x03
line.long 0x00 "SECDIV8D,Function: The boundary address setting of the secure region"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--19. 1. "DIVADDR_31_12,Protection division address offset [31:12] is set"
group.long 0x24++0x03
line.long 0x00 "SECDIV9D,Function: The boundary address setting of the secure region"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--19. 1. "DIVADDR_31_12,Protection division address offset [31:12] is set"
group.long 0x28++0x03
line.long 0x00 "SECDIV10D,Function: The boundary address setting of the secure region"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--19. 1. "DIVADDR_31_12,Protection division address offset [31:12] is set"
group.long 0x2C++0x03
line.long 0x00 "SECDIV11D,Function: The boundary address setting of the secure region"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--19. 1. "DIVADDR_31_12,Protection division address offset [31:12] is set"
group.long 0x30++0x03
line.long 0x00 "SECDIV12D,Function: The boundary address setting of the secure region"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--19. 1. "DIVADDR_31_12,Protection division address offset [31:12] is set"
group.long 0x34++0x03
line.long 0x00 "SECDIV13D,Function: The boundary address setting of the secure region"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--19. 1. "DIVADDR_31_12,Protection division address offset [31:12] is set"
group.long 0x38++0x03
line.long 0x00 "SECDIV14D,Function: The boundary address setting of the secure region"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--19. 1. "DIVADDR_31_12,Protection division address offset [31:12] is set"
group.long 0x40++0x03
line.long 0x00 "SECCTRR0D,Function: Privilege setting of each secure region"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
bitfld.long 0x00 19. "SECG0RP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 18. "SECG1RP,Public Group Read Privilege Setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 17. "SECG2RP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 16. "SECG3RP,Secure Group Read Privilege Setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 15. "SAFG0RP,Region15 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 14. "SAFG1RP,Region14 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 13. "SAFG2RP,Region13 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 12. "SAFG3RP,Region12 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 11. "SAFG4RP,Region11 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 10. "SAFG5RP,Region10 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 9. "SAFG6RP,Region9 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 8. "SAFG7RP,Region8 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 7. "SAFG8RP,Region7 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 6. "SAFG9RP,Region6 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 5. "SAFG10RP,Region5 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 4. "SAFG11RP,Region4 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 3. "SAFG12RP,Region3 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 2. "SAFG13RP,Region2 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 1. "SAFG14RP,Region1 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 0. "SAFG15RP,Region0 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
group.long 0x44++0x03
line.long 0x00 "SECCTRR1D,Function: Privilege setting of each secure region"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
bitfld.long 0x00 19. "SECG0RP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 18. "SECG1RP,Public Group Read Privilege Setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 17. "SECG2RP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 16. "SECG3RP,Secure Group Read Privilege Setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 15. "SAFG0RP,Region15 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 14. "SAFG1RP,Region14 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 13. "SAFG2RP,Region13 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 12. "SAFG3RP,Region12 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 11. "SAFG4RP,Region11 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 10. "SAFG5RP,Region10 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 9. "SAFG6RP,Region9 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 8. "SAFG7RP,Region8 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 7. "SAFG8RP,Region7 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 6. "SAFG9RP,Region6 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 5. "SAFG10RP,Region5 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 4. "SAFG11RP,Region4 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 3. "SAFG12RP,Region3 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 2. "SAFG13RP,Region2 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 1. "SAFG14RP,Region1 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 0. "SAFG15RP,Region0 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
group.long 0x48++0x03
line.long 0x00 "SECCTRR2D,Function: Privilege setting of each secure region"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
bitfld.long 0x00 19. "SECG0RP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 18. "SECG1RP,Public Group Read Privilege Setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 17. "SECG2RP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 16. "SECG3RP,Secure Group Read Privilege Setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 15. "SAFG0RP,Region15 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 14. "SAFG1RP,Region14 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 13. "SAFG2RP,Region13 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 12. "SAFG3RP,Region12 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 11. "SAFG4RP,Region11 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 10. "SAFG5RP,Region10 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 9. "SAFG6RP,Region9 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 8. "SAFG7RP,Region8 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 7. "SAFG8RP,Region7 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 6. "SAFG9RP,Region6 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 5. "SAFG10RP,Region5 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 4. "SAFG11RP,Region4 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 3. "SAFG12RP,Region3 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 2. "SAFG13RP,Region2 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 1. "SAFG14RP,Region1 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 0. "SAFG15RP,Region0 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
group.long 0x4C++0x03
line.long 0x00 "SECCTRR3D,Function: Privilege setting of each secure region"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
bitfld.long 0x00 19. "SECG0RP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 18. "SECG1RP,Public Group Read Privilege Setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 17. "SECG2RP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 16. "SECG3RP,Secure Group Read Privilege Setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 15. "SAFG0RP,Region15 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 14. "SAFG1RP,Region14 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 13. "SAFG2RP,Region13 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 12. "SAFG3RP,Region12 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 11. "SAFG4RP,Region11 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 10. "SAFG5RP,Region10 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 9. "SAFG6RP,Region9 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 8. "SAFG7RP,Region8 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 7. "SAFG8RP,Region7 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 6. "SAFG9RP,Region6 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 5. "SAFG10RP,Region5 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 4. "SAFG11RP,Region4 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 3. "SAFG12RP,Region3 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 2. "SAFG13RP,Region2 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 1. "SAFG14RP,Region1 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 0. "SAFG15RP,Region0 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
group.long 0x50++0x03
line.long 0x00 "SECCTRR4D,Function: Privilege setting of each secure region"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
bitfld.long 0x00 19. "SECG0RP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 18. "SECG1RP,Public Group Read Privilege Setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 17. "SECG2RP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 16. "SECG3RP,Secure Group Read Privilege Setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 15. "SAFG0RP,Region15 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 14. "SAFG1RP,Region14 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 13. "SAFG2RP,Region13 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 12. "SAFG3RP,Region12 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 11. "SAFG4RP,Region11 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 10. "SAFG5RP,Region10 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 9. "SAFG6RP,Region9 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 8. "SAFG7RP,Region8 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 7. "SAFG8RP,Region7 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 6. "SAFG9RP,Region6 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 5. "SAFG10RP,Region5 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 4. "SAFG11RP,Region4 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 3. "SAFG12RP,Region3 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 2. "SAFG13RP,Region2 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 1. "SAFG14RP,Region1 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 0. "SAFG15RP,Region0 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
group.long 0x54++0x03
line.long 0x00 "SECCTRR5D,Function: Privilege setting of each secure region"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
bitfld.long 0x00 19. "SECG0RP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 18. "SECG1RP,Public Group Read Privilege Setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 17. "SECG2RP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 16. "SECG3RP,Secure Group Read Privilege Setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 15. "SAFG0RP,Region15 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 14. "SAFG1RP,Region14 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 13. "SAFG2RP,Region13 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 12. "SAFG3RP,Region12 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 11. "SAFG4RP,Region11 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 10. "SAFG5RP,Region10 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 9. "SAFG6RP,Region9 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 8. "SAFG7RP,Region8 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 7. "SAFG8RP,Region7 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 6. "SAFG9RP,Region6 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 5. "SAFG10RP,Region5 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 4. "SAFG11RP,Region4 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 3. "SAFG12RP,Region3 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 2. "SAFG13RP,Region2 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 1. "SAFG14RP,Region1 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 0. "SAFG15RP,Region0 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
group.long 0x58++0x03
line.long 0x00 "SECCTRR6D,Function: Privilege setting of each secure region"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
bitfld.long 0x00 19. "SECG0RP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 18. "SECG1RP,Public Group Read Privilege Setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 17. "SECG2RP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 16. "SECG3RP,Secure Group Read Privilege Setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 15. "SAFG0RP,Region15 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 14. "SAFG1RP,Region14 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 13. "SAFG2RP,Region13 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 12. "SAFG3RP,Region12 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 11. "SAFG4RP,Region11 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 10. "SAFG5RP,Region10 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 9. "SAFG6RP,Region9 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 8. "SAFG7RP,Region8 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 7. "SAFG8RP,Region7 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 6. "SAFG9RP,Region6 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 5. "SAFG10RP,Region5 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 4. "SAFG11RP,Region4 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 3. "SAFG12RP,Region3 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 2. "SAFG13RP,Region2 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 1. "SAFG14RP,Region1 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 0. "SAFG15RP,Region0 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
group.long 0x5C++0x03
line.long 0x00 "SECCTRR7D,Function: Privilege setting of each secure region"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
bitfld.long 0x00 19. "SECG0RP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 18. "SECG1RP,Public Group Read Privilege Setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 17. "SECG2RP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 16. "SECG3RP,Secure Group Read Privilege Setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 15. "SAFG0RP,Region15 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 14. "SAFG1RP,Region14 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 13. "SAFG2RP,Region13 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 12. "SAFG3RP,Region12 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 11. "SAFG4RP,Region11 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 10. "SAFG5RP,Region10 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 9. "SAFG6RP,Region9 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 8. "SAFG7RP,Region8 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 7. "SAFG8RP,Region7 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 6. "SAFG9RP,Region6 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 5. "SAFG10RP,Region5 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 4. "SAFG11RP,Region4 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 3. "SAFG12RP,Region3 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 2. "SAFG13RP,Region2 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 1. "SAFG14RP,Region1 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 0. "SAFG15RP,Region0 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
group.long 0x60++0x03
line.long 0x00 "SECCTRR8D,Function: Privilege setting of each secure region"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
bitfld.long 0x00 19. "SECG0RP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 18. "SECG1RP,Public Group Read Privilege Setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 17. "SECG2RP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 16. "SECG3RP,Secure Group Read Privilege Setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 15. "SAFG0RP,Region15 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 14. "SAFG1RP,Region14 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 13. "SAFG2RP,Region13 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 12. "SAFG3RP,Region12 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 11. "SAFG4RP,Region11 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 10. "SAFG5RP,Region10 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 9. "SAFG6RP,Region9 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 8. "SAFG7RP,Region8 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 7. "SAFG8RP,Region7 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 6. "SAFG9RP,Region6 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 5. "SAFG10RP,Region5 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 4. "SAFG11RP,Region4 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 3. "SAFG12RP,Region3 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 2. "SAFG13RP,Region2 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 1. "SAFG14RP,Region1 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 0. "SAFG15RP,Region0 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
group.long 0x64++0x03
line.long 0x00 "SECCTRR9D,Function: Privilege setting of each secure region"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
bitfld.long 0x00 19. "SECG0RP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 18. "SECG1RP,Public Group Read Privilege Setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 17. "SECG2RP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 16. "SECG3RP,Secure Group Read Privilege Setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 15. "SAFG0RP,Region15 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 14. "SAFG1RP,Region14 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 13. "SAFG2RP,Region13 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 12. "SAFG3RP,Region12 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 11. "SAFG4RP,Region11 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 10. "SAFG5RP,Region10 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 9. "SAFG6RP,Region9 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 8. "SAFG7RP,Region8 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 7. "SAFG8RP,Region7 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 6. "SAFG9RP,Region6 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 5. "SAFG10RP,Region5 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 4. "SAFG11RP,Region4 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 3. "SAFG12RP,Region3 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 2. "SAFG13RP,Region2 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 1. "SAFG14RP,Region1 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 0. "SAFG15RP,Region0 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
group.long 0x68++0x03
line.long 0x00 "SECCTRR10D,Function: Privilege setting of each secure region"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
bitfld.long 0x00 19. "SECG0RP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 18. "SECG1RP,Public Group Read Privilege Setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 17. "SECG2RP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 16. "SECG3RP,Secure Group Read Privilege Setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 15. "SAFG0RP,Region15 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 14. "SAFG1RP,Region14 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 13. "SAFG2RP,Region13 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 12. "SAFG3RP,Region12 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 11. "SAFG4RP,Region11 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 10. "SAFG5RP,Region10 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 9. "SAFG6RP,Region9 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 8. "SAFG7RP,Region8 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 7. "SAFG8RP,Region7 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 6. "SAFG9RP,Region6 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 5. "SAFG10RP,Region5 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 4. "SAFG11RP,Region4 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 3. "SAFG12RP,Region3 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 2. "SAFG13RP,Region2 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 1. "SAFG14RP,Region1 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 0. "SAFG15RP,Region0 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
group.long 0x6C++0x03
line.long 0x00 "SECCTRR11D,Function: Privilege setting of each secure region"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
bitfld.long 0x00 19. "SECG0RP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 18. "SECG1RP,Public Group Read Privilege Setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 17. "SECG2RP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 16. "SECG3RP,Secure Group Read Privilege Setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 15. "SAFG0RP,Region15 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 14. "SAFG1RP,Region14 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 13. "SAFG2RP,Region13 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 12. "SAFG3RP,Region12 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 11. "SAFG4RP,Region11 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 10. "SAFG5RP,Region10 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 9. "SAFG6RP,Region9 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 8. "SAFG7RP,Region8 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 7. "SAFG8RP,Region7 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 6. "SAFG9RP,Region6 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 5. "SAFG10RP,Region5 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 4. "SAFG11RP,Region4 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 3. "SAFG12RP,Region3 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 2. "SAFG13RP,Region2 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 1. "SAFG14RP,Region1 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 0. "SAFG15RP,Region0 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
group.long 0x70++0x03
line.long 0x00 "SECCTRR12D,Function: Privilege setting of each secure region"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
bitfld.long 0x00 19. "SECG0RP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 18. "SECG1RP,Public Group Read Privilege Setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 17. "SECG2RP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 16. "SECG3RP,Secure Group Read Privilege Setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 15. "SAFG0RP,Region15 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 14. "SAFG1RP,Region14 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 13. "SAFG2RP,Region13 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 12. "SAFG3RP,Region12 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 11. "SAFG4RP,Region11 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 10. "SAFG5RP,Region10 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 9. "SAFG6RP,Region9 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 8. "SAFG7RP,Region8 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 7. "SAFG8RP,Region7 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 6. "SAFG9RP,Region6 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 5. "SAFG10RP,Region5 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 4. "SAFG11RP,Region4 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 3. "SAFG12RP,Region3 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 2. "SAFG13RP,Region2 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 1. "SAFG14RP,Region1 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 0. "SAFG15RP,Region0 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
group.long 0x74++0x03
line.long 0x00 "SECCTRR13D,Function: Privilege setting of each secure region"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
bitfld.long 0x00 19. "SECG0RP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 18. "SECG1RP,Public Group Read Privilege Setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 17. "SECG2RP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 16. "SECG3RP,Secure Group Read Privilege Setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 15. "SAFG0RP,Region15 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 14. "SAFG1RP,Region14 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 13. "SAFG2RP,Region13 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 12. "SAFG3RP,Region12 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 11. "SAFG4RP,Region11 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 10. "SAFG5RP,Region10 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 9. "SAFG6RP,Region9 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 8. "SAFG7RP,Region8 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 7. "SAFG8RP,Region7 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 6. "SAFG9RP,Region6 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 5. "SAFG10RP,Region5 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 4. "SAFG11RP,Region4 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 3. "SAFG12RP,Region3 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 2. "SAFG13RP,Region2 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 1. "SAFG14RP,Region1 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 0. "SAFG15RP,Region0 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
group.long 0x78++0x03
line.long 0x00 "SECCTRR14D,Function: Privilege setting of each secure region"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
bitfld.long 0x00 19. "SECG0RP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 18. "SECG1RP,Public Group Read Privilege Setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 17. "SECG2RP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 16. "SECG3RP,Secure Group Read Privilege Setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 15. "SAFG0RP,Region15 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 14. "SAFG1RP,Region14 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 13. "SAFG2RP,Region13 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 12. "SAFG3RP,Region12 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 11. "SAFG4RP,Region11 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 10. "SAFG5RP,Region10 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 9. "SAFG6RP,Region9 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 8. "SAFG7RP,Region8 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 7. "SAFG8RP,Region7 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 6. "SAFG9RP,Region6 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 5. "SAFG10RP,Region5 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 4. "SAFG11RP,Region4 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 3. "SAFG12RP,Region3 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 2. "SAFG13RP,Region2 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 1. "SAFG14RP,Region1 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 0. "SAFG15RP,Region0 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
group.long 0x7C++0x03
line.long 0x00 "SECCTRR15D,Function: Privilege setting of each secure region"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
bitfld.long 0x00 19. "SECG0RP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 18. "SECG1RP,Public Group Read Privilege Setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 17. "SECG2RP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 16. "SECG3RP,Secure Group Read Privilege Setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 15. "SAFG0RP,Region15 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 14. "SAFG1RP,Region14 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 13. "SAFG2RP,Region13 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 12. "SAFG3RP,Region12 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 11. "SAFG4RP,Region11 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 10. "SAFG5RP,Region10 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 9. "SAFG6RP,Region9 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 8. "SAFG7RP,Region8 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 7. "SAFG8RP,Region7 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 6. "SAFG9RP,Region6 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 5. "SAFG10RP,Region5 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 4. "SAFG11RP,Region4 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 3. "SAFG12RP,Region3 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 2. "SAFG13RP,Region2 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 1. "SAFG14RP,Region1 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 0. "SAFG15RP,Region0 Group Register Read Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
group.long 0x340++0x03
line.long 0x00 "SECCTRW0D,Function: Privilege setting of each secure region"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
bitfld.long 0x00 19. "SECG0WP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 18. "SECG1WP,Public Group Write Privilege Setting" "0: Has the privilege to Write to the relevant,1: Does not have the privilege Write to the"
bitfld.long 0x00 17. "SECG2WP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 16. "SECG3WP,Secure Group Write Privilege Setting" "0: Has the privilege to Write to the relevant,1: Does not have the privilege Write to the"
bitfld.long 0x00 15. "SAFG0WP,Region15 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 14. "SAFG1WP,Region14 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 13. "SAFG2WP,Region13 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 12. "SAFG3WP,Region12 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 11. "SAFG4WP,Region11 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 10. "SAFG5WP,Region10 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 9. "SAFG6WP,Region9 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 8. "SAFG7WP,Region8 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 7. "SAFG8WP,Region7 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 6. "SAFG9WP,Region6 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 5. "SAFG10WP,Region5 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 4. "SAFG11WP,Region4 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 3. "SAFG12WP,Region3 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 2. "SAFG13WP,Region2 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 1. "SAFG14WP,Region1 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 0. "SAFG15WP,Region0 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
group.long 0x344++0x03
line.long 0x00 "SECCTRW1D,Function: Privilege setting of each secure region"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
bitfld.long 0x00 19. "SECG0WP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 18. "SECG1WP,Public Group Write Privilege Setting" "0: Has the privilege to Write to the relevant,1: Does not have the privilege Write to the"
bitfld.long 0x00 17. "SECG2WP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 16. "SECG3WP,Secure Group Write Privilege Setting" "0: Has the privilege to Write to the relevant,1: Does not have the privilege Write to the"
bitfld.long 0x00 15. "SAFG0WP,Region15 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 14. "SAFG1WP,Region14 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 13. "SAFG2WP,Region13 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 12. "SAFG3WP,Region12 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 11. "SAFG4WP,Region11 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 10. "SAFG5WP,Region10 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 9. "SAFG6WP,Region9 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 8. "SAFG7WP,Region8 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 7. "SAFG8WP,Region7 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 6. "SAFG9WP,Region6 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 5. "SAFG10WP,Region5 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 4. "SAFG11WP,Region4 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 3. "SAFG12WP,Region3 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 2. "SAFG13WP,Region2 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 1. "SAFG14WP,Region1 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 0. "SAFG15WP,Region0 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
group.long 0x348++0x03
line.long 0x00 "SECCTRW2D,Function: Privilege setting of each secure region"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
bitfld.long 0x00 19. "SECG0WP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 18. "SECG1WP,Public Group Write Privilege Setting" "0: Has the privilege to Write to the relevant,1: Does not have the privilege Write to the"
bitfld.long 0x00 17. "SECG2WP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 16. "SECG3WP,Secure Group Write Privilege Setting" "0: Has the privilege to Write to the relevant,1: Does not have the privilege Write to the"
bitfld.long 0x00 15. "SAFG0WP,Region15 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 14. "SAFG1WP,Region14 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 13. "SAFG2WP,Region13 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 12. "SAFG3WP,Region12 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 11. "SAFG4WP,Region11 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 10. "SAFG5WP,Region10 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 9. "SAFG6WP,Region9 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 8. "SAFG7WP,Region8 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 7. "SAFG8WP,Region7 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 6. "SAFG9WP,Region6 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 5. "SAFG10WP,Region5 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 4. "SAFG11WP,Region4 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 3. "SAFG12WP,Region3 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 2. "SAFG13WP,Region2 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 1. "SAFG14WP,Region1 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 0. "SAFG15WP,Region0 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
group.long 0x34C++0x03
line.long 0x00 "SECCTRW3D,Function: Privilege setting of each secure region"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
bitfld.long 0x00 19. "SECG0WP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 18. "SECG1WP,Public Group Write Privilege Setting" "0: Has the privilege to Write to the relevant,1: Does not have the privilege Write to the"
bitfld.long 0x00 17. "SECG2WP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 16. "SECG3WP,Secure Group Write Privilege Setting" "0: Has the privilege to Write to the relevant,1: Does not have the privilege Write to the"
bitfld.long 0x00 15. "SAFG0WP,Region15 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 14. "SAFG1WP,Region14 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 13. "SAFG2WP,Region13 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 12. "SAFG3WP,Region12 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 11. "SAFG4WP,Region11 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 10. "SAFG5WP,Region10 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 9. "SAFG6WP,Region9 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 8. "SAFG7WP,Region8 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 7. "SAFG8WP,Region7 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 6. "SAFG9WP,Region6 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 5. "SAFG10WP,Region5 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 4. "SAFG11WP,Region4 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 3. "SAFG12WP,Region3 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 2. "SAFG13WP,Region2 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 1. "SAFG14WP,Region1 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 0. "SAFG15WP,Region0 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
group.long 0x350++0x03
line.long 0x00 "SECCTRW4D,Function: Privilege setting of each secure region"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
bitfld.long 0x00 19. "SECG0WP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 18. "SECG1WP,Public Group Write Privilege Setting" "0: Has the privilege to Write to the relevant,1: Does not have the privilege Write to the"
bitfld.long 0x00 17. "SECG2WP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 16. "SECG3WP,Secure Group Write Privilege Setting" "0: Has the privilege to Write to the relevant,1: Does not have the privilege Write to the"
bitfld.long 0x00 15. "SAFG0WP,Region15 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 14. "SAFG1WP,Region14 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 13. "SAFG2WP,Region13 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 12. "SAFG3WP,Region12 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 11. "SAFG4WP,Region11 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 10. "SAFG5WP,Region10 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 9. "SAFG6WP,Region9 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 8. "SAFG7WP,Region8 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 7. "SAFG8WP,Region7 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 6. "SAFG9WP,Region6 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 5. "SAFG10WP,Region5 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 4. "SAFG11WP,Region4 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 3. "SAFG12WP,Region3 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 2. "SAFG13WP,Region2 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 1. "SAFG14WP,Region1 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 0. "SAFG15WP,Region0 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
group.long 0x354++0x03
line.long 0x00 "SECCTRW5D,Function: Privilege setting of each secure region"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
bitfld.long 0x00 19. "SECG0WP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 18. "SECG1WP,Public Group Write Privilege Setting" "0: Has the privilege to Write to the relevant,1: Does not have the privilege Write to the"
bitfld.long 0x00 17. "SECG2WP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 16. "SECG3WP,Secure Group Write Privilege Setting" "0: Has the privilege to Write to the relevant,1: Does not have the privilege Write to the"
bitfld.long 0x00 15. "SAFG0WP,Region15 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 14. "SAFG1WP,Region14 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 13. "SAFG2WP,Region13 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 12. "SAFG3WP,Region12 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 11. "SAFG4WP,Region11 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 10. "SAFG5WP,Region10 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 9. "SAFG6WP,Region9 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 8. "SAFG7WP,Region8 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 7. "SAFG8WP,Region7 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 6. "SAFG9WP,Region6 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 5. "SAFG10WP,Region5 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 4. "SAFG11WP,Region4 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 3. "SAFG12WP,Region3 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 2. "SAFG13WP,Region2 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 1. "SAFG14WP,Region1 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 0. "SAFG15WP,Region0 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
group.long 0x358++0x03
line.long 0x00 "SECCTRW6D,Function: Privilege setting of each secure region"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
bitfld.long 0x00 19. "SECG0WP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 18. "SECG1WP,Public Group Write Privilege Setting" "0: Has the privilege to Write to the relevant,1: Does not have the privilege Write to the"
bitfld.long 0x00 17. "SECG2WP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 16. "SECG3WP,Secure Group Write Privilege Setting" "0: Has the privilege to Write to the relevant,1: Does not have the privilege Write to the"
bitfld.long 0x00 15. "SAFG0WP,Region15 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 14. "SAFG1WP,Region14 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 13. "SAFG2WP,Region13 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 12. "SAFG3WP,Region12 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 11. "SAFG4WP,Region11 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 10. "SAFG5WP,Region10 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 9. "SAFG6WP,Region9 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 8. "SAFG7WP,Region8 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 7. "SAFG8WP,Region7 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 6. "SAFG9WP,Region6 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 5. "SAFG10WP,Region5 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 4. "SAFG11WP,Region4 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 3. "SAFG12WP,Region3 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 2. "SAFG13WP,Region2 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 1. "SAFG14WP,Region1 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 0. "SAFG15WP,Region0 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
group.long 0x35C++0x03
line.long 0x00 "SECCTRW7D,Function: Privilege setting of each secure region"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
bitfld.long 0x00 19. "SECG0WP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 18. "SECG1WP,Public Group Write Privilege Setting" "0: Has the privilege to Write to the relevant,1: Does not have the privilege Write to the"
bitfld.long 0x00 17. "SECG2WP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 16. "SECG3WP,Secure Group Write Privilege Setting" "0: Has the privilege to Write to the relevant,1: Does not have the privilege Write to the"
bitfld.long 0x00 15. "SAFG0WP,Region15 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 14. "SAFG1WP,Region14 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 13. "SAFG2WP,Region13 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 12. "SAFG3WP,Region12 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 11. "SAFG4WP,Region11 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 10. "SAFG5WP,Region10 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 9. "SAFG6WP,Region9 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 8. "SAFG7WP,Region8 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 7. "SAFG8WP,Region7 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 6. "SAFG9WP,Region6 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 5. "SAFG10WP,Region5 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 4. "SAFG11WP,Region4 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 3. "SAFG12WP,Region3 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 2. "SAFG13WP,Region2 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 1. "SAFG14WP,Region1 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 0. "SAFG15WP,Region0 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
group.long 0x360++0x03
line.long 0x00 "SECCTRW8D,Function: Privilege setting of each secure region"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
bitfld.long 0x00 19. "SECG0WP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 18. "SECG1WP,Public Group Write Privilege Setting" "0: Has the privilege to Write to the relevant,1: Does not have the privilege Write to the"
bitfld.long 0x00 17. "SECG2WP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 16. "SECG3WP,Secure Group Write Privilege Setting" "0: Has the privilege to Write to the relevant,1: Does not have the privilege Write to the"
bitfld.long 0x00 15. "SAFG0WP,Region15 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 14. "SAFG1WP,Region14 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 13. "SAFG2WP,Region13 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 12. "SAFG3WP,Region12 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 11. "SAFG4WP,Region11 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 10. "SAFG5WP,Region10 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 9. "SAFG6WP,Region9 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 8. "SAFG7WP,Region8 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 7. "SAFG8WP,Region7 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 6. "SAFG9WP,Region6 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 5. "SAFG10WP,Region5 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 4. "SAFG11WP,Region4 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 3. "SAFG12WP,Region3 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 2. "SAFG13WP,Region2 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 1. "SAFG14WP,Region1 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 0. "SAFG15WP,Region0 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
group.long 0x364++0x03
line.long 0x00 "SECCTRW9D,Function: Privilege setting of each secure region"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
bitfld.long 0x00 19. "SECG0WP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 18. "SECG1WP,Public Group Write Privilege Setting" "0: Has the privilege to Write to the relevant,1: Does not have the privilege Write to the"
bitfld.long 0x00 17. "SECG2WP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 16. "SECG3WP,Secure Group Write Privilege Setting" "0: Has the privilege to Write to the relevant,1: Does not have the privilege Write to the"
bitfld.long 0x00 15. "SAFG0WP,Region15 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 14. "SAFG1WP,Region14 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 13. "SAFG2WP,Region13 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 12. "SAFG3WP,Region12 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 11. "SAFG4WP,Region11 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 10. "SAFG5WP,Region10 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 9. "SAFG6WP,Region9 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 8. "SAFG7WP,Region8 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 7. "SAFG8WP,Region7 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 6. "SAFG9WP,Region6 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 5. "SAFG10WP,Region5 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 4. "SAFG11WP,Region4 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 3. "SAFG12WP,Region3 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 2. "SAFG13WP,Region2 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 1. "SAFG14WP,Region1 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 0. "SAFG15WP,Region0 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
group.long 0x368++0x03
line.long 0x00 "SECCTRW10D,Function: Privilege setting of each secure region"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
bitfld.long 0x00 19. "SECG0WP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 18. "SECG1WP,Public Group Write Privilege Setting" "0: Has the privilege to Write to the relevant,1: Does not have the privilege Write to the"
bitfld.long 0x00 17. "SECG2WP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 16. "SECG3WP,Secure Group Write Privilege Setting" "0: Has the privilege to Write to the relevant,1: Does not have the privilege Write to the"
bitfld.long 0x00 15. "SAFG0WP,Region15 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 14. "SAFG1WP,Region14 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 13. "SAFG2WP,Region13 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 12. "SAFG3WP,Region12 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 11. "SAFG4WP,Region11 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 10. "SAFG5WP,Region10 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 9. "SAFG6WP,Region9 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 8. "SAFG7WP,Region8 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 7. "SAFG8WP,Region7 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 6. "SAFG9WP,Region6 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 5. "SAFG10WP,Region5 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 4. "SAFG11WP,Region4 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 3. "SAFG12WP,Region3 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 2. "SAFG13WP,Region2 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 1. "SAFG14WP,Region1 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 0. "SAFG15WP,Region0 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
group.long 0x36C++0x03
line.long 0x00 "SECCTRW11D,Function: Privilege setting of each secure region"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
bitfld.long 0x00 19. "SECG0WP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 18. "SECG1WP,Public Group Write Privilege Setting" "0: Has the privilege to Write to the relevant,1: Does not have the privilege Write to the"
bitfld.long 0x00 17. "SECG2WP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 16. "SECG3WP,Secure Group Write Privilege Setting" "0: Has the privilege to Write to the relevant,1: Does not have the privilege Write to the"
bitfld.long 0x00 15. "SAFG0WP,Region15 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 14. "SAFG1WP,Region14 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 13. "SAFG2WP,Region13 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 12. "SAFG3WP,Region12 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 11. "SAFG4WP,Region11 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 10. "SAFG5WP,Region10 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 9. "SAFG6WP,Region9 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 8. "SAFG7WP,Region8 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 7. "SAFG8WP,Region7 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 6. "SAFG9WP,Region6 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 5. "SAFG10WP,Region5 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 4. "SAFG11WP,Region4 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 3. "SAFG12WP,Region3 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 2. "SAFG13WP,Region2 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 1. "SAFG14WP,Region1 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 0. "SAFG15WP,Region0 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
group.long 0x370++0x03
line.long 0x00 "SECCTRW12D,Function: Privilege setting of each secure region"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
bitfld.long 0x00 19. "SECG0WP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 18. "SECG1WP,Public Group Write Privilege Setting" "0: Has the privilege to Write to the relevant,1: Does not have the privilege Write to the"
bitfld.long 0x00 17. "SECG2WP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 16. "SECG3WP,Secure Group Write Privilege Setting" "0: Has the privilege to Write to the relevant,1: Does not have the privilege Write to the"
bitfld.long 0x00 15. "SAFG0WP,Region15 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 14. "SAFG1WP,Region14 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 13. "SAFG2WP,Region13 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 12. "SAFG3WP,Region12 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 11. "SAFG4WP,Region11 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 10. "SAFG5WP,Region10 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 9. "SAFG6WP,Region9 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 8. "SAFG7WP,Region8 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 7. "SAFG8WP,Region7 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 6. "SAFG9WP,Region6 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 5. "SAFG10WP,Region5 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 4. "SAFG11WP,Region4 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 3. "SAFG12WP,Region3 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 2. "SAFG13WP,Region2 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 1. "SAFG14WP,Region1 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 0. "SAFG15WP,Region0 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
group.long 0x374++0x03
line.long 0x00 "SECCTRW13D,Function: Privilege setting of each secure region"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
bitfld.long 0x00 19. "SECG0WP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 18. "SECG1WP,Public Group Write Privilege Setting" "0: Has the privilege to Write to the relevant,1: Does not have the privilege Write to the"
bitfld.long 0x00 17. "SECG2WP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 16. "SECG3WP,Secure Group Write Privilege Setting" "0: Has the privilege to Write to the relevant,1: Does not have the privilege Write to the"
bitfld.long 0x00 15. "SAFG0WP,Region15 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 14. "SAFG1WP,Region14 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 13. "SAFG2WP,Region13 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 12. "SAFG3WP,Region12 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 11. "SAFG4WP,Region11 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 10. "SAFG5WP,Region10 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 9. "SAFG6WP,Region9 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 8. "SAFG7WP,Region8 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 7. "SAFG8WP,Region7 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 6. "SAFG9WP,Region6 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 5. "SAFG10WP,Region5 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 4. "SAFG11WP,Region4 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 3. "SAFG12WP,Region3 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 2. "SAFG13WP,Region2 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 1. "SAFG14WP,Region1 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 0. "SAFG15WP,Region0 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
group.long 0x378++0x03
line.long 0x00 "SECCTRW14D,Function: Privilege setting of each secure region"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
bitfld.long 0x00 19. "SECG0WP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 18. "SECG1WP,Public Group Write Privilege Setting" "0: Has the privilege to Write to the relevant,1: Does not have the privilege Write to the"
bitfld.long 0x00 17. "SECG2WP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 16. "SECG3WP,Secure Group Write Privilege Setting" "0: Has the privilege to Write to the relevant,1: Does not have the privilege Write to the"
bitfld.long 0x00 15. "SAFG0WP,Region15 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 14. "SAFG1WP,Region14 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 13. "SAFG2WP,Region13 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 12. "SAFG3WP,Region12 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 11. "SAFG4WP,Region11 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 10. "SAFG5WP,Region10 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 9. "SAFG6WP,Region9 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 8. "SAFG7WP,Region8 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 7. "SAFG8WP,Region7 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 6. "SAFG9WP,Region6 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 5. "SAFG10WP,Region5 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 4. "SAFG11WP,Region4 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 3. "SAFG12WP,Region3 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 2. "SAFG13WP,Region2 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 1. "SAFG14WP,Region1 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 0. "SAFG15WP,Region0 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
group.long 0x37C++0x03
line.long 0x00 "SECCTRW15D,Function: Privilege setting of each secure region"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
bitfld.long 0x00 19. "SECG0WP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 18. "SECG1WP,Public Group Write Privilege Setting" "0: Has the privilege to Write to the relevant,1: Does not have the privilege Write to the"
bitfld.long 0x00 17. "SECG2WP,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 16. "SECG3WP,Secure Group Write Privilege Setting" "0: Has the privilege to Write to the relevant,1: Does not have the privilege Write to the"
bitfld.long 0x00 15. "SAFG0WP,Region15 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 14. "SAFG1WP,Region14 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 13. "SAFG2WP,Region13 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 12. "SAFG3WP,Region12 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 11. "SAFG4WP,Region11 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 10. "SAFG5WP,Region10 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 9. "SAFG6WP,Region9 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 8. "SAFG7WP,Region8 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 7. "SAFG8WP,Region7 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 6. "SAFG9WP,Region6 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 5. "SAFG10WP,Region5 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 4. "SAFG11WP,Region4 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 3. "SAFG12WP,Region3 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 2. "SAFG13WP,Region2 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
bitfld.long 0x00 1. "SAFG14WP,Region1 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
newline
bitfld.long 0x00 0. "SAFG15WP,Region0 Group Register Write Privilege setting" "0: Has the privilege to read to the relevant,1: Does not have the privilege read to the.."
group.long 0x20A0++0x03
line.long 0x00 "ICUSECCAUSE,Function: Secure error cause by ICUMX"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
bitfld.long 0x00 16. "LOCK,If secure error is detected this bit is set to 1" "0,1"
newline
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved These bits are always read as 0"
bitfld.long 0x00 1. "SECERR_R,If secure error of read port is detected this bit is set to 1" "0,1"
newline
bitfld.long 0x00 0. "SECERR_W,If secure error of write port is detected this bit is set to 1" "0,1"
group.long 0x20A4++0x03
line.long 0x00 "ICUSAFCAUSE,"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
bitfld.long 0x00 16. "LOCK,If safety error is detected this bit is set to 1" "0,1"
newline
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved These bits are always read as 0"
bitfld.long 0x00 1. "SAFERR_R,If safety error of read port is detected this bit is set to 1" "0,1"
newline
bitfld.long 0x00 0. "SAFERR_W,If safety error of write port is detected this bit is set to 1" "0,1"
group.long 0x20A8++0x03
line.long 0x00 "ICUSECERRINF0,Secure error information(error ID) by ICUMX"
rbitfld.long 0x00 29.--31. "Reserved_29,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
hexmask.long 0x00 0.--28. 1. "SECERRID,Secure error axid Write 1 to ICUSECCAUSE.LOCK for clear"
group.long 0x20AC++0x03
line.long 0x00 "ICUSECERRINF1,Secure error information(error Address) by ICUMX"
hexmask.long 0x00 0.--31. 1. "SECERRADDR,Secure error axaddr [31:0] Write 1 to ICUSECCAUSE.LOCK for clear"
group.long 0x20B0++0x03
line.long 0x00 "ICUSAFERRINF0,Safety error information(error ID) by ICUMX"
rbitfld.long 0x00 29.--31. "Reserved_29,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
hexmask.long 0x00 0.--28. 1. "SAFERRID,Transaction ID that caused safety error"
group.long 0x20B4++0x03
line.long 0x00 "ICUSAFERRINF1,Safety error information(error Address) by ICUMX"
hexmask.long 0x00 0.--31. 1. "SAFERRADDR,Address offset of transaction that caused safety error"
group.long 0x2104++0x03
line.long 0x00 "ICUERRBUSCAUSE,"
hexmask.long.tbyte 0x00 10.--31. 1. "Reserved_10,Reserved These bits are always read as 0"
bitfld.long 0x00 9. "EDC_RD_TAGRAM_DBIT," "0,1"
newline
bitfld.long 0x00 8. "EDC_RD_SRAMBANK_DBIT," "0,1"
bitfld.long 0x00 7. "EDC_REGIF," "0,1"
newline
bitfld.long 0x00 6. "EDC_RD_TAGRAM," "0,1"
bitfld.long 0x00 5. "EDC_RD_SRAMBANK," "0,1"
newline
bitfld.long 0x00 4. "EDC_PW," "0,1"
bitfld.long 0x00 3. "EDC_PA," "0,1"
newline
rbitfld.long 0x00 2. "Reserved_2,Reserved These bits are always read as 0" "0,1"
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0x2200++0x03
line.long 0x00 "MEM_INIT,Function: Initialization request for the memory"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "INIT,(*1) Set this bit to 1 RT-VRAM start memory initialization both SRAM-BANK and TAGRAM" "0: idle,1: running"
group.long 0x2314++0x03
line.long 0x00 "ICUDUPERRCAUSE,"
hexmask.long 0x00 5.--31. 1. "Reserved_5,Reserved These bits are always read as 0"
bitfld.long 0x00 4. "ERR_INTER_CON," "0,1"
newline
bitfld.long 0x00 3. "ERR_OTHER_PORTS," "0,1"
bitfld.long 0x00 2. "ERR_AXI_INI," "0,1"
newline
bitfld.long 0x00 1. "ERR_AXI_TGT," "0,1"
bitfld.long 0x00 0. "ERR_APB," "0,1"
group.long 0x2334++0x03
line.long 0x00 "ICUTIMEOUT_ERR,"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "TOERR,If timeout error is detected this bit is set to 1" "0,1"
group.long 0x2348++0x03
line.long 0x00 "ICUCRC_ERRCAUSE,"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
bitfld.long 0x00 16. "Lock,If CRC error is detected this bit is set to 1" "0,1"
newline
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CRCERR,If CRC error is detected this bit is set to 1" "0,1"
group.long 0x234C++0x03
line.long 0x00 "ICUCRC_ERRVADDR,CRC error address Register(error cause by ICUMX)"
hexmask.long 0x00 0.--31. 1. "ERR_VADDR_31_0,Address[39:8] of transaction that caused CRC error"
group.long 0x2404++0x03
line.long 0x00 "ICUDUMMY_ERROR,"
hexmask.long 0x00 6.--31. 1. "Reserved_6,Reserved These bits are always read as 0"
bitfld.long 0x00 5. "DUPLEX,Forced ERR_STRAM_ICU_DUPLEX notification signal assertion" "0: disable,1: enable"
newline
bitfld.long 0x00 4. "SEC,Forced ERR_STRAM_ICU_SEC notification signal assertion" "0: disable,1: enable"
bitfld.long 0x00 3. "SAFE,Forced ERR_STRAM_ICU_SAFE notification signal assertion" "0: disable,1: enable"
newline
bitfld.long 0x00 2. "EDC_RAM_DBIT,Forced ERR_STRAM_ICU_EDC_RAM_DBIT notification signal assertion" "0: disable,1: enable"
bitfld.long 0x00 1. "EDC_RAM,Forced ERR_STRAM_ICU_EDC_RAM notification signal assertion" "0: disable,1: enable"
newline
bitfld.long 0x00 0. "EDC_BUS,Forced ERR_STRAM_ICU_EDC_BUS notification signal assertion" "0: disable,1: enable"
group.long 0x250C++0x03
line.long 0x00 "SCRAMBLE_CFG,"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "AREA7EN,It shall be set to 0" "0,1"
newline
bitfld.long 0x00 6. "AREA6EN,Specifies scramble enable for 7th 4M-byte area" "0: disable,1: enable"
bitfld.long 0x00 5. "AREA5EN,Specifies scramble enable for 6th 4M-byte area" "0: disable,1: enable"
newline
bitfld.long 0x00 4. "AREA4EN,Specifies scramble enable for 5th 4M-byte area" "0: disable,1: enable"
bitfld.long 0x00 3. "AREA3EN,Specifies scramble enable for 4th 4M-byte area" "0: disable,1: enable"
newline
bitfld.long 0x00 2. "AREA2EN,Specifies scramble enable for 3rd 4M-byte area" "0: disable,1: enable"
bitfld.long 0x00 1. "AREA1EN,Specifies scramble enable for 2nd 4M-byte area" "0: disable,1: enable"
newline
bitfld.long 0x00 0. "AREA0EN,Specifies scramble enable for 1st 4M-byte area" "0: disable,1: enable"
group.long 0x2510++0x03
line.long 0x00 "SCRAMBLE_KEY0,Scramble key0 Register Only ICUMX can set it once after reset then no IP can access"
hexmask.long 0x00 0.--31. 1. "KEY0,Specifies private key [31:0]"
group.long 0x2514++0x03
line.long 0x00 "SCRAMBLE_KEY1,Scramble key1 Register Only ICUMX can set it once after reset then no IP can access"
hexmask.long 0x00 0.--31. 1. "KEY1,Specifies private key [63:32]"
group.long 0x2518++0x03
line.long 0x00 "SCRAMBLE_KEY2,Scramble key2 Register Only ICUMX can set it once after reset then no IP can access"
hexmask.long 0x00 0.--31. 1. "KEY2,Specifies private key [95:64]"
group.long 0x251C++0x03
line.long 0x00 "SCRAMBLE_KEY3,Scramble key3 Register Only ICUMX can set it once after reset then no IP can access"
hexmask.long 0x00 0.--31. 1. "KEY3,Specifies private key [127:96]"
group.long 0x2520++0x03
line.long 0x00 "SCRAMBLE_NONCE0,Scramble nonce0 Register Only ICUMX can set it once after reset then no IP can access"
hexmask.long 0x00 0.--31. 1. "NONCE0,Specifies Nonce [31:0]"
group.long 0x2524++0x03
line.long 0x00 "SCRAMBLE_NONCE1,Scramble nonce1 Register Only ICUMX can set it once after reset then no IP can access"
hexmask.long 0x00 0.--31. 1. "NONCE1,Specifies Nonce [63:32]"
group.long 0x4080++0x03
line.long 0x00 "SECCAUSE,Function: Secure error cause excluding by ICUMX"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
bitfld.long 0x00 16. "LOCK,If secure error is detected this bit is set to 1" "0,1"
newline
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved"
bitfld.long 0x00 1. "SECERR_R,If secure error of read port is detected this bit is set to 1" "0,1"
newline
bitfld.long 0x00 0. "SECERR_W,If secure error of write port is detected this bit is set to 1" "0,1"
group.long 0x4084++0x03
line.long 0x00 "SAFCAUSE,"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
bitfld.long 0x00 16. "LOCK,If safety error is detected this bit is set to 1" "0,1"
newline
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved These bits are always read as 0"
bitfld.long 0x00 1. "SAFERR_R,If safety error of read port is detected this bit is set to 1" "0,1"
newline
bitfld.long 0x00 0. "SAFERR_W,If safety error of write port is detected this bit is set to 1" "0,1"
group.long 0x4088++0x03
line.long 0x00 "SECERRINF0,Safety error information(error ID) excluding by ICUMX"
rbitfld.long 0x00 29.--31. "Reserved_29,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
hexmask.long 0x00 0.--28. 1. "SECERRID,Transaction ID that caused secure error"
group.long 0x408C++0x03
line.long 0x00 "SECERRINF1,Secure error information(error Address) excluding by ICUMX"
hexmask.long 0x00 0.--31. 1. "SECERRADDR,Address offset of transaction that caused secure error"
group.long 0x4090++0x03
line.long 0x00 "SAFERRINF0,Safety error information(error ID) excluding by ICUMX"
rbitfld.long 0x00 29.--31. "Reserved_29,Reserved" "0,1,2,3,4,5,6,7"
hexmask.long 0x00 0.--28. 1. "SAFERRID,Transaction ID that caused safety error"
group.long 0x4094++0x03
line.long 0x00 "SAFERRINF1,Safety error information(error Address) excluding by ICUMX"
hexmask.long 0x00 0.--31. 1. "SAFERRADDR,Address offset of transaction that caused safety error"
group.long 0x4100++0x03
line.long 0x00 "ERRBUSCAUSE,"
hexmask.long.tbyte 0x00 10.--31. 1. "Reserved_10,Reserved These bits are always read as 0"
bitfld.long 0x00 9. "EDC_RD_TAGRAM_DBIT," "0,1"
newline
bitfld.long 0x00 8. "EDC_RD_SRAMBANK_DBIT," "0,1"
bitfld.long 0x00 7. "EDC_REGIF," "0,1"
newline
bitfld.long 0x00 6. "EDC_RD_TAGRAM," "0,1"
bitfld.long 0x00 5. "EDC_RD_SRAMBANK," "0,1"
newline
bitfld.long 0x00 4. "EDC_PW," "0,1"
bitfld.long 0x00 3. "EDC_PA," "0,1"
newline
rbitfld.long 0x00 2. "Reserved_2,Reserved These bits are always read as 0" "0,1"
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0x4110++0x03
line.long 0x00 "EDC_CFG,"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "EN_DETECT," "0,1"
group.long 0x4210++0x03
line.long 0x00 "EX_ADR_MASKL,Function: Address mask for exclusive access"
hexmask.long 0x00 0.--31. 1. "EXADRMSKL,Address compare mask of exclusive access(1: compare)"
group.long 0x4214++0x03
line.long 0x00 "EX_ADR_MASKU,Function: Address mask for exclusive access"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "EXADRMSKU,Address compare mask of exclusive access(1: compare)"
group.long 0x4300++0x03
line.long 0x00 "DUPERRCONT,"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "EN_DETECT," "0,1"
group.long 0x4310++0x03
line.long 0x00 "DUPERRCAUSE,"
hexmask.long 0x00 5.--31. 1. "Reserved_5,Reserved These bits are always read as 0"
bitfld.long 0x00 4. "ERR_INTER_CON," "0,1"
newline
bitfld.long 0x00 3. "ERR_OTHER_PORTS," "0,1"
bitfld.long 0x00 2. "ERR_AXI_INI," "0,1"
newline
bitfld.long 0x00 1. "ERR_AXI_TGT," "0,1"
bitfld.long 0x00 0. "ERR_APB," "0,1"
group.long 0x4330++0x03
line.long 0x00 "TIMEOUT_ERR,"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "TOERR,If timeout error is detected this bit is set to 1" "0,1"
group.long 0x4340++0x03
line.long 0x00 "CRC_ERRCAUSE,"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
bitfld.long 0x00 16. "Lock,If CRC error is detected this bit is set to 1" "0,1"
newline
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CRCERR,If CRC error is detected this bit is set to 1" "0,1"
group.long 0x4344++0x03
line.long 0x00 "CRC_ERRVADDR,CRC error address Register(error other than cause by ICUMX)"
hexmask.long 0x00 0.--31. 1. "ERR_VADDR_31_0,Address[39:8] of transaction that caused CRC error"
group.long 0x4350++0x03
line.long 0x00 "AXIINI_ERRCAUSE,"
hexmask.long 0x00 2.--31. 1. "Reserved_2,Reserved These bits are always read as 0"
bitfld.long 0x00 1. "UNKNOWNID,If RT-VRAM receives unknown ID which RT-VRAM doesn't issue this bit is set to 1" "0,1"
newline
bitfld.long 0x00 0. "ERRRESP,If RT-VRAM receives error response from ANMM this bit is set to 1" "0,1"
group.long 0x4400++0x03
line.long 0x00 "DUMMY_ERROR,"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "TIMEOUT,Forced ERR_RTSRAM_TIMEOUT notification signal assertion" "0: disable,1: enable"
newline
bitfld.long 0x00 6. "EXT,Forced ERR_RTSRAM_EXT notification signal assertion" "0: disable,1: enable"
bitfld.long 0x00 5. "DUPLEX,Forced ERR_RTSRAM_DUPLEX notification signal assertion" "0: disable,1: enable"
newline
bitfld.long 0x00 4. "SEC,Forced ERR_RTSRAM_SEC notification signal assertion" "0: disable,1: enable"
bitfld.long 0x00 3. "SAFE,Forced ERR_RTSRAM_SAFE notification signal assertion" "0: disable,1: enable"
newline
bitfld.long 0x00 2. "EDC_RAM_DBIT,Forced ERR_RTSRAM_EDC_RAM_DBIT notification signal assertion" "0: disable,1: enable"
bitfld.long 0x00 1. "EDC_RAM,Forced ERR_RTSRAM_EDC_RAM notification signal assertion" "0: disable,1: enable"
newline
bitfld.long 0x00 0. "EDC_BUS,Forced ERR_RTSRAM_EDC_BUS notification signal assertion" "0: disable,1: enable"
group.long 0x4408++0x03
line.long 0x00 "FAULT_INJECTION,"
hexmask.long.word 0x00 19.--31. 1. "Reserved_19,Reserved These bits are always read as 0"
bitfld.long 0x00 18. "DMY_ERR_AXIINI_ERRRSP," "0,1"
newline
bitfld.long 0x00 17. "DMY_EDC_RD_TAGRAM_DBIT," "0,1"
bitfld.long 0x00 16. "DMY_EDC_RD_SRAMBANK_DBIT," "0,1"
newline
bitfld.long 0x00 15. "DMY_ERR_AXIINI_UNKID," "0,1"
bitfld.long 0x00 14. "DMY_ERR_TIMEOUT_TOERR," "0,1"
newline
bitfld.long 0x00 13. "DMY_ERR_CRC_CRCERR," "0,1"
bitfld.long 0x00 12. "DMY_ERR_INTER_CON," "0,1"
newline
bitfld.long 0x00 11. "DMY_ERR_OTHER_PORTS," "0,1"
bitfld.long 0x00 10. "DMY_ERR_AXI_INI," "0,1"
newline
bitfld.long 0x00 9. "DMY_ERR_AXI_TGT," "0,1"
bitfld.long 0x00 8. "DMY_ERR_APB," "0,1"
newline
bitfld.long 0x00 7. "DMY_EDC_REGIF," "0,1"
bitfld.long 0x00 6. "DMY_EDC_RD_TAGRAM," "0,1"
newline
bitfld.long 0x00 5. "DMY_EDC_RD_SRAMBANK," "0,1"
bitfld.long 0x00 4. "DMY_EDC_PW," "0,1"
newline
bitfld.long 0x00 3. "DMY_EDC_PA," "0,1"
rbitfld.long 0x00 2. "Reserved_2,Reserved These bits are always read as 0" "0,1"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved These bits are always read as 0" "0,1"
rbitfld.long 0x00 0. "Reserved_0,Reserved These bits are always read as 0" "0,1"
group.long 0x4528++0x03
line.long 0x00 "TIMEOUT_CFG,"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.word 0x00 8.--23. 1. "THRESHOLD,Specifies a threshold of timeout detection [15:0]"
newline
hexmask.long.byte 0x00 1.--7. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "EN_DETECT,Specifies timeout detection enable" "0: disable,1: enable"
group.long 0x452C++0x03
line.long 0x00 "AXIINI_CFG,"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "EN_ERRDETECT,AXI initiator related error detection enable(receive error response or unknown ID)" "0: disable,1: enable"
group.long 0x4530++0x03
line.long 0x00 "CACHE_FLUSH,"
hexmask.long.tbyte 0x00 12.--31. 1. "Reserved_12,Reserved These bits are always read as 0"
bitfld.long 0x00 8.--11. "AREA_IDX,Index of protection area where flush operation is performed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.byte 0x00 1.--7. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "FLUSH,(*1) If it is set to 1 all data on cache data buffer are written back to DRAM" "0,1"
group.long 0x6504++0x03
line.long 0x00 "VBUF_CFG,"
hexmask.long.tbyte 0x00 9.--31. 1. "Reserved_9,Reserved These bits are always read as 0"
bitfld.long 0x00 8. "CACHE_MODE,Specifies the number of way" "0: 4-way,1: 8-way This"
newline
rbitfld.long 0x00 3.--7. "Reserved_3,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--2. "VBUF_SIZE_2_0,Specifies size of the virtual buffer" "0: 4M,1: 8M,2: 12M,3: 16M,4: 20M,5: 24M,6: 28M,7: "
group.long 0x6508++0x03
line.long 0x00 "CRC_CFG,"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "EN_CRC,Specifies CRC enable" "0: disable,1: enable"
group.long 0x8500++0x03
line.long 0x00 "EXT_MODE,"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "MODE,Specifies buffer mode" "0: compatible mode,1: extended mode Note that this bit can be"
group.long 0xA534++0x03
line.long 0x00 "CACHE_DEGRADE,"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "TAGINVLD,(*1) Writing 1 to this bit to Invalidate cache TAG" "0,1"
group.long 0xC580++0x03
line.long 0x00 "VBUF_BADDR0,"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "BASE_ADDR_23_0,Base address of 1st 4M-byte area of virtual buffer[39:16]"
group.long 0xC584++0x03
line.long 0x00 "VBUF_BADDR1,"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "BASE_ADDR_23_0,Base address of 2nd 4M-byte area of virtual buffer[39:16]"
group.long 0xC588++0x03
line.long 0x00 "VBUF_BADDR2,"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "BASE_ADDR_23_0,Base address of 3rd 4M-byte area of virtual buffer[39:16]"
group.long 0xC58C++0x03
line.long 0x00 "VBUF_BADDR3,"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "BASE_ADDR_23_0,Base address of 4th 4M-byte area of virtual buffer[39:16]"
group.long 0xC590++0x03
line.long 0x00 "VBUF_BADDR4,"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "BASE_ADDR_23_0,Base address of 5th 4M-byte area of virtual buffer[39:16]"
group.long 0xC594++0x03
line.long 0x00 "VBUF_BADDR5,"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "BASE_ADDR_23_0,Base address of 6th 4M-byte area of virtual buffer[39:16]"
group.long 0xC598++0x03
line.long 0x00 "VBUF_BADDR6,"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--23. 1. "BASE_ADDR_23_0,Base address of 7th 4M-byte area of virtual buffer[39:16]"
tree.end
tree "GWCA"
tree "GWCA_INST_0"
base ad:0xE6890000
group.long 0x00++0x03
line.long 0x00 "GWMC3,"
hexmask.long 0x00 2.--31. 1. "RSV,Reserved area"
bitfld.long 0x00 0.--1. "OPC,OPerating mode Command" "0,1,2,3"
group.long 0x04++0x03
line.long 0x00 "GWMS3,"
hexmask.long 0x00 2.--31. 1. "RSV,Reserved area"
rbitfld.long 0x00 0.--1. "OPS,OPerating mode Status" "0,1,2,3"
group.long 0x10++0x03
line.long 0x00 "GWIRC3,"
rbitfld.long 0x00 31. "RSV7,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "IPVR7,IPV remapping i Functions: Configure to which descriptor queue descriptor received with IPV i will be stored (when a descriptor is received from forwarding engine with FDESCR.IPV [FWD] equal to i)" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 27. "RSV6,Reserved area" "0,1"
bitfld.long 0x00 24.--26. "IPVR6,IPV remapping i Functions: Configure to which descriptor queue descriptor received with IPV i will be stored (when a descriptor is received from forwarding engine with FDESCR.IPV [FWD] equal to i)" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 23. "RSV5,Reserved area" "0,1"
bitfld.long 0x00 20.--22. "IPVR5,IPV remapping i Functions: Configure to which descriptor queue descriptor received with IPV i will be stored (when a descriptor is received from forwarding engine with FDESCR.IPV [FWD] equal to i)" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "RSV4,Reserved area" "0,1"
bitfld.long 0x00 16.--18. "IPVR4,IPV remapping i Functions: Configure to which descriptor queue descriptor received with IPV i will be stored (when a descriptor is received from forwarding engine with FDESCR.IPV [FWD] equal to i)" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 15. "RSV3,Reserved area" "0,1"
newline
bitfld.long 0x00 12.--14. "IPVR3,IPV remapping i Functions: Configure to which descriptor queue descriptor received with IPV i will be stored (when a descriptor is received from forwarding engine with FDESCR.IPV [FWD] equal to i)" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 11. "RSV2,Reserved area" "0,1"
bitfld.long 0x00 8.--10. "IPVR2,IPV remapping i Functions: Configure to which descriptor queue descriptor received with IPV i will be stored (when a descriptor is received from forwarding engine with FDESCR.IPV [FWD] equal to i)" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 7. "RSV1,Reserved area" "0,1"
bitfld.long 0x00 4.--6. "IPVR1,IPV remapping i Functions: Configure to which descriptor queue descriptor received with IPV i will be stored (when a descriptor is received from forwarding engine with FDESCR.IPV [FWD] equal to i)" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 3. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 0.--2. "IPVR0,IPV remapping i Functions: Configure to which descriptor queue descriptor received with IPV i will be stored (when a descriptor is received from forwarding engine with FDESCR.IPV [FWD] equal to i)" "0,1,2,3,4,5,6,7"
group.long 0x14++0x03
line.long 0x00 "GWRDQSC3,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
bitfld.long 0x00 7. "RDQSL7,RX Descriptor Queue Security Level i" "0,1"
bitfld.long 0x00 6. "RDQSL6,RX Descriptor Queue Security Level i" "0,1"
bitfld.long 0x00 5. "RDQSL5,RX Descriptor Queue Security Level i" "0,1"
bitfld.long 0x00 4. "RDQSL4,RX Descriptor Queue Security Level i" "0,1"
bitfld.long 0x00 3. "RDQSL3,RX Descriptor Queue Security Level i" "0,1"
bitfld.long 0x00 2. "RDQSL2,RX Descriptor Queue Security Level i" "0,1"
bitfld.long 0x00 1. "RDQSL1,RX Descriptor Queue Security Level i" "0,1"
bitfld.long 0x00 0. "RDQSL0,RX Descriptor Queue Security Level i" "0,1"
group.long 0x18++0x03
line.long 0x00 "GWRDQC3,"
hexmask.long.byte 0x00 24.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 23. "RDQP7,RX Descriptor Queue Pause i" "0,1"
bitfld.long 0x00 22. "RDQP6,RX Descriptor Queue Pause i" "0,1"
bitfld.long 0x00 21. "RDQP5,RX Descriptor Queue Pause i" "0,1"
bitfld.long 0x00 20. "RDQP4,RX Descriptor Queue Pause i" "0,1"
bitfld.long 0x00 19. "RDQP3,RX Descriptor Queue Pause i" "0,1"
bitfld.long 0x00 18. "RDQP2,RX Descriptor Queue Pause i" "0,1"
bitfld.long 0x00 17. "RDQP1,RX Descriptor Queue Pause i" "0,1"
bitfld.long 0x00 16. "RDQP0,RX Descriptor Queue Pause i" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "RSV1,Reserved area"
bitfld.long 0x00 7. "RDQD7,RX Descriptor Queue Disable i" "0,1"
bitfld.long 0x00 6. "RDQD6,RX Descriptor Queue Disable i" "0,1"
bitfld.long 0x00 5. "RDQD5,RX Descriptor Queue Disable i" "0,1"
bitfld.long 0x00 4. "RDQD4,RX Descriptor Queue Disable i" "0,1"
bitfld.long 0x00 3. "RDQD3,RX Descriptor Queue Disable i" "0,1"
bitfld.long 0x00 2. "RDQD2,RX Descriptor Queue Disable i" "0,1"
bitfld.long 0x00 1. "RDQD1,RX Descriptor Queue Disable i" "0,1"
bitfld.long 0x00 0. "RDQD0,RX Descriptor Queue Disable i" "0,1"
group.long 0x1C++0x03
line.long 0x00 "GWRDQAC3,"
bitfld.long 0x00 28.--31. "RDQA7,RX Descriptor Queue Arbitration i" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "RDQA6,RX Descriptor Queue Arbitration i" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 20.--23. "RDQA5,RX Descriptor Queue Arbitration i" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "RDQA4,RX Descriptor Queue Arbitration i" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "RDQA3,RX Descriptor Queue Arbitration i" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "RDQA2,RX Descriptor Queue Arbitration i" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "RDQA1,RX Descriptor Queue Arbitration i" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "RDQA0,RX Descriptor Queue Arbitration i" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x20++0x03
line.long 0x00 "GWRGC3,"
hexmask.long 0x00 1.--31. 1. "RSV,Reserved area"
bitfld.long 0x00 0. "RCPT,Receive CRC Pass Through [802.3] This bit selects to pass FCS field on the reception frame" "0,1"
group.long 0x40++0x03
line.long 0x00 "GWRMFSC0_3,"
hexmask.long.word 0x00 16.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--15. 1. "MFSq,Maximum Frame Size q Functions: Maximum frame size for descriptor queue q"
group.long 0x44++0x03
line.long 0x00 "GWRMFSC1_3,"
hexmask.long.word 0x00 16.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--15. 1. "MFSq,Maximum Frame Size q Functions: Maximum frame size for descriptor queue q"
group.long 0x48++0x03
line.long 0x00 "GWRMFSC2_3,"
hexmask.long.word 0x00 16.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--15. 1. "MFSq,Maximum Frame Size q Functions: Maximum frame size for descriptor queue q"
group.long 0x4C++0x03
line.long 0x00 "GWRMFSC3_3,"
hexmask.long.word 0x00 16.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--15. 1. "MFSq,Maximum Frame Size q Functions: Maximum frame size for descriptor queue q"
group.long 0x50++0x03
line.long 0x00 "GWRMFSC4_3,"
hexmask.long.word 0x00 16.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--15. 1. "MFSq,Maximum Frame Size q Functions: Maximum frame size for descriptor queue q"
group.long 0x54++0x03
line.long 0x00 "GWRMFSC5_3,"
hexmask.long.word 0x00 16.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--15. 1. "MFSq,Maximum Frame Size q Functions: Maximum frame size for descriptor queue q"
group.long 0x58++0x03
line.long 0x00 "GWRMFSC6_3,"
hexmask.long.word 0x00 16.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--15. 1. "MFSq,Maximum Frame Size q Functions: Maximum frame size for descriptor queue q"
group.long 0x5C++0x03
line.long 0x00 "GWRMFSC7_3,"
hexmask.long.word 0x00 16.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--15. 1. "MFSq,Maximum Frame Size q Functions: Maximum frame size for descriptor queue q"
group.long 0x60++0x03
line.long 0x00 "GWRDQDC0_3,"
hexmask.long.tbyte 0x00 11.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--10. 1. "DQDq,Descriptor Queue Depth q Functions?: Number of descriptors that can contain descriptor queue q"
group.long 0x64++0x03
line.long 0x00 "GWRDQDC1_3,"
hexmask.long.tbyte 0x00 11.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--10. 1. "DQDq,Descriptor Queue Depth q Functions?: Number of descriptors that can contain descriptor queue q"
group.long 0x68++0x03
line.long 0x00 "GWRDQDC2_3,"
hexmask.long.tbyte 0x00 11.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--10. 1. "DQDq,Descriptor Queue Depth q Functions?: Number of descriptors that can contain descriptor queue q"
group.long 0x6C++0x03
line.long 0x00 "GWRDQDC3_3,"
hexmask.long.tbyte 0x00 11.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--10. 1. "DQDq,Descriptor Queue Depth q Functions?: Number of descriptors that can contain descriptor queue q"
group.long 0x70++0x03
line.long 0x00 "GWRDQDC4_3,"
hexmask.long.tbyte 0x00 11.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--10. 1. "DQDq,Descriptor Queue Depth q Functions?: Number of descriptors that can contain descriptor queue q"
group.long 0x74++0x03
line.long 0x00 "GWRDQDC5_3,"
hexmask.long.tbyte 0x00 11.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--10. 1. "DQDq,Descriptor Queue Depth q Functions?: Number of descriptors that can contain descriptor queue q"
group.long 0x78++0x03
line.long 0x00 "GWRDQDC6_3,"
hexmask.long.tbyte 0x00 11.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--10. 1. "DQDq,Descriptor Queue Depth q Functions?: Number of descriptors that can contain descriptor queue q"
group.long 0x7C++0x03
line.long 0x00 "GWRDQDC7_3,"
hexmask.long.tbyte 0x00 11.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--10. 1. "DQDq,Descriptor Queue Depth q Functions?: Number of descriptors that can contain descriptor queue q"
group.long 0x80++0x03
line.long 0x00 "GWRDQM0_3,"
hexmask.long.tbyte 0x00 11.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--10. 1. "DNQq,Descriptor Number in Queue q"
group.long 0x84++0x03
line.long 0x00 "GWRDQM1_3,"
hexmask.long.tbyte 0x00 11.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--10. 1. "DNQq,Descriptor Number in Queue q"
group.long 0x88++0x03
line.long 0x00 "GWRDQM2_3,"
hexmask.long.tbyte 0x00 11.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--10. 1. "DNQq,Descriptor Number in Queue q"
group.long 0x8C++0x03
line.long 0x00 "GWRDQM3_3,"
hexmask.long.tbyte 0x00 11.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--10. 1. "DNQq,Descriptor Number in Queue q"
group.long 0x90++0x03
line.long 0x00 "GWRDQM4_3,"
hexmask.long.tbyte 0x00 11.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--10. 1. "DNQq,Descriptor Number in Queue q"
group.long 0x94++0x03
line.long 0x00 "GWRDQM5_3,"
hexmask.long.tbyte 0x00 11.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--10. 1. "DNQq,Descriptor Number in Queue q"
group.long 0x98++0x03
line.long 0x00 "GWRDQM6_3,"
hexmask.long.tbyte 0x00 11.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--10. 1. "DNQq,Descriptor Number in Queue q"
group.long 0x9C++0x03
line.long 0x00 "GWRDQM7_3,"
hexmask.long.tbyte 0x00 11.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--10. 1. "DNQq,Descriptor Number in Queue q"
group.long 0xA0++0x03
line.long 0x00 "GWRDQMLM0_3,"
hexmask.long.tbyte 0x00 11.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--10. 1. "DMLQq,Descriptor Max Level in Queue q"
group.long 0xA4++0x03
line.long 0x00 "GWRDQMLM1_3,"
hexmask.long.tbyte 0x00 11.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--10. 1. "DMLQq,Descriptor Max Level in Queue q"
group.long 0xA8++0x03
line.long 0x00 "GWRDQMLM2_3,"
hexmask.long.tbyte 0x00 11.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--10. 1. "DMLQq,Descriptor Max Level in Queue q"
group.long 0xAC++0x03
line.long 0x00 "GWRDQMLM3_3,"
hexmask.long.tbyte 0x00 11.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--10. 1. "DMLQq,Descriptor Max Level in Queue q"
group.long 0xB0++0x03
line.long 0x00 "GWRDQMLM4_3,"
hexmask.long.tbyte 0x00 11.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--10. 1. "DMLQq,Descriptor Max Level in Queue q"
group.long 0xB4++0x03
line.long 0x00 "GWRDQMLM5_3,"
hexmask.long.tbyte 0x00 11.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--10. 1. "DMLQq,Descriptor Max Level in Queue q"
group.long 0xB8++0x03
line.long 0x00 "GWRDQMLM6_3,"
hexmask.long.tbyte 0x00 11.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--10. 1. "DMLQq,Descriptor Max Level in Queue q"
group.long 0xBC++0x03
line.long 0x00 "GWRDQMLM7_3,"
hexmask.long.tbyte 0x00 11.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--10. 1. "DMLQq,Descriptor Max Level in Queue q"
group.long 0x100++0x03
line.long 0x00 "GWMTIRM3,"
hexmask.long 0x00 2.--31. 1. "RSV,Reserved area"
rbitfld.long 0x00 1. "MTR,Multicast Table Ready Set conditions: When GWMTIRM.MTIOG is getting cleared" "0,1"
bitfld.long 0x00 0. "MTIOG,Multicast Table Initialization Ongoing" "0,1"
group.long 0x104++0x03
line.long 0x00 "GWMSTLS3,"
hexmask.long.word 0x00 23.--31. 1. "RSV0,Reserved area"
hexmask.long.byte 0x00 16.--22. 1. "MSENL,Multicast Setting Entry Number Learn"
rbitfld.long 0x00 11.--15. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MNL,Multicast Number Learn" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 7. "RSV2,Reserved area" "0,1"
hexmask.long.byte 0x00 0.--6. 1. "MNRCNL,Multicast Next Descriptor Chain Number Learn"
group.long 0x108++0x03
line.long 0x00 "GWMSTLR3,"
rbitfld.long 0x00 31. "MTL,Multicast Table Learning Set conditions: SW: Writing GWMSTLS register will set this bit" "0,1"
hexmask.long 0x00 2.--30. 1. "RSV,Reserved area"
rbitfld.long 0x00 1. "MTLSF,Multicast Table Learning Security Fail Values: 1b0: Entry learning didnt fail because of a security error" "0,1"
rbitfld.long 0x00 0. "MTLF,Multicast Table Learning Fail Values: 1b0: Entry learning didnt fail because the Multicast table is not ready" "0,1"
group.long 0x10C++0x03
line.long 0x00 "GWMSTSS3,"
hexmask.long 0x00 7.--31. 1. "RSV,Reserved area"
hexmask.long.byte 0x00 0.--6. 1. "MSENS,Multicast Setting Entry Number Search"
group.long 0x110++0x03
line.long 0x00 "GWMSTSR3,"
rbitfld.long 0x00 31. "MTS,Multicast Table Searching Set conditions: SW: Writing GWMSTSS register will set this bit" "0,1"
hexmask.long.word 0x00 17.--30. 1. "RSV0,Reserved area"
rbitfld.long 0x00 16. "MTSEF,Multicast Table Searching ECC Fail Values: 1b0: Entry searching didnt fail because of an ECC error" "0,1"
rbitfld.long 0x00 11.--15. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rbitfld.long 0x00 8.--10. "MNR,Multicast Number result" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 7. "RSV2,Reserved area" "0,1"
hexmask.long.byte 0x00 0.--6. 1. "MNRCNR,Multicast Next RX Descriptor Chain Number result"
group.long 0x120++0x03
line.long 0x00 "GWMAC03,"
hexmask.long.word 0x00 16.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--15. 1. "MAUP,MAC Address Upper Part Functions: These bits are used to set the 16 higher-order bits of the MAC address"
group.long 0x124++0x03
line.long 0x00 "GWMAC13,"
hexmask.long 0x00 0.--31. 1. "MADP,MAC Address Downer Part Functions: These bits are used to set the 32 lower-order bits of the MAC address"
group.long 0x130++0x03
line.long 0x00 "GWVCC3,"
hexmask.long.word 0x00 19.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 16.--18. "VEM,VLAN Egress Mode Values?: 3b000: No VLAN mode frames are transmitted with no VLAN 3b001: C-TAG VLAN mode frames are transmitted with ingress C-TAG if there is one stored in the Local RAM" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 1.--15. 1. "RSV1,Reserved area"
bitfld.long 0x00 0. "VIM,VLAN Ingress Mode Values?: 1b0: Incoming VLAN mode 1b1: Port based VLAN mode Restrictions?: SW: This register shouldnt be set to 1b1 is the switch is in no VLAN mode (In forwarding engine FWGC.SVM is set to 2b00 [FWD]) A security register.." "0,1"
group.long 0x134++0x03
line.long 0x00 "GWVTC3,"
bitfld.long 0x00 31. "STD_P,S-TAG DEI" "0,1"
bitfld.long 0x00 28.--30. "STP_P,S-TAG PCP" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 16.--27. 1. "STV_P,S-TAG VLAN"
bitfld.long 0x00 15. "CTD_P,C-TAG DEI" "0,1"
bitfld.long 0x00 12.--14. "CTP_P,C-TAG PCP" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 0.--11. 1. "CTV_P,C-TAG VLAN"
group.long 0x138++0x03
line.long 0x00 "GWTTFC3,"
hexmask.long.tbyte 0x00 9.--31. 1. "RSV,Reserved area"
bitfld.long 0x00 8. "UT,Unknown TAG Values: 1b0: Unknow Tag frame passed 1b1: Unknow Tag frame rejected A security register should be set to authorize write/read access by the unsecure APB" "0,1"
bitfld.long 0x00 7. "SCRT,SCR-TAG Values: 1b0: SCR-TAG frame passed 1b1: SCR-TAG frame rejected A security register should be set to authorize write/read access by the unsecure APB" "0,1"
bitfld.long 0x00 6. "SCT,SC-TAG Values: 1b0: SC-TAG frame passed 1b1: SC-TAG frame rejected A security register should be set to authorize write/read access by the unsecure APB" "0,1"
bitfld.long 0x00 5. "CRT,CR-TAG Values: 1b0: CR-TAG frame passed 1b1: CR-TAG frame rejected A security register should be set to authorize write/read access by the unsecure APB" "0,1"
bitfld.long 0x00 4. "CT,C-TAG Values: 1b0: C-TAG frame passed 1b1: C-TAG frame rejected A security register should be set to authorize write/read access by the unsecure APB" "0,1"
bitfld.long 0x00 3. "CSRT,CoSR-TAG Values: 1b0: CoSR-TAG frame passed 1b1: CoSR-TAG frame rejected A security register should be set to authorize write/read access by the unsecure APB" "0,1"
bitfld.long 0x00 2. "CST,CoS-TAG Values: 1b0: CoS-TAG frame passed 1b1: CoS-TAG frame rejected A security register should be set to authorize write/read access by the unsecure APB" "0,1"
bitfld.long 0x00 1. "RT,R-TAG Values: 1b0: R-TAG frame passed 1b1: R-TAG frame rejected A security register should be set to authorize write/read access by the unsecure APB" "0,1"
newline
bitfld.long 0x00 0. "NT,No Tag Values: 1b0: No Tag frame passed 1b1: No Tag frame rejected A security register should be set to authorize write/read access by the unsecure APB" "0,1"
group.long 0x140++0x03
line.long 0x00 "GWTDCAC00_3,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
hexmask.long.byte 0x00 0.--7. 1. "TSCCAUPs,TS Descriptor Chain s Current Address Upper Part Update conditions: SW: Writing to this field with update it to the write value"
group.long 0x144++0x03
line.long 0x00 "GWTDCAC10_3,"
hexmask.long 0x00 0.--31. 1. "TSCCADPs,TS Descriptor Chain s Current Address Downer Part Update conditions: SW: Writing GWTDCAC0s register with update this field to the previous value written on it by the same APB"
group.long 0x148++0x03
line.long 0x00 "GWTDCAC01_3,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
hexmask.long.byte 0x00 0.--7. 1. "TSCCAUPs,TS Descriptor Chain s Current Address Upper Part Update conditions: SW: Writing to this field with update it to the write value"
group.long 0x14C++0x03
line.long 0x00 "GWTDCAC11_3,"
hexmask.long 0x00 0.--31. 1. "TSCCADPs,TS Descriptor Chain s Current Address Downer Part Update conditions: SW: Writing GWTDCAC0s register with update this field to the previous value written on it by the same APB"
group.long 0x160++0x03
line.long 0x00 "GWTSDCC0_3,"
hexmask.long.tbyte 0x00 11.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 8.--10. "OSIDs,OS ID s Functions: When a memory access is done for timer number s the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 3.--7. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 1.--2. "DCSs,Descriptor chain select Functions: Select to which chain timestamps taken with timer s will be received" "0,1,2,3"
bitfld.long 0x00 0. "TEs,Timer enable s" "0,1"
group.long 0x164++0x03
line.long 0x00 "GWTSDCC1_3,"
hexmask.long.tbyte 0x00 11.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 8.--10. "OSIDs,OS ID s Functions: When a memory access is done for timer number s the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 3.--7. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 1.--2. "DCSs,Descriptor chain select Functions: Select to which chain timestamps taken with timer s will be received" "0,1,2,3"
bitfld.long 0x00 0. "TEs,Timer enable s" "0,1"
group.long 0x180++0x03
line.long 0x00 "GWTSNM3,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
hexmask.long.byte 0x00 0.--7. 1. "TNTR,Timestamp Number in Timestamp RAM Increment conditions: HW: Incremented by 1 when a timestamp is received from a TSN Agent"
group.long 0x184++0x03
line.long 0x00 "GWTSMNM3,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
hexmask.long.byte 0x00 0.--7. 1. "TMNTR,Timestamp Maximum Number in Timestamp RAM Update conditions: HW: Set to GWTSNM.TNTR when GWTSNM.TNTR> GWTSNM.TMNTR"
group.long 0x190++0x03
line.long 0x00 "GWAC3,"
hexmask.long 0x00 2.--31. 1. "RSV,Reserved area"
rbitfld.long 0x00 1. "AMP,AXI Master Paused Values: 1b0: AXI master not paused (transaction ongoing) 1b1: AXI master paused (no transaction ongoing) Set conditions: HW: When GWAC.AMPR is set to 1b1 and all ongoing AXI transactions are completed this bit will be set" "0,1"
bitfld.long 0x00 0. "AMPR,AXI Master Pause Request Values: 1b0: AXI master pause not requested 1b1: AXI master pause requested Functions: This register blocks the AXI master from making new accesses (Because the AXI master has register slices for timing purpose few AXI.." "0,1"
group.long 0x194++0x03
line.long 0x00 "GWDCBAC03,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
hexmask.long.byte 0x00 0.--7. 1. "DCBAUP,Descriptor Chain Base Address Upper Part"
group.long 0x198++0x03
line.long 0x00 "GWDCBAC13,"
hexmask.long 0x00 0.--31. 1. "DCBADP,Descriptor Chain Base Address Downer Part"
group.long 0x1A0++0x03
line.long 0x00 "GWMDNC3,"
hexmask.long.word 0x00 18.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 16.--17. "TSDMN,TimeStamp Descriptor Maximum Number" "0,1,2,3"
rbitfld.long 0x00 13.--15. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--12. "TXDMN,TX Descriptor Maximum Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rbitfld.long 0x00 5.--7. "RSV2,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "RXDMN,RX Descriptor Maximum Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x200++0x03
line.long 0x00 "GWTRC0_3,"
bitfld.long 0x00 31. "TSR31,Transmission Start Request t" "0,1"
bitfld.long 0x00 30. "TSR30,Transmission Start Request t" "0,1"
bitfld.long 0x00 29. "TSR29,Transmission Start Request t" "0,1"
bitfld.long 0x00 28. "TSR28,Transmission Start Request t" "0,1"
bitfld.long 0x00 27. "TSR27,Transmission Start Request t" "0,1"
bitfld.long 0x00 26. "TSR26,Transmission Start Request t" "0,1"
bitfld.long 0x00 25. "TSR25,Transmission Start Request t" "0,1"
bitfld.long 0x00 24. "TSR24,Transmission Start Request t" "0,1"
bitfld.long 0x00 23. "TSR23,Transmission Start Request t" "0,1"
newline
bitfld.long 0x00 22. "TSR22,Transmission Start Request t" "0,1"
bitfld.long 0x00 21. "TSR21,Transmission Start Request t" "0,1"
bitfld.long 0x00 20. "TSR20,Transmission Start Request t" "0,1"
bitfld.long 0x00 19. "TSR19,Transmission Start Request t" "0,1"
bitfld.long 0x00 18. "TSR18,Transmission Start Request t" "0,1"
bitfld.long 0x00 17. "TSR17,Transmission Start Request t" "0,1"
bitfld.long 0x00 16. "TSR16,Transmission Start Request t" "0,1"
bitfld.long 0x00 15. "TSR15,Transmission Start Request t" "0,1"
bitfld.long 0x00 14. "TSR14,Transmission Start Request t" "0,1"
newline
bitfld.long 0x00 13. "TSR13,Transmission Start Request t" "0,1"
bitfld.long 0x00 12. "TSR12,Transmission Start Request t" "0,1"
bitfld.long 0x00 11. "TSR11,Transmission Start Request t" "0,1"
bitfld.long 0x00 10. "TSR10,Transmission Start Request t" "0,1"
bitfld.long 0x00 9. "TSR9,Transmission Start Request t" "0,1"
bitfld.long 0x00 8. "TSR8,Transmission Start Request t" "0,1"
bitfld.long 0x00 7. "TSR7,Transmission Start Request t" "0,1"
bitfld.long 0x00 6. "TSR6,Transmission Start Request t" "0,1"
bitfld.long 0x00 5. "TSR5,Transmission Start Request t" "0,1"
newline
bitfld.long 0x00 4. "TSR4,Transmission Start Request t" "0,1"
bitfld.long 0x00 3. "TSR3,Transmission Start Request t" "0,1"
bitfld.long 0x00 2. "TSR2,Transmission Start Request t" "0,1"
bitfld.long 0x00 1. "TSR1,Transmission Start Request t" "0,1"
bitfld.long 0x00 0. "TSR0,Transmission Start Request t" "0,1"
group.long 0x204++0x03
line.long 0x00 "GWTRC1_3,"
bitfld.long 0x00 31. "TSR31,Transmission Start Request t" "0,1"
bitfld.long 0x00 30. "TSR30,Transmission Start Request t" "0,1"
bitfld.long 0x00 29. "TSR29,Transmission Start Request t" "0,1"
bitfld.long 0x00 28. "TSR28,Transmission Start Request t" "0,1"
bitfld.long 0x00 27. "TSR27,Transmission Start Request t" "0,1"
bitfld.long 0x00 26. "TSR26,Transmission Start Request t" "0,1"
bitfld.long 0x00 25. "TSR25,Transmission Start Request t" "0,1"
bitfld.long 0x00 24. "TSR24,Transmission Start Request t" "0,1"
bitfld.long 0x00 23. "TSR23,Transmission Start Request t" "0,1"
newline
bitfld.long 0x00 22. "TSR22,Transmission Start Request t" "0,1"
bitfld.long 0x00 21. "TSR21,Transmission Start Request t" "0,1"
bitfld.long 0x00 20. "TSR20,Transmission Start Request t" "0,1"
bitfld.long 0x00 19. "TSR19,Transmission Start Request t" "0,1"
bitfld.long 0x00 18. "TSR18,Transmission Start Request t" "0,1"
bitfld.long 0x00 17. "TSR17,Transmission Start Request t" "0,1"
bitfld.long 0x00 16. "TSR16,Transmission Start Request t" "0,1"
bitfld.long 0x00 15. "TSR15,Transmission Start Request t" "0,1"
bitfld.long 0x00 14. "TSR14,Transmission Start Request t" "0,1"
newline
bitfld.long 0x00 13. "TSR13,Transmission Start Request t" "0,1"
bitfld.long 0x00 12. "TSR12,Transmission Start Request t" "0,1"
bitfld.long 0x00 11. "TSR11,Transmission Start Request t" "0,1"
bitfld.long 0x00 10. "TSR10,Transmission Start Request t" "0,1"
bitfld.long 0x00 9. "TSR9,Transmission Start Request t" "0,1"
bitfld.long 0x00 8. "TSR8,Transmission Start Request t" "0,1"
bitfld.long 0x00 7. "TSR7,Transmission Start Request t" "0,1"
bitfld.long 0x00 6. "TSR6,Transmission Start Request t" "0,1"
bitfld.long 0x00 5. "TSR5,Transmission Start Request t" "0,1"
newline
bitfld.long 0x00 4. "TSR4,Transmission Start Request t" "0,1"
bitfld.long 0x00 3. "TSR3,Transmission Start Request t" "0,1"
bitfld.long 0x00 2. "TSR2,Transmission Start Request t" "0,1"
bitfld.long 0x00 1. "TSR1,Transmission Start Request t" "0,1"
bitfld.long 0x00 0. "TSR0,Transmission Start Request t" "0,1"
group.long 0x208++0x03
line.long 0x00 "GWTRC2_3,"
bitfld.long 0x00 31. "TSR31,Transmission Start Request t" "0,1"
bitfld.long 0x00 30. "TSR30,Transmission Start Request t" "0,1"
bitfld.long 0x00 29. "TSR29,Transmission Start Request t" "0,1"
bitfld.long 0x00 28. "TSR28,Transmission Start Request t" "0,1"
bitfld.long 0x00 27. "TSR27,Transmission Start Request t" "0,1"
bitfld.long 0x00 26. "TSR26,Transmission Start Request t" "0,1"
bitfld.long 0x00 25. "TSR25,Transmission Start Request t" "0,1"
bitfld.long 0x00 24. "TSR24,Transmission Start Request t" "0,1"
bitfld.long 0x00 23. "TSR23,Transmission Start Request t" "0,1"
newline
bitfld.long 0x00 22. "TSR22,Transmission Start Request t" "0,1"
bitfld.long 0x00 21. "TSR21,Transmission Start Request t" "0,1"
bitfld.long 0x00 20. "TSR20,Transmission Start Request t" "0,1"
bitfld.long 0x00 19. "TSR19,Transmission Start Request t" "0,1"
bitfld.long 0x00 18. "TSR18,Transmission Start Request t" "0,1"
bitfld.long 0x00 17. "TSR17,Transmission Start Request t" "0,1"
bitfld.long 0x00 16. "TSR16,Transmission Start Request t" "0,1"
bitfld.long 0x00 15. "TSR15,Transmission Start Request t" "0,1"
bitfld.long 0x00 14. "TSR14,Transmission Start Request t" "0,1"
newline
bitfld.long 0x00 13. "TSR13,Transmission Start Request t" "0,1"
bitfld.long 0x00 12. "TSR12,Transmission Start Request t" "0,1"
bitfld.long 0x00 11. "TSR11,Transmission Start Request t" "0,1"
bitfld.long 0x00 10. "TSR10,Transmission Start Request t" "0,1"
bitfld.long 0x00 9. "TSR9,Transmission Start Request t" "0,1"
bitfld.long 0x00 8. "TSR8,Transmission Start Request t" "0,1"
bitfld.long 0x00 7. "TSR7,Transmission Start Request t" "0,1"
bitfld.long 0x00 6. "TSR6,Transmission Start Request t" "0,1"
bitfld.long 0x00 5. "TSR5,Transmission Start Request t" "0,1"
newline
bitfld.long 0x00 4. "TSR4,Transmission Start Request t" "0,1"
bitfld.long 0x00 3. "TSR3,Transmission Start Request t" "0,1"
bitfld.long 0x00 2. "TSR2,Transmission Start Request t" "0,1"
bitfld.long 0x00 1. "TSR1,Transmission Start Request t" "0,1"
bitfld.long 0x00 0. "TSR0,Transmission Start Request t" "0,1"
group.long 0x20C++0x03
line.long 0x00 "GWTRC3_3,"
bitfld.long 0x00 31. "TSR31,Transmission Start Request t" "0,1"
bitfld.long 0x00 30. "TSR30,Transmission Start Request t" "0,1"
bitfld.long 0x00 29. "TSR29,Transmission Start Request t" "0,1"
bitfld.long 0x00 28. "TSR28,Transmission Start Request t" "0,1"
bitfld.long 0x00 27. "TSR27,Transmission Start Request t" "0,1"
bitfld.long 0x00 26. "TSR26,Transmission Start Request t" "0,1"
bitfld.long 0x00 25. "TSR25,Transmission Start Request t" "0,1"
bitfld.long 0x00 24. "TSR24,Transmission Start Request t" "0,1"
bitfld.long 0x00 23. "TSR23,Transmission Start Request t" "0,1"
newline
bitfld.long 0x00 22. "TSR22,Transmission Start Request t" "0,1"
bitfld.long 0x00 21. "TSR21,Transmission Start Request t" "0,1"
bitfld.long 0x00 20. "TSR20,Transmission Start Request t" "0,1"
bitfld.long 0x00 19. "TSR19,Transmission Start Request t" "0,1"
bitfld.long 0x00 18. "TSR18,Transmission Start Request t" "0,1"
bitfld.long 0x00 17. "TSR17,Transmission Start Request t" "0,1"
bitfld.long 0x00 16. "TSR16,Transmission Start Request t" "0,1"
bitfld.long 0x00 15. "TSR15,Transmission Start Request t" "0,1"
bitfld.long 0x00 14. "TSR14,Transmission Start Request t" "0,1"
newline
bitfld.long 0x00 13. "TSR13,Transmission Start Request t" "0,1"
bitfld.long 0x00 12. "TSR12,Transmission Start Request t" "0,1"
bitfld.long 0x00 11. "TSR11,Transmission Start Request t" "0,1"
bitfld.long 0x00 10. "TSR10,Transmission Start Request t" "0,1"
bitfld.long 0x00 9. "TSR9,Transmission Start Request t" "0,1"
bitfld.long 0x00 8. "TSR8,Transmission Start Request t" "0,1"
bitfld.long 0x00 7. "TSR7,Transmission Start Request t" "0,1"
bitfld.long 0x00 6. "TSR6,Transmission Start Request t" "0,1"
bitfld.long 0x00 5. "TSR5,Transmission Start Request t" "0,1"
newline
bitfld.long 0x00 4. "TSR4,Transmission Start Request t" "0,1"
bitfld.long 0x00 3. "TSR3,Transmission Start Request t" "0,1"
bitfld.long 0x00 2. "TSR2,Transmission Start Request t" "0,1"
bitfld.long 0x00 1. "TSR1,Transmission Start Request t" "0,1"
bitfld.long 0x00 0. "TSR0,Transmission Start Request t" "0,1"
group.long 0x300++0x03
line.long 0x00 "GWTPC0_3,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
bitfld.long 0x00 7. "PPPLp7,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 6. "PPPLp6,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 5. "PPPLp5,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 4. "PPPLp4,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 3. "PPPLp3,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 2. "PPPLp2,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 1. "PPPLp1,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 0. "PPPLp0,Per Priority Pause Level p i" "0,1"
group.long 0x304++0x03
line.long 0x00 "GWTPC1_3,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
bitfld.long 0x00 7. "PPPLp7,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 6. "PPPLp6,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 5. "PPPLp5,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 4. "PPPLp4,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 3. "PPPLp3,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 2. "PPPLp2,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 1. "PPPLp1,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 0. "PPPLp0,Per Priority Pause Level p i" "0,1"
group.long 0x308++0x03
line.long 0x00 "GWTPC2_3,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
bitfld.long 0x00 7. "PPPLp7,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 6. "PPPLp6,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 5. "PPPLp5,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 4. "PPPLp4,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 3. "PPPLp3,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 2. "PPPLp2,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 1. "PPPLp1,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 0. "PPPLp0,Per Priority Pause Level p i" "0,1"
group.long 0x30C++0x03
line.long 0x00 "GWTPC3_3,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
bitfld.long 0x00 7. "PPPLp7,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 6. "PPPLp6,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 5. "PPPLp5,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 4. "PPPLp4,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 3. "PPPLp3,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 2. "PPPLp2,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 1. "PPPLp1,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 0. "PPPLp0,Per Priority Pause Level p i" "0,1"
group.long 0x310++0x03
line.long 0x00 "GWTPC4_3,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
bitfld.long 0x00 7. "PPPLp7,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 6. "PPPLp6,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 5. "PPPLp5,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 4. "PPPLp4,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 3. "PPPLp3,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 2. "PPPLp2,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 1. "PPPLp1,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 0. "PPPLp0,Per Priority Pause Level p i" "0,1"
group.long 0x314++0x03
line.long 0x00 "GWTPC5_3,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
bitfld.long 0x00 7. "PPPLp7,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 6. "PPPLp6,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 5. "PPPLp5,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 4. "PPPLp4,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 3. "PPPLp3,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 2. "PPPLp2,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 1. "PPPLp1,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 0. "PPPLp0,Per Priority Pause Level p i" "0,1"
group.long 0x318++0x03
line.long 0x00 "GWTPC6_3,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
bitfld.long 0x00 7. "PPPLp7,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 6. "PPPLp6,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 5. "PPPLp5,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 4. "PPPLp4,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 3. "PPPLp3,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 2. "PPPLp2,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 1. "PPPLp1,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 0. "PPPLp0,Per Priority Pause Level p i" "0,1"
group.long 0x31C++0x03
line.long 0x00 "GWTPC7_3,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
bitfld.long 0x00 7. "PPPLp7,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 6. "PPPLp6,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 5. "PPPLp5,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 4. "PPPLp4,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 3. "PPPLp3,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 2. "PPPLp2,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 1. "PPPLp1,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 0. "PPPLp0,Per Priority Pause Level p i" "0,1"
group.long 0x320++0x03
line.long 0x00 "GWTPC8_3,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
bitfld.long 0x00 7. "PPPLp7,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 6. "PPPLp6,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 5. "PPPLp5,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 4. "PPPLp4,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 3. "PPPLp3,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 2. "PPPLp2,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 1. "PPPLp1,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 0. "PPPLp0,Per Priority Pause Level p i" "0,1"
group.long 0x324++0x03
line.long 0x00 "GWTPC9_3,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
bitfld.long 0x00 7. "PPPLp7,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 6. "PPPLp6,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 5. "PPPLp5,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 4. "PPPLp4,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 3. "PPPLp3,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 2. "PPPLp2,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 1. "PPPLp1,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 0. "PPPLp0,Per Priority Pause Level p i" "0,1"
group.long 0x328++0x03
line.long 0x00 "GWTPC10_3,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
bitfld.long 0x00 7. "PPPLp7,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 6. "PPPLp6,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 5. "PPPLp5,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 4. "PPPLp4,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 3. "PPPLp3,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 2. "PPPLp2,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 1. "PPPLp1,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 0. "PPPLp0,Per Priority Pause Level p i" "0,1"
group.long 0x32C++0x03
line.long 0x00 "GWTPC11_3,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
bitfld.long 0x00 7. "PPPLp7,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 6. "PPPLp6,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 5. "PPPLp5,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 4. "PPPLp4,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 3. "PPPLp3,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 2. "PPPLp2,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 1. "PPPLp1,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 0. "PPPLp0,Per Priority Pause Level p i" "0,1"
group.long 0x330++0x03
line.long 0x00 "GWTPC12_3,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
bitfld.long 0x00 7. "PPPLp7,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 6. "PPPLp6,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 5. "PPPLp5,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 4. "PPPLp4,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 3. "PPPLp3,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 2. "PPPLp2,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 1. "PPPLp1,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 0. "PPPLp0,Per Priority Pause Level p i" "0,1"
group.long 0x334++0x03
line.long 0x00 "GWTPC13_3,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
bitfld.long 0x00 7. "PPPLp7,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 6. "PPPLp6,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 5. "PPPLp5,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 4. "PPPLp4,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 3. "PPPLp3,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 2. "PPPLp2,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 1. "PPPLp1,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 0. "PPPLp0,Per Priority Pause Level p i" "0,1"
group.long 0x338++0x03
line.long 0x00 "GWTPC14_3,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
bitfld.long 0x00 7. "PPPLp7,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 6. "PPPLp6,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 5. "PPPLp5,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 4. "PPPLp4,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 3. "PPPLp3,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 2. "PPPLp2,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 1. "PPPLp1,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 0. "PPPLp0,Per Priority Pause Level p i" "0,1"
group.long 0x33C++0x03
line.long 0x00 "GWTPC15_3,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
bitfld.long 0x00 7. "PPPLp7,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 6. "PPPLp6,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 5. "PPPLp5,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 4. "PPPLp4,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 3. "PPPLp3,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 2. "PPPLp2,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 1. "PPPLp1,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 0. "PPPLp0,Per Priority Pause Level p i" "0,1"
group.long 0x340++0x03
line.long 0x00 "GWTPC16_3,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
bitfld.long 0x00 7. "PPPLp7,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 6. "PPPLp6,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 5. "PPPLp5,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 4. "PPPLp4,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 3. "PPPLp3,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 2. "PPPLp2,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 1. "PPPLp1,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 0. "PPPLp0,Per Priority Pause Level p i" "0,1"
group.long 0x344++0x03
line.long 0x00 "GWTPC17_3,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
bitfld.long 0x00 7. "PPPLp7,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 6. "PPPLp6,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 5. "PPPLp5,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 4. "PPPLp4,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 3. "PPPLp3,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 2. "PPPLp2,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 1. "PPPLp1,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 0. "PPPLp0,Per Priority Pause Level p i" "0,1"
group.long 0x348++0x03
line.long 0x00 "GWTPC18_3,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
bitfld.long 0x00 7. "PPPLp7,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 6. "PPPLp6,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 5. "PPPLp5,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 4. "PPPLp4,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 3. "PPPLp3,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 2. "PPPLp2,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 1. "PPPLp1,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 0. "PPPLp0,Per Priority Pause Level p i" "0,1"
group.long 0x34C++0x03
line.long 0x00 "GWTPC19_3,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
bitfld.long 0x00 7. "PPPLp7,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 6. "PPPLp6,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 5. "PPPLp5,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 4. "PPPLp4,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 3. "PPPLp3,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 2. "PPPLp2,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 1. "PPPLp1,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 0. "PPPLp0,Per Priority Pause Level p i" "0,1"
group.long 0x350++0x03
line.long 0x00 "GWTPC20_3,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
bitfld.long 0x00 7. "PPPLp7,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 6. "PPPLp6,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 5. "PPPLp5,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 4. "PPPLp4,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 3. "PPPLp3,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 2. "PPPLp2,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 1. "PPPLp1,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 0. "PPPLp0,Per Priority Pause Level p i" "0,1"
group.long 0x380++0x03
line.long 0x00 "GWARIRM3,"
hexmask.long 0x00 2.--31. 1. "RSV,Reserved area"
rbitfld.long 0x00 1. "ARR,AXI RAM Ready Set conditions: When GWARIRM.ARIOG is getting cleared" "0,1"
bitfld.long 0x00 0. "ARIOG,AXI RAM Initialization Ongoing" "0,1"
group.long 0x400++0x03
line.long 0x00 "GWDCC0_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x404++0x03
line.long 0x00 "GWDCC1_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x408++0x03
line.long 0x00 "GWDCC2_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x40C++0x03
line.long 0x00 "GWDCC3_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x410++0x03
line.long 0x00 "GWDCC4_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x414++0x03
line.long 0x00 "GWDCC5_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x418++0x03
line.long 0x00 "GWDCC6_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x41C++0x03
line.long 0x00 "GWDCC7_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x420++0x03
line.long 0x00 "GWDCC8_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x424++0x03
line.long 0x00 "GWDCC9_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x428++0x03
line.long 0x00 "GWDCC10_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x42C++0x03
line.long 0x00 "GWDCC11_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x430++0x03
line.long 0x00 "GWDCC12_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x434++0x03
line.long 0x00 "GWDCC13_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x438++0x03
line.long 0x00 "GWDCC14_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x43C++0x03
line.long 0x00 "GWDCC15_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x440++0x03
line.long 0x00 "GWDCC16_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x444++0x03
line.long 0x00 "GWDCC17_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x448++0x03
line.long 0x00 "GWDCC18_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x44C++0x03
line.long 0x00 "GWDCC19_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x450++0x03
line.long 0x00 "GWDCC20_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x454++0x03
line.long 0x00 "GWDCC21_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x458++0x03
line.long 0x00 "GWDCC22_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x45C++0x03
line.long 0x00 "GWDCC23_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x460++0x03
line.long 0x00 "GWDCC24_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x464++0x03
line.long 0x00 "GWDCC25_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x468++0x03
line.long 0x00 "GWDCC26_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x46C++0x03
line.long 0x00 "GWDCC27_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x470++0x03
line.long 0x00 "GWDCC28_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x474++0x03
line.long 0x00 "GWDCC29_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x478++0x03
line.long 0x00 "GWDCC30_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x47C++0x03
line.long 0x00 "GWDCC31_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x480++0x03
line.long 0x00 "GWDCC32_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x484++0x03
line.long 0x00 "GWDCC33_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x488++0x03
line.long 0x00 "GWDCC34_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x48C++0x03
line.long 0x00 "GWDCC35_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x490++0x03
line.long 0x00 "GWDCC36_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x494++0x03
line.long 0x00 "GWDCC37_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x498++0x03
line.long 0x00 "GWDCC38_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x49C++0x03
line.long 0x00 "GWDCC39_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x4A0++0x03
line.long 0x00 "GWDCC40_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x4A4++0x03
line.long 0x00 "GWDCC41_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x4A8++0x03
line.long 0x00 "GWDCC42_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x4AC++0x03
line.long 0x00 "GWDCC43_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x4B0++0x03
line.long 0x00 "GWDCC44_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x4B4++0x03
line.long 0x00 "GWDCC45_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x4B8++0x03
line.long 0x00 "GWDCC46_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x4BC++0x03
line.long 0x00 "GWDCC47_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x4C0++0x03
line.long 0x00 "GWDCC48_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x4C4++0x03
line.long 0x00 "GWDCC49_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x4C8++0x03
line.long 0x00 "GWDCC50_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x4CC++0x03
line.long 0x00 "GWDCC51_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x4D0++0x03
line.long 0x00 "GWDCC52_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x4D4++0x03
line.long 0x00 "GWDCC53_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x4D8++0x03
line.long 0x00 "GWDCC54_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x4DC++0x03
line.long 0x00 "GWDCC55_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x4E0++0x03
line.long 0x00 "GWDCC56_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x4E4++0x03
line.long 0x00 "GWDCC57_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x4E8++0x03
line.long 0x00 "GWDCC58_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x4EC++0x03
line.long 0x00 "GWDCC59_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x4F0++0x03
line.long 0x00 "GWDCC60_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x4F4++0x03
line.long 0x00 "GWDCC61_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x4F8++0x03
line.long 0x00 "GWDCC62_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x4FC++0x03
line.long 0x00 "GWDCC63_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x500++0x03
line.long 0x00 "GWDCC64_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x504++0x03
line.long 0x00 "GWDCC65_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x508++0x03
line.long 0x00 "GWDCC66_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x50C++0x03
line.long 0x00 "GWDCC67_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x510++0x03
line.long 0x00 "GWDCC68_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x514++0x03
line.long 0x00 "GWDCC69_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x518++0x03
line.long 0x00 "GWDCC70_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x51C++0x03
line.long 0x00 "GWDCC71_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x520++0x03
line.long 0x00 "GWDCC72_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x524++0x03
line.long 0x00 "GWDCC73_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x528++0x03
line.long 0x00 "GWDCC74_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x52C++0x03
line.long 0x00 "GWDCC75_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x530++0x03
line.long 0x00 "GWDCC76_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x534++0x03
line.long 0x00 "GWDCC77_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x538++0x03
line.long 0x00 "GWDCC78_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x53C++0x03
line.long 0x00 "GWDCC79_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x540++0x03
line.long 0x00 "GWDCC80_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x544++0x03
line.long 0x00 "GWDCC81_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x548++0x03
line.long 0x00 "GWDCC82_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x54C++0x03
line.long 0x00 "GWDCC83_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x550++0x03
line.long 0x00 "GWDCC84_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x554++0x03
line.long 0x00 "GWDCC85_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x558++0x03
line.long 0x00 "GWDCC86_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x55C++0x03
line.long 0x00 "GWDCC87_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x560++0x03
line.long 0x00 "GWDCC88_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x564++0x03
line.long 0x00 "GWDCC89_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x568++0x03
line.long 0x00 "GWDCC90_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x56C++0x03
line.long 0x00 "GWDCC91_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x570++0x03
line.long 0x00 "GWDCC92_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x574++0x03
line.long 0x00 "GWDCC93_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x578++0x03
line.long 0x00 "GWDCC94_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x57C++0x03
line.long 0x00 "GWDCC95_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x580++0x03
line.long 0x00 "GWDCC96_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x584++0x03
line.long 0x00 "GWDCC97_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x588++0x03
line.long 0x00 "GWDCC98_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x58C++0x03
line.long 0x00 "GWDCC99_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x590++0x03
line.long 0x00 "GWDCC100_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x594++0x03
line.long 0x00 "GWDCC101_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x598++0x03
line.long 0x00 "GWDCC102_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x59C++0x03
line.long 0x00 "GWDCC103_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x5A0++0x03
line.long 0x00 "GWDCC104_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x5A4++0x03
line.long 0x00 "GWDCC105_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x5A8++0x03
line.long 0x00 "GWDCC106_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x5AC++0x03
line.long 0x00 "GWDCC107_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x5B0++0x03
line.long 0x00 "GWDCC108_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x5B4++0x03
line.long 0x00 "GWDCC109_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x5B8++0x03
line.long 0x00 "GWDCC110_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x5BC++0x03
line.long 0x00 "GWDCC111_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x5C0++0x03
line.long 0x00 "GWDCC112_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x5C4++0x03
line.long 0x00 "GWDCC113_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x5C8++0x03
line.long 0x00 "GWDCC114_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x5CC++0x03
line.long 0x00 "GWDCC115_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x5D0++0x03
line.long 0x00 "GWDCC116_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x5D4++0x03
line.long 0x00 "GWDCC117_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x5D8++0x03
line.long 0x00 "GWDCC118_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x5DC++0x03
line.long 0x00 "GWDCC119_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x5E0++0x03
line.long 0x00 "GWDCC120_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x5E4++0x03
line.long 0x00 "GWDCC121_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x5E8++0x03
line.long 0x00 "GWDCC122_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x5EC++0x03
line.long 0x00 "GWDCC123_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x5F0++0x03
line.long 0x00 "GWDCC124_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x5F4++0x03
line.long 0x00 "GWDCC125_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x5F8++0x03
line.long 0x00 "GWDCC126_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x5FC++0x03
line.long 0x00 "GWDCC127_3,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x800++0x03
line.long 0x00 "GWAARSS3,"
hexmask.long 0x00 7.--31. 1. "RSV,Reserved area"
hexmask.long.byte 0x00 0.--6. 1. "AARA,AXI Address RAM Address"
group.long 0x804++0x03
line.long 0x00 "GWAARSR03,"
rbitfld.long 0x00 31. "AARS,AXI Address RAM Searching Functions: This register is used to read an in AXI address RAM Set conditions: SW: Writing GWAARSS will set this bit" "0,1"
hexmask.long.word 0x00 18.--30. 1. "RSV0,Reserved area"
rbitfld.long 0x00 17. "AARSSF,AXI Address RAM Search Security fail Functions: Shows when a security error happened while reading an entry" "0,1"
rbitfld.long 0x00 16. "AARSEF,AXI Address RAM Search ECC fail Functions: Shows when an ECC error happened while reading an entry" "0,1"
hexmask.long.byte 0x00 8.--15. 1. "RSV1,Reserved area"
hexmask.long.byte 0x00 0.--7. 1. "ACARUP,AXI Current Address Result Upper Part Functions: Displays AXI address read value"
group.long 0x808++0x03
line.long 0x00 "GWAARSR13,"
hexmask.long 0x00 0.--31. 1. "ACARDP,AXI Current Address Result Downer Part Functions: Displays AXI address read value"
group.long 0x840++0x03
line.long 0x00 "GWIDAUAS0_3,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "IDAUASi,Incremental Data Area Used Size of RX Descriptor Chain i"
group.long 0x844++0x03
line.long 0x00 "GWIDAUAS1_3,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "IDAUASi,Incremental Data Area Used Size of RX Descriptor Chain i"
group.long 0x848++0x03
line.long 0x00 "GWIDAUAS2_3,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "IDAUASi,Incremental Data Area Used Size of RX Descriptor Chain i"
group.long 0x84C++0x03
line.long 0x00 "GWIDAUAS3_3,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "IDAUASi,Incremental Data Area Used Size of RX Descriptor Chain i"
group.long 0x850++0x03
line.long 0x00 "GWIDAUAS4_3,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "IDAUASi,Incremental Data Area Used Size of RX Descriptor Chain i"
group.long 0x854++0x03
line.long 0x00 "GWIDAUAS5_3,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "IDAUASi,Incremental Data Area Used Size of RX Descriptor Chain i"
group.long 0x858++0x03
line.long 0x00 "GWIDAUAS6_3,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "IDAUASi,Incremental Data Area Used Size of RX Descriptor Chain i"
group.long 0x85C++0x03
line.long 0x00 "GWIDAUAS7_3,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "IDAUASi,Incremental Data Area Used Size of RX Descriptor Chain i"
group.long 0x880++0x03
line.long 0x00 "GWIDASM0_3,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "IDASi,Incremental Data Area Size of RX Descriptor Chain i"
group.long 0x884++0x03
line.long 0x00 "GWIDASM1_3,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "IDASi,Incremental Data Area Size of RX Descriptor Chain i"
group.long 0x888++0x03
line.long 0x00 "GWIDASM2_3,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "IDASi,Incremental Data Area Size of RX Descriptor Chain i"
group.long 0x88C++0x03
line.long 0x00 "GWIDASM3_3,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "IDASi,Incremental Data Area Size of RX Descriptor Chain i"
group.long 0x890++0x03
line.long 0x00 "GWIDASM4_3,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "IDASi,Incremental Data Area Size of RX Descriptor Chain i"
group.long 0x894++0x03
line.long 0x00 "GWIDASM5_3,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "IDASi,Incremental Data Area Size of RX Descriptor Chain i"
group.long 0x898++0x03
line.long 0x00 "GWIDASM6_3,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "IDASi,Incremental Data Area Size of RX Descriptor Chain i"
group.long 0x89C++0x03
line.long 0x00 "GWIDASM7_3,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "IDASi,Incremental Data Area Size of RX Descriptor Chain i"
group.long 0x900++0x03
line.long 0x00 "GWIDASAM00_3,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
hexmask.long.byte 0x00 0.--7. 1. "IDASAUPi,Incremental Data Area Start Address Upper Part of RX Descriptor Chain i"
group.long 0x904++0x03
line.long 0x00 "GWIDASAM10_3,"
hexmask.long 0x00 0.--31. 1. "IDASADPi,Incremental Data Area Start Address Downer Part of RX Descriptor Chain i"
group.long 0x908++0x03
line.long 0x00 "GWIDASAM01_3,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
hexmask.long.byte 0x00 0.--7. 1. "IDASAUPi,Incremental Data Area Start Address Upper Part of RX Descriptor Chain i"
group.long 0x90C++0x03
line.long 0x00 "GWIDASAM11_3,"
hexmask.long 0x00 0.--31. 1. "IDASADPi,Incremental Data Area Start Address Downer Part of RX Descriptor Chain i"
group.long 0x910++0x03
line.long 0x00 "GWIDASAM02_3,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
hexmask.long.byte 0x00 0.--7. 1. "IDASAUPi,Incremental Data Area Start Address Upper Part of RX Descriptor Chain i"
group.long 0x914++0x03
line.long 0x00 "GWIDASAM12_3,"
hexmask.long 0x00 0.--31. 1. "IDASADPi,Incremental Data Area Start Address Downer Part of RX Descriptor Chain i"
group.long 0x918++0x03
line.long 0x00 "GWIDASAM03_3,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
hexmask.long.byte 0x00 0.--7. 1. "IDASAUPi,Incremental Data Area Start Address Upper Part of RX Descriptor Chain i"
group.long 0x91C++0x03
line.long 0x00 "GWIDASAM13_3,"
hexmask.long 0x00 0.--31. 1. "IDASADPi,Incremental Data Area Start Address Downer Part of RX Descriptor Chain i"
group.long 0x920++0x03
line.long 0x00 "GWIDASAM04_3,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
hexmask.long.byte 0x00 0.--7. 1. "IDASAUPi,Incremental Data Area Start Address Upper Part of RX Descriptor Chain i"
group.long 0x924++0x03
line.long 0x00 "GWIDASAM14_3,"
hexmask.long 0x00 0.--31. 1. "IDASADPi,Incremental Data Area Start Address Downer Part of RX Descriptor Chain i"
group.long 0x928++0x03
line.long 0x00 "GWIDASAM05_3,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
hexmask.long.byte 0x00 0.--7. 1. "IDASAUPi,Incremental Data Area Start Address Upper Part of RX Descriptor Chain i"
group.long 0x92C++0x03
line.long 0x00 "GWIDASAM15_3,"
hexmask.long 0x00 0.--31. 1. "IDASADPi,Incremental Data Area Start Address Downer Part of RX Descriptor Chain i"
group.long 0x930++0x03
line.long 0x00 "GWIDASAM06_3,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
hexmask.long.byte 0x00 0.--7. 1. "IDASAUPi,Incremental Data Area Start Address Upper Part of RX Descriptor Chain i"
group.long 0x934++0x03
line.long 0x00 "GWIDASAM16_3,"
hexmask.long 0x00 0.--31. 1. "IDASADPi,Incremental Data Area Start Address Downer Part of RX Descriptor Chain i"
group.long 0x938++0x03
line.long 0x00 "GWIDASAM07_3,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
hexmask.long.byte 0x00 0.--7. 1. "IDASAUPi,Incremental Data Area Start Address Upper Part of RX Descriptor Chain i"
group.long 0x93C++0x03
line.long 0x00 "GWIDASAM17_3,"
hexmask.long 0x00 0.--31. 1. "IDASADPi,Incremental Data Area Start Address Downer Part of RX Descriptor Chain i"
group.long 0x980++0x03
line.long 0x00 "GWIDACAM00_3,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
hexmask.long.byte 0x00 0.--7. 1. "IDACAUPi,Incremental Data Area Current Address Upper Part of RX Descriptor Chain i"
group.long 0x984++0x03
line.long 0x00 "GWIDACAM10_3,"
hexmask.long 0x00 0.--31. 1. "IDACADPi,Incremental Data Area Current Address Downer Part of RX Descriptor Chain i"
group.long 0x988++0x03
line.long 0x00 "GWIDACAM01_3,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
hexmask.long.byte 0x00 0.--7. 1. "IDACAUPi,Incremental Data Area Current Address Upper Part of RX Descriptor Chain i"
group.long 0x98C++0x03
line.long 0x00 "GWIDACAM11_3,"
hexmask.long 0x00 0.--31. 1. "IDACADPi,Incremental Data Area Current Address Downer Part of RX Descriptor Chain i"
group.long 0x990++0x03
line.long 0x00 "GWIDACAM02_3,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
hexmask.long.byte 0x00 0.--7. 1. "IDACAUPi,Incremental Data Area Current Address Upper Part of RX Descriptor Chain i"
group.long 0x994++0x03
line.long 0x00 "GWIDACAM12_3,"
hexmask.long 0x00 0.--31. 1. "IDACADPi,Incremental Data Area Current Address Downer Part of RX Descriptor Chain i"
group.long 0x998++0x03
line.long 0x00 "GWIDACAM03_3,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
hexmask.long.byte 0x00 0.--7. 1. "IDACAUPi,Incremental Data Area Current Address Upper Part of RX Descriptor Chain i"
group.long 0x99C++0x03
line.long 0x00 "GWIDACAM13_3,"
hexmask.long 0x00 0.--31. 1. "IDACADPi,Incremental Data Area Current Address Downer Part of RX Descriptor Chain i"
group.long 0x9A0++0x03
line.long 0x00 "GWIDACAM04_3,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
hexmask.long.byte 0x00 0.--7. 1. "IDACAUPi,Incremental Data Area Current Address Upper Part of RX Descriptor Chain i"
group.long 0x9A4++0x03
line.long 0x00 "GWIDACAM14_3,"
hexmask.long 0x00 0.--31. 1. "IDACADPi,Incremental Data Area Current Address Downer Part of RX Descriptor Chain i"
group.long 0x9A8++0x03
line.long 0x00 "GWIDACAM05_3,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
hexmask.long.byte 0x00 0.--7. 1. "IDACAUPi,Incremental Data Area Current Address Upper Part of RX Descriptor Chain i"
group.long 0x9AC++0x03
line.long 0x00 "GWIDACAM15_3,"
hexmask.long 0x00 0.--31. 1. "IDACADPi,Incremental Data Area Current Address Downer Part of RX Descriptor Chain i"
group.long 0x9B0++0x03
line.long 0x00 "GWIDACAM06_3,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
hexmask.long.byte 0x00 0.--7. 1. "IDACAUPi,Incremental Data Area Current Address Upper Part of RX Descriptor Chain i"
group.long 0x9B4++0x03
line.long 0x00 "GWIDACAM16_3,"
hexmask.long 0x00 0.--31. 1. "IDACADPi,Incremental Data Area Current Address Downer Part of RX Descriptor Chain i"
group.long 0x9B8++0x03
line.long 0x00 "GWIDACAM07_3,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
hexmask.long.byte 0x00 0.--7. 1. "IDACAUPi,Incremental Data Area Current Address Upper Part of RX Descriptor Chain i"
group.long 0x9BC++0x03
line.long 0x00 "GWIDACAM17_3,"
hexmask.long 0x00 0.--31. 1. "IDACADPi,Incremental Data Area Current Address Downer Part of RX Descriptor Chain i"
group.long 0xA00++0x03
line.long 0x00 "GWGRLC3,"
hexmask.long.word 0x00 18.--31. 1. "RSV,Reserved area"
bitfld.long 0x00 17. "GRLULRS,Global Rate Limiter Upper Limit Reached Status Set conditions: HW: When the global rate limit reaches its upper limit GWGRLULC.GRLUL this bit gets set Clear conditions: HW: Being in RESET mode will clear this register" "0,1"
bitfld.long 0x00 16. "GRLE,Global Rate Limiter Enable" "0,1"
hexmask.long.word 0x00 0.--15. 1. "GRLIV,Global Rate Limiter Incremental Value"
group.long 0xA04++0x03
line.long 0x00 "GWGRLULC3,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "GRLUL,Global Rate Limiter Upper Limit Functions: Set the maximum number of credits in bit rate limiter i can accumulate before stopping"
group.long 0xA80++0x03
line.long 0x00 "GWRLC0_3,"
hexmask.long.word 0x00 17.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 16. "RLEi,Rate limiter enable i" "0,1"
rbitfld.long 0x00 12.--15. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "RLIVi,Rate limiter incremental value for rate limiter i"
group.long 0xA84++0x03
line.long 0x00 "GWRLULC0_3,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "RLULi,Rate limiter upper limit for rate limiter i"
group.long 0xA88++0x03
line.long 0x00 "GWRLC1_3,"
hexmask.long.word 0x00 17.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 16. "RLEi,Rate limiter enable i" "0,1"
rbitfld.long 0x00 12.--15. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "RLIVi,Rate limiter incremental value for rate limiter i"
group.long 0xA8C++0x03
line.long 0x00 "GWRLULC1_3,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "RLULi,Rate limiter upper limit for rate limiter i"
group.long 0xA90++0x03
line.long 0x00 "GWRLC2_3,"
hexmask.long.word 0x00 17.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 16. "RLEi,Rate limiter enable i" "0,1"
rbitfld.long 0x00 12.--15. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "RLIVi,Rate limiter incremental value for rate limiter i"
group.long 0xA94++0x03
line.long 0x00 "GWRLULC2_3,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "RLULi,Rate limiter upper limit for rate limiter i"
group.long 0xA98++0x03
line.long 0x00 "GWRLC3_3,"
hexmask.long.word 0x00 17.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 16. "RLEi,Rate limiter enable i" "0,1"
rbitfld.long 0x00 12.--15. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "RLIVi,Rate limiter incremental value for rate limiter i"
group.long 0xA9C++0x03
line.long 0x00 "GWRLULC3_3,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "RLULi,Rate limiter upper limit for rate limiter i"
group.long 0xAA0++0x03
line.long 0x00 "GWRLC4_3,"
hexmask.long.word 0x00 17.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 16. "RLEi,Rate limiter enable i" "0,1"
rbitfld.long 0x00 12.--15. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "RLIVi,Rate limiter incremental value for rate limiter i"
group.long 0xAA4++0x03
line.long 0x00 "GWRLULC4_3,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "RLULi,Rate limiter upper limit for rate limiter i"
group.long 0xAA8++0x03
line.long 0x00 "GWRLC5_3,"
hexmask.long.word 0x00 17.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 16. "RLEi,Rate limiter enable i" "0,1"
rbitfld.long 0x00 12.--15. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "RLIVi,Rate limiter incremental value for rate limiter i"
group.long 0xAAC++0x03
line.long 0x00 "GWRLULC5_3,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "RLULi,Rate limiter upper limit for rate limiter i"
group.long 0xAB0++0x03
line.long 0x00 "GWRLC6_3,"
hexmask.long.word 0x00 17.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 16. "RLEi,Rate limiter enable i" "0,1"
rbitfld.long 0x00 12.--15. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "RLIVi,Rate limiter incremental value for rate limiter i"
group.long 0xAB4++0x03
line.long 0x00 "GWRLULC6_3,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "RLULi,Rate limiter upper limit for rate limiter i"
group.long 0xAB8++0x03
line.long 0x00 "GWRLC7_3,"
hexmask.long.word 0x00 17.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 16. "RLEi,Rate limiter enable i" "0,1"
rbitfld.long 0x00 12.--15. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "RLIVi,Rate limiter incremental value for rate limiter i"
group.long 0xABC++0x03
line.long 0x00 "GWRLULC7_3,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "RLULi,Rate limiter upper limit for rate limiter i"
group.long 0xAC0++0x03
line.long 0x00 "GWRLC8_3,"
hexmask.long.word 0x00 17.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 16. "RLEi,Rate limiter enable i" "0,1"
rbitfld.long 0x00 12.--15. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "RLIVi,Rate limiter incremental value for rate limiter i"
group.long 0xAC4++0x03
line.long 0x00 "GWRLULC8_3,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "RLULi,Rate limiter upper limit for rate limiter i"
group.long 0xAC8++0x03
line.long 0x00 "GWRLC9_3,"
hexmask.long.word 0x00 17.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 16. "RLEi,Rate limiter enable i" "0,1"
rbitfld.long 0x00 12.--15. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "RLIVi,Rate limiter incremental value for rate limiter i"
group.long 0xACC++0x03
line.long 0x00 "GWRLULC9_3,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "RLULi,Rate limiter upper limit for rate limiter i"
group.long 0xAD0++0x03
line.long 0x00 "GWRLC10_3,"
hexmask.long.word 0x00 17.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 16. "RLEi,Rate limiter enable i" "0,1"
rbitfld.long 0x00 12.--15. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "RLIVi,Rate limiter incremental value for rate limiter i"
group.long 0xAD4++0x03
line.long 0x00 "GWRLULC10_3,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "RLULi,Rate limiter upper limit for rate limiter i"
group.long 0xAD8++0x03
line.long 0x00 "GWRLC11_3,"
hexmask.long.word 0x00 17.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 16. "RLEi,Rate limiter enable i" "0,1"
rbitfld.long 0x00 12.--15. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "RLIVi,Rate limiter incremental value for rate limiter i"
group.long 0xADC++0x03
line.long 0x00 "GWRLULC11_3,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "RLULi,Rate limiter upper limit for rate limiter i"
group.long 0xAE0++0x03
line.long 0x00 "GWRLC12_3,"
hexmask.long.word 0x00 17.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 16. "RLEi,Rate limiter enable i" "0,1"
rbitfld.long 0x00 12.--15. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "RLIVi,Rate limiter incremental value for rate limiter i"
group.long 0xAE4++0x03
line.long 0x00 "GWRLULC12_3,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "RLULi,Rate limiter upper limit for rate limiter i"
group.long 0xAE8++0x03
line.long 0x00 "GWRLC13_3,"
hexmask.long.word 0x00 17.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 16. "RLEi,Rate limiter enable i" "0,1"
rbitfld.long 0x00 12.--15. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "RLIVi,Rate limiter incremental value for rate limiter i"
group.long 0xAEC++0x03
line.long 0x00 "GWRLULC13_3,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "RLULi,Rate limiter upper limit for rate limiter i"
group.long 0xAF0++0x03
line.long 0x00 "GWRLC14_3,"
hexmask.long.word 0x00 17.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 16. "RLEi,Rate limiter enable i" "0,1"
rbitfld.long 0x00 12.--15. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "RLIVi,Rate limiter incremental value for rate limiter i"
group.long 0xAF4++0x03
line.long 0x00 "GWRLULC14_3,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "RLULi,Rate limiter upper limit for rate limiter i"
group.long 0xAF8++0x03
line.long 0x00 "GWRLC15_3,"
hexmask.long.word 0x00 17.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 16. "RLEi,Rate limiter enable i" "0,1"
rbitfld.long 0x00 12.--15. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "RLIVi,Rate limiter incremental value for rate limiter i"
group.long 0xAFC++0x03
line.long 0x00 "GWRLULC15_3,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "RLULi,Rate limiter upper limit for rate limiter i"
group.long 0xB00++0x03
line.long 0x00 "GWRLC16_3,"
hexmask.long.word 0x00 17.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 16. "RLEi,Rate limiter enable i" "0,1"
rbitfld.long 0x00 12.--15. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "RLIVi,Rate limiter incremental value for rate limiter i"
group.long 0xB04++0x03
line.long 0x00 "GWRLULC16_3,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "RLULi,Rate limiter upper limit for rate limiter i"
group.long 0xB08++0x03
line.long 0x00 "GWRLC17_3,"
hexmask.long.word 0x00 17.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 16. "RLEi,Rate limiter enable i" "0,1"
rbitfld.long 0x00 12.--15. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "RLIVi,Rate limiter incremental value for rate limiter i"
group.long 0xB0C++0x03
line.long 0x00 "GWRLULC17_3,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "RLULi,Rate limiter upper limit for rate limiter i"
group.long 0xB10++0x03
line.long 0x00 "GWRLC18_3,"
hexmask.long.word 0x00 17.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 16. "RLEi,Rate limiter enable i" "0,1"
rbitfld.long 0x00 12.--15. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "RLIVi,Rate limiter incremental value for rate limiter i"
group.long 0xB14++0x03
line.long 0x00 "GWRLULC18_3,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "RLULi,Rate limiter upper limit for rate limiter i"
group.long 0xB18++0x03
line.long 0x00 "GWRLC19_3,"
hexmask.long.word 0x00 17.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 16. "RLEi,Rate limiter enable i" "0,1"
rbitfld.long 0x00 12.--15. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "RLIVi,Rate limiter incremental value for rate limiter i"
group.long 0xB1C++0x03
line.long 0x00 "GWRLULC19_3,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "RLULi,Rate limiter upper limit for rate limiter i"
group.long 0xB20++0x03
line.long 0x00 "GWRLC20_3,"
hexmask.long.word 0x00 17.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 16. "RLEi,Rate limiter enable i" "0,1"
rbitfld.long 0x00 12.--15. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "RLIVi,Rate limiter incremental value for rate limiter i"
group.long 0xB24++0x03
line.long 0x00 "GWRLULC20_3,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "RLULi,Rate limiter upper limit for rate limiter i"
group.long 0xB28++0x03
line.long 0x00 "GWRLC21_3,"
hexmask.long.word 0x00 17.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 16. "RLEi,Rate limiter enable i" "0,1"
rbitfld.long 0x00 12.--15. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "RLIVi,Rate limiter incremental value for rate limiter i"
group.long 0xB2C++0x03
line.long 0x00 "GWRLULC21_3,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "RLULi,Rate limiter upper limit for rate limiter i"
group.long 0xB30++0x03
line.long 0x00 "GWRLC22_3,"
hexmask.long.word 0x00 17.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 16. "RLEi,Rate limiter enable i" "0,1"
rbitfld.long 0x00 12.--15. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "RLIVi,Rate limiter incremental value for rate limiter i"
group.long 0xB34++0x03
line.long 0x00 "GWRLULC22_3,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "RLULi,Rate limiter upper limit for rate limiter i"
group.long 0xB38++0x03
line.long 0x00 "GWRLC23_3,"
hexmask.long.word 0x00 17.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 16. "RLEi,Rate limiter enable i" "0,1"
rbitfld.long 0x00 12.--15. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "RLIVi,Rate limiter incremental value for rate limiter i"
group.long 0xB3C++0x03
line.long 0x00 "GWRLULC23_3,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "RLULi,Rate limiter upper limit for rate limiter i"
group.long 0xB40++0x03
line.long 0x00 "GWRLC24_3,"
hexmask.long.word 0x00 17.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 16. "RLEi,Rate limiter enable i" "0,1"
rbitfld.long 0x00 12.--15. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "RLIVi,Rate limiter incremental value for rate limiter i"
group.long 0xB44++0x03
line.long 0x00 "GWRLULC24_3,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "RLULi,Rate limiter upper limit for rate limiter i"
group.long 0xB48++0x03
line.long 0x00 "GWRLC25_3,"
hexmask.long.word 0x00 17.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 16. "RLEi,Rate limiter enable i" "0,1"
rbitfld.long 0x00 12.--15. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "RLIVi,Rate limiter incremental value for rate limiter i"
group.long 0xB4C++0x03
line.long 0x00 "GWRLULC25_3,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "RLULi,Rate limiter upper limit for rate limiter i"
group.long 0xB50++0x03
line.long 0x00 "GWRLC26_3,"
hexmask.long.word 0x00 17.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 16. "RLEi,Rate limiter enable i" "0,1"
rbitfld.long 0x00 12.--15. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "RLIVi,Rate limiter incremental value for rate limiter i"
group.long 0xB54++0x03
line.long 0x00 "GWRLULC26_3,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "RLULi,Rate limiter upper limit for rate limiter i"
group.long 0xB58++0x03
line.long 0x00 "GWRLC27_3,"
hexmask.long.word 0x00 17.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 16. "RLEi,Rate limiter enable i" "0,1"
rbitfld.long 0x00 12.--15. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "RLIVi,Rate limiter incremental value for rate limiter i"
group.long 0xB5C++0x03
line.long 0x00 "GWRLULC27_3,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "RLULi,Rate limiter upper limit for rate limiter i"
group.long 0xB60++0x03
line.long 0x00 "GWRLC28_3,"
hexmask.long.word 0x00 17.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 16. "RLEi,Rate limiter enable i" "0,1"
rbitfld.long 0x00 12.--15. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "RLIVi,Rate limiter incremental value for rate limiter i"
group.long 0xB64++0x03
line.long 0x00 "GWRLULC28_3,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "RLULi,Rate limiter upper limit for rate limiter i"
group.long 0xB68++0x03
line.long 0x00 "GWRLC29_3,"
hexmask.long.word 0x00 17.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 16. "RLEi,Rate limiter enable i" "0,1"
rbitfld.long 0x00 12.--15. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "RLIVi,Rate limiter incremental value for rate limiter i"
group.long 0xB6C++0x03
line.long 0x00 "GWRLULC29_3,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "RLULi,Rate limiter upper limit for rate limiter i"
group.long 0xB70++0x03
line.long 0x00 "GWRLC30_3,"
hexmask.long.word 0x00 17.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 16. "RLEi,Rate limiter enable i" "0,1"
rbitfld.long 0x00 12.--15. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "RLIVi,Rate limiter incremental value for rate limiter i"
group.long 0xB74++0x03
line.long 0x00 "GWRLULC30_3,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "RLULi,Rate limiter upper limit for rate limiter i"
group.long 0xB78++0x03
line.long 0x00 "GWRLC31_3,"
hexmask.long.word 0x00 17.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 16. "RLEi,Rate limiter enable i" "0,1"
rbitfld.long 0x00 12.--15. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "RLIVi,Rate limiter incremental value for rate limiter i"
group.long 0xB7C++0x03
line.long 0x00 "GWRLULC31_3,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "RLULi,Rate limiter upper limit for rate limiter i"
group.long 0xB80++0x03
line.long 0x00 "GWIDPC3,"
hexmask.long.tbyte 0x00 10.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--9. 1. "IDPV,Interrupt delay prescaler value Functions: This register is used to create an internal clock"
group.long 0xC00++0x03
line.long 0x00 "GWIDC0_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xC04++0x03
line.long 0x00 "GWIDC1_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xC08++0x03
line.long 0x00 "GWIDC2_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xC0C++0x03
line.long 0x00 "GWIDC3_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xC10++0x03
line.long 0x00 "GWIDC4_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xC14++0x03
line.long 0x00 "GWIDC5_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xC18++0x03
line.long 0x00 "GWIDC6_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xC1C++0x03
line.long 0x00 "GWIDC7_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xC20++0x03
line.long 0x00 "GWIDC8_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xC24++0x03
line.long 0x00 "GWIDC9_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xC28++0x03
line.long 0x00 "GWIDC10_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xC2C++0x03
line.long 0x00 "GWIDC11_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xC30++0x03
line.long 0x00 "GWIDC12_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xC34++0x03
line.long 0x00 "GWIDC13_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xC38++0x03
line.long 0x00 "GWIDC14_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xC3C++0x03
line.long 0x00 "GWIDC15_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xC40++0x03
line.long 0x00 "GWIDC16_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xC44++0x03
line.long 0x00 "GWIDC17_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xC48++0x03
line.long 0x00 "GWIDC18_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xC4C++0x03
line.long 0x00 "GWIDC19_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xC50++0x03
line.long 0x00 "GWIDC20_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xC54++0x03
line.long 0x00 "GWIDC21_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xC58++0x03
line.long 0x00 "GWIDC22_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xC5C++0x03
line.long 0x00 "GWIDC23_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xC60++0x03
line.long 0x00 "GWIDC24_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xC64++0x03
line.long 0x00 "GWIDC25_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xC68++0x03
line.long 0x00 "GWIDC26_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xC6C++0x03
line.long 0x00 "GWIDC27_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xC70++0x03
line.long 0x00 "GWIDC28_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xC74++0x03
line.long 0x00 "GWIDC29_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xC78++0x03
line.long 0x00 "GWIDC30_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xC7C++0x03
line.long 0x00 "GWIDC31_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xC80++0x03
line.long 0x00 "GWIDC32_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xC84++0x03
line.long 0x00 "GWIDC33_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xC88++0x03
line.long 0x00 "GWIDC34_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xC8C++0x03
line.long 0x00 "GWIDC35_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xC90++0x03
line.long 0x00 "GWIDC36_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xC94++0x03
line.long 0x00 "GWIDC37_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xC98++0x03
line.long 0x00 "GWIDC38_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xC9C++0x03
line.long 0x00 "GWIDC39_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xCA0++0x03
line.long 0x00 "GWIDC40_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xCA4++0x03
line.long 0x00 "GWIDC41_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xCA8++0x03
line.long 0x00 "GWIDC42_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xCAC++0x03
line.long 0x00 "GWIDC43_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xCB0++0x03
line.long 0x00 "GWIDC44_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xCB4++0x03
line.long 0x00 "GWIDC45_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xCB8++0x03
line.long 0x00 "GWIDC46_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xCBC++0x03
line.long 0x00 "GWIDC47_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xCC0++0x03
line.long 0x00 "GWIDC48_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xCC4++0x03
line.long 0x00 "GWIDC49_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xCC8++0x03
line.long 0x00 "GWIDC50_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xCCC++0x03
line.long 0x00 "GWIDC51_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xCD0++0x03
line.long 0x00 "GWIDC52_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xCD4++0x03
line.long 0x00 "GWIDC53_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xCD8++0x03
line.long 0x00 "GWIDC54_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xCDC++0x03
line.long 0x00 "GWIDC55_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xCE0++0x03
line.long 0x00 "GWIDC56_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xCE4++0x03
line.long 0x00 "GWIDC57_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xCE8++0x03
line.long 0x00 "GWIDC58_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xCEC++0x03
line.long 0x00 "GWIDC59_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xCF0++0x03
line.long 0x00 "GWIDC60_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xCF4++0x03
line.long 0x00 "GWIDC61_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xCF8++0x03
line.long 0x00 "GWIDC62_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xCFC++0x03
line.long 0x00 "GWIDC63_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xD00++0x03
line.long 0x00 "GWIDC64_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xD04++0x03
line.long 0x00 "GWIDC65_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xD08++0x03
line.long 0x00 "GWIDC66_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xD0C++0x03
line.long 0x00 "GWIDC67_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xD10++0x03
line.long 0x00 "GWIDC68_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xD14++0x03
line.long 0x00 "GWIDC69_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xD18++0x03
line.long 0x00 "GWIDC70_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xD1C++0x03
line.long 0x00 "GWIDC71_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xD20++0x03
line.long 0x00 "GWIDC72_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xD24++0x03
line.long 0x00 "GWIDC73_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xD28++0x03
line.long 0x00 "GWIDC74_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xD2C++0x03
line.long 0x00 "GWIDC75_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xD30++0x03
line.long 0x00 "GWIDC76_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xD34++0x03
line.long 0x00 "GWIDC77_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xD38++0x03
line.long 0x00 "GWIDC78_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xD3C++0x03
line.long 0x00 "GWIDC79_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xD40++0x03
line.long 0x00 "GWIDC80_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xD44++0x03
line.long 0x00 "GWIDC81_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xD48++0x03
line.long 0x00 "GWIDC82_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xD4C++0x03
line.long 0x00 "GWIDC83_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xD50++0x03
line.long 0x00 "GWIDC84_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xD54++0x03
line.long 0x00 "GWIDC85_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xD58++0x03
line.long 0x00 "GWIDC86_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xD5C++0x03
line.long 0x00 "GWIDC87_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xD60++0x03
line.long 0x00 "GWIDC88_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xD64++0x03
line.long 0x00 "GWIDC89_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xD68++0x03
line.long 0x00 "GWIDC90_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xD6C++0x03
line.long 0x00 "GWIDC91_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xD70++0x03
line.long 0x00 "GWIDC92_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xD74++0x03
line.long 0x00 "GWIDC93_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xD78++0x03
line.long 0x00 "GWIDC94_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xD7C++0x03
line.long 0x00 "GWIDC95_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xD80++0x03
line.long 0x00 "GWIDC96_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xD84++0x03
line.long 0x00 "GWIDC97_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xD88++0x03
line.long 0x00 "GWIDC98_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xD8C++0x03
line.long 0x00 "GWIDC99_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xD90++0x03
line.long 0x00 "GWIDC100_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xD94++0x03
line.long 0x00 "GWIDC101_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xD98++0x03
line.long 0x00 "GWIDC102_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xD9C++0x03
line.long 0x00 "GWIDC103_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xDA0++0x03
line.long 0x00 "GWIDC104_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xDA4++0x03
line.long 0x00 "GWIDC105_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xDA8++0x03
line.long 0x00 "GWIDC106_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xDAC++0x03
line.long 0x00 "GWIDC107_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xDB0++0x03
line.long 0x00 "GWIDC108_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xDB4++0x03
line.long 0x00 "GWIDC109_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xDB8++0x03
line.long 0x00 "GWIDC110_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xDBC++0x03
line.long 0x00 "GWIDC111_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xDC0++0x03
line.long 0x00 "GWIDC112_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xDC4++0x03
line.long 0x00 "GWIDC113_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xDC8++0x03
line.long 0x00 "GWIDC114_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xDCC++0x03
line.long 0x00 "GWIDC115_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xDD0++0x03
line.long 0x00 "GWIDC116_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xDD4++0x03
line.long 0x00 "GWIDC117_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xDD8++0x03
line.long 0x00 "GWIDC118_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xDDC++0x03
line.long 0x00 "GWIDC119_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xDE0++0x03
line.long 0x00 "GWIDC120_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xDE4++0x03
line.long 0x00 "GWIDC121_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xDE8++0x03
line.long 0x00 "GWIDC122_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xDEC++0x03
line.long 0x00 "GWIDC123_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xDF0++0x03
line.long 0x00 "GWIDC124_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xDF4++0x03
line.long 0x00 "GWIDC125_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xDF8++0x03
line.long 0x00 "GWIDC126_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xDFC++0x03
line.long 0x00 "GWIDC127_3,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0x1000++0x03
line.long 0x00 "GWRDCN3,"
hexmask.long 0x00 0.--31. 1. "RDN,Received Data Number Functions: This register counts data that has been received by GWCA (data aborted by AXI error are accounted here)"
group.long 0x1004++0x03
line.long 0x00 "GWTDCN3,"
hexmask.long 0x00 0.--31. 1. "TDN,Transmitted Data Number Functions: This register counts data that has been transmit by GWCA (this includes data transmitted with an error and frames smaller than 32 bytes)"
group.long 0x1008++0x03
line.long 0x00 "GWTSCN3,"
hexmask.long 0x00 0.--31. 1. "TN,Timestamp Number Functions: This register counts timestamp processed by GWCA (TS lost because of AXI errors are accounted here) Clear conditions: HW: Being in RESET mode will clear this register"
group.long 0x100C++0x03
line.long 0x00 "GWTSOVFECN3,"
hexmask.long.word 0x00 16.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--15. 1. "TSOVFEN,TimeStamp OVerFlow Error Number Functions: This register counts the number of timestamps lost because of timestamp RAM overflow"
group.long 0x1010++0x03
line.long 0x00 "GWUSMFSECN3,"
hexmask.long.word 0x00 16.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--15. 1. "USMFSEN,Under Switch Minimum Frame Size Error Number Functions: This register counts the number of transmit data lost because of under switch minimum size error"
group.long 0x1014++0x03
line.long 0x00 "GWTFECN3,"
hexmask.long.word 0x00 16.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--15. 1. "TFEN,TAG Filtering Error Number Functions: This register counts the number of transmit data lost because of TAG filtering"
group.long 0x1018++0x03
line.long 0x00 "GWSEQECN3,"
hexmask.long.word 0x00 16.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--15. 1. "SEQEN,SEQuence Error Number Functions: This register counts the number of transmit data lost because of a sequence error"
group.long 0x1020++0x03
line.long 0x00 "GWTXDNECN3,"
hexmask.long.word 0x00 16.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--15. 1. "TXDNEN,TX Descriptor Number Error Number Functions: This register counts the number of transmit data lost because of a TX Descriptor Number Error"
group.long 0x1024++0x03
line.long 0x00 "GWFSECN3,"
hexmask.long.word 0x00 16.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--15. 1. "FSEN,Frame Size Error Number Functions: This register counts the number of receive data lost because of a Frame Size Error"
group.long 0x1028++0x03
line.long 0x00 "GWTDFECN3,"
hexmask.long.word 0x00 16.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--15. 1. "TDFEN,Timestamp Descriptor Full Error Number Functions: This register counts the number of timestamps lost because of a Timestamp Descriptor Full Error"
group.long 0x102C++0x03
line.long 0x00 "GWTSDNECN3,"
hexmask.long.word 0x00 16.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--15. 1. "TSDNEN,Timestamp Descriptor Number Error Number Functions: This register counts the number of timestamps lost because of a Timestamp Descriptor Number Error"
group.long 0x1030++0x03
line.long 0x00 "GWDQOECN3,"
hexmask.long.word 0x00 16.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--15. 1. "DQOEN,Descriptor Queue Overflow Error Number Functions: This register counts the number of receive data lost because of a Descriptor Queue Overflow Error"
group.long 0x1034++0x03
line.long 0x00 "GWDQSECN3,"
hexmask.long.word 0x00 16.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--15. 1. "DQSEN,Descriptor Queue Security Error Number Functions: This register counts the number of receive data lost because of a Descriptor Queue Security Error"
group.long 0x1038++0x03
line.long 0x00 "GWDFECN3,"
hexmask.long.word 0x00 16.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--15. 1. "DFEN,Descriptor Full Error Number Functions: This register counts the number of receive data lost because of a Descriptor Full Error"
group.long 0x103C++0x03
line.long 0x00 "GWDSECN3,"
hexmask.long.word 0x00 16.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--15. 1. "DSEN,Descriptor Security Error Number Functions: This register counts the number of receive data lost because of a Descriptor Security Error"
group.long 0x1040++0x03
line.long 0x00 "GWDSZECN3,"
hexmask.long.word 0x00 16.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--15. 1. "DSZEN,Data SiZe Error Number Functions: This register counts the number of receive data lost because of a Data Size Error"
group.long 0x1044++0x03
line.long 0x00 "GWDCTECN3,"
hexmask.long.word 0x00 16.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--15. 1. "DCTEN,Descriptor Chain Type Error Number Functions: This register counts the number of receive data lost because of a Descriptor Chain Type Error"
group.long 0x1048++0x03
line.long 0x00 "GWRXDNECN3,"
hexmask.long.word 0x00 16.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--15. 1. "RXDNEN,RX Descriptor Number Error Number Functions: This register counts the number of receive data lost because of a RX Descriptor Number Error"
group.long 0x1100++0x03
line.long 0x00 "GWDIS0_3,"
bitfld.long 0x00 31. "DIS31,Data Interrupt Status t" "0,1"
bitfld.long 0x00 30. "DIS30,Data Interrupt Status t" "0,1"
bitfld.long 0x00 29. "DIS29,Data Interrupt Status t" "0,1"
bitfld.long 0x00 28. "DIS28,Data Interrupt Status t" "0,1"
bitfld.long 0x00 27. "DIS27,Data Interrupt Status t" "0,1"
bitfld.long 0x00 26. "DIS26,Data Interrupt Status t" "0,1"
bitfld.long 0x00 25. "DIS25,Data Interrupt Status t" "0,1"
bitfld.long 0x00 24. "DIS24,Data Interrupt Status t" "0,1"
bitfld.long 0x00 23. "DIS23,Data Interrupt Status t" "0,1"
newline
bitfld.long 0x00 22. "DIS22,Data Interrupt Status t" "0,1"
bitfld.long 0x00 21. "DIS21,Data Interrupt Status t" "0,1"
bitfld.long 0x00 20. "DIS20,Data Interrupt Status t" "0,1"
bitfld.long 0x00 19. "DIS19,Data Interrupt Status t" "0,1"
bitfld.long 0x00 18. "DIS18,Data Interrupt Status t" "0,1"
bitfld.long 0x00 17. "DIS17,Data Interrupt Status t" "0,1"
bitfld.long 0x00 16. "DIS16,Data Interrupt Status t" "0,1"
bitfld.long 0x00 15. "DIS15,Data Interrupt Status t" "0,1"
bitfld.long 0x00 14. "DIS14,Data Interrupt Status t" "0,1"
newline
bitfld.long 0x00 13. "DIS13,Data Interrupt Status t" "0,1"
bitfld.long 0x00 12. "DIS12,Data Interrupt Status t" "0,1"
bitfld.long 0x00 11. "DIS11,Data Interrupt Status t" "0,1"
bitfld.long 0x00 10. "DIS10,Data Interrupt Status t" "0,1"
bitfld.long 0x00 9. "DIS9,Data Interrupt Status t" "0,1"
bitfld.long 0x00 8. "DIS8,Data Interrupt Status t" "0,1"
bitfld.long 0x00 7. "DIS7,Data Interrupt Status t" "0,1"
bitfld.long 0x00 6. "DIS6,Data Interrupt Status t" "0,1"
bitfld.long 0x00 5. "DIS5,Data Interrupt Status t" "0,1"
newline
bitfld.long 0x00 4. "DIS4,Data Interrupt Status t" "0,1"
bitfld.long 0x00 3. "DIS3,Data Interrupt Status t" "0,1"
bitfld.long 0x00 2. "DIS2,Data Interrupt Status t" "0,1"
bitfld.long 0x00 1. "DIS1,Data Interrupt Status t" "0,1"
bitfld.long 0x00 0. "DIS0,Data Interrupt Status t" "0,1"
group.long 0x1104++0x03
line.long 0x00 "GWDIE0_3,"
bitfld.long 0x00 31. "DIE31,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 30. "DIE30,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 29. "DIE29,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 28. "DIE28,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 27. "DIE27,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 26. "DIE26,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 25. "DIE25,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 24. "DIE24,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 23. "DIE23,Data Interrupt Enable t" "0,1"
newline
bitfld.long 0x00 22. "DIE22,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 21. "DIE21,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 20. "DIE20,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 19. "DIE19,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 18. "DIE18,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 17. "DIE17,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 16. "DIE16,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 15. "DIE15,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 14. "DIE14,Data Interrupt Enable t" "0,1"
newline
bitfld.long 0x00 13. "DIE13,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 12. "DIE12,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 11. "DIE11,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 10. "DIE10,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 9. "DIE9,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 8. "DIE8,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 7. "DIE7,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 6. "DIE6,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 5. "DIE5,Data Interrupt Enable t" "0,1"
newline
bitfld.long 0x00 4. "DIE4,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 3. "DIE3,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 2. "DIE2,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 1. "DIE1,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 0. "DIE0,Data Interrupt Enable t" "0,1"
group.long 0x1108++0x03
line.long 0x00 "GWDID0_3,"
bitfld.long 0x00 31. "DID31,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 30. "DID30,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 29. "DID29,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 28. "DID28,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 27. "DID27,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 26. "DID26,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 25. "DID25,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 24. "DID24,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 23. "DID23,Data Interrupt Disable t" "0,1"
newline
bitfld.long 0x00 22. "DID22,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 21. "DID21,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 20. "DID20,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 19. "DID19,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 18. "DID18,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 17. "DID17,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 16. "DID16,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 15. "DID15,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 14. "DID14,Data Interrupt Disable t" "0,1"
newline
bitfld.long 0x00 13. "DID13,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 12. "DID12,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 11. "DID11,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 10. "DID10,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 9. "DID9,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 8. "DID8,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 7. "DID7,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 6. "DID6,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 5. "DID5,Data Interrupt Disable t" "0,1"
newline
bitfld.long 0x00 4. "DID4,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 3. "DID3,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 2. "DID2,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 1. "DID1,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 0. "DID0,Data Interrupt Disable t" "0,1"
group.long 0x110C++0x03
line.long 0x00 "GWDIDS0_3,"
rbitfld.long 0x00 31. "DIDS31,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 30. "DIDS30,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 29. "DIDS29,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 28. "DIDS28,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 27. "DIDS27,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 26. "DIDS26,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 25. "DIDS25,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 24. "DIDS24,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 23. "DIDS23,Data Interrupt Delayed status t" "0,1"
newline
rbitfld.long 0x00 22. "DIDS22,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 21. "DIDS21,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 20. "DIDS20,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 19. "DIDS19,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 18. "DIDS18,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 17. "DIDS17,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 16. "DIDS16,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 15. "DIDS15,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 14. "DIDS14,Data Interrupt Delayed status t" "0,1"
newline
rbitfld.long 0x00 13. "DIDS13,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 12. "DIDS12,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 11. "DIDS11,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 10. "DIDS10,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 9. "DIDS9,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 8. "DIDS8,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 7. "DIDS7,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 6. "DIDS6,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 5. "DIDS5,Data Interrupt Delayed status t" "0,1"
newline
rbitfld.long 0x00 4. "DIDS4,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 3. "DIDS3,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 2. "DIDS2,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 1. "DIDS1,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 0. "DIDS0,Data Interrupt Delayed status t" "0,1"
group.long 0x1110++0x03
line.long 0x00 "GWDIS1_3,"
bitfld.long 0x00 31. "DIS31,Data Interrupt Status t" "0,1"
bitfld.long 0x00 30. "DIS30,Data Interrupt Status t" "0,1"
bitfld.long 0x00 29. "DIS29,Data Interrupt Status t" "0,1"
bitfld.long 0x00 28. "DIS28,Data Interrupt Status t" "0,1"
bitfld.long 0x00 27. "DIS27,Data Interrupt Status t" "0,1"
bitfld.long 0x00 26. "DIS26,Data Interrupt Status t" "0,1"
bitfld.long 0x00 25. "DIS25,Data Interrupt Status t" "0,1"
bitfld.long 0x00 24. "DIS24,Data Interrupt Status t" "0,1"
bitfld.long 0x00 23. "DIS23,Data Interrupt Status t" "0,1"
newline
bitfld.long 0x00 22. "DIS22,Data Interrupt Status t" "0,1"
bitfld.long 0x00 21. "DIS21,Data Interrupt Status t" "0,1"
bitfld.long 0x00 20. "DIS20,Data Interrupt Status t" "0,1"
bitfld.long 0x00 19. "DIS19,Data Interrupt Status t" "0,1"
bitfld.long 0x00 18. "DIS18,Data Interrupt Status t" "0,1"
bitfld.long 0x00 17. "DIS17,Data Interrupt Status t" "0,1"
bitfld.long 0x00 16. "DIS16,Data Interrupt Status t" "0,1"
bitfld.long 0x00 15. "DIS15,Data Interrupt Status t" "0,1"
bitfld.long 0x00 14. "DIS14,Data Interrupt Status t" "0,1"
newline
bitfld.long 0x00 13. "DIS13,Data Interrupt Status t" "0,1"
bitfld.long 0x00 12. "DIS12,Data Interrupt Status t" "0,1"
bitfld.long 0x00 11. "DIS11,Data Interrupt Status t" "0,1"
bitfld.long 0x00 10. "DIS10,Data Interrupt Status t" "0,1"
bitfld.long 0x00 9. "DIS9,Data Interrupt Status t" "0,1"
bitfld.long 0x00 8. "DIS8,Data Interrupt Status t" "0,1"
bitfld.long 0x00 7. "DIS7,Data Interrupt Status t" "0,1"
bitfld.long 0x00 6. "DIS6,Data Interrupt Status t" "0,1"
bitfld.long 0x00 5. "DIS5,Data Interrupt Status t" "0,1"
newline
bitfld.long 0x00 4. "DIS4,Data Interrupt Status t" "0,1"
bitfld.long 0x00 3. "DIS3,Data Interrupt Status t" "0,1"
bitfld.long 0x00 2. "DIS2,Data Interrupt Status t" "0,1"
bitfld.long 0x00 1. "DIS1,Data Interrupt Status t" "0,1"
bitfld.long 0x00 0. "DIS0,Data Interrupt Status t" "0,1"
group.long 0x1114++0x03
line.long 0x00 "GWDIE1_3,"
bitfld.long 0x00 31. "DIE31,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 30. "DIE30,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 29. "DIE29,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 28. "DIE28,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 27. "DIE27,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 26. "DIE26,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 25. "DIE25,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 24. "DIE24,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 23. "DIE23,Data Interrupt Enable t" "0,1"
newline
bitfld.long 0x00 22. "DIE22,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 21. "DIE21,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 20. "DIE20,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 19. "DIE19,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 18. "DIE18,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 17. "DIE17,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 16. "DIE16,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 15. "DIE15,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 14. "DIE14,Data Interrupt Enable t" "0,1"
newline
bitfld.long 0x00 13. "DIE13,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 12. "DIE12,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 11. "DIE11,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 10. "DIE10,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 9. "DIE9,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 8. "DIE8,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 7. "DIE7,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 6. "DIE6,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 5. "DIE5,Data Interrupt Enable t" "0,1"
newline
bitfld.long 0x00 4. "DIE4,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 3. "DIE3,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 2. "DIE2,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 1. "DIE1,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 0. "DIE0,Data Interrupt Enable t" "0,1"
group.long 0x1118++0x03
line.long 0x00 "GWDID1_3,"
bitfld.long 0x00 31. "DID31,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 30. "DID30,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 29. "DID29,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 28. "DID28,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 27. "DID27,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 26. "DID26,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 25. "DID25,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 24. "DID24,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 23. "DID23,Data Interrupt Disable t" "0,1"
newline
bitfld.long 0x00 22. "DID22,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 21. "DID21,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 20. "DID20,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 19. "DID19,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 18. "DID18,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 17. "DID17,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 16. "DID16,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 15. "DID15,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 14. "DID14,Data Interrupt Disable t" "0,1"
newline
bitfld.long 0x00 13. "DID13,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 12. "DID12,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 11. "DID11,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 10. "DID10,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 9. "DID9,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 8. "DID8,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 7. "DID7,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 6. "DID6,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 5. "DID5,Data Interrupt Disable t" "0,1"
newline
bitfld.long 0x00 4. "DID4,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 3. "DID3,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 2. "DID2,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 1. "DID1,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 0. "DID0,Data Interrupt Disable t" "0,1"
group.long 0x111C++0x03
line.long 0x00 "GWDIDS1_3,"
rbitfld.long 0x00 31. "DIDS31,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 30. "DIDS30,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 29. "DIDS29,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 28. "DIDS28,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 27. "DIDS27,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 26. "DIDS26,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 25. "DIDS25,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 24. "DIDS24,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 23. "DIDS23,Data Interrupt Delayed status t" "0,1"
newline
rbitfld.long 0x00 22. "DIDS22,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 21. "DIDS21,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 20. "DIDS20,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 19. "DIDS19,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 18. "DIDS18,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 17. "DIDS17,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 16. "DIDS16,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 15. "DIDS15,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 14. "DIDS14,Data Interrupt Delayed status t" "0,1"
newline
rbitfld.long 0x00 13. "DIDS13,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 12. "DIDS12,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 11. "DIDS11,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 10. "DIDS10,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 9. "DIDS9,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 8. "DIDS8,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 7. "DIDS7,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 6. "DIDS6,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 5. "DIDS5,Data Interrupt Delayed status t" "0,1"
newline
rbitfld.long 0x00 4. "DIDS4,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 3. "DIDS3,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 2. "DIDS2,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 1. "DIDS1,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 0. "DIDS0,Data Interrupt Delayed status t" "0,1"
group.long 0x1120++0x03
line.long 0x00 "GWDIS2_3,"
bitfld.long 0x00 31. "DIS31,Data Interrupt Status t" "0,1"
bitfld.long 0x00 30. "DIS30,Data Interrupt Status t" "0,1"
bitfld.long 0x00 29. "DIS29,Data Interrupt Status t" "0,1"
bitfld.long 0x00 28. "DIS28,Data Interrupt Status t" "0,1"
bitfld.long 0x00 27. "DIS27,Data Interrupt Status t" "0,1"
bitfld.long 0x00 26. "DIS26,Data Interrupt Status t" "0,1"
bitfld.long 0x00 25. "DIS25,Data Interrupt Status t" "0,1"
bitfld.long 0x00 24. "DIS24,Data Interrupt Status t" "0,1"
bitfld.long 0x00 23. "DIS23,Data Interrupt Status t" "0,1"
newline
bitfld.long 0x00 22. "DIS22,Data Interrupt Status t" "0,1"
bitfld.long 0x00 21. "DIS21,Data Interrupt Status t" "0,1"
bitfld.long 0x00 20. "DIS20,Data Interrupt Status t" "0,1"
bitfld.long 0x00 19. "DIS19,Data Interrupt Status t" "0,1"
bitfld.long 0x00 18. "DIS18,Data Interrupt Status t" "0,1"
bitfld.long 0x00 17. "DIS17,Data Interrupt Status t" "0,1"
bitfld.long 0x00 16. "DIS16,Data Interrupt Status t" "0,1"
bitfld.long 0x00 15. "DIS15,Data Interrupt Status t" "0,1"
bitfld.long 0x00 14. "DIS14,Data Interrupt Status t" "0,1"
newline
bitfld.long 0x00 13. "DIS13,Data Interrupt Status t" "0,1"
bitfld.long 0x00 12. "DIS12,Data Interrupt Status t" "0,1"
bitfld.long 0x00 11. "DIS11,Data Interrupt Status t" "0,1"
bitfld.long 0x00 10. "DIS10,Data Interrupt Status t" "0,1"
bitfld.long 0x00 9. "DIS9,Data Interrupt Status t" "0,1"
bitfld.long 0x00 8. "DIS8,Data Interrupt Status t" "0,1"
bitfld.long 0x00 7. "DIS7,Data Interrupt Status t" "0,1"
bitfld.long 0x00 6. "DIS6,Data Interrupt Status t" "0,1"
bitfld.long 0x00 5. "DIS5,Data Interrupt Status t" "0,1"
newline
bitfld.long 0x00 4. "DIS4,Data Interrupt Status t" "0,1"
bitfld.long 0x00 3. "DIS3,Data Interrupt Status t" "0,1"
bitfld.long 0x00 2. "DIS2,Data Interrupt Status t" "0,1"
bitfld.long 0x00 1. "DIS1,Data Interrupt Status t" "0,1"
bitfld.long 0x00 0. "DIS0,Data Interrupt Status t" "0,1"
group.long 0x1124++0x03
line.long 0x00 "GWDIE2_3,"
bitfld.long 0x00 31. "DIE31,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 30. "DIE30,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 29. "DIE29,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 28. "DIE28,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 27. "DIE27,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 26. "DIE26,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 25. "DIE25,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 24. "DIE24,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 23. "DIE23,Data Interrupt Enable t" "0,1"
newline
bitfld.long 0x00 22. "DIE22,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 21. "DIE21,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 20. "DIE20,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 19. "DIE19,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 18. "DIE18,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 17. "DIE17,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 16. "DIE16,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 15. "DIE15,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 14. "DIE14,Data Interrupt Enable t" "0,1"
newline
bitfld.long 0x00 13. "DIE13,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 12. "DIE12,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 11. "DIE11,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 10. "DIE10,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 9. "DIE9,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 8. "DIE8,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 7. "DIE7,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 6. "DIE6,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 5. "DIE5,Data Interrupt Enable t" "0,1"
newline
bitfld.long 0x00 4. "DIE4,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 3. "DIE3,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 2. "DIE2,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 1. "DIE1,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 0. "DIE0,Data Interrupt Enable t" "0,1"
group.long 0x1128++0x03
line.long 0x00 "GWDID2_3,"
bitfld.long 0x00 31. "DID31,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 30. "DID30,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 29. "DID29,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 28. "DID28,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 27. "DID27,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 26. "DID26,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 25. "DID25,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 24. "DID24,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 23. "DID23,Data Interrupt Disable t" "0,1"
newline
bitfld.long 0x00 22. "DID22,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 21. "DID21,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 20. "DID20,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 19. "DID19,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 18. "DID18,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 17. "DID17,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 16. "DID16,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 15. "DID15,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 14. "DID14,Data Interrupt Disable t" "0,1"
newline
bitfld.long 0x00 13. "DID13,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 12. "DID12,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 11. "DID11,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 10. "DID10,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 9. "DID9,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 8. "DID8,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 7. "DID7,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 6. "DID6,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 5. "DID5,Data Interrupt Disable t" "0,1"
newline
bitfld.long 0x00 4. "DID4,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 3. "DID3,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 2. "DID2,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 1. "DID1,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 0. "DID0,Data Interrupt Disable t" "0,1"
group.long 0x112C++0x03
line.long 0x00 "GWDIDS2_3,"
rbitfld.long 0x00 31. "DIDS31,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 30. "DIDS30,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 29. "DIDS29,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 28. "DIDS28,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 27. "DIDS27,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 26. "DIDS26,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 25. "DIDS25,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 24. "DIDS24,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 23. "DIDS23,Data Interrupt Delayed status t" "0,1"
newline
rbitfld.long 0x00 22. "DIDS22,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 21. "DIDS21,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 20. "DIDS20,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 19. "DIDS19,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 18. "DIDS18,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 17. "DIDS17,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 16. "DIDS16,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 15. "DIDS15,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 14. "DIDS14,Data Interrupt Delayed status t" "0,1"
newline
rbitfld.long 0x00 13. "DIDS13,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 12. "DIDS12,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 11. "DIDS11,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 10. "DIDS10,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 9. "DIDS9,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 8. "DIDS8,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 7. "DIDS7,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 6. "DIDS6,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 5. "DIDS5,Data Interrupt Delayed status t" "0,1"
newline
rbitfld.long 0x00 4. "DIDS4,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 3. "DIDS3,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 2. "DIDS2,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 1. "DIDS1,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 0. "DIDS0,Data Interrupt Delayed status t" "0,1"
group.long 0x1130++0x03
line.long 0x00 "GWDIS3_3,"
bitfld.long 0x00 31. "DIS31,Data Interrupt Status t" "0,1"
bitfld.long 0x00 30. "DIS30,Data Interrupt Status t" "0,1"
bitfld.long 0x00 29. "DIS29,Data Interrupt Status t" "0,1"
bitfld.long 0x00 28. "DIS28,Data Interrupt Status t" "0,1"
bitfld.long 0x00 27. "DIS27,Data Interrupt Status t" "0,1"
bitfld.long 0x00 26. "DIS26,Data Interrupt Status t" "0,1"
bitfld.long 0x00 25. "DIS25,Data Interrupt Status t" "0,1"
bitfld.long 0x00 24. "DIS24,Data Interrupt Status t" "0,1"
bitfld.long 0x00 23. "DIS23,Data Interrupt Status t" "0,1"
newline
bitfld.long 0x00 22. "DIS22,Data Interrupt Status t" "0,1"
bitfld.long 0x00 21. "DIS21,Data Interrupt Status t" "0,1"
bitfld.long 0x00 20. "DIS20,Data Interrupt Status t" "0,1"
bitfld.long 0x00 19. "DIS19,Data Interrupt Status t" "0,1"
bitfld.long 0x00 18. "DIS18,Data Interrupt Status t" "0,1"
bitfld.long 0x00 17. "DIS17,Data Interrupt Status t" "0,1"
bitfld.long 0x00 16. "DIS16,Data Interrupt Status t" "0,1"
bitfld.long 0x00 15. "DIS15,Data Interrupt Status t" "0,1"
bitfld.long 0x00 14. "DIS14,Data Interrupt Status t" "0,1"
newline
bitfld.long 0x00 13. "DIS13,Data Interrupt Status t" "0,1"
bitfld.long 0x00 12. "DIS12,Data Interrupt Status t" "0,1"
bitfld.long 0x00 11. "DIS11,Data Interrupt Status t" "0,1"
bitfld.long 0x00 10. "DIS10,Data Interrupt Status t" "0,1"
bitfld.long 0x00 9. "DIS9,Data Interrupt Status t" "0,1"
bitfld.long 0x00 8. "DIS8,Data Interrupt Status t" "0,1"
bitfld.long 0x00 7. "DIS7,Data Interrupt Status t" "0,1"
bitfld.long 0x00 6. "DIS6,Data Interrupt Status t" "0,1"
bitfld.long 0x00 5. "DIS5,Data Interrupt Status t" "0,1"
newline
bitfld.long 0x00 4. "DIS4,Data Interrupt Status t" "0,1"
bitfld.long 0x00 3. "DIS3,Data Interrupt Status t" "0,1"
bitfld.long 0x00 2. "DIS2,Data Interrupt Status t" "0,1"
bitfld.long 0x00 1. "DIS1,Data Interrupt Status t" "0,1"
bitfld.long 0x00 0. "DIS0,Data Interrupt Status t" "0,1"
group.long 0x1134++0x03
line.long 0x00 "GWDIE3_3,"
bitfld.long 0x00 31. "DIE31,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 30. "DIE30,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 29. "DIE29,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 28. "DIE28,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 27. "DIE27,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 26. "DIE26,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 25. "DIE25,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 24. "DIE24,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 23. "DIE23,Data Interrupt Enable t" "0,1"
newline
bitfld.long 0x00 22. "DIE22,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 21. "DIE21,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 20. "DIE20,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 19. "DIE19,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 18. "DIE18,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 17. "DIE17,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 16. "DIE16,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 15. "DIE15,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 14. "DIE14,Data Interrupt Enable t" "0,1"
newline
bitfld.long 0x00 13. "DIE13,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 12. "DIE12,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 11. "DIE11,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 10. "DIE10,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 9. "DIE9,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 8. "DIE8,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 7. "DIE7,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 6. "DIE6,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 5. "DIE5,Data Interrupt Enable t" "0,1"
newline
bitfld.long 0x00 4. "DIE4,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 3. "DIE3,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 2. "DIE2,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 1. "DIE1,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 0. "DIE0,Data Interrupt Enable t" "0,1"
group.long 0x1138++0x03
line.long 0x00 "GWDID3_3,"
bitfld.long 0x00 31. "DID31,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 30. "DID30,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 29. "DID29,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 28. "DID28,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 27. "DID27,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 26. "DID26,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 25. "DID25,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 24. "DID24,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 23. "DID23,Data Interrupt Disable t" "0,1"
newline
bitfld.long 0x00 22. "DID22,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 21. "DID21,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 20. "DID20,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 19. "DID19,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 18. "DID18,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 17. "DID17,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 16. "DID16,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 15. "DID15,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 14. "DID14,Data Interrupt Disable t" "0,1"
newline
bitfld.long 0x00 13. "DID13,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 12. "DID12,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 11. "DID11,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 10. "DID10,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 9. "DID9,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 8. "DID8,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 7. "DID7,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 6. "DID6,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 5. "DID5,Data Interrupt Disable t" "0,1"
newline
bitfld.long 0x00 4. "DID4,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 3. "DID3,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 2. "DID2,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 1. "DID1,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 0. "DID0,Data Interrupt Disable t" "0,1"
group.long 0x113C++0x03
line.long 0x00 "GWDIDS3_3,"
rbitfld.long 0x00 31. "DIDS31,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 30. "DIDS30,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 29. "DIDS29,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 28. "DIDS28,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 27. "DIDS27,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 26. "DIDS26,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 25. "DIDS25,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 24. "DIDS24,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 23. "DIDS23,Data Interrupt Delayed status t" "0,1"
newline
rbitfld.long 0x00 22. "DIDS22,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 21. "DIDS21,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 20. "DIDS20,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 19. "DIDS19,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 18. "DIDS18,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 17. "DIDS17,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 16. "DIDS16,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 15. "DIDS15,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 14. "DIDS14,Data Interrupt Delayed status t" "0,1"
newline
rbitfld.long 0x00 13. "DIDS13,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 12. "DIDS12,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 11. "DIDS11,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 10. "DIDS10,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 9. "DIDS9,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 8. "DIDS8,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 7. "DIDS7,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 6. "DIDS6,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 5. "DIDS5,Data Interrupt Delayed status t" "0,1"
newline
rbitfld.long 0x00 4. "DIDS4,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 3. "DIDS3,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 2. "DIDS2,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 1. "DIDS1,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 0. "DIDS0,Data Interrupt Delayed status t" "0,1"
group.long 0x1180++0x03
line.long 0x00 "GWTSDIS3,"
hexmask.long 0x00 2.--31. 1. "RSV,Reserved area"
bitfld.long 0x00 1. "TSDIS1,Time Stamp Data Interrupt Status s" "0,1"
bitfld.long 0x00 0. "TSDIS0,Time Stamp Data Interrupt Status s" "0,1"
group.long 0x1184++0x03
line.long 0x00 "GWTSDIE3,"
hexmask.long 0x00 2.--31. 1. "RSV,Reserved area"
bitfld.long 0x00 1. "TSDIE1,TimeStamp Data Interrupt Enable s" "0,1"
bitfld.long 0x00 0. "TSDIE0,TimeStamp Data Interrupt Enable s" "0,1"
group.long 0x1188++0x03
line.long 0x00 "GWTSDID3,"
hexmask.long 0x00 2.--31. 1. "RSV,Reserved area"
bitfld.long 0x00 1. "TSDID1,TimeStamp Data Interrupt Disable s" "0,1"
bitfld.long 0x00 0. "TSDID0,TimeStamp Data Interrupt Disable s" "0,1"
group.long 0x1190++0x03
line.long 0x00 "GWEIS03,"
rbitfld.long 0x00 30.--31. "RSV0,Reserved area" "0,1,2,3"
bitfld.long 0x00 28.--29. "TSDNES,Timestamp Descriptor Number Error Status Set conditions: HW: Bit i sets when GWMDNC.TSDMN+1 descriptor has already been used to process one timestamp for descriptor chain i and the timestamp processing is not finished" "0,1,2,3"
rbitfld.long 0x00 26.--27. "RSV1,Reserved area" "0,1,2,3"
bitfld.long 0x00 24.--25. "TDFES,Timestamp Descriptor Full Error Status" "0,1,2,3"
hexmask.long.byte 0x00 16.--23. 1. "FSES,Frame Size Error Status Set conditions: HW: Bit q of this register is set when a frame bigger than GWRMFSC.MFSq has been received for descriptor queue q"
bitfld.long 0x00 15. "TSHES,TimeStamp Hardware Error Status Set conditions: HW: This error happens when timestamps are coming too fast to GWCA to be stored in time so timestamp are lost even if the timestamp RAM is not full" "0,1"
bitfld.long 0x00 14. "TXDNES,TX Descriptor Number Error Status Set conditions: HW: GWMDNC.TXDMN+1 descriptor has already been used to process one frame and the frame processing is not finished" "0,1"
rbitfld.long 0x00 13. "RSV2,Reserved area" "0,1"
bitfld.long 0x00 12. "SEQES,SEQuence Error Status Set conditions: HW: A FMID FEND has been received before a frame transfer started" "0,1"
newline
bitfld.long 0x00 11. "TFES,TAG Filtering Error Status Set conditions: HW: An unauthorized TAG format has been detected" "0,1"
bitfld.long 0x00 10. "USMFSES,Under Switch Minimum Frame Size Error Status Set conditions: HW: A frame smaller than 32 bytes has been received from CPU for transmission" "0,1"
bitfld.long 0x00 9. "TSOVFES,TimeStamp OVerFlow Error Status Set conditions: HW: When a timestamp is received when the timestamp RAM is full" "0,1"
bitfld.long 0x00 8. "L23UECCES,Layer 2/3 Update ECC Error Status Set conditions: HW: When an ECC error has been detected while reading Layer 2/3 update information from the Layer 2/3 update RAM" "0,1"
bitfld.long 0x00 7. "TSECCES,TimeStamp ECC Error Status Set conditions: HW: When an ECC error has been detected while reading a timestamp from timestamp RAM" "0,1"
bitfld.long 0x00 6. "AECCES,AXI ECC Error Status" "0,1"
bitfld.long 0x00 5. "MECCES,Multicast ECC Error Status" "0,1"
bitfld.long 0x00 4. "DSECCES,Descriptor ECC Error Status" "0,1"
bitfld.long 0x00 3. "PECCES,Pointer ECC Error Status" "0,1"
newline
bitfld.long 0x00 2. "TECCES,TAG ECC Error Status Set conditions: HW: When an ECC error has been detected in a TAG from the fabric read interface and one or more TAGs are forwarded to the CPU (forwarded and not overwritten by L2/L3 update function)" "0,1"
bitfld.long 0x00 1. "DECCES,Data ECC Error Status Set conditions: HW: When an ECC error has been detected in a data from the fabric read interface" "0,1"
bitfld.long 0x00 0. "AES,AXI Error Status" "0,1"
group.long 0x1194++0x03
line.long 0x00 "GWEIE03,"
rbitfld.long 0x00 30.--31. "RSV0,Reserved area" "0,1,2,3"
bitfld.long 0x00 28.--29. "TSDNEE,TimeStamp Descriptor Number Error Enable Values: 1b0: Interrupt disabled" "0,1,2,3"
rbitfld.long 0x00 26.--27. "RSV1,Reserved area" "0,1,2,3"
bitfld.long 0x00 24.--25. "TDFEE,Timestamp Descriptor Full Error Enable" "0,1,2,3"
hexmask.long.byte 0x00 16.--23. 1. "FSEE,Frame Size Error Enable"
bitfld.long 0x00 15. "TSHEE,TimeStamp Hardware Error Enable" "0,1"
bitfld.long 0x00 14. "TXDNEE,TX Descriptor Number Error Enable Values: 1b0: Interrupt disabled" "0,1"
rbitfld.long 0x00 13. "RSV2,Reserved area" "0,1"
bitfld.long 0x00 12. "SEQEE,SEQuence Error Enable Values: 1b0: Interrupt disabled" "0,1"
newline
bitfld.long 0x00 11. "TFEE,TAG Filtering Error Enable Values: 1b0: Interrupt disabled" "0,1"
bitfld.long 0x00 10. "USMFSEE,Under Switch Minimum Frame Size Error Enable Values: 1b0: Interrupt disabled" "0,1"
bitfld.long 0x00 9. "TSOVFEE,TimeStamp Overflow Error Enable Values: 1b0: Interrupt disabled" "0,1"
bitfld.long 0x00 8. "L23UECCEE,Layer 2/3 Update ECC Error Enable Values: 1b0: Interrupt disabled" "0,1"
bitfld.long 0x00 7. "TSECCEE,TimeStamp ECC Error Enable" "0,1"
bitfld.long 0x00 6. "AECCEE,AXI ECC Error Enable" "0,1"
bitfld.long 0x00 5. "MECCEE,Multicast ECC Error Enable" "0,1"
bitfld.long 0x00 4. "DSECCEE,Descriptor ECC Error Enable" "0,1"
bitfld.long 0x00 3. "PECCEE,Pointer ECC Error Enable" "0,1"
newline
bitfld.long 0x00 2. "TECCEE,TAG ECC Error Enable" "0,1"
bitfld.long 0x00 1. "DECCEE,Data ECC Error Enable" "0,1"
bitfld.long 0x00 0. "AEE,AXI Error Enable" "0,1"
group.long 0x1198++0x03
line.long 0x00 "GWEID03,"
rbitfld.long 0x00 30.--31. "RSV0,Reserved area" "0,1,2,3"
bitfld.long 0x00 28.--29. "TSDNED,Timestamp Descriptor Number Error Disable Functions: Writing 1 to one of these bits will clear the corresponding bit in GWEIE0.TSDNED register" "0,1,2,3"
rbitfld.long 0x00 26.--27. "RSV1,Reserved area" "0,1,2,3"
bitfld.long 0x00 24.--25. "TDFED,Timestamp Descriptor Full Error Disable" "0,1,2,3"
hexmask.long.byte 0x00 16.--23. 1. "FSED,Frame Size Error Disable"
bitfld.long 0x00 15. "TSHED,TimeStamp Hardware Full Error Disable" "0,1"
bitfld.long 0x00 14. "TXDNED,TX Descriptor Number Error Disable Functions: Writing 1 to this bit will clear GWEIE0.TXDNEE register" "0,1"
rbitfld.long 0x00 13. "RSV2,Reserved area" "0,1"
bitfld.long 0x00 12. "SEQED,SEQuence Error Disable Functions: Writing 1 to this bit will clear GWEIE0.SEQEE register" "0,1"
newline
bitfld.long 0x00 11. "TFED,TAG Filtering Error Disable Functions: Writing 1 to this bit will clear GWEIE0.TFEE register" "0,1"
bitfld.long 0x00 10. "USMFSED,Under Switch Minimum Frame Size Error Disable Functions: Writing 1 to this bit will clear GWEIE0.USMFSEE register" "0,1"
bitfld.long 0x00 9. "TSOVFED,TimeStamp Overflow Error Disable Functions: Writing 1 to this bit will clear GWEIE0.TSOVFEE register" "0,1"
bitfld.long 0x00 8. "L23UECCED,Disable Functions: Writing 1 to this bit will clear GWEIE0.L23UECCEE register" "0,1"
bitfld.long 0x00 7. "TSECCED,TimeStamp ECC Error Disable" "0,1"
bitfld.long 0x00 6. "AECCED,AXI ECC Error Disable" "0,1"
bitfld.long 0x00 5. "MECCED,Multicast ECC error Disable" "0,1"
bitfld.long 0x00 4. "DSECCED,Descriptor ECC Error Disable" "0,1"
bitfld.long 0x00 3. "PECCED,Pointer ECC error Disable" "0,1"
newline
bitfld.long 0x00 2. "DECCED,Data ECC error Disable" "0,1"
bitfld.long 0x00 1. "TECCED,TAG ECC error Disable" "0,1"
bitfld.long 0x00 0. "AED,AXI Error Disable" "0,1"
group.long 0x11A0++0x03
line.long 0x00 "GWEIS13,"
hexmask.long.byte 0x00 24.--31. 1. "RSV0,Reserved area"
hexmask.long.byte 0x00 16.--23. 1. "DQSES,Descriptor Queue Security Error Status Set conditions: HW: Bit q of this register is set when a non-secure descriptor is received (FDESCR.SEC is not set [FWD]) and queue q is a secure queue (GWRDQSC.RDQSL[q] is set) Clear conditions: HW: Being in.."
hexmask.long.byte 0x00 8.--15. 1. "RSV1,Reserved area"
hexmask.long.byte 0x00 0.--7. 1. "DQOES,Descriptor Queue Overflow Error Status Set conditions: HW: Bit q of this register is set when a descriptor is received for queue q when it is full (GWRDQDCq.DQDq == GWRDQMq.DNQq) not disabled (GWRDQC.RDQD[q] is not set) and GWCA is not going out.."
group.long 0x11A4++0x03
line.long 0x00 "GWEIE13,"
hexmask.long.byte 0x00 24.--31. 1. "RSV0,Reserved area"
hexmask.long.byte 0x00 16.--23. 1. "DQSEE,Descriptor Queue Security Error Enable Values: 1b0 for bit q: Interrupt disabled for error q"
hexmask.long.byte 0x00 8.--15. 1. "RSV1,Reserved area"
hexmask.long.byte 0x00 0.--7. 1. "DQOEE,Descriptor Queue Overflow Error Enable Values: 1b0 for bit q: Interrupt disabled for error q"
group.long 0x11A8++0x03
line.long 0x00 "GWEID13,"
hexmask.long.byte 0x00 24.--31. 1. "RSV0,Reserved area"
hexmask.long.byte 0x00 16.--23. 1. "DQSED,Descriptor Queue Security Error Disable Functions: Writing 1 to bit q in this register will clear bit q in GWEIE1.DQSEE register"
hexmask.long.byte 0x00 8.--15. 1. "RSV1,Reserved area"
hexmask.long.byte 0x00 0.--7. 1. "DQOED,Descriptor Queue Overflow Error Disable Functions: Writing 1 to bit q in this register will clear bit q in GWEIE1.DQOEE register"
group.long 0x1200++0x03
line.long 0x00 "GWEIS20_3,"
bitfld.long 0x00 31. "DFES31,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 30. "DFES30,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 29. "DFES29,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 28. "DFES28,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 27. "DFES27,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 26. "DFES26,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 25. "DFES25,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 24. "DFES24,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 23. "DFES23,Descriptor Full Error Status t" "0,1"
newline
bitfld.long 0x00 22. "DFES22,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 21. "DFES21,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 20. "DFES20,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 19. "DFES19,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 18. "DFES18,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 17. "DFES17,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 16. "DFES16,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 15. "DFES15,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 14. "DFES14,Descriptor Full Error Status t" "0,1"
newline
bitfld.long 0x00 13. "DFES13,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 12. "DFES12,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 11. "DFES11,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 10. "DFES10,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 9. "DFES9,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 8. "DFES8,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 7. "DFES7,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 6. "DFES6,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 5. "DFES5,Descriptor Full Error Status t" "0,1"
newline
bitfld.long 0x00 4. "DFES4,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 3. "DFES3,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 2. "DFES2,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 1. "DFES1,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 0. "DFES0,Descriptor Full Error Status t" "0,1"
group.long 0x1204++0x03
line.long 0x00 "GWEIE20_3,"
bitfld.long 0x00 31. "DFEE31,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 30. "DFEE30,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 29. "DFEE29,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 28. "DFEE28,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 27. "DFEE27,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 26. "DFEE26,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 25. "DFEE25,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 24. "DFEE24,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 23. "DFEE23,Descriptor Full Error Enable t" "0,1"
newline
bitfld.long 0x00 22. "DFEE22,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 21. "DFEE21,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 20. "DFEE20,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 19. "DFEE19,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 18. "DFEE18,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 17. "DFEE17,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 16. "DFEE16,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 15. "DFEE15,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 14. "DFEE14,Descriptor Full Error Enable t" "0,1"
newline
bitfld.long 0x00 13. "DFEE13,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 12. "DFEE12,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 11. "DFEE11,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 10. "DFEE10,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 9. "DFEE9,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 8. "DFEE8,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 7. "DFEE7,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 6. "DFEE6,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 5. "DFEE5,Descriptor Full Error Enable t" "0,1"
newline
bitfld.long 0x00 4. "DFEE4,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 3. "DFEE3,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 2. "DFEE2,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 1. "DFEE1,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 0. "DFEE0,Descriptor Full Error Enable t" "0,1"
group.long 0x1208++0x03
line.long 0x00 "GWEID20_3,"
bitfld.long 0x00 31. "DFED31,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 30. "DFED30,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 29. "DFED29,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 28. "DFED28,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 27. "DFED27,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 26. "DFED26,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 25. "DFED25,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 24. "DFED24,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 23. "DFED23,Descriptor Full Error Enable t" "0,1"
newline
bitfld.long 0x00 22. "DFED22,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 21. "DFED21,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 20. "DFED20,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 19. "DFED19,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 18. "DFED18,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 17. "DFED17,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 16. "DFED16,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 15. "DFED15,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 14. "DFED14,Descriptor Full Error Enable t" "0,1"
newline
bitfld.long 0x00 13. "DFED13,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 12. "DFED12,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 11. "DFED11,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 10. "DFED10,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 9. "DFED9,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 8. "DFED8,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 7. "DFED7,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 6. "DFED6,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 5. "DFED5,Descriptor Full Error Enable t" "0,1"
newline
bitfld.long 0x00 4. "DFED4,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 3. "DFED3,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 2. "DFED2,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 1. "DFED1,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 0. "DFED0,Descriptor Full Error Enable t" "0,1"
group.long 0x1210++0x03
line.long 0x00 "GWEIS21_3,"
bitfld.long 0x00 31. "DFES31,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 30. "DFES30,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 29. "DFES29,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 28. "DFES28,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 27. "DFES27,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 26. "DFES26,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 25. "DFES25,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 24. "DFES24,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 23. "DFES23,Descriptor Full Error Status t" "0,1"
newline
bitfld.long 0x00 22. "DFES22,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 21. "DFES21,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 20. "DFES20,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 19. "DFES19,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 18. "DFES18,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 17. "DFES17,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 16. "DFES16,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 15. "DFES15,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 14. "DFES14,Descriptor Full Error Status t" "0,1"
newline
bitfld.long 0x00 13. "DFES13,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 12. "DFES12,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 11. "DFES11,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 10. "DFES10,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 9. "DFES9,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 8. "DFES8,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 7. "DFES7,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 6. "DFES6,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 5. "DFES5,Descriptor Full Error Status t" "0,1"
newline
bitfld.long 0x00 4. "DFES4,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 3. "DFES3,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 2. "DFES2,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 1. "DFES1,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 0. "DFES0,Descriptor Full Error Status t" "0,1"
group.long 0x1214++0x03
line.long 0x00 "GWEIE21_3,"
bitfld.long 0x00 31. "DFEE31,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 30. "DFEE30,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 29. "DFEE29,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 28. "DFEE28,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 27. "DFEE27,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 26. "DFEE26,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 25. "DFEE25,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 24. "DFEE24,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 23. "DFEE23,Descriptor Full Error Enable t" "0,1"
newline
bitfld.long 0x00 22. "DFEE22,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 21. "DFEE21,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 20. "DFEE20,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 19. "DFEE19,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 18. "DFEE18,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 17. "DFEE17,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 16. "DFEE16,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 15. "DFEE15,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 14. "DFEE14,Descriptor Full Error Enable t" "0,1"
newline
bitfld.long 0x00 13. "DFEE13,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 12. "DFEE12,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 11. "DFEE11,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 10. "DFEE10,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 9. "DFEE9,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 8. "DFEE8,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 7. "DFEE7,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 6. "DFEE6,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 5. "DFEE5,Descriptor Full Error Enable t" "0,1"
newline
bitfld.long 0x00 4. "DFEE4,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 3. "DFEE3,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 2. "DFEE2,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 1. "DFEE1,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 0. "DFEE0,Descriptor Full Error Enable t" "0,1"
group.long 0x1218++0x03
line.long 0x00 "GWEID21_3,"
bitfld.long 0x00 31. "DFED31,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 30. "DFED30,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 29. "DFED29,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 28. "DFED28,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 27. "DFED27,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 26. "DFED26,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 25. "DFED25,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 24. "DFED24,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 23. "DFED23,Descriptor Full Error Enable t" "0,1"
newline
bitfld.long 0x00 22. "DFED22,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 21. "DFED21,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 20. "DFED20,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 19. "DFED19,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 18. "DFED18,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 17. "DFED17,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 16. "DFED16,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 15. "DFED15,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 14. "DFED14,Descriptor Full Error Enable t" "0,1"
newline
bitfld.long 0x00 13. "DFED13,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 12. "DFED12,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 11. "DFED11,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 10. "DFED10,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 9. "DFED9,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 8. "DFED8,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 7. "DFED7,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 6. "DFED6,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 5. "DFED5,Descriptor Full Error Enable t" "0,1"
newline
bitfld.long 0x00 4. "DFED4,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 3. "DFED3,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 2. "DFED2,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 1. "DFED1,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 0. "DFED0,Descriptor Full Error Enable t" "0,1"
group.long 0x1220++0x03
line.long 0x00 "GWEIS22_3,"
bitfld.long 0x00 31. "DFES31,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 30. "DFES30,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 29. "DFES29,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 28. "DFES28,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 27. "DFES27,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 26. "DFES26,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 25. "DFES25,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 24. "DFES24,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 23. "DFES23,Descriptor Full Error Status t" "0,1"
newline
bitfld.long 0x00 22. "DFES22,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 21. "DFES21,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 20. "DFES20,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 19. "DFES19,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 18. "DFES18,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 17. "DFES17,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 16. "DFES16,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 15. "DFES15,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 14. "DFES14,Descriptor Full Error Status t" "0,1"
newline
bitfld.long 0x00 13. "DFES13,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 12. "DFES12,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 11. "DFES11,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 10. "DFES10,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 9. "DFES9,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 8. "DFES8,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 7. "DFES7,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 6. "DFES6,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 5. "DFES5,Descriptor Full Error Status t" "0,1"
newline
bitfld.long 0x00 4. "DFES4,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 3. "DFES3,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 2. "DFES2,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 1. "DFES1,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 0. "DFES0,Descriptor Full Error Status t" "0,1"
group.long 0x1224++0x03
line.long 0x00 "GWEIE22_3,"
bitfld.long 0x00 31. "DFEE31,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 30. "DFEE30,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 29. "DFEE29,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 28. "DFEE28,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 27. "DFEE27,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 26. "DFEE26,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 25. "DFEE25,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 24. "DFEE24,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 23. "DFEE23,Descriptor Full Error Enable t" "0,1"
newline
bitfld.long 0x00 22. "DFEE22,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 21. "DFEE21,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 20. "DFEE20,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 19. "DFEE19,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 18. "DFEE18,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 17. "DFEE17,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 16. "DFEE16,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 15. "DFEE15,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 14. "DFEE14,Descriptor Full Error Enable t" "0,1"
newline
bitfld.long 0x00 13. "DFEE13,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 12. "DFEE12,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 11. "DFEE11,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 10. "DFEE10,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 9. "DFEE9,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 8. "DFEE8,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 7. "DFEE7,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 6. "DFEE6,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 5. "DFEE5,Descriptor Full Error Enable t" "0,1"
newline
bitfld.long 0x00 4. "DFEE4,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 3. "DFEE3,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 2. "DFEE2,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 1. "DFEE1,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 0. "DFEE0,Descriptor Full Error Enable t" "0,1"
group.long 0x1228++0x03
line.long 0x00 "GWEID22_3,"
bitfld.long 0x00 31. "DFED31,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 30. "DFED30,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 29. "DFED29,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 28. "DFED28,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 27. "DFED27,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 26. "DFED26,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 25. "DFED25,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 24. "DFED24,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 23. "DFED23,Descriptor Full Error Enable t" "0,1"
newline
bitfld.long 0x00 22. "DFED22,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 21. "DFED21,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 20. "DFED20,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 19. "DFED19,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 18. "DFED18,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 17. "DFED17,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 16. "DFED16,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 15. "DFED15,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 14. "DFED14,Descriptor Full Error Enable t" "0,1"
newline
bitfld.long 0x00 13. "DFED13,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 12. "DFED12,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 11. "DFED11,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 10. "DFED10,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 9. "DFED9,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 8. "DFED8,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 7. "DFED7,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 6. "DFED6,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 5. "DFED5,Descriptor Full Error Enable t" "0,1"
newline
bitfld.long 0x00 4. "DFED4,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 3. "DFED3,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 2. "DFED2,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 1. "DFED1,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 0. "DFED0,Descriptor Full Error Enable t" "0,1"
group.long 0x1230++0x03
line.long 0x00 "GWEIS23_3,"
bitfld.long 0x00 31. "DFES31,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 30. "DFES30,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 29. "DFES29,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 28. "DFES28,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 27. "DFES27,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 26. "DFES26,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 25. "DFES25,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 24. "DFES24,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 23. "DFES23,Descriptor Full Error Status t" "0,1"
newline
bitfld.long 0x00 22. "DFES22,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 21. "DFES21,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 20. "DFES20,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 19. "DFES19,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 18. "DFES18,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 17. "DFES17,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 16. "DFES16,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 15. "DFES15,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 14. "DFES14,Descriptor Full Error Status t" "0,1"
newline
bitfld.long 0x00 13. "DFES13,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 12. "DFES12,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 11. "DFES11,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 10. "DFES10,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 9. "DFES9,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 8. "DFES8,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 7. "DFES7,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 6. "DFES6,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 5. "DFES5,Descriptor Full Error Status t" "0,1"
newline
bitfld.long 0x00 4. "DFES4,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 3. "DFES3,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 2. "DFES2,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 1. "DFES1,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 0. "DFES0,Descriptor Full Error Status t" "0,1"
group.long 0x1234++0x03
line.long 0x00 "GWEIE23_3,"
bitfld.long 0x00 31. "DFEE31,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 30. "DFEE30,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 29. "DFEE29,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 28. "DFEE28,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 27. "DFEE27,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 26. "DFEE26,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 25. "DFEE25,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 24. "DFEE24,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 23. "DFEE23,Descriptor Full Error Enable t" "0,1"
newline
bitfld.long 0x00 22. "DFEE22,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 21. "DFEE21,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 20. "DFEE20,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 19. "DFEE19,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 18. "DFEE18,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 17. "DFEE17,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 16. "DFEE16,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 15. "DFEE15,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 14. "DFEE14,Descriptor Full Error Enable t" "0,1"
newline
bitfld.long 0x00 13. "DFEE13,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 12. "DFEE12,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 11. "DFEE11,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 10. "DFEE10,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 9. "DFEE9,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 8. "DFEE8,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 7. "DFEE7,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 6. "DFEE6,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 5. "DFEE5,Descriptor Full Error Enable t" "0,1"
newline
bitfld.long 0x00 4. "DFEE4,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 3. "DFEE3,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 2. "DFEE2,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 1. "DFEE1,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 0. "DFEE0,Descriptor Full Error Enable t" "0,1"
group.long 0x1238++0x03
line.long 0x00 "GWEID23_3,"
bitfld.long 0x00 31. "DFED31,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 30. "DFED30,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 29. "DFED29,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 28. "DFED28,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 27. "DFED27,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 26. "DFED26,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 25. "DFED25,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 24. "DFED24,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 23. "DFED23,Descriptor Full Error Enable t" "0,1"
newline
bitfld.long 0x00 22. "DFED22,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 21. "DFED21,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 20. "DFED20,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 19. "DFED19,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 18. "DFED18,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 17. "DFED17,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 16. "DFED16,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 15. "DFED15,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 14. "DFED14,Descriptor Full Error Enable t" "0,1"
newline
bitfld.long 0x00 13. "DFED13,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 12. "DFED12,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 11. "DFED11,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 10. "DFED10,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 9. "DFED9,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 8. "DFED8,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 7. "DFED7,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 6. "DFED6,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 5. "DFED5,Descriptor Full Error Enable t" "0,1"
newline
bitfld.long 0x00 4. "DFED4,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 3. "DFED3,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 2. "DFED2,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 1. "DFED1,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 0. "DFED0,Descriptor Full Error Enable t" "0,1"
group.long 0x1280++0x03
line.long 0x00 "GWEIS33,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
bitfld.long 0x00 7. "IAOES7,Incremental Area Overflow Error Status i" "0,1"
bitfld.long 0x00 6. "IAOES6,Incremental Area Overflow Error Status i" "0,1"
bitfld.long 0x00 5. "IAOES5,Incremental Area Overflow Error Status i" "0,1"
bitfld.long 0x00 4. "IAOES4,Incremental Area Overflow Error Status i" "0,1"
bitfld.long 0x00 3. "IAOES3,Incremental Area Overflow Error Status i" "0,1"
bitfld.long 0x00 2. "IAOES2,Incremental Area Overflow Error Status i" "0,1"
bitfld.long 0x00 1. "IAOES1,Incremental Area Overflow Error Status i" "0,1"
bitfld.long 0x00 0. "IAOES0,Incremental Area Overflow Error Status i" "0,1"
group.long 0x1284++0x03
line.long 0x00 "GWEIE33,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
bitfld.long 0x00 7. "IAOEE7,Incremental Area Overflow Error Enable i" "0,1"
bitfld.long 0x00 6. "IAOEE6,Incremental Area Overflow Error Enable i" "0,1"
bitfld.long 0x00 5. "IAOEE5,Incremental Area Overflow Error Enable i" "0,1"
bitfld.long 0x00 4. "IAOEE4,Incremental Area Overflow Error Enable i" "0,1"
bitfld.long 0x00 3. "IAOEE3,Incremental Area Overflow Error Enable i" "0,1"
bitfld.long 0x00 2. "IAOEE2,Incremental Area Overflow Error Enable i" "0,1"
bitfld.long 0x00 1. "IAOEE1,Incremental Area Overflow Error Enable i" "0,1"
bitfld.long 0x00 0. "IAOEE0,Incremental Area Overflow Error Enable i" "0,1"
group.long 0x1288++0x03
line.long 0x00 "GWEID33,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
bitfld.long 0x00 7. "IAOED7,Incremental Area Overflow Error Disable i" "0,1"
bitfld.long 0x00 6. "IAOED6,Incremental Area Overflow Error Disable i" "0,1"
bitfld.long 0x00 5. "IAOED5,Incremental Area Overflow Error Disable i" "0,1"
bitfld.long 0x00 4. "IAOED4,Incremental Area Overflow Error Disable i" "0,1"
bitfld.long 0x00 3. "IAOED3,Incremental Area Overflow Error Disable i" "0,1"
bitfld.long 0x00 2. "IAOED2,Incremental Area Overflow Error Disable i" "0,1"
bitfld.long 0x00 1. "IAOED1,Incremental Area Overflow Error Disable i" "0,1"
bitfld.long 0x00 0. "IAOED0,Incremental Area Overflow Error Disable i" "0,1"
group.long 0x1290++0x03
line.long 0x00 "GWEIS43,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "DSECN,Data Size Error Chain Number Clear conditions: HW: Being in RESET mode will clear this register"
rbitfld.long 0x00 18.--23. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 17. "DSEIOS,Data Size Error Interrupt Overflow Status Set conditions: When a Data Size Error occurs and GWEIS4.DSES is already set to one" "0,1"
bitfld.long 0x00 16. "DSES,Data Size Error Status" "0,1"
rbitfld.long 0x00 15. "RSV2,Reserved area" "0,1"
hexmask.long.byte 0x00 8.--14. 1. "DSSECN,Descriptor Security Error Chain Number Restrictions: HW: This register is only valid for RX queues"
rbitfld.long 0x00 2.--7. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 1. "DSSEIOS,Descriptor Security Error Interrupt Overflow Status Clear conditions: HW: Being in RESET mode will clear this register" "0,1"
newline
bitfld.long 0x00 0. "DSSES,Descriptor Security Error Status" "0,1"
group.long 0x1294++0x03
line.long 0x00 "GWEIE43,"
hexmask.long.word 0x00 18.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 17. "DSEIOE,Data Size Error Interrupt Overflow Interrupt Enable" "0,1"
bitfld.long 0x00 16. "DSEE,Data Size Error Enable" "0,1"
hexmask.long.word 0x00 2.--15. 1. "RSV1,Reserved area"
bitfld.long 0x00 1. "DSSEIOE,Descriptor Security Error Interrupt Overflow Enable Values: 1b0: Interrupt disabled" "0,1"
bitfld.long 0x00 0. "DSSEE,Descriptor Security Error Enable" "0,1"
group.long 0x1298++0x03
line.long 0x00 "GWEID43,"
hexmask.long.word 0x00 18.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 17. "DSEIOD,Data Size Error Interrupt Overflow Disable" "0,1"
bitfld.long 0x00 16. "DSED,Data Size Error Disable" "0,1"
hexmask.long.word 0x00 2.--15. 1. "RSV1,Reserved area"
bitfld.long 0x00 1. "DSSEIOD,Descriptor Security Error Interrupt Overflow Disable Functions: Writing 1 to this bit will clear GWEIE4.DSSEIOE register" "0,1"
bitfld.long 0x00 0. "DSSED,Descriptor Security Error Disable Functions: Writing 1 to this bit will clear GWEIE4.DSSEE register" "0,1"
group.long 0x12A0++0x03
line.long 0x00 "GWEIS53,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "RXDNECN,RX Descriptor Number Error Chain Number Clear conditions: HW: Being in RESET mode will clear this register"
rbitfld.long 0x00 18.--23. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 17. "RXDNEIOS,RX Descriptor Number Error Interrupt Overflow Status Clear conditions: HW: Being in RESET mode will clear this register" "0,1"
bitfld.long 0x00 16. "RXDNES,RX Descriptor Number Error Status Set conditions: HW: GWMDNC.RXDMN+1 descriptor has already been used to process one frame and the frame processing is not finished" "0,1"
rbitfld.long 0x00 15. "RSV2,Reserved area" "0,1"
hexmask.long.byte 0x00 8.--14. 1. "DCTECN,Descriptor Chain Type Error Chain Number Clear conditions: HW: Being in RESET mode will clear this register"
rbitfld.long 0x00 2.--7. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 1. "DCTEIOS,Descriptor Chain Type Error Interrupt Overflow Status Clear conditions: HW: Being in RESET mode will clear this register" "0,1"
newline
bitfld.long 0x00 0. "DCTES,Descriptor Chain Type Error Status" "0,1"
group.long 0x12A4++0x03
line.long 0x00 "GWEIE53,"
hexmask.long.word 0x00 18.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 17. "RXDNEIOE,RX Descriptor Number Error Interrupt Overflow Enable Values: 1b0: Interrupt disabled" "0,1"
bitfld.long 0x00 16. "RXDNEE,RX Descriptor Number Error Enable" "0,1"
hexmask.long.word 0x00 2.--15. 1. "RSV1,Reserved area"
bitfld.long 0x00 1. "DCTEIOE,Descriptor Chain Type Error Interrupt Overflow Enable Values: 1b0: Interrupt disabled" "0,1"
bitfld.long 0x00 0. "DCTEE,Descriptor Chain Type Error Enable" "0,1"
group.long 0x12A8++0x03
line.long 0x00 "GWEID53,"
hexmask.long.word 0x00 18.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 17. "RXDNEIOD,RX Descriptor Number Error Interrupt Overflow Disable Functions: Writing 1 to this bit will clear GWEIE5.RXDNEIOE register" "0,1"
bitfld.long 0x00 16. "RXDNED,RX Descriptor Number Error Disable Functions: Writing 1 to this bit will clear GWEIE5.RXDNEE register" "0,1"
hexmask.long.word 0x00 2.--15. 1. "RSV1,Reserved area"
bitfld.long 0x00 1. "DCTEIOD,Descriptor Chain Type Error Interrupt Overflow Disable Functions: Writing 1 to this bit will clear GWEIE5.DCTEIOE register" "0,1"
bitfld.long 0x00 0. "DCTED,Descriptor Chain Type Error Disable Functions: Writing 1 to this bit will clear GWEIE5.DCTEE register" "0,1"
group.long 0x1800++0x03
line.long 0x00 "GWSCR03,"
rbitfld.long 0x00 30.--31. "RSV0,Reserved area" "0,1,2,3"
bitfld.long 0x00 28.--29. "TRSL,Timer Register Security Level" "0,1,2,3"
rbitfld.long 0x00 26.--27. "RSV1,Reserved area" "0,1,2,3"
bitfld.long 0x00 24.--25. "TSQRSL,Timestamp Queue Register Security Level" "0,1,2,3"
hexmask.long.byte 0x00 16.--23. 1. "DQRSL,Descriptor queue Register Security Level"
hexmask.long.byte 0x00 8.--15. 1. "APRSL,AXI Priority Register Security Level"
bitfld.long 0x00 7. "EIRSL,Error Interrupt Register Security Level Values: 1b0: Error Interrupt registers can only be accessed by the APB secure interface 1b1: Error Interrupt registers can be accessed by both APBs Error Interrupt registers include the following.." "0,1"
bitfld.long 0x00 6. "AXRSL,AXI Register Security Level" "0,1"
bitfld.long 0x00 5. "TSRSL,Timestamp Register Security Level" "0,1"
newline
bitfld.long 0x00 4. "TGRSL,TAG Register Security Level" "0,1"
bitfld.long 0x00 3. "MCRSL,MAC Register Security Level" "0,1"
bitfld.long 0x00 2. "MTRSL,Multicast Table Register Security Level" "0,1"
bitfld.long 0x00 1. "RRSL,Reception Register Security Level" "0,1"
bitfld.long 0x00 0. "MRSL,Mode Register Security Level" "0,1"
group.long 0x1804++0x03
line.long 0x00 "GWSCR13,"
hexmask.long 0x00 1.--31. 1. "RSV,Reserved area"
bitfld.long 0x00 0. "CRSL,Counter Register Security Level" "0,1"
group.long 0x1900++0x03
line.long 0x00 "GWSCR20_3,"
bitfld.long 0x00 31. "ACRSL31,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 30. "ACRSL30,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 29. "ACRSL29,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 28. "ACRSL28,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 27. "ACRSL27,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 26. "ACRSL26,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 25. "ACRSL25,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 24. "ACRSL24,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 23. "ACRSL23,AXI Chain Register Security Level t" "0,1"
newline
bitfld.long 0x00 22. "ACRSL22,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 21. "ACRSL21,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 20. "ACRSL20,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 19. "ACRSL19,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 18. "ACRSL18,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 17. "ACRSL17,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 16. "ACRSL16,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 15. "ACRSL15,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 14. "ACRSL14,AXI Chain Register Security Level t" "0,1"
newline
bitfld.long 0x00 13. "ACRSL13,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 12. "ACRSL12,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 11. "ACRSL11,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 10. "ACRSL10,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 9. "ACRSL9,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 8. "ACRSL8,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 7. "ACRSL7,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 6. "ACRSL6,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 5. "ACRSL5,AXI Chain Register Security Level t" "0,1"
newline
bitfld.long 0x00 4. "ACRSL4,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 3. "ACRSL3,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 2. "ACRSL2,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 1. "ACRSL1,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 0. "ACRSL0,AXI Chain Register Security Level t" "0,1"
group.long 0x1904++0x03
line.long 0x00 "GWSCR21_3,"
bitfld.long 0x00 31. "ACRSL31,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 30. "ACRSL30,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 29. "ACRSL29,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 28. "ACRSL28,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 27. "ACRSL27,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 26. "ACRSL26,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 25. "ACRSL25,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 24. "ACRSL24,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 23. "ACRSL23,AXI Chain Register Security Level t" "0,1"
newline
bitfld.long 0x00 22. "ACRSL22,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 21. "ACRSL21,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 20. "ACRSL20,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 19. "ACRSL19,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 18. "ACRSL18,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 17. "ACRSL17,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 16. "ACRSL16,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 15. "ACRSL15,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 14. "ACRSL14,AXI Chain Register Security Level t" "0,1"
newline
bitfld.long 0x00 13. "ACRSL13,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 12. "ACRSL12,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 11. "ACRSL11,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 10. "ACRSL10,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 9. "ACRSL9,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 8. "ACRSL8,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 7. "ACRSL7,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 6. "ACRSL6,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 5. "ACRSL5,AXI Chain Register Security Level t" "0,1"
newline
bitfld.long 0x00 4. "ACRSL4,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 3. "ACRSL3,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 2. "ACRSL2,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 1. "ACRSL1,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 0. "ACRSL0,AXI Chain Register Security Level t" "0,1"
group.long 0x1908++0x03
line.long 0x00 "GWSCR22_3,"
bitfld.long 0x00 31. "ACRSL31,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 30. "ACRSL30,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 29. "ACRSL29,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 28. "ACRSL28,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 27. "ACRSL27,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 26. "ACRSL26,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 25. "ACRSL25,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 24. "ACRSL24,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 23. "ACRSL23,AXI Chain Register Security Level t" "0,1"
newline
bitfld.long 0x00 22. "ACRSL22,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 21. "ACRSL21,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 20. "ACRSL20,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 19. "ACRSL19,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 18. "ACRSL18,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 17. "ACRSL17,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 16. "ACRSL16,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 15. "ACRSL15,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 14. "ACRSL14,AXI Chain Register Security Level t" "0,1"
newline
bitfld.long 0x00 13. "ACRSL13,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 12. "ACRSL12,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 11. "ACRSL11,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 10. "ACRSL10,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 9. "ACRSL9,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 8. "ACRSL8,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 7. "ACRSL7,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 6. "ACRSL6,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 5. "ACRSL5,AXI Chain Register Security Level t" "0,1"
newline
bitfld.long 0x00 4. "ACRSL4,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 3. "ACRSL3,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 2. "ACRSL2,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 1. "ACRSL1,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 0. "ACRSL0,AXI Chain Register Security Level t" "0,1"
group.long 0x190C++0x03
line.long 0x00 "GWSCR23_3,"
bitfld.long 0x00 31. "ACRSL31,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 30. "ACRSL30,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 29. "ACRSL29,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 28. "ACRSL28,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 27. "ACRSL27,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 26. "ACRSL26,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 25. "ACRSL25,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 24. "ACRSL24,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 23. "ACRSL23,AXI Chain Register Security Level t" "0,1"
newline
bitfld.long 0x00 22. "ACRSL22,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 21. "ACRSL21,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 20. "ACRSL20,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 19. "ACRSL19,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 18. "ACRSL18,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 17. "ACRSL17,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 16. "ACRSL16,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 15. "ACRSL15,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 14. "ACRSL14,AXI Chain Register Security Level t" "0,1"
newline
bitfld.long 0x00 13. "ACRSL13,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 12. "ACRSL12,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 11. "ACRSL11,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 10. "ACRSL10,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 9. "ACRSL9,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 8. "ACRSL8,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 7. "ACRSL7,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 6. "ACRSL6,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 5. "ACRSL5,AXI Chain Register Security Level t" "0,1"
newline
bitfld.long 0x00 4. "ACRSL4,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 3. "ACRSL3,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 2. "ACRSL2,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 1. "ACRSL1,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 0. "ACRSL0,AXI Chain Register Security Level t" "0,1"
tree.end
tree "GWCA_INST_1"
base ad:0xE6892000
group.long 0x00++0x03
line.long 0x00 "GWMC4,"
hexmask.long 0x00 2.--31. 1. "RSV,Reserved area"
bitfld.long 0x00 0.--1. "OPC,OPerating mode Command" "0,1,2,3"
group.long 0x04++0x03
line.long 0x00 "GWMS4,"
hexmask.long 0x00 2.--31. 1. "RSV,Reserved area"
rbitfld.long 0x00 0.--1. "OPS,OPerating mode Status" "0,1,2,3"
group.long 0x10++0x03
line.long 0x00 "GWIRC4,"
rbitfld.long 0x00 31. "RSV7,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "IPVR7,IPV remapping i Functions: Configure to which descriptor queue descriptor received with IPV i will be stored (when a descriptor is received from forwarding engine with FDESCR.IPV [FWD] equal to i)" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 27. "RSV6,Reserved area" "0,1"
bitfld.long 0x00 24.--26. "IPVR6,IPV remapping i Functions: Configure to which descriptor queue descriptor received with IPV i will be stored (when a descriptor is received from forwarding engine with FDESCR.IPV [FWD] equal to i)" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 23. "RSV5,Reserved area" "0,1"
bitfld.long 0x00 20.--22. "IPVR5,IPV remapping i Functions: Configure to which descriptor queue descriptor received with IPV i will be stored (when a descriptor is received from forwarding engine with FDESCR.IPV [FWD] equal to i)" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 19. "RSV4,Reserved area" "0,1"
bitfld.long 0x00 16.--18. "IPVR4,IPV remapping i Functions: Configure to which descriptor queue descriptor received with IPV i will be stored (when a descriptor is received from forwarding engine with FDESCR.IPV [FWD] equal to i)" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 15. "RSV3,Reserved area" "0,1"
newline
bitfld.long 0x00 12.--14. "IPVR3,IPV remapping i Functions: Configure to which descriptor queue descriptor received with IPV i will be stored (when a descriptor is received from forwarding engine with FDESCR.IPV [FWD] equal to i)" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 11. "RSV2,Reserved area" "0,1"
bitfld.long 0x00 8.--10. "IPVR2,IPV remapping i Functions: Configure to which descriptor queue descriptor received with IPV i will be stored (when a descriptor is received from forwarding engine with FDESCR.IPV [FWD] equal to i)" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 7. "RSV1,Reserved area" "0,1"
bitfld.long 0x00 4.--6. "IPVR1,IPV remapping i Functions: Configure to which descriptor queue descriptor received with IPV i will be stored (when a descriptor is received from forwarding engine with FDESCR.IPV [FWD] equal to i)" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 3. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 0.--2. "IPVR0,IPV remapping i Functions: Configure to which descriptor queue descriptor received with IPV i will be stored (when a descriptor is received from forwarding engine with FDESCR.IPV [FWD] equal to i)" "0,1,2,3,4,5,6,7"
group.long 0x14++0x03
line.long 0x00 "GWRDQSC4,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
bitfld.long 0x00 7. "RDQSL7,RX Descriptor Queue Security Level i" "0,1"
bitfld.long 0x00 6. "RDQSL6,RX Descriptor Queue Security Level i" "0,1"
bitfld.long 0x00 5. "RDQSL5,RX Descriptor Queue Security Level i" "0,1"
bitfld.long 0x00 4. "RDQSL4,RX Descriptor Queue Security Level i" "0,1"
bitfld.long 0x00 3. "RDQSL3,RX Descriptor Queue Security Level i" "0,1"
bitfld.long 0x00 2. "RDQSL2,RX Descriptor Queue Security Level i" "0,1"
bitfld.long 0x00 1. "RDQSL1,RX Descriptor Queue Security Level i" "0,1"
bitfld.long 0x00 0. "RDQSL0,RX Descriptor Queue Security Level i" "0,1"
group.long 0x18++0x03
line.long 0x00 "GWRDQC4,"
hexmask.long.byte 0x00 24.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 23. "RDQP7,RX Descriptor Queue Pause i" "0,1"
bitfld.long 0x00 22. "RDQP6,RX Descriptor Queue Pause i" "0,1"
bitfld.long 0x00 21. "RDQP5,RX Descriptor Queue Pause i" "0,1"
bitfld.long 0x00 20. "RDQP4,RX Descriptor Queue Pause i" "0,1"
bitfld.long 0x00 19. "RDQP3,RX Descriptor Queue Pause i" "0,1"
bitfld.long 0x00 18. "RDQP2,RX Descriptor Queue Pause i" "0,1"
bitfld.long 0x00 17. "RDQP1,RX Descriptor Queue Pause i" "0,1"
bitfld.long 0x00 16. "RDQP0,RX Descriptor Queue Pause i" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "RSV1,Reserved area"
bitfld.long 0x00 7. "RDQD7,RX Descriptor Queue Disable i" "0,1"
bitfld.long 0x00 6. "RDQD6,RX Descriptor Queue Disable i" "0,1"
bitfld.long 0x00 5. "RDQD5,RX Descriptor Queue Disable i" "0,1"
bitfld.long 0x00 4. "RDQD4,RX Descriptor Queue Disable i" "0,1"
bitfld.long 0x00 3. "RDQD3,RX Descriptor Queue Disable i" "0,1"
bitfld.long 0x00 2. "RDQD2,RX Descriptor Queue Disable i" "0,1"
bitfld.long 0x00 1. "RDQD1,RX Descriptor Queue Disable i" "0,1"
bitfld.long 0x00 0. "RDQD0,RX Descriptor Queue Disable i" "0,1"
group.long 0x1C++0x03
line.long 0x00 "GWRDQAC4,"
bitfld.long 0x00 28.--31. "RDQA7,RX Descriptor Queue Arbitration i" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "RDQA6,RX Descriptor Queue Arbitration i" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 20.--23. "RDQA5,RX Descriptor Queue Arbitration i" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "RDQA4,RX Descriptor Queue Arbitration i" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "RDQA3,RX Descriptor Queue Arbitration i" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "RDQA2,RX Descriptor Queue Arbitration i" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "RDQA1,RX Descriptor Queue Arbitration i" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "RDQA0,RX Descriptor Queue Arbitration i" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x20++0x03
line.long 0x00 "GWRGC4,"
hexmask.long 0x00 1.--31. 1. "RSV,Reserved area"
bitfld.long 0x00 0. "RCPT,Receive CRC Pass Through [802.3] This bit selects to pass FCS field on the reception frame" "0,1"
group.long 0x40++0x03
line.long 0x00 "GWRMFSC0_4,"
hexmask.long.word 0x00 16.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--15. 1. "MFSq,Maximum Frame Size q Functions: Maximum frame size for descriptor queue q"
group.long 0x44++0x03
line.long 0x00 "GWRMFSC1_4,"
hexmask.long.word 0x00 16.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--15. 1. "MFSq,Maximum Frame Size q Functions: Maximum frame size for descriptor queue q"
group.long 0x48++0x03
line.long 0x00 "GWRMFSC2_4,"
hexmask.long.word 0x00 16.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--15. 1. "MFSq,Maximum Frame Size q Functions: Maximum frame size for descriptor queue q"
group.long 0x4C++0x03
line.long 0x00 "GWRMFSC3_4,"
hexmask.long.word 0x00 16.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--15. 1. "MFSq,Maximum Frame Size q Functions: Maximum frame size for descriptor queue q"
group.long 0x50++0x03
line.long 0x00 "GWRMFSC4_4,"
hexmask.long.word 0x00 16.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--15. 1. "MFSq,Maximum Frame Size q Functions: Maximum frame size for descriptor queue q"
group.long 0x54++0x03
line.long 0x00 "GWRMFSC5_4,"
hexmask.long.word 0x00 16.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--15. 1. "MFSq,Maximum Frame Size q Functions: Maximum frame size for descriptor queue q"
group.long 0x58++0x03
line.long 0x00 "GWRMFSC6_4,"
hexmask.long.word 0x00 16.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--15. 1. "MFSq,Maximum Frame Size q Functions: Maximum frame size for descriptor queue q"
group.long 0x5C++0x03
line.long 0x00 "GWRMFSC7_4,"
hexmask.long.word 0x00 16.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--15. 1. "MFSq,Maximum Frame Size q Functions: Maximum frame size for descriptor queue q"
group.long 0x60++0x03
line.long 0x00 "GWRDQDC0_4,"
hexmask.long.tbyte 0x00 11.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--10. 1. "DQDq,Descriptor Queue Depth q Functions?: Number of descriptors that can contain descriptor queue q"
group.long 0x64++0x03
line.long 0x00 "GWRDQDC1_4,"
hexmask.long.tbyte 0x00 11.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--10. 1. "DQDq,Descriptor Queue Depth q Functions?: Number of descriptors that can contain descriptor queue q"
group.long 0x68++0x03
line.long 0x00 "GWRDQDC2_4,"
hexmask.long.tbyte 0x00 11.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--10. 1. "DQDq,Descriptor Queue Depth q Functions?: Number of descriptors that can contain descriptor queue q"
group.long 0x6C++0x03
line.long 0x00 "GWRDQDC3_4,"
hexmask.long.tbyte 0x00 11.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--10. 1. "DQDq,Descriptor Queue Depth q Functions?: Number of descriptors that can contain descriptor queue q"
group.long 0x70++0x03
line.long 0x00 "GWRDQDC4_4,"
hexmask.long.tbyte 0x00 11.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--10. 1. "DQDq,Descriptor Queue Depth q Functions?: Number of descriptors that can contain descriptor queue q"
group.long 0x74++0x03
line.long 0x00 "GWRDQDC5_4,"
hexmask.long.tbyte 0x00 11.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--10. 1. "DQDq,Descriptor Queue Depth q Functions?: Number of descriptors that can contain descriptor queue q"
group.long 0x78++0x03
line.long 0x00 "GWRDQDC6_4,"
hexmask.long.tbyte 0x00 11.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--10. 1. "DQDq,Descriptor Queue Depth q Functions?: Number of descriptors that can contain descriptor queue q"
group.long 0x7C++0x03
line.long 0x00 "GWRDQDC7_4,"
hexmask.long.tbyte 0x00 11.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--10. 1. "DQDq,Descriptor Queue Depth q Functions?: Number of descriptors that can contain descriptor queue q"
group.long 0x80++0x03
line.long 0x00 "GWRDQM0_4,"
hexmask.long.tbyte 0x00 11.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--10. 1. "DNQq,Descriptor Number in Queue q"
group.long 0x84++0x03
line.long 0x00 "GWRDQM1_4,"
hexmask.long.tbyte 0x00 11.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--10. 1. "DNQq,Descriptor Number in Queue q"
group.long 0x88++0x03
line.long 0x00 "GWRDQM2_4,"
hexmask.long.tbyte 0x00 11.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--10. 1. "DNQq,Descriptor Number in Queue q"
group.long 0x8C++0x03
line.long 0x00 "GWRDQM3_4,"
hexmask.long.tbyte 0x00 11.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--10. 1. "DNQq,Descriptor Number in Queue q"
group.long 0x90++0x03
line.long 0x00 "GWRDQM4_4,"
hexmask.long.tbyte 0x00 11.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--10. 1. "DNQq,Descriptor Number in Queue q"
group.long 0x94++0x03
line.long 0x00 "GWRDQM5_4,"
hexmask.long.tbyte 0x00 11.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--10. 1. "DNQq,Descriptor Number in Queue q"
group.long 0x98++0x03
line.long 0x00 "GWRDQM6_4,"
hexmask.long.tbyte 0x00 11.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--10. 1. "DNQq,Descriptor Number in Queue q"
group.long 0x9C++0x03
line.long 0x00 "GWRDQM7_4,"
hexmask.long.tbyte 0x00 11.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--10. 1. "DNQq,Descriptor Number in Queue q"
group.long 0xA0++0x03
line.long 0x00 "GWRDQMLM0_4,"
hexmask.long.tbyte 0x00 11.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--10. 1. "DMLQq,Descriptor Max Level in Queue q"
group.long 0xA4++0x03
line.long 0x00 "GWRDQMLM1_4,"
hexmask.long.tbyte 0x00 11.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--10. 1. "DMLQq,Descriptor Max Level in Queue q"
group.long 0xA8++0x03
line.long 0x00 "GWRDQMLM2_4,"
hexmask.long.tbyte 0x00 11.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--10. 1. "DMLQq,Descriptor Max Level in Queue q"
group.long 0xAC++0x03
line.long 0x00 "GWRDQMLM3_4,"
hexmask.long.tbyte 0x00 11.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--10. 1. "DMLQq,Descriptor Max Level in Queue q"
group.long 0xB0++0x03
line.long 0x00 "GWRDQMLM4_4,"
hexmask.long.tbyte 0x00 11.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--10. 1. "DMLQq,Descriptor Max Level in Queue q"
group.long 0xB4++0x03
line.long 0x00 "GWRDQMLM5_4,"
hexmask.long.tbyte 0x00 11.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--10. 1. "DMLQq,Descriptor Max Level in Queue q"
group.long 0xB8++0x03
line.long 0x00 "GWRDQMLM6_4,"
hexmask.long.tbyte 0x00 11.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--10. 1. "DMLQq,Descriptor Max Level in Queue q"
group.long 0xBC++0x03
line.long 0x00 "GWRDQMLM7_4,"
hexmask.long.tbyte 0x00 11.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--10. 1. "DMLQq,Descriptor Max Level in Queue q"
group.long 0x100++0x03
line.long 0x00 "GWMTIRM4,"
hexmask.long 0x00 2.--31. 1. "RSV,Reserved area"
rbitfld.long 0x00 1. "MTR,Multicast Table Ready Set conditions: When GWMTIRM.MTIOG is getting cleared" "0,1"
bitfld.long 0x00 0. "MTIOG,Multicast Table Initialization Ongoing" "0,1"
group.long 0x104++0x03
line.long 0x00 "GWMSTLS4,"
hexmask.long.word 0x00 23.--31. 1. "RSV0,Reserved area"
hexmask.long.byte 0x00 16.--22. 1. "MSENL,Multicast Setting Entry Number Learn"
rbitfld.long 0x00 11.--15. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MNL,Multicast Number Learn" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 7. "RSV2,Reserved area" "0,1"
hexmask.long.byte 0x00 0.--6. 1. "MNRCNL,Multicast Next Descriptor Chain Number Learn"
group.long 0x108++0x03
line.long 0x00 "GWMSTLR4,"
rbitfld.long 0x00 31. "MTL,Multicast Table Learning Set conditions: SW: Writing GWMSTLS register will set this bit" "0,1"
hexmask.long 0x00 2.--30. 1. "RSV,Reserved area"
rbitfld.long 0x00 1. "MTLSF,Multicast Table Learning Security Fail Values: 1b0: Entry learning didnt fail because of a security error" "0,1"
rbitfld.long 0x00 0. "MTLF,Multicast Table Learning Fail Values: 1b0: Entry learning didnt fail because the Multicast table is not ready" "0,1"
group.long 0x10C++0x03
line.long 0x00 "GWMSTSS4,"
hexmask.long 0x00 7.--31. 1. "RSV,Reserved area"
hexmask.long.byte 0x00 0.--6. 1. "MSENS,Multicast Setting Entry Number Search"
group.long 0x110++0x03
line.long 0x00 "GWMSTSR4,"
rbitfld.long 0x00 31. "MTS,Multicast Table Searching Set conditions: SW: Writing GWMSTSS register will set this bit" "0,1"
hexmask.long.word 0x00 17.--30. 1. "RSV0,Reserved area"
rbitfld.long 0x00 16. "MTSEF,Multicast Table Searching ECC Fail Values: 1b0: Entry searching didnt fail because of an ECC error" "0,1"
rbitfld.long 0x00 11.--15. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rbitfld.long 0x00 8.--10. "MNR,Multicast Number result" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 7. "RSV2,Reserved area" "0,1"
hexmask.long.byte 0x00 0.--6. 1. "MNRCNR,Multicast Next RX Descriptor Chain Number result"
group.long 0x120++0x03
line.long 0x00 "GWMAC04,"
hexmask.long.word 0x00 16.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--15. 1. "MAUP,MAC Address Upper Part Functions: These bits are used to set the 16 higher-order bits of the MAC address"
group.long 0x124++0x03
line.long 0x00 "GWMAC14,"
hexmask.long 0x00 0.--31. 1. "MADP,MAC Address Downer Part Functions: These bits are used to set the 32 lower-order bits of the MAC address"
group.long 0x130++0x03
line.long 0x00 "GWVCC4,"
hexmask.long.word 0x00 19.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 16.--18. "VEM,VLAN Egress Mode Values?: 3b000: No VLAN mode frames are transmitted with no VLAN 3b001: C-TAG VLAN mode frames are transmitted with ingress C-TAG if there is one stored in the Local RAM" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 1.--15. 1. "RSV1,Reserved area"
bitfld.long 0x00 0. "VIM,VLAN Ingress Mode Values?: 1b0: Incoming VLAN mode 1b1: Port based VLAN mode Restrictions?: SW: This register shouldnt be set to 1b1 is the switch is in no VLAN mode (In forwarding engine FWGC.SVM is set to 2b00 [FWD]) A security register.." "0,1"
group.long 0x134++0x03
line.long 0x00 "GWVTC4,"
bitfld.long 0x00 31. "STD_P,S-TAG DEI" "0,1"
bitfld.long 0x00 28.--30. "STP_P,S-TAG PCP" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 16.--27. 1. "STV_P,S-TAG VLAN"
bitfld.long 0x00 15. "CTD_P,C-TAG DEI" "0,1"
bitfld.long 0x00 12.--14. "CTP_P,C-TAG PCP" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 0.--11. 1. "CTV_P,C-TAG VLAN"
group.long 0x138++0x03
line.long 0x00 "GWTTFC4,"
hexmask.long.tbyte 0x00 9.--31. 1. "RSV,Reserved area"
bitfld.long 0x00 8. "UT,Unknown TAG Values: 1b0: Unknow Tag frame passed 1b1: Unknow Tag frame rejected A security register should be set to authorize write/read access by the unsecure APB" "0,1"
bitfld.long 0x00 7. "SCRT,SCR-TAG Values: 1b0: SCR-TAG frame passed 1b1: SCR-TAG frame rejected A security register should be set to authorize write/read access by the unsecure APB" "0,1"
bitfld.long 0x00 6. "SCT,SC-TAG Values: 1b0: SC-TAG frame passed 1b1: SC-TAG frame rejected A security register should be set to authorize write/read access by the unsecure APB" "0,1"
bitfld.long 0x00 5. "CRT,CR-TAG Values: 1b0: CR-TAG frame passed 1b1: CR-TAG frame rejected A security register should be set to authorize write/read access by the unsecure APB" "0,1"
bitfld.long 0x00 4. "CT,C-TAG Values: 1b0: C-TAG frame passed 1b1: C-TAG frame rejected A security register should be set to authorize write/read access by the unsecure APB" "0,1"
bitfld.long 0x00 3. "CSRT,CoSR-TAG Values: 1b0: CoSR-TAG frame passed 1b1: CoSR-TAG frame rejected A security register should be set to authorize write/read access by the unsecure APB" "0,1"
bitfld.long 0x00 2. "CST,CoS-TAG Values: 1b0: CoS-TAG frame passed 1b1: CoS-TAG frame rejected A security register should be set to authorize write/read access by the unsecure APB" "0,1"
bitfld.long 0x00 1. "RT,R-TAG Values: 1b0: R-TAG frame passed 1b1: R-TAG frame rejected A security register should be set to authorize write/read access by the unsecure APB" "0,1"
newline
bitfld.long 0x00 0. "NT,No Tag Values: 1b0: No Tag frame passed 1b1: No Tag frame rejected A security register should be set to authorize write/read access by the unsecure APB" "0,1"
group.long 0x140++0x03
line.long 0x00 "GWTDCAC00_4,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
hexmask.long.byte 0x00 0.--7. 1. "TSCCAUPs,TS Descriptor Chain s Current Address Upper Part Update conditions: SW: Writing to this field with update it to the write value"
group.long 0x144++0x03
line.long 0x00 "GWTDCAC10_4,"
hexmask.long 0x00 0.--31. 1. "TSCCADPs,TS Descriptor Chain s Current Address Downer Part Update conditions: SW: Writing GWTDCAC0s register with update this field to the previous value written on it by the same APB"
group.long 0x148++0x03
line.long 0x00 "GWTDCAC01_4,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
hexmask.long.byte 0x00 0.--7. 1. "TSCCAUPs,TS Descriptor Chain s Current Address Upper Part Update conditions: SW: Writing to this field with update it to the write value"
group.long 0x14C++0x03
line.long 0x00 "GWTDCAC11_4,"
hexmask.long 0x00 0.--31. 1. "TSCCADPs,TS Descriptor Chain s Current Address Downer Part Update conditions: SW: Writing GWTDCAC0s register with update this field to the previous value written on it by the same APB"
group.long 0x160++0x03
line.long 0x00 "GWTSDCC0_4,"
hexmask.long.tbyte 0x00 11.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 8.--10. "OSIDs,OS ID s Functions: When a memory access is done for timer number s the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 3.--7. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 1.--2. "DCSs,Descriptor chain select Functions: Select to which chain timestamps taken with timer s will be received" "0,1,2,3"
bitfld.long 0x00 0. "TEs,Timer enable s" "0,1"
group.long 0x164++0x03
line.long 0x00 "GWTSDCC1_4,"
hexmask.long.tbyte 0x00 11.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 8.--10. "OSIDs,OS ID s Functions: When a memory access is done for timer number s the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 3.--7. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 1.--2. "DCSs,Descriptor chain select Functions: Select to which chain timestamps taken with timer s will be received" "0,1,2,3"
bitfld.long 0x00 0. "TEs,Timer enable s" "0,1"
group.long 0x180++0x03
line.long 0x00 "GWTSNM4,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
hexmask.long.byte 0x00 0.--7. 1. "TNTR,Timestamp Number in Timestamp RAM Increment conditions: HW: Incremented by 1 when a timestamp is received from a TSN Agent"
group.long 0x184++0x03
line.long 0x00 "GWTSMNM4,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
hexmask.long.byte 0x00 0.--7. 1. "TMNTR,Timestamp Maximum Number in Timestamp RAM Update conditions: HW: Set to GWTSNM.TNTR when GWTSNM.TNTR> GWTSNM.TMNTR"
group.long 0x190++0x03
line.long 0x00 "GWAC4,"
hexmask.long 0x00 2.--31. 1. "RSV,Reserved area"
rbitfld.long 0x00 1. "AMP,AXI Master Paused Values: 1b0: AXI master not paused (transaction ongoing) 1b1: AXI master paused (no transaction ongoing) Set conditions: HW: When GWAC.AMPR is set to 1b1 and all ongoing AXI transactions are completed this bit will be set" "0,1"
bitfld.long 0x00 0. "AMPR,AXI Master Pause Request Values: 1b0: AXI master pause not requested 1b1: AXI master pause requested Functions: This register blocks the AXI master from making new accesses (Because the AXI master has register slices for timing purpose few AXI.." "0,1"
group.long 0x194++0x03
line.long 0x00 "GWDCBAC04,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
hexmask.long.byte 0x00 0.--7. 1. "DCBAUP,Descriptor Chain Base Address Upper Part"
group.long 0x198++0x03
line.long 0x00 "GWDCBAC14,"
hexmask.long 0x00 0.--31. 1. "DCBADP,Descriptor Chain Base Address Downer Part"
group.long 0x1A0++0x03
line.long 0x00 "GWMDNC4,"
hexmask.long.word 0x00 18.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 16.--17. "TSDMN,TimeStamp Descriptor Maximum Number" "0,1,2,3"
rbitfld.long 0x00 13.--15. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--12. "TXDMN,TX Descriptor Maximum Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rbitfld.long 0x00 5.--7. "RSV2,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "RXDMN,RX Descriptor Maximum Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x200++0x03
line.long 0x00 "GWTRC0_4,"
bitfld.long 0x00 31. "TSR31,Transmission Start Request t" "0,1"
bitfld.long 0x00 30. "TSR30,Transmission Start Request t" "0,1"
bitfld.long 0x00 29. "TSR29,Transmission Start Request t" "0,1"
bitfld.long 0x00 28. "TSR28,Transmission Start Request t" "0,1"
bitfld.long 0x00 27. "TSR27,Transmission Start Request t" "0,1"
bitfld.long 0x00 26. "TSR26,Transmission Start Request t" "0,1"
bitfld.long 0x00 25. "TSR25,Transmission Start Request t" "0,1"
bitfld.long 0x00 24. "TSR24,Transmission Start Request t" "0,1"
bitfld.long 0x00 23. "TSR23,Transmission Start Request t" "0,1"
newline
bitfld.long 0x00 22. "TSR22,Transmission Start Request t" "0,1"
bitfld.long 0x00 21. "TSR21,Transmission Start Request t" "0,1"
bitfld.long 0x00 20. "TSR20,Transmission Start Request t" "0,1"
bitfld.long 0x00 19. "TSR19,Transmission Start Request t" "0,1"
bitfld.long 0x00 18. "TSR18,Transmission Start Request t" "0,1"
bitfld.long 0x00 17. "TSR17,Transmission Start Request t" "0,1"
bitfld.long 0x00 16. "TSR16,Transmission Start Request t" "0,1"
bitfld.long 0x00 15. "TSR15,Transmission Start Request t" "0,1"
bitfld.long 0x00 14. "TSR14,Transmission Start Request t" "0,1"
newline
bitfld.long 0x00 13. "TSR13,Transmission Start Request t" "0,1"
bitfld.long 0x00 12. "TSR12,Transmission Start Request t" "0,1"
bitfld.long 0x00 11. "TSR11,Transmission Start Request t" "0,1"
bitfld.long 0x00 10. "TSR10,Transmission Start Request t" "0,1"
bitfld.long 0x00 9. "TSR9,Transmission Start Request t" "0,1"
bitfld.long 0x00 8. "TSR8,Transmission Start Request t" "0,1"
bitfld.long 0x00 7. "TSR7,Transmission Start Request t" "0,1"
bitfld.long 0x00 6. "TSR6,Transmission Start Request t" "0,1"
bitfld.long 0x00 5. "TSR5,Transmission Start Request t" "0,1"
newline
bitfld.long 0x00 4. "TSR4,Transmission Start Request t" "0,1"
bitfld.long 0x00 3. "TSR3,Transmission Start Request t" "0,1"
bitfld.long 0x00 2. "TSR2,Transmission Start Request t" "0,1"
bitfld.long 0x00 1. "TSR1,Transmission Start Request t" "0,1"
bitfld.long 0x00 0. "TSR0,Transmission Start Request t" "0,1"
group.long 0x204++0x03
line.long 0x00 "GWTRC1_4,"
bitfld.long 0x00 31. "TSR31,Transmission Start Request t" "0,1"
bitfld.long 0x00 30. "TSR30,Transmission Start Request t" "0,1"
bitfld.long 0x00 29. "TSR29,Transmission Start Request t" "0,1"
bitfld.long 0x00 28. "TSR28,Transmission Start Request t" "0,1"
bitfld.long 0x00 27. "TSR27,Transmission Start Request t" "0,1"
bitfld.long 0x00 26. "TSR26,Transmission Start Request t" "0,1"
bitfld.long 0x00 25. "TSR25,Transmission Start Request t" "0,1"
bitfld.long 0x00 24. "TSR24,Transmission Start Request t" "0,1"
bitfld.long 0x00 23. "TSR23,Transmission Start Request t" "0,1"
newline
bitfld.long 0x00 22. "TSR22,Transmission Start Request t" "0,1"
bitfld.long 0x00 21. "TSR21,Transmission Start Request t" "0,1"
bitfld.long 0x00 20. "TSR20,Transmission Start Request t" "0,1"
bitfld.long 0x00 19. "TSR19,Transmission Start Request t" "0,1"
bitfld.long 0x00 18. "TSR18,Transmission Start Request t" "0,1"
bitfld.long 0x00 17. "TSR17,Transmission Start Request t" "0,1"
bitfld.long 0x00 16. "TSR16,Transmission Start Request t" "0,1"
bitfld.long 0x00 15. "TSR15,Transmission Start Request t" "0,1"
bitfld.long 0x00 14. "TSR14,Transmission Start Request t" "0,1"
newline
bitfld.long 0x00 13. "TSR13,Transmission Start Request t" "0,1"
bitfld.long 0x00 12. "TSR12,Transmission Start Request t" "0,1"
bitfld.long 0x00 11. "TSR11,Transmission Start Request t" "0,1"
bitfld.long 0x00 10. "TSR10,Transmission Start Request t" "0,1"
bitfld.long 0x00 9. "TSR9,Transmission Start Request t" "0,1"
bitfld.long 0x00 8. "TSR8,Transmission Start Request t" "0,1"
bitfld.long 0x00 7. "TSR7,Transmission Start Request t" "0,1"
bitfld.long 0x00 6. "TSR6,Transmission Start Request t" "0,1"
bitfld.long 0x00 5. "TSR5,Transmission Start Request t" "0,1"
newline
bitfld.long 0x00 4. "TSR4,Transmission Start Request t" "0,1"
bitfld.long 0x00 3. "TSR3,Transmission Start Request t" "0,1"
bitfld.long 0x00 2. "TSR2,Transmission Start Request t" "0,1"
bitfld.long 0x00 1. "TSR1,Transmission Start Request t" "0,1"
bitfld.long 0x00 0. "TSR0,Transmission Start Request t" "0,1"
group.long 0x208++0x03
line.long 0x00 "GWTRC2_4,"
bitfld.long 0x00 31. "TSR31,Transmission Start Request t" "0,1"
bitfld.long 0x00 30. "TSR30,Transmission Start Request t" "0,1"
bitfld.long 0x00 29. "TSR29,Transmission Start Request t" "0,1"
bitfld.long 0x00 28. "TSR28,Transmission Start Request t" "0,1"
bitfld.long 0x00 27. "TSR27,Transmission Start Request t" "0,1"
bitfld.long 0x00 26. "TSR26,Transmission Start Request t" "0,1"
bitfld.long 0x00 25. "TSR25,Transmission Start Request t" "0,1"
bitfld.long 0x00 24. "TSR24,Transmission Start Request t" "0,1"
bitfld.long 0x00 23. "TSR23,Transmission Start Request t" "0,1"
newline
bitfld.long 0x00 22. "TSR22,Transmission Start Request t" "0,1"
bitfld.long 0x00 21. "TSR21,Transmission Start Request t" "0,1"
bitfld.long 0x00 20. "TSR20,Transmission Start Request t" "0,1"
bitfld.long 0x00 19. "TSR19,Transmission Start Request t" "0,1"
bitfld.long 0x00 18. "TSR18,Transmission Start Request t" "0,1"
bitfld.long 0x00 17. "TSR17,Transmission Start Request t" "0,1"
bitfld.long 0x00 16. "TSR16,Transmission Start Request t" "0,1"
bitfld.long 0x00 15. "TSR15,Transmission Start Request t" "0,1"
bitfld.long 0x00 14. "TSR14,Transmission Start Request t" "0,1"
newline
bitfld.long 0x00 13. "TSR13,Transmission Start Request t" "0,1"
bitfld.long 0x00 12. "TSR12,Transmission Start Request t" "0,1"
bitfld.long 0x00 11. "TSR11,Transmission Start Request t" "0,1"
bitfld.long 0x00 10. "TSR10,Transmission Start Request t" "0,1"
bitfld.long 0x00 9. "TSR9,Transmission Start Request t" "0,1"
bitfld.long 0x00 8. "TSR8,Transmission Start Request t" "0,1"
bitfld.long 0x00 7. "TSR7,Transmission Start Request t" "0,1"
bitfld.long 0x00 6. "TSR6,Transmission Start Request t" "0,1"
bitfld.long 0x00 5. "TSR5,Transmission Start Request t" "0,1"
newline
bitfld.long 0x00 4. "TSR4,Transmission Start Request t" "0,1"
bitfld.long 0x00 3. "TSR3,Transmission Start Request t" "0,1"
bitfld.long 0x00 2. "TSR2,Transmission Start Request t" "0,1"
bitfld.long 0x00 1. "TSR1,Transmission Start Request t" "0,1"
bitfld.long 0x00 0. "TSR0,Transmission Start Request t" "0,1"
group.long 0x20C++0x03
line.long 0x00 "GWTRC3_4,"
bitfld.long 0x00 31. "TSR31,Transmission Start Request t" "0,1"
bitfld.long 0x00 30. "TSR30,Transmission Start Request t" "0,1"
bitfld.long 0x00 29. "TSR29,Transmission Start Request t" "0,1"
bitfld.long 0x00 28. "TSR28,Transmission Start Request t" "0,1"
bitfld.long 0x00 27. "TSR27,Transmission Start Request t" "0,1"
bitfld.long 0x00 26. "TSR26,Transmission Start Request t" "0,1"
bitfld.long 0x00 25. "TSR25,Transmission Start Request t" "0,1"
bitfld.long 0x00 24. "TSR24,Transmission Start Request t" "0,1"
bitfld.long 0x00 23. "TSR23,Transmission Start Request t" "0,1"
newline
bitfld.long 0x00 22. "TSR22,Transmission Start Request t" "0,1"
bitfld.long 0x00 21. "TSR21,Transmission Start Request t" "0,1"
bitfld.long 0x00 20. "TSR20,Transmission Start Request t" "0,1"
bitfld.long 0x00 19. "TSR19,Transmission Start Request t" "0,1"
bitfld.long 0x00 18. "TSR18,Transmission Start Request t" "0,1"
bitfld.long 0x00 17. "TSR17,Transmission Start Request t" "0,1"
bitfld.long 0x00 16. "TSR16,Transmission Start Request t" "0,1"
bitfld.long 0x00 15. "TSR15,Transmission Start Request t" "0,1"
bitfld.long 0x00 14. "TSR14,Transmission Start Request t" "0,1"
newline
bitfld.long 0x00 13. "TSR13,Transmission Start Request t" "0,1"
bitfld.long 0x00 12. "TSR12,Transmission Start Request t" "0,1"
bitfld.long 0x00 11. "TSR11,Transmission Start Request t" "0,1"
bitfld.long 0x00 10. "TSR10,Transmission Start Request t" "0,1"
bitfld.long 0x00 9. "TSR9,Transmission Start Request t" "0,1"
bitfld.long 0x00 8. "TSR8,Transmission Start Request t" "0,1"
bitfld.long 0x00 7. "TSR7,Transmission Start Request t" "0,1"
bitfld.long 0x00 6. "TSR6,Transmission Start Request t" "0,1"
bitfld.long 0x00 5. "TSR5,Transmission Start Request t" "0,1"
newline
bitfld.long 0x00 4. "TSR4,Transmission Start Request t" "0,1"
bitfld.long 0x00 3. "TSR3,Transmission Start Request t" "0,1"
bitfld.long 0x00 2. "TSR2,Transmission Start Request t" "0,1"
bitfld.long 0x00 1. "TSR1,Transmission Start Request t" "0,1"
bitfld.long 0x00 0. "TSR0,Transmission Start Request t" "0,1"
group.long 0x300++0x03
line.long 0x00 "GWTPC0_4,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
bitfld.long 0x00 7. "PPPLp7,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 6. "PPPLp6,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 5. "PPPLp5,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 4. "PPPLp4,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 3. "PPPLp3,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 2. "PPPLp2,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 1. "PPPLp1,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 0. "PPPLp0,Per Priority Pause Level p i" "0,1"
group.long 0x304++0x03
line.long 0x00 "GWTPC1_4,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
bitfld.long 0x00 7. "PPPLp7,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 6. "PPPLp6,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 5. "PPPLp5,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 4. "PPPLp4,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 3. "PPPLp3,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 2. "PPPLp2,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 1. "PPPLp1,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 0. "PPPLp0,Per Priority Pause Level p i" "0,1"
group.long 0x308++0x03
line.long 0x00 "GWTPC2_4,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
bitfld.long 0x00 7. "PPPLp7,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 6. "PPPLp6,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 5. "PPPLp5,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 4. "PPPLp4,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 3. "PPPLp3,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 2. "PPPLp2,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 1. "PPPLp1,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 0. "PPPLp0,Per Priority Pause Level p i" "0,1"
group.long 0x30C++0x03
line.long 0x00 "GWTPC3_4,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
bitfld.long 0x00 7. "PPPLp7,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 6. "PPPLp6,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 5. "PPPLp5,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 4. "PPPLp4,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 3. "PPPLp3,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 2. "PPPLp2,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 1. "PPPLp1,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 0. "PPPLp0,Per Priority Pause Level p i" "0,1"
group.long 0x310++0x03
line.long 0x00 "GWTPC4_4,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
bitfld.long 0x00 7. "PPPLp7,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 6. "PPPLp6,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 5. "PPPLp5,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 4. "PPPLp4,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 3. "PPPLp3,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 2. "PPPLp2,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 1. "PPPLp1,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 0. "PPPLp0,Per Priority Pause Level p i" "0,1"
group.long 0x314++0x03
line.long 0x00 "GWTPC5_4,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
bitfld.long 0x00 7. "PPPLp7,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 6. "PPPLp6,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 5. "PPPLp5,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 4. "PPPLp4,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 3. "PPPLp3,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 2. "PPPLp2,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 1. "PPPLp1,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 0. "PPPLp0,Per Priority Pause Level p i" "0,1"
group.long 0x318++0x03
line.long 0x00 "GWTPC6_4,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
bitfld.long 0x00 7. "PPPLp7,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 6. "PPPLp6,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 5. "PPPLp5,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 4. "PPPLp4,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 3. "PPPLp3,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 2. "PPPLp2,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 1. "PPPLp1,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 0. "PPPLp0,Per Priority Pause Level p i" "0,1"
group.long 0x31C++0x03
line.long 0x00 "GWTPC7_4,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
bitfld.long 0x00 7. "PPPLp7,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 6. "PPPLp6,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 5. "PPPLp5,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 4. "PPPLp4,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 3. "PPPLp3,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 2. "PPPLp2,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 1. "PPPLp1,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 0. "PPPLp0,Per Priority Pause Level p i" "0,1"
group.long 0x320++0x03
line.long 0x00 "GWTPC8_4,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
bitfld.long 0x00 7. "PPPLp7,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 6. "PPPLp6,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 5. "PPPLp5,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 4. "PPPLp4,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 3. "PPPLp3,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 2. "PPPLp2,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 1. "PPPLp1,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 0. "PPPLp0,Per Priority Pause Level p i" "0,1"
group.long 0x324++0x03
line.long 0x00 "GWTPC9_4,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
bitfld.long 0x00 7. "PPPLp7,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 6. "PPPLp6,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 5. "PPPLp5,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 4. "PPPLp4,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 3. "PPPLp3,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 2. "PPPLp2,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 1. "PPPLp1,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 0. "PPPLp0,Per Priority Pause Level p i" "0,1"
group.long 0x328++0x03
line.long 0x00 "GWTPC10_4,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
bitfld.long 0x00 7. "PPPLp7,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 6. "PPPLp6,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 5. "PPPLp5,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 4. "PPPLp4,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 3. "PPPLp3,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 2. "PPPLp2,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 1. "PPPLp1,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 0. "PPPLp0,Per Priority Pause Level p i" "0,1"
group.long 0x32C++0x03
line.long 0x00 "GWTPC11_4,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
bitfld.long 0x00 7. "PPPLp7,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 6. "PPPLp6,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 5. "PPPLp5,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 4. "PPPLp4,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 3. "PPPLp3,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 2. "PPPLp2,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 1. "PPPLp1,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 0. "PPPLp0,Per Priority Pause Level p i" "0,1"
group.long 0x330++0x03
line.long 0x00 "GWTPC12_4,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
bitfld.long 0x00 7. "PPPLp7,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 6. "PPPLp6,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 5. "PPPLp5,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 4. "PPPLp4,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 3. "PPPLp3,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 2. "PPPLp2,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 1. "PPPLp1,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 0. "PPPLp0,Per Priority Pause Level p i" "0,1"
group.long 0x334++0x03
line.long 0x00 "GWTPC13_4,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
bitfld.long 0x00 7. "PPPLp7,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 6. "PPPLp6,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 5. "PPPLp5,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 4. "PPPLp4,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 3. "PPPLp3,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 2. "PPPLp2,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 1. "PPPLp1,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 0. "PPPLp0,Per Priority Pause Level p i" "0,1"
group.long 0x338++0x03
line.long 0x00 "GWTPC14_4,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
bitfld.long 0x00 7. "PPPLp7,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 6. "PPPLp6,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 5. "PPPLp5,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 4. "PPPLp4,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 3. "PPPLp3,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 2. "PPPLp2,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 1. "PPPLp1,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 0. "PPPLp0,Per Priority Pause Level p i" "0,1"
group.long 0x33C++0x03
line.long 0x00 "GWTPC15_4,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
bitfld.long 0x00 7. "PPPLp7,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 6. "PPPLp6,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 5. "PPPLp5,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 4. "PPPLp4,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 3. "PPPLp3,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 2. "PPPLp2,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 1. "PPPLp1,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 0. "PPPLp0,Per Priority Pause Level p i" "0,1"
group.long 0x340++0x03
line.long 0x00 "GWTPC16_4,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
bitfld.long 0x00 7. "PPPLp7,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 6. "PPPLp6,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 5. "PPPLp5,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 4. "PPPLp4,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 3. "PPPLp3,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 2. "PPPLp2,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 1. "PPPLp1,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 0. "PPPLp0,Per Priority Pause Level p i" "0,1"
group.long 0x344++0x03
line.long 0x00 "GWTPC17_4,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
bitfld.long 0x00 7. "PPPLp7,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 6. "PPPLp6,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 5. "PPPLp5,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 4. "PPPLp4,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 3. "PPPLp3,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 2. "PPPLp2,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 1. "PPPLp1,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 0. "PPPLp0,Per Priority Pause Level p i" "0,1"
group.long 0x348++0x03
line.long 0x00 "GWTPC18_4,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
bitfld.long 0x00 7. "PPPLp7,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 6. "PPPLp6,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 5. "PPPLp5,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 4. "PPPLp4,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 3. "PPPLp3,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 2. "PPPLp2,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 1. "PPPLp1,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 0. "PPPLp0,Per Priority Pause Level p i" "0,1"
group.long 0x34C++0x03
line.long 0x00 "GWTPC19_4,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
bitfld.long 0x00 7. "PPPLp7,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 6. "PPPLp6,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 5. "PPPLp5,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 4. "PPPLp4,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 3. "PPPLp3,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 2. "PPPLp2,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 1. "PPPLp1,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 0. "PPPLp0,Per Priority Pause Level p i" "0,1"
group.long 0x350++0x03
line.long 0x00 "GWTPC20_4,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
bitfld.long 0x00 7. "PPPLp7,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 6. "PPPLp6,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 5. "PPPLp5,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 4. "PPPLp4,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 3. "PPPLp3,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 2. "PPPLp2,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 1. "PPPLp1,Per Priority Pause Level p i" "0,1"
bitfld.long 0x00 0. "PPPLp0,Per Priority Pause Level p i" "0,1"
group.long 0x380++0x03
line.long 0x00 "GWARIRM4,"
hexmask.long 0x00 2.--31. 1. "RSV,Reserved area"
rbitfld.long 0x00 1. "ARR,AXI RAM Ready Set conditions: When GWARIRM.ARIOG is getting cleared" "0,1"
bitfld.long 0x00 0. "ARIOG,AXI RAM Initialization Ongoing" "0,1"
group.long 0x400++0x03
line.long 0x00 "GWDCC0_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x404++0x03
line.long 0x00 "GWDCC1_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x408++0x03
line.long 0x00 "GWDCC2_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x40C++0x03
line.long 0x00 "GWDCC3_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x410++0x03
line.long 0x00 "GWDCC4_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x414++0x03
line.long 0x00 "GWDCC5_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x418++0x03
line.long 0x00 "GWDCC6_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x41C++0x03
line.long 0x00 "GWDCC7_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x420++0x03
line.long 0x00 "GWDCC8_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x424++0x03
line.long 0x00 "GWDCC9_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x428++0x03
line.long 0x00 "GWDCC10_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x42C++0x03
line.long 0x00 "GWDCC11_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x430++0x03
line.long 0x00 "GWDCC12_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x434++0x03
line.long 0x00 "GWDCC13_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x438++0x03
line.long 0x00 "GWDCC14_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x43C++0x03
line.long 0x00 "GWDCC15_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x440++0x03
line.long 0x00 "GWDCC16_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x444++0x03
line.long 0x00 "GWDCC17_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x448++0x03
line.long 0x00 "GWDCC18_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x44C++0x03
line.long 0x00 "GWDCC19_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x450++0x03
line.long 0x00 "GWDCC20_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x454++0x03
line.long 0x00 "GWDCC21_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x458++0x03
line.long 0x00 "GWDCC22_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x45C++0x03
line.long 0x00 "GWDCC23_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x460++0x03
line.long 0x00 "GWDCC24_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x464++0x03
line.long 0x00 "GWDCC25_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x468++0x03
line.long 0x00 "GWDCC26_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x46C++0x03
line.long 0x00 "GWDCC27_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x470++0x03
line.long 0x00 "GWDCC28_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x474++0x03
line.long 0x00 "GWDCC29_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x478++0x03
line.long 0x00 "GWDCC30_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x47C++0x03
line.long 0x00 "GWDCC31_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x480++0x03
line.long 0x00 "GWDCC32_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x484++0x03
line.long 0x00 "GWDCC33_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x488++0x03
line.long 0x00 "GWDCC34_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x48C++0x03
line.long 0x00 "GWDCC35_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x490++0x03
line.long 0x00 "GWDCC36_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x494++0x03
line.long 0x00 "GWDCC37_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x498++0x03
line.long 0x00 "GWDCC38_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x49C++0x03
line.long 0x00 "GWDCC39_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x4A0++0x03
line.long 0x00 "GWDCC40_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x4A4++0x03
line.long 0x00 "GWDCC41_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x4A8++0x03
line.long 0x00 "GWDCC42_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x4AC++0x03
line.long 0x00 "GWDCC43_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x4B0++0x03
line.long 0x00 "GWDCC44_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x4B4++0x03
line.long 0x00 "GWDCC45_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x4B8++0x03
line.long 0x00 "GWDCC46_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x4BC++0x03
line.long 0x00 "GWDCC47_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x4C0++0x03
line.long 0x00 "GWDCC48_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x4C4++0x03
line.long 0x00 "GWDCC49_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x4C8++0x03
line.long 0x00 "GWDCC50_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x4CC++0x03
line.long 0x00 "GWDCC51_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x4D0++0x03
line.long 0x00 "GWDCC52_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x4D4++0x03
line.long 0x00 "GWDCC53_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x4D8++0x03
line.long 0x00 "GWDCC54_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x4DC++0x03
line.long 0x00 "GWDCC55_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x4E0++0x03
line.long 0x00 "GWDCC56_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x4E4++0x03
line.long 0x00 "GWDCC57_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x4E8++0x03
line.long 0x00 "GWDCC58_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x4EC++0x03
line.long 0x00 "GWDCC59_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x4F0++0x03
line.long 0x00 "GWDCC60_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x4F4++0x03
line.long 0x00 "GWDCC61_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x4F8++0x03
line.long 0x00 "GWDCC62_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x4FC++0x03
line.long 0x00 "GWDCC63_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x500++0x03
line.long 0x00 "GWDCC64_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x504++0x03
line.long 0x00 "GWDCC65_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x508++0x03
line.long 0x00 "GWDCC66_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x50C++0x03
line.long 0x00 "GWDCC67_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x510++0x03
line.long 0x00 "GWDCC68_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x514++0x03
line.long 0x00 "GWDCC69_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x518++0x03
line.long 0x00 "GWDCC70_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x51C++0x03
line.long 0x00 "GWDCC71_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x520++0x03
line.long 0x00 "GWDCC72_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x524++0x03
line.long 0x00 "GWDCC73_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x528++0x03
line.long 0x00 "GWDCC74_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x52C++0x03
line.long 0x00 "GWDCC75_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x530++0x03
line.long 0x00 "GWDCC76_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x534++0x03
line.long 0x00 "GWDCC77_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x538++0x03
line.long 0x00 "GWDCC78_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x53C++0x03
line.long 0x00 "GWDCC79_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x540++0x03
line.long 0x00 "GWDCC80_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x544++0x03
line.long 0x00 "GWDCC81_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x548++0x03
line.long 0x00 "GWDCC82_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x54C++0x03
line.long 0x00 "GWDCC83_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x550++0x03
line.long 0x00 "GWDCC84_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x554++0x03
line.long 0x00 "GWDCC85_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x558++0x03
line.long 0x00 "GWDCC86_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x55C++0x03
line.long 0x00 "GWDCC87_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x560++0x03
line.long 0x00 "GWDCC88_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x564++0x03
line.long 0x00 "GWDCC89_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x568++0x03
line.long 0x00 "GWDCC90_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x56C++0x03
line.long 0x00 "GWDCC91_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x570++0x03
line.long 0x00 "GWDCC92_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x574++0x03
line.long 0x00 "GWDCC93_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x578++0x03
line.long 0x00 "GWDCC94_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x57C++0x03
line.long 0x00 "GWDCC95_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x580++0x03
line.long 0x00 "GWDCC96_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x584++0x03
line.long 0x00 "GWDCC97_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x588++0x03
line.long 0x00 "GWDCC98_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x58C++0x03
line.long 0x00 "GWDCC99_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x590++0x03
line.long 0x00 "GWDCC100_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x594++0x03
line.long 0x00 "GWDCC101_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x598++0x03
line.long 0x00 "GWDCC102_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x59C++0x03
line.long 0x00 "GWDCC103_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x5A0++0x03
line.long 0x00 "GWDCC104_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x5A4++0x03
line.long 0x00 "GWDCC105_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x5A8++0x03
line.long 0x00 "GWDCC106_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x5AC++0x03
line.long 0x00 "GWDCC107_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x5B0++0x03
line.long 0x00 "GWDCC108_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x5B4++0x03
line.long 0x00 "GWDCC109_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x5B8++0x03
line.long 0x00 "GWDCC110_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x5BC++0x03
line.long 0x00 "GWDCC111_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x5C0++0x03
line.long 0x00 "GWDCC112_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x5C4++0x03
line.long 0x00 "GWDCC113_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x5C8++0x03
line.long 0x00 "GWDCC114_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x5CC++0x03
line.long 0x00 "GWDCC115_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x5D0++0x03
line.long 0x00 "GWDCC116_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x5D4++0x03
line.long 0x00 "GWDCC117_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x5D8++0x03
line.long 0x00 "GWDCC118_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x5DC++0x03
line.long 0x00 "GWDCC119_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x5E0++0x03
line.long 0x00 "GWDCC120_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x5E4++0x03
line.long 0x00 "GWDCC121_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x5E8++0x03
line.long 0x00 "GWDCC122_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x5EC++0x03
line.long 0x00 "GWDCC123_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x5F0++0x03
line.long 0x00 "GWDCC124_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x5F4++0x03
line.long 0x00 "GWDCC125_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x5F8++0x03
line.long 0x00 "GWDCC126_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x5FC++0x03
line.long 0x00 "GWDCC127_4,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "OSIDi,OS ID i Functions: When a memory access is done for descriptor queue number i the OSID set in this register will be used" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 25.--27. "RSV1,Reserved area" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "BALRi,Base address load request i" "0,1"
rbitfld.long 0x00 19.--23. "RSV2,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "DCPi,Descriptor Chain Priority i" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12.--15. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "DQTi,Descriptor queue type i Values: 1b0: Descriptor queue i is a reception queue" "0,1"
bitfld.long 0x00 10. "SLi,Security level Values: 1b0: Chain i unsecure 1b1: Chain i secure Functions: When a chain is secured an unsecure descriptor cannot enter it (when a descriptor is received from forwarding engine [FWD] with FDESCR.SEC equal to 0)" "0,1"
newline
bitfld.long 0x00 9. "ETSi,Enable Timestamp Storage Values: 1b0: Timestamp is not added in the Descriptor" "0,1"
bitfld.long 0x00 8. "EDEi,Extended Descriptor Enable Values: 1b0: Basic Descriptor 1b1: Extended Descriptor A security register should be set to authorize write/read access by the unsecure APB" "0,1"
rbitfld.long 0x00 2.--7. "RSV4,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "_SMi,Synchronization Mode i Values: 2b00: Normal mode (full descriptor writeback) 2b01: No-write-back mode (no descriptor writeback) 2b10: Keep-DT mode (no update of DT field at descriptor write back) 2b11?: Reserved A security register should be.." "0,1,2,3"
group.long 0x800++0x03
line.long 0x00 "GWAARSS4,"
hexmask.long 0x00 7.--31. 1. "RSV,Reserved area"
hexmask.long.byte 0x00 0.--6. 1. "AARA,AXI Address RAM Address"
group.long 0x804++0x03
line.long 0x00 "GWAARSR04,"
rbitfld.long 0x00 31. "AARS,AXI Address RAM Searching Functions: This register is used to read an in AXI address RAM Set conditions: SW: Writing GWAARSS will set this bit" "0,1"
hexmask.long.word 0x00 18.--30. 1. "RSV0,Reserved area"
rbitfld.long 0x00 17. "AARSSF,AXI Address RAM Search Security fail Functions: Shows when a security error happened while reading an entry" "0,1"
rbitfld.long 0x00 16. "AARSEF,AXI Address RAM Search ECC fail Functions: Shows when an ECC error happened while reading an entry" "0,1"
hexmask.long.byte 0x00 8.--15. 1. "RSV1,Reserved area"
hexmask.long.byte 0x00 0.--7. 1. "ACARUP,AXI Current Address Result Upper Part Functions: Displays AXI address read value"
group.long 0x808++0x03
line.long 0x00 "GWAARSR14,"
hexmask.long 0x00 0.--31. 1. "ACARDP,AXI Current Address Result Downer Part Functions: Displays AXI address read value"
group.long 0x840++0x03
line.long 0x00 "GWIDAUAS0_4,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "IDAUASi,Incremental Data Area Used Size of RX Descriptor Chain i"
group.long 0x844++0x03
line.long 0x00 "GWIDAUAS1_4,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "IDAUASi,Incremental Data Area Used Size of RX Descriptor Chain i"
group.long 0x848++0x03
line.long 0x00 "GWIDAUAS2_4,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "IDAUASi,Incremental Data Area Used Size of RX Descriptor Chain i"
group.long 0x84C++0x03
line.long 0x00 "GWIDAUAS3_4,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "IDAUASi,Incremental Data Area Used Size of RX Descriptor Chain i"
group.long 0x850++0x03
line.long 0x00 "GWIDAUAS4_4,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "IDAUASi,Incremental Data Area Used Size of RX Descriptor Chain i"
group.long 0x854++0x03
line.long 0x00 "GWIDAUAS5_4,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "IDAUASi,Incremental Data Area Used Size of RX Descriptor Chain i"
group.long 0x858++0x03
line.long 0x00 "GWIDAUAS6_4,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "IDAUASi,Incremental Data Area Used Size of RX Descriptor Chain i"
group.long 0x85C++0x03
line.long 0x00 "GWIDAUAS7_4,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "IDAUASi,Incremental Data Area Used Size of RX Descriptor Chain i"
group.long 0x880++0x03
line.long 0x00 "GWIDASM0_4,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "IDASi,Incremental Data Area Size of RX Descriptor Chain i"
group.long 0x884++0x03
line.long 0x00 "GWIDASM1_4,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "IDASi,Incremental Data Area Size of RX Descriptor Chain i"
group.long 0x888++0x03
line.long 0x00 "GWIDASM2_4,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "IDASi,Incremental Data Area Size of RX Descriptor Chain i"
group.long 0x88C++0x03
line.long 0x00 "GWIDASM3_4,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "IDASi,Incremental Data Area Size of RX Descriptor Chain i"
group.long 0x890++0x03
line.long 0x00 "GWIDASM4_4,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "IDASi,Incremental Data Area Size of RX Descriptor Chain i"
group.long 0x894++0x03
line.long 0x00 "GWIDASM5_4,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "IDASi,Incremental Data Area Size of RX Descriptor Chain i"
group.long 0x898++0x03
line.long 0x00 "GWIDASM6_4,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "IDASi,Incremental Data Area Size of RX Descriptor Chain i"
group.long 0x89C++0x03
line.long 0x00 "GWIDASM7_4,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "IDASi,Incremental Data Area Size of RX Descriptor Chain i"
group.long 0x900++0x03
line.long 0x00 "GWIDASAM00_4,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
hexmask.long.byte 0x00 0.--7. 1. "IDASAUPi,Incremental Data Area Start Address Upper Part of RX Descriptor Chain i"
group.long 0x904++0x03
line.long 0x00 "GWIDASAM10_4,"
hexmask.long 0x00 0.--31. 1. "IDASADPi,Incremental Data Area Start Address Downer Part of RX Descriptor Chain i"
group.long 0x908++0x03
line.long 0x00 "GWIDASAM01_4,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
hexmask.long.byte 0x00 0.--7. 1. "IDASAUPi,Incremental Data Area Start Address Upper Part of RX Descriptor Chain i"
group.long 0x90C++0x03
line.long 0x00 "GWIDASAM11_4,"
hexmask.long 0x00 0.--31. 1. "IDASADPi,Incremental Data Area Start Address Downer Part of RX Descriptor Chain i"
group.long 0x910++0x03
line.long 0x00 "GWIDASAM02_4,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
hexmask.long.byte 0x00 0.--7. 1. "IDASAUPi,Incremental Data Area Start Address Upper Part of RX Descriptor Chain i"
group.long 0x914++0x03
line.long 0x00 "GWIDASAM12_4,"
hexmask.long 0x00 0.--31. 1. "IDASADPi,Incremental Data Area Start Address Downer Part of RX Descriptor Chain i"
group.long 0x918++0x03
line.long 0x00 "GWIDASAM03_4,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
hexmask.long.byte 0x00 0.--7. 1. "IDASAUPi,Incremental Data Area Start Address Upper Part of RX Descriptor Chain i"
group.long 0x91C++0x03
line.long 0x00 "GWIDASAM13_4,"
hexmask.long 0x00 0.--31. 1. "IDASADPi,Incremental Data Area Start Address Downer Part of RX Descriptor Chain i"
group.long 0x920++0x03
line.long 0x00 "GWIDASAM04_4,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
hexmask.long.byte 0x00 0.--7. 1. "IDASAUPi,Incremental Data Area Start Address Upper Part of RX Descriptor Chain i"
group.long 0x924++0x03
line.long 0x00 "GWIDASAM14_4,"
hexmask.long 0x00 0.--31. 1. "IDASADPi,Incremental Data Area Start Address Downer Part of RX Descriptor Chain i"
group.long 0x928++0x03
line.long 0x00 "GWIDASAM05_4,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
hexmask.long.byte 0x00 0.--7. 1. "IDASAUPi,Incremental Data Area Start Address Upper Part of RX Descriptor Chain i"
group.long 0x92C++0x03
line.long 0x00 "GWIDASAM15_4,"
hexmask.long 0x00 0.--31. 1. "IDASADPi,Incremental Data Area Start Address Downer Part of RX Descriptor Chain i"
group.long 0x930++0x03
line.long 0x00 "GWIDASAM06_4,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
hexmask.long.byte 0x00 0.--7. 1. "IDASAUPi,Incremental Data Area Start Address Upper Part of RX Descriptor Chain i"
group.long 0x934++0x03
line.long 0x00 "GWIDASAM16_4,"
hexmask.long 0x00 0.--31. 1. "IDASADPi,Incremental Data Area Start Address Downer Part of RX Descriptor Chain i"
group.long 0x938++0x03
line.long 0x00 "GWIDASAM07_4,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
hexmask.long.byte 0x00 0.--7. 1. "IDASAUPi,Incremental Data Area Start Address Upper Part of RX Descriptor Chain i"
group.long 0x93C++0x03
line.long 0x00 "GWIDASAM17_4,"
hexmask.long 0x00 0.--31. 1. "IDASADPi,Incremental Data Area Start Address Downer Part of RX Descriptor Chain i"
group.long 0x980++0x03
line.long 0x00 "GWIDACAM00_4,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
hexmask.long.byte 0x00 0.--7. 1. "IDACAUPi,Incremental Data Area Current Address Upper Part of RX Descriptor Chain i"
group.long 0x984++0x03
line.long 0x00 "GWIDACAM10_4,"
hexmask.long 0x00 0.--31. 1. "IDACADPi,Incremental Data Area Current Address Downer Part of RX Descriptor Chain i"
group.long 0x988++0x03
line.long 0x00 "GWIDACAM01_4,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
hexmask.long.byte 0x00 0.--7. 1. "IDACAUPi,Incremental Data Area Current Address Upper Part of RX Descriptor Chain i"
group.long 0x98C++0x03
line.long 0x00 "GWIDACAM11_4,"
hexmask.long 0x00 0.--31. 1. "IDACADPi,Incremental Data Area Current Address Downer Part of RX Descriptor Chain i"
group.long 0x990++0x03
line.long 0x00 "GWIDACAM02_4,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
hexmask.long.byte 0x00 0.--7. 1. "IDACAUPi,Incremental Data Area Current Address Upper Part of RX Descriptor Chain i"
group.long 0x994++0x03
line.long 0x00 "GWIDACAM12_4,"
hexmask.long 0x00 0.--31. 1. "IDACADPi,Incremental Data Area Current Address Downer Part of RX Descriptor Chain i"
group.long 0x998++0x03
line.long 0x00 "GWIDACAM03_4,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
hexmask.long.byte 0x00 0.--7. 1. "IDACAUPi,Incremental Data Area Current Address Upper Part of RX Descriptor Chain i"
group.long 0x99C++0x03
line.long 0x00 "GWIDACAM13_4,"
hexmask.long 0x00 0.--31. 1. "IDACADPi,Incremental Data Area Current Address Downer Part of RX Descriptor Chain i"
group.long 0x9A0++0x03
line.long 0x00 "GWIDACAM04_4,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
hexmask.long.byte 0x00 0.--7. 1. "IDACAUPi,Incremental Data Area Current Address Upper Part of RX Descriptor Chain i"
group.long 0x9A4++0x03
line.long 0x00 "GWIDACAM14_4,"
hexmask.long 0x00 0.--31. 1. "IDACADPi,Incremental Data Area Current Address Downer Part of RX Descriptor Chain i"
group.long 0x9A8++0x03
line.long 0x00 "GWIDACAM05_4,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
hexmask.long.byte 0x00 0.--7. 1. "IDACAUPi,Incremental Data Area Current Address Upper Part of RX Descriptor Chain i"
group.long 0x9AC++0x03
line.long 0x00 "GWIDACAM15_4,"
hexmask.long 0x00 0.--31. 1. "IDACADPi,Incremental Data Area Current Address Downer Part of RX Descriptor Chain i"
group.long 0x9B0++0x03
line.long 0x00 "GWIDACAM06_4,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
hexmask.long.byte 0x00 0.--7. 1. "IDACAUPi,Incremental Data Area Current Address Upper Part of RX Descriptor Chain i"
group.long 0x9B4++0x03
line.long 0x00 "GWIDACAM16_4,"
hexmask.long 0x00 0.--31. 1. "IDACADPi,Incremental Data Area Current Address Downer Part of RX Descriptor Chain i"
group.long 0x9B8++0x03
line.long 0x00 "GWIDACAM07_4,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
hexmask.long.byte 0x00 0.--7. 1. "IDACAUPi,Incremental Data Area Current Address Upper Part of RX Descriptor Chain i"
group.long 0x9BC++0x03
line.long 0x00 "GWIDACAM17_4,"
hexmask.long 0x00 0.--31. 1. "IDACADPi,Incremental Data Area Current Address Downer Part of RX Descriptor Chain i"
group.long 0xA00++0x03
line.long 0x00 "GWGRLC4,"
hexmask.long.word 0x00 18.--31. 1. "RSV,Reserved area"
bitfld.long 0x00 17. "GRLULRS,Global Rate Limiter Upper Limit Reached Status Set conditions: HW: When the global rate limit reaches its upper limit GWGRLULC.GRLUL this bit gets set Clear conditions: HW: Being in RESET mode will clear this register" "0,1"
bitfld.long 0x00 16. "GRLE,Global Rate Limiter Enable" "0,1"
hexmask.long.word 0x00 0.--15. 1. "GRLIV,Global Rate Limiter Incremental Value"
group.long 0xA04++0x03
line.long 0x00 "GWGRLULC4,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "GRLUL,Global Rate Limiter Upper Limit Functions: Set the maximum number of credits in bit rate limiter i can accumulate before stopping"
group.long 0xA80++0x03
line.long 0x00 "GWRLC0_4,"
hexmask.long.word 0x00 17.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 16. "RLEi,Rate limiter enable i" "0,1"
rbitfld.long 0x00 12.--15. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "RLIVi,Rate limiter incremental value for rate limiter i"
group.long 0xA84++0x03
line.long 0x00 "GWRLULC0_4,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "RLULi,Rate limiter upper limit for rate limiter i"
group.long 0xA88++0x03
line.long 0x00 "GWRLC1_4,"
hexmask.long.word 0x00 17.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 16. "RLEi,Rate limiter enable i" "0,1"
rbitfld.long 0x00 12.--15. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "RLIVi,Rate limiter incremental value for rate limiter i"
group.long 0xA8C++0x03
line.long 0x00 "GWRLULC1_4,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "RLULi,Rate limiter upper limit for rate limiter i"
group.long 0xA90++0x03
line.long 0x00 "GWRLC2_4,"
hexmask.long.word 0x00 17.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 16. "RLEi,Rate limiter enable i" "0,1"
rbitfld.long 0x00 12.--15. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "RLIVi,Rate limiter incremental value for rate limiter i"
group.long 0xA94++0x03
line.long 0x00 "GWRLULC2_4,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "RLULi,Rate limiter upper limit for rate limiter i"
group.long 0xA98++0x03
line.long 0x00 "GWRLC3_4,"
hexmask.long.word 0x00 17.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 16. "RLEi,Rate limiter enable i" "0,1"
rbitfld.long 0x00 12.--15. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "RLIVi,Rate limiter incremental value for rate limiter i"
group.long 0xA9C++0x03
line.long 0x00 "GWRLULC3_4,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "RLULi,Rate limiter upper limit for rate limiter i"
group.long 0xAA0++0x03
line.long 0x00 "GWRLC4_4,"
hexmask.long.word 0x00 17.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 16. "RLEi,Rate limiter enable i" "0,1"
rbitfld.long 0x00 12.--15. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "RLIVi,Rate limiter incremental value for rate limiter i"
group.long 0xAA4++0x03
line.long 0x00 "GWRLULC4_4,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "RLULi,Rate limiter upper limit for rate limiter i"
group.long 0xAA8++0x03
line.long 0x00 "GWRLC5_4,"
hexmask.long.word 0x00 17.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 16. "RLEi,Rate limiter enable i" "0,1"
rbitfld.long 0x00 12.--15. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "RLIVi,Rate limiter incremental value for rate limiter i"
group.long 0xAAC++0x03
line.long 0x00 "GWRLULC5_4,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "RLULi,Rate limiter upper limit for rate limiter i"
group.long 0xAB0++0x03
line.long 0x00 "GWRLC6_4,"
hexmask.long.word 0x00 17.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 16. "RLEi,Rate limiter enable i" "0,1"
rbitfld.long 0x00 12.--15. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "RLIVi,Rate limiter incremental value for rate limiter i"
group.long 0xAB4++0x03
line.long 0x00 "GWRLULC6_4,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "RLULi,Rate limiter upper limit for rate limiter i"
group.long 0xAB8++0x03
line.long 0x00 "GWRLC7_4,"
hexmask.long.word 0x00 17.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 16. "RLEi,Rate limiter enable i" "0,1"
rbitfld.long 0x00 12.--15. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "RLIVi,Rate limiter incremental value for rate limiter i"
group.long 0xABC++0x03
line.long 0x00 "GWRLULC7_4,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "RLULi,Rate limiter upper limit for rate limiter i"
group.long 0xAC0++0x03
line.long 0x00 "GWRLC8_4,"
hexmask.long.word 0x00 17.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 16. "RLEi,Rate limiter enable i" "0,1"
rbitfld.long 0x00 12.--15. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "RLIVi,Rate limiter incremental value for rate limiter i"
group.long 0xAC4++0x03
line.long 0x00 "GWRLULC8_4,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "RLULi,Rate limiter upper limit for rate limiter i"
group.long 0xAC8++0x03
line.long 0x00 "GWRLC9_4,"
hexmask.long.word 0x00 17.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 16. "RLEi,Rate limiter enable i" "0,1"
rbitfld.long 0x00 12.--15. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "RLIVi,Rate limiter incremental value for rate limiter i"
group.long 0xACC++0x03
line.long 0x00 "GWRLULC9_4,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "RLULi,Rate limiter upper limit for rate limiter i"
group.long 0xAD0++0x03
line.long 0x00 "GWRLC10_4,"
hexmask.long.word 0x00 17.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 16. "RLEi,Rate limiter enable i" "0,1"
rbitfld.long 0x00 12.--15. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "RLIVi,Rate limiter incremental value for rate limiter i"
group.long 0xAD4++0x03
line.long 0x00 "GWRLULC10_4,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "RLULi,Rate limiter upper limit for rate limiter i"
group.long 0xAD8++0x03
line.long 0x00 "GWRLC11_4,"
hexmask.long.word 0x00 17.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 16. "RLEi,Rate limiter enable i" "0,1"
rbitfld.long 0x00 12.--15. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "RLIVi,Rate limiter incremental value for rate limiter i"
group.long 0xADC++0x03
line.long 0x00 "GWRLULC11_4,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "RLULi,Rate limiter upper limit for rate limiter i"
group.long 0xAE0++0x03
line.long 0x00 "GWRLC12_4,"
hexmask.long.word 0x00 17.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 16. "RLEi,Rate limiter enable i" "0,1"
rbitfld.long 0x00 12.--15. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "RLIVi,Rate limiter incremental value for rate limiter i"
group.long 0xAE4++0x03
line.long 0x00 "GWRLULC12_4,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "RLULi,Rate limiter upper limit for rate limiter i"
group.long 0xAE8++0x03
line.long 0x00 "GWRLC13_4,"
hexmask.long.word 0x00 17.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 16. "RLEi,Rate limiter enable i" "0,1"
rbitfld.long 0x00 12.--15. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "RLIVi,Rate limiter incremental value for rate limiter i"
group.long 0xAEC++0x03
line.long 0x00 "GWRLULC13_4,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "RLULi,Rate limiter upper limit for rate limiter i"
group.long 0xAF0++0x03
line.long 0x00 "GWRLC14_4,"
hexmask.long.word 0x00 17.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 16. "RLEi,Rate limiter enable i" "0,1"
rbitfld.long 0x00 12.--15. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "RLIVi,Rate limiter incremental value for rate limiter i"
group.long 0xAF4++0x03
line.long 0x00 "GWRLULC14_4,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "RLULi,Rate limiter upper limit for rate limiter i"
group.long 0xAF8++0x03
line.long 0x00 "GWRLC15_4,"
hexmask.long.word 0x00 17.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 16. "RLEi,Rate limiter enable i" "0,1"
rbitfld.long 0x00 12.--15. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "RLIVi,Rate limiter incremental value for rate limiter i"
group.long 0xAFC++0x03
line.long 0x00 "GWRLULC15_4,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "RLULi,Rate limiter upper limit for rate limiter i"
group.long 0xB00++0x03
line.long 0x00 "GWRLC16_4,"
hexmask.long.word 0x00 17.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 16. "RLEi,Rate limiter enable i" "0,1"
rbitfld.long 0x00 12.--15. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "RLIVi,Rate limiter incremental value for rate limiter i"
group.long 0xB04++0x03
line.long 0x00 "GWRLULC16_4,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "RLULi,Rate limiter upper limit for rate limiter i"
group.long 0xB08++0x03
line.long 0x00 "GWRLC17_4,"
hexmask.long.word 0x00 17.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 16. "RLEi,Rate limiter enable i" "0,1"
rbitfld.long 0x00 12.--15. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "RLIVi,Rate limiter incremental value for rate limiter i"
group.long 0xB0C++0x03
line.long 0x00 "GWRLULC17_4,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "RLULi,Rate limiter upper limit for rate limiter i"
group.long 0xB10++0x03
line.long 0x00 "GWRLC18_4,"
hexmask.long.word 0x00 17.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 16. "RLEi,Rate limiter enable i" "0,1"
rbitfld.long 0x00 12.--15. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "RLIVi,Rate limiter incremental value for rate limiter i"
group.long 0xB14++0x03
line.long 0x00 "GWRLULC18_4,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "RLULi,Rate limiter upper limit for rate limiter i"
group.long 0xB18++0x03
line.long 0x00 "GWRLC19_4,"
hexmask.long.word 0x00 17.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 16. "RLEi,Rate limiter enable i" "0,1"
rbitfld.long 0x00 12.--15. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "RLIVi,Rate limiter incremental value for rate limiter i"
group.long 0xB1C++0x03
line.long 0x00 "GWRLULC19_4,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "RLULi,Rate limiter upper limit for rate limiter i"
group.long 0xB20++0x03
line.long 0x00 "GWRLC20_4,"
hexmask.long.word 0x00 17.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 16. "RLEi,Rate limiter enable i" "0,1"
rbitfld.long 0x00 12.--15. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "RLIVi,Rate limiter incremental value for rate limiter i"
group.long 0xB24++0x03
line.long 0x00 "GWRLULC20_4,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "RLULi,Rate limiter upper limit for rate limiter i"
group.long 0xB28++0x03
line.long 0x00 "GWRLC21_4,"
hexmask.long.word 0x00 17.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 16. "RLEi,Rate limiter enable i" "0,1"
rbitfld.long 0x00 12.--15. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "RLIVi,Rate limiter incremental value for rate limiter i"
group.long 0xB2C++0x03
line.long 0x00 "GWRLULC21_4,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "RLULi,Rate limiter upper limit for rate limiter i"
group.long 0xB30++0x03
line.long 0x00 "GWRLC22_4,"
hexmask.long.word 0x00 17.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 16. "RLEi,Rate limiter enable i" "0,1"
rbitfld.long 0x00 12.--15. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "RLIVi,Rate limiter incremental value for rate limiter i"
group.long 0xB34++0x03
line.long 0x00 "GWRLULC22_4,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "RLULi,Rate limiter upper limit for rate limiter i"
group.long 0xB38++0x03
line.long 0x00 "GWRLC23_4,"
hexmask.long.word 0x00 17.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 16. "RLEi,Rate limiter enable i" "0,1"
rbitfld.long 0x00 12.--15. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "RLIVi,Rate limiter incremental value for rate limiter i"
group.long 0xB3C++0x03
line.long 0x00 "GWRLULC23_4,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "RLULi,Rate limiter upper limit for rate limiter i"
group.long 0xB40++0x03
line.long 0x00 "GWRLC24_4,"
hexmask.long.word 0x00 17.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 16. "RLEi,Rate limiter enable i" "0,1"
rbitfld.long 0x00 12.--15. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "RLIVi,Rate limiter incremental value for rate limiter i"
group.long 0xB44++0x03
line.long 0x00 "GWRLULC24_4,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "RLULi,Rate limiter upper limit for rate limiter i"
group.long 0xB48++0x03
line.long 0x00 "GWRLC25_4,"
hexmask.long.word 0x00 17.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 16. "RLEi,Rate limiter enable i" "0,1"
rbitfld.long 0x00 12.--15. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "RLIVi,Rate limiter incremental value for rate limiter i"
group.long 0xB4C++0x03
line.long 0x00 "GWRLULC25_4,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "RLULi,Rate limiter upper limit for rate limiter i"
group.long 0xB50++0x03
line.long 0x00 "GWRLC26_4,"
hexmask.long.word 0x00 17.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 16. "RLEi,Rate limiter enable i" "0,1"
rbitfld.long 0x00 12.--15. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "RLIVi,Rate limiter incremental value for rate limiter i"
group.long 0xB54++0x03
line.long 0x00 "GWRLULC26_4,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "RLULi,Rate limiter upper limit for rate limiter i"
group.long 0xB58++0x03
line.long 0x00 "GWRLC27_4,"
hexmask.long.word 0x00 17.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 16. "RLEi,Rate limiter enable i" "0,1"
rbitfld.long 0x00 12.--15. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "RLIVi,Rate limiter incremental value for rate limiter i"
group.long 0xB5C++0x03
line.long 0x00 "GWRLULC27_4,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "RLULi,Rate limiter upper limit for rate limiter i"
group.long 0xB60++0x03
line.long 0x00 "GWRLC28_4,"
hexmask.long.word 0x00 17.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 16. "RLEi,Rate limiter enable i" "0,1"
rbitfld.long 0x00 12.--15. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "RLIVi,Rate limiter incremental value for rate limiter i"
group.long 0xB64++0x03
line.long 0x00 "GWRLULC28_4,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "RLULi,Rate limiter upper limit for rate limiter i"
group.long 0xB68++0x03
line.long 0x00 "GWRLC29_4,"
hexmask.long.word 0x00 17.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 16. "RLEi,Rate limiter enable i" "0,1"
rbitfld.long 0x00 12.--15. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "RLIVi,Rate limiter incremental value for rate limiter i"
group.long 0xB6C++0x03
line.long 0x00 "GWRLULC29_4,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "RLULi,Rate limiter upper limit for rate limiter i"
group.long 0xB70++0x03
line.long 0x00 "GWRLC30_4,"
hexmask.long.word 0x00 17.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 16. "RLEi,Rate limiter enable i" "0,1"
rbitfld.long 0x00 12.--15. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "RLIVi,Rate limiter incremental value for rate limiter i"
group.long 0xB74++0x03
line.long 0x00 "GWRLULC30_4,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "RLULi,Rate limiter upper limit for rate limiter i"
group.long 0xB78++0x03
line.long 0x00 "GWRLC31_4,"
hexmask.long.word 0x00 17.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 16. "RLEi,Rate limiter enable i" "0,1"
rbitfld.long 0x00 12.--15. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "RLIVi,Rate limiter incremental value for rate limiter i"
group.long 0xB7C++0x03
line.long 0x00 "GWRLULC31_4,"
hexmask.long.byte 0x00 24.--31. 1. "RSV,Reserved area"
hexmask.long.tbyte 0x00 0.--23. 1. "RLULi,Rate limiter upper limit for rate limiter i"
group.long 0xB80++0x03
line.long 0x00 "GWIDPC4,"
hexmask.long.tbyte 0x00 10.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--9. 1. "IDPV,Interrupt delay prescaler value Functions: This register is used to create an internal clock"
group.long 0xC00++0x03
line.long 0x00 "GWIDC0_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xC04++0x03
line.long 0x00 "GWIDC1_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xC08++0x03
line.long 0x00 "GWIDC2_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xC0C++0x03
line.long 0x00 "GWIDC3_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xC10++0x03
line.long 0x00 "GWIDC4_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xC14++0x03
line.long 0x00 "GWIDC5_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xC18++0x03
line.long 0x00 "GWIDC6_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xC1C++0x03
line.long 0x00 "GWIDC7_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xC20++0x03
line.long 0x00 "GWIDC8_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xC24++0x03
line.long 0x00 "GWIDC9_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xC28++0x03
line.long 0x00 "GWIDC10_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xC2C++0x03
line.long 0x00 "GWIDC11_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xC30++0x03
line.long 0x00 "GWIDC12_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xC34++0x03
line.long 0x00 "GWIDC13_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xC38++0x03
line.long 0x00 "GWIDC14_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xC3C++0x03
line.long 0x00 "GWIDC15_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xC40++0x03
line.long 0x00 "GWIDC16_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xC44++0x03
line.long 0x00 "GWIDC17_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xC48++0x03
line.long 0x00 "GWIDC18_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xC4C++0x03
line.long 0x00 "GWIDC19_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xC50++0x03
line.long 0x00 "GWIDC20_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xC54++0x03
line.long 0x00 "GWIDC21_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xC58++0x03
line.long 0x00 "GWIDC22_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xC5C++0x03
line.long 0x00 "GWIDC23_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xC60++0x03
line.long 0x00 "GWIDC24_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xC64++0x03
line.long 0x00 "GWIDC25_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xC68++0x03
line.long 0x00 "GWIDC26_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xC6C++0x03
line.long 0x00 "GWIDC27_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xC70++0x03
line.long 0x00 "GWIDC28_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xC74++0x03
line.long 0x00 "GWIDC29_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xC78++0x03
line.long 0x00 "GWIDC30_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xC7C++0x03
line.long 0x00 "GWIDC31_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xC80++0x03
line.long 0x00 "GWIDC32_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xC84++0x03
line.long 0x00 "GWIDC33_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xC88++0x03
line.long 0x00 "GWIDC34_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xC8C++0x03
line.long 0x00 "GWIDC35_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xC90++0x03
line.long 0x00 "GWIDC36_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xC94++0x03
line.long 0x00 "GWIDC37_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xC98++0x03
line.long 0x00 "GWIDC38_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xC9C++0x03
line.long 0x00 "GWIDC39_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xCA0++0x03
line.long 0x00 "GWIDC40_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xCA4++0x03
line.long 0x00 "GWIDC41_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xCA8++0x03
line.long 0x00 "GWIDC42_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xCAC++0x03
line.long 0x00 "GWIDC43_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xCB0++0x03
line.long 0x00 "GWIDC44_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xCB4++0x03
line.long 0x00 "GWIDC45_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xCB8++0x03
line.long 0x00 "GWIDC46_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xCBC++0x03
line.long 0x00 "GWIDC47_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xCC0++0x03
line.long 0x00 "GWIDC48_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xCC4++0x03
line.long 0x00 "GWIDC49_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xCC8++0x03
line.long 0x00 "GWIDC50_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xCCC++0x03
line.long 0x00 "GWIDC51_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xCD0++0x03
line.long 0x00 "GWIDC52_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xCD4++0x03
line.long 0x00 "GWIDC53_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xCD8++0x03
line.long 0x00 "GWIDC54_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xCDC++0x03
line.long 0x00 "GWIDC55_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xCE0++0x03
line.long 0x00 "GWIDC56_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xCE4++0x03
line.long 0x00 "GWIDC57_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xCE8++0x03
line.long 0x00 "GWIDC58_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xCEC++0x03
line.long 0x00 "GWIDC59_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xCF0++0x03
line.long 0x00 "GWIDC60_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xCF4++0x03
line.long 0x00 "GWIDC61_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xCF8++0x03
line.long 0x00 "GWIDC62_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xCFC++0x03
line.long 0x00 "GWIDC63_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xD00++0x03
line.long 0x00 "GWIDC64_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xD04++0x03
line.long 0x00 "GWIDC65_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xD08++0x03
line.long 0x00 "GWIDC66_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xD0C++0x03
line.long 0x00 "GWIDC67_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xD10++0x03
line.long 0x00 "GWIDC68_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xD14++0x03
line.long 0x00 "GWIDC69_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xD18++0x03
line.long 0x00 "GWIDC70_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xD1C++0x03
line.long 0x00 "GWIDC71_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xD20++0x03
line.long 0x00 "GWIDC72_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xD24++0x03
line.long 0x00 "GWIDC73_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xD28++0x03
line.long 0x00 "GWIDC74_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xD2C++0x03
line.long 0x00 "GWIDC75_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xD30++0x03
line.long 0x00 "GWIDC76_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xD34++0x03
line.long 0x00 "GWIDC77_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xD38++0x03
line.long 0x00 "GWIDC78_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xD3C++0x03
line.long 0x00 "GWIDC79_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xD40++0x03
line.long 0x00 "GWIDC80_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xD44++0x03
line.long 0x00 "GWIDC81_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xD48++0x03
line.long 0x00 "GWIDC82_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xD4C++0x03
line.long 0x00 "GWIDC83_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xD50++0x03
line.long 0x00 "GWIDC84_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xD54++0x03
line.long 0x00 "GWIDC85_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xD58++0x03
line.long 0x00 "GWIDC86_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xD5C++0x03
line.long 0x00 "GWIDC87_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xD60++0x03
line.long 0x00 "GWIDC88_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xD64++0x03
line.long 0x00 "GWIDC89_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xD68++0x03
line.long 0x00 "GWIDC90_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xD6C++0x03
line.long 0x00 "GWIDC91_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xD70++0x03
line.long 0x00 "GWIDC92_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xD74++0x03
line.long 0x00 "GWIDC93_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xD78++0x03
line.long 0x00 "GWIDC94_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xD7C++0x03
line.long 0x00 "GWIDC95_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xD80++0x03
line.long 0x00 "GWIDC96_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xD84++0x03
line.long 0x00 "GWIDC97_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xD88++0x03
line.long 0x00 "GWIDC98_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xD8C++0x03
line.long 0x00 "GWIDC99_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xD90++0x03
line.long 0x00 "GWIDC100_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xD94++0x03
line.long 0x00 "GWIDC101_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xD98++0x03
line.long 0x00 "GWIDC102_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xD9C++0x03
line.long 0x00 "GWIDC103_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xDA0++0x03
line.long 0x00 "GWIDC104_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xDA4++0x03
line.long 0x00 "GWIDC105_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xDA8++0x03
line.long 0x00 "GWIDC106_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xDAC++0x03
line.long 0x00 "GWIDC107_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xDB0++0x03
line.long 0x00 "GWIDC108_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xDB4++0x03
line.long 0x00 "GWIDC109_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xDB8++0x03
line.long 0x00 "GWIDC110_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xDBC++0x03
line.long 0x00 "GWIDC111_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xDC0++0x03
line.long 0x00 "GWIDC112_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xDC4++0x03
line.long 0x00 "GWIDC113_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xDC8++0x03
line.long 0x00 "GWIDC114_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xDCC++0x03
line.long 0x00 "GWIDC115_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xDD0++0x03
line.long 0x00 "GWIDC116_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xDD4++0x03
line.long 0x00 "GWIDC117_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xDD8++0x03
line.long 0x00 "GWIDC118_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xDDC++0x03
line.long 0x00 "GWIDC119_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xDE0++0x03
line.long 0x00 "GWIDC120_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xDE4++0x03
line.long 0x00 "GWIDC121_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xDE8++0x03
line.long 0x00 "GWIDC122_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xDEC++0x03
line.long 0x00 "GWIDC123_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xDF0++0x03
line.long 0x00 "GWIDC124_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xDF4++0x03
line.long 0x00 "GWIDC125_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xDF8++0x03
line.long 0x00 "GWIDC126_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0xDFC++0x03
line.long 0x00 "GWIDC127_4,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--11. 1. "IDVi,Interrupt delay value i Functions: Configures the delay between the interrupt status flag GWDISi.DISt setting and the actual interrupt event in us"
group.long 0x1000++0x03
line.long 0x00 "GWRDCN4,"
hexmask.long 0x00 0.--31. 1. "RDN,Received Data Number Functions: This register counts data that has been received by GWCA (data aborted by AXI error are accounted here)"
group.long 0x1004++0x03
line.long 0x00 "GWTDCN4,"
hexmask.long 0x00 0.--31. 1. "TDN,Transmitted Data Number Functions: This register counts data that has been transmit by GWCA (this includes data transmitted with an error and frames smaller than 32 bytes)"
group.long 0x1008++0x03
line.long 0x00 "GWTSCN4,"
hexmask.long 0x00 0.--31. 1. "TN,Timestamp Number Functions: This register counts timestamp processed by GWCA (TS lost because of AXI errors are accounted here) Clear conditions: HW: Being in RESET mode will clear this register"
group.long 0x100C++0x03
line.long 0x00 "GWTSOVFECN4,"
hexmask.long.word 0x00 16.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--15. 1. "TSOVFEN,TimeStamp OVerFlow Error Number Functions: This register counts the number of timestamps lost because of timestamp RAM overflow"
group.long 0x1010++0x03
line.long 0x00 "GWUSMFSECN4,"
hexmask.long.word 0x00 16.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--15. 1. "USMFSEN,Under Switch Minimum Frame Size Error Number Functions: This register counts the number of transmit data lost because of under switch minimum size error"
group.long 0x1014++0x03
line.long 0x00 "GWTFECN4,"
hexmask.long.word 0x00 16.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--15. 1. "TFEN,TAG Filtering Error Number Functions: This register counts the number of transmit data lost because of TAG filtering"
group.long 0x1018++0x03
line.long 0x00 "GWSEQECN4,"
hexmask.long.word 0x00 16.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--15. 1. "SEQEN,SEQuence Error Number Functions: This register counts the number of transmit data lost because of a sequence error"
group.long 0x1020++0x03
line.long 0x00 "GWTXDNECN4,"
hexmask.long.word 0x00 16.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--15. 1. "TXDNEN,TX Descriptor Number Error Number Functions: This register counts the number of transmit data lost because of a TX Descriptor Number Error"
group.long 0x1024++0x03
line.long 0x00 "GWFSECN4,"
hexmask.long.word 0x00 16.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--15. 1. "FSEN,Frame Size Error Number Functions: This register counts the number of receive data lost because of a Frame Size Error"
group.long 0x1028++0x03
line.long 0x00 "GWTDFECN4,"
hexmask.long.word 0x00 16.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--15. 1. "TDFEN,Timestamp Descriptor Full Error Number Functions: This register counts the number of timestamps lost because of a Timestamp Descriptor Full Error"
group.long 0x102C++0x03
line.long 0x00 "GWTSDNECN4,"
hexmask.long.word 0x00 16.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--15. 1. "TSDNEN,Timestamp Descriptor Number Error Number Functions: This register counts the number of timestamps lost because of a Timestamp Descriptor Number Error"
group.long 0x1030++0x03
line.long 0x00 "GWDQOECN4,"
hexmask.long.word 0x00 16.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--15. 1. "DQOEN,Descriptor Queue Overflow Error Number Functions: This register counts the number of receive data lost because of a Descriptor Queue Overflow Error"
group.long 0x1034++0x03
line.long 0x00 "GWDQSECN4,"
hexmask.long.word 0x00 16.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--15. 1. "DQSEN,Descriptor Queue Security Error Number Functions: This register counts the number of receive data lost because of a Descriptor Queue Security Error"
group.long 0x1038++0x03
line.long 0x00 "GWDFECN4,"
hexmask.long.word 0x00 16.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--15. 1. "DFEN,Descriptor Full Error Number Functions: This register counts the number of receive data lost because of a Descriptor Full Error"
group.long 0x103C++0x03
line.long 0x00 "GWDSECN4,"
hexmask.long.word 0x00 16.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--15. 1. "DSEN,Descriptor Security Error Number Functions: This register counts the number of receive data lost because of a Descriptor Security Error"
group.long 0x1040++0x03
line.long 0x00 "GWDSZECN4,"
hexmask.long.word 0x00 16.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--15. 1. "DSZEN,Data SiZe Error Number Functions: This register counts the number of receive data lost because of a Data Size Error"
group.long 0x1044++0x03
line.long 0x00 "GWDCTECN4,"
hexmask.long.word 0x00 16.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--15. 1. "DCTEN,Descriptor Chain Type Error Number Functions: This register counts the number of receive data lost because of a Descriptor Chain Type Error"
group.long 0x1048++0x03
line.long 0x00 "GWRXDNECN4,"
hexmask.long.word 0x00 16.--31. 1. "RSV,Reserved area"
hexmask.long.word 0x00 0.--15. 1. "RXDNEN,RX Descriptor Number Error Number Functions: This register counts the number of receive data lost because of a RX Descriptor Number Error"
group.long 0x1100++0x03
line.long 0x00 "GWDIS0_4,"
bitfld.long 0x00 31. "DIS31,Data Interrupt Status t" "0,1"
bitfld.long 0x00 30. "DIS30,Data Interrupt Status t" "0,1"
bitfld.long 0x00 29. "DIS29,Data Interrupt Status t" "0,1"
bitfld.long 0x00 28. "DIS28,Data Interrupt Status t" "0,1"
bitfld.long 0x00 27. "DIS27,Data Interrupt Status t" "0,1"
bitfld.long 0x00 26. "DIS26,Data Interrupt Status t" "0,1"
bitfld.long 0x00 25. "DIS25,Data Interrupt Status t" "0,1"
bitfld.long 0x00 24. "DIS24,Data Interrupt Status t" "0,1"
bitfld.long 0x00 23. "DIS23,Data Interrupt Status t" "0,1"
newline
bitfld.long 0x00 22. "DIS22,Data Interrupt Status t" "0,1"
bitfld.long 0x00 21. "DIS21,Data Interrupt Status t" "0,1"
bitfld.long 0x00 20. "DIS20,Data Interrupt Status t" "0,1"
bitfld.long 0x00 19. "DIS19,Data Interrupt Status t" "0,1"
bitfld.long 0x00 18. "DIS18,Data Interrupt Status t" "0,1"
bitfld.long 0x00 17. "DIS17,Data Interrupt Status t" "0,1"
bitfld.long 0x00 16. "DIS16,Data Interrupt Status t" "0,1"
bitfld.long 0x00 15. "DIS15,Data Interrupt Status t" "0,1"
bitfld.long 0x00 14. "DIS14,Data Interrupt Status t" "0,1"
newline
bitfld.long 0x00 13. "DIS13,Data Interrupt Status t" "0,1"
bitfld.long 0x00 12. "DIS12,Data Interrupt Status t" "0,1"
bitfld.long 0x00 11. "DIS11,Data Interrupt Status t" "0,1"
bitfld.long 0x00 10. "DIS10,Data Interrupt Status t" "0,1"
bitfld.long 0x00 9. "DIS9,Data Interrupt Status t" "0,1"
bitfld.long 0x00 8. "DIS8,Data Interrupt Status t" "0,1"
bitfld.long 0x00 7. "DIS7,Data Interrupt Status t" "0,1"
bitfld.long 0x00 6. "DIS6,Data Interrupt Status t" "0,1"
bitfld.long 0x00 5. "DIS5,Data Interrupt Status t" "0,1"
newline
bitfld.long 0x00 4. "DIS4,Data Interrupt Status t" "0,1"
bitfld.long 0x00 3. "DIS3,Data Interrupt Status t" "0,1"
bitfld.long 0x00 2. "DIS2,Data Interrupt Status t" "0,1"
bitfld.long 0x00 1. "DIS1,Data Interrupt Status t" "0,1"
bitfld.long 0x00 0. "DIS0,Data Interrupt Status t" "0,1"
group.long 0x1104++0x03
line.long 0x00 "GWDIE0_4,"
bitfld.long 0x00 31. "DIE31,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 30. "DIE30,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 29. "DIE29,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 28. "DIE28,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 27. "DIE27,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 26. "DIE26,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 25. "DIE25,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 24. "DIE24,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 23. "DIE23,Data Interrupt Enable t" "0,1"
newline
bitfld.long 0x00 22. "DIE22,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 21. "DIE21,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 20. "DIE20,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 19. "DIE19,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 18. "DIE18,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 17. "DIE17,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 16. "DIE16,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 15. "DIE15,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 14. "DIE14,Data Interrupt Enable t" "0,1"
newline
bitfld.long 0x00 13. "DIE13,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 12. "DIE12,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 11. "DIE11,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 10. "DIE10,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 9. "DIE9,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 8. "DIE8,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 7. "DIE7,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 6. "DIE6,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 5. "DIE5,Data Interrupt Enable t" "0,1"
newline
bitfld.long 0x00 4. "DIE4,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 3. "DIE3,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 2. "DIE2,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 1. "DIE1,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 0. "DIE0,Data Interrupt Enable t" "0,1"
group.long 0x1108++0x03
line.long 0x00 "GWDID0_4,"
bitfld.long 0x00 31. "DID31,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 30. "DID30,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 29. "DID29,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 28. "DID28,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 27. "DID27,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 26. "DID26,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 25. "DID25,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 24. "DID24,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 23. "DID23,Data Interrupt Disable t" "0,1"
newline
bitfld.long 0x00 22. "DID22,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 21. "DID21,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 20. "DID20,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 19. "DID19,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 18. "DID18,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 17. "DID17,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 16. "DID16,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 15. "DID15,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 14. "DID14,Data Interrupt Disable t" "0,1"
newline
bitfld.long 0x00 13. "DID13,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 12. "DID12,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 11. "DID11,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 10. "DID10,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 9. "DID9,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 8. "DID8,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 7. "DID7,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 6. "DID6,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 5. "DID5,Data Interrupt Disable t" "0,1"
newline
bitfld.long 0x00 4. "DID4,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 3. "DID3,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 2. "DID2,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 1. "DID1,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 0. "DID0,Data Interrupt Disable t" "0,1"
group.long 0x110C++0x03
line.long 0x00 "GWDIDS0_4,"
rbitfld.long 0x00 31. "DIDS31,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 30. "DIDS30,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 29. "DIDS29,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 28. "DIDS28,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 27. "DIDS27,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 26. "DIDS26,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 25. "DIDS25,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 24. "DIDS24,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 23. "DIDS23,Data Interrupt Delayed status t" "0,1"
newline
rbitfld.long 0x00 22. "DIDS22,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 21. "DIDS21,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 20. "DIDS20,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 19. "DIDS19,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 18. "DIDS18,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 17. "DIDS17,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 16. "DIDS16,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 15. "DIDS15,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 14. "DIDS14,Data Interrupt Delayed status t" "0,1"
newline
rbitfld.long 0x00 13. "DIDS13,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 12. "DIDS12,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 11. "DIDS11,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 10. "DIDS10,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 9. "DIDS9,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 8. "DIDS8,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 7. "DIDS7,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 6. "DIDS6,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 5. "DIDS5,Data Interrupt Delayed status t" "0,1"
newline
rbitfld.long 0x00 4. "DIDS4,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 3. "DIDS3,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 2. "DIDS2,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 1. "DIDS1,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 0. "DIDS0,Data Interrupt Delayed status t" "0,1"
group.long 0x1110++0x03
line.long 0x00 "GWDIS1_4,"
bitfld.long 0x00 31. "DIS31,Data Interrupt Status t" "0,1"
bitfld.long 0x00 30. "DIS30,Data Interrupt Status t" "0,1"
bitfld.long 0x00 29. "DIS29,Data Interrupt Status t" "0,1"
bitfld.long 0x00 28. "DIS28,Data Interrupt Status t" "0,1"
bitfld.long 0x00 27. "DIS27,Data Interrupt Status t" "0,1"
bitfld.long 0x00 26. "DIS26,Data Interrupt Status t" "0,1"
bitfld.long 0x00 25. "DIS25,Data Interrupt Status t" "0,1"
bitfld.long 0x00 24. "DIS24,Data Interrupt Status t" "0,1"
bitfld.long 0x00 23. "DIS23,Data Interrupt Status t" "0,1"
newline
bitfld.long 0x00 22. "DIS22,Data Interrupt Status t" "0,1"
bitfld.long 0x00 21. "DIS21,Data Interrupt Status t" "0,1"
bitfld.long 0x00 20. "DIS20,Data Interrupt Status t" "0,1"
bitfld.long 0x00 19. "DIS19,Data Interrupt Status t" "0,1"
bitfld.long 0x00 18. "DIS18,Data Interrupt Status t" "0,1"
bitfld.long 0x00 17. "DIS17,Data Interrupt Status t" "0,1"
bitfld.long 0x00 16. "DIS16,Data Interrupt Status t" "0,1"
bitfld.long 0x00 15. "DIS15,Data Interrupt Status t" "0,1"
bitfld.long 0x00 14. "DIS14,Data Interrupt Status t" "0,1"
newline
bitfld.long 0x00 13. "DIS13,Data Interrupt Status t" "0,1"
bitfld.long 0x00 12. "DIS12,Data Interrupt Status t" "0,1"
bitfld.long 0x00 11. "DIS11,Data Interrupt Status t" "0,1"
bitfld.long 0x00 10. "DIS10,Data Interrupt Status t" "0,1"
bitfld.long 0x00 9. "DIS9,Data Interrupt Status t" "0,1"
bitfld.long 0x00 8. "DIS8,Data Interrupt Status t" "0,1"
bitfld.long 0x00 7. "DIS7,Data Interrupt Status t" "0,1"
bitfld.long 0x00 6. "DIS6,Data Interrupt Status t" "0,1"
bitfld.long 0x00 5. "DIS5,Data Interrupt Status t" "0,1"
newline
bitfld.long 0x00 4. "DIS4,Data Interrupt Status t" "0,1"
bitfld.long 0x00 3. "DIS3,Data Interrupt Status t" "0,1"
bitfld.long 0x00 2. "DIS2,Data Interrupt Status t" "0,1"
bitfld.long 0x00 1. "DIS1,Data Interrupt Status t" "0,1"
bitfld.long 0x00 0. "DIS0,Data Interrupt Status t" "0,1"
group.long 0x1114++0x03
line.long 0x00 "GWDIE1_4,"
bitfld.long 0x00 31. "DIE31,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 30. "DIE30,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 29. "DIE29,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 28. "DIE28,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 27. "DIE27,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 26. "DIE26,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 25. "DIE25,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 24. "DIE24,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 23. "DIE23,Data Interrupt Enable t" "0,1"
newline
bitfld.long 0x00 22. "DIE22,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 21. "DIE21,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 20. "DIE20,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 19. "DIE19,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 18. "DIE18,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 17. "DIE17,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 16. "DIE16,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 15. "DIE15,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 14. "DIE14,Data Interrupt Enable t" "0,1"
newline
bitfld.long 0x00 13. "DIE13,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 12. "DIE12,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 11. "DIE11,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 10. "DIE10,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 9. "DIE9,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 8. "DIE8,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 7. "DIE7,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 6. "DIE6,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 5. "DIE5,Data Interrupt Enable t" "0,1"
newline
bitfld.long 0x00 4. "DIE4,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 3. "DIE3,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 2. "DIE2,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 1. "DIE1,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 0. "DIE0,Data Interrupt Enable t" "0,1"
group.long 0x1118++0x03
line.long 0x00 "GWDID1_4,"
bitfld.long 0x00 31. "DID31,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 30. "DID30,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 29. "DID29,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 28. "DID28,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 27. "DID27,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 26. "DID26,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 25. "DID25,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 24. "DID24,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 23. "DID23,Data Interrupt Disable t" "0,1"
newline
bitfld.long 0x00 22. "DID22,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 21. "DID21,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 20. "DID20,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 19. "DID19,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 18. "DID18,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 17. "DID17,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 16. "DID16,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 15. "DID15,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 14. "DID14,Data Interrupt Disable t" "0,1"
newline
bitfld.long 0x00 13. "DID13,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 12. "DID12,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 11. "DID11,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 10. "DID10,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 9. "DID9,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 8. "DID8,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 7. "DID7,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 6. "DID6,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 5. "DID5,Data Interrupt Disable t" "0,1"
newline
bitfld.long 0x00 4. "DID4,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 3. "DID3,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 2. "DID2,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 1. "DID1,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 0. "DID0,Data Interrupt Disable t" "0,1"
group.long 0x111C++0x03
line.long 0x00 "GWDIDS1_4,"
rbitfld.long 0x00 31. "DIDS31,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 30. "DIDS30,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 29. "DIDS29,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 28. "DIDS28,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 27. "DIDS27,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 26. "DIDS26,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 25. "DIDS25,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 24. "DIDS24,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 23. "DIDS23,Data Interrupt Delayed status t" "0,1"
newline
rbitfld.long 0x00 22. "DIDS22,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 21. "DIDS21,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 20. "DIDS20,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 19. "DIDS19,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 18. "DIDS18,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 17. "DIDS17,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 16. "DIDS16,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 15. "DIDS15,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 14. "DIDS14,Data Interrupt Delayed status t" "0,1"
newline
rbitfld.long 0x00 13. "DIDS13,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 12. "DIDS12,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 11. "DIDS11,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 10. "DIDS10,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 9. "DIDS9,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 8. "DIDS8,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 7. "DIDS7,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 6. "DIDS6,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 5. "DIDS5,Data Interrupt Delayed status t" "0,1"
newline
rbitfld.long 0x00 4. "DIDS4,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 3. "DIDS3,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 2. "DIDS2,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 1. "DIDS1,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 0. "DIDS0,Data Interrupt Delayed status t" "0,1"
group.long 0x1120++0x03
line.long 0x00 "GWDIS2_4,"
bitfld.long 0x00 31. "DIS31,Data Interrupt Status t" "0,1"
bitfld.long 0x00 30. "DIS30,Data Interrupt Status t" "0,1"
bitfld.long 0x00 29. "DIS29,Data Interrupt Status t" "0,1"
bitfld.long 0x00 28. "DIS28,Data Interrupt Status t" "0,1"
bitfld.long 0x00 27. "DIS27,Data Interrupt Status t" "0,1"
bitfld.long 0x00 26. "DIS26,Data Interrupt Status t" "0,1"
bitfld.long 0x00 25. "DIS25,Data Interrupt Status t" "0,1"
bitfld.long 0x00 24. "DIS24,Data Interrupt Status t" "0,1"
bitfld.long 0x00 23. "DIS23,Data Interrupt Status t" "0,1"
newline
bitfld.long 0x00 22. "DIS22,Data Interrupt Status t" "0,1"
bitfld.long 0x00 21. "DIS21,Data Interrupt Status t" "0,1"
bitfld.long 0x00 20. "DIS20,Data Interrupt Status t" "0,1"
bitfld.long 0x00 19. "DIS19,Data Interrupt Status t" "0,1"
bitfld.long 0x00 18. "DIS18,Data Interrupt Status t" "0,1"
bitfld.long 0x00 17. "DIS17,Data Interrupt Status t" "0,1"
bitfld.long 0x00 16. "DIS16,Data Interrupt Status t" "0,1"
bitfld.long 0x00 15. "DIS15,Data Interrupt Status t" "0,1"
bitfld.long 0x00 14. "DIS14,Data Interrupt Status t" "0,1"
newline
bitfld.long 0x00 13. "DIS13,Data Interrupt Status t" "0,1"
bitfld.long 0x00 12. "DIS12,Data Interrupt Status t" "0,1"
bitfld.long 0x00 11. "DIS11,Data Interrupt Status t" "0,1"
bitfld.long 0x00 10. "DIS10,Data Interrupt Status t" "0,1"
bitfld.long 0x00 9. "DIS9,Data Interrupt Status t" "0,1"
bitfld.long 0x00 8. "DIS8,Data Interrupt Status t" "0,1"
bitfld.long 0x00 7. "DIS7,Data Interrupt Status t" "0,1"
bitfld.long 0x00 6. "DIS6,Data Interrupt Status t" "0,1"
bitfld.long 0x00 5. "DIS5,Data Interrupt Status t" "0,1"
newline
bitfld.long 0x00 4. "DIS4,Data Interrupt Status t" "0,1"
bitfld.long 0x00 3. "DIS3,Data Interrupt Status t" "0,1"
bitfld.long 0x00 2. "DIS2,Data Interrupt Status t" "0,1"
bitfld.long 0x00 1. "DIS1,Data Interrupt Status t" "0,1"
bitfld.long 0x00 0. "DIS0,Data Interrupt Status t" "0,1"
group.long 0x1124++0x03
line.long 0x00 "GWDIE2_4,"
bitfld.long 0x00 31. "DIE31,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 30. "DIE30,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 29. "DIE29,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 28. "DIE28,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 27. "DIE27,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 26. "DIE26,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 25. "DIE25,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 24. "DIE24,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 23. "DIE23,Data Interrupt Enable t" "0,1"
newline
bitfld.long 0x00 22. "DIE22,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 21. "DIE21,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 20. "DIE20,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 19. "DIE19,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 18. "DIE18,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 17. "DIE17,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 16. "DIE16,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 15. "DIE15,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 14. "DIE14,Data Interrupt Enable t" "0,1"
newline
bitfld.long 0x00 13. "DIE13,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 12. "DIE12,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 11. "DIE11,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 10. "DIE10,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 9. "DIE9,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 8. "DIE8,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 7. "DIE7,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 6. "DIE6,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 5. "DIE5,Data Interrupt Enable t" "0,1"
newline
bitfld.long 0x00 4. "DIE4,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 3. "DIE3,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 2. "DIE2,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 1. "DIE1,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 0. "DIE0,Data Interrupt Enable t" "0,1"
group.long 0x1128++0x03
line.long 0x00 "GWDID2_4,"
bitfld.long 0x00 31. "DID31,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 30. "DID30,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 29. "DID29,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 28. "DID28,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 27. "DID27,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 26. "DID26,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 25. "DID25,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 24. "DID24,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 23. "DID23,Data Interrupt Disable t" "0,1"
newline
bitfld.long 0x00 22. "DID22,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 21. "DID21,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 20. "DID20,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 19. "DID19,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 18. "DID18,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 17. "DID17,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 16. "DID16,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 15. "DID15,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 14. "DID14,Data Interrupt Disable t" "0,1"
newline
bitfld.long 0x00 13. "DID13,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 12. "DID12,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 11. "DID11,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 10. "DID10,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 9. "DID9,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 8. "DID8,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 7. "DID7,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 6. "DID6,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 5. "DID5,Data Interrupt Disable t" "0,1"
newline
bitfld.long 0x00 4. "DID4,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 3. "DID3,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 2. "DID2,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 1. "DID1,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 0. "DID0,Data Interrupt Disable t" "0,1"
group.long 0x112C++0x03
line.long 0x00 "GWDIDS2_4,"
rbitfld.long 0x00 31. "DIDS31,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 30. "DIDS30,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 29. "DIDS29,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 28. "DIDS28,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 27. "DIDS27,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 26. "DIDS26,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 25. "DIDS25,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 24. "DIDS24,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 23. "DIDS23,Data Interrupt Delayed status t" "0,1"
newline
rbitfld.long 0x00 22. "DIDS22,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 21. "DIDS21,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 20. "DIDS20,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 19. "DIDS19,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 18. "DIDS18,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 17. "DIDS17,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 16. "DIDS16,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 15. "DIDS15,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 14. "DIDS14,Data Interrupt Delayed status t" "0,1"
newline
rbitfld.long 0x00 13. "DIDS13,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 12. "DIDS12,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 11. "DIDS11,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 10. "DIDS10,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 9. "DIDS9,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 8. "DIDS8,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 7. "DIDS7,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 6. "DIDS6,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 5. "DIDS5,Data Interrupt Delayed status t" "0,1"
newline
rbitfld.long 0x00 4. "DIDS4,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 3. "DIDS3,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 2. "DIDS2,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 1. "DIDS1,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 0. "DIDS0,Data Interrupt Delayed status t" "0,1"
group.long 0x1130++0x03
line.long 0x00 "GWDIS3_4,"
bitfld.long 0x00 31. "DIS31,Data Interrupt Status t" "0,1"
bitfld.long 0x00 30. "DIS30,Data Interrupt Status t" "0,1"
bitfld.long 0x00 29. "DIS29,Data Interrupt Status t" "0,1"
bitfld.long 0x00 28. "DIS28,Data Interrupt Status t" "0,1"
bitfld.long 0x00 27. "DIS27,Data Interrupt Status t" "0,1"
bitfld.long 0x00 26. "DIS26,Data Interrupt Status t" "0,1"
bitfld.long 0x00 25. "DIS25,Data Interrupt Status t" "0,1"
bitfld.long 0x00 24. "DIS24,Data Interrupt Status t" "0,1"
bitfld.long 0x00 23. "DIS23,Data Interrupt Status t" "0,1"
newline
bitfld.long 0x00 22. "DIS22,Data Interrupt Status t" "0,1"
bitfld.long 0x00 21. "DIS21,Data Interrupt Status t" "0,1"
bitfld.long 0x00 20. "DIS20,Data Interrupt Status t" "0,1"
bitfld.long 0x00 19. "DIS19,Data Interrupt Status t" "0,1"
bitfld.long 0x00 18. "DIS18,Data Interrupt Status t" "0,1"
bitfld.long 0x00 17. "DIS17,Data Interrupt Status t" "0,1"
bitfld.long 0x00 16. "DIS16,Data Interrupt Status t" "0,1"
bitfld.long 0x00 15. "DIS15,Data Interrupt Status t" "0,1"
bitfld.long 0x00 14. "DIS14,Data Interrupt Status t" "0,1"
newline
bitfld.long 0x00 13. "DIS13,Data Interrupt Status t" "0,1"
bitfld.long 0x00 12. "DIS12,Data Interrupt Status t" "0,1"
bitfld.long 0x00 11. "DIS11,Data Interrupt Status t" "0,1"
bitfld.long 0x00 10. "DIS10,Data Interrupt Status t" "0,1"
bitfld.long 0x00 9. "DIS9,Data Interrupt Status t" "0,1"
bitfld.long 0x00 8. "DIS8,Data Interrupt Status t" "0,1"
bitfld.long 0x00 7. "DIS7,Data Interrupt Status t" "0,1"
bitfld.long 0x00 6. "DIS6,Data Interrupt Status t" "0,1"
bitfld.long 0x00 5. "DIS5,Data Interrupt Status t" "0,1"
newline
bitfld.long 0x00 4. "DIS4,Data Interrupt Status t" "0,1"
bitfld.long 0x00 3. "DIS3,Data Interrupt Status t" "0,1"
bitfld.long 0x00 2. "DIS2,Data Interrupt Status t" "0,1"
bitfld.long 0x00 1. "DIS1,Data Interrupt Status t" "0,1"
bitfld.long 0x00 0. "DIS0,Data Interrupt Status t" "0,1"
group.long 0x1134++0x03
line.long 0x00 "GWDIE3_4,"
bitfld.long 0x00 31. "DIE31,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 30. "DIE30,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 29. "DIE29,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 28. "DIE28,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 27. "DIE27,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 26. "DIE26,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 25. "DIE25,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 24. "DIE24,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 23. "DIE23,Data Interrupt Enable t" "0,1"
newline
bitfld.long 0x00 22. "DIE22,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 21. "DIE21,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 20. "DIE20,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 19. "DIE19,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 18. "DIE18,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 17. "DIE17,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 16. "DIE16,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 15. "DIE15,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 14. "DIE14,Data Interrupt Enable t" "0,1"
newline
bitfld.long 0x00 13. "DIE13,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 12. "DIE12,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 11. "DIE11,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 10. "DIE10,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 9. "DIE9,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 8. "DIE8,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 7. "DIE7,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 6. "DIE6,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 5. "DIE5,Data Interrupt Enable t" "0,1"
newline
bitfld.long 0x00 4. "DIE4,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 3. "DIE3,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 2. "DIE2,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 1. "DIE1,Data Interrupt Enable t" "0,1"
bitfld.long 0x00 0. "DIE0,Data Interrupt Enable t" "0,1"
group.long 0x1138++0x03
line.long 0x00 "GWDID3_4,"
bitfld.long 0x00 31. "DID31,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 30. "DID30,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 29. "DID29,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 28. "DID28,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 27. "DID27,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 26. "DID26,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 25. "DID25,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 24. "DID24,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 23. "DID23,Data Interrupt Disable t" "0,1"
newline
bitfld.long 0x00 22. "DID22,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 21. "DID21,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 20. "DID20,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 19. "DID19,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 18. "DID18,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 17. "DID17,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 16. "DID16,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 15. "DID15,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 14. "DID14,Data Interrupt Disable t" "0,1"
newline
bitfld.long 0x00 13. "DID13,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 12. "DID12,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 11. "DID11,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 10. "DID10,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 9. "DID9,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 8. "DID8,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 7. "DID7,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 6. "DID6,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 5. "DID5,Data Interrupt Disable t" "0,1"
newline
bitfld.long 0x00 4. "DID4,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 3. "DID3,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 2. "DID2,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 1. "DID1,Data Interrupt Disable t" "0,1"
bitfld.long 0x00 0. "DID0,Data Interrupt Disable t" "0,1"
group.long 0x113C++0x03
line.long 0x00 "GWDIDS3_4,"
rbitfld.long 0x00 31. "DIDS31,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 30. "DIDS30,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 29. "DIDS29,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 28. "DIDS28,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 27. "DIDS27,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 26. "DIDS26,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 25. "DIDS25,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 24. "DIDS24,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 23. "DIDS23,Data Interrupt Delayed status t" "0,1"
newline
rbitfld.long 0x00 22. "DIDS22,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 21. "DIDS21,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 20. "DIDS20,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 19. "DIDS19,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 18. "DIDS18,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 17. "DIDS17,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 16. "DIDS16,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 15. "DIDS15,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 14. "DIDS14,Data Interrupt Delayed status t" "0,1"
newline
rbitfld.long 0x00 13. "DIDS13,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 12. "DIDS12,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 11. "DIDS11,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 10. "DIDS10,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 9. "DIDS9,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 8. "DIDS8,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 7. "DIDS7,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 6. "DIDS6,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 5. "DIDS5,Data Interrupt Delayed status t" "0,1"
newline
rbitfld.long 0x00 4. "DIDS4,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 3. "DIDS3,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 2. "DIDS2,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 1. "DIDS1,Data Interrupt Delayed status t" "0,1"
rbitfld.long 0x00 0. "DIDS0,Data Interrupt Delayed status t" "0,1"
group.long 0x1180++0x03
line.long 0x00 "GWTSDIS4,"
hexmask.long 0x00 2.--31. 1. "RSV,Reserved area"
bitfld.long 0x00 1. "TSDIS1,Time Stamp Data Interrupt Status s" "0,1"
bitfld.long 0x00 0. "TSDIS0,Time Stamp Data Interrupt Status s" "0,1"
group.long 0x1184++0x03
line.long 0x00 "GWTSDIE4,"
hexmask.long 0x00 2.--31. 1. "RSV,Reserved area"
bitfld.long 0x00 1. "TSDIE1,TimeStamp Data Interrupt Enable s" "0,1"
bitfld.long 0x00 0. "TSDIE0,TimeStamp Data Interrupt Enable s" "0,1"
group.long 0x1188++0x03
line.long 0x00 "GWTSDID4,"
hexmask.long 0x00 2.--31. 1. "RSV,Reserved area"
bitfld.long 0x00 1. "TSDID1,TimeStamp Data Interrupt Disable s" "0,1"
bitfld.long 0x00 0. "TSDID0,TimeStamp Data Interrupt Disable s" "0,1"
group.long 0x1190++0x03
line.long 0x00 "GWEIS04,"
rbitfld.long 0x00 30.--31. "RSV0,Reserved area" "0,1,2,3"
bitfld.long 0x00 28.--29. "TSDNES,Timestamp Descriptor Number Error Status Set conditions: HW: Bit i sets when GWMDNC.TSDMN+1 descriptor has already been used to process one timestamp for descriptor chain i and the timestamp processing is not finished" "0,1,2,3"
rbitfld.long 0x00 26.--27. "RSV1,Reserved area" "0,1,2,3"
bitfld.long 0x00 24.--25. "TDFES,Timestamp Descriptor Full Error Status" "0,1,2,3"
hexmask.long.byte 0x00 16.--23. 1. "FSES,Frame Size Error Status Set conditions: HW: Bit q of this register is set when a frame bigger than GWRMFSC.MFSq has been received for descriptor queue q"
bitfld.long 0x00 15. "TSHES,TimeStamp Hardware Error Status Set conditions: HW: This error happens when timestamps are coming too fast to GWCA to be stored in time so timestamp are lost even if the timestamp RAM is not full" "0,1"
bitfld.long 0x00 14. "TXDNES,TX Descriptor Number Error Status Set conditions: HW: GWMDNC.TXDMN+1 descriptor has already been used to process one frame and the frame processing is not finished" "0,1"
rbitfld.long 0x00 13. "RSV2,Reserved area" "0,1"
bitfld.long 0x00 12. "SEQES,SEQuence Error Status Set conditions: HW: A FMID FEND has been received before a frame transfer started" "0,1"
newline
bitfld.long 0x00 11. "TFES,TAG Filtering Error Status Set conditions: HW: An unauthorized TAG format has been detected" "0,1"
bitfld.long 0x00 10. "USMFSES,Under Switch Minimum Frame Size Error Status Set conditions: HW: A frame smaller than 32 bytes has been received from CPU for transmission" "0,1"
bitfld.long 0x00 9. "TSOVFES,TimeStamp OVerFlow Error Status Set conditions: HW: When a timestamp is received when the timestamp RAM is full" "0,1"
bitfld.long 0x00 8. "L23UECCES,Layer 2/3 Update ECC Error Status Set conditions: HW: When an ECC error has been detected while reading Layer 2/3 update information from the Layer 2/3 update RAM" "0,1"
bitfld.long 0x00 7. "TSECCES,TimeStamp ECC Error Status Set conditions: HW: When an ECC error has been detected while reading a timestamp from timestamp RAM" "0,1"
bitfld.long 0x00 6. "AECCES,AXI ECC Error Status" "0,1"
bitfld.long 0x00 5. "MECCES,Multicast ECC Error Status" "0,1"
bitfld.long 0x00 4. "DSECCES,Descriptor ECC Error Status" "0,1"
bitfld.long 0x00 3. "PECCES,Pointer ECC Error Status" "0,1"
newline
bitfld.long 0x00 2. "TECCES,TAG ECC Error Status Set conditions: HW: When an ECC error has been detected in a TAG from the fabric read interface and one or more TAGs are forwarded to the CPU (forwarded and not overwritten by L2/L3 update function)" "0,1"
bitfld.long 0x00 1. "DECCES,Data ECC Error Status Set conditions: HW: When an ECC error has been detected in a data from the fabric read interface" "0,1"
bitfld.long 0x00 0. "AES,AXI Error Status" "0,1"
group.long 0x1194++0x03
line.long 0x00 "GWEIE04,"
rbitfld.long 0x00 30.--31. "RSV0,Reserved area" "0,1,2,3"
bitfld.long 0x00 28.--29. "TSDNEE,TimeStamp Descriptor Number Error Enable Values: 1b0: Interrupt disabled" "0,1,2,3"
rbitfld.long 0x00 26.--27. "RSV1,Reserved area" "0,1,2,3"
bitfld.long 0x00 24.--25. "TDFEE,Timestamp Descriptor Full Error Enable" "0,1,2,3"
hexmask.long.byte 0x00 16.--23. 1. "FSEE,Frame Size Error Enable"
bitfld.long 0x00 15. "TSHEE,TimeStamp Hardware Error Enable" "0,1"
bitfld.long 0x00 14. "TXDNEE,TX Descriptor Number Error Enable Values: 1b0: Interrupt disabled" "0,1"
rbitfld.long 0x00 13. "RSV2,Reserved area" "0,1"
bitfld.long 0x00 12. "SEQEE,SEQuence Error Enable Values: 1b0: Interrupt disabled" "0,1"
newline
bitfld.long 0x00 11. "TFEE,TAG Filtering Error Enable Values: 1b0: Interrupt disabled" "0,1"
bitfld.long 0x00 10. "USMFSEE,Under Switch Minimum Frame Size Error Enable Values: 1b0: Interrupt disabled" "0,1"
bitfld.long 0x00 9. "TSOVFEE,TimeStamp Overflow Error Enable Values: 1b0: Interrupt disabled" "0,1"
bitfld.long 0x00 8. "L23UECCEE,Layer 2/3 Update ECC Error Enable Values: 1b0: Interrupt disabled" "0,1"
bitfld.long 0x00 7. "TSECCEE,TimeStamp ECC Error Enable" "0,1"
bitfld.long 0x00 6. "AECCEE,AXI ECC Error Enable" "0,1"
bitfld.long 0x00 5. "MECCEE,Multicast ECC Error Enable" "0,1"
bitfld.long 0x00 4. "DSECCEE,Descriptor ECC Error Enable" "0,1"
bitfld.long 0x00 3. "PECCEE,Pointer ECC Error Enable" "0,1"
newline
bitfld.long 0x00 2. "TECCEE,TAG ECC Error Enable" "0,1"
bitfld.long 0x00 1. "DECCEE,Data ECC Error Enable" "0,1"
bitfld.long 0x00 0. "AEE,AXI Error Enable" "0,1"
group.long 0x1198++0x03
line.long 0x00 "GWEID04,"
rbitfld.long 0x00 30.--31. "RSV0,Reserved area" "0,1,2,3"
bitfld.long 0x00 28.--29. "TSDNED,Timestamp Descriptor Number Error Disable Functions: Writing 1 to one of these bits will clear the corresponding bit in GWEIE0.TSDNED register" "0,1,2,3"
rbitfld.long 0x00 26.--27. "RSV1,Reserved area" "0,1,2,3"
bitfld.long 0x00 24.--25. "TDFED,Timestamp Descriptor Full Error Disable" "0,1,2,3"
hexmask.long.byte 0x00 16.--23. 1. "FSED,Frame Size Error Disable"
bitfld.long 0x00 15. "TSHED,TimeStamp Hardware Full Error Disable" "0,1"
bitfld.long 0x00 14. "TXDNED,TX Descriptor Number Error Disable Functions: Writing 1 to this bit will clear GWEIE0.TXDNEE register" "0,1"
rbitfld.long 0x00 13. "RSV2,Reserved area" "0,1"
bitfld.long 0x00 12. "SEQED,SEQuence Error Disable Functions: Writing 1 to this bit will clear GWEIE0.SEQEE register" "0,1"
newline
bitfld.long 0x00 11. "TFED,TAG Filtering Error Disable Functions: Writing 1 to this bit will clear GWEIE0.TFEE register" "0,1"
bitfld.long 0x00 10. "USMFSED,Under Switch Minimum Frame Size Error Disable Functions: Writing 1 to this bit will clear GWEIE0.USMFSEE register" "0,1"
bitfld.long 0x00 9. "TSOVFED,TimeStamp Overflow Error Disable Functions: Writing 1 to this bit will clear GWEIE0.TSOVFEE register" "0,1"
bitfld.long 0x00 8. "L23UECCED,Disable Functions: Writing 1 to this bit will clear GWEIE0.L23UECCEE register" "0,1"
bitfld.long 0x00 7. "TSECCED,TimeStamp ECC Error Disable" "0,1"
bitfld.long 0x00 6. "AECCED,AXI ECC Error Disable" "0,1"
bitfld.long 0x00 5. "MECCED,Multicast ECC error Disable" "0,1"
bitfld.long 0x00 4. "DSECCED,Descriptor ECC Error Disable" "0,1"
bitfld.long 0x00 3. "PECCED,Pointer ECC error Disable" "0,1"
newline
bitfld.long 0x00 2. "DECCED,Data ECC error Disable" "0,1"
bitfld.long 0x00 1. "TECCED,TAG ECC error Disable" "0,1"
bitfld.long 0x00 0. "AED,AXI Error Disable" "0,1"
group.long 0x11A0++0x03
line.long 0x00 "GWEIS14,"
hexmask.long.byte 0x00 24.--31. 1. "RSV0,Reserved area"
hexmask.long.byte 0x00 16.--23. 1. "DQSES,Descriptor Queue Security Error Status Set conditions: HW: Bit q of this register is set when a non-secure descriptor is received (FDESCR.SEC is not set [FWD]) and queue q is a secure queue (GWRDQSC.RDQSL[q] is set) Clear conditions: HW: Being in.."
hexmask.long.byte 0x00 8.--15. 1. "RSV1,Reserved area"
hexmask.long.byte 0x00 0.--7. 1. "DQOES,Descriptor Queue Overflow Error Status Set conditions: HW: Bit q of this register is set when a descriptor is received for queue q when it is full (GWRDQDCq.DQDq == GWRDQMq.DNQq) not disabled (GWRDQC.RDQD[q] is not set) and GWCA is not going out.."
group.long 0x11A4++0x03
line.long 0x00 "GWEIE14,"
hexmask.long.byte 0x00 24.--31. 1. "RSV0,Reserved area"
hexmask.long.byte 0x00 16.--23. 1. "DQSEE,Descriptor Queue Security Error Enable Values: 1b0 for bit q: Interrupt disabled for error q"
hexmask.long.byte 0x00 8.--15. 1. "RSV1,Reserved area"
hexmask.long.byte 0x00 0.--7. 1. "DQOEE,Descriptor Queue Overflow Error Enable Values: 1b0 for bit q: Interrupt disabled for error q"
group.long 0x11A8++0x03
line.long 0x00 "GWEID14,"
hexmask.long.byte 0x00 24.--31. 1. "RSV0,Reserved area"
hexmask.long.byte 0x00 16.--23. 1. "DQSED,Descriptor Queue Security Error Disable Functions: Writing 1 to bit q in this register will clear bit q in GWEIE1.DQSEE register"
hexmask.long.byte 0x00 8.--15. 1. "RSV1,Reserved area"
hexmask.long.byte 0x00 0.--7. 1. "DQOED,Descriptor Queue Overflow Error Disable Functions: Writing 1 to bit q in this register will clear bit q in GWEIE1.DQOEE register"
group.long 0x1200++0x03
line.long 0x00 "GWEIS20_4,"
bitfld.long 0x00 31. "DFES31,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 30. "DFES30,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 29. "DFES29,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 28. "DFES28,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 27. "DFES27,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 26. "DFES26,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 25. "DFES25,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 24. "DFES24,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 23. "DFES23,Descriptor Full Error Status t" "0,1"
newline
bitfld.long 0x00 22. "DFES22,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 21. "DFES21,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 20. "DFES20,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 19. "DFES19,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 18. "DFES18,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 17. "DFES17,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 16. "DFES16,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 15. "DFES15,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 14. "DFES14,Descriptor Full Error Status t" "0,1"
newline
bitfld.long 0x00 13. "DFES13,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 12. "DFES12,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 11. "DFES11,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 10. "DFES10,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 9. "DFES9,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 8. "DFES8,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 7. "DFES7,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 6. "DFES6,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 5. "DFES5,Descriptor Full Error Status t" "0,1"
newline
bitfld.long 0x00 4. "DFES4,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 3. "DFES3,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 2. "DFES2,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 1. "DFES1,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 0. "DFES0,Descriptor Full Error Status t" "0,1"
group.long 0x1204++0x03
line.long 0x00 "GWEIE20_4,"
bitfld.long 0x00 31. "DFEE31,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 30. "DFEE30,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 29. "DFEE29,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 28. "DFEE28,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 27. "DFEE27,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 26. "DFEE26,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 25. "DFEE25,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 24. "DFEE24,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 23. "DFEE23,Descriptor Full Error Enable t" "0,1"
newline
bitfld.long 0x00 22. "DFEE22,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 21. "DFEE21,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 20. "DFEE20,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 19. "DFEE19,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 18. "DFEE18,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 17. "DFEE17,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 16. "DFEE16,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 15. "DFEE15,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 14. "DFEE14,Descriptor Full Error Enable t" "0,1"
newline
bitfld.long 0x00 13. "DFEE13,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 12. "DFEE12,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 11. "DFEE11,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 10. "DFEE10,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 9. "DFEE9,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 8. "DFEE8,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 7. "DFEE7,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 6. "DFEE6,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 5. "DFEE5,Descriptor Full Error Enable t" "0,1"
newline
bitfld.long 0x00 4. "DFEE4,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 3. "DFEE3,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 2. "DFEE2,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 1. "DFEE1,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 0. "DFEE0,Descriptor Full Error Enable t" "0,1"
group.long 0x1208++0x03
line.long 0x00 "GWEID20_4,"
bitfld.long 0x00 31. "DFED31,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 30. "DFED30,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 29. "DFED29,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 28. "DFED28,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 27. "DFED27,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 26. "DFED26,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 25. "DFED25,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 24. "DFED24,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 23. "DFED23,Descriptor Full Error Enable t" "0,1"
newline
bitfld.long 0x00 22. "DFED22,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 21. "DFED21,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 20. "DFED20,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 19. "DFED19,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 18. "DFED18,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 17. "DFED17,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 16. "DFED16,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 15. "DFED15,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 14. "DFED14,Descriptor Full Error Enable t" "0,1"
newline
bitfld.long 0x00 13. "DFED13,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 12. "DFED12,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 11. "DFED11,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 10. "DFED10,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 9. "DFED9,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 8. "DFED8,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 7. "DFED7,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 6. "DFED6,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 5. "DFED5,Descriptor Full Error Enable t" "0,1"
newline
bitfld.long 0x00 4. "DFED4,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 3. "DFED3,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 2. "DFED2,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 1. "DFED1,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 0. "DFED0,Descriptor Full Error Enable t" "0,1"
group.long 0x1210++0x03
line.long 0x00 "GWEIS21_4,"
bitfld.long 0x00 31. "DFES31,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 30. "DFES30,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 29. "DFES29,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 28. "DFES28,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 27. "DFES27,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 26. "DFES26,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 25. "DFES25,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 24. "DFES24,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 23. "DFES23,Descriptor Full Error Status t" "0,1"
newline
bitfld.long 0x00 22. "DFES22,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 21. "DFES21,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 20. "DFES20,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 19. "DFES19,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 18. "DFES18,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 17. "DFES17,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 16. "DFES16,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 15. "DFES15,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 14. "DFES14,Descriptor Full Error Status t" "0,1"
newline
bitfld.long 0x00 13. "DFES13,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 12. "DFES12,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 11. "DFES11,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 10. "DFES10,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 9. "DFES9,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 8. "DFES8,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 7. "DFES7,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 6. "DFES6,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 5. "DFES5,Descriptor Full Error Status t" "0,1"
newline
bitfld.long 0x00 4. "DFES4,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 3. "DFES3,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 2. "DFES2,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 1. "DFES1,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 0. "DFES0,Descriptor Full Error Status t" "0,1"
group.long 0x1214++0x03
line.long 0x00 "GWEIE21_4,"
bitfld.long 0x00 31. "DFEE31,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 30. "DFEE30,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 29. "DFEE29,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 28. "DFEE28,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 27. "DFEE27,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 26. "DFEE26,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 25. "DFEE25,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 24. "DFEE24,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 23. "DFEE23,Descriptor Full Error Enable t" "0,1"
newline
bitfld.long 0x00 22. "DFEE22,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 21. "DFEE21,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 20. "DFEE20,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 19. "DFEE19,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 18. "DFEE18,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 17. "DFEE17,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 16. "DFEE16,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 15. "DFEE15,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 14. "DFEE14,Descriptor Full Error Enable t" "0,1"
newline
bitfld.long 0x00 13. "DFEE13,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 12. "DFEE12,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 11. "DFEE11,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 10. "DFEE10,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 9. "DFEE9,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 8. "DFEE8,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 7. "DFEE7,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 6. "DFEE6,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 5. "DFEE5,Descriptor Full Error Enable t" "0,1"
newline
bitfld.long 0x00 4. "DFEE4,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 3. "DFEE3,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 2. "DFEE2,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 1. "DFEE1,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 0. "DFEE0,Descriptor Full Error Enable t" "0,1"
group.long 0x1218++0x03
line.long 0x00 "GWEID21_4,"
bitfld.long 0x00 31. "DFED31,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 30. "DFED30,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 29. "DFED29,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 28. "DFED28,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 27. "DFED27,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 26. "DFED26,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 25. "DFED25,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 24. "DFED24,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 23. "DFED23,Descriptor Full Error Enable t" "0,1"
newline
bitfld.long 0x00 22. "DFED22,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 21. "DFED21,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 20. "DFED20,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 19. "DFED19,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 18. "DFED18,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 17. "DFED17,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 16. "DFED16,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 15. "DFED15,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 14. "DFED14,Descriptor Full Error Enable t" "0,1"
newline
bitfld.long 0x00 13. "DFED13,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 12. "DFED12,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 11. "DFED11,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 10. "DFED10,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 9. "DFED9,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 8. "DFED8,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 7. "DFED7,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 6. "DFED6,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 5. "DFED5,Descriptor Full Error Enable t" "0,1"
newline
bitfld.long 0x00 4. "DFED4,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 3. "DFED3,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 2. "DFED2,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 1. "DFED1,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 0. "DFED0,Descriptor Full Error Enable t" "0,1"
group.long 0x1220++0x03
line.long 0x00 "GWEIS22_4,"
bitfld.long 0x00 31. "DFES31,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 30. "DFES30,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 29. "DFES29,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 28. "DFES28,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 27. "DFES27,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 26. "DFES26,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 25. "DFES25,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 24. "DFES24,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 23. "DFES23,Descriptor Full Error Status t" "0,1"
newline
bitfld.long 0x00 22. "DFES22,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 21. "DFES21,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 20. "DFES20,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 19. "DFES19,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 18. "DFES18,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 17. "DFES17,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 16. "DFES16,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 15. "DFES15,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 14. "DFES14,Descriptor Full Error Status t" "0,1"
newline
bitfld.long 0x00 13. "DFES13,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 12. "DFES12,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 11. "DFES11,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 10. "DFES10,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 9. "DFES9,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 8. "DFES8,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 7. "DFES7,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 6. "DFES6,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 5. "DFES5,Descriptor Full Error Status t" "0,1"
newline
bitfld.long 0x00 4. "DFES4,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 3. "DFES3,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 2. "DFES2,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 1. "DFES1,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 0. "DFES0,Descriptor Full Error Status t" "0,1"
group.long 0x1224++0x03
line.long 0x00 "GWEIE22_4,"
bitfld.long 0x00 31. "DFEE31,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 30. "DFEE30,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 29. "DFEE29,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 28. "DFEE28,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 27. "DFEE27,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 26. "DFEE26,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 25. "DFEE25,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 24. "DFEE24,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 23. "DFEE23,Descriptor Full Error Enable t" "0,1"
newline
bitfld.long 0x00 22. "DFEE22,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 21. "DFEE21,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 20. "DFEE20,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 19. "DFEE19,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 18. "DFEE18,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 17. "DFEE17,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 16. "DFEE16,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 15. "DFEE15,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 14. "DFEE14,Descriptor Full Error Enable t" "0,1"
newline
bitfld.long 0x00 13. "DFEE13,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 12. "DFEE12,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 11. "DFEE11,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 10. "DFEE10,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 9. "DFEE9,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 8. "DFEE8,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 7. "DFEE7,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 6. "DFEE6,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 5. "DFEE5,Descriptor Full Error Enable t" "0,1"
newline
bitfld.long 0x00 4. "DFEE4,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 3. "DFEE3,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 2. "DFEE2,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 1. "DFEE1,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 0. "DFEE0,Descriptor Full Error Enable t" "0,1"
group.long 0x1228++0x03
line.long 0x00 "GWEID22_4,"
bitfld.long 0x00 31. "DFED31,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 30. "DFED30,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 29. "DFED29,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 28. "DFED28,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 27. "DFED27,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 26. "DFED26,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 25. "DFED25,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 24. "DFED24,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 23. "DFED23,Descriptor Full Error Enable t" "0,1"
newline
bitfld.long 0x00 22. "DFED22,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 21. "DFED21,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 20. "DFED20,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 19. "DFED19,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 18. "DFED18,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 17. "DFED17,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 16. "DFED16,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 15. "DFED15,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 14. "DFED14,Descriptor Full Error Enable t" "0,1"
newline
bitfld.long 0x00 13. "DFED13,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 12. "DFED12,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 11. "DFED11,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 10. "DFED10,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 9. "DFED9,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 8. "DFED8,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 7. "DFED7,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 6. "DFED6,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 5. "DFED5,Descriptor Full Error Enable t" "0,1"
newline
bitfld.long 0x00 4. "DFED4,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 3. "DFED3,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 2. "DFED2,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 1. "DFED1,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 0. "DFED0,Descriptor Full Error Enable t" "0,1"
group.long 0x1230++0x03
line.long 0x00 "GWEIS23_4,"
bitfld.long 0x00 31. "DFES31,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 30. "DFES30,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 29. "DFES29,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 28. "DFES28,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 27. "DFES27,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 26. "DFES26,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 25. "DFES25,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 24. "DFES24,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 23. "DFES23,Descriptor Full Error Status t" "0,1"
newline
bitfld.long 0x00 22. "DFES22,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 21. "DFES21,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 20. "DFES20,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 19. "DFES19,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 18. "DFES18,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 17. "DFES17,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 16. "DFES16,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 15. "DFES15,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 14. "DFES14,Descriptor Full Error Status t" "0,1"
newline
bitfld.long 0x00 13. "DFES13,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 12. "DFES12,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 11. "DFES11,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 10. "DFES10,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 9. "DFES9,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 8. "DFES8,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 7. "DFES7,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 6. "DFES6,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 5. "DFES5,Descriptor Full Error Status t" "0,1"
newline
bitfld.long 0x00 4. "DFES4,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 3. "DFES3,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 2. "DFES2,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 1. "DFES1,Descriptor Full Error Status t" "0,1"
bitfld.long 0x00 0. "DFES0,Descriptor Full Error Status t" "0,1"
group.long 0x1234++0x03
line.long 0x00 "GWEIE23_4,"
bitfld.long 0x00 31. "DFEE31,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 30. "DFEE30,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 29. "DFEE29,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 28. "DFEE28,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 27. "DFEE27,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 26. "DFEE26,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 25. "DFEE25,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 24. "DFEE24,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 23. "DFEE23,Descriptor Full Error Enable t" "0,1"
newline
bitfld.long 0x00 22. "DFEE22,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 21. "DFEE21,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 20. "DFEE20,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 19. "DFEE19,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 18. "DFEE18,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 17. "DFEE17,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 16. "DFEE16,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 15. "DFEE15,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 14. "DFEE14,Descriptor Full Error Enable t" "0,1"
newline
bitfld.long 0x00 13. "DFEE13,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 12. "DFEE12,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 11. "DFEE11,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 10. "DFEE10,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 9. "DFEE9,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 8. "DFEE8,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 7. "DFEE7,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 6. "DFEE6,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 5. "DFEE5,Descriptor Full Error Enable t" "0,1"
newline
bitfld.long 0x00 4. "DFEE4,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 3. "DFEE3,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 2. "DFEE2,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 1. "DFEE1,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 0. "DFEE0,Descriptor Full Error Enable t" "0,1"
group.long 0x1238++0x03
line.long 0x00 "GWEID23_4,"
bitfld.long 0x00 31. "DFED31,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 30. "DFED30,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 29. "DFED29,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 28. "DFED28,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 27. "DFED27,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 26. "DFED26,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 25. "DFED25,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 24. "DFED24,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 23. "DFED23,Descriptor Full Error Enable t" "0,1"
newline
bitfld.long 0x00 22. "DFED22,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 21. "DFED21,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 20. "DFED20,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 19. "DFED19,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 18. "DFED18,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 17. "DFED17,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 16. "DFED16,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 15. "DFED15,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 14. "DFED14,Descriptor Full Error Enable t" "0,1"
newline
bitfld.long 0x00 13. "DFED13,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 12. "DFED12,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 11. "DFED11,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 10. "DFED10,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 9. "DFED9,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 8. "DFED8,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 7. "DFED7,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 6. "DFED6,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 5. "DFED5,Descriptor Full Error Enable t" "0,1"
newline
bitfld.long 0x00 4. "DFED4,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 3. "DFED3,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 2. "DFED2,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 1. "DFED1,Descriptor Full Error Enable t" "0,1"
bitfld.long 0x00 0. "DFED0,Descriptor Full Error Enable t" "0,1"
group.long 0x1280++0x03
line.long 0x00 "GWEIS34,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
bitfld.long 0x00 7. "IAOES7,Incremental Area Overflow Error Status i" "0,1"
bitfld.long 0x00 6. "IAOES6,Incremental Area Overflow Error Status i" "0,1"
bitfld.long 0x00 5. "IAOES5,Incremental Area Overflow Error Status i" "0,1"
bitfld.long 0x00 4. "IAOES4,Incremental Area Overflow Error Status i" "0,1"
bitfld.long 0x00 3. "IAOES3,Incremental Area Overflow Error Status i" "0,1"
bitfld.long 0x00 2. "IAOES2,Incremental Area Overflow Error Status i" "0,1"
bitfld.long 0x00 1. "IAOES1,Incremental Area Overflow Error Status i" "0,1"
bitfld.long 0x00 0. "IAOES0,Incremental Area Overflow Error Status i" "0,1"
group.long 0x1284++0x03
line.long 0x00 "GWEIE34,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
bitfld.long 0x00 7. "IAOEE7,Incremental Area Overflow Error Enable i" "0,1"
bitfld.long 0x00 6. "IAOEE6,Incremental Area Overflow Error Enable i" "0,1"
bitfld.long 0x00 5. "IAOEE5,Incremental Area Overflow Error Enable i" "0,1"
bitfld.long 0x00 4. "IAOEE4,Incremental Area Overflow Error Enable i" "0,1"
bitfld.long 0x00 3. "IAOEE3,Incremental Area Overflow Error Enable i" "0,1"
bitfld.long 0x00 2. "IAOEE2,Incremental Area Overflow Error Enable i" "0,1"
bitfld.long 0x00 1. "IAOEE1,Incremental Area Overflow Error Enable i" "0,1"
bitfld.long 0x00 0. "IAOEE0,Incremental Area Overflow Error Enable i" "0,1"
group.long 0x1288++0x03
line.long 0x00 "GWEID34,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
bitfld.long 0x00 7. "IAOED7,Incremental Area Overflow Error Disable i" "0,1"
bitfld.long 0x00 6. "IAOED6,Incremental Area Overflow Error Disable i" "0,1"
bitfld.long 0x00 5. "IAOED5,Incremental Area Overflow Error Disable i" "0,1"
bitfld.long 0x00 4. "IAOED4,Incremental Area Overflow Error Disable i" "0,1"
bitfld.long 0x00 3. "IAOED3,Incremental Area Overflow Error Disable i" "0,1"
bitfld.long 0x00 2. "IAOED2,Incremental Area Overflow Error Disable i" "0,1"
bitfld.long 0x00 1. "IAOED1,Incremental Area Overflow Error Disable i" "0,1"
bitfld.long 0x00 0. "IAOED0,Incremental Area Overflow Error Disable i" "0,1"
group.long 0x1290++0x03
line.long 0x00 "GWEIS44,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "DSECN,Data Size Error Chain Number Clear conditions: HW: Being in RESET mode will clear this register"
rbitfld.long 0x00 18.--23. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 17. "DSEIOS,Data Size Error Interrupt Overflow Status Set conditions: When a Data Size Error occurs and GWEIS4.DSES is already set to one" "0,1"
bitfld.long 0x00 16. "DSES,Data Size Error Status" "0,1"
rbitfld.long 0x00 15. "RSV2,Reserved area" "0,1"
hexmask.long.byte 0x00 8.--14. 1. "DSSECN,Descriptor Security Error Chain Number Restrictions: HW: This register is only valid for RX queues"
rbitfld.long 0x00 2.--7. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 1. "DSSEIOS,Descriptor Security Error Interrupt Overflow Status Clear conditions: HW: Being in RESET mode will clear this register" "0,1"
newline
bitfld.long 0x00 0. "DSSES,Descriptor Security Error Status" "0,1"
group.long 0x1294++0x03
line.long 0x00 "GWEIE44,"
hexmask.long.word 0x00 18.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 17. "DSEIOE,Data Size Error Interrupt Overflow Interrupt Enable" "0,1"
bitfld.long 0x00 16. "DSEE,Data Size Error Enable" "0,1"
hexmask.long.word 0x00 2.--15. 1. "RSV1,Reserved area"
bitfld.long 0x00 1. "DSSEIOE,Descriptor Security Error Interrupt Overflow Enable Values: 1b0: Interrupt disabled" "0,1"
bitfld.long 0x00 0. "DSSEE,Descriptor Security Error Enable" "0,1"
group.long 0x1298++0x03
line.long 0x00 "GWEID44,"
hexmask.long.word 0x00 18.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 17. "DSEIOD,Data Size Error Interrupt Overflow Disable" "0,1"
bitfld.long 0x00 16. "DSED,Data Size Error Disable" "0,1"
hexmask.long.word 0x00 2.--15. 1. "RSV1,Reserved area"
bitfld.long 0x00 1. "DSSEIOD,Descriptor Security Error Interrupt Overflow Disable Functions: Writing 1 to this bit will clear GWEIE4.DSSEIOE register" "0,1"
bitfld.long 0x00 0. "DSSED,Descriptor Security Error Disable Functions: Writing 1 to this bit will clear GWEIE4.DSSEE register" "0,1"
group.long 0x12A0++0x03
line.long 0x00 "GWEIS54,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "RXDNECN,RX Descriptor Number Error Chain Number Clear conditions: HW: Being in RESET mode will clear this register"
rbitfld.long 0x00 18.--23. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 17. "RXDNEIOS,RX Descriptor Number Error Interrupt Overflow Status Clear conditions: HW: Being in RESET mode will clear this register" "0,1"
bitfld.long 0x00 16. "RXDNES,RX Descriptor Number Error Status Set conditions: HW: GWMDNC.RXDMN+1 descriptor has already been used to process one frame and the frame processing is not finished" "0,1"
rbitfld.long 0x00 15. "RSV2,Reserved area" "0,1"
hexmask.long.byte 0x00 8.--14. 1. "DCTECN,Descriptor Chain Type Error Chain Number Clear conditions: HW: Being in RESET mode will clear this register"
rbitfld.long 0x00 2.--7. "RSV3,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 1. "DCTEIOS,Descriptor Chain Type Error Interrupt Overflow Status Clear conditions: HW: Being in RESET mode will clear this register" "0,1"
newline
bitfld.long 0x00 0. "DCTES,Descriptor Chain Type Error Status" "0,1"
group.long 0x12A4++0x03
line.long 0x00 "GWEIE54,"
hexmask.long.word 0x00 18.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 17. "RXDNEIOE,RX Descriptor Number Error Interrupt Overflow Enable Values: 1b0: Interrupt disabled" "0,1"
bitfld.long 0x00 16. "RXDNEE,RX Descriptor Number Error Enable" "0,1"
hexmask.long.word 0x00 2.--15. 1. "RSV1,Reserved area"
bitfld.long 0x00 1. "DCTEIOE,Descriptor Chain Type Error Interrupt Overflow Enable Values: 1b0: Interrupt disabled" "0,1"
bitfld.long 0x00 0. "DCTEE,Descriptor Chain Type Error Enable" "0,1"
group.long 0x12A8++0x03
line.long 0x00 "GWEID54,"
hexmask.long.word 0x00 18.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 17. "RXDNEIOD,RX Descriptor Number Error Interrupt Overflow Disable Functions: Writing 1 to this bit will clear GWEIE5.RXDNEIOE register" "0,1"
bitfld.long 0x00 16. "RXDNED,RX Descriptor Number Error Disable Functions: Writing 1 to this bit will clear GWEIE5.RXDNEE register" "0,1"
hexmask.long.word 0x00 2.--15. 1. "RSV1,Reserved area"
bitfld.long 0x00 1. "DCTEIOD,Descriptor Chain Type Error Interrupt Overflow Disable Functions: Writing 1 to this bit will clear GWEIE5.DCTEIOE register" "0,1"
bitfld.long 0x00 0. "DCTED,Descriptor Chain Type Error Disable Functions: Writing 1 to this bit will clear GWEIE5.DCTEE register" "0,1"
group.long 0x1800++0x03
line.long 0x00 "GWSCR04,"
rbitfld.long 0x00 30.--31. "RSV0,Reserved area" "0,1,2,3"
bitfld.long 0x00 28.--29. "TRSL,Timer Register Security Level" "0,1,2,3"
rbitfld.long 0x00 26.--27. "RSV1,Reserved area" "0,1,2,3"
bitfld.long 0x00 24.--25. "TSQRSL,Timestamp Queue Register Security Level" "0,1,2,3"
hexmask.long.byte 0x00 16.--23. 1. "DQRSL,Descriptor queue Register Security Level"
hexmask.long.byte 0x00 8.--15. 1. "APRSL,AXI Priority Register Security Level"
bitfld.long 0x00 7. "EIRSL,Error Interrupt Register Security Level Values: 1b0: Error Interrupt registers can only be accessed by the APB secure interface 1b1: Error Interrupt registers can be accessed by both APBs Error Interrupt registers include the following.." "0,1"
bitfld.long 0x00 6. "AXRSL,AXI Register Security Level" "0,1"
bitfld.long 0x00 5. "TSRSL,Timestamp Register Security Level" "0,1"
newline
bitfld.long 0x00 4. "TGRSL,TAG Register Security Level" "0,1"
bitfld.long 0x00 3. "MCRSL,MAC Register Security Level" "0,1"
bitfld.long 0x00 2. "MTRSL,Multicast Table Register Security Level" "0,1"
bitfld.long 0x00 1. "RRSL,Reception Register Security Level" "0,1"
bitfld.long 0x00 0. "MRSL,Mode Register Security Level" "0,1"
group.long 0x1804++0x03
line.long 0x00 "GWSCR14,"
hexmask.long 0x00 1.--31. 1. "RSV,Reserved area"
bitfld.long 0x00 0. "CRSL,Counter Register Security Level" "0,1"
group.long 0x1900++0x03
line.long 0x00 "GWSCR20_4,"
bitfld.long 0x00 31. "ACRSL31,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 30. "ACRSL30,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 29. "ACRSL29,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 28. "ACRSL28,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 27. "ACRSL27,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 26. "ACRSL26,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 25. "ACRSL25,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 24. "ACRSL24,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 23. "ACRSL23,AXI Chain Register Security Level t" "0,1"
newline
bitfld.long 0x00 22. "ACRSL22,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 21. "ACRSL21,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 20. "ACRSL20,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 19. "ACRSL19,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 18. "ACRSL18,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 17. "ACRSL17,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 16. "ACRSL16,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 15. "ACRSL15,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 14. "ACRSL14,AXI Chain Register Security Level t" "0,1"
newline
bitfld.long 0x00 13. "ACRSL13,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 12. "ACRSL12,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 11. "ACRSL11,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 10. "ACRSL10,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 9. "ACRSL9,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 8. "ACRSL8,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 7. "ACRSL7,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 6. "ACRSL6,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 5. "ACRSL5,AXI Chain Register Security Level t" "0,1"
newline
bitfld.long 0x00 4. "ACRSL4,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 3. "ACRSL3,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 2. "ACRSL2,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 1. "ACRSL1,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 0. "ACRSL0,AXI Chain Register Security Level t" "0,1"
group.long 0x1904++0x03
line.long 0x00 "GWSCR21_4,"
bitfld.long 0x00 31. "ACRSL31,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 30. "ACRSL30,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 29. "ACRSL29,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 28. "ACRSL28,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 27. "ACRSL27,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 26. "ACRSL26,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 25. "ACRSL25,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 24. "ACRSL24,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 23. "ACRSL23,AXI Chain Register Security Level t" "0,1"
newline
bitfld.long 0x00 22. "ACRSL22,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 21. "ACRSL21,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 20. "ACRSL20,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 19. "ACRSL19,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 18. "ACRSL18,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 17. "ACRSL17,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 16. "ACRSL16,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 15. "ACRSL15,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 14. "ACRSL14,AXI Chain Register Security Level t" "0,1"
newline
bitfld.long 0x00 13. "ACRSL13,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 12. "ACRSL12,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 11. "ACRSL11,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 10. "ACRSL10,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 9. "ACRSL9,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 8. "ACRSL8,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 7. "ACRSL7,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 6. "ACRSL6,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 5. "ACRSL5,AXI Chain Register Security Level t" "0,1"
newline
bitfld.long 0x00 4. "ACRSL4,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 3. "ACRSL3,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 2. "ACRSL2,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 1. "ACRSL1,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 0. "ACRSL0,AXI Chain Register Security Level t" "0,1"
group.long 0x1908++0x03
line.long 0x00 "GWSCR22_4,"
bitfld.long 0x00 31. "ACRSL31,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 30. "ACRSL30,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 29. "ACRSL29,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 28. "ACRSL28,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 27. "ACRSL27,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 26. "ACRSL26,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 25. "ACRSL25,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 24. "ACRSL24,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 23. "ACRSL23,AXI Chain Register Security Level t" "0,1"
newline
bitfld.long 0x00 22. "ACRSL22,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 21. "ACRSL21,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 20. "ACRSL20,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 19. "ACRSL19,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 18. "ACRSL18,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 17. "ACRSL17,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 16. "ACRSL16,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 15. "ACRSL15,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 14. "ACRSL14,AXI Chain Register Security Level t" "0,1"
newline
bitfld.long 0x00 13. "ACRSL13,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 12. "ACRSL12,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 11. "ACRSL11,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 10. "ACRSL10,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 9. "ACRSL9,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 8. "ACRSL8,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 7. "ACRSL7,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 6. "ACRSL6,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 5. "ACRSL5,AXI Chain Register Security Level t" "0,1"
newline
bitfld.long 0x00 4. "ACRSL4,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 3. "ACRSL3,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 2. "ACRSL2,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 1. "ACRSL1,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 0. "ACRSL0,AXI Chain Register Security Level t" "0,1"
group.long 0x190C++0x03
line.long 0x00 "GWSCR23_4,"
bitfld.long 0x00 31. "ACRSL31,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 30. "ACRSL30,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 29. "ACRSL29,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 28. "ACRSL28,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 27. "ACRSL27,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 26. "ACRSL26,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 25. "ACRSL25,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 24. "ACRSL24,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 23. "ACRSL23,AXI Chain Register Security Level t" "0,1"
newline
bitfld.long 0x00 22. "ACRSL22,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 21. "ACRSL21,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 20. "ACRSL20,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 19. "ACRSL19,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 18. "ACRSL18,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 17. "ACRSL17,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 16. "ACRSL16,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 15. "ACRSL15,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 14. "ACRSL14,AXI Chain Register Security Level t" "0,1"
newline
bitfld.long 0x00 13. "ACRSL13,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 12. "ACRSL12,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 11. "ACRSL11,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 10. "ACRSL10,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 9. "ACRSL9,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 8. "ACRSL8,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 7. "ACRSL7,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 6. "ACRSL6,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 5. "ACRSL5,AXI Chain Register Security Level t" "0,1"
newline
bitfld.long 0x00 4. "ACRSL4,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 3. "ACRSL3,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 2. "ACRSL2,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 1. "ACRSL1,AXI Chain Register Security Level t" "0,1"
bitfld.long 0x00 0. "ACRSL0,AXI Chain Register Security Level t" "0,1"
tree.end
tree.end
tree "R_SWITCH_2"
base ad:0xE6888000
group.long 0x00++0x03
line.long 0x00 "TPEMIMC0,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "SSICM1,Switch Status Interrupt Core Mapping 1 Functions: Used to decide to which pin Switch Status Interrupt 1 are mapped when mapped to a GWCA" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 26.--27. "RSV1,Reserved area" "0,1,2,3"
bitfld.long 0x00 25. "SSIGM1,Switch Status Interrupt GWCA Mapping 1 Values: 1b0: When TPEMIMC0.SSIM1 is set to 1b1 Switch Status Interrupt 1 are mapped to race_gwca0_core_int[TPEMIMC0.SSICM1] 1b1: When TPEMIMC0.SSIM1 is set to 1b1 Switch Status Interrupt 1 are mapped to.." "0,1"
bitfld.long 0x00 24. "SSIM1,Switch Status Interrupt Mapping 1 Values: 1b0: Switch Status Interrupt 1 are mapped to race_race_status_int 1b1: Switch Status Interrupt 1 are mapped to a specific core depending on TPEMIMC0.SSIGM1 register Switch Status Interrupt 1 contain the.." "0,1"
rbitfld.long 0x00 23. "RSV2,Reserved area" "0,1"
bitfld.long 0x00 20.--22. "SSICM0,Switch Status Interrupt Core Mapping 0 Functions: Used to decide to which pin Switch Status Interrupt 0 are mapped when mapped to a GWCA" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 18.--19. "RSV3,Reserved area" "0,1,2,3"
bitfld.long 0x00 17. "SSIGM0,Switch Status Interrupt GWCA Mapping 0 Values: 1b0: When TPEMIMC0.SSIM0 is set to 1b1 Switch Status Interrupt 0 are mapped to race_gwca0_core_int[TPEMIMC0.SSICM0] 1b1: When TPEMIMC0.SSIM0 is set to 1b1 Switch Status Interrupt 0 are mapped to.." "0,1"
bitfld.long 0x00 16. "SSIM0,Switch Status Interrupt Mapping 0 Values: 1b0: Switch Status Interrupt 0 are mapped to race_race_status_int 1b1: Switch Status Interrupt 0 are mapped to a specific core depending on TPEMIMC0.SSIGM0 register Switch Status Interrupt 0 contain the.." "0,1"
newline
hexmask.long.word 0x00 7.--15. 1. "RSV4,Reserved area"
bitfld.long 0x00 4.--6. "SEICM,Switch Error Interrupt Core Mapping Functions: Used to decide to which pin Switch Error Interrupt are mapped when mapped to a GWCA" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 2.--3. "RSV5,Reserved area" "0,1,2,3"
bitfld.long 0x00 1. "SEIGM,Switch Error Interrupt GWCA Mapping Values: 1b0: When TPEMIMC0.SEIM is set to 1b1 Switch Error Interrupt are mapped to race_gwca0_core_int[TPEMIMC0.SEICM] 1b1: When TPEMIMC0.SEIM is set to 1b1 Switch Error Interrupt are mapped to.." "0,1"
bitfld.long 0x00 0. "SEIM,Switch Error Interrupt Mapping Values: 1b0: Switch Error Interrupt are mapped to race_race_error_int 1b1: Switch Error Interrupt are mapped to a specific core depending on TPEMIMC0.SEIGM register Switch Error Interrupt contain the following.." "0,1"
group.long 0x04++0x03
line.long 0x00 "TPEMIMC1,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "CSICM,Common Status Interrupt Core Mapping Functions: Used to decide to which pin Common Status Interrupt are mapped when mapped to a GWCA" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 26.--27. "RSV1,Reserved area" "0,1,2,3"
bitfld.long 0x00 25. "CSIGM,Common Status Interrupt GWCA Mapping Values: 1b0: When TPEMIMC1.CSIM is set to 1b1 Common Status Interrupt are mapped to race_gwca0_core_int[TPEMIMC1.CSICM] 1b1: When TPEMIMC1.CSIM is set to 1b1 Common Status Interrupt are mapped to.." "0,1"
bitfld.long 0x00 24. "CSIM,Common Status Interrupt Mapping Values: 1b0: Common Status Interrupt are mapped to race_coma_status_int 1b1: Common Status Interrupt are mapped to a specific core depending on TPEMIMC1.CSIGM register Common Status Interrupt contain the following.." "0,1"
rbitfld.long 0x00 23. "RSV2,Reserved area" "0,1"
bitfld.long 0x00 20.--22. "CEICM,Common Error Interrupt Core Mapping Functions: Used to decide to which pin Common Error Interrupt are mapped when mapped to a GWCA" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 18.--19. "RSV3,Reserved area" "0,1,2,3"
bitfld.long 0x00 17. "CEIGM,Common Error Interrupt GWCA Mapping Values: 1b0: When TPEMIMC1.CEIM is set to 1b1 Common Error Interrupt are mapped to race_gwca0_core_int[TPEMIMC1.CEICM] 1b1: When TPEMIMC1.CEIM is set to 1b1 Common Error Interrupt are mapped to.." "0,1"
bitfld.long 0x00 16. "CEIM,Common Error Interrupt Mapping Values: 1b0: Common Error Interrupt are mapped to race_coma_error_int 1b1: Common Error Interrupt are mapped to a specific core depending on TPEMIMC1.CEIGM register Common Error Interrupt contain the following.." "0,1"
newline
rbitfld.long 0x00 15. "RSV4,Reserved area" "0,1"
bitfld.long 0x00 12.--14. "FSICM,Forwarding Status Interrupt Core Mapping Functions: Used to decide to which pin Forwarding Status Interrupt are mapped when mapped to a GWCA" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 10.--11. "RSV5,Reserved area" "0,1,2,3"
bitfld.long 0x00 9. "FSIGM,Forwarding Status Interrupt GWCA Mapping Values: 1b0: When TPEMIMC1.FSIM is set to 1b1 Forwarding Status Interrupt are mapped to race_gwca0_core_int[TPEMIMC1.FSICM] 1b1: When TPEMIMC1.FSIM is set to 1b1 Forwarding Status Interrupt are mapped.." "0,1"
bitfld.long 0x00 8. "FSIM,Forwarding Status Interrupt Mapping Values: 1b0: Forwarding Status Interrupt are mapped to race_mfwd_status_int 1b1: Forwarding Status Interrupt are mapped to a specific core depending on TPEMIMC1.FSIGM register Forwarding Status Interrupt.." "0,1"
rbitfld.long 0x00 7. "RSV6,Reserved area" "0,1"
bitfld.long 0x00 4.--6. "FEICM,Forwarding Error Interrupt Core Mapping Functions: Used to decide to which pin Forwarding Error Interrupt are mapped when mapped to a GWCA" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 2.--3. "RSV7,Reserved area" "0,1,2,3"
bitfld.long 0x00 1. "FEIGM,Forwarding Error Interrupt GWCA Mapping Values: 1b0: When TPEMIMC1.FEIM is set to 1b1 Forwarding Error Interrupt are mapped to race_gwca0_core_int[TPEMIMC1.FEICM] 1b1: When TPEMIMC1.FEIM is set to 1b1 Forwarding Error Interrupt are mapped to.." "0,1"
bitfld.long 0x00 0. "FEIM,Forwarding Error Interrupt Mapping Values: 1b0: Forwarding Error Interrupt are mapped to race_mfwd_error_int 1b1: Forwarding Error Interrupt are mapped to a specific core depending on TPEMIMC1.FEIGM register Forwarding Error Interrupt contain the.." "0,1"
group.long 0x08++0x03
line.long 0x00 "TPEMIMC2,"
rbitfld.long 0x00 31. "RSV0,Reserved area" "0,1"
bitfld.long 0x00 28.--30. "GSICM1,GWCA1 Status Interrupt Core Mapping Functions: Used to decide to which pin GWCA1 Status Interrupt are mapped when mapped to a GWCA" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 26.--27. "RSV1,Reserved area" "0,1,2,3"
bitfld.long 0x00 25. "GSIGM1,GWCA1 Status Interrupt GWCA Mapping Values: 1b0: When TPEMIMC2.GSIM1 is set to 1b1 GWCA1 Status Interrupt are mapped to race_gwca0_core_int[TPEMIMC2.GSICM1] 1b1: When TPEMIMC2.GSIM1 is set to 1b1 GWCA1 Status Interrupt are mapped to.." "0,1"
bitfld.long 0x00 24. "GSIM1,GWCA1 Status Interrupt Mapping Values: 1b0: GWCA1 Status Interrupt are mapped to race_gwca1_status_int 1b1: GWCA1 Status Interrupt are mapped to a specific core depending on TPEMIMC2.GSIGM1 register GWCA1 Status Interrupt contain the following.." "0,1"
rbitfld.long 0x00 23. "RSV2,Reserved area" "0,1"
bitfld.long 0x00 20.--22. "GEICM1,GWCA1 Error Interrupt Core Mapping Functions: Used to decide to which pin GWCA1 Error Interrupt are mapped when mapped to a GWCA" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 18.--19. "RSV3,Reserved area" "0,1,2,3"
bitfld.long 0x00 17. "GEIGM1,GWCA1 Error Interrupt GWCA Mapping Values: 1b0: When TPEMIMC2.GEIM1 is set to 1b1 GWCA1 Error Interrupt are mapped to race_gwca0_core_int[TPEMIMC2.GEICM1] 1b1: When TPEMIMC2.GEIM1 is set to 1b1 GWCA1 Error Interrupt are mapped to.." "0,1"
bitfld.long 0x00 16. "GEIM1,GWCA1 Error Interrupt Mapping Values: 1b0: GWCA1 Error Interrupt are mapped to race_ gwca1_error_int 1b1: GWCA1 Error Interrupt are mapped to a specific core depending on TPEMIMC2.GEIGM1 register GWCA1 Error Interrupt contain the following.." "0,1"
newline
rbitfld.long 0x00 15. "RSV4,Reserved area" "0,1"
bitfld.long 0x00 12.--14. "GSICM0,GWCA0 Status Interrupt Core Mapping Functions: Used to decide to which pin GWCA0 Status Interrupt are mapped when mapped to a GWCA" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 10.--11. "RSV5,Reserved area" "0,1,2,3"
bitfld.long 0x00 9. "GSIGM0,GWCA0 Status Interrupt GWCA Mapping Values: 1b0: When TPEMIMC2.GSIM0 is set to 1b1 GWCA0 Status Interrupt are mapped to race_gwca0_core_int[TPEMIMC2.GSICM0] 1b1: When TPEMIMC2.GSIM0 is set to 1b1 GWCA0 Status Interrupt are mapped to.." "0,1"
bitfld.long 0x00 8. "GSIM0,GWCA0 Status Interrupt Mapping Values: 1b0: GWCA0 Status Interrupt are mapped to race_ gwca0_status_int 1b1: GWCA0 Status Interrupt are mapped to a specific core depending on TPEMIMC2.GSIGM0 register GWCA0 Status Interrupt contain the following.." "0,1"
rbitfld.long 0x00 7. "RSV6,Reserved area" "0,1"
bitfld.long 0x00 4.--6. "GEICM0,GWCA0 Error Interrupt Core Mapping Functions: Used to decide to which pin GWCA0 Error Interrupt are mapped when mapped to a GWCA" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 2.--3. "RSV7,Reserved area" "0,1,2,3"
bitfld.long 0x00 1. "GEIGM0,GWCA0 Error Interrupt GWCA Mapping Values: 1b0: When TPEMIMC2.GEIM0 is set to 1b1 GWCA0 Error Interrupt are mapped to race_gwca0_core_int[TPEMIMC2.GEICM0] 1b1: When TPEMIMC2.GEIM0 is set to 1b1 GWCA0 Error Interrupt are mapped to.." "0,1"
bitfld.long 0x00 0. "GEIM0,GWCA0 Error Interrupt Mapping Values: 1b0: GWCA0 Error Interrupt are mapped to race_ gwca0_error_int 1b1: GWCA0 Error Interrupt are mapped to a specific core depending on TPEMIMC2.GEIGM0 register GWCA0 Error Interrupt contain the following.." "0,1"
group.long 0x0C++0x03
line.long 0x00 "TPEMIMC3,"
hexmask.long.word 0x00 23.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 20.--22. "RSICM0,RMAC0 Status Interrupt Core Mapping Functions: Used to decide to which pin RMAC0 Status Interrupt are mapped when mapped to a GWCA" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 18.--19. "RSV1,Reserved area" "0,1,2,3"
bitfld.long 0x00 17. "RSIGM0,RMAC0 Status Interrupt GWCA Mapping Values: 1b0: When TPEMIMC3.RSIM0 is set to 1b1 RMAC0 Status Interrupt are mapped to race_gwca0_core_int[TPEMIMC3.RSICM0] 1b1: When TPEMIMC3.RSIM0 is set to 1b1 RMAC0 Status Interrupt are mapped to.." "0,1"
bitfld.long 0x00 16. "RSIM0,RMAC0 Status Interrupt Mapping Values: 1b0: RMAC0 Status Interrupt are mapped to race_rmac0_status_int 1b1: RMAC0 Status Interrupt are mapped to a specific core depending on TPEMIMC3.RSIGM0 register RMAC0 Status Interrupt contain the following.." "0,1"
rbitfld.long 0x00 15. "RSV2,Reserved area" "0,1"
bitfld.long 0x00 12.--14. "ESICM0,ETHA0 Status Interrupt Core Mapping Functions: Used to decide to which pin ETHA0 Status Interrupt are mapped when mapped to a GWCA" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 10.--11. "RSV3,Reserved area" "0,1,2,3"
bitfld.long 0x00 9. "ESIGM0,ETHA0 Status Interrupt GWCA Mapping Values: 1b0: When TPEMIMC3.ESIM0 is set to 1b1 ETHA0 Status Interrupt are mapped to race_gwca0_core_int[TPEMIMC3.ESICM0] 1b1: When TPEMIMC3.ESIM0 is set to 1b1 ETHA0 Status Interrupt are mapped to.." "0,1"
bitfld.long 0x00 8. "ESIM0,ETHA0 Status Interrupt Mapping Values: 1b0: ETHA0 Status Interrupt are mapped to race_etha0_status_int 1b1: ETHA0 Status Interrupt are mapped to a specific core depending on TPEMIMC3.ESIGM0 register ETHA0 Status Interrupt contain the following.." "0,1"
newline
rbitfld.long 0x00 7. "RSV4,Reserved area" "0,1"
bitfld.long 0x00 4.--6. "EEICM0,ETHA0 Error Interrupt Core Mapping Functions: Used to decide to which pin ETHA0 Error Interrupt are mapped when mapped to a GWCA" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 2.--3. "RSV5,Reserved area" "0,1,2,3"
bitfld.long 0x00 1. "EEIGM0,ETHA0 Error Interrupt GWCA Mapping Values: 1b0: When TPEMIMC3.EEIM0 is set to 1b1 ETHA0 Error Interrupt are mapped to race_gwca0_core_int[TPEMIMC3.EEICM0] 1b1: When TPEMIMC3.EEIM0 is set to 1b1 ETHA0 Error Interrupt are mapped to.." "0,1"
bitfld.long 0x00 0. "EEIM0,ETHA0 Error Interrupt Mapping Values: 1b0: ETHA0 Error Interrupt are mapped to race_ etha0_error_int 1b1: ETHA0 Error Interrupt are mapped to a specific core depending on TPEMIMC3.EEIGM0 register ETHA0 Error Interrupt contain the following.." "0,1"
group.long 0x10++0x03
line.long 0x00 "TPEMIMC4,"
hexmask.long.word 0x00 23.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 20.--22. "RSICM1,RMAC1 Status Interrupt Core Mapping Functions: Used to decide to which pin RMAC1 Status Interrupt are mapped when mapped to a GWCA" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 18.--19. "RSV1,Reserved area" "0,1,2,3"
bitfld.long 0x00 17. "RSIGM1,RMAC1 Status Interrupt GWCA Mapping Values: 1b0: When TPEMIMC4.RSIM1 is set to 1b1 RMAC1 Status Interrupt are mapped to race_gwca0_core_int[TPEMIMC4.RSICM1] 1b1: When TPEMIMC4.RSIM1 is set to 1b1 RMAC1 Status Interrupt are mapped to.." "0,1"
bitfld.long 0x00 16. "RSIM1,RMAC1 Status Interrupt Mapping Values: 1b0: RMAC1 Status Interrupt are mapped to race_ rmac1_status_int 1b1: RMAC1 Status Interrupt are mapped to a specific core depending on TPEMIMC4.RSIGM1 register RMAC1 Status Interrupt contain the following.." "0,1"
rbitfld.long 0x00 15. "RSV2,Reserved area" "0,1"
bitfld.long 0x00 12.--14. "ESICM1,ETHA1 Status Interrupt Core Mapping Functions: Used to decide to which pin ETHA1 Status Interrupt are mapped when mapped to a GWCA" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 10.--11. "RSV3,Reserved area" "0,1,2,3"
bitfld.long 0x00 9. "ESIGM1,ETHA1 Status Interrupt GWCA Mapping Values: 1b0: When TPEMIMC4.ESIM1 is set to 1b1 ETHA1 Status Interrupt are mapped to race_gwca0_core_int[TPEMIMC4.ESICM1] 1b1: When TPEMIMC4.ESIM1 is set to 1b1 ETHA1 Status Interrupt are mapped to.." "0,1"
bitfld.long 0x00 8. "ESIM1,ETHA1 Status Interrupt Mapping Values: 1b0: ETHA1 Status Interrupt are mapped to race_ etha1_status_int 1b1: ETHA1 Status Interrupt are mapped to a specific core depending on TPEMIMC4.ESIGM1 register ETHA1 Status Interrupt contain the following.." "0,1"
newline
rbitfld.long 0x00 7. "RSV4,Reserved area" "0,1"
bitfld.long 0x00 4.--6. "EEICM1,ETHA1 Error Interrupt Core Mapping Functions: Used to decide to which pin ETHA1 Error Interrupt are mapped when mapped to a GWCA" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 2.--3. "RSV5,Reserved area" "0,1,2,3"
bitfld.long 0x00 1. "EEIGM1,ETHA1 Error Interrupt GWCA Mapping Values: 1b0: When TPEMIMC4.EEIM1 is set to 1b1 ETHA1 Error Interrupt are mapped to race_gwca0_core_int[TPEMIMC4.EEICM1] 1b1: When TPEMIMC4.EEIM1 is set to 1b1 ETHA1 Error Interrupt are mapped to.." "0,1"
bitfld.long 0x00 0. "EEIM1,ETHA1 Error Interrupt Mapping Values: 1b0: ETHA1 Error Interrupt are mapped to race_ etha1_error_int 1b1: ETHA1 Error Interrupt are mapped to a specific core depending on TPEMIMC4.EEIGM1 register ETHA1 Error Interrupt contain the following.." "0,1"
group.long 0x14++0x03
line.long 0x00 "TPEMIMC5,"
hexmask.long.word 0x00 23.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 20.--22. "RSICM2,RMAC2 Status Interrupt Core Mapping Functions: Used to decide to which pin RMAC2 Status Interrupt are mapped when mapped to a GWCA" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 18.--19. "RSV1,Reserved area" "0,1,2,3"
bitfld.long 0x00 17. "RSIGM2,RMAC2 Status Interrupt GWCA Mapping Values: 1b0: When TPEMIMC5.RSIM2 is set to 1b1 RMAC2 Status Interrupt are mapped to race_gwca0_core_int[TPEMIMC5.RSICM2] 1b1: When TPEMIMC5.RSIM2 is set to 1b1 RMAC2 Status Interrupt are mapped to.." "0,1"
bitfld.long 0x00 16. "RSIM2,RMAC2 Status Interrupt Mapping Values: 1b0: RMAC2 Status Interrupt are mapped to race_ rmac2_status_int 1b1: RMAC2 Status Interrupt are mapped to a specific core depending on TPEMIMC5.RSIGM2 register RMAC2 Status Interrupt contain the following.." "0,1"
rbitfld.long 0x00 15. "RSV2,Reserved area" "0,1"
bitfld.long 0x00 12.--14. "ESICM2,ETHA2 Status Interrupt Core Mapping Functions: Used to decide to which pin ETHA2 Status Interrupt are mapped when mapped to a GWCA" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 10.--11. "RSV3,Reserved area" "0,1,2,3"
bitfld.long 0x00 9. "ESIGM2,ETHA2 Status Interrupt GWCA Mapping Values: 1b0: When TPEMIMC5.ESIM2 is set to 1b1 ETHA2 Status Interrupt are mapped to race_gwca0_core_int[TPEMIMC5.ESICM2] 1b1: When TPEMIMC5.ESIM2 is set to 1b1 ETHA2 Status Interrupt are mapped to.." "0,1"
bitfld.long 0x00 8. "ESIM2,ETHA2 Status Interrupt Mapping Values: 1b0: ETHA2 Status Interrupt are mapped to race_ etha2_status_int 1b1: ETHA2 Status Interrupt are mapped to a specific core depending on TPEMIMC5.ESIGM2 register ETHA2 Status Interrupt contain the following.." "0,1"
newline
rbitfld.long 0x00 7. "RSV4,Reserved area" "0,1"
bitfld.long 0x00 4.--6. "EEICM2,ETHA2 Error Interrupt Core Mapping Functions: Used to decide to which pin ETHA2 Error Interrupt are mapped when mapped to a GWCA" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 2.--3. "RSV5,Reserved area" "0,1,2,3"
bitfld.long 0x00 1. "EEIGM2,ETHA2 Error Interrupt GWCA Mapping Values: 1b0: When TPEMIMC5.EEIM2 is set to 1b1 ETHA2 Error Interrupt are mapped to race_gwca0_core_int[TPEMIMC5.EEICM2] 1b1: When TPEMIMC5.EEIM2 is set to 1b1 ETHA2 Error Interrupt are mapped to.." "0,1"
bitfld.long 0x00 0. "EEIM2,ETHA2 Error Interrupt Mapping Values: 1b0: ETHA2 Error Interrupt are mapped to race_ etha2_error_int 1b1: ETHA2 Error Interrupt are mapped to a specific core depending on TPEMIMC5.EEIGM2 register ETHA2 Error Interrupt contain the following.." "0,1"
repeat 2. (strings "60" "61" )(list 0x0 0x4 )
group.long ($2+0x80)++0x03
line.long 0x00 "TPEMIMC$1,"
hexmask.long.tbyte 0x00 12.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 9.--11. "GTSICM1t,GWCA1 TimeStamp Interrupt Core Mapping t Functions: Map GWCA1 TimeStamp Interrupts t to race_gwca1_core_int[TPEMIMC6t.GTSICM1t] when TPEMIMC6t" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8. "GTSIM1t,GWCA1 TimeStamp Interrupt Mapping t Values: 1b0: GWCA1 TimeStamp Interrupt t are mapped to race_gwca1_timer_int[t] 1b1: GWCA1 TimeStamp Interrupt t are mapped to race_gwca1_core_int depending on TPEMIMC6t.GTSICM1t setting GWCA1 TimeStamp.." "0,1"
rbitfld.long 0x00 4.--7. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1.--3. "GTSICM0t,GWCA0 TimeStamp Interrupt Core Mapping t Functions: Map GWCA0 TimeStamp Interrupts t to race_gwca0_core_int[TPEMIMC6t.GTSICM0t] when TPEMIMC6t" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "GTSIM0t,GWCA0 TimeStamp Interrupt Mapping t Values: 1b0: GWCA0 TimeStamp Interrupt t are mapped to race_gwca0_timer_int[t] 1b1: GWCA0 TimeStamp Interrupt t are mapped to race_gwca0_core_int depending on TPEMIMC6t.GTSICM0t setting GWCA0 TimeStamp.." "0,1"
repeat.end
repeat 16. (strings "70" "71" "72" "73" "74" "75" "76" "77" "78" "79" "710" "711" "712" "713" "714" "715" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x100)++0x03
line.long 0x00 "TPEMIMC$1,"
hexmask.long.tbyte 0x00 11.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 8.--10. "GDICM1t,GWCA1 Data Interrupt Core Mapping t Functions: Map GWCA1 Data Interrupts t to race_gwca1_core_int[TPEMIMC7t. GDICM1t] RMAC2 Status Interrupt contain the following interrupts: GWDISi.DISt for GWCA1 [GWCA] GWEIS2i.DFESt for GWCA1 [GWCA].." "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 3.--7. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--2. "GDICM0t,GWCA0 Data Interrupt Core Mapping t Functions: Map GWCA0 Data Interrupts t to race_gwca0_core_int[TPEMIMC7t. GDICM0t] RMAC2 Status Interrupt contain the following interrupts: GWDISi.DISt for GWCA0 [GWCA] GWEIS2i.DFESt for GWCA0 [GWCA].." "0,1,2,3,4,5,6,7"
repeat.end
repeat 16. (strings "716" "717" "718" "719" "720" "721" "722" "723" "724" "725" "726" "727" "728" "729" "730" "731" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x140)++0x03
line.long 0x00 "TPEMIMC$1,"
hexmask.long.tbyte 0x00 11.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 8.--10. "GDICM1t,GWCA1 Data Interrupt Core Mapping t Functions: Map GWCA1 Data Interrupts t to race_gwca1_core_int[TPEMIMC7t. GDICM1t] RMAC2 Status Interrupt contain the following interrupts: GWDISi.DISt for GWCA1 [GWCA] GWEIS2i.DFESt for GWCA1 [GWCA].." "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 3.--7. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--2. "GDICM0t,GWCA0 Data Interrupt Core Mapping t Functions: Map GWCA0 Data Interrupts t to race_gwca0_core_int[TPEMIMC7t. GDICM0t] RMAC2 Status Interrupt contain the following interrupts: GWDISi.DISt for GWCA0 [GWCA] GWEIS2i.DFESt for GWCA0 [GWCA].." "0,1,2,3,4,5,6,7"
repeat.end
repeat 16. (strings "732" "733" "734" "735" "736" "737" "738" "739" "740" "741" "742" "743" "744" "745" "746" "747" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x180)++0x03
line.long 0x00 "TPEMIMC$1,"
hexmask.long.tbyte 0x00 11.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 8.--10. "GDICM1t,GWCA1 Data Interrupt Core Mapping t Functions: Map GWCA1 Data Interrupts t to race_gwca1_core_int[TPEMIMC7t. GDICM1t] RMAC2 Status Interrupt contain the following interrupts: GWDISi.DISt for GWCA1 [GWCA] GWEIS2i.DFESt for GWCA1 [GWCA].." "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 3.--7. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--2. "GDICM0t,GWCA0 Data Interrupt Core Mapping t Functions: Map GWCA0 Data Interrupts t to race_gwca0_core_int[TPEMIMC7t. GDICM0t] RMAC2 Status Interrupt contain the following interrupts: GWDISi.DISt for GWCA0 [GWCA] GWEIS2i.DFESt for GWCA0 [GWCA].." "0,1,2,3,4,5,6,7"
repeat.end
repeat 16. (strings "748" "749" "750" "751" "752" "753" "754" "755" "756" "757" "758" "759" "760" "761" "762" "763" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x1C0)++0x03
line.long 0x00 "TPEMIMC$1,"
hexmask.long.tbyte 0x00 11.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 8.--10. "GDICM1t,GWCA1 Data Interrupt Core Mapping t Functions: Map GWCA1 Data Interrupts t to race_gwca1_core_int[TPEMIMC7t. GDICM1t] RMAC2 Status Interrupt contain the following interrupts: GWDISi.DISt for GWCA1 [GWCA] GWEIS2i.DFESt for GWCA1 [GWCA].." "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 3.--7. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--2. "GDICM0t,GWCA0 Data Interrupt Core Mapping t Functions: Map GWCA0 Data Interrupts t to race_gwca0_core_int[TPEMIMC7t. GDICM0t] RMAC2 Status Interrupt contain the following interrupts: GWDISi.DISt for GWCA0 [GWCA] GWEIS2i.DFESt for GWCA0 [GWCA].." "0,1,2,3,4,5,6,7"
repeat.end
repeat 16. (strings "764" "765" "766" "767" "768" "769" "770" "771" "772" "773" "774" "775" "776" "777" "778" "779" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x200)++0x03
line.long 0x00 "TPEMIMC$1,"
hexmask.long.tbyte 0x00 11.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 8.--10. "GDICM1t,GWCA1 Data Interrupt Core Mapping t Functions: Map GWCA1 Data Interrupts t to race_gwca1_core_int[TPEMIMC7t. GDICM1t] RMAC2 Status Interrupt contain the following interrupts: GWDISi.DISt for GWCA1 [GWCA] GWEIS2i.DFESt for GWCA1 [GWCA].." "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 3.--7. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--2. "GDICM0t,GWCA0 Data Interrupt Core Mapping t Functions: Map GWCA0 Data Interrupts t to race_gwca0_core_int[TPEMIMC7t. GDICM0t] RMAC2 Status Interrupt contain the following interrupts: GWDISi.DISt for GWCA0 [GWCA] GWEIS2i.DFESt for GWCA0 [GWCA].." "0,1,2,3,4,5,6,7"
repeat.end
repeat 16. (strings "780" "781" "782" "783" "784" "785" "786" "787" "788" "789" "790" "791" "792" "793" "794" "795" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x240)++0x03
line.long 0x00 "TPEMIMC$1,"
hexmask.long.tbyte 0x00 11.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 8.--10. "GDICM1t,GWCA1 Data Interrupt Core Mapping t Functions: Map GWCA1 Data Interrupts t to race_gwca1_core_int[TPEMIMC7t. GDICM1t] RMAC2 Status Interrupt contain the following interrupts: GWDISi.DISt for GWCA1 [GWCA] GWEIS2i.DFESt for GWCA1 [GWCA].." "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 3.--7. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--2. "GDICM0t,GWCA0 Data Interrupt Core Mapping t Functions: Map GWCA0 Data Interrupts t to race_gwca0_core_int[TPEMIMC7t. GDICM0t] RMAC2 Status Interrupt contain the following interrupts: GWDISi.DISt for GWCA0 [GWCA] GWEIS2i.DFESt for GWCA0 [GWCA].." "0,1,2,3,4,5,6,7"
repeat.end
repeat 16. (strings "796" "797" "798" "799" "7100" "7101" "7102" "7103" "7104" "7105" "7106" "7107" "7108" "7109" "7110" "7111" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x280)++0x03
line.long 0x00 "TPEMIMC$1,"
hexmask.long.tbyte 0x00 11.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 8.--10. "GDICM1t,GWCA1 Data Interrupt Core Mapping t Functions: Map GWCA1 Data Interrupts t to race_gwca1_core_int[TPEMIMC7t. GDICM1t] RMAC2 Status Interrupt contain the following interrupts: GWDISi.DISt for GWCA1 [GWCA] GWEIS2i.DFESt for GWCA1 [GWCA].." "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 3.--7. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--2. "GDICM0t,GWCA0 Data Interrupt Core Mapping t Functions: Map GWCA0 Data Interrupts t to race_gwca0_core_int[TPEMIMC7t. GDICM0t] RMAC2 Status Interrupt contain the following interrupts: GWDISi.DISt for GWCA0 [GWCA] GWEIS2i.DFESt for GWCA0 [GWCA].." "0,1,2,3,4,5,6,7"
repeat.end
repeat 16. (strings "7112" "7113" "7114" "7115" "7116" "7117" "7118" "7119" "7120" "7121" "7122" "7123" "7124" "7125" "7126" "7127" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x2C0)++0x03
line.long 0x00 "TPEMIMC$1,"
hexmask.long.tbyte 0x00 11.--31. 1. "RSV0,Reserved area"
bitfld.long 0x00 8.--10. "GDICM1t,GWCA1 Data Interrupt Core Mapping t Functions: Map GWCA1 Data Interrupts t to race_gwca1_core_int[TPEMIMC7t. GDICM1t] RMAC2 Status Interrupt contain the following interrupts: GWDISi.DISt for GWCA1 [GWCA] GWEIS2i.DFESt for GWCA1 [GWCA].." "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 3.--7. "RSV1,Reserved area" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--2. "GDICM0t,GWCA0 Data Interrupt Core Mapping t Functions: Map GWCA0 Data Interrupts t to race_gwca0_core_int[TPEMIMC7t. GDICM0t] RMAC2 Status Interrupt contain the following interrupts: GWDISi.DISt for GWCA0 [GWCA] GWEIS2i.DFESt for GWCA0 [GWCA].." "0,1,2,3,4,5,6,7"
repeat.end
group.long 0x700++0x03
line.long 0x00 "TSIM,"
hexmask.long 0x00 7.--31. 1. "RSV,Reserved area"
rbitfld.long 0x00 6. "EIM2,ETHA2 Interrupt Monitoring Values: 1b0: No interrupt is set in ETHA2 1b1: An interrupt is set in ETHA2" "0,1"
rbitfld.long 0x00 5. "EIM1,ETHA1 Interrupt Monitoring Values: 1b0: No interrupt is set in ETHA1 1b1: An interrupt is set in ETHA1" "0,1"
rbitfld.long 0x00 4. "EIM0,ETHA0 Interrupt Monitoring Values: 1b0: No interrupt is set in ETHA0 1b1: An interrupt is set in ETHA0" "0,1"
rbitfld.long 0x00 3. "GIM1,GWCA1 Interrupt Monitoring Values: 1b0: No interrupt is set in GWCA1 1b1: An interrupt is set in GWCA1" "0,1"
rbitfld.long 0x00 2. "GIM0,GWCA0 Interrupt Monitoring Values: 1b0: No interrupt is set in GWCA0 1b1: An interrupt is set in GWCA0" "0,1"
rbitfld.long 0x00 1. "CIM,Common Interrupt Mirroring Values: 1b0: No interrupt is set in common agent 1b1: An interrupt is set in common agent" "0,1"
rbitfld.long 0x00 0. "FWM,Forwarding engine Interrupt Mirroring Values: 1b0: No interrupt is set in forwarding engine 1b1: An interrupt is set in forwarding engine" "0,1"
group.long 0x704++0x03
line.long 0x00 "TFIM,"
hexmask.long.tbyte 0x00 10.--31. 1. "RSV,Reserved area"
rbitfld.long 0x00 9. "FWMISIM0,FWMIS0 Interrupt Mirroring Values: 1b0: No interrupt is set in forwarding engine FWMIS0 register 1b1: An interrupt is set in forwarding engine FWMIS0 register" "0,1"
rbitfld.long 0x00 8. "FWEISIM8,FWEIS8 Interrupt Mirroring Values: 1b0: No interrupt is set in forwarding engine FWEIS8 register 1b1: An interrupt is set in forwarding engine FWEIS8 register" "0,1"
rbitfld.long 0x00 7. "FWEISIM7,FWEIS7 Interrupt Mirroring Values: 1b0: No interrupt is set in forwarding engine FWEIS7 register 1b1: An interrupt is set in forwarding engine FWEIS7 register" "0,1"
rbitfld.long 0x00 6. "FWEISIM6,FWEIS6 Interrupt Mirroring Values: 1b0: No interrupt is set in forwarding engine FWEIS6 register 1b1: An interrupt is set in forwarding engine FWEIS6 register" "0,1"
rbitfld.long 0x00 5. "FWEISIM5,FWEIS5 Interrupt Mirroring Values: 1b0: No interrupt is set in forwarding engine FWEIS5 register 1b1: An interrupt is set in forwarding engine FWEIS5 register" "0,1"
rbitfld.long 0x00 4. "FWEISIM4,FWEIS4 Interrupt Mirroring Values: 1b0: No interrupt is set in forwarding engine FWEIS4 register 1b1: An interrupt is set in forwarding engine FWEIS4 register" "0,1"
rbitfld.long 0x00 3. "FWEISIM3,FWEIS3 Interrupt Mirroring Values: 1b0: No interrupt is set in forwarding engine FWEIS3 register 1b1: An interrupt is set in forwarding engine FWEIS3 register" "0,1"
rbitfld.long 0x00 2. "FWEISIM2,FWEIS2 Interrupt Mirroring Values: 1b0: No interrupt is set in forwarding engine FWEIS2 register 1b1: An interrupt is set in forwarding engine FWEIS2 register" "0,1"
rbitfld.long 0x00 1. "FWEISIM1,FWEIS1 Interrupt Mirroring Values: 1b0: No interrupt is set in forwarding engine FWEIS1 register 1b1: An interrupt is set in forwarding engine FWEIS1 register" "0,1"
newline
rbitfld.long 0x00 0. "FWEISIM0,FWEIS0 Interrupt Mirroring Values: 1b0: No interrupt is set in forwarding engine FWEIS0 register 1b1: An interrupt is set in forwarding engine FWEIS0 register" "0,1"
group.long 0x708++0x03
line.long 0x00 "TCIM,"
hexmask.long 0x00 5.--31. 1. "RSV,Reserved area"
rbitfld.long 0x00 4. "CAMISIM1,CAMIS1 Interrupt Mirroring Values: 1b0: No interrupt is set in Common agent CAMIS1 register 1b1: An interrupt is set in Common agent CAMIS1 register" "0,1"
rbitfld.long 0x00 3. "CAMISIM0,CAMIS0 Interrupt Mirroring Values: 1b0: No interrupt is set in Common agent CAMIS0 register 1b1: An interrupt is set in Common agent CAMIS0 register" "0,1"
rbitfld.long 0x00 2. "CAEISIM1,CAEIS1 Interrupt Mirroring Values: 1b0: No interrupt is set in Common agent CAEIS1 register 1b1: An interrupt is set in Common agent CAEIS1 register" "0,1"
rbitfld.long 0x00 1. "CAEISIM0,CAEIS0 Interrupt Mirroring Values: 1b0: No interrupt is set in Common agent CAEIS0 register 1b1: An interrupt is set in Common agent CAEIS0 register" "0,1"
rbitfld.long 0x00 0. "RSSISIM,RSSIS Interrupt Mirroring Values: 1b0: No interrupt is set in Common agent RSSIS register 1b1: An interrupt is set in Common agent RSSIS register" "0,1"
group.long 0x710++0x03
line.long 0x00 "TGIM0,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
rbitfld.long 0x00 7. "GWEISIM5,GWEIS5 Interrupt Mirroring Values: 1b0: No interrupt is set in GWCA0 GWEIS5 register 1b1: An interrupt is set in GWCA0 GWEIS5 register" "0,1"
rbitfld.long 0x00 6. "GWEISIM4,GWEIS4 Interrupt Mirroring Values: 1b0: No interrupt is set in GWCA0 GWEIS4 register 1b1: An interrupt is set in GWCA0 GWEIS4 register" "0,1"
rbitfld.long 0x00 5. "GWEISIM3,GWEIS3 Interrupt Mirroring Values: 1b0: No interrupt is set in GWCA0 GWEIS3 register 1b1: An interrupt is set in GWCA0 GWEIS3 register" "0,1"
rbitfld.long 0x00 4. "GWEISIM2,GWEIS2 Interrupt Mirroring Values: 1b0: No interrupt is set in GWCA0 GWEIS2 register 1b1: An interrupt is set in GWCA0 GWEIS2 register" "0,1"
rbitfld.long 0x00 3. "GWEISIM1,GWEIS1 Interrupt Mirroring Values: 1b0: No interrupt is set in GWCA0 GWEIS1 register 1b1: An interrupt is set in GWCA0 GWEIS1 register" "0,1"
rbitfld.long 0x00 2. "GWEISIM0,GWEIS0 Interrupt Mirroring Values: 1b0: No interrupt is set in GWCA0 GWEIS0 register 1b1: An interrupt is set in GWCA0 GWEIS0 register" "0,1"
rbitfld.long 0x00 1. "GWTSDISIM,GWTSDIS Interrupt Mirroring Values: 1b0: No interrupt is set in GWCA0 GWTSDIS register 1b1: An interrupt is set in GWCA0 GWTSDIS register" "0,1"
rbitfld.long 0x00 0. "GWDISIM,GWDIS Interrupt Mirroring Values: 1b0: No interrupt is set in GWCA0 GWDIS register 1b1: An interrupt is set in GWCA0 GWDIS register" "0,1"
group.long 0x714++0x03
line.long 0x00 "TGIM1,"
hexmask.long.tbyte 0x00 8.--31. 1. "RSV,Reserved area"
rbitfld.long 0x00 7. "GWEISIM5,GWEIS5 Interrupt Mirroring Values: 1b0: No interrupt is set in GWCA1 GWEIS5 register 1b1: An interrupt is set in GWCA1 GWEIS5 register" "0,1"
rbitfld.long 0x00 6. "GWEISIM4,GWEIS4 Interrupt Mirroring Values: 1b0: No interrupt is set in GWCA1 GWEIS4 register 1b1: An interrupt is set in GWCA1 GWEIS4 register" "0,1"
rbitfld.long 0x00 5. "GWEISIM3,GWEIS3 Interrupt Mirroring Values: 1b0: No interrupt is set in GWCA1 GWEIS3 register 1b1: An interrupt is set in GWCA1 GWEIS3 register" "0,1"
rbitfld.long 0x00 4. "GWEISIM2,GWEIS2 Interrupt Mirroring Values: 1b0: No interrupt is set in GWCA1 GWEIS2 register 1b1: An interrupt is set in GWCA1 GWEIS2 register" "0,1"
rbitfld.long 0x00 3. "GWEISIM1,GWEIS1 Interrupt Mirroring Values: 1b0: No interrupt is set in GWCA1 GWEIS1 register 1b1: An interrupt is set in GWCA1 GWEIS1 register" "0,1"
rbitfld.long 0x00 2. "GWEISIM0,GWEIS0 Interrupt Mirroring Values: 1b0: No interrupt is set in GWCA1 GWEIS0 register 1b1: An interrupt is set in GWCA1 GWEIS0 register" "0,1"
rbitfld.long 0x00 1. "GWTSDISIM,GWTSDIS Interrupt Mirroring Values: 1b0: No interrupt is set in GWCA1 GWTSDIS register 1b1: An interrupt is set in GWCA1 GWTSDIS register" "0,1"
rbitfld.long 0x00 0. "GWDISIM,GWDIS Interrupt Mirroring Values: 1b0: No interrupt is set in GWCA1 GWDIS register 1b1: An interrupt is set in GWCA1 GWDIS register" "0,1"
group.long 0x720++0x03
line.long 0x00 "TEIM0,"
hexmask.long 0x00 5.--31. 1. "RSV,Reserved area"
rbitfld.long 0x00 4. "MMISIM,MMIS0 Interrupt Mirroring Values: 1b0: No interrupt is set in ETHA0 RMAC MMIS0 register 1b1: An interrupt is set in ETHA0 RMAC MMIS0 register" "0,1"
rbitfld.long 0x00 3. "MEISIM,MEIS Interrupt Mirroring Values: 1b0: No interrupt is set in ETHA0 RMAC MEIS register 1b1: An interrupt is set in ETHA0 RMAC MEIS register" "0,1"
rbitfld.long 0x00 2. "EAEISIM2,EAEIS2 Interrupt Mirroring Values: 1b0: No interrupt is set in ETHA0 EAEIS2 register 1b1: An interrupt is set in ETHA0 EAEIS2 register" "0,1"
rbitfld.long 0x00 1. "EAEISIM1,EAEIS1 Interrupt Mirroring Values: 1b0: No interrupt is set in ETHA0 EAEIS1 register 1b1: An interrupt is set in ETHA0 EAEIS1 register" "0,1"
rbitfld.long 0x00 0. "EAEISIM0,EAEIS0 Interrupt Mirroring Values: 1b0: No interrupt is set in ETHA0 EAEIS0 register 1b1: An interrupt is set in ETHA0 EAEIS0 register" "0,1"
group.long 0x724++0x03
line.long 0x00 "TEIM1,"
hexmask.long 0x00 5.--31. 1. "RSV,Reserved area"
rbitfld.long 0x00 4. "MMISIM,MMIS0 Interrupt Mirroring Values: 1b0: No interrupt is set in ETHA1 RMAC MMIS0 register 1b1: An interrupt is set in ETHA1 RMAC MMIS0 register" "0,1"
rbitfld.long 0x00 3. "MEISIM,MEIS Interrupt Mirroring Values: 1b0: No interrupt is set in ETHA1 RMAC MEIS register 1b1: An interrupt is set in ETHA1 RMAC MEIS register" "0,1"
rbitfld.long 0x00 2. "EAEISIM2,EAEIS2 Interrupt Mirroring Values: 1b0: No interrupt is set in ETHA1 EAEIS2 register 1b1: An interrupt is set in ETHA1 EAEIS2 register" "0,1"
rbitfld.long 0x00 1. "EAEISIM1,EAEIS1 Interrupt Mirroring Values: 1b0: No interrupt is set in ETHA1 EAEIS1 register 1b1: An interrupt is set in ETHA1 EAEIS1 register" "0,1"
rbitfld.long 0x00 0. "EAEISIM0,EAEIS0 Interrupt Mirroring Values: 1b0: No interrupt is set in ETHA1 EAEIS0 register 1b1: An interrupt is set in ETHA1 EAEIS0 register" "0,1"
group.long 0x728++0x03
line.long 0x00 "TEIM2,"
hexmask.long 0x00 5.--31. 1. "RSV,Reserved area"
rbitfld.long 0x00 4. "MMISIM,MMIS0 Interrupt Mirroring Values: 1b0: No interrupt is set in ETHA2 RMAC MMIS0 register 1b1: An interrupt is set in ETHA2 RMAC MMIS0 register" "0,1"
rbitfld.long 0x00 3. "MEISIM,MEIS Interrupt Mirroring Values: 1b0: No interrupt is set in ETHA2 RMAC MEIS register 1b1: An interrupt is set in ETHA2 RMAC MEIS register" "0,1"
rbitfld.long 0x00 2. "EAEISIM2,EAEIS2 Interrupt Mirroring Values: 1b0: No interrupt is set in ETHA2 EAEIS2 register 1b1: An interrupt is set in ETHA2 EAEIS2 register" "0,1"
rbitfld.long 0x00 1. "EAEISIM1,EAEIS1 Interrupt Mirroring Values: 1b0: No interrupt is set in ETHA2 EAEIS1 register 1b1: An interrupt is set in ETHA2 EAEIS1 register" "0,1"
rbitfld.long 0x00 0. "EAEISIM0,EAEIS0 Interrupt Mirroring Values: 1b0: No interrupt is set in ETHA2 EAEIS0 register 1b1: An interrupt is set in ETHA2 EAEIS0 register" "0,1"
tree.end
tree "ETHERNET_SWITCH_SRAM"
base ad:0xE643B000
group.long 0x00++0x03
line.long 0x00 "RSW_n_MS,This register is accessible in both of User Mode and Error Injection Mode"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved (R.F.U)"
bitfld.long 0x00 0. "MS,Mode Select" "0: User Mode,1: Error Injection Mode"
group.long 0x04++0x03
line.long 0x00 "RSW_n_RS0,Please don't set multiple bits to 1"
bitfld.long 0x00 27.--31. "Reserved_27,Reserved (R.F.U)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 26. "RACE,Select R-ACE Data RAM" "0: not selected,1: selected"
bitfld.long 0x00 25. "RTAG,Select TAG RAM" "0: not selected,1: selected"
newline
bitfld.long 0x00 24. "RPTR,Select Pointer RAM" "0: not selected,1: selected"
bitfld.long 0x00 23. "RRJT,Select Descriptor reject RAM" "0: not selected,1: selected"
bitfld.long 0x00 22. "RBPR,Select Buffer pointer RAM" "0: not selected,1: selected"
newline
bitfld.long 0x00 21. "RL3F,Select L3 Filter table RAM" "0: not selected,1: selected"
bitfld.long 0x00 20. "RFRER,Select FRER RAM" "0: not selected,1: selected"
bitfld.long 0x00 19. "RPSFP,Select PSFP gate RAM" "0: not selected,1: selected"
newline
bitfld.long 0x00 18. "RATS,Select ATS RAM" "0: not selected,1: selected"
bitfld.long 0x00 17. "RMAC,Select MAC table RAM" "0: not selected,1: selected"
bitfld.long 0x00 16. "RVLAN,Select VLAN table RAM" "0: not selected,1: selected"
newline
bitfld.long 0x00 15. "RL3IP,Select L3 IP address table RAM" "0: not selected,1: selected"
bitfld.long 0x00 14. "RL23U,Select L2 L3 Update RAM" "0: not selected,1: selected"
bitfld.long 0x00 13. "READS0,Select Ethernet agent descriptor RAM 0" "0: not selected,1: selected"
newline
bitfld.long 0x00 12. "REATCL0,Select Ethernet agent TAS control list RAM 0" "0: not selected,1: selected"
bitfld.long 0x00 11. "READS1,Select Ethernet agent descriptor RAM 1" "0: not selected,1: selected"
bitfld.long 0x00 10. "REATCL1,Select Ethernet agent TAS control list RAM 1" "0: not selected,1: selected"
newline
bitfld.long 0x00 9. "READS2,Select Ethernet agent descriptor RAM 2" "0: not selected,1: selected"
bitfld.long 0x00 8. "REATCL2,Select Ethernet agent TAS control list RAM 2" "0: not selected,1: selected"
bitfld.long 0x00 7. "RGAAD0,Select GWCA AXI address RAM 0" "0: not selected,1: selected"
newline
bitfld.long 0x00 6. "RGADS0,Select GWCA descriptor RAM 0" "0: not selected,1: selected"
bitfld.long 0x00 5. "RGARM0,Select GWCA RX multicast RAM 0" "0: not selected,1: selected"
bitfld.long 0x00 4. "RGATS0,Select GWCA Timestamp RAM 0" "0: not selected,1: selected"
newline
bitfld.long 0x00 3. "RGAAD1,Select GWCA AXI address RAM 1" "0: not selected,1: selected"
bitfld.long 0x00 2. "RGADS1,Select GWCA descriptor RAM 1" "0: not selected,1: selected"
bitfld.long 0x00 1. "RGARM1,Select GWCA RX multicast RAM 1" "0: not selected,1: selected"
newline
bitfld.long 0x00 0. "RGATS1,Select GWCA Timestamp RAM 1" "0: not selected,1: selected"
group.long 0x14++0x03
line.long 0x00 "RSW_n_SDAE,"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved (R.F.U)"
bitfld.long 0x00 0. "SDAEN,SRAM Direct Access Enable Enable to directly access the SRAM which is selected by RSWnRS" "0: Not enable is issued,1: 1 pulse enable is issued"
group.long 0x18++0x03
line.long 0x00 "RSW_n_SDARWS,"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved (R.F.U)"
bitfld.long 0x00 0. "SDARWS,SRAM Direct Access Read Write Switch The SRAM selected by RSWnRS is avilable" "0: read,1: write"
group.long 0x1C++0x03
line.long 0x00 "RSW_n_SDAA,"
hexmask.long.tbyte 0x00 15.--31. 1. "Reserved_15,Reserved (R.F.U)"
hexmask.long.word 0x00 0.--14. 1. "SDAA,SRAM Direct Access Address Write address to access the SRAM which is selected by RSWnRS"
repeat 7. (strings "0" "1" "2" "3" "4" "5" "6" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 )
group.long ($2+0x20)++0x03
line.long 0x00 "RSW_n_SDWD$1,SRAM Direct Write Data 6 corresponds to write data size _223:192_"
hexmask.long 0x00 0.--31. 1. "SDWDi,SRAM Direct Write Data i (i = 0 to 6) The SRAM selected by RSWnRS is avilable"
repeat.end
repeat 7. (strings "0" "1" "2" "3" "4" "5" "6" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 )
group.long ($2+0x64)++0x03
line.long 0x00 "RSW_n_SDRD$1,SRAM Direct Read Data 6 corresponds to read data size _223:192_"
hexmask.long 0x00 0.--31. 1. "SDRDi,SRAM Direct Read Data i (i = 0 to 6) The SRAM selected by RSWnRS is avilable"
repeat.end
group.long 0xA8++0x03
line.long 0x00 "RSW_n_WDEIE,"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved (R.F.U)"
bitfld.long 0x00 0. "WDEIEN,Write Data Error Injection Enable Enable to convert value of RSWnSDWDi which correspond to RSWnWDEIBSi written as 1" "0: Not enable is issued,1: 1 pulse enable is issued"
group.long 0xAC++0x03
line.long 0x00 "RSW_n_RDEIE,"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved (R.F.U)"
bitfld.long 0x00 0. "RDEIEN,Read Data Error Injection Enable Enable to convert value of RSWnSDRDi which correspond to RSWnRDEIBSi written as 1" "0: Not enable is issued,1: 1 pulse enable is issued"
repeat 7. (strings "0" "1" "2" "3" "4" "5" "6" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 )
group.long ($2+0xB0)++0x03
line.long 0x00 "RSW_n_WDEIBS$1,Write Data Error Injection Bit Select 6 corresponds to write data size _223:192_"
hexmask.long 0x00 0.--31. 1. "WDEIBSi,Write Data Error Injection Bit Select i (i = 0 to 6) The SRAM selected by RSWnRS is avilable"
repeat.end
repeat 7. (strings "0" "1" "2" "3" "4" "5" "6" )(list 0x0 0x4 0x8 0x0C 0x10 0x14 0x18 )
group.long ($2+0xF4)++0x03
line.long 0x00 "RSW_n_RDEIBS$1,Read Data Error Injection Bit Select 6 corresponds to read data size _223:192_"
hexmask.long 0x00 0.--31. 1. "RDEIBSi,Read Data Error Injection Bit Select i (i = 0 to 6) The SRAM selected by RSWnRS is avilable"
repeat.end
group.long 0x138++0x03
line.long 0x00 "RSW_n_EECE0,This register is accessible in both of User Mode and Error Injection Mode"
bitfld.long 0x00 27.--31. "Reserved_27,Reserved (R.F.U)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 26. "ECACE,ECC Error Correct of R-ACE Data RAM" "0: not correct,1: correct"
bitfld.long 0x00 25. "ECTAG,ECC Error Correct of TAG RAM" "0: not correct,1: correct"
newline
bitfld.long 0x00 24. "ECPTR,ECC Error Correct of Pointer RAM" "0: not correct,1: correct"
bitfld.long 0x00 23. "ECRJT,ECC Error Correct of Descriptor reject RAM" "0: not correct,1: correct"
bitfld.long 0x00 22. "ECBPR,ECC Error Correct of Buffer pointer RAM" "0: not correct,1: correct"
newline
bitfld.long 0x00 21. "ECL3F,ECC Error Correct of L3 Filter table RAM" "0: not correct,1: correct"
bitfld.long 0x00 20. "ECFRER,ECC Error Correct of FRER RAM" "0: not correct,1: correct"
bitfld.long 0x00 19. "ECPSFP,ECC Error Correct of PSFP gate RAM" "0: not correct,1: correct"
newline
bitfld.long 0x00 18. "ECATS,ECC Error Correct of ATS RAM" "0: not correct,1: correct"
bitfld.long 0x00 17. "ECMAC,ECC Error Correct of MAC table RAM" "0: not correct,1: correct"
bitfld.long 0x00 16. "ECVLAN,ECC Error Correct of VLAN table RAM" "0: not correct,1: correct"
newline
bitfld.long 0x00 15. "ECL3IP,ECC Error Correct of L3 IP address table RAM" "0: not correct,1: correct"
bitfld.long 0x00 14. "ECL23U,ECC Error Correct of L2 L3 Update RAM" "0: not correct,1: correct"
bitfld.long 0x00 13. "ECEADS0,ECC Error Correct of Ethernet agent descriptor RAM 0" "0: not correct,1: correct"
newline
bitfld.long 0x00 12. "ECEATCL0,ECC Error Correct of Ethernet agent TAS control list RAM 0" "0: not correct,1: correct"
bitfld.long 0x00 11. "ECEADS1,ECC Error Correct of Ethernet agent descriptor RAM 1" "0: not correct,1: correct"
bitfld.long 0x00 10. "ECEATCL1,ECC Error Correct of Ethernet agent TAS control list RAM 1" "0: not correct,1: correct"
newline
bitfld.long 0x00 9. "ECEADS2,ECC Error Correct of Ethernet agent descriptor RAM 2" "0: not correct,1: correct"
bitfld.long 0x00 8. "ECEATCL2,ECC Error Correct of Ethernet agent TAS control list RAM 2" "0: not correct,1: correct"
bitfld.long 0x00 7. "ECGAAD0,ECC Error Correct of GWCA AXI address RAM 0" "0: not correct,1: correct"
newline
bitfld.long 0x00 6. "ECGADS0,ECC Error Correct of GWCA descriptor RAM 0" "0: not correct,1: correct"
bitfld.long 0x00 5. "ECGARM0,ECC Error Correct of GWCA RX multicast RAM 0" "0: not correct,1: correct"
bitfld.long 0x00 4. "ECGATS0,ECC Error Correct of GWCA Timestamp RAM 0" "0: not correct,1: correct"
newline
bitfld.long 0x00 3. "ECGAAD1,ECC Error Correct of GWCA AXI address RAM 1" "0: not correct,1: correct"
bitfld.long 0x00 2. "ECGADS1,ECC Error Correct of GWCA descriptor RAM 1" "0: not correct,1: correct"
bitfld.long 0x00 1. "ECGARM1,ECC Error Correct of GWCA RX multicast RAM 1" "0: not correct,1: correct"
newline
bitfld.long 0x00 0. "ECGATS1,ECC Error Correct of GWCA Timestamp RAM 1" "0: not correct,1: correct"
group.long 0x148++0x03
line.long 0x00 "RSW_n_EPS0,This register is accessible in Error Injection Mode"
bitfld.long 0x00 27.--31. "Reserved_27,Reserved (R.F.U)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 26. "EPSACE,ECC Path Select of R-ACE Data RAM" "0: bypass ECC,1: through ECC"
bitfld.long 0x00 25. "EPSTAG,ECC Path Select of TAG RAM" "0: bypass ECC,1: through ECC"
newline
bitfld.long 0x00 24. "EPSPTR,ECC Path Select of Pointer RAM" "0: bypass ECC,1: through ECC"
bitfld.long 0x00 23. "EPSRJT,ECC Path Select of Descriptor reject RAM" "0: bypass ECC,1: through ECC"
bitfld.long 0x00 22. "EPSBPR,ECC Path Select of Buffer pointer RAM" "0: bypass ECC,1: through ECC"
newline
bitfld.long 0x00 21. "EPSL3F,ECC Path Select of L3 Filter table RAM" "0: bypass ECC,1: through ECC"
bitfld.long 0x00 20. "EPSFRER,ECC Path Select of FRER RAM" "0: bypass ECC,1: through ECC"
bitfld.long 0x00 19. "EPSPSFP,ECC Path Select of PSFP gate RAM" "0: bypass ECC,1: through ECC"
newline
bitfld.long 0x00 18. "EPSATS,ECC Path Select of ATS RAM" "0: bypass ECC,1: through ECC"
bitfld.long 0x00 17. "EPSMAC,ECC Path Select of MAC table RAM" "0: bypass ECC,1: through ECC"
bitfld.long 0x00 16. "EPSVLAN,ECC Path Select of VLAN table RAM" "0: bypass ECC,1: through ECC"
newline
bitfld.long 0x00 15. "EPSL3IP,ECC Path Select of L3 IP address table RAM" "0: bypass ECC,1: through ECC"
bitfld.long 0x00 14. "EPSL23U,ECC Path Select of L2 L3 Update RAM" "0: bypass ECC,1: through ECC"
bitfld.long 0x00 13. "EPSEADS0,ECC Path Select of Ethernet agent descriptor RAM 0" "0: bypass ECC,1: through ECC"
newline
bitfld.long 0x00 12. "EPSEATCL0,ECC Path Select of Ethernet agent TAS control list RAM 0" "0: bypass ECC,1: through ECC"
bitfld.long 0x00 11. "EPSEADS1,ECC Path Select of Ethernet agent descriptor RAM 1" "0: bypass ECC,1: through ECC"
bitfld.long 0x00 10. "EPSEATCL1,ECC Path Select of Ethernet agent TAS control list RAM 1" "0: bypass ECC,1: through ECC"
newline
bitfld.long 0x00 9. "EPSEADS2,ECC Path Select of Ethernet agent descriptor RAM 2" "0: bypass ECC,1: through ECC"
bitfld.long 0x00 8. "EPSEATCL2,ECC Path Select of Ethernet agent TAS control list RAM 2" "0: bypass ECC,1: through ECC"
bitfld.long 0x00 7. "EPSGAAD0,ECC Path Select of GWCA AXI address RAM 0" "0: bypass ECC,1: through ECC"
newline
bitfld.long 0x00 6. "EPSGADS0,ECC Path Select of GWCA descriptor RAM 0" "0: bypass ECC,1: through ECC"
bitfld.long 0x00 5. "EPSGARM0,ECC Path Select of GWCA RX multicast RAM 0" "0: bypass ECC,1: through ECC"
bitfld.long 0x00 4. "EPSGATS0,ECC Path Select of GWCA Timestamp RAM 0" "0: bypass ECC,1: through ECC"
newline
bitfld.long 0x00 3. "EPSGAAD1,ECC Path Select of GWCA AXI address RAM 1" "0: bypass ECC,1: through ECC"
bitfld.long 0x00 2. "EPSGADS1,ECC Path Select of GWCA descriptor RAM 1" "0: bypass ECC,1: through ECC"
bitfld.long 0x00 1. "EPSGARM1,ECC Path Select of GWCA RX multicast RAM 1" "0: bypass ECC,1: through ECC"
newline
bitfld.long 0x00 0. "EPSGATS1,ECC Path Select of GWCA Timestamp RAM 1" "0: bypass ECC,1: through ECC"
group.long 0x158++0x03
line.long 0x00 "RSW_n_EOED0,This register is accessible in both of User Mode and Error Injection Mode"
rbitfld.long 0x00 27.--31. "Reserved_27,Reserved (R.F.U)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rbitfld.long 0x00 26. "OEDACE,One bit Error Detect of R-ACE Data RAM" "0: Not one bit error detected,1: One bit error detected"
rbitfld.long 0x00 25. "OEDTAG,One bit Error Detect of TAG RAM" "0: Not one bit error detected,1: One bit error detected"
newline
rbitfld.long 0x00 24. "OEDPTR,One bit Error Detect of Pointer RAM" "0: Not one bit error detected,1: One bit error detected"
rbitfld.long 0x00 23. "OEDRJT,One bit Error Detect of Descriptor reject RAM" "0: Not one bit error detected,1: One bit error detected"
rbitfld.long 0x00 22. "OEDBPR,One bit Error Detect of Buffer pointer RAM" "0: Not one bit error detected,1: One bit error detected"
newline
rbitfld.long 0x00 21. "OEDL3F,One bit Error Detect of L3 Filter table RAM" "0: Not one bit error detected,1: One bit error detected"
rbitfld.long 0x00 20. "OEDFRER,One bit Error Detect of FRER RAM" "0: Not one bit error detected,1: One bit error detected"
rbitfld.long 0x00 19. "OEDPSFP,One bit Error Detect of PSFP gate RAM" "0: Not one bit error detected,1: One bit error detected"
newline
rbitfld.long 0x00 18. "OEDATS,One bit Error Detect of ATS RAM" "0: Not one bit error detected,1: One bit error detected"
rbitfld.long 0x00 17. "OEDMAC,One bit Error Detect of MAC table RAM" "0: Not one bit error detected,1: One bit error detected"
rbitfld.long 0x00 16. "OEDVLAN,One bit Error Detect of VLAN table RAM" "0: Not one bit error detected,1: One bit error detected"
newline
rbitfld.long 0x00 15. "OEDL3IP,One bit Error Detect of L3 IP address table RAM" "0: Not one bit error detected,1: One bit error detected"
rbitfld.long 0x00 14. "OEDL23U,One bit Error Detect of L2 L3 Update RAM" "0: Not one bit error detected,1: One bit error detected"
rbitfld.long 0x00 13. "OEDEADS0,One bit Error Detect of Ethernet agent descriptor RAM 0" "0: Not one bit error detected,1: One bit error detected"
newline
rbitfld.long 0x00 12. "OEDEATCL0,One bit Error Detect of Ethernet agent TAS control list RAM 0" "0: Not one bit error detected,1: One bit error detected"
rbitfld.long 0x00 11. "OEDEADS1,One bit Error Detect of Ethernet agent descriptor RAM 1" "0: Not one bit error detected,1: One bit error detected"
rbitfld.long 0x00 10. "OEDEATCL1,One bit Error Detect of Ethernet agent TAS control list RAM 1" "0: Not one bit error detected,1: One bit error detected"
newline
rbitfld.long 0x00 9. "OEDEADS2,One bit Error Detect of Ethernet agent descriptor RAM 2" "0: Not one bit error detected,1: One bit error detected"
rbitfld.long 0x00 8. "OEDEATCL2,One bit Error Detect of Ethernet agent TAS control list RAM 2" "0: Not one bit error detected,1: One bit error detected"
rbitfld.long 0x00 7. "OEDGAAD0,One bit Error Detect of GWCA AXI address RAM 0" "0: Not one bit error detected,1: One bit error detected"
newline
rbitfld.long 0x00 6. "OEDGADS0,One bit Error Detect of GWCA descriptor RAM 0" "0: Not one bit error detected,1: One bit error detected"
rbitfld.long 0x00 5. "OEDGARM0,One bit Error Detect of GWCA RX multicast RAM 0" "0: Not one bit error detected,1: One bit error detected"
rbitfld.long 0x00 4. "OEDGATS0,One bit Error Detect of GWCA Timestamp RAM 0" "0: Not one bit error detected,1: One bit error detected"
newline
rbitfld.long 0x00 3. "OEDGAAD1,One bit Error Detect of GWCA AXI address RAM 1" "0: Not one bit error detected,1: One bit error detected"
rbitfld.long 0x00 2. "OEDGADS1,One bit Error Detect of GWCA descriptor RAM 1" "0: Not one bit error detected,1: One bit error detected"
rbitfld.long 0x00 1. "OEDGARM1,One bit Error Detect of GWCA RX multicast RAM 1" "0: Not one bit error detected,1: One bit error detected"
newline
rbitfld.long 0x00 0. "OEDGATS1,One bit Error Detect of GWCA Timestamp RAM 1" "0: Not one bit error detected,1: One bit error detected"
group.long 0x168++0x03
line.long 0x00 "RSW_n_EMED0,This register is accessible in both of User Mode and Error Injection Mode"
rbitfld.long 0x00 27.--31. "Reserved_27,Reserved (R.F.U)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rbitfld.long 0x00 26. "MEDACE,Multiple bit Error Detect of R-ACE Data RAM" "0: Not multiple bit error detected,1: Multiple bit error detected"
rbitfld.long 0x00 25. "MEDTAG,Multiple bit Error Detect of TAG RAM" "0: Not multiple bit error detected,1: Multiple bit error detected"
newline
rbitfld.long 0x00 24. "MEDPTR,Multiple bit Error Detect of Pointer RAM" "0: Not multiple bit error detected,1: Multiple bit error detected"
rbitfld.long 0x00 23. "MEDRJT,Multiple bit Error Detect of Descriptor reject RAM" "0: Not multiple bit error detected,1: Multiple bit error detected"
rbitfld.long 0x00 22. "MEDBPR,Multiple bit Error Detect of Buffer pointer RAM" "0: Not multiple bit error detected,1: Multiple bit error detected"
newline
rbitfld.long 0x00 21. "MEDL3F,Multiple bit Error Detect of L3 Filter table RAM" "0: Not multiple bit error detected,1: Multiple bit error detected"
rbitfld.long 0x00 20. "MEDFRER,Multiple bit Error Detect of FRER RAM" "0: Not multiple bit error detected,1: Multiple bit error detected"
rbitfld.long 0x00 19. "MEDPSFP,Multiple bit Error Detect of PSFP gate RAM" "0: Not multiple bit error detected,1: Multiple bit error detected"
newline
rbitfld.long 0x00 18. "MEDATS,Multiple bit Error Detect of ATS RAM" "0: Not multiple bit error detected,1: Multiple bit error detected"
rbitfld.long 0x00 17. "MEDMAC,Multiple bit Error Detect of MAC table RAM" "0: Not multiple bit error detected,1: Multiple bit error detected"
rbitfld.long 0x00 16. "MEDVLAN,Multiple bit Error Detect of VLAN table RAM" "0: Not multiple bit error detected,1: Multiple bit error detected"
newline
rbitfld.long 0x00 15. "MEDL3IP,Multiple bit Error Detect of L3 IP address table RAM" "0: Not multiple bit error detected,1: Multiple bit error detected"
rbitfld.long 0x00 14. "MEDL23U,Multiple bit Error Detect of L2 L3 Update RAM" "0: Not multiple bit error detected,1: Multiple bit error detected"
rbitfld.long 0x00 13. "MEDEADS0,Multiple bit Error Detect of Ethernet agent descriptor RAM 0" "0: Not multiple bit error detected,1: Multiple bit error detected"
newline
rbitfld.long 0x00 12. "MEDEATCL0,Multiple bit Error Detect of Ethernet agent TAS control list RAM 0" "0: Not multiple bit error detected,1: Multiple bit error detected"
rbitfld.long 0x00 11. "MEDEADS1,Multiple bit Error Detect of Ethernet agent descriptor RAM 1" "0: Not multiple bit error detected,1: Multiple bit error detected"
rbitfld.long 0x00 10. "MEDEATCL1,Multiple bit Error Detect of Ethernet agent TAS control list RAM 1" "0: Not multiple bit error detected,1: Multiple bit error detected"
newline
rbitfld.long 0x00 9. "MEDEADS2,Multiple bit Error Detect of Ethernet agent descriptor RAM 2" "0: Not multiple bit error detected,1: Multiple bit error detected"
rbitfld.long 0x00 8. "MEDEATCL2,Multiple bit Error Detect of Ethernet agent TAS control list RAM 2" "0: Not multiple bit error detected,1: Multiple bit error detected"
rbitfld.long 0x00 7. "MEDGAAD0,Multiple bit Error Detect of GWCA AXI address RAM 0" "0: Not multiple bit error detected,1: Multiple bit error detected"
newline
rbitfld.long 0x00 6. "MEDGADS0,Multiple bit Error Detect of GWCA descriptor RAM 0" "0: Not multiple bit error detected,1: Multiple bit error detected"
rbitfld.long 0x00 5. "MEDGARM0,Multiple bit Error Detect of GWCA RX multicast RAM 0" "0: Not multiple bit error detected,1: Multiple bit error detected"
rbitfld.long 0x00 4. "MEDGATS0,Multiple bit Error Detect of GWCA Timestamp RAM 0" "0: Not multiple bit error detected,1: Multiple bit error detected"
newline
rbitfld.long 0x00 3. "MEDGAAD1,Multiple bit Error Detect of GWCA AXI address RAM 1" "0: Not multiple bit error detected,1: Multiple bit error detected"
rbitfld.long 0x00 2. "MEDGADS1,Multiple bit Error Detect of GWCA descriptor RAM 1" "0: Not multiple bit error detected,1: Multiple bit error detected"
rbitfld.long 0x00 1. "MEDGARM1,Multiple bit Error Detect of GWCA RX multicast RAM 1" "0: Not multiple bit error detected,1: Multiple bit error detected"
newline
rbitfld.long 0x00 0. "MEDGATS1,Multiple bit Error Detect of GWCA Timestamp RAM 1" "0: Not multiple bit error detected,1: Multiple bit error detected"
group.long 0x178++0x03
line.long 0x00 "RSW_n_EOEDC0,This register is accessible in both of User Mode and Error Injection Mode"
bitfld.long 0x00 27.--31. "Reserved_27,Reserved (R.F.U)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 26. "OECACE,One bit Error Clear of R-ACE Data RAM" "0: Not clear,1: clear"
bitfld.long 0x00 25. "OECTAG,One bit Error Clear of TAG RAM" "0: Not clear,1: clear"
newline
bitfld.long 0x00 24. "OECPTR,One bit Error Clear of Pointer RAM" "0: Not clear,1: clear"
bitfld.long 0x00 23. "OECRJT,One bit Error Clear of Descriptor reject RAM" "0: Not clear,1: clear"
bitfld.long 0x00 22. "OECBPR,One bit Error Clear of Buffer pointer RAM" "0: Not clear,1: clear"
newline
bitfld.long 0x00 21. "OECL3F,One bit Error Clear of L3 Filter table RAM" "0: Not clear,1: clear"
bitfld.long 0x00 20. "OECFRER,One bit Error Clear of FRER RAM" "0: Not clear,1: clear"
bitfld.long 0x00 19. "OECPSFP,One bit Error Clear of PSFP gate RAM" "0: Not clear,1: clear"
newline
bitfld.long 0x00 18. "OECATS,One bit Error Clear of ATS RAM" "0: Not clear,1: clear"
bitfld.long 0x00 17. "OECMAC,One bit Error Clear of MAC table RAM" "0: Not clear,1: clear"
bitfld.long 0x00 16. "OECVLAN,One bit Error Clear of VLAN table RAM" "0: Not clear,1: clear"
newline
bitfld.long 0x00 15. "OECL3IP,One bit Error Clear of L3 IP address table RAM" "0: Not clear,1: clear"
bitfld.long 0x00 14. "OECL23U,One bit Error Clear of L2 L3 Update RAM" "0: Not clear,1: clear"
bitfld.long 0x00 13. "OECEADS0,One bit Error Clear of Ethernet agent descriptor RAM 0" "0: Not clear,1: clear"
newline
bitfld.long 0x00 12. "OECEATCL0,One bit Error Clear of Ethernet agent TAS control list RAM 0" "0: Not clear,1: clear"
bitfld.long 0x00 11. "OECEADS1,One bit Error Clear of Ethernet agent descriptor RAM 1" "0: Not clear,1: clear"
bitfld.long 0x00 10. "OECEATCL1,One bit Error Clear of Ethernet agent TAS control list RAM 1" "0: Not clear,1: clear"
newline
bitfld.long 0x00 9. "OECEADS2,One bit Error Clear of Ethernet agent descriptor RAM 2" "0: Not clear,1: clear"
bitfld.long 0x00 8. "OECEATCL2,One bit Error Clear of Ethernet agent TAS control list RAM 2" "0: Not clear,1: clear"
bitfld.long 0x00 7. "OECGAAD0,One bit Error Clear of GWCA AXI address RAM 0" "0: Not clear,1: clear"
newline
bitfld.long 0x00 6. "OECGADS0,One bit Error Clear of GWCA descriptor RAM 0" "0: Not clear,1: clear"
bitfld.long 0x00 5. "OECGARM0,One bit Error Clear of GWCA RX multicast RAM 0" "0: Not clear,1: clear"
bitfld.long 0x00 4. "OECGATS0,One bit Error Clear of GWCA Timestamp RAM 0" "0: Not clear,1: clear"
newline
bitfld.long 0x00 3. "OECGAAD1,One bit Error Clear of GWCA AXI address RAM 1" "0: Not clear,1: clear"
bitfld.long 0x00 2. "OECGADS1,One bit Error Clear of GWCA descriptor RAM 1" "0: Not clear,1: clear"
bitfld.long 0x00 1. "OECGARM1,One bit Error Clear of GWCA RX multicast RAM 1" "0: Not clear,1: clear"
newline
bitfld.long 0x00 0. "OECGATS1,One bit Error Clear of GWCA Timestamp RAM 1" "0: Not clear,1: clear"
group.long 0x188++0x03
line.long 0x00 "RSW_n_EMEDC0,This register is accessible in both of User Mode and Error Injection Mode"
bitfld.long 0x00 27.--31. "Reserved_27,Reserved (R.F.U)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 26. "MECACE,Multiple bit Error Clear of R-ACE Data RAM" "0: Not clear,1: clear"
bitfld.long 0x00 25. "MECTAG,Multiple bit Error Clear of TAG RAM" "0: Not clear,1: clear"
newline
bitfld.long 0x00 24. "MECPTR,Multiple bit Error Clear of Pointer RAM" "0: Not clear,1: clear"
bitfld.long 0x00 23. "MECRJT,Multiple bit Error Clear of Descriptor reject RAM" "0: Not clear,1: clear"
bitfld.long 0x00 22. "MECBPR,Multiple bit Error Clear of Buffer pointer RAM" "0: Not clear,1: clear"
newline
bitfld.long 0x00 21. "MECL3F,Multiple bit Error Clear of L3 Filter table RAM" "0: Not clear,1: clear"
bitfld.long 0x00 20. "MECFRER,Multiple bit Error Clear of FRER RAM" "0: Not clear,1: clear"
bitfld.long 0x00 19. "MECPSFP,Multiple bit Error Clear of PSFP gate RAM" "0: Not clear,1: clear"
newline
bitfld.long 0x00 18. "MECATS,Multiple bit Error Clear of ATS RAM" "0: Not clear,1: clear"
bitfld.long 0x00 17. "MECMAC,Multiple bit Error Clear of MAC table RAM" "0: Not clear,1: clear"
bitfld.long 0x00 16. "MECVLAN,Multiple bit Error Clear of VLAN table RAM" "0: Not clear,1: clear"
newline
bitfld.long 0x00 15. "MECL3IP,Multiple bit Error Clear of L3 IP address table RAM" "0: Not clear,1: clear"
bitfld.long 0x00 14. "MECL23U,Multiple bit Error Clear of L2 L3 Update RAM" "0: Not clear,1: clear"
bitfld.long 0x00 13. "MECEADS0,Multiple bit Error Clear of Ethernet agent descriptor RAM 0" "0: Not clear,1: clear"
newline
bitfld.long 0x00 12. "MECEATCL0,Multiple bit Error Clear of Ethernet agent TAS control list RAM 0" "0: Not clear,1: clear"
bitfld.long 0x00 11. "MECEADS1,Multiple bit Error Clear of Ethernet agent descriptor RAM 1" "0: Not clear,1: clear"
bitfld.long 0x00 10. "MECEATCL1,Multiple bit Error Clear of Ethernet agent TAS control list RAM 1" "0: Not clear,1: clear"
newline
bitfld.long 0x00 9. "MECEADS2,Multiple bit Error Clear of Ethernet agent descriptor RAM 2" "0: Not clear,1: clear"
bitfld.long 0x00 8. "MECEATCL2,Multiple bit Error Clear of Ethernet agent TAS control list RAM 2" "0: Not clear,1: clear"
bitfld.long 0x00 7. "MECGAAD0,Multiple bit Error Clear of GWCA AXI address RAM 0" "0: Not clear,1: clear"
newline
bitfld.long 0x00 6. "MECGADS0,Multiple bit Error Clear of GWCA descriptor RAM 0" "0: Not clear,1: clear"
bitfld.long 0x00 5. "MECGARM0,Multiple bit Error Clear of GWCA RX multicast RAM 0" "0: Not clear,1: clear"
bitfld.long 0x00 4. "MECGATS0,Multiple bit Error Clear of GWCA Timestamp RAM 0" "0: Not clear,1: clear"
newline
bitfld.long 0x00 3. "MECGAAD1,Multiple bit Error Clear of GWCA AXI address RAM 1" "0: Not clear,1: clear"
bitfld.long 0x00 2. "MECGADS1,Multiple bit Error Clear of GWCA descriptor RAM 1" "0: Not clear,1: clear"
bitfld.long 0x00 1. "MECGARM1,Multiple bit Error Clear of GWCA RX multicast RAM 1" "0: Not clear,1: clear"
newline
bitfld.long 0x00 0. "MECGATS1,Multiple bit Error Clear of GWCA Timestamp RAM 1" "0: Not clear,1: clear"
group.long 0x604++0x03
line.long 0x00 "RSW_n_PPS0R0,This register is to select gate or pps pins for debug"
bitfld.long 0x00 31. "PSFPGATE2,select mfw_race_psfp_gate_state_2_" "0,1"
bitfld.long 0x00 30. "PSFPGATE1,select mfw_race_psfp_gate_state_1_" "0,1"
bitfld.long 0x00 29. "PSFPGATE0,select mfw_race_psfp_gate_state_0_" "0,1"
newline
bitfld.long 0x00 28. "Reserved_28,Reserved (R.F.U)" "0,1"
bitfld.long 0x00 27. "ETH2GATE7,select eha_race_tas_gate_state_7_ for channel 2" "0,1"
bitfld.long 0x00 26. "ETH2GATE6,select eha_race_tas_gate_state_6_ for channel 2" "0,1"
newline
bitfld.long 0x00 25. "ETH2GATE5,select eha_race_tas_gate_state_5_ for channel 2" "0,1"
bitfld.long 0x00 24. "ETH2GATE4,select eha_race_tas_gate_state_4_ for channel 2" "0,1"
bitfld.long 0x00 23. "ETH2GATE3,select eha_race_tas_gate_state_3_ for channel 2" "0,1"
newline
bitfld.long 0x00 22. "ETH2GATE2,select eha_race_tas_gate_state_2_ for channel 2" "0,1"
bitfld.long 0x00 21. "ETH2GATE1,select eha_race_tas_gate_state_1_ for channel 2" "0,1"
bitfld.long 0x00 20. "ETH2GATE0,select eha_race_tas_gate_state_0_ for channel 2" "0,1"
newline
bitfld.long 0x00 19. "Reserved_19,Reserved (R.F.U)" "0,1"
bitfld.long 0x00 18. "ETH1GATE7,select eha_race_tas_gate_state_7_ for channel 1" "0,1"
bitfld.long 0x00 17. "ETH1GATE6,select eha_race_tas_gate_state_6_ for channel 1" "0,1"
newline
bitfld.long 0x00 16. "ETH1GATE5,select eha_race_tas_gate_state_5_ for channel 1" "0,1"
bitfld.long 0x00 15. "ETH1GATE4,select eha_race_tas_gate_state_4_ for channel 1" "0,1"
bitfld.long 0x00 14. "ETH1GATE3,select eha_race_tas_gate_state_3_ for channel 1" "0,1"
newline
bitfld.long 0x00 13. "ETH1GATE2,select eha_race_tas_gate_state_2_ for channel 1" "0,1"
bitfld.long 0x00 12. "ETH1GATE1,select eha_race_tas_gate_state_1_ for channel 1" "0,1"
bitfld.long 0x00 11. "ETH1GATE0,select eha_race_tas_gate_state_0_ for channel 1" "0,1"
newline
bitfld.long 0x00 10. "Reserved_10,Reserved (R.F.U)" "0,1"
bitfld.long 0x00 9. "ETH0GATE7,select eha_race_tas_gate_state_7_ for channel 0" "0,1"
bitfld.long 0x00 8. "ETH0GATE6,select eha_race_tas_gate_state_6_ for channel 0" "0,1"
newline
bitfld.long 0x00 7. "ETH0GATE5,select eha_race_tas_gate_state_5_ for channel 0" "0,1"
bitfld.long 0x00 6. "ETH0GATE4,select eha_race_tas_gate_state_4_ for channel 0" "0,1"
bitfld.long 0x00 5. "ETH0GATE3,select eha_race_tas_gate_state_3_ for channel 0" "0,1"
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bitfld.long 0x00 4. "ETH0GATE2,select eha_race_tas_gate_state_2_ for channel 0" "0,1"
bitfld.long 0x00 3. "ETH0GATE1,select eha_race_tas_gate_state_1_ for channel 0" "0,1"
bitfld.long 0x00 2. "ETH0GATE0,select eha_race_tas_gate_state_0_ for channel 0" "0,1"
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bitfld.long 0x00 1. "GPTPPPS1,select gptp_pps_1_" "0,1"
bitfld.long 0x00 0. "GPTPPPS0,select gptp_pps_0_" "0,1"
group.long 0x608++0x03
line.long 0x00 "RSW_n_PPS0R1,This register is to select gate or pps pins for debug"
hexmask.long 0x00 5.--31. 1. "Reserved_5,Reserved (R.F.U)"
bitfld.long 0x00 4. "PSFPGATE7,select mfw_race_psfp_gate_state_7_" "0,1"
bitfld.long 0x00 3. "PSFPGATE6,select mfw_race_psfp_gate_state_6_" "0,1"
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bitfld.long 0x00 2. "PSFPGATE5,select mfw_race_psfp_gate_state_5_" "0,1"
bitfld.long 0x00 1. "PSFPGATE4,select mfw_race_psfp_gate_state_4_" "0,1"
bitfld.long 0x00 0. "PSFPGATE3,select mfw_race_psfp_gate_state_3_" "0,1"
group.long 0x60C++0x03
line.long 0x00 "RSW_n_PPS1R0,This register is to select gate or pps pins for debug"
bitfld.long 0x00 31. "PSFPGATE2,select mfw_race_psfp_gate_state_2_" "0,1"
bitfld.long 0x00 30. "PSFPGATE1,select mfw_race_psfp_gate_state_1_" "0,1"
bitfld.long 0x00 29. "PSFPGATE0,select mfw_race_psfp_gate_state_0_" "0,1"
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bitfld.long 0x00 28. "Reserved_28,Reserved (R.F.U)" "0,1"
bitfld.long 0x00 27. "ETH2GATE7,select eha_race_tas_gate_state_7_ for channel 2" "0,1"
bitfld.long 0x00 26. "ETH2GATE6,select eha_race_tas_gate_state_6_ for channel 2" "0,1"
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bitfld.long 0x00 25. "ETH2GATE5,select eha_race_tas_gate_state_5_ for channel 2" "0,1"
bitfld.long 0x00 24. "ETH2GATE4,select eha_race_tas_gate_state_4_ for channel 2" "0,1"
bitfld.long 0x00 23. "ETH2GATE3,select eha_race_tas_gate_state_3_ for channel 2" "0,1"
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bitfld.long 0x00 22. "ETH2GATE2,select eha_race_tas_gate_state_2_ for channel 2" "0,1"
bitfld.long 0x00 21. "ETH2GATE1,select eha_race_tas_gate_state_1_ for channel 2" "0,1"
bitfld.long 0x00 20. "ETH2GATE0,select eha_race_tas_gate_state_0_ for channel 2" "0,1"
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bitfld.long 0x00 19. "Reserved_19,Reserved (R.F.U)" "0,1"
bitfld.long 0x00 18. "ETH1GATE7,select eha_race_tas_gate_state_7_ for channel 1" "0,1"
bitfld.long 0x00 17. "ETH1GATE6,select eha_race_tas_gate_state_6_ for channel 1" "0,1"
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bitfld.long 0x00 16. "ETH1GATE5,select eha_race_tas_gate_state_5_ for channel 1" "0,1"
bitfld.long 0x00 15. "ETH1GATE4,select eha_race_tas_gate_state_4_ for channel 1" "0,1"
bitfld.long 0x00 14. "ETH1GATE3,select eha_race_tas_gate_state_3_ for channel 1" "0,1"
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bitfld.long 0x00 13. "ETH1GATE2,select eha_race_tas_gate_state_2_ for channel 1" "0,1"
bitfld.long 0x00 12. "ETH1GATE1,select eha_race_tas_gate_state_1_ for channel 1" "0,1"
bitfld.long 0x00 11. "ETH1GATE0,select eha_race_tas_gate_state_0_ for channel 1" "0,1"
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bitfld.long 0x00 10. "Reserved_10,Reserved (R.F.U)" "0,1"
bitfld.long 0x00 9. "ETH0GATE7,select eha_race_tas_gate_state_7_ for channel 0" "0,1"
bitfld.long 0x00 8. "ETH0GATE6,select eha_race_tas_gate_state_6_ for channel 0" "0,1"
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bitfld.long 0x00 7. "ETH0GATE5,select eha_race_tas_gate_state_5_ for channel 0" "0,1"
bitfld.long 0x00 6. "ETH0GATE4,select eha_race_tas_gate_state_4_ for channel 0" "0,1"
bitfld.long 0x00 5. "ETH0GATE3,select eha_race_tas_gate_state_3_ for channel 0" "0,1"
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bitfld.long 0x00 4. "ETH0GATE2,select eha_race_tas_gate_state_2_ for channel 0" "0,1"
bitfld.long 0x00 3. "ETH0GATE1,select eha_race_tas_gate_state_1_ for channel 0" "0,1"
bitfld.long 0x00 2. "ETH0GATE0,select eha_race_tas_gate_state_0_ for channel 0" "0,1"
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bitfld.long 0x00 1. "GPTPPPS1,select gptp_pps_1_" "0,1"
bitfld.long 0x00 0. "GPTPPPS0,select gptp_pps_0_" "0,1"
group.long 0x610++0x03
line.long 0x00 "RSW_n_PPS1R1,This register is to select gate or pps pins for debug"
hexmask.long 0x00 5.--31. 1. "Reserved_5,Reserved (R.F.U)"
bitfld.long 0x00 4. "PSFPGATE7,select mfw_race_psfp_gate_state_7_" "0,1"
bitfld.long 0x00 3. "PSFPGATE6,select mfw_race_psfp_gate_state_6_" "0,1"
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bitfld.long 0x00 2. "PSFPGATE5,select mfw_race_psfp_gate_state_5_" "0,1"
bitfld.long 0x00 1. "PSFPGATE4,select mfw_race_psfp_gate_state_4_" "0,1"
bitfld.long 0x00 0. "PSFPGATE3,select mfw_race_psfp_gate_state_3_" "0,1"
tree.end
tree "ETHERNET_SERDES_SRAM"
base ad:0xE643E000
group.long 0x00++0x03
line.long 0x00 "RSWSD0MS,This register is accessible in both of User Mode and Error Injection Mode"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved (R.F.U)"
bitfld.long 0x00 0. "MS,Mode Select" "0: User Mode,1: Error Injection Mode"
group.long 0x04++0x03
line.long 0x00 "RSWSD0RS0,"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved (R.F.U)"
bitfld.long 0x00 0. "RETHSD,Select EtherSerDes RAM" "0: not selected,1: selected"
group.long 0x14++0x03
line.long 0x00 "RSWSD0SDAE,"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved (R.F.U)"
bitfld.long 0x00 0. "DAEN,Direct Access Enable Enable to directly access the SRAM which is selected by RSWSDnRS" "0: Not enable is issued,1: 1 pulse enable is issued"
group.long 0x18++0x03
line.long 0x00 "RSWSD0SDARWS,"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved (R.F.U)"
bitfld.long 0x00 0. "DARWS,Direct Access Read Write Switch The SRAM selected by RSWSDnRS is avilable" "0: read,1: write"
group.long 0x1C++0x03
line.long 0x00 "RSWSD0SDAA,"
hexmask.long 0x00 0.--31. 1. "DAA,Direct Access Address Write address to access the SRAM which is selected by RSWSDnRS"
group.long 0x20++0x03
line.long 0x00 "RSWSD0SDWD0,SRAM Direct Write Data 0 corresponds to write data size [31:0]"
hexmask.long 0x00 0.--31. 1. "SDWD0,SRAM Direct Write Data 0 The SRAM selected by RSWSDnRS is avilable"
group.long 0x64++0x03
line.long 0x00 "RSWSD0SDRD0,SRAM Direct Read Data 0 corresponds to read data size [31:0]"
hexmask.long 0x00 0.--31. 1. "SDRD0,SRAM Direct Read Data 0 The SRAM selected by RSWSDnRS is avilable"
group.long 0xA8++0x03
line.long 0x00 "RSWSD0WDEIE0,"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved (R.F.U)"
bitfld.long 0x00 0. "WDEIEN,Write Data Error Injection Enable Enable to convert value of RSWSDnSDWDi which correspond to RSWSDnWDEIBSi written as 1" "0: Not enable is issued,1: 1 pulse enable is issued"
group.long 0xAC++0x03
line.long 0x00 "RSWSD0RDEIE0,"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved (R.F.U)"
bitfld.long 0x00 0. "RDEIEN,Read Data Error Injection Enable Enable to convert value of RSWSDnSDRDi which correspond to RSWSDnRDEIBSi written as 1" "0: Not enable is issued,1: 1 pulse enable is issued"
group.long 0xB0++0x03
line.long 0x00 "RSWSD0WDEIBS0,Write Data Error Injection Bit Select 0 corresponds to write data size [31:0]"
hexmask.long 0x00 0.--31. 1. "WDEIBS0,Write Data Error Injection Bit Select 0 The SRAM selected by RSWSDnRS is avilable"
group.long 0xF4++0x03
line.long 0x00 "RSWSD0RDEIBS0,Read Data Error Injection Bit Select 0 corresponds to read data size [31:0]"
hexmask.long 0x00 0.--31. 1. "RDEIBS0,Read Data Error Injection Bit Select 0 The SRAM selected by RSWSDnRS is avilable"
group.long 0x138++0x03
line.long 0x00 "RSWSD0EECE0,This register is accessible in both of User Mode and Error Injection Mode"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved (R.F.U)"
bitfld.long 0x00 0. "ECETHSD,ECC Error Correct of EtherSerDes RAM" "0: not correct,1: correct"
group.long 0x148++0x03
line.long 0x00 "RSWSD0EPS0,This register is accessible in Error Injection Mode"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved (R.F.U)"
bitfld.long 0x00 0. "EPETHSD,ECC Path Select of EtherSerDes RAM" "0: bypass ECC,1: through ECC"
group.long 0x158++0x03
line.long 0x00 "RSWSD0EOED0,This register is accessible in both of User Mode and Error Injection Mode"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved (R.F.U)"
rbitfld.long 0x00 0. "OEDETHSD,One bit Error Detect of EtherSerDes RAM" "0: Not one bit error detected,1: One bit error detected"
group.long 0x168++0x03
line.long 0x00 "RSWSD0EMED0,This register is accessible in both of User Mode and Error Injection Mode"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved (R.F.U)"
rbitfld.long 0x00 0. "MEDETHSD,Multiple bit Error Detect of EtherSerDes RAM" "0: Not multiple bit error detected,1: Multiple bit error detected"
group.long 0x178++0x03
line.long 0x00 "RSWSD0EOEDC0,This register is accessible in both of User Mode and Error Injection Mode"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved (R.F.U)"
bitfld.long 0x00 0. "OECETHSD,One bit Error Clear of EtherSerDes RAM This bit clear OEDACE" "0: Not clear,1: clear"
group.long 0x188++0x03
line.long 0x00 "RSWSD0EMEDC0,This register is accessible in both of User Mode and Error Injection Mode"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved (R.F.U)"
bitfld.long 0x00 0. "MECETHSD,Multiple bit Error Clear of EtherSerDes RAM" "0: Not clear,1: clear"
tree.end
tree "SCIF"
tree "SCIF_INST_0"
base ad:0xE6E60000
group.word 0x00++0x01
line.word 0x00 "SCSMR0,SCSMR is a 16-bit register that sets the SCIF's serial transfer format and selects the baud rate generator clock source"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 7. "C_A_SHARP,Communication Mode Selects asynchronous mode or clock synchronous mode for the SCIF operation" "0: Asynchronous mode,1: Clock synchronous mode"
newline
bitfld.word 0x00 6. "CHR,Character Length Selects 7 or 8 bits for asynchronous mode data length" "0: 8 bits,1: 7 bits*"
bitfld.word 0x00 5. "PE,Parity Enable Determines whether parity bit is added in transmission or not and parity bit is checked in reception in asynchronous mode or not" "0: Disables parity bit addition and check,1: Enables parity bit addition and check"
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bitfld.word 0x00 4. "O_E_SHARP,Parity Mode Selects either even or odd parity to use in parity addition and check" "0: Even parity*1,1: Odd parity*2 Notes"
bitfld.word 0x00 3. "STOP,Stop Bit Length Selects 1 bit or 2 bits as the stop bit length in asynchronous mode" "0: 1 stop bit*1,1: 2 stop bits*2 Notes"
newline
rbitfld.word 0x00 2. "Reserved_2,Reserved This bit is always read as 0" "0,1"
bitfld.word 0x00 0.--1. "CKS_1_0,Clock Select 1 and 0 These bits select the clock source for the on-chip baud rate generator" "0: PCK,1: PCK /4,2: PCK /16,3: PCK /64"
group.byte 0x04++0x00
line.byte 0x00 "SCBRR0,SCBRR is an 8-bit register that sets the serial transmission/reception bit rate in accordance with the baud rate generator operating clock selected by the CKS1 and CKS0 bits in SCSMR"
hexmask.byte 0x00 0.--7. 1. "Reserved_0,The SCBRR setting is determined by the following equation: [Asynchronous mode] N = ( PCK / 64 x 22n-1 x B ) x"
group.word 0x08++0x01
line.word 0x00 "SCSCR0,SCSCR is a register that enables or disables transmission/reception by the SCIF enables or disables interrupt requests and selects transmission/reception clock source for the SCIF"
rbitfld.word 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 11. "TEIE,Transmit End Interrupt Enable When a transmit-end request is enabled by the TIE bit the TEIE bit selects the source of the transmit end interrupt request from the following: Setting the TDFE flag in SCFSR Setting the TEND flag in SCFSR.." "0: The transmit FIFO data empty (TDFE) interrupt,1: The transmit end (TEND) interrupt request is.."
newline
rbitfld.word 0x00 8.--10. "Reserved_8,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.word 0x00 7. "TIE,Transmit Interrupt Enable Enables or disables a transmit-FIFO-data-empty interrupt (TDFE) request when the TEIE bit in SCSCR is pulled 0 if all of the following conditions are satisfied: Serial transmit data has been transferred from SCFTDR to .." "0: When the TEIE bit is 0 disables,1: When the TEIE bit is 0 enables"
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bitfld.word 0x00 6. "RIE,Receive Interrupt Enable Enables or disables a receive-FIFO-data-full interrupt request when the RDF flag in SCFSR is set to 1 a receive-data-ready interrupt request when the DR flag in SCFSR is set to 1 a receive-error interrupt request.." "0: Disables receive-FIFO-data-full interrupt (RDF),1: Enables receive-FIFO-data-full interrupt (RDF)"
bitfld.word 0x00 5. "TE,Transmit Enable Enables or disables the start of SCIF serial transmission" "0: Disables transmission,1: Enables transmission"
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bitfld.word 0x00 4. "RE,Receive Enable Enables or disables the start of SCIF serial reception" "0: Disables reception.*,1: Enables reception"
bitfld.word 0x00 3. "REIE,Receive Error Interrupt Enable Enables or Disables generation of receive-error interrupt (ER) requests break interrupt (BRK) requests and overrun-error interrupt (ORER) requests" "0: Disables receive-error interrupt (ER) requests,1: Enables receive-error interrupt (ER) requests"
newline
bitfld.word 0x00 2. "TOIE,Timeout Interrupt Enable Enables or disables generation of timeout interrupt (TO) requests when the TO flag in SCLSR is set to 1" "0: Disables timeout interrupts (TO),1: Enables timeout interrupts (TO)"
bitfld.word 0x00 0.--1. "CKE_1_0,Clock Enable 1 and 0 These bits select the SCIF clock source and enables or disables the clock output from the SCK pin" "0,1,2,3"
group.byte 0x0C++0x00
line.byte 0x00 "SCFTDR0,SCFTDR is an 8-bit FIFO register of 16 stages that stores data for serial transmission"
hexmask.byte 0x00 0.--7. 1. "Reserved_0,"
group.word 0x10++0x01
line.word 0x00 "SCFSR0,SCFSR is a 16-bit register"
rbitfld.word 0x00 12.--15. "PER_3_0,Parity Error Count These bits indicate the number of parity errors of receive data stored in the receive FIFO data register (SCFRDR)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.word 0x00 8.--11. "FER_3_0,Framing Error Count These bits indicate the number of framing errors of receive data stored in the receive FIFO data register (SCFRDR)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 7. "ER,Receive Error Indicates that a framing error or a parity error has occurred in reception.*1 The ER flag is not affected by an error and retains its previous state when the RE bit is 0 in SCSCR" "0: Indicates that no framing or parity error has,1: Indicates that a framing error or a parity.."
bitfld.word 0x00 6. "TEND,Indicates that transmission has been ended * because there was no valid data in SCFTDR when the last bit of the transmit character was transmitted" "0: Indicates that transmission is in progress,1: Indicates that transmission has been ended"
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bitfld.word 0x00 5. "TDFE,Transmit FIFO Data Empty Indicates that the SCIF has transferred data from SCFTDR to SCTSR the number of data bytes in SCFTDR becomes equal to or less than the transmit trigger count specified by the TTRG1 and TTRG0 bits in SCFCR and SCFTDR is.." "0: Indicates that the number of transmit data,1: Indicates that the number of transmit data in"
bitfld.word 0x00 4. "BRK,Break Detect Indicates that a receive data break signal has been detected" "0: Indicates that no break signal has been..,1: Indicates that a break signal has been received"
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rbitfld.word 0x00 3. "FER,Framing Error Indicates that a framing error has been found in the data that is to be read next from SCFRDR in asynchronous mode" "0: Indicates that there is no framing error in the,1: Indicates that there is a framing error in the"
rbitfld.word 0x00 2. "PER,Parity Error This bit indicates that a parity error has been found in the data that is to be read next from SCFRDR in asynchronous mode" "0: Indicates that there is no parity error in the,1: Indicates that there is a parity error in the"
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bitfld.word 0x00 1. "RDF,Receive FIFO Data Full Indicates that the received data has been transferred from SCRSR to SCFRDR and the number of receive data bytes in SCFRDR becomes equal to or more than the receive trigger count specified by the RTRG1 and RTRG0 bits in SCFCR.." "0: Indicates that the number of receive data bytes,1: Indicates that the number of receive data bytes"
bitfld.word 0x00 0. "DR,Receive Data Ready Indicates that the number of data bytes in SCFRDR is less than the receive trigger count and that no further data has been received for at least 15 etu after the stop bit of the data received last in asynchronous mode.." "0: Indicates that data is being received or has,1: Indicates that no further receive data has been"
group.byte 0x14++0x00
line.byte 0x00 "SCFRDR0,SCFRDR is a 16-stage FIFO register that stores received serial data"
hexmask.byte 0x00 0.--7. 1. "Reserved_0,"
group.word 0x18++0x01
line.word 0x00 "SCFCR0,SCFCR is a register that resets data counts and sets the number of trigger data bytes for the transmit and receive FIFO registers"
rbitfld.word 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 8.--10. "RSTRG_2_0,RTS Output Active Trigger The RTS# signal is high when the number of receive data bytes stored in SCFRDR is equal to or more than the specified trigger number shown below" "0: 15,1: 1,2: 4,3: 6,4: 8,5: 10,6: 12,7: 14"
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bitfld.word 0x00 6.--7. "RTRG_1_0,Receive FIFO Data Count Trigger These bits specify the number of receive data bytes that makes the RDF (receive data full) flag to be set in SCFSR" "0: 1 (Asynchronous Mode and Clock Synchronous..,1: 4 (Asynchronous Mode) 2 (Clock Synchronous..,2: 8 (Asynchronous Mode and Clock Synchronous..,3: 14 (Asynchronous Mode and Clock Synchronous.."
bitfld.word 0x00 4.--5. "TTRG_1_0,Transmit FIFO Data Count Trigger These bits specify the number of remaining transmit data bytes that makes the transmit FIFO data register empty (TDFE) flag to be set in SCFSR" "0: 8 (8),1: 4 (12),2: 2 (14),3: 0 (16)"
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bitfld.word 0x00 3. "MCE,Modem Control Enable Enables or disables modem control signals CTS# and RTS#" "0: Disables modem signals.*,1: Enables modem signals"
bitfld.word 0x00 2. "TFRST,Transmit FIFO Data Register Reset Enables or disables a transmit FIFO data register reset that empties the register" "0: Disables the reset.*,1: Enables the reset"
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bitfld.word 0x00 1. "RFRST,Receive FIFO Data Register Reset Enables or disables a receive FIFO data register reset that empties the register" "0: Disables the reset.*,1: Enables the reset"
bitfld.word 0x00 0. "LOOP,Loopback Test Enables or disables the loopback test by internally connecting the transmit output pin (TX) and receive input pin (RX) and the RTS# pin and CTS# pin" "0: Disables the loopback test,1: Enables the loopback test"
group.word 0x1C++0x01
line.word 0x00 "SCFDR0,SCFDR is a 16-bit register that indicates the number of data bytes stored in SCFTDR and that in SCFRDR"
rbitfld.word 0x00 13.--15. "Reserved_13,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
rbitfld.word 0x00 8.--12. "T_4_0,These bits show the number of data bytes untransmitted and still stored in SCFTDR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.word 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
rbitfld.word 0x00 0.--4. "R_4_0,These bits show the number of receive data stored in SCFRDR in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x20++0x01
line.word 0x00 "SCSPTR0,SCSPTR controls multiplexed input/output and data on the serial communication interface (SCIF) ports"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 7. "RTSIO,Serial Port RTS# Pin Input/output Specifies input or output for the serial port RTS# pin" "0: Indicates that this bit does not output the,1: Indicates that this bit outputs the value of.."
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bitfld.word 0x00 6. "RTSDT,Serial Port RTS# Pin Data Specifies the input/output data level of the serial port RTS# pin" "0: Indicates that the input/output data is low..,1: Indicates that the input/output data is high.."
bitfld.word 0x00 5. "CTSIO,Serial Port CTS# Pin Input/output Specifies input or output for the serial port CTS# pin" "0: Indicates that the CTSDT bit value is not..,1: Indicates that the CTSDT bit value is output to"
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bitfld.word 0x00 4. "CTSDT,Serial Port CTS# Pin Data Specifies the input/output data level of the serial port CTS# pin" "0: Indicates that the input/output data is low..,1: Indicates that the input/output data is high.."
bitfld.word 0x00 3. "SCKIO,Serial Port Clock Pin Input/output Specifies input or output for the serial port SCK pin" "0: Indicates that the SCKDT bit value is not..,1: Indicates that the SCKDT bit value is output to"
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bitfld.word 0x00 2. "SCKDT,Serial Port Clock Pin Data Specifies the input/output data level of the serial port SCK pin" "0: Indicates that the input/output data is low..,1: Indicates that the input/output data is high.."
bitfld.word 0x00 1. "SPB2IO,Serial Port Break Input/Output Specifies the output condition of the serial port TX pin" "0: Indicates that the SPB2DT bit value is not,1: Indicates that the SPB2DT bit value is output.."
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bitfld.word 0x00 0. "SPB2DT,Serial Port Break Data Specifies the input level of the serial port RX pin and the output level of the TX pin" "0: Indicates that the input/output data is low..,1: Indicates that the input/output data is high.."
group.word 0x24++0x01
line.word 0x00 "SCLSR0,"
hexmask.word 0x00 3.--15. 1. "Reserved_3,Reserved These bits are always read as 0"
bitfld.word 0x00 2. "TO,Timeout Indicates that the number of data bytes in SCFRDR is less than the receive trigger count and that no further data has been received for at least 15 etu after the stop bit of the last receive data in asynchronous mode" "0: Indicates that data is being received or has,1: Indicates that no further receive data has been"
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rbitfld.word 0x00 1. "Reserved_1,Reserved This bit is always read as 0" "0,1"
bitfld.word 0x00 0. "ORER,Overrun Error Indicates that an overrun error has occurred in reception and abnormal termination is caused" "0: Indicates that data is being received or has,1: Indicates that an overrun error has occurred in"
group.word 0x30++0x01
line.word 0x00 "DL0,This register specifies the value of frequency division for the frequency divided clock generated by the BRG"
hexmask.word 0x00 0.--15. 1. "DL_15_0,Specifies a division value of frequency clock generated in BRG"
group.word 0x34++0x01
line.word 0x00 "CKS0,This register switches the output between the frequency divided clock and specifies a source clock for the external baud rate"
bitfld.word 0x00 15. "CKS,This bit switches the output between the frequency divided clock (SC_CLK) and external clock (SCK)" "0: Selects the frequency divided clock,1: Selects the external clock"
bitfld.word 0x00 14. "XIN,Selects the baud rate generator clock source for the external clock between SCIF_CLK and SCKi" "0: Selects the external clock (SCIF_CLK),1: Selects the internal clock (SCKi)"
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hexmask.word 0x00 0.--13. 1. "Reserved_0,Reserved These bits are always read as 0"
tree.end
tree "SCIF_INST_1"
base ad:0xE6E68000
group.word 0x00++0x01
line.word 0x00 "SCSMR1,SCSMR is a 16-bit register that sets the SCIF's serial transfer format and selects the baud rate generator clock source"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 7. "C_A_SHARP,Communication Mode Selects asynchronous mode or clock synchronous mode for the SCIF operation" "0: Asynchronous mode,1: Clock synchronous mode"
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bitfld.word 0x00 6. "CHR,Character Length Selects 7 or 8 bits for asynchronous mode data length" "0: 8 bits,1: 7 bits*"
bitfld.word 0x00 5. "PE,Parity Enable Determines whether parity bit is added in transmission or not and parity bit is checked in reception in asynchronous mode or not" "0: Disables parity bit addition and check,1: Enables parity bit addition and check"
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bitfld.word 0x00 4. "O_E_SHARP,Parity Mode Selects either even or odd parity to use in parity addition and check" "0: Even parity*1,1: Odd parity*2 Notes"
bitfld.word 0x00 3. "STOP,Stop Bit Length Selects 1 bit or 2 bits as the stop bit length in asynchronous mode" "0: 1 stop bit*1,1: 2 stop bits*2 Notes"
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rbitfld.word 0x00 2. "Reserved_2,Reserved This bit is always read as 0" "0,1"
bitfld.word 0x00 0.--1. "CKS_1_0,Clock Select 1 and 0 These bits select the clock source for the on-chip baud rate generator" "0: PCK,1: PCK /4,2: PCK /16,3: PCK /64"
group.byte 0x04++0x00
line.byte 0x00 "SCBRR1,SCBRR is an 8-bit register that sets the serial transmission/reception bit rate in accordance with the baud rate generator operating clock selected by the CKS1 and CKS0 bits in SCSMR"
hexmask.byte 0x00 0.--7. 1. "Reserved_0,The SCBRR setting is determined by the following equation: [Asynchronous mode] N = ( PCK / 64 x 22n-1 x B ) x"
group.word 0x08++0x01
line.word 0x00 "SCSCR1,SCSCR is a register that enables or disables transmission/reception by the SCIF enables or disables interrupt requests and selects transmission/reception clock source for the SCIF"
rbitfld.word 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 11. "TEIE,Transmit End Interrupt Enable When a transmit-end request is enabled by the TIE bit the TEIE bit selects the source of the transmit end interrupt request from the following: Setting the TDFE flag in SCFSR Setting the TEND flag in SCFSR.." "0: The transmit FIFO data empty (TDFE) interrupt,1: The transmit end (TEND) interrupt request is.."
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rbitfld.word 0x00 8.--10. "Reserved_8,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.word 0x00 7. "TIE,Transmit Interrupt Enable Enables or disables a transmit-FIFO-data-empty interrupt (TDFE) request when the TEIE bit in SCSCR is pulled 0 if all of the following conditions are satisfied: Serial transmit data has been transferred from SCFTDR to .." "0: When the TEIE bit is 0 disables,1: When the TEIE bit is 0 enables"
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bitfld.word 0x00 6. "RIE,Receive Interrupt Enable Enables or disables a receive-FIFO-data-full interrupt request when the RDF flag in SCFSR is set to 1 a receive-data-ready interrupt request when the DR flag in SCFSR is set to 1 a receive-error interrupt request when the .." "0: Disables receive-FIFO-data-full interrupt (RDF),1: Enables receive-FIFO-data-full interrupt (RDF)"
bitfld.word 0x00 5. "TE,Transmit Enable Enables or disables the start of SCIF serial transmission" "0: Disables transmission,1: Enables transmission"
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bitfld.word 0x00 4. "RE,Receive Enable Enables or disables the start of SCIF serial reception" "0: Disables reception.*,1: Enables reception"
bitfld.word 0x00 3. "REIE,Receive Error Interrupt Enable Enables or Disables generation of receive-error interrupt (ER) requests break interrupt (BRK) requests and overrun-error interrupt (ORER) requests" "0: Disables receive-error interrupt (ER) requests,1: Enables receive-error interrupt (ER) requests"
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bitfld.word 0x00 2. "TOIE,Timeout Interrupt Enable Enables or disables generation of timeout interrupt (TO) requests when the TO flag in SCLSR is set to 1" "0: Disables timeout interrupts (TO),1: Enables timeout interrupts (TO)"
bitfld.word 0x00 0.--1. "CKE_1_0,Clock Enable 1 and 0 These bits select the SCIF clock source and enables or disables the clock output from the SCK pin" "0,1,2,3"
group.byte 0x0C++0x00
line.byte 0x00 "SCFTDR1,SCFTDR is an 8-bit FIFO register of 16 stages that stores data for serial transmission"
hexmask.byte 0x00 0.--7. 1. "Reserved_0,"
group.word 0x10++0x01
line.word 0x00 "SCFSR1,SCFSR is a 16-bit register"
rbitfld.word 0x00 12.--15. "PER_3_0,Parity Error Count These bits indicate the number of parity errors of receive data stored in the receive FIFO data register (SCFRDR)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.word 0x00 8.--11. "FER_3_0,Framing Error Count These bits indicate the number of framing errors of receive data stored in the receive FIFO data register (SCFRDR)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 7. "ER,Receive Error Indicates that a framing error or a parity error has occurred in reception.*1 The ER flag is not affected by an error and retains its previous state when the RE bit is 0 in SCSCR" "0: Indicates that no framing or parity error has,1: Indicates that a framing error or a parity.."
bitfld.word 0x00 6. "TEND,Indicates that transmission has been ended * because there was no valid data in SCFTDR when the last bit of the transmit character was transmitted" "0: Indicates that transmission is in progress,1: Indicates that transmission has been ended"
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bitfld.word 0x00 5. "TDFE,Transmit FIFO Data Empty Indicates that the SCIF has transferred data from SCFTDR to SCTSR the number of data bytes in SCFTDR becomes equal to or less than the transmit trigger count specified by the TTRG1 and TTRG0 bits in SCFCR and SCFTDR is.." "0: Indicates that the number of transmit data,1: Indicates that the number of transmit data in"
bitfld.word 0x00 4. "BRK,Break Detect Indicates that a receive data break signal has been detected" "0: Indicates that no break signal has been..,1: Indicates that a break signal has been received"
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rbitfld.word 0x00 3. "FER,Framing Error Indicates that a framing error has been found in the data that is to be read next from SCFRDR in asynchronous mode" "0: Indicates that there is no framing error in the,1: Indicates that there is a framing error in the"
rbitfld.word 0x00 2. "PER,Parity Error This bit indicates that a parity error has been found in the data that is to be read next from SCFRDR in asynchronous mode" "0: Indicates that there is no parity error in the,1: Indicates that there is a parity error in the"
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bitfld.word 0x00 1. "RDF,Receive FIFO Data Full Indicates that the received data has been transferred from SCRSR to SCFRDR and the number of receive data bytes in SCFRDR becomes equal to or more than the receive trigger count specified by the RTRG1 and RTRG0 bits in SCFCR.." "0: Indicates that the number of receive data bytes,1: Indicates that the number of receive data bytes"
bitfld.word 0x00 0. "DR,Receive Data Ready Indicates that the number of data bytes in SCFRDR is less than the receive trigger count and that no further data has been received for at least 15 etu after the stop bit of the data received last in asynchronous mode.." "0: Indicates that data is being received or has,1: Indicates that no further receive data has been"
group.byte 0x14++0x00
line.byte 0x00 "SCFRDR1,SCFRDR is a 16-stage FIFO register that stores received serial data"
hexmask.byte 0x00 0.--7. 1. "Reserved_0,"
group.word 0x18++0x01
line.word 0x00 "SCFCR1,SCFCR is a register that resets data counts and sets the number of trigger data bytes for the transmit and receive FIFO registers"
rbitfld.word 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 8.--10. "RSTRG_2_0,RTS Output Active Trigger The RTS# signal is high when the number of receive data bytes stored in SCFRDR is equal to or more than the specified trigger number shown below" "0: 15,1: 1,2: 4,3: 6,4: 8,5: 10,6: 12,7: 14"
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bitfld.word 0x00 6.--7. "RTRG_1_0,Receive FIFO Data Count Trigger These bits specify the number of receive data bytes that makes the RDF (receive data full) flag to be set in SCFSR" "0: 1 (Asynchronous Mode and Clock Synchronous..,1: 4 (Asynchronous Mode) 2 (Clock Synchronous..,2: 8 (Asynchronous Mode and Clock Synchronous..,3: 14 (Asynchronous Mode and Clock Synchronous.."
bitfld.word 0x00 4.--5. "TTRG_1_0,Transmit FIFO Data Count Trigger These bits specify the number of remaining transmit data bytes that makes the transmit FIFO data register empty (TDFE) flag to be set in SCFSR" "0: 8 (8),1: 4 (12),2: 2 (14),3: 0 (16)"
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bitfld.word 0x00 3. "MCE,Modem Control Enable Enables or disables modem control signals CTS# and RTS#" "0: Disables modem signals.*,1: Enables modem signals"
bitfld.word 0x00 2. "TFRST,Transmit FIFO Data Register Reset Enables or disables a transmit FIFO data register reset that empties the register" "0: Disables the reset.*,1: Enables the reset"
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bitfld.word 0x00 1. "RFRST,Receive FIFO Data Register Reset Enables or disables a receive FIFO data register reset that empties the register" "0: Disables the reset.*,1: Enables the reset"
bitfld.word 0x00 0. "LOOP,Loopback Test Enables or disables the loopback test by internally connecting the transmit output pin (TX) and receive input pin (RX) and the RTS# pin and CTS# pin" "0: Disables the loopback test,1: Enables the loopback test"
group.word 0x1C++0x01
line.word 0x00 "SCFDR1,SCFDR is a 16-bit register that indicates the number of data bytes stored in SCFTDR and that in SCFRDR"
rbitfld.word 0x00 13.--15. "Reserved_13,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
rbitfld.word 0x00 8.--12. "T_4_0,These bits show the number of data bytes untransmitted and still stored in SCFTDR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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rbitfld.word 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
rbitfld.word 0x00 0.--4. "R_4_0,These bits show the number of receive data stored in SCFRDR in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x20++0x01
line.word 0x00 "SCSPTR1,SCSPTR controls multiplexed input/output and data on the serial communication interface (SCIF) ports"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 7. "RTSIO,Serial Port RTS# Pin Input/output Specifies input or output for the serial port RTS# pin" "0: Indicates that this bit does not output the,1: Indicates that this bit outputs the value of.."
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bitfld.word 0x00 6. "RTSDT,Serial Port RTS# Pin Data Specifies the input/output data level of the serial port RTS# pin" "0: Indicates that the input/output data is low..,1: Indicates that the input/output data is high.."
bitfld.word 0x00 5. "CTSIO,Serial Port CTS# Pin Input/output Specifies input or output for the serial port CTS# pin" "0: Indicates that the CTSDT bit value is not..,1: Indicates that the CTSDT bit value is output to"
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bitfld.word 0x00 4. "CTSDT,Serial Port CTS# Pin Data Specifies the input/output data level of the serial port CTS# pin" "0: Indicates that the input/output data is low..,1: Indicates that the input/output data is high.."
bitfld.word 0x00 3. "SCKIO,Serial Port Clock Pin Input/output Specifies input or output for the serial port SCK pin" "0: Indicates that the SCKDT bit value is not..,1: Indicates that the SCKDT bit value is output to"
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bitfld.word 0x00 2. "SCKDT,Serial Port Clock Pin Data Specifies the input/output data level of the serial port SCK pin" "0: Indicates that the input/output data is low..,1: Indicates that the input/output data is high.."
bitfld.word 0x00 1. "SPB2IO,Serial Port Break Input/Output Specifies the output condition of the serial port TX pin" "0: Indicates that the SPB2DT bit value is not,1: Indicates that the SPB2DT bit value is output.."
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bitfld.word 0x00 0. "SPB2DT,Serial Port Break Data Specifies the input level of the serial port RX pin and the output level of the TX pin" "0: Indicates that the input/output data is low..,1: Indicates that the input/output data is high.."
group.word 0x24++0x01
line.word 0x00 "SCLSR1,"
hexmask.word 0x00 3.--15. 1. "Reserved_3,Reserved These bits are always read as 0"
bitfld.word 0x00 2. "TO,Timeout Indicates that the number of data bytes in SCFRDR is less than the receive trigger count and that no further data has been received for at least 15 etu after the stop bit of the last receive data in asynchronous mode" "0: Indicates that data is being received or has,1: Indicates that no further receive data has been"
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rbitfld.word 0x00 1. "Reserved_1,Reserved This bit is always read as 0" "0,1"
bitfld.word 0x00 0. "ORER,Overrun Error Indicates that an overrun error has occurred in reception and abnormal termination is caused" "0: Indicates that data is being received or has,1: Indicates that an overrun error has occurred in"
group.word 0x30++0x01
line.word 0x00 "DL1,This register specifies the value of frequency division for the frequency divided clock generated by the BRG"
hexmask.word 0x00 0.--15. 1. "DL_15_0,Specifies a division value of frequency clock generated in BRG"
group.word 0x34++0x01
line.word 0x00 "CKS1,This register switches the output between the frequency divided clock and specifies a source clock for the external baud rate"
bitfld.word 0x00 15. "CKS,This bit switches the output between the frequency divided clock (SC_CLK) and external clock (SCK)" "0: Selects the frequency divided clock,1: Selects the external clock"
bitfld.word 0x00 14. "XIN,Selects the baud rate generator clock source for the external clock between SCIF_CLK and SCKi" "0: Selects the external clock (SCIF_CLK),1: Selects the internal clock (SCKi)"
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hexmask.word 0x00 0.--13. 1. "Reserved_0,Reserved These bits are always read as 0"
tree.end
tree "SCIF_INST_2"
base ad:0xE6C50000
group.word 0x00++0x01
line.word 0x00 "SCSMR2,SCSMR is a 16-bit register that sets the SCIF's serial transfer format and selects the baud rate generator clock source"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 7. "C_A_SHARP,Communication Mode Selects asynchronous mode or clock synchronous mode for the SCIF operation" "0: Asynchronous mode,1: Clock synchronous mode"
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bitfld.word 0x00 6. "CHR,Character Length Selects 7 or 8 bits for asynchronous mode data length" "0: 8 bits,1: 7 bits*"
bitfld.word 0x00 5. "PE,Parity Enable Determines whether parity bit is added in transmission or not and parity bit is checked in reception in asynchronous mode or not" "0: Disables parity bit addition and check,1: Enables parity bit addition and check"
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bitfld.word 0x00 4. "O_E_SHARP,Parity Mode Selects either even or odd parity to use in parity addition and check" "0: Even parity*1,1: Odd parity*2 Notes"
bitfld.word 0x00 3. "STOP,Stop Bit Length Selects 1 bit or 2 bits as the stop bit length in asynchronous mode" "0: 1 stop bit*1,1: 2 stop bits*2 Notes"
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rbitfld.word 0x00 2. "Reserved_2,Reserved This bit is always read as 0" "0,1"
bitfld.word 0x00 0.--1. "CKS_1_0,Clock Select 1 and 0 These bits select the clock source for the on-chip baud rate generator" "0: PCK,1: PCK /4,2: PCK /16,3: PCK /64"
group.byte 0x04++0x00
line.byte 0x00 "SCBRR2,SCBRR is an 8-bit register that sets the serial transmission/reception bit rate in accordance with the baud rate generator operating clock selected by the CKS1 and CKS0 bits in SCSMR"
hexmask.byte 0x00 0.--7. 1. "Reserved_0,The SCBRR setting is determined by the following equation: [Asynchronous mode] N = ( PCK / 64 x 22n-1 x B ) x"
group.word 0x08++0x01
line.word 0x00 "SCSCR2,SCSCR is a register that enables or disables transmission/reception by the SCIF enables or disables interrupt requests and selects transmission/reception clock source for the SCIF"
rbitfld.word 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 11. "TEIE,Transmit End Interrupt Enable When a transmit-end request is enabled by the TIE bit the TEIE bit selects the source of the transmit end interrupt request from the following: Setting the TDFE flag in SCFSR Setting the TEND flag in SCFSR.." "0: The transmit FIFO data empty (TDFE) interrupt,1: The transmit end (TEND) interrupt request is.."
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rbitfld.word 0x00 8.--10. "Reserved_8,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.word 0x00 7. "TIE,Transmit Interrupt Enable Enables or disables a transmit-FIFO-data-empty interrupt (TDFE) request when the TEIE bit in SCSCR is pulled 0 if all of the following conditions are satisfied: Serial transmit data has been transferred from SCFTDR to .." "0: When the TEIE bit is 0 disables,1: When the TEIE bit is 0 enables"
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bitfld.word 0x00 6. "RIE,Receive Interrupt Enable Enables or disables a receive-FIFO-data-full interrupt request when the RDF flag in SCFSR is set to 1 a receive-data-ready interrupt request when the DR flag in SCFSR is set to 1 a receive-error interrupt request when the .." "0: Disables receive-FIFO-data-full interrupt (RDF),1: Enables receive-FIFO-data-full interrupt (RDF)"
bitfld.word 0x00 5. "TE,Transmit Enable Enables or disables the start of SCIF serial transmission" "0: Disables transmission,1: Enables transmission"
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bitfld.word 0x00 4. "RE,Receive Enable Enables or disables the start of SCIF serial reception" "0: Disables reception.*,1: Enables reception"
bitfld.word 0x00 3. "REIE,Receive Error Interrupt Enable Enables or Disables generation of receive-error interrupt (ER) requests break interrupt (BRK) requests and overrun-error interrupt (ORER) requests" "0: Disables receive-error interrupt (ER) requests,1: Enables receive-error interrupt (ER) requests"
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bitfld.word 0x00 2. "TOIE,Timeout Interrupt Enable Enables or disables generation of timeout interrupt (TO) requests when the TO flag in SCLSR is set to 1" "0: Disables timeout interrupts (TO),1: Enables timeout interrupts (TO)"
bitfld.word 0x00 0.--1. "CKE_1_0,Clock Enable 1 and 0 These bits select the SCIF clock source and enables or disables the clock output from the SCK pin" "0,1,2,3"
group.byte 0x0C++0x00
line.byte 0x00 "SCFTDR2,SCFTDR is an 8-bit FIFO register of 16 stages that stores data for serial transmission"
hexmask.byte 0x00 0.--7. 1. "Reserved_0,"
group.word 0x10++0x01
line.word 0x00 "SCFSR2,SCFSR is a 16-bit register"
rbitfld.word 0x00 12.--15. "PER_3_0,Parity Error Count These bits indicate the number of parity errors of receive data stored in the receive FIFO data register (SCFRDR)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.word 0x00 8.--11. "FER_3_0,Framing Error Count These bits indicate the number of framing errors of receive data stored in the receive FIFO data register (SCFRDR)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 7. "ER,Receive Error Indicates that a framing error or a parity error has occurred in reception.*1 The ER flag is not affected by an error and retains its previous state when the RE bit is 0 in SCSCR" "0: Indicates that no framing or parity error has,1: Indicates that a framing error or a parity.."
bitfld.word 0x00 6. "TEND,Indicates that transmission has been ended * because there was no valid data in SCFTDR when the last bit of the transmit character was transmitted" "0: Indicates that transmission is in progress,1: Indicates that transmission has been ended"
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bitfld.word 0x00 5. "TDFE,Transmit FIFO Data Empty Indicates that the SCIF has transferred data from SCFTDR to SCTSR the number of data bytes in SCFTDR becomes equal to or less than the transmit trigger count specified by the TTRG1 and TTRG0 bits in SCFCR and SCFTDR is.." "0: Indicates that the number of transmit data,1: Indicates that the number of transmit data in"
bitfld.word 0x00 4. "BRK,Break Detect Indicates that a receive data break signal has been detected" "0: Indicates that no break signal has been..,1: Indicates that a break signal has been received"
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rbitfld.word 0x00 3. "FER,Framing Error Indicates that a framing error has been found in the data that is to be read next from SCFRDR in asynchronous mode" "0: Indicates that there is no framing error in the,1: Indicates that there is a framing error in the"
rbitfld.word 0x00 2. "PER,Parity Error This bit indicates that a parity error has been found in the data that is to be read next from SCFRDR in asynchronous mode" "0: Indicates that there is no parity error in the,1: Indicates that there is a parity error in the"
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bitfld.word 0x00 1. "RDF,Receive FIFO Data Full Indicates that the received data has been transferred from SCRSR to SCFRDR and the number of receive data bytes in SCFRDR becomes equal to or more than the receive trigger count specified by the RTRG1 and RTRG0 bits in SCFCR.." "0: Indicates that the number of receive data bytes,1: Indicates that the number of receive data bytes"
bitfld.word 0x00 0. "DR,Receive Data Ready Indicates that the number of data bytes in SCFRDR is less than the receive trigger count and that no further data has been received for at least 15 etu after the stop bit of the data received last in asynchronous mode.." "0: Indicates that data is being received or has,1: Indicates that no further receive data has been"
group.byte 0x14++0x00
line.byte 0x00 "SCFRDR2,SCFRDR is a 16-stage FIFO register that stores received serial data"
hexmask.byte 0x00 0.--7. 1. "Reserved_0,"
group.word 0x18++0x01
line.word 0x00 "SCFCR2,SCFCR is a register that resets data counts and sets the number of trigger data bytes for the transmit and receive FIFO registers"
rbitfld.word 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 8.--10. "RSTRG_2_0,RTS Output Active Trigger The RTS# signal is high when the number of receive data bytes stored in SCFRDR is equal to or more than the specified trigger number shown below" "0: 15,1: 1,2: 4,3: 6,4: 8,5: 10,6: 12,7: 14"
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bitfld.word 0x00 6.--7. "RTRG_1_0,Receive FIFO Data Count Trigger These bits specify the number of receive data bytes that makes the RDF (receive data full) flag to be set in SCFSR" "0: 1 (Asynchronous Mode and Clock Synchronous..,1: 4 (Asynchronous Mode) 2 (Clock Synchronous..,2: 8 (Asynchronous Mode and Clock Synchronous..,3: 14 (Asynchronous Mode and Clock Synchronous.."
bitfld.word 0x00 4.--5. "TTRG_1_0,Transmit FIFO Data Count Trigger These bits specify the number of remaining transmit data bytes that makes the transmit FIFO data register empty (TDFE) flag to be set in SCFSR" "0: 8 (8),1: 4 (12),2: 2 (14),3: 0 (16)"
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bitfld.word 0x00 3. "MCE,Modem Control Enable Enables or disables modem control signals CTS# and RTS#" "0: Disables modem signals.*,1: Enables modem signals"
bitfld.word 0x00 2. "TFRST,Transmit FIFO Data Register Reset Enables or disables a transmit FIFO data register reset that empties the register" "0: Disables the reset.*,1: Enables the reset"
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bitfld.word 0x00 1. "RFRST,Receive FIFO Data Register Reset Enables or disables a receive FIFO data register reset that empties the register" "0: Disables the reset.*,1: Enables the reset"
bitfld.word 0x00 0. "LOOP,Loopback Test Enables or disables the loopback test by internally connecting the transmit output pin (TX) and receive input pin (RX) and the RTS# pin and CTS# pin" "0: Disables the loopback test,1: Enables the loopback test"
group.word 0x1C++0x01
line.word 0x00 "SCFDR2,SCFDR is a 16-bit register that indicates the number of data bytes stored in SCFTDR and that in SCFRDR"
rbitfld.word 0x00 13.--15. "Reserved_13,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
rbitfld.word 0x00 8.--12. "T_4_0,These bits show the number of data bytes untransmitted and still stored in SCFTDR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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rbitfld.word 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
rbitfld.word 0x00 0.--4. "R_4_0,These bits show the number of receive data stored in SCFRDR in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x20++0x01
line.word 0x00 "SCSPTR2,SCSPTR controls multiplexed input/output and data on the serial communication interface (SCIF) ports"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 7. "RTSIO,Serial Port RTS# Pin Input/output Specifies input or output for the serial port RTS# pin" "0: Indicates that this bit does not output the,1: Indicates that this bit outputs the value of.."
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bitfld.word 0x00 6. "RTSDT,Serial Port RTS# Pin Data Specifies the input/output data level of the serial port RTS# pin" "0: Indicates that the input/output data is low..,1: Indicates that the input/output data is high.."
bitfld.word 0x00 5. "CTSIO,Serial Port CTS# Pin Input/output Specifies input or output for the serial port CTS# pin" "0: Indicates that the CTSDT bit value is not..,1: Indicates that the CTSDT bit value is output to"
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bitfld.word 0x00 4. "CTSDT,Serial Port CTS# Pin Data Specifies the input/output data level of the serial port CTS# pin" "0: Indicates that the input/output data is low..,1: Indicates that the input/output data is high.."
bitfld.word 0x00 3. "SCKIO,Serial Port Clock Pin Input/output Specifies input or output for the serial port SCK pin" "0: Indicates that the SCKDT bit value is not..,1: Indicates that the SCKDT bit value is output to"
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bitfld.word 0x00 2. "SCKDT,Serial Port Clock Pin Data Specifies the input/output data level of the serial port SCK pin" "0: Indicates that the input/output data is low..,1: Indicates that the input/output data is high.."
bitfld.word 0x00 1. "SPB2IO,Serial Port Break Input/Output Specifies the output condition of the serial port TX pin" "0: Indicates that the SPB2DT bit value is not,1: Indicates that the SPB2DT bit value is output.."
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bitfld.word 0x00 0. "SPB2DT,Serial Port Break Data Specifies the input level of the serial port RX pin and the output level of the TX pin" "0: Indicates that the input/output data is low..,1: Indicates that the input/output data is high.."
group.word 0x24++0x01
line.word 0x00 "SCLSR2,"
hexmask.word 0x00 3.--15. 1. "Reserved_3,Reserved These bits are always read as 0"
bitfld.word 0x00 2. "TO,Timeout Indicates that the number of data bytes in SCFRDR is less than the receive trigger count and that no further data has been received for at least 15 etu after the stop bit of the last receive data in asynchronous mode" "0: Indicates that data is being received or has,1: Indicates that no further receive data has been"
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rbitfld.word 0x00 1. "Reserved_1,Reserved This bit is always read as 0" "0,1"
bitfld.word 0x00 0. "ORER,Overrun Error Indicates that an overrun error has occurred in reception and abnormal termination is caused" "0: Indicates that data is being received or has,1: Indicates that an overrun error has occurred in"
group.word 0x30++0x01
line.word 0x00 "DL2,This register specifies the value of frequency division for the frequency divided clock generated by the BRG"
hexmask.word 0x00 0.--15. 1. "DL_15_0,Specifies a division value of frequency clock generated in BRG"
group.word 0x34++0x01
line.word 0x00 "CKS2,This register switches the output between the frequency divided clock and specifies a source clock for the external baud rate"
bitfld.word 0x00 15. "CKS,This bit switches the output between the frequency divided clock (SC_CLK) and external clock (SCK)" "0: Selects the frequency divided clock,1: Selects the external clock"
bitfld.word 0x00 14. "XIN,Selects the baud rate generator clock source for the external clock between SCIF_CLK and SCKi" "0: Selects the external clock (SCIF_CLK),1: Selects the internal clock (SCKi)"
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hexmask.word 0x00 0.--13. 1. "Reserved_0,Reserved These bits are always read as 0"
tree.end
tree "SCIF_INST_3"
base ad:0xE6C40000
group.word 0x00++0x01
line.word 0x00 "SCSMR3,SCSMR is a 16-bit register that sets the SCIF's serial transfer format and selects the baud rate generator clock source"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 7. "C_A_SHARP,Communication Mode Selects asynchronous mode or clock synchronous mode for the SCIF operation" "0: Asynchronous mode,1: Clock synchronous mode"
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bitfld.word 0x00 6. "CHR,Character Length Selects 7 or 8 bits for asynchronous mode data length" "0: 8 bits,1: 7 bits*"
bitfld.word 0x00 5. "PE,Parity Enable Determines whether parity bit is added in transmission or not and parity bit is checked in reception in asynchronous mode or not" "0: Disables parity bit addition and check,1: Enables parity bit addition and check"
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bitfld.word 0x00 4. "O_E_SHARP,Parity Mode Selects either even or odd parity to use in parity addition and check" "0: Even parity*1,1: Odd parity*2 Notes"
bitfld.word 0x00 3. "STOP,Stop Bit Length Selects 1 bit or 2 bits as the stop bit length in asynchronous mode" "0: 1 stop bit*1,1: 2 stop bits*2 Notes"
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rbitfld.word 0x00 2. "Reserved_2,Reserved This bit is always read as 0" "0,1"
bitfld.word 0x00 0.--1. "CKS_1_0,Clock Select 1 and 0 These bits select the clock source for the on-chip baud rate generator" "0: PCK,1: PCK /4,2: PCK /16,3: PCK /64"
group.byte 0x04++0x00
line.byte 0x00 "SCBRR3,SCBRR is an 8-bit register that sets the serial transmission/reception bit rate in accordance with the baud rate generator operating clock selected by the CKS1 and CKS0 bits in SCSMR"
hexmask.byte 0x00 0.--7. 1. "Reserved_0,The SCBRR setting is determined by the following equation: [Asynchronous mode] N = ( PCK / 64 x 22n-1 x B ) x"
group.word 0x08++0x01
line.word 0x00 "SCSCR3,SCSCR is a register that enables or disables transmission/reception by the SCIF enables or disables interrupt requests and selects transmission/reception clock source for the SCIF"
rbitfld.word 0x00 12.--15. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 11. "TEIE,Transmit End Interrupt Enable When a transmit-end request is enabled by the TIE bit the TEIE bit selects the source of the transmit end interrupt request from the following: Setting the TDFE flag in SCFSR Setting the TEND flag in SCFSR.." "0: The transmit FIFO data empty (TDFE) interrupt,1: The transmit end (TEND) interrupt request is.."
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rbitfld.word 0x00 8.--10. "Reserved_8,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.word 0x00 7. "TIE,Transmit Interrupt Enable Enables or disables a transmit-FIFO-data-empty interrupt (TDFE) request when the TEIE bit in SCSCR is pulled 0 if all of the following conditions are satisfied: Serial transmit data has been transferred from SCFTDR to .." "0: When the TEIE bit is 0 disables,1: When the TEIE bit is 0 enables"
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bitfld.word 0x00 6. "RIE,Receive Interrupt Enable Enables or disables a receive-FIFO-data-full interrupt request when the RDF flag in SCFSR is set to 1 a receive-data-ready interrupt request when the DR flag in SCFSR is set to 1 a receive-error interrupt request when the .." "0: Disables receive-FIFO-data-full interrupt (RDF),1: Enables receive-FIFO-data-full interrupt (RDF)"
bitfld.word 0x00 5. "TE,Transmit Enable Enables or disables the start of SCIF serial transmission" "0: Disables transmission,1: Enables transmission"
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bitfld.word 0x00 4. "RE,Receive Enable Enables or disables the start of SCIF serial reception" "0: Disables reception.*,1: Enables reception"
bitfld.word 0x00 3. "REIE,Receive Error Interrupt Enable Enables or Disables generation of receive-error interrupt (ER) requests break interrupt (BRK) requests and overrun-error interrupt (ORER) requests" "0: Disables receive-error interrupt (ER) requests,1: Enables receive-error interrupt (ER) requests"
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bitfld.word 0x00 2. "TOIE,Timeout Interrupt Enable Enables or disables generation of timeout interrupt (TO) requests when the TO flag in SCLSR is set to 1" "0: Disables timeout interrupts (TO),1: Enables timeout interrupts (TO)"
bitfld.word 0x00 0.--1. "CKE_1_0,Clock Enable 1 and 0 These bits select the SCIF clock source and enables or disables the clock output from the SCK pin" "0,1,2,3"
group.byte 0x0C++0x00
line.byte 0x00 "SCFTDR3,SCFTDR is an 8-bit FIFO register of 16 stages that stores data for serial transmission"
hexmask.byte 0x00 0.--7. 1. "Reserved_0,"
group.word 0x10++0x01
line.word 0x00 "SCFSR3,SCFSR is a 16-bit register"
rbitfld.word 0x00 12.--15. "PER_3_0,Parity Error Count These bits indicate the number of parity errors of receive data stored in the receive FIFO data register (SCFRDR)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.word 0x00 8.--11. "FER_3_0,Framing Error Count These bits indicate the number of framing errors of receive data stored in the receive FIFO data register (SCFRDR)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 7. "ER,Receive Error Indicates that a framing error or a parity error has occurred in reception.*1 The ER flag is not affected by an error and retains its previous state when the RE bit is 0 in SCSCR" "0: Indicates that no framing or parity error has,1: Indicates that a framing error or a parity.."
bitfld.word 0x00 6. "TEND,Indicates that transmission has been ended * because there was no valid data in SCFTDR when the last bit of the transmit character was transmitted" "0: Indicates that transmission is in progress,1: Indicates that transmission has been ended"
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bitfld.word 0x00 5. "TDFE,Transmit FIFO Data Empty Indicates that the SCIF has transferred data from SCFTDR to SCTSR the number of data bytes in SCFTDR becomes equal to or less than the transmit trigger count specified by the TTRG1 and TTRG0 bits in SCFCR and SCFTDR is.." "0: Indicates that the number of transmit data,1: Indicates that the number of transmit data in"
bitfld.word 0x00 4. "BRK,Break Detect Indicates that a receive data break signal has been detected" "0: Indicates that no break signal has been..,1: Indicates that a break signal has been received"
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rbitfld.word 0x00 3. "FER,Framing Error Indicates that a framing error has been found in the data that is to be read next from SCFRDR in asynchronous mode" "0: Indicates that there is no framing error in the,1: Indicates that there is a framing error in the"
rbitfld.word 0x00 2. "PER,Parity Error This bit indicates that a parity error has been found in the data that is to be read next from SCFRDR in asynchronous mode" "0: Indicates that there is no parity error in the,1: Indicates that there is a parity error in the"
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bitfld.word 0x00 1. "RDF,Receive FIFO Data Full Indicates that the received data has been transferred from SCRSR to SCFRDR and the number of receive data bytes in SCFRDR becomes equal to or more than the receive trigger count specified by the RTRG1 and RTRG0 bits in SCFCR.." "0: Indicates that the number of receive data bytes,1: Indicates that the number of receive data bytes"
bitfld.word 0x00 0. "DR,Receive Data Ready Indicates that the number of data bytes in SCFRDR is less than the receive trigger count and that no further data has been received for at least 15 etu after the stop bit of the data received last in asynchronous mode.." "0: Indicates that data is being received or has,1: Indicates that no further receive data has been"
group.byte 0x14++0x00
line.byte 0x00 "SCFRDR3,SCFRDR is a 16-stage FIFO register that stores received serial data"
hexmask.byte 0x00 0.--7. 1. "Reserved_0,"
group.word 0x18++0x01
line.word 0x00 "SCFCR3,SCFCR is a register that resets data counts and sets the number of trigger data bytes for the transmit and receive FIFO registers"
rbitfld.word 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 8.--10. "RSTRG_2_0,RTS Output Active Trigger The RTS# signal is high when the number of receive data bytes stored in SCFRDR is equal to or more than the specified trigger number shown below" "0: 15,1: 1,2: 4,3: 6,4: 8,5: 10,6: 12,7: 14"
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bitfld.word 0x00 6.--7. "RTRG_1_0,Receive FIFO Data Count Trigger These bits specify the number of receive data bytes that makes the RDF (receive data full) flag to be set in SCFSR" "0: 1 (Asynchronous Mode and Clock Synchronous..,1: 4 (Asynchronous Mode) 2 (Clock Synchronous..,2: 8 (Asynchronous Mode and Clock Synchronous..,3: 14 (Asynchronous Mode and Clock Synchronous.."
bitfld.word 0x00 4.--5. "TTRG_1_0,Transmit FIFO Data Count Trigger These bits specify the number of remaining transmit data bytes that makes the transmit FIFO data register empty (TDFE) flag to be set in SCFSR" "0: 8 (8),1: 4 (12),2: 2 (14),3: 0 (16)"
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bitfld.word 0x00 3. "MCE,Modem Control Enable Enables or disables modem control signals CTS# and RTS#" "0: Disables modem signals.*,1: Enables modem signals"
bitfld.word 0x00 2. "TFRST,Transmit FIFO Data Register Reset Enables or disables a transmit FIFO data register reset that empties the register" "0: Disables the reset.*,1: Enables the reset"
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bitfld.word 0x00 1. "RFRST,Receive FIFO Data Register Reset Enables or disables a receive FIFO data register reset that empties the register" "0: Disables the reset.*,1: Enables the reset"
bitfld.word 0x00 0. "LOOP,Loopback Test Enables or disables the loopback test by internally connecting the transmit output pin (TX) and receive input pin (RX) and the RTS# pin and CTS# pin" "0: Disables the loopback test,1: Enables the loopback test"
group.word 0x1C++0x01
line.word 0x00 "SCFDR3,SCFDR is a 16-bit register that indicates the number of data bytes stored in SCFTDR and that in SCFRDR"
rbitfld.word 0x00 13.--15. "Reserved_13,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
rbitfld.word 0x00 8.--12. "T_4_0,These bits show the number of data bytes untransmitted and still stored in SCFTDR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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rbitfld.word 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
rbitfld.word 0x00 0.--4. "R_4_0,These bits show the number of receive data stored in SCFRDR in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x20++0x01
line.word 0x00 "SCSPTR3,SCSPTR controls multiplexed input/output and data on the serial communication interface (SCIF) ports"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 7. "RTSIO,Serial Port RTS# Pin Input/output Specifies input or output for the serial port RTS# pin" "0: Indicates that this bit does not output the,1: Indicates that this bit outputs the value of.."
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bitfld.word 0x00 6. "RTSDT,Serial Port RTS# Pin Data Specifies the input/output data level of the serial port RTS# pin" "0: Indicates that the input/output data is low..,1: Indicates that the input/output data is high.."
bitfld.word 0x00 5. "CTSIO,Serial Port CTS# Pin Input/output Specifies input or output for the serial port CTS# pin" "0: Indicates that the CTSDT bit value is not..,1: Indicates that the CTSDT bit value is output to"
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bitfld.word 0x00 4. "CTSDT,Serial Port CTS# Pin Data Specifies the input/output data level of the serial port CTS# pin" "0: Indicates that the input/output data is low..,1: Indicates that the input/output data is high.."
bitfld.word 0x00 3. "SCKIO,Serial Port Clock Pin Input/output Specifies input or output for the serial port SCK pin" "0: Indicates that the SCKDT bit value is not..,1: Indicates that the SCKDT bit value is output to"
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bitfld.word 0x00 2. "SCKDT,Serial Port Clock Pin Data Specifies the input/output data level of the serial port SCK pin" "0: Indicates that the input/output data is low..,1: Indicates that the input/output data is high.."
bitfld.word 0x00 1. "SPB2IO,Serial Port Break Input/Output Specifies the output condition of the serial port TX pin" "0: Indicates that the SPB2DT bit value is not,1: Indicates that the SPB2DT bit value is output.."
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bitfld.word 0x00 0. "SPB2DT,Serial Port Break Data Specifies the input level of the serial port RX pin and the output level of the TX pin" "0: Indicates that the input/output data is low..,1: Indicates that the input/output data is high.."
group.word 0x24++0x01
line.word 0x00 "SCLSR3,"
hexmask.word 0x00 3.--15. 1. "Reserved_3,Reserved These bits are always read as 0"
bitfld.word 0x00 2. "TO,Timeout Indicates that the number of data bytes in SCFRDR is less than the receive trigger count and that no further data has been received for at least 15 etu after the stop bit of the last receive data in asynchronous mode" "0: Indicates that data is being received or has,1: Indicates that no further receive data has been"
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rbitfld.word 0x00 1. "Reserved_1,Reserved This bit is always read as 0" "0,1"
bitfld.word 0x00 0. "ORER,Overrun Error Indicates that an overrun error has occurred in reception and abnormal termination is caused" "0: Indicates that data is being received or has,1: Indicates that an overrun error has occurred in"
group.word 0x30++0x01
line.word 0x00 "DL3,This register specifies the value of frequency division for the frequency divided clock generated by the BRG"
hexmask.word 0x00 0.--15. 1. "DL_15_0,Specifies a division value of frequency clock generated in BRG"
group.word 0x34++0x01
line.word 0x00 "CKS3,This register switches the output between the frequency divided clock and specifies a source clock for the external baud rate"
bitfld.word 0x00 15. "CKS,This bit switches the output between the frequency divided clock (SC_CLK) and external clock (SCK)" "0: Selects the frequency divided clock,1: Selects the external clock"
bitfld.word 0x00 14. "XIN,Selects the baud rate generator clock source for the external clock between SCIF_CLK and SCKi" "0: Selects the external clock (SCIF_CLK),1: Selects the internal clock (SCKi)"
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hexmask.word 0x00 0.--13. 1. "Reserved_0,Reserved These bits are always read as 0"
tree.end
tree.end
tree "HSCIF"
tree "HSCIF_INST_0"
base ad:0xE6540000
group.word 0x00++0x01
line.word 0x00 "HSSMR0,"
hexmask.word 0x00 7.--15. 1. "Reserved_7,Reserved These bits are always read as 0"
bitfld.word 0x00 6. "CHR,Character Length Selects 7 or 8 bits for data length" "0: 8 bits,1: 7 bits"
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bitfld.word 0x00 5. "PE,Parity Enable Determines whether parity bit is added in transmission or not and parity bit is checked in reception or not" "0: Disables parity bit addition and check,1: Enables parity bit addition and check"
bitfld.word 0x00 4. "O_E_SHARP,Parity Mode Selects either even or odd parity to use in parity addition and check" "0: Even parity,1: Odd parity When even parity is"
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bitfld.word 0x00 3. "STOP,Stop Bit Length Selects 1 bit or 2 bits as the stop bit length" "0: 1 stop bit*1,1: 2 stop bits*2 Notes"
rbitfld.word 0x00 2. "Reserved_2,Reserved This bit is always read as 0" "0,1"
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bitfld.word 0x00 0.--1. "CKS_1_0,Clock Select 1 and 0 These bits select the clock source for the on-chip baud rate generator" "0: Internal clock,1: Internal clock/4,2: Internal clock/16,3: Internal clock/64"
group.byte 0x04++0x00
line.byte 0x00 "HSBRR0,"
hexmask.byte 0x00 0.--7. 1. "Reserved_0,HSBRR is an 8-bit register that sets the serial transmission/reception bit rate in accordance with the baud rate generator operating clock selected by the CKS [1:0] bits in HSSMR"
group.word 0x08++0x01
line.word 0x00 "HSSCR0,HSSCR is a register that enables or disables transmission/reception by the HSCIF enables or disables interrupt requests and selects transmission/reception clock source for the HSCIF"
bitfld.word 0x00 14.--15. "TOT_1_0,Set the time for a data ready (DR) or a timeout (TO) to be set in asynchronous mode" "0: 15 etu*,1: 31 etu,2: 47 etu,3: 63 etu"
rbitfld.word 0x00 12.--13. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.word 0x00 11. "TEIE,Transmit End Interrupt Enable When a transmit-end request is enabled by the TIE bit the TEIE bit selects the source of the transmit end interrupt request from the following: Setting the TDFE flag in HSFSR  Setting the TEND flag in HSFSR.." "0: The transmit FIFO data empty (TDFE) interrupt,1: The transmit end (TEND) interrupt request is.."
rbitfld.word 0x00 8.--10. "Reserved_8,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 7. "TIE,Transmit Interrupt Enable Enables or disables a transmit-FIFO-data-empty interrupt (TDFE) request when the TEIE bit in HSSCR is pulled 0 if all of the following conditions are satisfied: Serial transmit data has been transferred from HSFTDR to .." "0: When the TEIE bit is 0 disables,1: When the TEIE bit is 0 enables"
bitfld.word 0x00 6. "RIE,Receive Interrupt Enable Enables or disables a receive-FIFO-data-full interrupt request when the RDF flag in HSFSR is set to 1 a receive-data-ready interrupt request when the DR flag in HSFSR is set to 1 a receive-error interrupt request when the .." "0: Disables receive-FIFO-data-full interrupts..,1: Enables receive-FIFO-data-full interrupt (RDF)"
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bitfld.word 0x00 5. "TE,Transmit Enable Enables or disables the start of HSCIF serial transmission" "0: Disables transmission,1: Enables transmission"
bitfld.word 0x00 4. "RE,Receive Enable Enables or disables the start of HSCIF serial reception" "0: Disables reception.*,1: Enables reception"
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bitfld.word 0x00 3. "REIE,Receive Error Interrupt Enable Enables or Disables generation of receive-error interrupt (ER) requests break interrupt (BRK) requests and overrun-error interrupt (ORER) requests" "0: Disables receive-error interrupt (ER) requests,1: Enables receive-error interrupt (ER) requests"
bitfld.word 0x00 2. "TOIE,Timeout Interrupt Enable Enables or disables generation of timeout interrupt (TO) requests when the TO flag in HSLSR is set to 1" "0: Disables timeout interrupts (TO),1: Enables timeout interrupts (TO)"
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bitfld.word 0x00 0.--1. "CKE_1_0,Clock Enable 1 and" "0,1,2,3"
group.byte 0x0C++0x00
line.byte 0x00 "HSFTDR0,"
hexmask.byte 0x00 0.--7. 1. "Reserved_0,HSFTDR is an 8-bit FIFO register of 128 stages that stores data for serial transmission"
group.word 0x10++0x01
line.word 0x00 "HSFSR0,HSFSR is a 16-bit register"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 7. "ER,Receive Error Indicates that a framing error or a parity error has occurred in reception" "0: Indicates that no framing or parity error has,1: Indicates that a framing error or a parity.."
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bitfld.word 0x00 6. "TEND,Transmit End Indicates that transmission has been ended because there was no valid data in HSFTDR when the last bit of the transmit character was transmitted" "0: Indicates that transmission is in progress,1: Indicates that transmission has been ended"
bitfld.word 0x00 5. "TDFE,Transmit FIFO Data Empty Indicates that the HSCIF has transferred data from HSFTDR to HSTSR the number of data bytes in HSFTDR becomes equal to or less than the transmit trigger count specified by the HSTTRGR and HSFTDR is ready to be written by.." "0: Indicates that the number of transmit data,1: Indicates that the number of transmit data in"
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bitfld.word 0x00 4. "BRK,Break Detect Indicates that a receive data break signal has been detected" "0: Indicates that no break signal has been..,1: Indicates that a break signal has been received"
rbitfld.word 0x00 3. "FER,Framing Error Indicates that a framing error has been found in the data that is to be read next from HSFRDR" "0: Indicates that there is no framing error in the,1: Indicates that there is a framing error in the"
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rbitfld.word 0x00 2. "PER,Parity Error This bit indicates that a parity error has been found in the data that is to be read next from HSFRDR" "0: Indicates that there is no parity error in the,1: Indicates that there is a parity error in the"
bitfld.word 0x00 1. "RDF,Receive FIFO Data Full Indicates that the received data has been transferred from HSRSR to HSFRDR and the number of receive data bytes in HSFRDR becomes equal to or more than the receive trigger count specified by the HSRTRGR" "0: Indicates that the number of receive data bytes,1: Indicates that the number of receive data bytes"
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bitfld.word 0x00 0. "DR,Receive Data Ready Indicates that the receive FIFO data register (HSFRDR) contains fewer bytes than the trigger number for reception and no further data have arrived over at least the time corresponding to the setting of HSSCR[15:14]* since the stop.." "0: Indicates that data is being received or has,1: Indicates that no further receive data has been"
group.byte 0x14++0x00
line.byte 0x00 "HSFRDR0,"
hexmask.byte 0x00 0.--7. 1. "Reserved_0,HSFRDR is a 128-stage FIFO register that stores received serial data"
group.word 0x18++0x01
line.word 0x00 "HSFCR0,HSFCR is a register that resets data counts for transmit and receive FIFO registers"
hexmask.word 0x00 4.--15. 1. "Reserved_4,Reserved These bits are always read as 0"
bitfld.word 0x00 3. "MCE,Modem Control Enable Enables or disables modem control signals HCTS# and HRTS#" "0: Disables modem signals.*,1: Enables modem signals"
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bitfld.word 0x00 2. "TFRST,Transmit FIFO Data Register Reset Enables or disables a transmit FIFO data register reset that empties the register" "0: Disables the reset.*,1: Enables the reset"
bitfld.word 0x00 1. "RFRST,Receive FIFO Data Register Reset Enables or disables a receive FIFO data register (HSFRDR) reset that empties the register" "0: Disables the reset.*,1: Enables the reset"
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bitfld.word 0x00 0. "LOOP,Loopback Test Enables or disables the loopback test by internally connecting the transmit output pin (HTX) and receive input pin (HRX) and the HRTS# pin and HCTS# pin" "0: Disables the loopback test,1: Enables the loopback test"
group.word 0x1C++0x01
line.word 0x00 "HSFDR0,HSFDR is a 16-bit register that indicates the number of data bytes stored in HSFTDR and that in HSFRDR"
hexmask.word.byte 0x00 8.--15. 1. "T_7_0,These bits indicate the number of data bytes un-transmitted and still stored in HSFTDR"
hexmask.word.byte 0x00 0.--7. 1. "R_7_0,These bits indicate the number of receive data stored in HSFRDR"
group.word 0x20++0x01
line.word 0x00 "HSSPTR0,HSSPTR controls multiplexed input/output and data on the high speed serial communication interface (HSCIF) ports"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 7. "RTSIO,Serial Port  RTS Port Input/output Specifies input or output for the serial port HRTS# pin" "0: Indicates that this bit does not output the,1: Indicates that this bit outputs the value of.."
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bitfld.word 0x00 6. "RTSDT,Serial Port  RTS Port Data Specifies the input/output data level of the serial port HRTS# pin" "0: Indicates that the input/output data is low..,1: Indicates that the input/output data is high.."
bitfld.word 0x00 5. "CTSIO,Serial Port  CTS Port Input/output Specifies input or output for the serial port HCTS# pin" "0: Indicates that the CTSDT bit value is not..,1: Indicates that the CTSDT bit value is output to"
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bitfld.word 0x00 4. "CTSDT,Serial Port  CTS Port Data Specifies the input/output data level of the serial port HCTS# pin" "0: Indicates that the input/output data is low..,1: Indicates that the input/output data is high.."
rbitfld.word 0x00 3. "SCKIO,Serial Port  Clock Port Input" "0,1"
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rbitfld.word 0x00 2. "SCKDT,Serial Port  Clock Port Data The initial value of this bit is undefined after a power-on reset" "0,1"
bitfld.word 0x00 1. "SPB2IO,Serial Port  Break Input/output Specifies the output condition of the serial port HTX pin" "0: Indicates that the SPB2DT bit value is not,1: Indicates that the SPB2DT bit value is output.."
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bitfld.word 0x00 0. "SPB2DT,Serial Port  Break Data Specifies the input level of the serial port HRX pin and the output level of the HTX pin" "0: Indicates that the input/output data is low..,1: Indicates that the input/output data is high.."
group.word 0x24++0x01
line.word 0x00 "HSLSR0,"
hexmask.word 0x00 3.--15. 1. "Reserved_3,Reserved These bits are always read as 0"
bitfld.word 0x00 2. "TO,Timeout Indicates that the receive FIFO data register (HSFRDR) contains fewer bytes than the trigger number for reception and no further data have arrived over at least the time corresponding to the setting of HSSCR[15:14]* since the stop bit for .." "0: Indicates that data is being received or has,1: Indicates that no further receive data has been"
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rbitfld.word 0x00 1. "Reserved_1,Reserved This bit is always read as 0" "0,1"
bitfld.word 0x00 0. "ORER,Overrun Error Indicates that an overrun error has occurred in reception and abnormal termination is caused" "0: Indicates that data is being received or has,1: Indicates that an overrun error has occurred in"
group.word 0x40++0x01
line.word 0x00 "HSSRR0,"
bitfld.word 0x00 15. "SRE,Sampling Rate Register Enable (SRE)" "0: Set the SRCYC [4: 0] bits to 15 (initial value),1: Validates the setting of the SRCYC [4:0] bits"
bitfld.word 0x00 14. "SRDE,Sampling Point Register Enable (SRDE)" "0: Invalidates the setting of the SRHP [3:0] bits,1: Validates the setting of the SRHP [3: 0] bits"
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rbitfld.word 0x00 12.--13. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3"
bitfld.word 0x00 8.--11. "SRHP_3_0,Sampling Point Register (SRHP) The sampling point can be moved by setting the SDRE bit to 1 and setting a value in these bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.word 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.word 0x00 0.--4. "SRCYC_4_0,Bits 4 to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x44++0x01
line.word 0x00 "HSRER0,"
rbitfld.word 0x00 15. "Reserved_15,Reserved This bit is always read as 0" "0,1"
hexmask.word.byte 0x00 8.--14. 1. "PER_6_0,Parity Error Count These bits indicate the number of data items in which a parity error occurred in the receive data stored in the receive FIFO data register (HSFRDR)"
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rbitfld.word 0x00 7. "Reserved_7,Reserved This bit is always read as 0" "0,1"
hexmask.word.byte 0x00 0.--6. 1. "FER_6_0,Framing Error Count These bits indicate the number of data items in which a framing error occurred in the receive data stored in the receive FIFO data register (HSFRDR)"
group.word 0x50++0x01
line.word 0x00 "HSRTGR0,"
hexmask.word 0x00 7.--15. 1. "Reserved_7,Reserved These bits are always read as 0"
hexmask.word.byte 0x00 0.--6. 1. "RSTRG_6_0,RTS Output Active Trigger Count The HRTS# signal goes high when the number of receive data items stored in the receive FIFO data register (HSFRDR) exceeds the value set in these bits"
group.word 0x54++0x01
line.word 0x00 "HSRTRGR0,"
hexmask.word 0x00 7.--15. 1. "Reserved_7,Reserved These bits are always read as 0"
hexmask.word.byte 0x00 0.--6. 1. "RTRG_6_0,Receive FIFO Data Count Trigger These bits set the receive data item count at which the receive data full (RDF) flag in the serial status register (HSFSR) is set"
group.word 0x58++0x01
line.word 0x00 "HSTTRGR0,"
hexmask.word 0x00 7.--15. 1. "Reserved_7,Reserved These bits are always read as 0"
hexmask.word.byte 0x00 0.--6. 1. "TTRG_6_0,Transmit FIFO Data Count Trigger These bits set the un-transmitted data item count at which the transmit FIFO data register empty (TDFE) flag in the serial status register (HSFSR) is set"
tree.end
tree "HSCIF_INST_1"
base ad:0xE6550000
group.word 0x00++0x01
line.word 0x00 "HSSMR1,"
hexmask.word 0x00 7.--15. 1. "Reserved_7,Reserved These bits are always read as 0"
bitfld.word 0x00 6. "CHR,Character Length Selects 7 or 8 bits for data length" "0: 8 bits,1: 7 bits"
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bitfld.word 0x00 5. "PE,Parity Enable Determines whether parity bit is added in transmission or not and parity bit is checked in reception or not" "0: Disables parity bit addition and check,1: Enables parity bit addition and check"
bitfld.word 0x00 4. "O_E_SHARP,Parity Mode Selects either even or odd parity to use in parity addition and check" "0: Even parity,1: Odd parity When even parity is"
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bitfld.word 0x00 3. "STOP,Stop Bit Length Selects 1 bit or 2 bits as the stop bit length" "0: 1 stop bit*1,1: 2 stop bits*2 Notes"
rbitfld.word 0x00 2. "Reserved_2,Reserved This bit is always read as 0" "0,1"
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bitfld.word 0x00 0.--1. "CKS_1_0,Clock Select 1 and 0 These bits select the clock source for the on-chip baud rate generator" "0: Internal clock,1: Internal clock/4,2: Internal clock/16,3: Internal clock/64"
group.byte 0x04++0x00
line.byte 0x00 "HSBRR1,"
hexmask.byte 0x00 0.--7. 1. "Reserved_0,HSBRR is an 8-bit register that sets the serial transmission/reception bit rate in accordance with the baud rate generator operating clock selected by the CKS [1:0] bits in HSSMR"
group.word 0x08++0x01
line.word 0x00 "HSSCR1,HSSCR is a register that enables or disables transmission/reception by the HSCIF enables or disables interrupt requests and selects transmission/reception clock source for the HSCIF"
bitfld.word 0x00 14.--15. "TOT_1_0,Set the time for a data ready (DR) or a timeout (TO) to be set in asynchronous mode" "0: 15 etu*,1: 31 etu,2: 47 etu,3: 63 etu"
rbitfld.word 0x00 12.--13. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.word 0x00 11. "TEIE,Transmit End Interrupt Enable When a transmit-end request is enabled by the TIE bit the TEIE bit selects the source of the transmit end interrupt request from the following: Setting the TDFE flag in HSFSR Setting the TEND flag in HSFSR.." "0: The transmit FIFO data empty (TDFE) interrupt,1: The transmit end (TEND) interrupt request is.."
rbitfld.word 0x00 8.--10. "Reserved_8,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 7. "TIE,Transmit Interrupt Enable Enables or disables a transmit-FIFO-data-empty interrupt (TDFE) request when the TEIE bit in HSSCR is pulled 0 if all of the following conditions are satisfied: Serial transmit data has been transferred from HSFTDR to .." "0: When the TEIE bit is 0 disables,1: When the TEIE bit is 0 enables"
bitfld.word 0x00 6. "RIE,Receive Interrupt Enable Enables or disables a receive-FIFO-data-full interrupt request when the RDF flag in HSFSR is set to 1 a receive-data-ready interrupt request when the DR flag in HSFSR is set to 1 a receive-error interrupt request when the .." "0: Disables receive-FIFO-data-full interrupts..,1: Enables receive-FIFO-data-full interrupt (RDF)"
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bitfld.word 0x00 5. "TE,Transmit Enable Enables or disables the start of HSCIF serial transmission" "0: Disables transmission,1: Enables transmission"
bitfld.word 0x00 4. "RE,Receive Enable Enables or disables the start of HSCIF serial reception" "0: Disables reception.*,1: Enables reception"
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bitfld.word 0x00 3. "REIE,Receive Error Interrupt Enable Enables or Disables generation of receive-error interrupt (ER) requests break interrupt (BRK) requests and overrun-error interrupt (ORER) requests" "0: Disables receive-error interrupt (ER) requests,1: Enables receive-error interrupt (ER) requests"
bitfld.word 0x00 2. "TOIE,Timeout Interrupt Enable Enables or disables generation of timeout interrupt (TO) requests when the TO flag in HSLSR is set to 1" "0: Disables timeout interrupts (TO),1: Enables timeout interrupts (TO)"
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bitfld.word 0x00 0.--1. "CKE_1_0,Clock Enable 1 and" "0,1,2,3"
group.byte 0x0C++0x00
line.byte 0x00 "HSFTDR1,"
hexmask.byte 0x00 0.--7. 1. "Reserved_0,HSFTDR is an 8-bit FIFO register of 128 stages that stores data for serial transmission"
group.word 0x10++0x01
line.word 0x00 "HSFSR1,HSFSR is a 16-bit register"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 7. "ER,Receive Error Indicates that a framing error or a parity error has occurred in reception" "0: Indicates that no framing or parity error has,1: Indicates that a framing error or a parity.."
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bitfld.word 0x00 6. "TEND,Transmit End Indicates that transmission has been ended because there was no valid data in HSFTDR when the last bit of the transmit character was transmitted" "0: Indicates that transmission is in progress,1: Indicates that transmission has been ended"
bitfld.word 0x00 5. "TDFE,Transmit FIFO Data Empty Indicates that the HSCIF has transferred data from HSFTDR to HSTSR the number of data bytes in HSFTDR becomes equal to or less than the transmit trigger count specified by the HSTTRGR and HSFTDR is ready to be written by.." "0: Indicates that the number of transmit data,1: Indicates that the number of transmit data in"
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bitfld.word 0x00 4. "BRK,Break Detect Indicates that a receive data break signal has been detected" "0: Indicates that no break signal has been..,1: Indicates that a break signal has been received"
rbitfld.word 0x00 3. "FER,Framing Error Indicates that a framing error has been found in the data that is to be read next from HSFRDR" "0: Indicates that there is no framing error in the,1: Indicates that there is a framing error in the"
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rbitfld.word 0x00 2. "PER,Parity Error This bit indicates that a parity error has been found in the data that is to be read next from HSFRDR" "0: Indicates that there is no parity error in the,1: Indicates that there is a parity error in the"
bitfld.word 0x00 1. "RDF,Receive FIFO Data Full Indicates that the received data has been transferred from HSRSR to HSFRDR and the number of receive data bytes in HSFRDR becomes equal to or more than the receive trigger count specified by the HSRTRGR" "0: Indicates that the number of receive data bytes,1: Indicates that the number of receive data bytes"
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bitfld.word 0x00 0. "DR,Receive Data Ready Indicates that the receive FIFO data register (HSFRDR) contains fewer bytes than the trigger number for reception and no further data have arrived over at least the time corresponding to the setting of HSSCR[15:14]* since the stop.." "0: Indicates that data is being received or has,1: Indicates that no further receive data has been"
group.byte 0x14++0x00
line.byte 0x00 "HSFRDR1,"
hexmask.byte 0x00 0.--7. 1. "Reserved_0,HSFRDR is a 128-stage FIFO register that stores received serial data"
group.word 0x18++0x01
line.word 0x00 "HSFCR1,HSFCR is a register that resets data counts for transmit and receive FIFO registers"
hexmask.word 0x00 4.--15. 1. "Reserved_4,Reserved These bits are always read as 0"
bitfld.word 0x00 3. "MCE,Modem Control Enable Enables or disables modem control signals HCTS# and HRTS#" "0: Disables modem signals.*,1: Enables modem signals"
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bitfld.word 0x00 2. "TFRST,Transmit FIFO Data Register Reset Enables or disables a transmit FIFO data register reset that empties the register" "0: Disables the reset.*,1: Enables the reset"
bitfld.word 0x00 1. "RFRST,Receive FIFO Data Register Reset Enables or disables a receive FIFO data register (HSFRDR) reset that empties the register" "0: Disables the reset.*,1: Enables the reset"
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bitfld.word 0x00 0. "LOOP,Loopback Test Enables or disables the loopback test by internally connecting the transmit output pin (HTX) and receive input pin (HRX) and the HRTS# pin and HCTS# pin" "0: Disables the loopback test,1: Enables the loopback test"
group.word 0x1C++0x01
line.word 0x00 "HSFDR1,HSFDR is a 16-bit register that indicates the number of data bytes stored in HSFTDR and that in HSFRDR"
hexmask.word.byte 0x00 8.--15. 1. "T_7_0,These bits indicate the number of data bytes un-transmitted and still stored in HSFTDR"
hexmask.word.byte 0x00 0.--7. 1. "R_7_0,These bits indicate the number of receive data stored in HSFRDR"
group.word 0x20++0x01
line.word 0x00 "HSSPTR1,HSSPTR controls multiplexed input/output and data on the high speed serial communication interface (HSCIF) ports"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 7. "RTSIO,Serial Port  RTS Port Input/output Specifies input or output for the serial port HRTS# pin" "0: Indicates that this bit does not output the,1: Indicates that this bit outputs the value of.."
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bitfld.word 0x00 6. "RTSDT,Serial Port  RTS Port Data Specifies the input/output data level of the serial port HRTS# pin" "0: Indicates that the input/output data is low..,1: Indicates that the input/output data is high.."
bitfld.word 0x00 5. "CTSIO,Serial Port  CTS Port Input/output Specifies input or output for the serial port HCTS# pin" "0: Indicates that the CTSDT bit value is not..,1: Indicates that the CTSDT bit value is output to"
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bitfld.word 0x00 4. "CTSDT,Serial Port  CTS Port Data Specifies the input/output data level of the serial port HCTS# pin" "0: Indicates that the input/output data is low..,1: Indicates that the input/output data is high.."
rbitfld.word 0x00 3. "SCKIO,Serial Port  Clock Port Input" "0,1"
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rbitfld.word 0x00 2. "SCKDT,Serial Port  Clock Port Data The initial value of this bit is undefined after a power-on reset" "0,1"
bitfld.word 0x00 1. "SPB2IO,Serial Port  Break Input/output Specifies the output condition of the serial port HTX pin" "0: Indicates that the SPB2DT bit value is not,1: Indicates that the SPB2DT bit value is output.."
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bitfld.word 0x00 0. "SPB2DT,Serial Port  Break Data Specifies the input level of the serial port HRX pin and the output level of the HTX pin" "0: Indicates that the input/output data is low..,1: Indicates that the input/output data is high.."
group.word 0x24++0x01
line.word 0x00 "HSLSR1,"
hexmask.word 0x00 3.--15. 1. "Reserved_3,Reserved These bits are always read as 0"
bitfld.word 0x00 2. "TO,Timeout Indicates that the receive FIFO data register (HSFRDR) contains fewer bytes than the trigger number for reception and no further data have arrived over at least the time corresponding to the setting of HSSCR[15:14]* since the stop bit for .." "0: Indicates that data is being received or has,1: Indicates that no further receive data has been"
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rbitfld.word 0x00 1. "Reserved_1,Reserved This bit is always read as 0" "0,1"
bitfld.word 0x00 0. "ORER,Overrun Error Indicates that an overrun error has occurred in reception and abnormal termination is caused" "0: Indicates that data is being received or has,1: Indicates that an overrun error has occurred in"
group.word 0x40++0x01
line.word 0x00 "HSSRR1,"
bitfld.word 0x00 15. "SRE,Sampling Rate Register Enable (SRE)" "0: Set the SRCYC [4: 0] bits to 15 (initial value),1: Validates the setting of the SRCYC [4:0] bits"
bitfld.word 0x00 14. "SRDE,Sampling Point Register Enable (SRDE)" "0: Invalidates the setting of the SRHP [3:0] bits,1: Validates the setting of the SRHP [3: 0] bits"
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rbitfld.word 0x00 12.--13. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3"
bitfld.word 0x00 8.--11. "SRHP_3_0,Sampling Point Register (SRHP) The sampling point can be moved by setting the SDRE bit to 1 and setting a value in these bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.word 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.word 0x00 0.--4. "SRCYC_4_0,Bits 4 to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x44++0x01
line.word 0x00 "HSRER1,"
rbitfld.word 0x00 15. "Reserved_15,Reserved This bit is always read as 0" "0,1"
hexmask.word.byte 0x00 8.--14. 1. "PER_6_0,Parity Error Count These bits indicate the number of data items in which a parity error occurred in the receive data stored in the receive FIFO data register (HSFRDR)"
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rbitfld.word 0x00 7. "Reserved_7,Reserved This bit is always read as 0" "0,1"
hexmask.word.byte 0x00 0.--6. 1. "FER_6_0,Framing Error Count These bits indicate the number of data items in which a framing error occurred in the receive data stored in the receive FIFO data register (HSFRDR)"
group.word 0x50++0x01
line.word 0x00 "HSRTGR1,"
hexmask.word 0x00 7.--15. 1. "Reserved_7,Reserved These bits are always read as 0"
hexmask.word.byte 0x00 0.--6. 1. "RSTRG_6_0,RTS Output Active Trigger Count The HRTS# signal goes high when the number of receive data items stored in the receive FIFO data register (HSFRDR) exceeds the value set in these bits"
group.word 0x54++0x01
line.word 0x00 "HSRTRGR1,"
hexmask.word 0x00 7.--15. 1. "Reserved_7,Reserved These bits are always read as 0"
hexmask.word.byte 0x00 0.--6. 1. "RTRG_6_0,Receive FIFO Data Count Trigger These bits set the receive data item count at which the receive data full (RDF) flag in the serial status register (HSFSR) is set"
group.word 0x58++0x01
line.word 0x00 "HSTTRGR1,"
hexmask.word 0x00 7.--15. 1. "Reserved_7,Reserved These bits are always read as 0"
hexmask.word.byte 0x00 0.--6. 1. "TTRG_6_0,Transmit FIFO Data Count Trigger These bits set the un-transmitted data item count at which the transmit FIFO data register empty (TDFE) flag in the serial status register (HSFSR) is set"
tree.end
tree "HSCIF_INST_2"
base ad:0xE6560000
group.word 0x00++0x01
line.word 0x00 "HSSMR2,"
hexmask.word 0x00 7.--15. 1. "Reserved_7,Reserved These bits are always read as 0"
bitfld.word 0x00 6. "CHR,Character Length Selects 7 or 8 bits for data length" "0: 8 bits,1: 7 bits"
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bitfld.word 0x00 5. "PE,Parity Enable Determines whether parity bit is added in transmission or not and parity bit is checked in reception or not" "0: Disables parity bit addition and check,1: Enables parity bit addition and check"
bitfld.word 0x00 4. "O_E_SHARP,Parity Mode Selects either even or odd parity to use in parity addition and check" "0: Even parity,1: Odd parity When even parity is"
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bitfld.word 0x00 3. "STOP,Stop Bit Length Selects 1 bit or 2 bits as the stop bit length" "0: 1 stop bit*1,1: 2 stop bits*2 Notes"
rbitfld.word 0x00 2. "Reserved_2,Reserved This bit is always read as 0" "0,1"
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bitfld.word 0x00 0.--1. "CKS_1_0,Clock Select 1 and 0 These bits select the clock source for the on-chip baud rate generator" "0: Internal clock,1: Internal clock/4,2: Internal clock/16,3: Internal clock/64"
group.byte 0x04++0x00
line.byte 0x00 "HSBRR2,"
hexmask.byte 0x00 0.--7. 1. "Reserved_0,HSBRR is an 8-bit register that sets the serial transmission/reception bit rate in accordance with the baud rate generator operating clock selected by the CKS [1:0] bits in HSSMR"
group.word 0x08++0x01
line.word 0x00 "HSSCR2,HSSCR is a register that enables or disables transmission/reception by the HSCIF enables or disables interrupt requests and selects transmission/reception clock source for the HSCIF"
bitfld.word 0x00 14.--15. "TOT_1_0,Set the time for a data ready (DR) or a timeout (TO) to be set in asynchronous mode" "0: 15 etu*,1: 31 etu,2: 47 etu,3: 63 etu"
rbitfld.word 0x00 12.--13. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.word 0x00 11. "TEIE,Transmit End Interrupt Enable When a transmit-end request is enabled by the TIE bit the TEIE bit selects the source of the transmit end interrupt request from the following: Setting the TDFE flag in HSFSR Setting the TEND flag in HSFSR.." "0: The transmit FIFO data empty (TDFE) interrupt,1: The transmit end (TEND) interrupt request is.."
rbitfld.word 0x00 8.--10. "Reserved_8,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 7. "TIE,Transmit Interrupt Enable Enables or disables a transmit-FIFO-data-empty interrupt (TDFE) request when the TEIE bit in HSSCR is pulled 0 if all of the following conditions are satisfied: Serial transmit data has been transferred from HSFTDR to.." "0: When the TEIE bit is 0 disables,1: When the TEIE bit is 0 enables"
bitfld.word 0x00 6. "RIE,Receive Interrupt Enable Enables or disables a receive-FIFO-data-full interrupt request when the RDF flag in HSFSR is set to 1 a receive-data-ready interrupt request when the DR flag in HSFSR is set to 1 a receive-error interrupt request when the.." "0: Disables receive-FIFO-data-full interrupts..,1: Enables receive-FIFO-data-full interrupt (RDF)"
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bitfld.word 0x00 5. "TE,Transmit Enable Enables or disables the start of HSCIF serial transmission" "0: Disables transmission,1: Enables transmission"
bitfld.word 0x00 4. "RE,Receive Enable Enables or disables the start of HSCIF serial reception" "0: Disables reception.*,1: Enables reception"
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bitfld.word 0x00 3. "REIE,Receive Error Interrupt Enable Enables or Disables generation of receive-error interrupt (ER) requests break interrupt (BRK) requests and overrun-error interrupt (ORER) requests" "0: Disables receive-error interrupt (ER) requests,1: Enables receive-error interrupt (ER) requests"
bitfld.word 0x00 2. "TOIE,Timeout Interrupt Enable Enables or disables generation of timeout interrupt (TO) requests when the TO flag in HSLSR is set to 1" "0: Disables timeout interrupts (TO),1: Enables timeout interrupts (TO)"
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bitfld.word 0x00 0.--1. "CKE_1_0,Clock Enable 1 and" "0,1,2,3"
group.byte 0x0C++0x00
line.byte 0x00 "HSFTDR2,"
hexmask.byte 0x00 0.--7. 1. "Reserved_0,HSFTDR is an 8-bit FIFO register of 128 stages that stores data for serial transmission"
group.word 0x10++0x01
line.word 0x00 "HSFSR2,HSFSR is a 16-bit register"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 7. "ER,Receive Error Indicates that a framing error or a parity error has occurred in reception" "0: Indicates that no framing or parity error has,1: Indicates that a framing error or a parity.."
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bitfld.word 0x00 6. "TEND,Transmit End Indicates that transmission has been ended because there was no valid data in HSFTDR when the last bit of the transmit character was transmitted" "0: Indicates that transmission is in progress,1: Indicates that transmission has been ended"
bitfld.word 0x00 5. "TDFE,Transmit FIFO Data Empty Indicates that the HSCIF has transferred data from HSFTDR to HSTSR the number of data bytes in HSFTDR becomes equal to or less than the transmit trigger count specified by the HSTTRGR and HSFTDR is ready to be written by.." "0: Indicates that the number of transmit data,1: Indicates that the number of transmit data in"
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bitfld.word 0x00 4. "BRK,Break Detect Indicates that a receive data break signal has been detected" "0: Indicates that no break signal has been..,1: Indicates that a break signal has been received"
rbitfld.word 0x00 3. "FER,Framing Error Indicates that a framing error has been found in the data that is to be read next from HSFRDR" "0: Indicates that there is no framing error in the,1: Indicates that there is a framing error in the"
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rbitfld.word 0x00 2. "PER,Parity Error This bit indicates that a parity error has been found in the data that is to be read next from HSFRDR" "0: Indicates that there is no parity error in the,1: Indicates that there is a parity error in the"
bitfld.word 0x00 1. "RDF,Receive FIFO Data Full Indicates that the received data has been transferred from HSRSR to HSFRDR and the number of receive data bytes in HSFRDR becomes equal to or more than the receive trigger count specified by the HSRTRGR" "0: Indicates that the number of receive data bytes,1: Indicates that the number of receive data bytes"
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bitfld.word 0x00 0. "DR,Receive Data Ready Indicates that the receive FIFO data register (HSFRDR) contains fewer bytes than the trigger number for reception and no further data have arrived over at least the time corresponding to the setting of HSSCR[15:14]* since the stop.." "0: Indicates that data is being received or has,1: Indicates that no further receive data has been"
group.byte 0x14++0x00
line.byte 0x00 "HSFRDR2,"
hexmask.byte 0x00 0.--7. 1. "Reserved_0,HSFRDR is a 128-stage FIFO register that stores received serial data"
group.word 0x18++0x01
line.word 0x00 "HSFCR2,HSFCR is a register that resets data counts for transmit and receive FIFO registers"
hexmask.word 0x00 4.--15. 1. "Reserved_4,Reserved These bits are always read as 0"
bitfld.word 0x00 3. "MCE,Modem Control Enable Enables or disables modem control signals HCTS# and HRTS#" "0: Disables modem signals.*,1: Enables modem signals"
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bitfld.word 0x00 2. "TFRST,Transmit FIFO Data Register Reset Enables or disables a transmit FIFO data register reset that empties the register" "0: Disables the reset.*,1: Enables the reset"
bitfld.word 0x00 1. "RFRST,Receive FIFO Data Register Reset Enables or disables a receive FIFO data register (HSFRDR) reset that empties the register" "0: Disables the reset.*,1: Enables the reset"
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bitfld.word 0x00 0. "LOOP,Loopback Test Enables or disables the loopback test by internally connecting the transmit output pin (HTX) and receive input pin (HRX) and the HRTS# pin and HCTS# pin" "0: Disables the loopback test,1: Enables the loopback test"
group.word 0x1C++0x01
line.word 0x00 "HSFDR2,HSFDR is a 16-bit register that indicates the number of data bytes stored in HSFTDR and that in HSFRDR"
hexmask.word.byte 0x00 8.--15. 1. "T_7_0,These bits indicate the number of data bytes un-transmitted and still stored in HSFTDR"
hexmask.word.byte 0x00 0.--7. 1. "R_7_0,These bits indicate the number of receive data stored in HSFRDR"
group.word 0x20++0x01
line.word 0x00 "HSSPTR2,HSSPTR controls multiplexed input/output and data on the high speed serial communication interface (HSCIF) ports"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 7. "RTSIO,Serial Port  RTS Port Input/output Specifies input or output for the serial port HRTS# pin" "0: Indicates that this bit does not output the,1: Indicates that this bit outputs the value of.."
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bitfld.word 0x00 6. "RTSDT,Serial Port  RTS Port Data Specifies the input/output data level of the serial port HRTS# pin" "0: Indicates that the input/output data is low..,1: Indicates that the input/output data is high.."
bitfld.word 0x00 5. "CTSIO,Serial Port  CTS Port Input/output Specifies input or output for the serial port HCTS# pin" "0: Indicates that the CTSDT bit value is not..,1: Indicates that the CTSDT bit value is output to"
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bitfld.word 0x00 4. "CTSDT,Serial Port  CTS Port Data Specifies the input/output data level of the serial port HCTS# pin" "0: Indicates that the input/output data is low..,1: Indicates that the input/output data is high.."
rbitfld.word 0x00 3. "SCKIO,Serial Port  Clock Port Input" "0,1"
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rbitfld.word 0x00 2. "SCKDT,Serial Port  Clock Port Data The initial value of this bit is undefined after a power-on reset" "0,1"
bitfld.word 0x00 1. "SPB2IO,Serial Port  Break Input/output Specifies the output condition of the serial port HTX pin" "0: Indicates that the SPB2DT bit value is not,1: Indicates that the SPB2DT bit value is output.."
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bitfld.word 0x00 0. "SPB2DT,Serial Port  Break Data Specifies the input level of the serial port HRX pin and the output level of the HTX pin" "0: Indicates that the input/output data is low..,1: Indicates that the input/output data is high.."
group.word 0x24++0x01
line.word 0x00 "HSLSR2,"
hexmask.word 0x00 3.--15. 1. "Reserved_3,Reserved These bits are always read as 0"
bitfld.word 0x00 2. "TO,Timeout Indicates that the receive FIFO data register (HSFRDR) contains fewer bytes than the trigger number for reception and no further data have arrived over at least the time corresponding to the setting of HSSCR[15:14]* since the stop bit for.." "0: Indicates that data is being received or has,1: Indicates that no further receive data has been"
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rbitfld.word 0x00 1. "Reserved_1,Reserved This bit is always read as 0" "0,1"
bitfld.word 0x00 0. "ORER,Overrun Error Indicates that an overrun error has occurred in reception and abnormal termination is caused" "0: Indicates that data is being received or has,1: Indicates that an overrun error has occurred in"
group.word 0x40++0x01
line.word 0x00 "HSSRR2,"
bitfld.word 0x00 15. "SRE,Sampling Rate Register Enable (SRE)" "0: Set the SRCYC [4: 0] bits to 15 (initial value),1: Validates the setting of the SRCYC [4:0] bits"
bitfld.word 0x00 14. "SRDE,Sampling Point Register Enable (SRDE)" "0: Invalidates the setting of the SRHP [3:0] bits,1: Validates the setting of the SRHP [3: 0] bits"
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rbitfld.word 0x00 12.--13. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3"
bitfld.word 0x00 8.--11. "SRHP_3_0,Sampling Point Register (SRHP) The sampling point can be moved by setting the SDRE bit to 1 and setting a value in these bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.word 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.word 0x00 0.--4. "SRCYC_4_0,Bits 4 to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x44++0x01
line.word 0x00 "HSRER2,"
rbitfld.word 0x00 15. "Reserved_15,Reserved This bit is always read as 0" "0,1"
hexmask.word.byte 0x00 8.--14. 1. "PER_6_0,Parity Error Count These bits indicate the number of data items in which a parity error occurred in the receive data stored in the receive FIFO data register (HSFRDR)"
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rbitfld.word 0x00 7. "Reserved_7,Reserved This bit is always read as 0" "0,1"
hexmask.word.byte 0x00 0.--6. 1. "FER_6_0,Framing Error Count These bits indicate the number of data items in which a framing error occurred in the receive data stored in the receive FIFO data register (HSFRDR)"
group.word 0x50++0x01
line.word 0x00 "HSRTGR2,"
hexmask.word 0x00 7.--15. 1. "Reserved_7,Reserved These bits are always read as 0"
hexmask.word.byte 0x00 0.--6. 1. "RSTRG_6_0,RTS Output Active Trigger Count The HRTS# signal goes high when the number of receive data items stored in the receive FIFO data register (HSFRDR) exceeds the value set in these bits"
group.word 0x54++0x01
line.word 0x00 "HSRTRGR2,"
hexmask.word 0x00 7.--15. 1. "Reserved_7,Reserved These bits are always read as 0"
hexmask.word.byte 0x00 0.--6. 1. "RTRG_6_0,Receive FIFO Data Count Trigger These bits set the receive data item count at which the receive data full (RDF) flag in the serial status register (HSFSR) is set"
group.word 0x58++0x01
line.word 0x00 "HSTTRGR2,"
hexmask.word 0x00 7.--15. 1. "Reserved_7,Reserved These bits are always read as 0"
hexmask.word.byte 0x00 0.--6. 1. "TTRG_6_0,Transmit FIFO Data Count Trigger These bits set the un-transmitted data item count at which the transmit FIFO data register empty (TDFE) flag in the serial status register (HSFSR) is set"
tree.end
tree "HSCIF_INST_3"
base ad:0xE66A0000
group.word 0x00++0x01
line.word 0x00 "HSSMR3,"
hexmask.word 0x00 7.--15. 1. "Reserved_7,Reserved These bits are always read as 0"
bitfld.word 0x00 6. "CHR,Character Length Selects 7 or 8 bits for data length" "0: 8 bits,1: 7 bits"
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bitfld.word 0x00 5. "PE,Parity Enable Determines whether parity bit is added in transmission or not and parity bit is checked in reception or not" "0: Disables parity bit addition and check,1: Enables parity bit addition and check"
bitfld.word 0x00 4. "O_E_SHARP,Parity Mode Selects either even or odd parity to use in parity addition and check" "0: Even parity,1: Odd parity When even parity is"
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bitfld.word 0x00 3. "STOP,Stop Bit Length Selects 1 bit or 2 bits as the stop bit length" "0: 1 stop bit*1,1: 2 stop bits*2 Notes"
rbitfld.word 0x00 2. "Reserved_2,Reserved This bit is always read as 0" "0,1"
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bitfld.word 0x00 0.--1. "CKS_1_0,Clock Select 1 and 0 These bits select the clock source for the on-chip baud rate generator" "0: Internal clock,1: Internal clock/4,2: Internal clock/16,3: Internal clock/64"
group.byte 0x04++0x00
line.byte 0x00 "HSBRR3,"
hexmask.byte 0x00 0.--7. 1. "Reserved_0,HSBRR is an 8-bit register that sets the serial transmission/reception bit rate in accordance with the baud rate generator operating clock selected by the CKS [1:0] bits in HSSMR"
group.word 0x08++0x01
line.word 0x00 "HSSCR3,HSSCR is a register that enables or disables transmission/reception by the HSCIF enables or disables interrupt requests and selects transmission/reception clock source for the HSCIF"
bitfld.word 0x00 14.--15. "TOT_1_0,Set the time for a data ready (DR) or a timeout (TO) to be set in asynchronous mode" "0: 15 etu*,1: 31 etu,2: 47 etu,3: 63 etu"
rbitfld.word 0x00 12.--13. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.word 0x00 11. "TEIE,Transmit End Interrupt Enable When a transmit-end request is enabled by the TIE bit the TEIE bit selects the source of the transmit end interrupt request from the following: Setting the TDFE flag in HSFSR Setting the TEND flag in HSFSR.." "0: The transmit FIFO data empty (TDFE) interrupt,1: The transmit end (TEND) interrupt request is.."
rbitfld.word 0x00 8.--10. "Reserved_8,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 7. "TIE,Transmit Interrupt Enable Enables or disables a transmit-FIFO-data-empty interrupt (TDFE) request when the TEIE bit in HSSCR is pulled 0 if all of the following conditions are satisfied: Serial transmit data has been transferred from HSFTDR to .." "0: When the TEIE bit is 0 disables,1: When the TEIE bit is 0 enables"
bitfld.word 0x00 6. "RIE,Receive Interrupt Enable Enables or disables a receive-FIFO-data-full interrupt request when the RDF flag in HSFSR is set to 1 a receive-data-ready interrupt request when the DR flag in HSFSR is set to 1 a receive-error interrupt request when the .." "0: Disables receive-FIFO-data-full interrupts..,1: Enables receive-FIFO-data-full interrupt (RDF)"
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bitfld.word 0x00 5. "TE,Transmit Enable Enables or disables the start of HSCIF serial transmission" "0: Disables transmission,1: Enables transmission"
bitfld.word 0x00 4. "RE,Receive Enable Enables or disables the start of HSCIF serial reception" "0: Disables reception.*,1: Enables reception"
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bitfld.word 0x00 3. "REIE,Receive Error Interrupt Enable Enables or Disables generation of receive-error interrupt (ER) requests break interrupt (BRK) requests and overrun-error interrupt (ORER) requests" "0: Disables receive-error interrupt (ER) requests,1: Enables receive-error interrupt (ER) requests"
bitfld.word 0x00 2. "TOIE,Timeout Interrupt Enable Enables or disables generation of timeout interrupt (TO) requests when the TO flag in HSLSR is set to 1" "0: Disables timeout interrupts (TO),1: Enables timeout interrupts (TO)"
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bitfld.word 0x00 0.--1. "CKE_1_0,Clock Enable 1 and" "0,1,2,3"
group.byte 0x0C++0x00
line.byte 0x00 "HSFTDR3,"
hexmask.byte 0x00 0.--7. 1. "Reserved_0,HSFTDR is an 8-bit FIFO register of 128 stages that stores data for serial transmission"
group.word 0x10++0x01
line.word 0x00 "HSFSR3,HSFSR is a 16-bit register"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 7. "ER,Receive Error Indicates that a framing error or a parity error has occurred in reception" "0: Indicates that no framing or parity error has,1: Indicates that a framing error or a parity.."
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bitfld.word 0x00 6. "TEND,Transmit End Indicates that transmission has been ended because there was no valid data in HSFTDR when the last bit of the transmit character was transmitted" "0: Indicates that transmission is in progress,1: Indicates that transmission has been ended"
bitfld.word 0x00 5. "TDFE,Transmit FIFO Data Empty Indicates that the HSCIF has transferred data from HSFTDR to HSTSR the number of data bytes in HSFTDR becomes equal to or less than the transmit trigger count specified by the HSTTRGR and HSFTDR is ready to be written by.." "0: Indicates that the number of transmit data,1: Indicates that the number of transmit data in"
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bitfld.word 0x00 4. "BRK,Break Detect Indicates that a receive data break signal has been detected" "0: Indicates that no break signal has been..,1: Indicates that a break signal has been received"
rbitfld.word 0x00 3. "FER,Framing Error Indicates that a framing error has been found in the data that is to be read next from HSFRDR" "0: Indicates that there is no framing error in the,1: Indicates that there is a framing error in the"
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rbitfld.word 0x00 2. "PER,Parity Error This bit indicates that a parity error has been found in the data that is to be read next from HSFRDR" "0: Indicates that there is no parity error in the,1: Indicates that there is a parity error in the"
bitfld.word 0x00 1. "RDF,Receive FIFO Data Full Indicates that the received data has been transferred from HSRSR to HSFRDR and the number of receive data bytes in HSFRDR becomes equal to or more than the receive trigger count specified by the HSRTRGR" "0: Indicates that the number of receive data bytes,1: Indicates that the number of receive data bytes"
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bitfld.word 0x00 0. "DR,Receive Data Ready Indicates that the receive FIFO data register (HSFRDR) contains fewer bytes than the trigger number for reception and no further data have arrived over at least the time corresponding to the setting of HSSCR[15:14]* since the stop.." "0: Indicates that data is being received or has,1: Indicates that no further receive data has been"
group.byte 0x14++0x00
line.byte 0x00 "HSFRDR3,"
hexmask.byte 0x00 0.--7. 1. "Reserved_0,HSFRDR is a 128-stage FIFO register that stores received serial data"
group.word 0x18++0x01
line.word 0x00 "HSFCR3,HSFCR is a register that resets data counts for transmit and receive FIFO registers"
hexmask.word 0x00 4.--15. 1. "Reserved_4,Reserved These bits are always read as 0"
bitfld.word 0x00 3. "MCE,Modem Control Enable Enables or disables modem control signals HCTS# and HRTS#" "0: Disables modem signals.*,1: Enables modem signals"
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bitfld.word 0x00 2. "TFRST,Transmit FIFO Data Register Reset Enables or disables a transmit FIFO data register reset that empties the register" "0: Disables the reset.*,1: Enables the reset"
bitfld.word 0x00 1. "RFRST,Receive FIFO Data Register Reset Enables or disables a receive FIFO data register (HSFRDR) reset that empties the register" "0: Disables the reset.*,1: Enables the reset"
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bitfld.word 0x00 0. "LOOP,Loopback Test Enables or disables the loopback test by internally connecting the transmit output pin (HTX) and receive input pin (HRX) and the HRTS# pin and HCTS# pin" "0: Disables the loopback test,1: Enables the loopback test"
group.word 0x1C++0x01
line.word 0x00 "HSFDR3,HSFDR is a 16-bit register that indicates the number of data bytes stored in HSFTDR and that in HSFRDR"
hexmask.word.byte 0x00 8.--15. 1. "T_7_0,These bits indicate the number of data bytes un-transmitted and still stored in HSFTDR"
hexmask.word.byte 0x00 0.--7. 1. "R_7_0,These bits indicate the number of receive data stored in HSFRDR"
group.word 0x20++0x01
line.word 0x00 "HSSPTR3,HSSPTR controls multiplexed input/output and data on the high speed serial communication interface (HSCIF) ports"
hexmask.word.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.word 0x00 7. "RTSIO,Serial Port  RTS Port Input/output Specifies input or output for the serial port HRTS# pin" "0: Indicates that this bit does not output the,1: Indicates that this bit outputs the value of.."
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bitfld.word 0x00 6. "RTSDT,Serial Port  RTS Port Data Specifies the input/output data level of the serial port HRTS# pin" "0: Indicates that the input/output data is low..,1: Indicates that the input/output data is high.."
bitfld.word 0x00 5. "CTSIO,Serial Port  CTS Port Input/output Specifies input or output for the serial port HCTS# pin" "0: Indicates that the CTSDT bit value is not..,1: Indicates that the CTSDT bit value is output to"
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bitfld.word 0x00 4. "CTSDT,Serial Port  CTS Port Data Specifies the input/output data level of the serial port HCTS# pin" "0: Indicates that the input/output data is low..,1: Indicates that the input/output data is high.."
rbitfld.word 0x00 3. "SCKIO,Serial Port  Clock Port Input" "0,1"
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rbitfld.word 0x00 2. "SCKDT,Serial Port  Clock Port Data The initial value of this bit is undefined after a power-on reset" "0,1"
bitfld.word 0x00 1. "SPB2IO,Serial Port  Break Input/output Specifies the output condition of the serial port HTX pin" "0: Indicates that the SPB2DT bit value is not,1: Indicates that the SPB2DT bit value is output.."
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bitfld.word 0x00 0. "SPB2DT,Serial Port  Break Data Specifies the input level of the serial port HRX pin and the output level of the HTX pin" "0: Indicates that the input/output data is low..,1: Indicates that the input/output data is high.."
group.word 0x24++0x01
line.word 0x00 "HSLSR3,"
hexmask.word 0x00 3.--15. 1. "Reserved_3,Reserved These bits are always read as 0"
bitfld.word 0x00 2. "TO,Timeout Indicates that the receive FIFO data register (HSFRDR) contains fewer bytes than the trigger number for reception and no further data have arrived over at least the time corresponding to the setting of HSSCR[15:14]* since the stop bit for .." "0: Indicates that data is being received or has,1: Indicates that no further receive data has been"
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rbitfld.word 0x00 1. "Reserved_1,Reserved This bit is always read as 0" "0,1"
bitfld.word 0x00 0. "ORER,Overrun Error Indicates that an overrun error has occurred in reception and abnormal termination is caused" "0: Indicates that data is being received or has,1: Indicates that an overrun error has occurred in"
group.word 0x40++0x01
line.word 0x00 "HSSRR3,"
bitfld.word 0x00 15. "SRE,Sampling Rate Register Enable (SRE)" "0: Set the SRCYC [4: 0] bits to 15 (initial value),1: Validates the setting of the SRCYC [4:0] bits"
bitfld.word 0x00 14. "SRDE,Sampling Point Register Enable (SRDE)" "0: Invalidates the setting of the SRHP [3:0] bits,1: Validates the setting of the SRHP [3: 0] bits"
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rbitfld.word 0x00 12.--13. "Reserved_12,Reserved These bits are always read as 0" "0,1,2,3"
bitfld.word 0x00 8.--11. "SRHP_3_0,Sampling Point Register (SRHP) The sampling point can be moved by setting the SDRE bit to 1 and setting a value in these bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.word 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.word 0x00 0.--4. "SRCYC_4_0,Bits 4 to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x44++0x01
line.word 0x00 "HSRER3,"
rbitfld.word 0x00 15. "Reserved_15,Reserved This bit is always read as 0" "0,1"
hexmask.word.byte 0x00 8.--14. 1. "PER_6_0,Parity Error Count These bits indicate the number of data items in which a parity error occurred in the receive data stored in the receive FIFO data register (HSFRDR)"
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rbitfld.word 0x00 7. "Reserved_7,Reserved This bit is always read as 0" "0,1"
hexmask.word.byte 0x00 0.--6. 1. "FER_6_0,Framing Error Count These bits indicate the number of data items in which a framing error occurred in the receive data stored in the receive FIFO data register (HSFRDR)"
group.word 0x50++0x01
line.word 0x00 "HSRTGR3,"
hexmask.word 0x00 7.--15. 1. "Reserved_7,Reserved These bits are always read as 0"
hexmask.word.byte 0x00 0.--6. 1. "RSTRG_6_0,RTS Output Active Trigger Count The HRTS# signal goes high when the number of receive data items stored in the receive FIFO data register (HSFRDR) exceeds the value set in these bits"
group.word 0x54++0x01
line.word 0x00 "HSRTRGR3,"
hexmask.word 0x00 7.--15. 1. "Reserved_7,Reserved These bits are always read as 0"
hexmask.word.byte 0x00 0.--6. 1. "RTRG_6_0,Receive FIFO Data Count Trigger These bits set the receive data item count at which the receive data full (RDF) flag in the serial status register (HSFSR) is set"
group.word 0x58++0x01
line.word 0x00 "HSTTRGR3,"
hexmask.word 0x00 7.--15. 1. "Reserved_7,Reserved These bits are always read as 0"
hexmask.word.byte 0x00 0.--6. 1. "TTRG_6_0,Transmit FIFO Data Count Trigger These bits set the un-transmitted data item count at which the transmit FIFO data register empty (TDFE) flag in the serial status register (HSFSR) is set"
tree.end
tree.end
tree "I2C"
tree "I2C_INST_0"
base ad:0xE6500000
group.long 0x00++0x03
line.long 0x00 "ICSCR0,"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved When these bits are read bits 31 to 24 23 to 16 and 15 to 8 reflect the values of bits 7 to 0"
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4. "SCSS,Slave Clock Stretch Select This bit is used to select the timing of Clock Stretch" "0: Clock Stretch is in front of Acknowledgement,1: Clock Stretch is next to Non Acknowledgement"
bitfld.long 0x00 3. "SDBS,Slave Data Buffer Select This bit is used to select the data buffer" "0: Setting prohibited,1: Single-buffer mode"
newline
bitfld.long 0x00 2. "SIE,Slave Interface Enable This bit must be set for the slave operation" "0,1"
bitfld.long 0x00 1. "GCAE,General Call Acknowledgement Enable When slave devices are to issue an acknowledgement in response to a general call address sent from a master this bit must be set to 1" "0,1"
newline
bitfld.long 0x00 0. "FNA,Forced Non Acknowledgement In the slave receive mode the level of this bit is sent to the transmitting device as the acknowledge signal" "0,1"
group.long 0x04++0x03
line.long 0x00 "ICMCR0,"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved When these bits are read bits 31 to 24 23 to 16 and 15 to 8 reflect the values of bits 7 to 0"
bitfld.long 0x00 7. "MDBS,Master Data Buffer Select This bit is used to select the data buffer mode" "0: Setting prohibited,1: Single-buffer mode"
newline
bitfld.long 0x00 6. "FSCL,Forced SCL This bit controls the status of the I2C_SCL pin (reading reflects the current status of the I2C_SCL pin[n])" "0,1"
bitfld.long 0x00 5. "FSDA,Forced SDA This bit controls the status of the I2C_SDA pin (reading reflects the busy status level on the I2C bus[n])" "0,1"
newline
bitfld.long 0x00 4. "OBPC,Override Bus Pin Control When this bit is set to 1 the FSDA and FSCL bits in this register control SDA and SCL directly" "0,1"
bitfld.long 0x00 3. "MIE,Master Interface Enable When this bit is set to 1 the master interface is enabled" "0,1"
newline
bitfld.long 0x00 2. "TSBE,Start Byte Transmission Enable The write value for this bit should always be 0" "0,1"
bitfld.long 0x00 1. "FSB,Forced Stop onto the Bus When this bit is set to 1 the master transmits a STOP condition on the bus at the end of the current transfer" "0,1"
newline
bitfld.long 0x00 0. "ESG,Enable Start Generation When this bit is set to 1 the master starts transmission of a data packet" "0,1"
group.long 0x08++0x03
line.long 0x00 "ICSSR0,Bits 0 to 4 among the status bits in the slave status register are cleared by writing 0 to the respective status bit positions"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved When these bits are read bits 31 to 24 23 to 16 and 15 to 8 reflect the values of bits 7 to 0"
rbitfld.long 0x00 7. "Reserved_7,Reserved The write value should always be 0" "0,1"
newline
rbitfld.long 0x00 6. "GCAR,General Call Address Received Indicates that the address received from the bus is a general call address (H'00[n])" "0,1"
rbitfld.long 0x00 5. "STM,Slave Transmit Mode Indicates whether the current slave transmit mode is read or write" "0,1"
newline
bitfld.long 0x00 4. "SSR,Slave Stop Received A stop condition has been output on the bus" "0,1"
bitfld.long 0x00 3. "SDE,Slave Data Empty Indicates that data to be transmitted has been loaded into the shift register" "0,1"
newline
bitfld.long 0x00 2. "SDT,Slave Data Transmitted A byte of data has been transmitted to the bus" "0,1"
bitfld.long 0x00 1. "SDR,Slave Data Received A byte of data has been received from the bus and is ready for reading from the receive data register" "0,1"
newline
bitfld.long 0x00 0. "SAR,Slave Address Received Indicates that the slave has recognized its own address on the bus (defined by the contents of the slave address register[n])" "0,1"
group.long 0x0C++0x03
line.long 0x00 "ICMSR0,The status bits (bits 0 to 6[n]) in the master status register are cleared by writing 0 to the respective status bit positions"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved When these bits are read bits 31 to 24 23 to 16 and 15 to 8 reflect the values of bits 7 to 0"
rbitfld.long 0x00 7. "Reserved_7,Reserved The write value should always be 0" "0,1"
newline
bitfld.long 0x00 6. "MNR,Master NACK Received When this bit is set to 1 this bit indicates that the master has received a NACK response (the SDA line is high during the acknowledge cycle on the bus[n]) to either an address or data transmission" "0,1"
bitfld.long 0x00 5. "MAL,Master Arbitration Lost In a multi-master system when this bit is set to 1 it indicates that the master has lost arbitration to other masters on the bus" "0,1"
newline
bitfld.long 0x00 4. "MST,Master Stop Transmitted When this bit is set to 1 it indicates that the master has sent a STOP condition on the bus" "0,1"
bitfld.long 0x00 3. "MDE,Master Data Empty At the start of a byte data transmission the contents of the transmit data register are loaded into a shift register ready for transmitting on the bus" "0,1"
newline
bitfld.long 0x00 2. "MDT,Master Data Transmitted Byte data has been sent to the slave on the bus" "0,1"
bitfld.long 0x00 1. "MDR,Master Data Received Byte data has been received from the bus and is in the receive data register" "0,1"
newline
bitfld.long 0x00 0. "MAT,Master Address Transmitted The master has been transmitted the slave address byte of a data packet" "0,1"
group.long 0x10++0x03
line.long 0x00 "ICSIER0,"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved When these bits are read bits 31 to 24 23 to 16 and 15 to 8 reflect the values of bits 7 to 0"
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4. "SSRE,Slave Stop Received Interrupt Enable" "0: Disables the SSR interrupt,1: Enables the SSR interrupt"
bitfld.long 0x00 3. "SDEE,Slave Data Empty Interrupt Enable" "0: Disables the SDE interrupt,1: Enables the SDE interrupt"
newline
bitfld.long 0x00 2. "SDTE,Slave Data Transmitted Interrupt Enable" "0: Disables the SDT interrupt,1: Enables the SDT interrupt"
bitfld.long 0x00 1. "SDRE,Slave Data Received Interrupt Enable" "0: Disables the SDR interrupt,1: Enables the SDR interrupt"
newline
bitfld.long 0x00 0. "SARE,Slave Address Received Interrupt Enable" "0: Disables the SAR interrupt,1: Enables the SAR interrupt"
group.long 0x14++0x03
line.long 0x00 "ICMIER0,"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved When these bits are read bits 31 to 24 23 to 16 and 15 to 8 reflect the values of bits 7 to 0"
rbitfld.long 0x00 7. "Reserved_7,Reserved The write value should always be 0" "0,1"
newline
bitfld.long 0x00 6. "MNRE,Master NACK Received Interrupt Enable" "0: Disables the MNR interrupt,1: Enables the MNR interrupt"
bitfld.long 0x00 5. "MALE,Master Arbitration Lost Interrupt Enable" "0: Disables the MAL interrupt,1: Enables the MAL interrupt"
newline
bitfld.long 0x00 4. "MSTE,Master Stop Transmitted Interrupt Enable" "0: Disables the MST interrupt,1: Enables the MST interrupt"
bitfld.long 0x00 3. "MDEE,Master Data Empty Interrupt Enable" "0: Disables the MDE interrupt,1: Enables the MDE interrupt"
newline
bitfld.long 0x00 2. "MDTE,Master Data Transmitted Interrupt Enable" "0: Disables the MDT interrupt,1: Enables the MDT interrupt"
bitfld.long 0x00 1. "MDRE,Master Data Received Interrupt Enable" "0: Disables the MDR interrupt,1: Enables the MDR interrupt"
newline
bitfld.long 0x00 0. "MATE,Master Address Transmitted Interrupt Enable" "0: Disables the MAT interrupt,1: Enables the MAT interrupt"
group.long 0x18++0x03
line.long 0x00 "ICCCR0,"
hexmask.long.tbyte 0x00 9.--31. 1. "Reserved_9,Reserved The read value is always 0"
bitfld.long 0x00 3.--8. "SCGD,SCL Clock Generation Divider When operation is in master mode the SCL clock is generated from the internal clock by using SCGD as the ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0.--2. "CDF,Clock Division Factor The internal clock used in most blocks in the I2C module is a divided module clock" "0,1,2,3,4,5,6,7"
group.long 0x1C++0x03
line.long 0x00 "ICSAR0,"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved When these bits are read bits 31 to 24 23 to 16 and 15 to 8 reflect the values of bits 7 to 0"
rbitfld.long 0x00 7. "Reserved_7,Reserved The write value should always be 0" "0,1"
newline
hexmask.long.byte 0x00 0.--6. 1. "SADD0_6_0,Slave Address This is the unique 7-bit address allocated to the slave on the I2C bus"
group.long 0x20++0x03
line.long 0x00 "ICMAR0,"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved When these bits are read bits 31 to 24 23 to 16 and 15 to 8 reflect the values of bits 7 to 0"
hexmask.long.byte 0x00 1.--7. 1. "SADD1_6_0,Slave Address These bits are the address of the slave which the master communicates with"
newline
bitfld.long 0x00 0. "STM1,Slave Transfer Mode This bit specifies the mode in which the slave operates" "0,1"
group.long 0x24++0x03
line.long 0x00 "ICRXD_ICTXD0,"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved When these bits are read bits 31 to 24 23 to 16 and 15 to 8 reflect the values of bits 7 to 0"
hexmask.long.byte 0x00 0.--7. 1. "RXD_TXD,Read Receive Data Data received by master or slave"
group.long 0x28++0x03
line.long 0x00 "ICCCR20,Notes: 1"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved When these bits are read the value in bits 7 to 0 is set to bits 31 to 24 bits 23 to 16 and bits 15 to 8"
rbitfld.long 0x00 7. "Reserved_7,Reserved The write value should always be 0" "0,1"
newline
rbitfld.long 0x00 3.--6. "Reserved_3,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 2. "CDFD,CDF Disable When this bit is set to 1 the module clock is used for internal clocks except the clock filter" "0,1"
newline
bitfld.long 0x00 1. "HLSE,HIGH/LOW Separate Control Enable When this bit is set to 1 the SCGD setting is ignored and SCL is generated with the division ratio set by ICHPR during a high period and with the division ratio set by ICLPR during a low period" "0,1"
bitfld.long 0x00 0. "SME,SCL Mask Enable When this bit is set to 1 a change of internal SCL is ignored after an SCL external input pin changes during the time equal to the number of internal clock cycles specified by ICMPR" "0,1"
group.long 0x2C++0x03
line.long 0x00 "ICMPR0,"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved When these bits are read the value in bits 7 to 0 is set to bits 31 to 24 bits 23 to 16 and bits 15 to 8"
hexmask.long.byte 0x00 0.--7. 1. "SMD,SCL Mask Division When SME = 1 a change of internal SCL is ignored after the external SCL changes during the time equal to the number of internal clock cycles specified by SMD"
group.long 0x30++0x03
line.long 0x00 "ICHPR0,"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved The write value should always be 0"
hexmask.long.word 0x00 0.--15. 1. "SCHD,SCL HIGH Clock Division When HLSE is 1 and internal SCL is driven high the clock generated using the SCHD internal clock division ratio is output"
group.long 0x34++0x03
line.long 0x00 "ICLPR0,"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved The write value should always be 0"
hexmask.long.word 0x00 0.--15. 1. "SCLD,SCL LOW Clock Division When HLSE is 1 and internal SCL is driven low the clock generated using the SCLD internal clock division ratio is output"
group.long 0x38++0x03
line.long 0x00 "ICFBSCR0,Note: The delay time of the 1st data bit between SDA and SCL was calculated as below table"
hexmask.long 0x00 5.--31. 1. "Reserved_5,Reserved When these bits are read bits 31 to 24 23 to 16 and 15 to 8 reflect the values of bits 7 to 0"
bitfld.long 0x00 0.--4. "FBSC_4_0,Setting the delay time of the 1st data bit between SDA and SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x3C++0x03
line.long 0x00 "ICDMAER0,"
hexmask.long.byte 0x00 24.--31. 1. "MDMACTSZ,DMA Master Continuous mode Transfer Size Specify the number of transfer counts"
hexmask.long.byte 0x00 16.--23. 1. "RMDMATSZ,DMA Master Continuous Received mode 1unit Transfer Size register"
newline
hexmask.long.byte 0x00 8.--15. 1. "TMDMATSZ,DMA Master Continuous Transmitted mode 1unit Transfer Size register"
bitfld.long 0x00 7. "TMDMACE,DMA Master Continuous Transmitted Enable" "0: Disables DMA Continuous Transmitted mode,1: Enables DMA Continuous Transmitted mode"
newline
bitfld.long 0x00 6. "RMDMACE,DMA Master Continuous Received Enable" "0: Disables DMA Continuous Received mode,1: Enables DMA Continuous Received mode"
rbitfld.long 0x00 4.--5. "Reserved_4,Reserved The write value should always be 0" "0,1,2,3"
newline
bitfld.long 0x00 3. "RSDMAE,DMA Slave Received Enable" "0: Disables DMA Slave Received Mode,1: Enables DMA Slave Received Mode"
bitfld.long 0x00 2. "TSDMAE,DMA Slave Transmitted Enable" "0: Disables DMA Slave Transmitted Mode,1: Enables DMA Slave Transmitted Mode"
newline
bitfld.long 0x00 1. "RMDMAE,DMA Master Received Enable" "0: Disables DMA Master Received Mode,1: Enables DMA Master Received Mode"
bitfld.long 0x00 0. "TMDMAE,DMA Master Transmitted Enable" "0: Disables DMA Master Transmitted Mode,1: Enables DMA Master Transmitted Mode"
tree.end
tree "I2C_INST_1"
base ad:0xE6508000
group.long 0x00++0x03
line.long 0x00 "ICSCR1,"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved When these bits are read bits 31 to 24 23 to 16 and 15 to 8 reflect the values of bits 7 to 0"
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4. "SCSS,Slave Clock Stretch Select This bit is used to select the timing of Clock Stretch" "0: Clock Stretch is in front of Acknowledgement,1: Clock Stretch is next to Non Acknowledgement"
bitfld.long 0x00 3. "SDBS,Slave Data Buffer Select This bit is used to select the data buffer" "0: Setting prohibited,1: Single-buffer mode"
newline
bitfld.long 0x00 2. "SIE,Slave Interface Enable This bit must be set for the slave operation" "0,1"
bitfld.long 0x00 1. "GCAE,General Call Acknowledgement Enable When slave devices are to issue an acknowledgement in response to a general call address sent from a master this bit must be set to 1" "0,1"
newline
bitfld.long 0x00 0. "FNA,Forced Non Acknowledgement In the slave receive mode the level of this bit is sent to the transmitting device as the acknowledge signal" "0,1"
group.long 0x04++0x03
line.long 0x00 "ICMCR1,"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved When these bits are read bits 31 to 24 23 to 16 and 15 to 8 reflect the values of bits 7 to 0"
bitfld.long 0x00 7. "MDBS,Master Data Buffer Select This bit is used to select the data buffer mode" "0: Setting prohibited,1: Single-buffer mode"
newline
bitfld.long 0x00 6. "FSCL,Forced SCL This bit controls the status of the I2C_SCL pin (reading reflects the current status of the I2C_SCL pin[n])" "0,1"
bitfld.long 0x00 5. "FSDA,Forced SDA This bit controls the status of the I2C_SDA pin (reading reflects the busy status level on the I2C bus[n])" "0,1"
newline
bitfld.long 0x00 4. "OBPC,Override Bus Pin Control When this bit is set to 1 the FSDA and FSCL bits in this register control SDA and SCL directly" "0,1"
bitfld.long 0x00 3. "MIE,Master Interface Enable When this bit is set to 1 the master interface is enabled" "0,1"
newline
bitfld.long 0x00 2. "TSBE,Start Byte Transmission Enable The write value for this bit should always be 0" "0,1"
bitfld.long 0x00 1. "FSB,Forced Stop onto the Bus When this bit is set to 1 the master transmits a STOP condition on the bus at the end of the current transfer" "0,1"
newline
bitfld.long 0x00 0. "ESG,Enable Start Generation When this bit is set to 1 the master starts transmission of a data packet" "0,1"
group.long 0x08++0x03
line.long 0x00 "ICSSR1,Bits 0 to 4 among the status bits in the slave status register are cleared by writing 0 to the respective status bit positions"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved When these bits are read bits 31 to 24 23 to 16 and 15 to 8 reflect the values of bits 7 to 0"
rbitfld.long 0x00 7. "Reserved_7,Reserved The write value should always be 0" "0,1"
newline
rbitfld.long 0x00 6. "GCAR,General Call Address Received Indicates that the address received from the bus is a general call address (H'00[n])" "0,1"
rbitfld.long 0x00 5. "STM,Slave Transmit Mode Indicates whether the current slave transmit mode is read or write" "0,1"
newline
bitfld.long 0x00 4. "SSR,Slave Stop Received A stop condition has been output on the bus" "0,1"
bitfld.long 0x00 3. "SDE,Slave Data Empty Indicates that data to be transmitted has been loaded into the shift register" "0,1"
newline
bitfld.long 0x00 2. "SDT,Slave Data Transmitted A byte of data has been transmitted to the bus" "0,1"
bitfld.long 0x00 1. "SDR,Slave Data Received A byte of data has been received from the bus and is ready for reading from the receive data register" "0,1"
newline
bitfld.long 0x00 0. "SAR,Slave Address Received Indicates that the slave has recognized its own address on the bus (defined by the contents of the slave address register[n])" "0,1"
group.long 0x0C++0x03
line.long 0x00 "ICMSR1,The status bits (bits 0 to 6[n]) in the master status register are cleared by writing 0 to the respective status bit positions"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved When these bits are read bits 31 to 24 23 to 16 and 15 to 8 reflect the values of bits 7 to 0"
rbitfld.long 0x00 7. "Reserved_7,Reserved The write value should always be 0" "0,1"
newline
bitfld.long 0x00 6. "MNR,Master NACK Received When this bit is set to 1 this bit indicates that the master has received a NACK response (the SDA line is high during the acknowledge cycle on the bus[n]) to either an address or data transmission" "0,1"
bitfld.long 0x00 5. "MAL,Master Arbitration Lost In a multi-master system when this bit is set to 1 it indicates that the master has lost arbitration to other masters on the bus" "0,1"
newline
bitfld.long 0x00 4. "MST,Master Stop Transmitted When this bit is set to 1 it indicates that the master has sent a STOP condition on the bus" "0,1"
bitfld.long 0x00 3. "MDE,Master Data Empty At the start of a byte data transmission the contents of the transmit data register are loaded into a shift register ready for transmitting on the bus" "0,1"
newline
bitfld.long 0x00 2. "MDT,Master Data Transmitted Byte data has been sent to the slave on the bus" "0,1"
bitfld.long 0x00 1. "MDR,Master Data Received Byte data has been received from the bus and is in the receive data register" "0,1"
newline
bitfld.long 0x00 0. "MAT,Master Address Transmitted The master has been transmitted the slave address byte of a data packet" "0,1"
group.long 0x10++0x03
line.long 0x00 "ICSIER1,"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved When these bits are read bits 31 to 24 23 to 16 and 15 to 8 reflect the values of bits 7 to 0"
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4. "SSRE,Slave Stop Received Interrupt Enable" "0: Disables the SSR interrupt,1: Enables the SSR interrupt"
bitfld.long 0x00 3. "SDEE,Slave Data Empty Interrupt Enable" "0: Disables the SDE interrupt,1: Enables the SDE interrupt"
newline
bitfld.long 0x00 2. "SDTE,Slave Data Transmitted Interrupt Enable" "0: Disables the SDT interrupt,1: Enables the SDT interrupt"
bitfld.long 0x00 1. "SDRE,Slave Data Received Interrupt Enable" "0: Disables the SDR interrupt,1: Enables the SDR interrupt"
newline
bitfld.long 0x00 0. "SARE,Slave Address Received Interrupt Enable" "0: Disables the SAR interrupt,1: Enables the SAR interrupt"
group.long 0x14++0x03
line.long 0x00 "ICMIER1,"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved When these bits are read bits 31 to 24 23 to 16 and 15 to 8 reflect the values of bits 7 to 0"
rbitfld.long 0x00 7. "Reserved_7,Reserved The write value should always be 0" "0,1"
newline
bitfld.long 0x00 6. "MNRE,Master NACK Received Interrupt Enable" "0: Disables the MNR interrupt,1: Enables the MNR interrupt"
bitfld.long 0x00 5. "MALE,Master Arbitration Lost Interrupt Enable" "0: Disables the MAL interrupt,1: Enables the MAL interrupt"
newline
bitfld.long 0x00 4. "MSTE,Master Stop Transmitted Interrupt Enable" "0: Disables the MST interrupt,1: Enables the MST interrupt"
bitfld.long 0x00 3. "MDEE,Master Data Empty Interrupt Enable" "0: Disables the MDE interrupt,1: Enables the MDE interrupt"
newline
bitfld.long 0x00 2. "MDTE,Master Data Transmitted Interrupt Enable" "0: Disables the MDT interrupt,1: Enables the MDT interrupt"
bitfld.long 0x00 1. "MDRE,Master Data Received Interrupt Enable" "0: Disables the MDR interrupt,1: Enables the MDR interrupt"
newline
bitfld.long 0x00 0. "MATE,Master Address Transmitted Interrupt Enable" "0: Disables the MAT interrupt,1: Enables the MAT interrupt"
group.long 0x18++0x03
line.long 0x00 "ICCCR1,"
hexmask.long.tbyte 0x00 9.--31. 1. "Reserved_9,Reserved The read value is always 0"
bitfld.long 0x00 3.--8. "SCGD,SCL Clock Generation Divider When operation is in master mode the SCL clock is generated from the internal clock by using SCGD as the ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0.--2. "CDF,Clock Division Factor The internal clock used in most blocks in the I2C module is a divided module clock" "0,1,2,3,4,5,6,7"
group.long 0x1C++0x03
line.long 0x00 "ICSAR1,"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved When these bits are read bits 31 to 24 23 to 16 and 15 to 8 reflect the values of bits 7 to 0"
rbitfld.long 0x00 7. "Reserved_7,Reserved The write value should always be 0" "0,1"
newline
hexmask.long.byte 0x00 0.--6. 1. "SADD0_6_0,Slave Address This is the unique 7-bit address allocated to the slave on the I2C bus"
group.long 0x20++0x03
line.long 0x00 "ICMAR1,"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved When these bits are read bits 31 to 24 23 to 16 and 15 to 8 reflect the values of bits 7 to 0"
hexmask.long.byte 0x00 1.--7. 1. "SADD1_6_0,Slave Address These bits are the address of the slave which the master communicates with"
newline
bitfld.long 0x00 0. "STM1,Slave Transfer Mode This bit specifies the mode in which the slave operates" "0,1"
group.long 0x24++0x03
line.long 0x00 "ICRXD_ICTXD1,"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved When these bits are read bits 31 to 24 23 to 16 and 15 to 8 reflect the values of bits 7 to 0"
hexmask.long.byte 0x00 0.--7. 1. "RXD_TXD,Read Receive Data Data received by master or slave"
group.long 0x28++0x03
line.long 0x00 "ICCCR21,Notes: 1"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved When these bits are read the value in bits 7 to 0 is set to bits 31 to 24 bits 23 to 16 and bits 15 to 8"
rbitfld.long 0x00 7. "Reserved_7,Reserved The write value should always be 0" "0,1"
newline
rbitfld.long 0x00 3.--6. "Reserved_3,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 2. "CDFD,CDF Disable When this bit is set to 1 the module clock is used for internal clocks except the clock filter" "0,1"
newline
bitfld.long 0x00 1. "HLSE,HIGH/LOW Separate Control Enable When this bit is set to 1 the SCGD setting is ignored and SCL is generated with the division ratio set by ICHPR during a high period and with the division ratio set by ICLPR during a low period" "0,1"
bitfld.long 0x00 0. "SME,SCL Mask Enable When this bit is set to 1 a change of internal SCL is ignored after an SCL external input pin changes during the time equal to the number of internal clock cycles specified by ICMPR" "0,1"
group.long 0x2C++0x03
line.long 0x00 "ICMPR1,"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved When these bits are read the value in bits 7 to 0 is set to bits 31 to 24 bits 23 to 16 and bits 15 to 8"
hexmask.long.byte 0x00 0.--7. 1. "SMD,SCL Mask Division When SME = 1 a change of internal SCL is ignored after the external SCL changes during the time equal to the number of internal clock cycles specified by SMD"
group.long 0x30++0x03
line.long 0x00 "ICHPR1,"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved The write value should always be 0"
hexmask.long.word 0x00 0.--15. 1. "SCHD,SCL HIGH Clock Division When HLSE is 1 and internal SCL is driven high the clock generated using the SCHD internal clock division ratio is output"
group.long 0x34++0x03
line.long 0x00 "ICLPR1,"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved The write value should always be 0"
hexmask.long.word 0x00 0.--15. 1. "SCLD,SCL LOW Clock Division When HLSE is 1 and internal SCL is driven low the clock generated using the SCLD internal clock division ratio is output"
group.long 0x38++0x03
line.long 0x00 "ICFBSCR1,Note: The delay time of the 1st data bit between SDA and SCL was calculated as below table"
hexmask.long 0x00 5.--31. 1. "Reserved_5,Reserved When these bits are read bits 31 to 24 23 to 16 and 15 to 8 reflect the values of bits 7 to 0"
bitfld.long 0x00 0.--4. "FBSC_4_0,Setting the delay time of the 1st data bit between SDA and SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x3C++0x03
line.long 0x00 "ICDMAER1,"
hexmask.long.byte 0x00 24.--31. 1. "MDMACTSZ,DMA Master Continuous mode Transfer Size Specify the number of transfer counts"
hexmask.long.byte 0x00 16.--23. 1. "RMDMATSZ,DMA Master Continuous Received mode 1unit Transfer Size register"
newline
hexmask.long.byte 0x00 8.--15. 1. "TMDMATSZ,DMA Master Continuous Transmitted mode 1unit Transfer Size register"
bitfld.long 0x00 7. "TMDMACE,DMA Master Continuous Transmitted Enable" "0: Disables DMA Continuous Transmitted mode,1: Enables DMA Continuous Transmitted mode"
newline
bitfld.long 0x00 6. "RMDMACE,DMA Master Continuous Received Enable" "0: Disables DMA Continuous Received mode,1: Enables DMA Continuous Received mode"
rbitfld.long 0x00 4.--5. "Reserved_4,Reserved The write value should always be 0" "0,1,2,3"
newline
bitfld.long 0x00 3. "RSDMAE,DMA Slave Received Enable" "0: Disables DMA Slave Received Mode,1: Enables DMA Slave Received Mode"
bitfld.long 0x00 2. "TSDMAE,DMA Slave Transmitted Enable" "0: Disables DMA Slave Transmitted Mode,1: Enables DMA Slave Transmitted Mode"
newline
bitfld.long 0x00 1. "RMDMAE,DMA Master Received Enable" "0: Disables DMA Master Received Mode,1: Enables DMA Master Received Mode"
bitfld.long 0x00 0. "TMDMAE,DMA Master Transmitted Enable" "0: Disables DMA Master Transmitted Mode,1: Enables DMA Master Transmitted Mode"
tree.end
tree "I2C_INST_2"
base ad:0xE6510000
group.long 0x00++0x03
line.long 0x00 "ICSCR2,"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved When these bits are read bits 31 to 24 23 to 16 and 15 to 8 reflect the values of bits 7 to 0"
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4. "SCSS,Slave Clock Stretch Select This bit is used to select the timing of Clock Stretch" "0: Clock Stretch is in front of Acknowledgement,1: Clock Stretch is next to Non Acknowledgement"
bitfld.long 0x00 3. "SDBS,Slave Data Buffer Select This bit is used to select the data buffer" "0: Setting prohibited,1: Single-buffer mode"
newline
bitfld.long 0x00 2. "SIE,Slave Interface Enable This bit must be set for the slave operation" "0,1"
bitfld.long 0x00 1. "GCAE,General Call Acknowledgement Enable When slave devices are to issue an acknowledgement in response to a general call address sent from a master this bit must be set to 1" "0,1"
newline
bitfld.long 0x00 0. "FNA,Forced Non Acknowledgement In the slave receive mode the level of this bit is sent to the transmitting device as the acknowledge signal" "0,1"
group.long 0x04++0x03
line.long 0x00 "ICMCR2,"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved When these bits are read bits 31 to 24 23 to 16 and 15 to 8 reflect the values of bits 7 to 0"
bitfld.long 0x00 7. "MDBS,Master Data Buffer Select This bit is used to select the data buffer mode" "0: Setting prohibited,1: Single-buffer mode"
newline
bitfld.long 0x00 6. "FSCL,Forced SCL This bit controls the status of the I2C_SCL pin (reading reflects the current status of the I2C_SCL pin[n])" "0,1"
bitfld.long 0x00 5. "FSDA,Forced SDA This bit controls the status of the I2C_SDA pin (reading reflects the busy status level on the I2C bus[n])" "0,1"
newline
bitfld.long 0x00 4. "OBPC,Override Bus Pin Control When this bit is set to 1 the FSDA and FSCL bits in this register control SDA and SCL directly" "0,1"
bitfld.long 0x00 3. "MIE,Master Interface Enable When this bit is set to 1 the master interface is enabled" "0,1"
newline
bitfld.long 0x00 2. "TSBE,Start Byte Transmission Enable The write value for this bit should always be 0" "0,1"
bitfld.long 0x00 1. "FSB,Forced Stop onto the Bus When this bit is set to 1 the master transmits a STOP condition on the bus at the end of the current transfer" "0,1"
newline
bitfld.long 0x00 0. "ESG,Enable Start Generation When this bit is set to 1 the master starts transmission of a data packet" "0,1"
group.long 0x08++0x03
line.long 0x00 "ICSSR2,Bits 0 to 4 among the status bits in the slave status register are cleared by writing 0 to the respective status bit positions"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved When these bits are read bits 31 to 24 23 to 16 and 15 to 8 reflect the values of bits 7 to 0"
rbitfld.long 0x00 7. "Reserved_7,Reserved The write value should always be 0" "0,1"
newline
rbitfld.long 0x00 6. "GCAR,General Call Address Received Indicates that the address received from the bus is a general call address (H'00[n])" "0,1"
rbitfld.long 0x00 5. "STM,Slave Transmit Mode Indicates whether the current slave transmit mode is read or write" "0,1"
newline
bitfld.long 0x00 4. "SSR,Slave Stop Received A stop condition has been output on the bus" "0,1"
bitfld.long 0x00 3. "SDE,Slave Data Empty Indicates that data to be transmitted has been loaded into the shift register" "0,1"
newline
bitfld.long 0x00 2. "SDT,Slave Data Transmitted A byte of data has been transmitted to the bus" "0,1"
bitfld.long 0x00 1. "SDR,Slave Data Received A byte of data has been received from the bus and is ready for reading from the receive data register" "0,1"
newline
bitfld.long 0x00 0. "SAR,Slave Address Received Indicates that the slave has recognized its own address on the bus (defined by the contents of the slave address register[n])" "0,1"
group.long 0x0C++0x03
line.long 0x00 "ICMSR2,The status bits (bits 0 to 6[n]) in the master status register are cleared by writing 0 to the respective status bit positions"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved When these bits are read bits 31 to 24 23 to 16 and 15 to 8 reflect the values of bits 7 to 0"
rbitfld.long 0x00 7. "Reserved_7,Reserved The write value should always be 0" "0,1"
newline
bitfld.long 0x00 6. "MNR,Master NACK Received When this bit is set to 1 this bit indicates that the master has received a NACK response (the SDA line is high during the acknowledge cycle on the bus[n]) to either an address or data transmission" "0,1"
bitfld.long 0x00 5. "MAL,Master Arbitration Lost In a multi-master system when this bit is set to 1 it indicates that the master has lost arbitration to other masters on the bus" "0,1"
newline
bitfld.long 0x00 4. "MST,Master Stop Transmitted When this bit is set to 1 it indicates that the master has sent a STOP condition on the bus" "0,1"
bitfld.long 0x00 3. "MDE,Master Data Empty At the start of a byte data transmission the contents of the transmit data register are loaded into a shift register ready for transmitting on the bus" "0,1"
newline
bitfld.long 0x00 2. "MDT,Master Data Transmitted Byte data has been sent to the slave on the bus" "0,1"
bitfld.long 0x00 1. "MDR,Master Data Received Byte data has been received from the bus and is in the receive data register" "0,1"
newline
bitfld.long 0x00 0. "MAT,Master Address Transmitted The master has been transmitted the slave address byte of a data packet" "0,1"
group.long 0x10++0x03
line.long 0x00 "ICSIER2,"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved When these bits are read bits 31 to 24 23 to 16 and 15 to 8 reflect the values of bits 7 to 0"
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4. "SSRE,Slave Stop Received Interrupt Enable" "0: Disables the SSR interrupt,1: Enables the SSR interrupt"
bitfld.long 0x00 3. "SDEE,Slave Data Empty Interrupt Enable" "0: Disables the SDE interrupt,1: Enables the SDE interrupt"
newline
bitfld.long 0x00 2. "SDTE,Slave Data Transmitted Interrupt Enable" "0: Disables the SDT interrupt,1: Enables the SDT interrupt"
bitfld.long 0x00 1. "SDRE,Slave Data Received Interrupt Enable" "0: Disables the SDR interrupt,1: Enables the SDR interrupt"
newline
bitfld.long 0x00 0. "SARE,Slave Address Received Interrupt Enable" "0: Disables the SAR interrupt,1: Enables the SAR interrupt"
group.long 0x14++0x03
line.long 0x00 "ICMIER2,"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved When these bits are read bits 31 to 24 23 to 16 and 15 to 8 reflect the values of bits 7 to 0"
rbitfld.long 0x00 7. "Reserved_7,Reserved The write value should always be 0" "0,1"
newline
bitfld.long 0x00 6. "MNRE,Master NACK Received Interrupt Enable" "0: Disables the MNR interrupt,1: Enables the MNR interrupt"
bitfld.long 0x00 5. "MALE,Master Arbitration Lost Interrupt Enable" "0: Disables the MAL interrupt,1: Enables the MAL interrupt"
newline
bitfld.long 0x00 4. "MSTE,Master Stop Transmitted Interrupt Enable" "0: Disables the MST interrupt,1: Enables the MST interrupt"
bitfld.long 0x00 3. "MDEE,Master Data Empty Interrupt Enable" "0: Disables the MDE interrupt,1: Enables the MDE interrupt"
newline
bitfld.long 0x00 2. "MDTE,Master Data Transmitted Interrupt Enable" "0: Disables the MDT interrupt,1: Enables the MDT interrupt"
bitfld.long 0x00 1. "MDRE,Master Data Received Interrupt Enable" "0: Disables the MDR interrupt,1: Enables the MDR interrupt"
newline
bitfld.long 0x00 0. "MATE,Master Address Transmitted Interrupt Enable" "0: Disables the MAT interrupt,1: Enables the MAT interrupt"
group.long 0x18++0x03
line.long 0x00 "ICCCR2,"
hexmask.long.tbyte 0x00 9.--31. 1. "Reserved_9,Reserved The read value is always 0"
bitfld.long 0x00 3.--8. "SCGD,SCL Clock Generation Divider When operation is in master mode the SCL clock is generated from the internal clock by using SCGD as the ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0.--2. "CDF,Clock Division Factor The internal clock used in most blocks in the I2C module is a divided module clock" "0,1,2,3,4,5,6,7"
group.long 0x1C++0x03
line.long 0x00 "ICSAR2,"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved When these bits are read bits 31 to 24 23 to 16 and 15 to 8 reflect the values of bits 7 to 0"
rbitfld.long 0x00 7. "Reserved_7,Reserved The write value should always be 0" "0,1"
newline
hexmask.long.byte 0x00 0.--6. 1. "SADD0_6_0,Slave Address This is the unique 7-bit address allocated to the slave on the I2C bus"
group.long 0x20++0x03
line.long 0x00 "ICMAR2,"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved When these bits are read bits 31 to 24 23 to 16 and 15 to 8 reflect the values of bits 7 to 0"
hexmask.long.byte 0x00 1.--7. 1. "SADD1_6_0,Slave Address These bits are the address of the slave which the master communicates with"
newline
bitfld.long 0x00 0. "STM1,Slave Transfer Mode This bit specifies the mode in which the slave operates" "0,1"
group.long 0x24++0x03
line.long 0x00 "ICRXD_ICTXD2,"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved When these bits are read bits 31 to 24 23 to 16 and 15 to 8 reflect the values of bits 7 to 0"
hexmask.long.byte 0x00 0.--7. 1. "RXD_TXD,Read Receive Data Data received by master or slave"
group.long 0x28++0x03
line.long 0x00 "ICCCR22,Notes: 1"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved When these bits are read the value in bits 7 to 0 is set to bits 31 to 24 bits 23 to 16 and bits 15 to 8"
rbitfld.long 0x00 7. "Reserved_7,Reserved The write value should always be 0" "0,1"
newline
rbitfld.long 0x00 3.--6. "Reserved_3,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 2. "CDFD,CDF Disable When this bit is set to 1 the module clock is used for internal clocks except the clock filter" "0,1"
newline
bitfld.long 0x00 1. "HLSE,HIGH/LOW Separate Control Enable When this bit is set to 1 the SCGD setting is ignored and SCL is generated with the division ratio set by ICHPR during a high period and with the division ratio set by ICLPR during a low period" "0,1"
bitfld.long 0x00 0. "SME,SCL Mask Enable When this bit is set to 1 a change of internal SCL is ignored after an SCL external input pin changes during the time equal to the number of internal clock cycles specified by ICMPR" "0,1"
group.long 0x2C++0x03
line.long 0x00 "ICMPR2,"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved When these bits are read the value in bits 7 to 0 is set to bits 31 to 24 bits 23 to 16 and bits 15 to 8"
hexmask.long.byte 0x00 0.--7. 1. "SMD,SCL Mask Division When SME = 1 a change of internal SCL is ignored after the external SCL changes during the time equal to the number of internal clock cycles specified by SMD"
group.long 0x30++0x03
line.long 0x00 "ICHPR2,"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved The write value should always be 0"
hexmask.long.word 0x00 0.--15. 1. "SCHD,SCL HIGH Clock Division When HLSE is 1 and internal SCL is driven high the clock generated using the SCHD internal clock division ratio is output"
group.long 0x34++0x03
line.long 0x00 "ICLPR2,"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved The write value should always be 0"
hexmask.long.word 0x00 0.--15. 1. "SCLD,SCL LOW Clock Division When HLSE is 1 and internal SCL is driven low the clock generated using the SCLD internal clock division ratio is output"
group.long 0x38++0x03
line.long 0x00 "ICFBSCR2,Note: The delay time of the 1st data bit between SDA and SCL was calculated as below table"
hexmask.long 0x00 5.--31. 1. "Reserved_5,Reserved When these bits are read bits 31 to 24 23 to 16 and 15 to 8 reflect the values of bits 7 to 0"
bitfld.long 0x00 0.--4. "FBSC_4_0,Setting the delay time of the 1st data bit between SDA and SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x3C++0x03
line.long 0x00 "ICDMAER2,"
hexmask.long.byte 0x00 24.--31. 1. "MDMACTSZ,DMA Master Continuous mode Transfer Size Specify the number of transfer counts"
hexmask.long.byte 0x00 16.--23. 1. "RMDMATSZ,DMA Master Continuous Received mode 1unit Transfer Size register"
newline
hexmask.long.byte 0x00 8.--15. 1. "TMDMATSZ,DMA Master Continuous Transmitted mode 1unit Transfer Size register"
bitfld.long 0x00 7. "TMDMACE,DMA Master Continuous Transmitted Enable" "0: Disables DMA Continuous Transmitted mode,1: Enables DMA Continuous Transmitted mode"
newline
bitfld.long 0x00 6. "RMDMACE,DMA Master Continuous Received Enable" "0: Disables DMA Continuous Received mode,1: Enables DMA Continuous Received mode"
rbitfld.long 0x00 4.--5. "Reserved_4,Reserved The write value should always be 0" "0,1,2,3"
newline
bitfld.long 0x00 3. "RSDMAE,DMA Slave Received Enable" "0: Disables DMA Slave Received Mode,1: Enables DMA Slave Received Mode"
bitfld.long 0x00 2. "TSDMAE,DMA Slave Transmitted Enable" "0: Disables DMA Slave Transmitted Mode,1: Enables DMA Slave Transmitted Mode"
newline
bitfld.long 0x00 1. "RMDMAE,DMA Master Received Enable" "0: Disables DMA Master Received Mode,1: Enables DMA Master Received Mode"
bitfld.long 0x00 0. "TMDMAE,DMA Master Transmitted Enable" "0: Disables DMA Master Transmitted Mode,1: Enables DMA Master Transmitted Mode"
tree.end
tree "I2C_INST_3"
base ad:0xE66D0000
group.long 0x00++0x03
line.long 0x00 "ICSCR3,"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved When these bits are read bits 31 to 24 23 to 16 and 15 to 8 reflect the values of bits 7 to 0"
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4. "SCSS,Slave Clock Stretch Select This bit is used to select the timing of Clock Stretch" "0: Clock Stretch is in front of Acknowledgement,1: Clock Stretch is next to Non Acknowledgement"
bitfld.long 0x00 3. "SDBS,Slave Data Buffer Select This bit is used to select the data buffer" "0: Setting prohibited,1: Single-buffer mode"
newline
bitfld.long 0x00 2. "SIE,Slave Interface Enable This bit must be set for the slave operation" "0,1"
bitfld.long 0x00 1. "GCAE,General Call Acknowledgement Enable When slave devices are to issue an acknowledgement in response to a general call address sent from a master this bit must be set to 1" "0,1"
newline
bitfld.long 0x00 0. "FNA,Forced Non Acknowledgement In the slave receive mode the level of this bit is sent to the transmitting device as the acknowledge signal" "0,1"
group.long 0x04++0x03
line.long 0x00 "ICMCR3,"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved When these bits are read bits 31 to 24 23 to 16 and 15 to 8 reflect the values of bits 7 to 0"
bitfld.long 0x00 7. "MDBS,Master Data Buffer Select This bit is used to select the data buffer mode" "0: Setting prohibited,1: Single-buffer mode"
newline
bitfld.long 0x00 6. "FSCL,Forced SCL This bit controls the status of the I2C_SCL pin (reading reflects the current status of the I2C_SCL pin[n])" "0,1"
bitfld.long 0x00 5. "FSDA,Forced SDA This bit controls the status of the I2C_SDA pin (reading reflects the busy status level on the I2C bus[n])" "0,1"
newline
bitfld.long 0x00 4. "OBPC,Override Bus Pin Control When this bit is set to 1 the FSDA and FSCL bits in this register control SDA and SCL directly" "0,1"
bitfld.long 0x00 3. "MIE,Master Interface Enable When this bit is set to 1 the master interface is enabled" "0,1"
newline
bitfld.long 0x00 2. "TSBE,Start Byte Transmission Enable The write value for this bit should always be 0" "0,1"
bitfld.long 0x00 1. "FSB,Forced Stop onto the Bus When this bit is set to 1 the master transmits a STOP condition on the bus at the end of the current transfer" "0,1"
newline
bitfld.long 0x00 0. "ESG,Enable Start Generation When this bit is set to 1 the master starts transmission of a data packet" "0,1"
group.long 0x08++0x03
line.long 0x00 "ICSSR3,Bits 0 to 4 among the status bits in the slave status register are cleared by writing 0 to the respective status bit positions"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved When these bits are read bits 31 to 24 23 to 16 and 15 to 8 reflect the values of bits 7 to 0"
rbitfld.long 0x00 7. "Reserved_7,Reserved The write value should always be 0" "0,1"
newline
rbitfld.long 0x00 6. "GCAR,General Call Address Received Indicates that the address received from the bus is a general call address (H'00[n])" "0,1"
rbitfld.long 0x00 5. "STM,Slave Transmit Mode Indicates whether the current slave transmit mode is read or write" "0,1"
newline
bitfld.long 0x00 4. "SSR,Slave Stop Received A stop condition has been output on the bus" "0,1"
bitfld.long 0x00 3. "SDE,Slave Data Empty Indicates that data to be transmitted has been loaded into the shift register" "0,1"
newline
bitfld.long 0x00 2. "SDT,Slave Data Transmitted A byte of data has been transmitted to the bus" "0,1"
bitfld.long 0x00 1. "SDR,Slave Data Received A byte of data has been received from the bus and is ready for reading from the receive data register" "0,1"
newline
bitfld.long 0x00 0. "SAR,Slave Address Received Indicates that the slave has recognized its own address on the bus (defined by the contents of the slave address register[n])" "0,1"
group.long 0x0C++0x03
line.long 0x00 "ICMSR3,The status bits (bits 0 to 6[n]) in the master status register are cleared by writing 0 to the respective status bit positions"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved When these bits are read bits 31 to 24 23 to 16 and 15 to 8 reflect the values of bits 7 to 0"
rbitfld.long 0x00 7. "Reserved_7,Reserved The write value should always be 0" "0,1"
newline
bitfld.long 0x00 6. "MNR,Master NACK Received When this bit is set to 1 this bit indicates that the master has received a NACK response (the SDA line is high during the acknowledge cycle on the bus[n]) to either an address or data transmission" "0,1"
bitfld.long 0x00 5. "MAL,Master Arbitration Lost In a multi-master system when this bit is set to 1 it indicates that the master has lost arbitration to other masters on the bus" "0,1"
newline
bitfld.long 0x00 4. "MST,Master Stop Transmitted When this bit is set to 1 it indicates that the master has sent a STOP condition on the bus" "0,1"
bitfld.long 0x00 3. "MDE,Master Data Empty At the start of a byte data transmission the contents of the transmit data register are loaded into a shift register ready for transmitting on the bus" "0,1"
newline
bitfld.long 0x00 2. "MDT,Master Data Transmitted Byte data has been sent to the slave on the bus" "0,1"
bitfld.long 0x00 1. "MDR,Master Data Received Byte data has been received from the bus and is in the receive data register" "0,1"
newline
bitfld.long 0x00 0. "MAT,Master Address Transmitted The master has been transmitted the slave address byte of a data packet" "0,1"
group.long 0x10++0x03
line.long 0x00 "ICSIER3,"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved When these bits are read bits 31 to 24 23 to 16 and 15 to 8 reflect the values of bits 7 to 0"
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4. "SSRE,Slave Stop Received Interrupt Enable" "0: Disables the SSR interrupt,1: Enables the SSR interrupt"
bitfld.long 0x00 3. "SDEE,Slave Data Empty Interrupt Enable" "0: Disables the SDE interrupt,1: Enables the SDE interrupt"
newline
bitfld.long 0x00 2. "SDTE,Slave Data Transmitted Interrupt Enable" "0: Disables the SDT interrupt,1: Enables the SDT interrupt"
bitfld.long 0x00 1. "SDRE,Slave Data Received Interrupt Enable" "0: Disables the SDR interrupt,1: Enables the SDR interrupt"
newline
bitfld.long 0x00 0. "SARE,Slave Address Received Interrupt Enable" "0: Disables the SAR interrupt,1: Enables the SAR interrupt"
group.long 0x14++0x03
line.long 0x00 "ICMIER3,"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved When these bits are read bits 31 to 24 23 to 16 and 15 to 8 reflect the values of bits 7 to 0"
rbitfld.long 0x00 7. "Reserved_7,Reserved The write value should always be 0" "0,1"
newline
bitfld.long 0x00 6. "MNRE,Master NACK Received Interrupt Enable" "0: Disables the MNR interrupt,1: Enables the MNR interrupt"
bitfld.long 0x00 5. "MALE,Master Arbitration Lost Interrupt Enable" "0: Disables the MAL interrupt,1: Enables the MAL interrupt"
newline
bitfld.long 0x00 4. "MSTE,Master Stop Transmitted Interrupt Enable" "0: Disables the MST interrupt,1: Enables the MST interrupt"
bitfld.long 0x00 3. "MDEE,Master Data Empty Interrupt Enable" "0: Disables the MDE interrupt,1: Enables the MDE interrupt"
newline
bitfld.long 0x00 2. "MDTE,Master Data Transmitted Interrupt Enable" "0: Disables the MDT interrupt,1: Enables the MDT interrupt"
bitfld.long 0x00 1. "MDRE,Master Data Received Interrupt Enable" "0: Disables the MDR interrupt,1: Enables the MDR interrupt"
newline
bitfld.long 0x00 0. "MATE,Master Address Transmitted Interrupt Enable" "0: Disables the MAT interrupt,1: Enables the MAT interrupt"
group.long 0x18++0x03
line.long 0x00 "ICCCR3,"
hexmask.long.tbyte 0x00 9.--31. 1. "Reserved_9,Reserved The read value is always 0"
bitfld.long 0x00 3.--8. "SCGD,SCL Clock Generation Divider When operation is in master mode the SCL clock is generated from the internal clock by using SCGD as the ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0.--2. "CDF,Clock Division Factor The internal clock used in most blocks in the I2C module is a divided module clock" "0,1,2,3,4,5,6,7"
group.long 0x1C++0x03
line.long 0x00 "ICSAR3,"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved When these bits are read bits 31 to 24 23 to 16 and 15 to 8 reflect the values of bits 7 to 0"
rbitfld.long 0x00 7. "Reserved_7,Reserved The write value should always be 0" "0,1"
newline
hexmask.long.byte 0x00 0.--6. 1. "SADD0_6_0,Slave Address This is the unique 7-bit address allocated to the slave on the I2C bus"
group.long 0x20++0x03
line.long 0x00 "ICMAR3,"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved When these bits are read bits 31 to 24 23 to 16 and 15 to 8 reflect the values of bits 7 to 0"
hexmask.long.byte 0x00 1.--7. 1. "SADD1_6_0,Slave Address These bits are the address of the slave which the master communicates with"
newline
bitfld.long 0x00 0. "STM1,Slave Transfer Mode This bit specifies the mode in which the slave operates" "0,1"
group.long 0x24++0x03
line.long 0x00 "ICRXD_ICTXD3,"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved When these bits are read bits 31 to 24 23 to 16 and 15 to 8 reflect the values of bits 7 to 0"
hexmask.long.byte 0x00 0.--7. 1. "RXD_TXD,Read Receive Data Data received by master or slave"
group.long 0x28++0x03
line.long 0x00 "ICCCR23,Notes: 1"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved When these bits are read the value in bits 7 to 0 is set to bits 31 to 24 bits 23 to 16 and bits 15 to 8"
rbitfld.long 0x00 7. "Reserved_7,Reserved The write value should always be 0" "0,1"
newline
rbitfld.long 0x00 3.--6. "Reserved_3,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 2. "CDFD,CDF Disable When this bit is set to 1 the module clock is used for internal clocks except the clock filter" "0,1"
newline
bitfld.long 0x00 1. "HLSE,HIGH/LOW Separate Control Enable When this bit is set to 1 the SCGD setting is ignored and SCL is generated with the division ratio set by ICHPR during a high period and with the division ratio set by ICLPR during a low period" "0,1"
bitfld.long 0x00 0. "SME,SCL Mask Enable When this bit is set to 1 a change of internal SCL is ignored after an SCL external input pin changes during the time equal to the number of internal clock cycles specified by ICMPR" "0,1"
group.long 0x2C++0x03
line.long 0x00 "ICMPR3,"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved When these bits are read the value in bits 7 to 0 is set to bits 31 to 24 bits 23 to 16 and bits 15 to 8"
hexmask.long.byte 0x00 0.--7. 1. "SMD,SCL Mask Division When SME = 1 a change of internal SCL is ignored after the external SCL changes during the time equal to the number of internal clock cycles specified by SMD"
group.long 0x30++0x03
line.long 0x00 "ICHPR3,"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved The write value should always be 0"
hexmask.long.word 0x00 0.--15. 1. "SCHD,SCL HIGH Clock Division When HLSE is 1 and internal SCL is driven high the clock generated using the SCHD internal clock division ratio is output"
group.long 0x34++0x03
line.long 0x00 "ICLPR3,"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved The write value should always be 0"
hexmask.long.word 0x00 0.--15. 1. "SCLD,SCL LOW Clock Division When HLSE is 1 and internal SCL is driven low the clock generated using the SCLD internal clock division ratio is output"
group.long 0x38++0x03
line.long 0x00 "ICFBSCR3,Note: The delay time of the 1st data bit between SDA and SCL was calculated as below table"
hexmask.long 0x00 5.--31. 1. "Reserved_5,Reserved When these bits are read bits 31 to 24 23 to 16 and 15 to 8 reflect the values of bits 7 to 0"
bitfld.long 0x00 0.--4. "FBSC_4_0,Setting the delay time of the 1st data bit between SDA and SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x3C++0x03
line.long 0x00 "ICDMAER3,"
hexmask.long.byte 0x00 24.--31. 1. "MDMACTSZ,DMA Master Continuous mode Transfer Size Specify the number of transfer counts"
hexmask.long.byte 0x00 16.--23. 1. "RMDMATSZ,DMA Master Continuous Received mode 1unit Transfer Size register"
newline
hexmask.long.byte 0x00 8.--15. 1. "TMDMATSZ,DMA Master Continuous Transmitted mode 1unit Transfer Size register"
bitfld.long 0x00 7. "TMDMACE,DMA Master Continuous Transmitted Enable" "0: Disables DMA Continuous Transmitted mode,1: Enables DMA Continuous Transmitted mode"
newline
bitfld.long 0x00 6. "RMDMACE,DMA Master Continuous Received Enable" "0: Disables DMA Continuous Received mode,1: Enables DMA Continuous Received mode"
rbitfld.long 0x00 4.--5. "Reserved_4,Reserved The write value should always be 0" "0,1,2,3"
newline
bitfld.long 0x00 3. "RSDMAE,DMA Slave Received Enable" "0: Disables DMA Slave Received Mode,1: Enables DMA Slave Received Mode"
bitfld.long 0x00 2. "TSDMAE,DMA Slave Transmitted Enable" "0: Disables DMA Slave Transmitted Mode,1: Enables DMA Slave Transmitted Mode"
newline
bitfld.long 0x00 1. "RMDMAE,DMA Master Received Enable" "0: Disables DMA Master Received Mode,1: Enables DMA Master Received Mode"
bitfld.long 0x00 0. "TMDMAE,DMA Master Transmitted Enable" "0: Disables DMA Master Transmitted Mode,1: Enables DMA Master Transmitted Mode"
tree.end
tree "I2C_INST_4"
base ad:0xE66D8000
group.long 0x00++0x03
line.long 0x00 "ICSCR4,"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved When these bits are read bits 31 to 24 23 to 16 and 15 to 8 reflect the values of bits 7 to 0"
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4. "SCSS,Slave Clock Stretch Select This bit is used to select the timing of Clock Stretch" "0: Clock Stretch is in front of Acknowledgement,1: Clock Stretch is next to Non Acknowledgement"
bitfld.long 0x00 3. "SDBS,Slave Data Buffer Select This bit is used to select the data buffer" "0: Setting prohibited,1: Single-buffer mode"
newline
bitfld.long 0x00 2. "SIE,Slave Interface Enable This bit must be set for the slave operation" "0,1"
bitfld.long 0x00 1. "GCAE,General Call Acknowledgement Enable When slave devices are to issue an acknowledgement in response to a general call address sent from a master this bit must be set to 1" "0,1"
newline
bitfld.long 0x00 0. "FNA,Forced Non Acknowledgement In the slave receive mode the level of this bit is sent to the transmitting device as the acknowledge signal" "0,1"
group.long 0x04++0x03
line.long 0x00 "ICMCR4,"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved When these bits are read bits 31 to 24 23 to 16 and 15 to 8 reflect the values of bits 7 to 0"
bitfld.long 0x00 7. "MDBS,Master Data Buffer Select This bit is used to select the data buffer mode" "0: Setting prohibited,1: Single-buffer mode"
newline
bitfld.long 0x00 6. "FSCL,Forced SCL This bit controls the status of the I2C_SCL pin (reading reflects the current status of the I2C_SCL pin[n])" "0,1"
bitfld.long 0x00 5. "FSDA,Forced SDA This bit controls the status of the I2C_SDA pin (reading reflects the busy status level on the I2C bus[n])" "0,1"
newline
bitfld.long 0x00 4. "OBPC,Override Bus Pin Control When this bit is set to 1 the FSDA and FSCL bits in this register control SDA and SCL directly" "0,1"
bitfld.long 0x00 3. "MIE,Master Interface Enable When this bit is set to 1 the master interface is enabled" "0,1"
newline
bitfld.long 0x00 2. "TSBE,Start Byte Transmission Enable The write value for this bit should always be 0" "0,1"
bitfld.long 0x00 1. "FSB,Forced Stop onto the Bus When this bit is set to 1 the master transmits a STOP condition on the bus at the end of the current transfer" "0,1"
newline
bitfld.long 0x00 0. "ESG,Enable Start Generation When this bit is set to 1 the master starts transmission of a data packet" "0,1"
group.long 0x08++0x03
line.long 0x00 "ICSSR4,Bits 0 to 4 among the status bits in the slave status register are cleared by writing 0 to the respective status bit positions"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved When these bits are read bits 31 to 24 23 to 16 and 15 to 8 reflect the values of bits 7 to 0"
rbitfld.long 0x00 7. "Reserved_7,Reserved The write value should always be 0" "0,1"
newline
rbitfld.long 0x00 6. "GCAR,General Call Address Received Indicates that the address received from the bus is a general call address (H'00[n])" "0,1"
rbitfld.long 0x00 5. "STM,Slave Transmit Mode Indicates whether the current slave transmit mode is read or write" "0,1"
newline
bitfld.long 0x00 4. "SSR,Slave Stop Received A stop condition has been output on the bus" "0,1"
bitfld.long 0x00 3. "SDE,Slave Data Empty Indicates that data to be transmitted has been loaded into the shift register" "0,1"
newline
bitfld.long 0x00 2. "SDT,Slave Data Transmitted A byte of data has been transmitted to the bus" "0,1"
bitfld.long 0x00 1. "SDR,Slave Data Received A byte of data has been received from the bus and is ready for reading from the receive data register" "0,1"
newline
bitfld.long 0x00 0. "SAR,Slave Address Received Indicates that the slave has recognized its own address on the bus (defined by the contents of the slave address register[n])" "0,1"
group.long 0x0C++0x03
line.long 0x00 "ICMSR4,The status bits (bits 0 to 6[n]) in the master status register are cleared by writing 0 to the respective status bit positions"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved When these bits are read bits 31 to 24 23 to 16 and 15 to 8 reflect the values of bits 7 to 0"
rbitfld.long 0x00 7. "Reserved_7,Reserved The write value should always be 0" "0,1"
newline
bitfld.long 0x00 6. "MNR,Master NACK Received When this bit is set to 1 this bit indicates that the master has received a NACK response (the SDA line is high during the acknowledge cycle on the bus[n]) to either an address or data transmission" "0,1"
bitfld.long 0x00 5. "MAL,Master Arbitration Lost In a multi-master system when this bit is set to 1 it indicates that the master has lost arbitration to other masters on the bus" "0,1"
newline
bitfld.long 0x00 4. "MST,Master Stop Transmitted When this bit is set to 1 it indicates that the master has sent a STOP condition on the bus" "0,1"
bitfld.long 0x00 3. "MDE,Master Data Empty At the start of a byte data transmission the contents of the transmit data register are loaded into a shift register ready for transmitting on the bus" "0,1"
newline
bitfld.long 0x00 2. "MDT,Master Data Transmitted Byte data has been sent to the slave on the bus" "0,1"
bitfld.long 0x00 1. "MDR,Master Data Received Byte data has been received from the bus and is in the receive data register" "0,1"
newline
bitfld.long 0x00 0. "MAT,Master Address Transmitted The master has been transmitted the slave address byte of a data packet" "0,1"
group.long 0x10++0x03
line.long 0x00 "ICSIER4,"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved When these bits are read bits 31 to 24 23 to 16 and 15 to 8 reflect the values of bits 7 to 0"
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4. "SSRE,Slave Stop Received Interrupt Enable" "0: Disables the SSR interrupt,1: Enables the SSR interrupt"
bitfld.long 0x00 3. "SDEE,Slave Data Empty Interrupt Enable" "0: Disables the SDE interrupt,1: Enables the SDE interrupt"
newline
bitfld.long 0x00 2. "SDTE,Slave Data Transmitted Interrupt Enable" "0: Disables the SDT interrupt,1: Enables the SDT interrupt"
bitfld.long 0x00 1. "SDRE,Slave Data Received Interrupt Enable" "0: Disables the SDR interrupt,1: Enables the SDR interrupt"
newline
bitfld.long 0x00 0. "SARE,Slave Address Received Interrupt Enable" "0: Disables the SAR interrupt,1: Enables the SAR interrupt"
group.long 0x14++0x03
line.long 0x00 "ICMIER4,"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved When these bits are read bits 31 to 24 23 to 16 and 15 to 8 reflect the values of bits 7 to 0"
rbitfld.long 0x00 7. "Reserved_7,Reserved The write value should always be 0" "0,1"
newline
bitfld.long 0x00 6. "MNRE,Master NACK Received Interrupt Enable" "0: Disables the MNR interrupt,1: Enables the MNR interrupt"
bitfld.long 0x00 5. "MALE,Master Arbitration Lost Interrupt Enable" "0: Disables the MAL interrupt,1: Enables the MAL interrupt"
newline
bitfld.long 0x00 4. "MSTE,Master Stop Transmitted Interrupt Enable" "0: Disables the MST interrupt,1: Enables the MST interrupt"
bitfld.long 0x00 3. "MDEE,Master Data Empty Interrupt Enable" "0: Disables the MDE interrupt,1: Enables the MDE interrupt"
newline
bitfld.long 0x00 2. "MDTE,Master Data Transmitted Interrupt Enable" "0: Disables the MDT interrupt,1: Enables the MDT interrupt"
bitfld.long 0x00 1. "MDRE,Master Data Received Interrupt Enable" "0: Disables the MDR interrupt,1: Enables the MDR interrupt"
newline
bitfld.long 0x00 0. "MATE,Master Address Transmitted Interrupt Enable" "0: Disables the MAT interrupt,1: Enables the MAT interrupt"
group.long 0x18++0x03
line.long 0x00 "ICCCR4,"
hexmask.long.tbyte 0x00 9.--31. 1. "Reserved_9,Reserved The read value is always 0"
bitfld.long 0x00 3.--8. "SCGD,SCL Clock Generation Divider When operation is in master mode the SCL clock is generated from the internal clock by using SCGD as the ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0.--2. "CDF,Clock Division Factor The internal clock used in most blocks in the I2C module is a divided module clock" "0,1,2,3,4,5,6,7"
group.long 0x1C++0x03
line.long 0x00 "ICSAR4,"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved When these bits are read bits 31 to 24 23 to 16 and 15 to 8 reflect the values of bits 7 to 0"
rbitfld.long 0x00 7. "Reserved_7,Reserved The write value should always be 0" "0,1"
newline
hexmask.long.byte 0x00 0.--6. 1. "SADD0_6_0,Slave Address This is the unique 7-bit address allocated to the slave on the I2C bus"
group.long 0x20++0x03
line.long 0x00 "ICMAR4,"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved When these bits are read bits 31 to 24 23 to 16 and 15 to 8 reflect the values of bits 7 to 0"
hexmask.long.byte 0x00 1.--7. 1. "SADD1_6_0,Slave Address These bits are the address of the slave which the master communicates with"
newline
bitfld.long 0x00 0. "STM1,Slave Transfer Mode This bit specifies the mode in which the slave operates" "0,1"
group.long 0x24++0x03
line.long 0x00 "ICRXD_ICTXD4,"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved When these bits are read bits 31 to 24 23 to 16 and 15 to 8 reflect the values of bits 7 to 0"
hexmask.long.byte 0x00 0.--7. 1. "RXD_TXD,Read Receive Data Data received by master or slave"
group.long 0x28++0x03
line.long 0x00 "ICCCR24,Notes: 1"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved When these bits are read the value in bits 7 to 0 is set to bits 31 to 24 bits 23 to 16 and bits 15 to 8"
rbitfld.long 0x00 7. "Reserved_7,Reserved The write value should always be 0" "0,1"
newline
rbitfld.long 0x00 3.--6. "Reserved_3,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 2. "CDFD,CDF Disable When this bit is set to 1 the module clock is used for internal clocks except the clock filter" "0,1"
newline
bitfld.long 0x00 1. "HLSE,HIGH/LOW Separate Control Enable When this bit is set to 1 the SCGD setting is ignored and SCL is generated with the division ratio set by ICHPR during a high period and with the division ratio set by ICLPR during a low period" "0,1"
bitfld.long 0x00 0. "SME,SCL Mask Enable When this bit is set to 1 a change of internal SCL is ignored after an SCL external input pin changes during the time equal to the number of internal clock cycles specified by ICMPR" "0,1"
group.long 0x2C++0x03
line.long 0x00 "ICMPR4,"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved When these bits are read the value in bits 7 to 0 is set to bits 31 to 24 bits 23 to 16 and bits 15 to 8"
hexmask.long.byte 0x00 0.--7. 1. "SMD,SCL Mask Division When SME = 1 a change of internal SCL is ignored after the external SCL changes during the time equal to the number of internal clock cycles specified by SMD"
group.long 0x30++0x03
line.long 0x00 "ICHPR4,"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved The write value should always be 0"
hexmask.long.word 0x00 0.--15. 1. "SCHD,SCL HIGH Clock Division When HLSE is 1 and internal SCL is driven high the clock generated using the SCHD internal clock division ratio is output"
group.long 0x34++0x03
line.long 0x00 "ICLPR4,"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved The write value should always be 0"
hexmask.long.word 0x00 0.--15. 1. "SCLD,SCL LOW Clock Division When HLSE is 1 and internal SCL is driven low the clock generated using the SCLD internal clock division ratio is output"
group.long 0x38++0x03
line.long 0x00 "ICFBSCR4,Note: The delay time of the 1st data bit between SDA and SCL was calculated as below table"
hexmask.long 0x00 5.--31. 1. "Reserved_5,Reserved When these bits are read bits 31 to 24 23 to 16 and 15 to 8 reflect the values of bits 7 to 0"
bitfld.long 0x00 0.--4. "FBSC_4_0,Setting the delay time of the 1st data bit between SDA and SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x3C++0x03
line.long 0x00 "ICDMAER4,"
hexmask.long.byte 0x00 24.--31. 1. "MDMACTSZ,DMA Master Continuous mode Transfer Size Specify the number of transfer counts"
hexmask.long.byte 0x00 16.--23. 1. "RMDMATSZ,DMA Master Continuous Received mode 1unit Transfer Size register"
newline
hexmask.long.byte 0x00 8.--15. 1. "TMDMATSZ,DMA Master Continuous Transmitted mode 1unit Transfer Size register"
bitfld.long 0x00 7. "TMDMACE,DMA Master Continuous Transmitted Enable" "0: Disables DMA Continuous Transmitted mode,1: Enables DMA Continuous Transmitted mode"
newline
bitfld.long 0x00 6. "RMDMACE,DMA Master Continuous Received Enable" "0: Disables DMA Continuous Received mode,1: Enables DMA Continuous Received mode"
rbitfld.long 0x00 4.--5. "Reserved_4,Reserved The write value should always be 0" "0,1,2,3"
newline
bitfld.long 0x00 3. "RSDMAE,DMA Slave Received Enable" "0: Disables DMA Slave Received Mode,1: Enables DMA Slave Received Mode"
bitfld.long 0x00 2. "TSDMAE,DMA Slave Transmitted Enable" "0: Disables DMA Slave Transmitted Mode,1: Enables DMA Slave Transmitted Mode"
newline
bitfld.long 0x00 1. "RMDMAE,DMA Master Received Enable" "0: Disables DMA Master Received Mode,1: Enables DMA Master Received Mode"
bitfld.long 0x00 0. "TMDMAE,DMA Master Transmitted Enable" "0: Disables DMA Master Transmitted Mode,1: Enables DMA Master Transmitted Mode"
tree.end
tree "I2C_INST_5"
base ad:0xE66E0000
group.long 0x00++0x03
line.long 0x00 "ICSCR5,"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved When these bits are read bits 31 to 24 23 to 16 and 15 to 8 reflect the values of bits 7 to 0"
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4. "SCSS,Slave Clock Stretch Select This bit is used to select the timing of Clock Stretch" "0: Clock Stretch is in front of Acknowledgement,1: Clock Stretch is next to Non Acknowledgement"
bitfld.long 0x00 3. "SDBS,Slave Data Buffer Select This bit is used to select the data buffer" "0: Setting prohibited,1: Single-buffer mode"
newline
bitfld.long 0x00 2. "SIE,Slave Interface Enable This bit must be set for the slave operation" "0,1"
bitfld.long 0x00 1. "GCAE,General Call Acknowledgement Enable When slave devices are to issue an acknowledgement in response to a general call address sent from a master this bit must be set to 1" "0,1"
newline
bitfld.long 0x00 0. "FNA,Forced Non Acknowledgement In the slave receive mode the level of this bit is sent to the transmitting device as the acknowledge signal" "0,1"
group.long 0x04++0x03
line.long 0x00 "ICMCR5,"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved When these bits are read bits 31 to 24 23 to 16 and 15 to 8 reflect the values of bits 7 to 0"
bitfld.long 0x00 7. "MDBS,Master Data Buffer Select This bit is used to select the data buffer mode" "0: Setting prohibited,1: Single-buffer mode"
newline
bitfld.long 0x00 6. "FSCL,Forced SCL This bit controls the status of the I2C_SCL pin (reading reflects the current status of the I2C_SCL pin[n])" "0,1"
bitfld.long 0x00 5. "FSDA,Forced SDA This bit controls the status of the I2C_SDA pin (reading reflects the busy status level on the I2C bus[n])" "0,1"
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bitfld.long 0x00 4. "OBPC,Override Bus Pin Control When this bit is set to 1 the FSDA and FSCL bits in this register control SDA and SCL directly" "0,1"
bitfld.long 0x00 3. "MIE,Master Interface Enable When this bit is set to 1 the master interface is enabled" "0,1"
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bitfld.long 0x00 2. "TSBE,Start Byte Transmission Enable The write value for this bit should always be 0" "0,1"
bitfld.long 0x00 1. "FSB,Forced Stop onto the Bus When this bit is set to 1 the master transmits a STOP condition on the bus at the end of the current transfer" "0,1"
newline
bitfld.long 0x00 0. "ESG,Enable Start Generation When this bit is set to 1 the master starts transmission of a data packet" "0,1"
group.long 0x08++0x03
line.long 0x00 "ICSSR5,Bits 0 to 4 among the status bits in the slave status register are cleared by writing 0 to the respective status bit positions"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved When these bits are read bits 31 to 24 23 to 16 and 15 to 8 reflect the values of bits 7 to 0"
rbitfld.long 0x00 7. "Reserved_7,Reserved The write value should always be 0" "0,1"
newline
rbitfld.long 0x00 6. "GCAR,General Call Address Received Indicates that the address received from the bus is a general call address (H'00[n])" "0,1"
rbitfld.long 0x00 5. "STM,Slave Transmit Mode Indicates whether the current slave transmit mode is read or write" "0,1"
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bitfld.long 0x00 4. "SSR,Slave Stop Received A stop condition has been output on the bus" "0,1"
bitfld.long 0x00 3. "SDE,Slave Data Empty Indicates that data to be transmitted has been loaded into the shift register" "0,1"
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bitfld.long 0x00 2. "SDT,Slave Data Transmitted A byte of data has been transmitted to the bus" "0,1"
bitfld.long 0x00 1. "SDR,Slave Data Received A byte of data has been received from the bus and is ready for reading from the receive data register" "0,1"
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bitfld.long 0x00 0. "SAR,Slave Address Received Indicates that the slave has recognized its own address on the bus (defined by the contents of the slave address register[n])" "0,1"
group.long 0x0C++0x03
line.long 0x00 "ICMSR5,The status bits (bits 0 to 6[n]) in the master status register are cleared by writing 0 to the respective status bit positions"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved When these bits are read bits 31 to 24 23 to 16 and 15 to 8 reflect the values of bits 7 to 0"
rbitfld.long 0x00 7. "Reserved_7,Reserved The write value should always be 0" "0,1"
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bitfld.long 0x00 6. "MNR,Master NACK Received When this bit is set to 1 this bit indicates that the master has received a NACK response (the SDA line is high during the acknowledge cycle on the bus[n]) to either an address or data transmission" "0,1"
bitfld.long 0x00 5. "MAL,Master Arbitration Lost In a multi-master system when this bit is set to 1 it indicates that the master has lost arbitration to other masters on the bus" "0,1"
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bitfld.long 0x00 4. "MST,Master Stop Transmitted When this bit is set to 1 it indicates that the master has sent a STOP condition on the bus" "0,1"
bitfld.long 0x00 3. "MDE,Master Data Empty At the start of a byte data transmission the contents of the transmit data register are loaded into a shift register ready for transmitting on the bus" "0,1"
newline
bitfld.long 0x00 2. "MDT,Master Data Transmitted Byte data has been sent to the slave on the bus" "0,1"
bitfld.long 0x00 1. "MDR,Master Data Received Byte data has been received from the bus and is in the receive data register" "0,1"
newline
bitfld.long 0x00 0. "MAT,Master Address Transmitted The master has been transmitted the slave address byte of a data packet" "0,1"
group.long 0x10++0x03
line.long 0x00 "ICSIER5,"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved When these bits are read bits 31 to 24 23 to 16 and 15 to 8 reflect the values of bits 7 to 0"
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4. "SSRE,Slave Stop Received Interrupt Enable" "0: Disables the SSR interrupt,1: Enables the SSR interrupt"
bitfld.long 0x00 3. "SDEE,Slave Data Empty Interrupt Enable" "0: Disables the SDE interrupt,1: Enables the SDE interrupt"
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bitfld.long 0x00 2. "SDTE,Slave Data Transmitted Interrupt Enable" "0: Disables the SDT interrupt,1: Enables the SDT interrupt"
bitfld.long 0x00 1. "SDRE,Slave Data Received Interrupt Enable" "0: Disables the SDR interrupt,1: Enables the SDR interrupt"
newline
bitfld.long 0x00 0. "SARE,Slave Address Received Interrupt Enable" "0: Disables the SAR interrupt,1: Enables the SAR interrupt"
group.long 0x14++0x03
line.long 0x00 "ICMIER5,"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved When these bits are read bits 31 to 24 23 to 16 and 15 to 8 reflect the values of bits 7 to 0"
rbitfld.long 0x00 7. "Reserved_7,Reserved The write value should always be 0" "0,1"
newline
bitfld.long 0x00 6. "MNRE,Master NACK Received Interrupt Enable" "0: Disables the MNR interrupt,1: Enables the MNR interrupt"
bitfld.long 0x00 5. "MALE,Master Arbitration Lost Interrupt Enable" "0: Disables the MAL interrupt,1: Enables the MAL interrupt"
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bitfld.long 0x00 4. "MSTE,Master Stop Transmitted Interrupt Enable" "0: Disables the MST interrupt,1: Enables the MST interrupt"
bitfld.long 0x00 3. "MDEE,Master Data Empty Interrupt Enable" "0: Disables the MDE interrupt,1: Enables the MDE interrupt"
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bitfld.long 0x00 2. "MDTE,Master Data Transmitted Interrupt Enable" "0: Disables the MDT interrupt,1: Enables the MDT interrupt"
bitfld.long 0x00 1. "MDRE,Master Data Received Interrupt Enable" "0: Disables the MDR interrupt,1: Enables the MDR interrupt"
newline
bitfld.long 0x00 0. "MATE,Master Address Transmitted Interrupt Enable" "0: Disables the MAT interrupt,1: Enables the MAT interrupt"
group.long 0x18++0x03
line.long 0x00 "ICCCR5,"
hexmask.long.tbyte 0x00 9.--31. 1. "Reserved_9,Reserved The read value is always 0"
bitfld.long 0x00 3.--8. "SCGD,SCL Clock Generation Divider When operation is in master mode the SCL clock is generated from the internal clock by using SCGD as the ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0.--2. "CDF,Clock Division Factor The internal clock used in most blocks in the I2C module is a divided module clock" "0,1,2,3,4,5,6,7"
group.long 0x1C++0x03
line.long 0x00 "ICSAR5,"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved When these bits are read bits 31 to 24 23 to 16 and 15 to 8 reflect the values of bits 7 to 0"
rbitfld.long 0x00 7. "Reserved_7,Reserved The write value should always be 0" "0,1"
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hexmask.long.byte 0x00 0.--6. 1. "SADD0_6_0,Slave Address This is the unique 7-bit address allocated to the slave on the I2C bus"
group.long 0x20++0x03
line.long 0x00 "ICMAR5,"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved When these bits are read bits 31 to 24 23 to 16 and 15 to 8 reflect the values of bits 7 to 0"
hexmask.long.byte 0x00 1.--7. 1. "SADD1_6_0,Slave Address These bits are the address of the slave which the master communicates with"
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bitfld.long 0x00 0. "STM1,Slave Transfer Mode This bit specifies the mode in which the slave operates" "0,1"
group.long 0x24++0x03
line.long 0x00 "ICRXD_ICTXD5,"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved When these bits are read bits 31 to 24 23 to 16 and 15 to 8 reflect the values of bits 7 to 0"
hexmask.long.byte 0x00 0.--7. 1. "RXD_TXD,Read Receive Data Data received by master or slave"
group.long 0x28++0x03
line.long 0x00 "ICCCR25,Notes: 1"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved When these bits are read the value in bits 7 to 0 is set to bits 31 to 24 bits 23 to 16 and bits 15 to 8"
rbitfld.long 0x00 7. "Reserved_7,Reserved The write value should always be 0" "0,1"
newline
rbitfld.long 0x00 3.--6. "Reserved_3,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 2. "CDFD,CDF Disable When this bit is set to 1 the module clock is used for internal clocks except the clock filter" "0,1"
newline
bitfld.long 0x00 1. "HLSE,HIGH/LOW Separate Control Enable When this bit is set to 1 the SCGD setting is ignored and SCL is generated with the division ratio set by ICHPR during a high period and with the division ratio set by ICLPR during a low period" "0,1"
bitfld.long 0x00 0. "SME,SCL Mask Enable When this bit is set to 1 a change of internal SCL is ignored after an SCL external input pin changes during the time equal to the number of internal clock cycles specified by ICMPR" "0,1"
group.long 0x2C++0x03
line.long 0x00 "ICMPR5,"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved When these bits are read the value in bits 7 to 0 is set to bits 31 to 24 bits 23 to 16 and bits 15 to 8"
hexmask.long.byte 0x00 0.--7. 1. "SMD,SCL Mask Division When SME = 1 a change of internal SCL is ignored after the external SCL changes during the time equal to the number of internal clock cycles specified by SMD"
group.long 0x30++0x03
line.long 0x00 "ICHPR5,"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved The write value should always be 0"
hexmask.long.word 0x00 0.--15. 1. "SCHD,SCL HIGH Clock Division When HLSE is 1 and internal SCL is driven high the clock generated using the SCHD internal clock division ratio is output"
group.long 0x34++0x03
line.long 0x00 "ICLPR5,"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved The write value should always be 0"
hexmask.long.word 0x00 0.--15. 1. "SCLD,SCL LOW Clock Division When HLSE is 1 and internal SCL is driven low the clock generated using the SCLD internal clock division ratio is output"
group.long 0x38++0x03
line.long 0x00 "ICFBSCR5,Note: The delay time of the 1st data bit between SDA and SCL was calculated as below table"
hexmask.long 0x00 5.--31. 1. "Reserved_5,Reserved When these bits are read bits 31 to 24 23 to 16 and 15 to 8 reflect the values of bits 7 to 0"
bitfld.long 0x00 0.--4. "FBSC_4_0,Setting the delay time of the 1st data bit between SDA and SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x3C++0x03
line.long 0x00 "ICDMAER5,"
hexmask.long.byte 0x00 24.--31. 1. "MDMACTSZ,DMA Master Continuous mode Transfer Size Specify the number of transfer counts"
hexmask.long.byte 0x00 16.--23. 1. "RMDMATSZ,DMA Master Continuous Received mode 1unit Transfer Size register"
newline
hexmask.long.byte 0x00 8.--15. 1. "TMDMATSZ,DMA Master Continuous Transmitted mode 1unit Transfer Size register"
bitfld.long 0x00 7. "TMDMACE,DMA Master Continuous Transmitted Enable" "0: Disables DMA Continuous Transmitted mode,1: Enables DMA Continuous Transmitted mode"
newline
bitfld.long 0x00 6. "RMDMACE,DMA Master Continuous Received Enable" "0: Disables DMA Continuous Received mode,1: Enables DMA Continuous Received mode"
rbitfld.long 0x00 4.--5. "Reserved_4,Reserved The write value should always be 0" "0,1,2,3"
newline
bitfld.long 0x00 3. "RSDMAE,DMA Slave Received Enable" "0: Disables DMA Slave Received Mode,1: Enables DMA Slave Received Mode"
bitfld.long 0x00 2. "TSDMAE,DMA Slave Transmitted Enable" "0: Disables DMA Slave Transmitted Mode,1: Enables DMA Slave Transmitted Mode"
newline
bitfld.long 0x00 1. "RMDMAE,DMA Master Received Enable" "0: Disables DMA Master Received Mode,1: Enables DMA Master Received Mode"
bitfld.long 0x00 0. "TMDMAE,DMA Master Transmitted Enable" "0: Disables DMA Master Transmitted Mode,1: Enables DMA Master Transmitted Mode"
tree.end
tree.end
tree "MSIOF"
tree "MSIOF_INST_0"
base ad:0xE6E90000
group.long 0x00++0x03
line.long 0x00 "SITMDR10,SITMDR1 is a 32-bit readable/writable register that specifies the MSIOF transmit mode"
bitfld.long 0x00 31. "TRMD,Transfer Mode Selects the transfer mode" "0: Slave mode,1: Master mode"
bitfld.long 0x00 30. "PCON,Transfer Signal Connection" "0: Setting prohibited,1: MSIOF_SCK and MSIOF_SYNC are used as common"
newline
bitfld.long 0x00 28.--29. "SYNCMD,SYNC Mode These bits specify the mode for the MSIOF_SYNC signal" "0: Frame start synchronization,1: Reserved,2: Level mode/SPI,3: L/R mode"
bitfld.long 0x00 26.--27. "SYNCCH,Synchronization Signal Channel Select These bits are valid only in master mode" "0: The frame synchronization signal output at,1: The frame synchronization signal output at,2: The frame synchronization signal output at,3: Setting prohibited"
newline
bitfld.long 0x00 25. "SYNCAC,MSIOF_SYNC Polarity" "0: Active-high signal in synchronization pulse or,1: Active-low signal in synchronization pulse or"
bitfld.long 0x00 24. "BITLSB,MSB/LSB First" "0: MSB first,1: LSB first"
newline
rbitfld.long 0x00 23. "Reserved_23,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 20.--22. "DTDL,Data Pin Bit Delay for MSIOF_SYNC Pin The value specified with TXDIZ in SICTR is output during transmission" "0: No bit delay,1: 1-clock-cycle delay,2: 2-clock-cycle delay,?,?,5: 0.5-clock-cycle delay,6: 1.5-clock-cycle delay Other than above,?..."
newline
rbitfld.long 0x00 19. "Reserved_19,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 16.--18. "SYNCDL,Frame Synchronization Signal Timing Delay These bits extend the transmit frame synchronization signal" "0: No bit delay,1: 1-clock-cycle delay,2: 2-clock-cycle delay,3: 3-clock-cycle delay,?,5: 0.5-clock-cycle delay,6: 1.5-clock-cycle delay Other than above,?..."
newline
hexmask.long.word 0x00 4.--15. 1. "Reserved_4,Reserved These bits are always read as 0"
bitfld.long 0x00 2.--3. "FLD,Frame Synchronization Signal Interval Specify the minimum idle time between frames in the number of serial clock cycles" "0: 0-clock-cycle delay,1: 1-clock-cycle delay,2: 2-clock-cycle delay,3: 3-clock-cycle delay"
newline
rbitfld.long 0x00 1. "Reserved_1,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 0. "TXSTP,Transmission Stop" "0: Setting prohibited,1: Stop a frame from starting to transmit until"
group.long 0x04++0x03
line.long 0x00 "SITMDR20,SITMDR2 is a 32-bit readable/writable register that specifies the MSIOF transmit mode"
rbitfld.long 0x00 31. "Reserved_31,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 30. "GRP,Group Count" "0: Group count 1,1: Group count 2"
newline
rbitfld.long 0x00 29. "Reserved_29,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 24.--28. "BITLEN1,Data Size (8 to 32 bits) The word size (bits) of Group 1 is set to the value specified in these bits + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 22.--23. "Reserved_22,Reserved These bits are always read as 0" "0,1,2,3"
bitfld.long 0x00 16.--21. "WDLEN1,Word Count (1 to 64 words) The word count of Group 1 is set to WDLEN1 + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.long.word 0x00 0.--15. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x08++0x03
line.long 0x00 "SITMDR30,SITMDR3 is a 32-bit readable/writable register that specifies the MSIOF transmit mode"
rbitfld.long 0x00 29.--31. "Reserved_29,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24.--28. "BITLEN2,Word Size (8 to 32 bits) The word size (bits) of Group 2 is set to the value specified in these bits + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 22.--23. "Reserved_22,Reserved These bits are always read as 0" "0,1,2,3"
bitfld.long 0x00 16.--21. "WDLEN2,Word Count (1 to 64 words) The word count of Group 2 is set to WDLEN2 + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.long.word 0x00 0.--15. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x10++0x03
line.long 0x00 "SIRMDR10,SIRMDR1 is a 32-bit readable/writable register that specifies the MSIOF receive mode"
bitfld.long 0x00 31. "TRMD,Transfer Mode Selects the transfer mode" "0,1"
rbitfld.long 0x00 30. "Reserved_30,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 28.--29. "SYNCMD,SYNC Mode The mode setting in these bits should be the same as that in SITMDR1.SYNCMD" "0: Frame start synchronization,1: Reserved,2: Level mode/SPI,3: L/R mode"
rbitfld.long 0x00 26.--27. "Reserved_26,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 25. "SYNCAC,SYNC Polarity" "0: Active-high signal in synchronization pulse or,1: Active-low signal in synchronization pulse or"
bitfld.long 0x00 24. "BITLSB,MSB/LSB First" "0: MSB first,1: LSB first"
newline
rbitfld.long 0x00 23. "Reserved_23,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 20.--22. "DTDL,Data Pin Bit Delay for MSIOF_SYNC Pin" "0: No bit delay,1: 1-clock-cycle delay,2: 2-clock-cycle delay Other than above,?..."
newline
rbitfld.long 0x00 19. "Reserved_19,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 16.--18. "SYNCDL,MSIOF_SYNC Timing Delay These bits should always be set to B000" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x00 0.--15. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x14++0x03
line.long 0x00 "SIRMDR20,SIRMDR2 is a 32-bit readable/writable register that specifies the MSIOF receive mode"
rbitfld.long 0x00 31. "Reserved_31,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 30. "GRP,Group Count" "0: Group count 1,1: Group count 2 When using reception in"
newline
rbitfld.long 0x00 29. "Reserved_29,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 24.--28. "BITLEN1,Word Size (8 to 32 bits) The word size (bits) of Group 1 is set to the value specified in these bits + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 22.--23. "Reserved_22,Reserved These bits are always read as 0" "0,1,2,3"
bitfld.long 0x00 16.--21. "WDLEN1,Word Count (1 to 64 words) The word count of Group 1 is set to WDLEN1 + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.long.word 0x00 0.--15. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x18++0x03
line.long 0x00 "SIRMDR30,SIRMDR3 is a 32-bit readable/writable register that specifies the MSIOF receive mode"
rbitfld.long 0x00 29.--31. "Reserved_29,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24.--28. "BITLEN2,Word Size (8 to 32 bits) The word size (bits) of Group 2 is set to the value specified in these bits + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 22.--23. "Reserved_22,Reserved These bits are always read as 0" "0,1,2,3"
bitfld.long 0x00 16.--21. "WDLEN2,Word Count (1 to 64 words) The word count of Group 2 is set to WDLEN2 + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.long.word 0x00 0.--15. 1. "Reserved_0,Reserved These bits are always read as 0"
group.word 0x20++0x01
line.word 0x00 "SITSCR0,SITSCR is a 16-bit readable/writable register that specifies the conditions for generating transmit serial clock in master mode"
bitfld.word 0x00 14.--15. "MSSEL,Master Clock Source Select The master clock is the clock input to the baud rate generator" "0,1,2,3"
bitfld.word 0x00 13. "MSIMM,Master Clock Direct Select" "0: Selects the clock output from the baud rate,1: Setting prohibited"
newline
bitfld.word 0x00 8.--12. "BRPS,Prescaler Setting These bits specify the master clock (MSO?) division ratio in the count value of the prescaler in the baud rate generator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rbitfld.word 0x00 3.--7. "Reserved_3,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 0.--2. "BRDV,Baud Rate Generator's Division Ratio These bits specify the frequency division ratio for the output stage of the baud rate generator" "0: Prescaler output ? 1/2,1: Prescaler output ? 1/4,2: Prescaler output ? 1/8,3: Prescaler output ? 1/16,4: Prescaler output ? 1/32,5: Setting prohibited,6: Setting prohibited,7: Prescaler output ? 1/1"
group.long 0x28++0x03
line.long 0x00 "SICTR0,SICTR is a 32-bit readable/writable register that specifies the MSIOF operating state"
bitfld.long 0x00 30.--31. "TSCKIZ,Transmit Clock Input/output Polarity Select in SPI Mode When Transmission is Disabled When SPI mode is not used these bits must always be set to B00" "0: Inputs MSIOF_SCK when transmission is disabled,1: Setting prohibited,2: Inputs 0 through MSIOF_SCK when transmission is,3: Inputs 1 through MSIOF_SCK when transmission is"
bitfld.long 0x00 28.--29. "RSCKIZ,Receive Clock Polarity Select in SPI Mode Set the same value as the value specified by the TSCKIZ bits" "0,1,2,3"
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bitfld.long 0x00 27. "TEDG,Transmit Timing" "0: Outputs transmit data at the rising edge of the,1: Outputs transmit data at the falling edge of.."
bitfld.long 0x00 26. "REDG,Receive Timing" "0: Samples receive data at the falling edge of the,1: Samples receive data at the rising edge of the"
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rbitfld.long 0x00 24.--25. "Reserved_24,Reserved These bits are always read as 0" "0,1,2,3"
bitfld.long 0x00 22.--23. "TXDIZ,Pin Output When Transmission is Disabled These bits specify the MSIOF_TXD pin output state when transmission is disabled" "0: Outputs 0,1: Outputs 1,2: Setting prohibited,3: Setting prohibited"
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rbitfld.long 0x00 16.--21. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 15. "TSCKE,Transmit Serial Clock Output Enable This bit is valid in master mode" "0: Does not output MSIOF_SCK.(Outputs the value,1: Outputs MSIOF_SCK"
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bitfld.long 0x00 14. "TFSE,Transmit Frame Synchronization Signal Output Enable This bit is valid in master mode" "0: Does not output MSIOF_SYNC.(Outputs the value,1: Outputs MSIOF_SYNC"
bitfld.long 0x00 13. "RSCKE,Receive Serial Clock Output Enable The write value should always be 0" "0,1"
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bitfld.long 0x00 12. "RFSE,Receive Frame Synchronization Signal Output Enable The write value should always be 0" "0,1"
rbitfld.long 0x00 10.--11. "Reserved_10,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 9. "TXE,Transmit Enable When this bit is set to 1 the MSIOF starts data transmission from the beginning of the next frame (at the rising edge of the frame synchronization signal)" "0: Does not output MSIOF_TXD.(Outputs the value,1: Outputs MSIOF_TXD"
bitfld.long 0x00 8. "RXE,Receive Enable When this bit is set to 1 the MSIOF starts data reception from the beginning of the next frame (at the rising edge of the frame synchronization signal)" "0: Data is not received through MSIOF_RXD,1: Data can be received through MSIOF_RXD"
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rbitfld.long 0x00 2.--7. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 1. "TXRST,Transmit Reset When value 1 set to this bit becomes valid the MSIOF immediately sets transmit data through the MSIOF_TXD pin to 0 and initializes the transmit data registers and transmit-related status" "0: Transmit operation reset is completed,1: Transmit operation is being reset"
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bitfld.long 0x00 0. "RXRST,Receive Reset When value 1 set to this bit becomes valid the MSIOF immediately disables reception through the MSIOF_RXD pin and initializes the receive data registers and receive-related status" "0: Receive operation reset is completed,1: Receive operation is being reset"
group.long 0x30++0x03
line.long 0x00 "SIFCTR0,SIFCTR is a 32-bit readable/writable register that indicates the area available for the transmit/receive FIFO transfer"
bitfld.long 0x00 29.--31. "TFWM,Transmit FIFO Watermark A transfer request of the transmit FIFO is issued by the TDREQE bit in SIIER" "0: Issues a transfer request when 64 stages of the,1: Issues a transfer request when 32 or more..,2: Issues a transfer request when 24 or more..,3: Issues a transfer request when 16 or more..,4: Issues a transfer request when 12 or more..,5: Issues a transfer request when 8 or more stages,6: Issues a transfer request when 4 or more stages,7: Issues a transfer request when 1 or more stages"
rbitfld.long 0x00 27.--28. "Reserved_27,Reserved These bits are always read as 0" "0,1,2,3"
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hexmask.long.byte 0x00 20.--26. 1. "TFUA,Transmit FIFO Usable Area Indicate the number of words that can be transferred by the CPU or DMAC as B'000 0000 (full) to B'100 0000 (empty)"
rbitfld.long 0x00 16.--19. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 13.--15. "RFWM,Receive FIFO Watermark A transfer request of the receive FIFO is issued by the RDREQE bit in SIIER" "0: Issues a transfer request when 1 stage or more,1: Issues a transfer request when 4 or more stages,2: Issues a transfer request when 8 or more stages,3: Issues a transfer request when 16 or more..,4: Issues a transfer request when 32 or more..,5: Issues a transfer request when 64 or more..,6: Issues a transfer request when 128 or more,7: Issues a transfer request when 256 stages of.."
hexmask.long.word 0x00 4.--12. 1. "RFUA,Receive FIFO Usable Area Indicate the number of words that can be transferred by the CPU or DMAC as B'0 0000 0000 (empty) to B'1 0000 0000 (full)"
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rbitfld.long 0x00 0.--3. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x40++0x03
line.long 0x00 "SISTR0,Each bit in SISTR becomes an MSIOF interrupt source when the corresponding bit in SIIER is set to 1"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved These bits are always read as 0" "0,1,2,3"
bitfld.long 0x00 29. "TFEMP,Transmit FIFO Empty This bit is set to 1 when the TXE bit in SICTR is 1 and transmit FIFO is empty" "0: Transmit FIFO is not empty,1: Transmit FIFO is empty"
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rbitfld.long 0x00 28. "TDREQ,Transmit Data Transfer Request This bit is set when the empty space in the transmit FIFO exceeds the size specified by the TFWM bits in SIFCTR" "0: The size of empty space in the transmit FIFO..,1: The size of empty space in the transmit FIFO.."
rbitfld.long 0x00 24.--27. "Reserved_24,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 23. "TEOF,Frame Transmission End This bit is set when one-frame data transmission is completed" "0: One-frame transmission end is not detected,1: One-frame transmission end is detected"
rbitfld.long 0x00 22. "Reserved_22,Reserved This bit is always read as 0" "0,1"
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bitfld.long 0x00 21. "TFSERR,Transmit Frame Synchronization Error This bit is set when the next transmit frame synchronization timing arrives before the previous data transmission has been completed" "0: No transmit frame synchronization error has,1: A transmit frame synchronization error has"
bitfld.long 0x00 20. "TFOVF,Transmit FIFO Overflow A transmit FIFO overflow means that there has been an attempt to write to SITFDR when the transmit FIFO is full" "0: No transmit FIFO overflow has occurred,1: A transmit FIFO overflow has occurred"
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bitfld.long 0x00 19. "TFUDF,Transmit FIFO Underflow A transmit FIFO underflow means that loading for transmission has occurred when the transmit FIFO is empty" "0: No transmit FIFO underflow has occurred,1: A transmit FIFO underflow has occurred"
rbitfld.long 0x00 14.--18. "Reserved_14,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 13. "RFFUL,Receive FIFO Full This bit is valid when the RXE bit in SICTR is 1" "0: Receive FIFO is not full,1: Receive FIFO is full"
rbitfld.long 0x00 12. "RDREQ,Receive Data Transfer Request This bit is set when the valid data space in the receive FIFO exceeds the size specified by the RFWM bits in SIFCTR" "0: The size of valid data space in the receive..,1: The size of valid data space in the receive.."
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rbitfld.long 0x00 8.--11. "Reserved_8,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 7. "REOF,Frame Reception End The MSIOF issues the frame reception end flag upon completion of one-frame data reception" "0: One-frame reception end is not detected,1: One-frame reception end is detected"
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rbitfld.long 0x00 6. "Reserved_6,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 5. "RFSERR,Receive Frame Synchronization Error A receive frame synchronization error occurs when the next receive frame synchronization timing arrives before the previous data reception has been completed" "0: No receive frame synchronization error has,1: A receive frame synchronization error has.."
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bitfld.long 0x00 4. "RFUDF,Receive FIFO Underflow A receive FIFO underflow means that reading of SIRFDR has occurred when the receive FIFO is empty" "0: No receive FIFO underflow has occurred,1: A receive FIFO underflow has occurred"
bitfld.long 0x00 3. "RFOVF,Receive FIFO Overflow A receive FIFO overflow means that writing has been caused by receiving operation when the receive FIFO is full" "0: No receive FIFO overflow has occurred,1: A receive FIFO overflow has occurred"
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eventfld.long 0x00 0.--2. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
group.long 0x44++0x03
line.long 0x00 "SIIER0,"
bitfld.long 0x00 31. "TDMAE,Transmit Data DMA Transfer Request Enable Specifies whether to send an interrupt as an interrupt request to the CPU or a transfer request to the DMAC" "0: Sends an interrupt request to the CPU,1: Sends a DMA transfer request to the DMAC"
rbitfld.long 0x00 30. "Reserved_30,Reserved This bit is always read as 0" "0,1"
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bitfld.long 0x00 29. "TFEMPE,Transmit FIFO Empty Enable" "0: Disables interrupts due to transmit FIFO empty,1: Enables interrupts due to transmit FIFO empty"
bitfld.long 0x00 28. "TDREQE,Transmit Data Transfer Request Enable" "0: Disables interrupts due to transmit data,1: Enables interrupts due to transmit data.."
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rbitfld.long 0x00 24.--27. "Reserved_24,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 23. "TEOFE,Frame Transmission End Enable" "0: Disables a frame transmission end interrupt,1: Enables a frame transmission end interrupt"
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rbitfld.long 0x00 22. "Reserved_22,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 21. "TFSERRE,Transmit Frame Synchronization Error Enable" "0: Disables interrupts due to transmit frame,1: Enables interrupts due to transmit frame"
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bitfld.long 0x00 20. "TFOVFE,Transmit FIFO Overflow Enable" "0: Disables interrupts due to transmit FIFO..,1: Enables interrupts due to transmit FIFO.."
bitfld.long 0x00 19. "TFUDFE,Transmit FIFO Underflow Enable" "0: Disables interrupts due to transmit FIFO..,1: Enables interrupts due to transmit FIFO.."
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rbitfld.long 0x00 16.--18. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 15. "RDMAE,Receive Data DMA Transfer Request Enable Specifies whether to send an interrupt as an interrupt request to the CPU or a transfer request to the DMAC" "0: Sends an interrupt request to the CPU,1: Sends a DMA transfer request to the DMAC"
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rbitfld.long 0x00 14. "Reserved_14,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 13. "RFFULE,Receive FIFO Full Enable" "0: Disables interrupts due to receive FIFO full,1: Enables interrupts due to receive FIFO full"
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bitfld.long 0x00 12. "RDREQE,Receive Data Transfer Request Enable" "0: Disables interrupts due to receive data..,1: Enables interrupts due to receive data transfer"
rbitfld.long 0x00 8.--11. "Reserved_8,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 7. "REOFE,Frame Reception End Enable" "0: Disables a frame reception end interrupt,1: Enables a frame reception end interrupt"
rbitfld.long 0x00 6. "Reserved_6,Reserved This bit is always read as 0" "0,1"
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bitfld.long 0x00 5. "RFSERRE,Receive Frame Synchronization Error Enable" "0: Disables interrupts due to receive frame,1: Enables interrupts due to receive frame"
bitfld.long 0x00 4. "RFUDFE,Receive FIFO Underflow Enable" "0: Disables interrupts due to receive FIFO..,1: Enables interrupts due to receive FIFO.."
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bitfld.long 0x00 3. "RFOVFE,Receive FIFO Overflow Enable" "0: Disables interrupts due to receive FIFO..,1: Enables interrupts due to receive FIFO overflow"
rbitfld.long 0x00 0.--2. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
group.long 0x50++0x03
line.long 0x00 "SITFDR0,SITFDR is a 32/16/8-bit write-only register that specifies the transmit FIFO data of the MSIOF"
hexmask.long.word 0x00 16.--31. 1. "SITFD1,These bits specify the upper 16 bits of the FIFO data to be output through MSIOF_TXD"
hexmask.long.word 0x00 0.--15. 1. "SITFD2,These bits specify the lower 16 bits of the FIFO data to be output through MSIOF_TXD"
group.long 0x50++0x03
line.long 0x00 "SITFDR0__16_L,SITFDR is a 32/16/8-bit write-only register that specifies the transmit FIFO data of the MSIOF"
hexmask.long.word 0x00 16.--31. 1. "Reserved0,Reserved"
hexmask.long.word 0x00 0.--15. 1. "SITFD2,These bits specify the lower 16 bits of the FIFO data to be output through MSIOF_TXD"
group.long 0x50++0x03
line.long 0x00 "SITFDR0__16_H,SITFDR is a 32/16/8-bit write-only register that specifies the transmit FIFO data of the MSIOF"
hexmask.long.word 0x00 16.--31. 1. "SITFD1,These bits specify the upper 16 bits of the FIFO data to be output through MSIOF_TXD"
hexmask.long.word 0x00 0.--15. 1. "Reserved1,Reserved"
group.long 0x50++0x03
line.long 0x00 "SITFDR0__8_LL,SITFDR is a 32/16/8-bit write-only register that specifies the transmit FIFO data of the MSIOF"
hexmask.long.word 0x00 16.--31. 1. "Reserved0,Reserved"
hexmask.long.byte 0x00 8.--15. 1. "Reserved1,Reserved"
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hexmask.long.byte 0x00 0.--7. 1. "SITFD2,These bits specify the lower 16 bits of the FIFO data to be output through MSIOF_TXD"
group.long 0x50++0x03
line.long 0x00 "SITFDR0__8_LH,SITFDR is a 32/16/8-bit write-only register that specifies the transmit FIFO data of the MSIOF"
hexmask.long.word 0x00 16.--31. 1. "Reserved0,Reserved"
hexmask.long.byte 0x00 8.--15. 1. "SITFD2,These bits specify the lower 16 bits of the FIFO data to be output through MSIOF_TXD"
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hexmask.long.byte 0x00 0.--7. 1. "Reserved1,Reserved"
group.long 0x50++0x03
line.long 0x00 "SITFDR0__8_HL,SITFDR is a 32/16/8-bit write-only register that specifies the transmit FIFO data of the MSIOF"
hexmask.long.byte 0x00 24.--31. 1. "Reserved0,Reserved"
hexmask.long.byte 0x00 16.--23. 1. "SITFD1,These bits specify the upper 16 bits of the FIFO data to be output through MSIOF_TXD"
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hexmask.long.word 0x00 0.--15. 1. "Reserved1,Reserved"
group.long 0x50++0x03
line.long 0x00 "SITFDR0__8_HH,SITFDR is a 32/16/8-bit write-only register that specifies the transmit FIFO data of the MSIOF"
hexmask.long.byte 0x00 24.--31. 1. "SITFD1,These bits specify the upper 16 bits of the FIFO data to be output through MSIOF_TXD"
hexmask.long.byte 0x00 16.--23. 1. "Reserved0,Reserved"
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hexmask.long.word 0x00 0.--15. 1. "Reserved1,Reserved"
group.long 0x60++0x03
line.long 0x00 "SIRFDR0,SIRFDR is a 32/16/8-bit read-only register that stores the receive FIFO data of the MSIOF"
hexmask.long.word 0x00 16.--31. 1. "SIRFD1,Store the upper 16 bits of the FIFO data received through MSIOF_RXD"
hexmask.long.word 0x00 0.--15. 1. "SIRFD2,Store the lower 16 bits of the FIFO data received through MSIOF_RXD"
group.long 0x60++0x03
line.long 0x00 "SIRFDR0__16_L,SIRFDR is a 32/16/8-bit read-only register that stores the receive FIFO data of the MSIOF"
hexmask.long.word 0x00 16.--31. 1. "Reserved0,Reserved"
hexmask.long.word 0x00 0.--15. 1. "SIRFD2,Store the lower 16 bits of the FIFO data received through MSIOF_RXD"
group.long 0x60++0x03
line.long 0x00 "SIRFDR0__16_H,SIRFDR is a 32/16/8-bit read-only register that stores the receive FIFO data of the MSIOF"
hexmask.long.word 0x00 16.--31. 1. "SIRFD1,Store the upper 16 bits of the FIFO data received through MSIOF_RXD"
hexmask.long.word 0x00 0.--15. 1. "Reserved1,Reserved"
group.long 0x60++0x03
line.long 0x00 "SIRFDR0__8_LL,SIRFDR is a 32/16/8-bit read-only register that stores the receive FIFO data of the MSIOF"
hexmask.long.word 0x00 16.--31. 1. "Reserved0,Reserved"
hexmask.long.byte 0x00 8.--15. 1. "Reserved1,Reserved"
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hexmask.long.byte 0x00 0.--7. 1. "SIRFD2,Store the lower 16 bits of the FIFO data received through MSIOF_RXD"
group.long 0x60++0x03
line.long 0x00 "SIRFDR0__8_LH,SIRFDR is a 32/16/8-bit read-only register that stores the receive FIFO data of the MSIOF"
hexmask.long.word 0x00 16.--31. 1. "Reserved0,Reserved"
hexmask.long.byte 0x00 8.--15. 1. "SIRFD2,Store the lower 16 bits of the FIFO data received through MSIOF_RXD"
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hexmask.long.byte 0x00 0.--7. 1. "Reserved1,Reserved"
group.long 0x60++0x03
line.long 0x00 "SIRFDR0__8_HL,SIRFDR is a 32/16/8-bit read-only register that stores the receive FIFO data of the MSIOF"
hexmask.long.byte 0x00 24.--31. 1. "Reserved0,Reserved"
hexmask.long.byte 0x00 16.--23. 1. "SIRFD1,Store the upper 16 bits of the FIFO data received through MSIOF_RXD"
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hexmask.long.word 0x00 0.--15. 1. "Reserved1,Reserved"
group.long 0x60++0x03
line.long 0x00 "SIRFDR0__8_HH,SIRFDR is a 32/16/8-bit read-only register that stores the receive FIFO data of the MSIOF"
hexmask.long.byte 0x00 24.--31. 1. "SIRFD1,Store the upper 16 bits of the FIFO data received through MSIOF_RXD"
hexmask.long.byte 0x00 16.--23. 1. "Reserved0,Reserved"
newline
hexmask.long.word 0x00 0.--15. 1. "Reserved1,Reserved"
tree.end
tree "MSIOF_INST_1"
base ad:0xE6EA0000
group.long 0x00++0x03
line.long 0x00 "SITMDR11,SITMDR1 is a 32-bit readable/writable register that specifies the MSIOF transmit mode"
bitfld.long 0x00 31. "TRMD,Transfer Mode Selects the transfer mode" "0: Slave mode,1: Master mode"
bitfld.long 0x00 30. "PCON,Transfer Signal Connection" "0: Setting prohibited,1: MSIOF_SCK and MSIOF_SYNC are used as common"
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bitfld.long 0x00 28.--29. "SYNCMD,SYNC Mode These bits specify the mode for the MSIOF_SYNC signal" "0: Frame start synchronization,1: Reserved,2: Level mode/SPI,3: L/R mode"
bitfld.long 0x00 26.--27. "SYNCCH,Synchronization Signal Channel Select These bits are valid only in master mode" "0: The frame synchronization signal output at,1: The frame synchronization signal output at,2: The frame synchronization signal output at,3: Setting prohibited"
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bitfld.long 0x00 25. "SYNCAC,MSIOF_SYNC Polarity" "0: Active-high signal in synchronization pulse or,1: Active-low signal in synchronization pulse or"
bitfld.long 0x00 24. "BITLSB,MSB/LSB First" "0: MSB first,1: LSB first"
newline
rbitfld.long 0x00 23. "Reserved_23,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 20.--22. "DTDL,Data Pin Bit Delay for MSIOF_SYNC Pin The value specified with TXDIZ in SICTR is output during transmission" "0: No bit delay,1: 1-clock-cycle delay,2: 2-clock-cycle delay,?,?,5: 0.5-clock-cycle delay,6: 1.5-clock-cycle delay Other than above,?..."
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rbitfld.long 0x00 19. "Reserved_19,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 16.--18. "SYNCDL,Frame Synchronization Signal Timing Delay These bits extend the transmit frame synchronization signal" "0: No bit delay,1: 1-clock-cycle delay,2: 2-clock-cycle delay,3: 3-clock-cycle delay,?,5: 0.5-clock-cycle delay,6: 1.5-clock-cycle delay Other than above,?..."
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hexmask.long.word 0x00 4.--15. 1. "Reserved_4,Reserved These bits are always read as 0"
bitfld.long 0x00 2.--3. "FLD,Frame Synchronization Signal Interval Specify the minimum idle time between frames in the number of serial clock cycles" "0: 0-clock-cycle delay,1: 1-clock-cycle delay,2: 2-clock-cycle delay,3: 3-clock-cycle delay"
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rbitfld.long 0x00 1. "Reserved_1,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 0. "TXSTP,Transmission Stop" "0: Setting prohibited,1: Stop a frame from starting to transmit until"
group.long 0x04++0x03
line.long 0x00 "SITMDR21,SITMDR2 is a 32-bit readable/writable register that specifies the MSIOF transmit mode"
rbitfld.long 0x00 31. "Reserved_31,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 30. "GRP,Group Count" "0: Group count 1,1: Group count 2"
newline
rbitfld.long 0x00 29. "Reserved_29,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 24.--28. "BITLEN1,Data Size (8 to 32 bits) The word size (bits) of Group 1 is set to the value specified in these bits + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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rbitfld.long 0x00 22.--23. "Reserved_22,Reserved These bits are always read as 0" "0,1,2,3"
bitfld.long 0x00 16.--21. "WDLEN1,Word Count (1 to 64 words) The word count of Group 1 is set to WDLEN1 + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.long.word 0x00 0.--15. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x08++0x03
line.long 0x00 "SITMDR31,SITMDR3 is a 32-bit readable/writable register that specifies the MSIOF transmit mode"
rbitfld.long 0x00 29.--31. "Reserved_29,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24.--28. "BITLEN2,Word Size (8 to 32 bits) The word size (bits) of Group 2 is set to the value specified in these bits + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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rbitfld.long 0x00 22.--23. "Reserved_22,Reserved These bits are always read as 0" "0,1,2,3"
bitfld.long 0x00 16.--21. "WDLEN2,Word Count (1 to 64 words) The word count of Group 2 is set to WDLEN2 + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.word 0x00 0.--15. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x10++0x03
line.long 0x00 "SIRMDR11,SIRMDR1 is a 32-bit readable/writable register that specifies the MSIOF receive mode"
bitfld.long 0x00 31. "TRMD,Transfer Mode Selects the transfer mode" "0,1"
rbitfld.long 0x00 30. "Reserved_30,Reserved This bit is always read as 0" "0,1"
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bitfld.long 0x00 28.--29. "SYNCMD,SYNC Mode The mode setting in these bits should be the same as that in SITMDR1.SYNCMD" "0: Frame start synchronization,1: Reserved,2: Level mode/SPI,3: L/R mode"
rbitfld.long 0x00 26.--27. "Reserved_26,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 25. "SYNCAC,SYNC Polarity" "0: Active-high signal in synchronization pulse or,1: Active-low signal in synchronization pulse or"
bitfld.long 0x00 24. "BITLSB,MSB/LSB First" "0: MSB first,1: LSB first"
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rbitfld.long 0x00 23. "Reserved_23,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 20.--22. "DTDL,Data Pin Bit Delay for MSIOF_SYNC Pin" "0: No bit delay,1: 1-clock-cycle delay,2: 2-clock-cycle delay Other than above,?..."
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rbitfld.long 0x00 19. "Reserved_19,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 16.--18. "SYNCDL,MSIOF_SYNC Timing Delay These bits should always be set to B000" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x00 0.--15. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x14++0x03
line.long 0x00 "SIRMDR21,SIRMDR2 is a 32-bit readable/writable register that specifies the MSIOF receive mode"
rbitfld.long 0x00 31. "Reserved_31,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 30. "GRP,Group Count" "0: Group count 1,1: Group count 2 When using reception in"
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rbitfld.long 0x00 29. "Reserved_29,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 24.--28. "BITLEN1,Word Size (8 to 32 bits) The word size (bits) of Group 1 is set to the value specified in these bits + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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rbitfld.long 0x00 22.--23. "Reserved_22,Reserved These bits are always read as 0" "0,1,2,3"
bitfld.long 0x00 16.--21. "WDLEN1,Word Count (1 to 64 words) The word count of Group 1 is set to WDLEN1 + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.word 0x00 0.--15. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x18++0x03
line.long 0x00 "SIRMDR31,SIRMDR3 is a 32-bit readable/writable register that specifies the MSIOF receive mode"
rbitfld.long 0x00 29.--31. "Reserved_29,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24.--28. "BITLEN2,Word Size (8 to 32 bits) The word size (bits) of Group 2 is set to the value specified in these bits + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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rbitfld.long 0x00 22.--23. "Reserved_22,Reserved These bits are always read as 0" "0,1,2,3"
bitfld.long 0x00 16.--21. "WDLEN2,Word Count (1 to 64 words) The word count of Group 2 is set to WDLEN2 + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.word 0x00 0.--15. 1. "Reserved_0,Reserved These bits are always read as 0"
group.word 0x20++0x01
line.word 0x00 "SITSCR1,SITSCR is a 16-bit readable/writable register that specifies the conditions for generating transmit serial clock in master mode"
bitfld.word 0x00 14.--15. "MSSEL,Master Clock Source Select The master clock is the clock input to the baud rate generator" "0,1,2,3"
bitfld.word 0x00 13. "MSIMM,Master Clock Direct Select" "0: Selects the clock output from the baud rate,1: Setting prohibited"
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bitfld.word 0x00 8.--12. "BRPS,Prescaler Setting These bits specify the master clock (MSO?) division ratio in the count value of the prescaler in the baud rate generator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rbitfld.word 0x00 3.--7. "Reserved_3,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.word 0x00 0.--2. "BRDV,Baud Rate Generator's Division Ratio These bits specify the frequency division ratio for the output stage of the baud rate generator" "0: Prescaler output ? 1/2,1: Prescaler output ? 1/4,2: Prescaler output ? 1/8,3: Prescaler output ? 1/16,4: Prescaler output ? 1/32,5: Setting prohibited,6: Setting prohibited,7: Prescaler output ? 1/1"
group.long 0x28++0x03
line.long 0x00 "SICTR1,SICTR is a 32-bit readable/writable register that specifies the MSIOF operating state"
bitfld.long 0x00 30.--31. "TSCKIZ,Transmit Clock Input/output Polarity Select in SPI Mode When Transmission is Disabled When SPI mode is not used these bits must always be set to B00" "0: Inputs MSIOF_SCK when transmission is disabled,1: Setting prohibited,2: Inputs 0 through MSIOF_SCK when transmission is,3: Inputs 1 through MSIOF_SCK when transmission is"
bitfld.long 0x00 28.--29. "RSCKIZ,Receive Clock Polarity Select in SPI Mode Set the same value as the value specified by the TSCKIZ bits" "0,1,2,3"
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bitfld.long 0x00 27. "TEDG,Transmit Timing" "0: Outputs transmit data at the rising edge of the,1: Outputs transmit data at the falling edge of.."
bitfld.long 0x00 26. "REDG,Receive Timing" "0: Samples receive data at the falling edge of the,1: Samples receive data at the rising edge of the"
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rbitfld.long 0x00 24.--25. "Reserved_24,Reserved These bits are always read as 0" "0,1,2,3"
bitfld.long 0x00 22.--23. "TXDIZ,Pin Output When Transmission is Disabled These bits specify the MSIOF_TXD pin output state when transmission is disabled" "0: Outputs 0,1: Outputs 1,2: Setting prohibited,3: Setting prohibited"
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rbitfld.long 0x00 16.--21. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 15. "TSCKE,Transmit Serial Clock Output Enable This bit is valid in master mode" "0: Does not output MSIOF_SCK.(Outputs the value,1: Outputs MSIOF_SCK"
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bitfld.long 0x00 14. "TFSE,Transmit Frame Synchronization Signal Output Enable This bit is valid in master mode" "0: Does not output MSIOF_SYNC.(Outputs the value,1: Outputs MSIOF_SYNC"
bitfld.long 0x00 13. "RSCKE,Receive Serial Clock Output Enable The write value should always be 0" "0,1"
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bitfld.long 0x00 12. "RFSE,Receive Frame Synchronization Signal Output Enable The write value should always be 0" "0,1"
rbitfld.long 0x00 10.--11. "Reserved_10,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 9. "TXE,Transmit Enable When this bit is set to 1 the MSIOF starts data transmission from the beginning of the next frame (at the rising edge of the frame synchronization signal)" "0: Does not output MSIOF_TXD.(Outputs the value,1: Outputs MSIOF_TXD"
bitfld.long 0x00 8. "RXE,Receive Enable When this bit is set to 1 the MSIOF starts data reception from the beginning of the next frame (at the rising edge of the frame synchronization signal)" "0: Data is not received through MSIOF_RXD,1: Data can be received through MSIOF_RXD"
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rbitfld.long 0x00 2.--7. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 1. "TXRST,Transmit Reset When value 1 set to this bit becomes valid the MSIOF immediately sets transmit data through the MSIOF_TXD pin to 0 and initializes the transmit data registers and transmit-related status" "0: Transmit operation reset is completed,1: Transmit operation is being reset"
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bitfld.long 0x00 0. "RXRST,Receive Reset When value 1 set to this bit becomes valid the MSIOF immediately disables reception through the MSIOF_RXD pin and initializes the receive data registers and receive-related status" "0: Receive operation reset is completed,1: Receive operation is being reset"
group.long 0x30++0x03
line.long 0x00 "SIFCTR1,SIFCTR is a 32-bit readable/writable register that indicates the area available for the transmit/receive FIFO transfer"
bitfld.long 0x00 29.--31. "TFWM,Transmit FIFO Watermark A transfer request of the transmit FIFO is issued by the TDREQE bit in SIIER" "0: Issues a transfer request when 64 stages of the,1: Issues a transfer request when 32 or more..,2: Issues a transfer request when 24 or more..,3: Issues a transfer request when 16 or more..,4: Issues a transfer request when 12 or more..,5: Issues a transfer request when 8 or more stages,6: Issues a transfer request when 4 or more stages,7: Issues a transfer request when 1 or more stages"
rbitfld.long 0x00 27.--28. "Reserved_27,Reserved These bits are always read as 0" "0,1,2,3"
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hexmask.long.byte 0x00 20.--26. 1. "TFUA,Transmit FIFO Usable Area Indicate the number of words that can be transferred by the CPU or DMAC as B'000 0000 (full) to B'100 0000 (empty)"
rbitfld.long 0x00 16.--19. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 13.--15. "RFWM,Receive FIFO Watermark A transfer request of the receive FIFO is issued by the RDREQE bit in SIIER" "0: Issues a transfer request when 1 stage or more,1: Issues a transfer request when 4 or more stages,2: Issues a transfer request when 8 or more stages,3: Issues a transfer request when 16 or more..,4: Issues a transfer request when 32 or more..,5: Issues a transfer request when 64 or more..,6: Issues a transfer request when 128 or more,7: Issues a transfer request when 256 stages of.."
hexmask.long.word 0x00 4.--12. 1. "RFUA,Receive FIFO Usable Area Indicate the number of words that can be transferred by the CPU or DMAC as B'0 0000 0000 (empty) to B'1 0000 0000 (full)"
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rbitfld.long 0x00 0.--3. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x40++0x03
line.long 0x00 "SISTR1,Each bit in SISTR becomes an MSIOF interrupt source when the corresponding bit in SIIER is set to 1"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved These bits are always read as 0" "0,1,2,3"
bitfld.long 0x00 29. "TFEMP,Transmit FIFO Empty This bit is set to 1 when the TXE bit in SICTR is 1 and transmit FIFO is empty" "0: Transmit FIFO is not empty,1: Transmit FIFO is empty"
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rbitfld.long 0x00 28. "TDREQ,Transmit Data Transfer Request This bit is set when the empty space in the transmit FIFO exceeds the size specified by the TFWM bits in SIFCTR" "0: The size of empty space in the transmit FIFO..,1: The size of empty space in the transmit FIFO.."
rbitfld.long 0x00 24.--27. "Reserved_24,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 23. "TEOF,Frame Transmission End This bit is set when one-frame data transmission is completed" "0: One-frame transmission end is not detected,1: One-frame transmission end is detected"
rbitfld.long 0x00 22. "Reserved_22,Reserved This bit is always read as 0" "0,1"
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bitfld.long 0x00 21. "TFSERR,Transmit Frame Synchronization Error This bit is set when the next transmit frame synchronization timing arrives before the previous data transmission has been completed" "0: No transmit frame synchronization error has,1: A transmit frame synchronization error has"
bitfld.long 0x00 20. "TFOVF,Transmit FIFO Overflow A transmit FIFO overflow means that there has been an attempt to write to SITFDR when the transmit FIFO is full" "0: No transmit FIFO overflow has occurred,1: A transmit FIFO overflow has occurred"
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bitfld.long 0x00 19. "TFUDF,Transmit FIFO Underflow A transmit FIFO underflow means that loading for transmission has occurred when the transmit FIFO is empty" "0: No transmit FIFO underflow has occurred,1: A transmit FIFO underflow has occurred"
rbitfld.long 0x00 14.--18. "Reserved_14,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 13. "RFFUL,Receive FIFO Full This bit is valid when the RXE bit in SICTR is 1" "0: Receive FIFO is not full,1: Receive FIFO is full"
rbitfld.long 0x00 12. "RDREQ,Receive Data Transfer Request This bit is set when the valid data space in the receive FIFO exceeds the size specified by the RFWM bits in SIFCTR" "0: The size of valid data space in the receive..,1: The size of valid data space in the receive.."
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rbitfld.long 0x00 8.--11. "Reserved_8,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 7. "REOF,Frame Reception End The MSIOF issues the frame reception end flag upon completion of one-frame data reception" "0: One-frame reception end is not detected,1: One-frame reception end is detected"
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rbitfld.long 0x00 6. "Reserved_6,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 5. "RFSERR,Receive Frame Synchronization Error A receive frame synchronization error occurs when the next receive frame synchronization timing arrives before the previous data reception has been completed" "0: No receive frame synchronization error has,1: A receive frame synchronization error has.."
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bitfld.long 0x00 4. "RFUDF,Receive FIFO Underflow A receive FIFO underflow means that reading of SIRFDR has occurred when the receive FIFO is empty" "0: No receive FIFO underflow has occurred,1: A receive FIFO underflow has occurred"
bitfld.long 0x00 3. "RFOVF,Receive FIFO Overflow A receive FIFO overflow means that writing has been caused by receiving operation when the receive FIFO is full" "0: No receive FIFO overflow has occurred,1: A receive FIFO overflow has occurred"
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eventfld.long 0x00 0.--2. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
group.long 0x44++0x03
line.long 0x00 "SIIER1,"
bitfld.long 0x00 31. "TDMAE,Transmit Data DMA Transfer Request Enable Specifies whether to send an interrupt as an interrupt request to the CPU or a transfer request to the DMAC" "0: Sends an interrupt request to the CPU,1: Sends a DMA transfer request to the DMAC"
rbitfld.long 0x00 30. "Reserved_30,Reserved This bit is always read as 0" "0,1"
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bitfld.long 0x00 29. "TFEMPE,Transmit FIFO Empty Enable" "0: Disables interrupts due to transmit FIFO empty,1: Enables interrupts due to transmit FIFO empty"
bitfld.long 0x00 28. "TDREQE,Transmit Data Transfer Request Enable" "0: Disables interrupts due to transmit data,1: Enables interrupts due to transmit data.."
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rbitfld.long 0x00 24.--27. "Reserved_24,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 23. "TEOFE,Frame Transmission End Enable" "0: Disables a frame transmission end interrupt,1: Enables a frame transmission end interrupt"
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rbitfld.long 0x00 22. "Reserved_22,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 21. "TFSERRE,Transmit Frame Synchronization Error Enable" "0: Disables interrupts due to transmit frame,1: Enables interrupts due to transmit frame"
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bitfld.long 0x00 20. "TFOVFE,Transmit FIFO Overflow Enable" "0: Disables interrupts due to transmit FIFO..,1: Enables interrupts due to transmit FIFO.."
bitfld.long 0x00 19. "TFUDFE,Transmit FIFO Underflow Enable" "0: Disables interrupts due to transmit FIFO..,1: Enables interrupts due to transmit FIFO.."
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rbitfld.long 0x00 16.--18. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 15. "RDMAE,Receive Data DMA Transfer Request Enable Specifies whether to send an interrupt as an interrupt request to the CPU or a transfer request to the DMAC" "0: Sends an interrupt request to the CPU,1: Sends a DMA transfer request to the DMAC"
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rbitfld.long 0x00 14. "Reserved_14,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 13. "RFFULE,Receive FIFO Full Enable" "0: Disables interrupts due to receive FIFO full,1: Enables interrupts due to receive FIFO full"
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bitfld.long 0x00 12. "RDREQE,Receive Data Transfer Request Enable" "0: Disables interrupts due to receive data..,1: Enables interrupts due to receive data transfer"
rbitfld.long 0x00 8.--11. "Reserved_8,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 7. "REOFE,Frame Reception End Enable" "0: Disables a frame reception end interrupt,1: Enables a frame reception end interrupt"
rbitfld.long 0x00 6. "Reserved_6,Reserved This bit is always read as 0" "0,1"
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bitfld.long 0x00 5. "RFSERRE,Receive Frame Synchronization Error Enable" "0: Disables interrupts due to receive frame,1: Enables interrupts due to receive frame"
bitfld.long 0x00 4. "RFUDFE,Receive FIFO Underflow Enable" "0: Disables interrupts due to receive FIFO..,1: Enables interrupts due to receive FIFO.."
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bitfld.long 0x00 3. "RFOVFE,Receive FIFO Overflow Enable" "0: Disables interrupts due to receive FIFO..,1: Enables interrupts due to receive FIFO overflow"
rbitfld.long 0x00 0.--2. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
group.long 0x50++0x03
line.long 0x00 "SITFDR1,SITFDR is a 32/16/8-bit write-only register that specifies the transmit FIFO data of the MSIOF"
hexmask.long.word 0x00 16.--31. 1. "SITFD1,These bits specify the upper 16 bits of the FIFO data to be output through MSIOF_TXD"
hexmask.long.word 0x00 0.--15. 1. "SITFD2,These bits specify the lower 16 bits of the FIFO data to be output through MSIOF_TXD"
group.long 0x50++0x03
line.long 0x00 "SITFDR1__16_L,SITFDR is a 32/16/8-bit write-only register that specifies the transmit FIFO data of the MSIOF"
hexmask.long.word 0x00 16.--31. 1. "Reserved0,Reserved"
hexmask.long.word 0x00 0.--15. 1. "SITFD2,These bits specify the lower 16 bits of the FIFO data to be output through MSIOF_TXD"
group.long 0x50++0x03
line.long 0x00 "SITFDR1__16_H,SITFDR is a 32/16/8-bit write-only register that specifies the transmit FIFO data of the MSIOF"
hexmask.long.word 0x00 16.--31. 1. "SITFD1,These bits specify the upper 16 bits of the FIFO data to be output through MSIOF_TXD"
hexmask.long.word 0x00 0.--15. 1. "Reserved1,Reserved"
group.long 0x50++0x03
line.long 0x00 "SITFDR1__8_LL,SITFDR is a 32/16/8-bit write-only register that specifies the transmit FIFO data of the MSIOF"
hexmask.long.word 0x00 16.--31. 1. "Reserved0,Reserved"
hexmask.long.byte 0x00 8.--15. 1. "Reserved1,Reserved"
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hexmask.long.byte 0x00 0.--7. 1. "SITFD2,These bits specify the lower 16 bits of the FIFO data to be output through MSIOF_TXD"
group.long 0x50++0x03
line.long 0x00 "SITFDR1__8_LH,SITFDR is a 32/16/8-bit write-only register that specifies the transmit FIFO data of the MSIOF"
hexmask.long.word 0x00 16.--31. 1. "Reserved0,Reserved"
hexmask.long.byte 0x00 8.--15. 1. "SITFD2,These bits specify the lower 16 bits of the FIFO data to be output through MSIOF_TXD"
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hexmask.long.byte 0x00 0.--7. 1. "Reserved1,Reserved"
group.long 0x50++0x03
line.long 0x00 "SITFDR1__8_HL,SITFDR is a 32/16/8-bit write-only register that specifies the transmit FIFO data of the MSIOF"
hexmask.long.byte 0x00 24.--31. 1. "Reserved0,Reserved"
hexmask.long.byte 0x00 16.--23. 1. "SITFD1,These bits specify the upper 16 bits of the FIFO data to be output through MSIOF_TXD"
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hexmask.long.word 0x00 0.--15. 1. "Reserved1,Reserved"
group.long 0x50++0x03
line.long 0x00 "SITFDR1__8_HH,SITFDR is a 32/16/8-bit write-only register that specifies the transmit FIFO data of the MSIOF"
hexmask.long.byte 0x00 24.--31. 1. "SITFD1,These bits specify the upper 16 bits of the FIFO data to be output through MSIOF_TXD"
hexmask.long.byte 0x00 16.--23. 1. "Reserved0,Reserved"
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hexmask.long.word 0x00 0.--15. 1. "Reserved1,Reserved"
group.long 0x60++0x03
line.long 0x00 "SIRFDR1,SIRFDR is a 32/16/8-bit read-only register that stores the receive FIFO data of the MSIOF"
hexmask.long.word 0x00 16.--31. 1. "SIRFD1,Store the upper 16 bits of the FIFO data received through MSIOF_RXD"
hexmask.long.word 0x00 0.--15. 1. "SIRFD2,Store the lower 16 bits of the FIFO data received through MSIOF_RXD"
group.long 0x60++0x03
line.long 0x00 "SIRFDR1__16_L,SIRFDR is a 32/16/8-bit read-only register that stores the receive FIFO data of the MSIOF"
hexmask.long.word 0x00 16.--31. 1. "Reserved0,Reserved"
hexmask.long.word 0x00 0.--15. 1. "SIRFD2,Store the lower 16 bits of the FIFO data received through MSIOF_RXD"
group.long 0x60++0x03
line.long 0x00 "SIRFDR1__16_H,SIRFDR is a 32/16/8-bit read-only register that stores the receive FIFO data of the MSIOF"
hexmask.long.word 0x00 16.--31. 1. "SIRFD1,Store the upper 16 bits of the FIFO data received through MSIOF_RXD"
hexmask.long.word 0x00 0.--15. 1. "Reserved1,Reserved"
group.long 0x60++0x03
line.long 0x00 "SIRFDR1__8_LL,SIRFDR is a 32/16/8-bit read-only register that stores the receive FIFO data of the MSIOF"
hexmask.long.word 0x00 16.--31. 1. "Reserved0,Reserved"
hexmask.long.byte 0x00 8.--15. 1. "Reserved1,Reserved"
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hexmask.long.byte 0x00 0.--7. 1. "SIRFD2,Store the lower 16 bits of the FIFO data received through MSIOF_RXD"
group.long 0x60++0x03
line.long 0x00 "SIRFDR1__8_LH,SIRFDR is a 32/16/8-bit read-only register that stores the receive FIFO data of the MSIOF"
hexmask.long.word 0x00 16.--31. 1. "Reserved0,Reserved"
hexmask.long.byte 0x00 8.--15. 1. "SIRFD2,Store the lower 16 bits of the FIFO data received through MSIOF_RXD"
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hexmask.long.byte 0x00 0.--7. 1. "Reserved1,Reserved"
group.long 0x60++0x03
line.long 0x00 "SIRFDR1__8_HL,SIRFDR is a 32/16/8-bit read-only register that stores the receive FIFO data of the MSIOF"
hexmask.long.byte 0x00 24.--31. 1. "Reserved0,Reserved"
hexmask.long.byte 0x00 16.--23. 1. "SIRFD1,Store the upper 16 bits of the FIFO data received through MSIOF_RXD"
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hexmask.long.word 0x00 0.--15. 1. "Reserved1,Reserved"
group.long 0x60++0x03
line.long 0x00 "SIRFDR1__8_HH,SIRFDR is a 32/16/8-bit read-only register that stores the receive FIFO data of the MSIOF"
hexmask.long.byte 0x00 24.--31. 1. "SIRFD1,Store the upper 16 bits of the FIFO data received through MSIOF_RXD"
hexmask.long.byte 0x00 16.--23. 1. "Reserved0,Reserved"
newline
hexmask.long.word 0x00 0.--15. 1. "Reserved1,Reserved"
tree.end
tree "MSIOF_INST_2"
base ad:0xE6C00000
group.long 0x00++0x03
line.long 0x00 "SITMDR12,SITMDR1 is a 32-bit readable/writable register that specifies the MSIOF transmit mode"
bitfld.long 0x00 31. "TRMD,Transfer Mode Selects the transfer mode" "0: Slave mode,1: Master mode"
bitfld.long 0x00 30. "PCON,Transfer Signal Connection" "0: Setting prohibited,1: MSIOF_SCK and MSIOF_SYNC are used as common"
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bitfld.long 0x00 28.--29. "SYNCMD,SYNC Mode These bits specify the mode for the MSIOF_SYNC signal" "0: Frame start synchronization,1: Reserved,2: Level mode/SPI,3: L/R mode"
bitfld.long 0x00 26.--27. "SYNCCH,Synchronization Signal Channel Select These bits are valid only in master mode" "0: The frame synchronization signal output at,1: The frame synchronization signal output at,2: The frame synchronization signal output at,3: Setting prohibited"
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bitfld.long 0x00 25. "SYNCAC,MSIOF_SYNC Polarity" "0: Active-high signal in synchronization pulse or,1: Active-low signal in synchronization pulse or"
bitfld.long 0x00 24. "BITLSB,MSB/LSB First" "0: MSB first,1: LSB first"
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rbitfld.long 0x00 23. "Reserved_23,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 20.--22. "DTDL,Data Pin Bit Delay for MSIOF_SYNC Pin The value specified with TXDIZ in SICTR is output during transmission" "0: No bit delay,1: 1-clock-cycle delay,2: 2-clock-cycle delay,?,?,5: 0.5-clock-cycle delay,6: 1.5-clock-cycle delay Other than above,?..."
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rbitfld.long 0x00 19. "Reserved_19,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 16.--18. "SYNCDL,Frame Synchronization Signal Timing Delay These bits extend the transmit frame synchronization signal" "0: No bit delay,1: 1-clock-cycle delay,2: 2-clock-cycle delay,3: 3-clock-cycle delay,?,5: 0.5-clock-cycle delay,6: 1.5-clock-cycle delay Other than above,?..."
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hexmask.long.word 0x00 4.--15. 1. "Reserved_4,Reserved These bits are always read as 0"
bitfld.long 0x00 2.--3. "FLD,Frame Synchronization Signal Interval Specify the minimum idle time between frames in the number of serial clock cycles" "0: 0-clock-cycle delay,1: 1-clock-cycle delay,2: 2-clock-cycle delay,3: 3-clock-cycle delay"
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rbitfld.long 0x00 1. "Reserved_1,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 0. "TXSTP,Transmission Stop" "0: Setting prohibited,1: Stop a frame from starting to transmit until"
group.long 0x04++0x03
line.long 0x00 "SITMDR22,SITMDR2 is a 32-bit readable/writable register that specifies the MSIOF transmit mode"
rbitfld.long 0x00 31. "Reserved_31,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 30. "GRP,Group Count" "0: Group count 1,1: Group count 2"
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rbitfld.long 0x00 29. "Reserved_29,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 24.--28. "BITLEN1,Data Size (8 to 32 bits) The word size (bits) of Group 1 is set to the value specified in these bits + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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rbitfld.long 0x00 22.--23. "Reserved_22,Reserved These bits are always read as 0" "0,1,2,3"
bitfld.long 0x00 16.--21. "WDLEN1,Word Count (1 to 64 words) The word count of Group 1 is set to WDLEN1 + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.word 0x00 0.--15. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x08++0x03
line.long 0x00 "SITMDR32,SITMDR3 is a 32-bit readable/writable register that specifies the MSIOF transmit mode"
rbitfld.long 0x00 29.--31. "Reserved_29,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24.--28. "BITLEN2,Word Size (8 to 32 bits) The word size (bits) of Group 2 is set to the value specified in these bits + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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rbitfld.long 0x00 22.--23. "Reserved_22,Reserved These bits are always read as 0" "0,1,2,3"
bitfld.long 0x00 16.--21. "WDLEN2,Word Count (1 to 64 words) The word count of Group 2 is set to WDLEN2 + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.word 0x00 0.--15. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x10++0x03
line.long 0x00 "SIRMDR12,SIRMDR1 is a 32-bit readable/writable register that specifies the MSIOF receive mode"
bitfld.long 0x00 31. "TRMD,Transfer Mode Selects the transfer mode" "0,1"
rbitfld.long 0x00 30. "Reserved_30,Reserved This bit is always read as 0" "0,1"
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bitfld.long 0x00 28.--29. "SYNCMD,SYNC Mode The mode setting in these bits should be the same as that in SITMDR1.SYNCMD" "0: Frame start synchronization,1: Reserved,2: Level mode/SPI,3: L/R mode"
rbitfld.long 0x00 26.--27. "Reserved_26,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 25. "SYNCAC,SYNC Polarity" "0: Active-high signal in synchronization pulse or,1: Active-low signal in synchronization pulse or"
bitfld.long 0x00 24. "BITLSB,MSB/LSB First" "0: MSB first,1: LSB first"
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rbitfld.long 0x00 23. "Reserved_23,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 20.--22. "DTDL,Data Pin Bit Delay for MSIOF_SYNC Pin" "0: No bit delay,1: 1-clock-cycle delay,2: 2-clock-cycle delay Other than above,?..."
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rbitfld.long 0x00 19. "Reserved_19,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 16.--18. "SYNCDL,MSIOF_SYNC Timing Delay These bits should always be set to B000" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x00 0.--15. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x14++0x03
line.long 0x00 "SIRMDR22,SIRMDR2 is a 32-bit readable/writable register that specifies the MSIOF receive mode"
rbitfld.long 0x00 31. "Reserved_31,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 30. "GRP,Group Count" "0: Group count 1,1: Group count 2 When using reception in"
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rbitfld.long 0x00 29. "Reserved_29,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 24.--28. "BITLEN1,Word Size (8 to 32 bits) The word size (bits) of Group 1 is set to the value specified in these bits + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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rbitfld.long 0x00 22.--23. "Reserved_22,Reserved These bits are always read as 0" "0,1,2,3"
bitfld.long 0x00 16.--21. "WDLEN1,Word Count (1 to 64 words) The word count of Group 1 is set to WDLEN1 + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.word 0x00 0.--15. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x18++0x03
line.long 0x00 "SIRMDR32,SIRMDR3 is a 32-bit readable/writable register that specifies the MSIOF receive mode"
rbitfld.long 0x00 29.--31. "Reserved_29,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24.--28. "BITLEN2,Word Size (8 to 32 bits) The word size (bits) of Group 2 is set to the value specified in these bits + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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rbitfld.long 0x00 22.--23. "Reserved_22,Reserved These bits are always read as 0" "0,1,2,3"
bitfld.long 0x00 16.--21. "WDLEN2,Word Count (1 to 64 words) The word count of Group 2 is set to WDLEN2 + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.word 0x00 0.--15. 1. "Reserved_0,Reserved These bits are always read as 0"
group.word 0x20++0x01
line.word 0x00 "SITSCR2,SITSCR is a 16-bit readable/writable register that specifies the conditions for generating transmit serial clock in master mode"
bitfld.word 0x00 14.--15. "MSSEL,Master Clock Source Select The master clock is the clock input to the baud rate generator" "0,1,2,3"
bitfld.word 0x00 13. "MSIMM,Master Clock Direct Select" "0: Selects the clock output from the baud rate,1: Setting prohibited"
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bitfld.word 0x00 8.--12. "BRPS,Prescaler Setting These bits specify the master clock (MSO?) division ratio in the count value of the prescaler in the baud rate generator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rbitfld.word 0x00 3.--7. "Reserved_3,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.word 0x00 0.--2. "BRDV,Baud Rate Generator's Division Ratio These bits specify the frequency division ratio for the output stage of the baud rate generator" "0: Prescaler output ? 1/2,1: Prescaler output ? 1/4,2: Prescaler output ? 1/8,3: Prescaler output ? 1/16,4: Prescaler output ? 1/32,5: Setting prohibited,6: Setting prohibited,7: Prescaler output ? 1/1"
group.long 0x28++0x03
line.long 0x00 "SICTR2,SICTR is a 32-bit readable/writable register that specifies the MSIOF operating state"
bitfld.long 0x00 30.--31. "TSCKIZ,Transmit Clock Input/output Polarity Select in SPI Mode When Transmission is Disabled When SPI mode is not used these bits must always be set to B00" "0: Inputs MSIOF_SCK when transmission is disabled,1: Setting prohibited,2: Inputs 0 through MSIOF_SCK when transmission is,3: Inputs 1 through MSIOF_SCK when transmission is"
bitfld.long 0x00 28.--29. "RSCKIZ,Receive Clock Polarity Select in SPI Mode Set the same value as the value specified by the TSCKIZ bits" "0,1,2,3"
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bitfld.long 0x00 27. "TEDG,Transmit Timing" "0: Outputs transmit data at the rising edge of the,1: Outputs transmit data at the falling edge of.."
bitfld.long 0x00 26. "REDG,Receive Timing" "0: Samples receive data at the falling edge of the,1: Samples receive data at the rising edge of the"
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rbitfld.long 0x00 24.--25. "Reserved_24,Reserved These bits are always read as 0" "0,1,2,3"
bitfld.long 0x00 22.--23. "TXDIZ,Pin Output When Transmission is Disabled These bits specify the MSIOF_TXD pin output state when transmission is disabled" "0: Outputs 0,1: Outputs 1,2: Setting prohibited,3: Setting prohibited"
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rbitfld.long 0x00 16.--21. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 15. "TSCKE,Transmit Serial Clock Output Enable This bit is valid in master mode" "0: Does not output MSIOF_SCK.(Outputs the value,1: Outputs MSIOF_SCK"
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bitfld.long 0x00 14. "TFSE,Transmit Frame Synchronization Signal Output Enable This bit is valid in master mode" "0: Does not output MSIOF_SYNC.(Outputs the value,1: Outputs MSIOF_SYNC"
bitfld.long 0x00 13. "RSCKE,Receive Serial Clock Output Enable The write value should always be 0" "0,1"
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bitfld.long 0x00 12. "RFSE,Receive Frame Synchronization Signal Output Enable The write value should always be 0" "0,1"
rbitfld.long 0x00 10.--11. "Reserved_10,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 9. "TXE,Transmit Enable When this bit is set to 1 the MSIOF starts data transmission from the beginning of the next frame (at the rising edge of the frame synchronization signal)" "0: Does not output MSIOF_TXD.(Outputs the value,1: Outputs MSIOF_TXD"
bitfld.long 0x00 8. "RXE,Receive Enable When this bit is set to 1 the MSIOF starts data reception from the beginning of the next frame (at the rising edge of the frame synchronization signal)" "0: Data is not received through MSIOF_RXD,1: Data can be received through MSIOF_RXD"
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rbitfld.long 0x00 2.--7. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 1. "TXRST,Transmit Reset When value 1 set to this bit becomes valid the MSIOF immediately sets transmit data through the MSIOF_TXD pin to 0 and initializes the transmit data registers and transmit-related status" "0: Transmit operation reset is completed,1: Transmit operation is being reset"
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bitfld.long 0x00 0. "RXRST,Receive Reset When value 1 set to this bit becomes valid the MSIOF immediately disables reception through the MSIOF_RXD pin and initializes the receive data registers and receive-related status" "0: Receive operation reset is completed,1: Receive operation is being reset"
group.long 0x30++0x03
line.long 0x00 "SIFCTR2,SIFCTR is a 32-bit readable/writable register that indicates the area available for the transmit/receive FIFO transfer"
bitfld.long 0x00 29.--31. "TFWM,Transmit FIFO Watermark A transfer request of the transmit FIFO is issued by the TDREQE bit in SIIER" "0: Issues a transfer request when 64 stages of the,1: Issues a transfer request when 32 or more..,2: Issues a transfer request when 24 or more..,3: Issues a transfer request when 16 or more..,4: Issues a transfer request when 12 or more..,5: Issues a transfer request when 8 or more stages,6: Issues a transfer request when 4 or more stages,7: Issues a transfer request when 1 or more stages"
rbitfld.long 0x00 27.--28. "Reserved_27,Reserved These bits are always read as 0" "0,1,2,3"
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hexmask.long.byte 0x00 20.--26. 1. "TFUA,Transmit FIFO Usable Area Indicate the number of words that can be transferred by the CPU or DMAC as B'000 0000 (full) to B'100 0000 (empty)"
rbitfld.long 0x00 16.--19. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 13.--15. "RFWM,Receive FIFO Watermark A transfer request of the receive FIFO is issued by the RDREQE bit in SIIER" "0: Issues a transfer request when 1 stage or more,1: Issues a transfer request when 4 or more stages,2: Issues a transfer request when 8 or more stages,3: Issues a transfer request when 16 or more..,4: Issues a transfer request when 32 or more..,5: Issues a transfer request when 64 or more..,6: Issues a transfer request when 128 or more,7: Issues a transfer request when 256 stages of.."
hexmask.long.word 0x00 4.--12. 1. "RFUA,Receive FIFO Usable Area Indicate the number of words that can be transferred by the CPU or DMAC as B'0 0000 0000 (empty) to B'1 0000 0000 (full)"
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rbitfld.long 0x00 0.--3. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x40++0x03
line.long 0x00 "SISTR2,Each bit in SISTR becomes an MSIOF interrupt source when the corresponding bit in SIIER is set to 1"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved These bits are always read as 0" "0,1,2,3"
bitfld.long 0x00 29. "TFEMP,Transmit FIFO Empty This bit is set to 1 when the TXE bit in SICTR is 1 and transmit FIFO is empty" "0: Transmit FIFO is not empty,1: Transmit FIFO is empty"
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rbitfld.long 0x00 28. "TDREQ,Transmit Data Transfer Request This bit is set when the empty space in the transmit FIFO exceeds the size specified by the TFWM bits in SIFCTR" "0: The size of empty space in the transmit FIFO..,1: The size of empty space in the transmit FIFO.."
rbitfld.long 0x00 24.--27. "Reserved_24,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 23. "TEOF,Frame Transmission End This bit is set when one-frame data transmission is completed" "0: One-frame transmission end is not detected,1: One-frame transmission end is detected"
rbitfld.long 0x00 22. "Reserved_22,Reserved This bit is always read as 0" "0,1"
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bitfld.long 0x00 21. "TFSERR,Transmit Frame Synchronization Error This bit is set when the next transmit frame synchronization timing arrives before the previous data transmission has been completed" "0: No transmit frame synchronization error has,1: A transmit frame synchronization error has"
bitfld.long 0x00 20. "TFOVF,Transmit FIFO Overflow A transmit FIFO overflow means that there has been an attempt to write to SITFDR when the transmit FIFO is full" "0: No transmit FIFO overflow has occurred,1: A transmit FIFO overflow has occurred"
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bitfld.long 0x00 19. "TFUDF,Transmit FIFO Underflow A transmit FIFO underflow means that loading for transmission has occurred when the transmit FIFO is empty" "0: No transmit FIFO underflow has occurred,1: A transmit FIFO underflow has occurred"
rbitfld.long 0x00 14.--18. "Reserved_14,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 13. "RFFUL,Receive FIFO Full This bit is valid when the RXE bit in SICTR is 1" "0: Receive FIFO is not full,1: Receive FIFO is full"
rbitfld.long 0x00 12. "RDREQ,Receive Data Transfer Request This bit is set when the valid data space in the receive FIFO exceeds the size specified by the RFWM bits in SIFCTR" "0: The size of valid data space in the receive..,1: The size of valid data space in the receive.."
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rbitfld.long 0x00 8.--11. "Reserved_8,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 7. "REOF,Frame Reception End The MSIOF issues the frame reception end flag upon completion of one-frame data reception" "0: One-frame reception end is not detected,1: One-frame reception end is detected"
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rbitfld.long 0x00 6. "Reserved_6,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 5. "RFSERR,Receive Frame Synchronization Error A receive frame synchronization error occurs when the next receive frame synchronization timing arrives before the previous data reception has been completed" "0: No receive frame synchronization error has,1: A receive frame synchronization error has.."
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bitfld.long 0x00 4. "RFUDF,Receive FIFO Underflow A receive FIFO underflow means that reading of SIRFDR has occurred when the receive FIFO is empty" "0: No receive FIFO underflow has occurred,1: A receive FIFO underflow has occurred"
bitfld.long 0x00 3. "RFOVF,Receive FIFO Overflow A receive FIFO overflow means that writing has been caused by receiving operation when the receive FIFO is full" "0: No receive FIFO overflow has occurred,1: A receive FIFO overflow has occurred"
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eventfld.long 0x00 0.--2. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
group.long 0x44++0x03
line.long 0x00 "SIIER2,"
bitfld.long 0x00 31. "TDMAE,Transmit Data DMA Transfer Request Enable Specifies whether to send an interrupt as an interrupt request to the CPU or a transfer request to the DMAC" "0: Sends an interrupt request to the CPU,1: Sends a DMA transfer request to the DMAC"
rbitfld.long 0x00 30. "Reserved_30,Reserved This bit is always read as 0" "0,1"
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bitfld.long 0x00 29. "TFEMPE,Transmit FIFO Empty Enable" "0: Disables interrupts due to transmit FIFO empty,1: Enables interrupts due to transmit FIFO empty"
bitfld.long 0x00 28. "TDREQE,Transmit Data Transfer Request Enable" "0: Disables interrupts due to transmit data,1: Enables interrupts due to transmit data.."
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rbitfld.long 0x00 24.--27. "Reserved_24,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 23. "TEOFE,Frame Transmission End Enable" "0: Disables a frame transmission end interrupt,1: Enables a frame transmission end interrupt"
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rbitfld.long 0x00 22. "Reserved_22,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 21. "TFSERRE,Transmit Frame Synchronization Error Enable" "0: Disables interrupts due to transmit frame,1: Enables interrupts due to transmit frame"
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bitfld.long 0x00 20. "TFOVFE,Transmit FIFO Overflow Enable" "0: Disables interrupts due to transmit FIFO..,1: Enables interrupts due to transmit FIFO.."
bitfld.long 0x00 19. "TFUDFE,Transmit FIFO Underflow Enable" "0: Disables interrupts due to transmit FIFO..,1: Enables interrupts due to transmit FIFO.."
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rbitfld.long 0x00 16.--18. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 15. "RDMAE,Receive Data DMA Transfer Request Enable Specifies whether to send an interrupt as an interrupt request to the CPU or a transfer request to the DMAC" "0: Sends an interrupt request to the CPU,1: Sends a DMA transfer request to the DMAC"
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rbitfld.long 0x00 14. "Reserved_14,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 13. "RFFULE,Receive FIFO Full Enable" "0: Disables interrupts due to receive FIFO full,1: Enables interrupts due to receive FIFO full"
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bitfld.long 0x00 12. "RDREQE,Receive Data Transfer Request Enable" "0: Disables interrupts due to receive data..,1: Enables interrupts due to receive data transfer"
rbitfld.long 0x00 8.--11. "Reserved_8,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 7. "REOFE,Frame Reception End Enable" "0: Disables a frame reception end interrupt,1: Enables a frame reception end interrupt"
rbitfld.long 0x00 6. "Reserved_6,Reserved This bit is always read as 0" "0,1"
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bitfld.long 0x00 5. "RFSERRE,Receive Frame Synchronization Error Enable" "0: Disables interrupts due to receive frame,1: Enables interrupts due to receive frame"
bitfld.long 0x00 4. "RFUDFE,Receive FIFO Underflow Enable" "0: Disables interrupts due to receive FIFO..,1: Enables interrupts due to receive FIFO.."
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bitfld.long 0x00 3. "RFOVFE,Receive FIFO Overflow Enable" "0: Disables interrupts due to receive FIFO..,1: Enables interrupts due to receive FIFO overflow"
rbitfld.long 0x00 0.--2. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
group.long 0x50++0x03
line.long 0x00 "SITFDR2,SITFDR is a 32/16/8-bit write-only register that specifies the transmit FIFO data of the MSIOF"
hexmask.long.word 0x00 16.--31. 1. "SITFD1,These bits specify the upper 16 bits of the FIFO data to be output through MSIOF_TXD"
hexmask.long.word 0x00 0.--15. 1. "SITFD2,These bits specify the lower 16 bits of the FIFO data to be output through MSIOF_TXD"
group.long 0x50++0x03
line.long 0x00 "SITFDR2__16_L,SITFDR is a 32/16/8-bit write-only register that specifies the transmit FIFO data of the MSIOF"
hexmask.long.word 0x00 16.--31. 1. "Reserved0,Reserved"
hexmask.long.word 0x00 0.--15. 1. "SITFD2,These bits specify the lower 16 bits of the FIFO data to be output through MSIOF_TXD"
group.long 0x50++0x03
line.long 0x00 "SITFDR2__16_H,SITFDR is a 32/16/8-bit write-only register that specifies the transmit FIFO data of the MSIOF"
hexmask.long.word 0x00 16.--31. 1. "SITFD1,These bits specify the upper 16 bits of the FIFO data to be output through MSIOF_TXD"
hexmask.long.word 0x00 0.--15. 1. "Reserved1,Reserved"
group.long 0x50++0x03
line.long 0x00 "SITFDR2__8_LL,SITFDR is a 32/16/8-bit write-only register that specifies the transmit FIFO data of the MSIOF"
hexmask.long.word 0x00 16.--31. 1. "Reserved0,Reserved"
hexmask.long.byte 0x00 8.--15. 1. "Reserved1,Reserved"
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hexmask.long.byte 0x00 0.--7. 1. "SITFD2,These bits specify the lower 16 bits of the FIFO data to be output through MSIOF_TXD"
group.long 0x50++0x03
line.long 0x00 "SITFDR2__8_LH,SITFDR is a 32/16/8-bit write-only register that specifies the transmit FIFO data of the MSIOF"
hexmask.long.word 0x00 16.--31. 1. "Reserved0,Reserved"
hexmask.long.byte 0x00 8.--15. 1. "SITFD2,These bits specify the lower 16 bits of the FIFO data to be output through MSIOF_TXD"
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hexmask.long.byte 0x00 0.--7. 1. "Reserved1,Reserved"
group.long 0x50++0x03
line.long 0x00 "SITFDR2__8_HL,SITFDR is a 32/16/8-bit write-only register that specifies the transmit FIFO data of the MSIOF"
hexmask.long.byte 0x00 24.--31. 1. "Reserved0,Reserved"
hexmask.long.byte 0x00 16.--23. 1. "SITFD1,These bits specify the upper 16 bits of the FIFO data to be output through MSIOF_TXD"
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hexmask.long.word 0x00 0.--15. 1. "Reserved1,Reserved"
group.long 0x50++0x03
line.long 0x00 "SITFDR2__8_HH,SITFDR is a 32/16/8-bit write-only register that specifies the transmit FIFO data of the MSIOF"
hexmask.long.byte 0x00 24.--31. 1. "SITFD1,These bits specify the upper 16 bits of the FIFO data to be output through MSIOF_TXD"
hexmask.long.byte 0x00 16.--23. 1. "Reserved0,Reserved"
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hexmask.long.word 0x00 0.--15. 1. "Reserved1,Reserved"
group.long 0x60++0x03
line.long 0x00 "SIRFDR2,SIRFDR is a 32/16/8-bit read-only register that stores the receive FIFO data of the MSIOF"
hexmask.long.word 0x00 16.--31. 1. "SIRFD1,Store the upper 16 bits of the FIFO data received through MSIOF_RXD"
hexmask.long.word 0x00 0.--15. 1. "SIRFD2,Store the lower 16 bits of the FIFO data received through MSIOF_RXD"
group.long 0x60++0x03
line.long 0x00 "SIRFDR2__16_L,SIRFDR is a 32/16/8-bit read-only register that stores the receive FIFO data of the MSIOF"
hexmask.long.word 0x00 16.--31. 1. "Reserved0,Reserved"
hexmask.long.word 0x00 0.--15. 1. "SIRFD2,Store the lower 16 bits of the FIFO data received through MSIOF_RXD"
group.long 0x60++0x03
line.long 0x00 "SIRFDR2__16_H,SIRFDR is a 32/16/8-bit read-only register that stores the receive FIFO data of the MSIOF"
hexmask.long.word 0x00 16.--31. 1. "SIRFD1,Store the upper 16 bits of the FIFO data received through MSIOF_RXD"
hexmask.long.word 0x00 0.--15. 1. "Reserved1,Reserved"
group.long 0x60++0x03
line.long 0x00 "SIRFDR2__8_LL,SIRFDR is a 32/16/8-bit read-only register that stores the receive FIFO data of the MSIOF"
hexmask.long.word 0x00 16.--31. 1. "Reserved0,Reserved"
hexmask.long.byte 0x00 8.--15. 1. "Reserved1,Reserved"
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hexmask.long.byte 0x00 0.--7. 1. "SIRFD2,Store the lower 16 bits of the FIFO data received through MSIOF_RXD"
group.long 0x60++0x03
line.long 0x00 "SIRFDR2__8_LH,SIRFDR is a 32/16/8-bit read-only register that stores the receive FIFO data of the MSIOF"
hexmask.long.word 0x00 16.--31. 1. "Reserved0,Reserved"
hexmask.long.byte 0x00 8.--15. 1. "SIRFD2,Store the lower 16 bits of the FIFO data received through MSIOF_RXD"
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hexmask.long.byte 0x00 0.--7. 1. "Reserved1,Reserved"
group.long 0x60++0x03
line.long 0x00 "SIRFDR2__8_HL,SIRFDR is a 32/16/8-bit read-only register that stores the receive FIFO data of the MSIOF"
hexmask.long.byte 0x00 24.--31. 1. "Reserved0,Reserved"
hexmask.long.byte 0x00 16.--23. 1. "SIRFD1,Store the upper 16 bits of the FIFO data received through MSIOF_RXD"
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hexmask.long.word 0x00 0.--15. 1. "Reserved1,Reserved"
group.long 0x60++0x03
line.long 0x00 "SIRFDR2__8_HH,SIRFDR is a 32/16/8-bit read-only register that stores the receive FIFO data of the MSIOF"
hexmask.long.byte 0x00 24.--31. 1. "SIRFD1,Store the upper 16 bits of the FIFO data received through MSIOF_RXD"
hexmask.long.byte 0x00 16.--23. 1. "Reserved0,Reserved"
newline
hexmask.long.word 0x00 0.--15. 1. "Reserved1,Reserved"
tree.end
tree "MSIOF_INST_3"
base ad:0xE6C10000
group.long 0x00++0x03
line.long 0x00 "SITMDR13,SITMDR1 is a 32-bit readable/writable register that specifies the MSIOF transmit mode"
bitfld.long 0x00 31. "TRMD,Transfer Mode Selects the transfer mode" "0: Slave mode,1: Master mode"
bitfld.long 0x00 30. "PCON,Transfer Signal Connection" "0: Setting prohibited,1: MSIOF_SCK and MSIOF_SYNC are used as common"
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bitfld.long 0x00 28.--29. "SYNCMD,SYNC Mode These bits specify the mode for the MSIOF_SYNC signal" "0: Frame start synchronization,1: Reserved,2: Level mode/SPI,3: L/R mode"
bitfld.long 0x00 26.--27. "SYNCCH,Synchronization Signal Channel Select These bits are valid only in master mode" "0: The frame synchronization signal output at,1: The frame synchronization signal output at,2: The frame synchronization signal output at,3: Setting prohibited"
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bitfld.long 0x00 25. "SYNCAC,MSIOF_SYNC Polarity" "0: Active-high signal in synchronization pulse or,1: Active-low signal in synchronization pulse or"
bitfld.long 0x00 24. "BITLSB,MSB/LSB First" "0: MSB first,1: LSB first"
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rbitfld.long 0x00 23. "Reserved_23,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 20.--22. "DTDL,Data Pin Bit Delay for MSIOF_SYNC Pin The value specified with TXDIZ in SICTR is output during transmission" "0: No bit delay,1: 1-clock-cycle delay,2: 2-clock-cycle delay,?,?,5: 0.5-clock-cycle delay,6: 1.5-clock-cycle delay Other than above,?..."
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rbitfld.long 0x00 19. "Reserved_19,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 16.--18. "SYNCDL,Frame Synchronization Signal Timing Delay These bits extend the transmit frame synchronization signal" "0: No bit delay,1: 1-clock-cycle delay,2: 2-clock-cycle delay,3: 3-clock-cycle delay,?,5: 0.5-clock-cycle delay,6: 1.5-clock-cycle delay Other than above,?..."
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hexmask.long.word 0x00 4.--15. 1. "Reserved_4,Reserved These bits are always read as 0"
bitfld.long 0x00 2.--3. "FLD,Frame Synchronization Signal Interval Specify the minimum idle time between frames in the number of serial clock cycles" "0: 0-clock-cycle delay,1: 1-clock-cycle delay,2: 2-clock-cycle delay,3: 3-clock-cycle delay"
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rbitfld.long 0x00 1. "Reserved_1,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 0. "TXSTP,Transmission Stop" "0: Setting prohibited,1: Stop a frame from starting to transmit until"
group.long 0x04++0x03
line.long 0x00 "SITMDR23,SITMDR2 is a 32-bit readable/writable register that specifies the MSIOF transmit mode"
rbitfld.long 0x00 31. "Reserved_31,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 30. "GRP,Group Count" "0: Group count 1,1: Group count 2"
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rbitfld.long 0x00 29. "Reserved_29,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 24.--28. "BITLEN1,Data Size (8 to 32 bits) The word size (bits) of Group 1 is set to the value specified in these bits + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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rbitfld.long 0x00 22.--23. "Reserved_22,Reserved These bits are always read as 0" "0,1,2,3"
bitfld.long 0x00 16.--21. "WDLEN1,Word Count (1 to 64 words) The word count of Group 1 is set to WDLEN1 + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.word 0x00 0.--15. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x08++0x03
line.long 0x00 "SITMDR33,SITMDR3 is a 32-bit readable/writable register that specifies the MSIOF transmit mode"
rbitfld.long 0x00 29.--31. "Reserved_29,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24.--28. "BITLEN2,Word Size (8 to 32 bits) The word size (bits) of Group 2 is set to the value specified in these bits + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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rbitfld.long 0x00 22.--23. "Reserved_22,Reserved These bits are always read as 0" "0,1,2,3"
bitfld.long 0x00 16.--21. "WDLEN2,Word Count (1 to 64 words) The word count of Group 2 is set to WDLEN2 + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.word 0x00 0.--15. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x10++0x03
line.long 0x00 "SIRMDR13,SIRMDR1 is a 32-bit readable/writable register that specifies the MSIOF receive mode"
bitfld.long 0x00 31. "TRMD,Transfer Mode Selects the transfer mode" "0,1"
rbitfld.long 0x00 30. "Reserved_30,Reserved This bit is always read as 0" "0,1"
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bitfld.long 0x00 28.--29. "SYNCMD,SYNC Mode The mode setting in these bits should be the same as that in SITMDR1.SYNCMD" "0: Frame start synchronization,1: Reserved,2: Level mode/SPI,3: L/R mode"
rbitfld.long 0x00 26.--27. "Reserved_26,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 25. "SYNCAC,SYNC Polarity" "0: Active-high signal in synchronization pulse or,1: Active-low signal in synchronization pulse or"
bitfld.long 0x00 24. "BITLSB,MSB/LSB First" "0: MSB first,1: LSB first"
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rbitfld.long 0x00 23. "Reserved_23,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 20.--22. "DTDL,Data Pin Bit Delay for MSIOF_SYNC Pin" "0: No bit delay,1: 1-clock-cycle delay,2: 2-clock-cycle delay Other than above,?..."
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rbitfld.long 0x00 19. "Reserved_19,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 16.--18. "SYNCDL,MSIOF_SYNC Timing Delay These bits should always be set to B000" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x00 0.--15. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x14++0x03
line.long 0x00 "SIRMDR23,SIRMDR2 is a 32-bit readable/writable register that specifies the MSIOF receive mode"
rbitfld.long 0x00 31. "Reserved_31,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 30. "GRP,Group Count" "0: Group count 1,1: Group count 2 When using reception in"
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rbitfld.long 0x00 29. "Reserved_29,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 24.--28. "BITLEN1,Word Size (8 to 32 bits) The word size (bits) of Group 1 is set to the value specified in these bits + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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rbitfld.long 0x00 22.--23. "Reserved_22,Reserved These bits are always read as 0" "0,1,2,3"
bitfld.long 0x00 16.--21. "WDLEN1,Word Count (1 to 64 words) The word count of Group 1 is set to WDLEN1 + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.word 0x00 0.--15. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x18++0x03
line.long 0x00 "SIRMDR33,SIRMDR3 is a 32-bit readable/writable register that specifies the MSIOF receive mode"
rbitfld.long 0x00 29.--31. "Reserved_29,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24.--28. "BITLEN2,Word Size (8 to 32 bits) The word size (bits) of Group 2 is set to the value specified in these bits + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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rbitfld.long 0x00 22.--23. "Reserved_22,Reserved These bits are always read as 0" "0,1,2,3"
bitfld.long 0x00 16.--21. "WDLEN2,Word Count (1 to 64 words) The word count of Group 2 is set to WDLEN2 + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.long.word 0x00 0.--15. 1. "Reserved_0,Reserved These bits are always read as 0"
group.word 0x20++0x01
line.word 0x00 "SITSCR3,SITSCR is a 16-bit readable/writable register that specifies the conditions for generating transmit serial clock in master mode"
bitfld.word 0x00 14.--15. "MSSEL,Master Clock Source Select The master clock is the clock input to the baud rate generator" "0,1,2,3"
bitfld.word 0x00 13. "MSIMM,Master Clock Direct Select" "0: Selects the clock output from the baud rate,1: Setting prohibited"
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bitfld.word 0x00 8.--12. "BRPS,Prescaler Setting These bits specify the master clock (MSO?) division ratio in the count value of the prescaler in the baud rate generator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rbitfld.word 0x00 3.--7. "Reserved_3,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 0.--2. "BRDV,Baud Rate Generator's Division Ratio These bits specify the frequency division ratio for the output stage of the baud rate generator" "0: Prescaler output ? 1/2,1: Prescaler output ? 1/4,2: Prescaler output ? 1/8,3: Prescaler output ? 1/16,4: Prescaler output ? 1/32,5: Setting prohibited,6: Setting prohibited,7: Prescaler output ? 1/1"
group.long 0x28++0x03
line.long 0x00 "SICTR3,SICTR is a 32-bit readable/writable register that specifies the MSIOF operating state"
bitfld.long 0x00 30.--31. "TSCKIZ,Transmit Clock Input/output Polarity Select in SPI Mode When Transmission is Disabled When SPI mode is not used these bits must always be set to B00" "0: Inputs MSIOF_SCK when transmission is disabled,1: Setting prohibited,2: Inputs 0 through MSIOF_SCK when transmission is,3: Inputs 1 through MSIOF_SCK when transmission is"
bitfld.long 0x00 28.--29. "RSCKIZ,Receive Clock Polarity Select in SPI Mode Set the same value as the value specified by the TSCKIZ bits" "0,1,2,3"
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bitfld.long 0x00 27. "TEDG,Transmit Timing" "0: Outputs transmit data at the rising edge of the,1: Outputs transmit data at the falling edge of.."
bitfld.long 0x00 26. "REDG,Receive Timing" "0: Samples receive data at the falling edge of the,1: Samples receive data at the rising edge of the"
newline
rbitfld.long 0x00 24.--25. "Reserved_24,Reserved These bits are always read as 0" "0,1,2,3"
bitfld.long 0x00 22.--23. "TXDIZ,Pin Output When Transmission is Disabled These bits specify the MSIOF_TXD pin output state when transmission is disabled" "0: Outputs 0,1: Outputs 1,2: Setting prohibited,3: Setting prohibited"
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rbitfld.long 0x00 16.--21. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 15. "TSCKE,Transmit Serial Clock Output Enable This bit is valid in master mode" "0: Does not output MSIOF_SCK.(Outputs the value,1: Outputs MSIOF_SCK"
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bitfld.long 0x00 14. "TFSE,Transmit Frame Synchronization Signal Output Enable This bit is valid in master mode" "0: Does not output MSIOF_SYNC.(Outputs the value,1: Outputs MSIOF_SYNC"
bitfld.long 0x00 13. "RSCKE,Receive Serial Clock Output Enable The write value should always be 0" "0,1"
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bitfld.long 0x00 12. "RFSE,Receive Frame Synchronization Signal Output Enable The write value should always be 0" "0,1"
rbitfld.long 0x00 10.--11. "Reserved_10,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 9. "TXE,Transmit Enable When this bit is set to 1 the MSIOF starts data transmission from the beginning of the next frame (at the rising edge of the frame synchronization signal)" "0: Does not output MSIOF_TXD.(Outputs the value,1: Outputs MSIOF_TXD"
bitfld.long 0x00 8. "RXE,Receive Enable When this bit is set to 1 the MSIOF starts data reception from the beginning of the next frame (at the rising edge of the frame synchronization signal)" "0: Data is not received through MSIOF_RXD,1: Data can be received through MSIOF_RXD"
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rbitfld.long 0x00 2.--7. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 1. "TXRST,Transmit Reset When value 1 set to this bit becomes valid the MSIOF immediately sets transmit data through the MSIOF_TXD pin to 0 and initializes the transmit data registers and transmit-related status" "0: Transmit operation reset is completed,1: Transmit operation is being reset"
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bitfld.long 0x00 0. "RXRST,Receive Reset When value 1 set to this bit becomes valid the MSIOF immediately disables reception through the MSIOF_RXD pin and initializes the receive data registers and receive-related status" "0: Receive operation reset is completed,1: Receive operation is being reset"
group.long 0x30++0x03
line.long 0x00 "SIFCTR3,SIFCTR is a 32-bit readable/writable register that indicates the area available for the transmit/receive FIFO transfer"
bitfld.long 0x00 29.--31. "TFWM,Transmit FIFO Watermark A transfer request of the transmit FIFO is issued by the TDREQE bit in SIIER" "0: Issues a transfer request when 64 stages of the,1: Issues a transfer request when 32 or more..,2: Issues a transfer request when 24 or more..,3: Issues a transfer request when 16 or more..,4: Issues a transfer request when 12 or more..,5: Issues a transfer request when 8 or more stages,6: Issues a transfer request when 4 or more stages,7: Issues a transfer request when 1 or more stages"
rbitfld.long 0x00 27.--28. "Reserved_27,Reserved These bits are always read as 0" "0,1,2,3"
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hexmask.long.byte 0x00 20.--26. 1. "TFUA,Transmit FIFO Usable Area Indicate the number of words that can be transferred by the CPU or DMAC as B'000 0000 (full) to B'100 0000 (empty)"
rbitfld.long 0x00 16.--19. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 13.--15. "RFWM,Receive FIFO Watermark A transfer request of the receive FIFO is issued by the RDREQE bit in SIIER" "0: Issues a transfer request when 1 stage or more,1: Issues a transfer request when 4 or more stages,2: Issues a transfer request when 8 or more stages,3: Issues a transfer request when 16 or more..,4: Issues a transfer request when 32 or more..,5: Issues a transfer request when 64 or more..,6: Issues a transfer request when 128 or more,7: Issues a transfer request when 256 stages of.."
hexmask.long.word 0x00 4.--12. 1. "RFUA,Receive FIFO Usable Area Indicate the number of words that can be transferred by the CPU or DMAC as B'0 0000 0000 (empty) to B'1 0000 0000 (full)"
newline
rbitfld.long 0x00 0.--3. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x40++0x03
line.long 0x00 "SISTR3,Each bit in SISTR becomes an MSIOF interrupt source when the corresponding bit in SIIER is set to 1"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved These bits are always read as 0" "0,1,2,3"
bitfld.long 0x00 29. "TFEMP,Transmit FIFO Empty This bit is set to 1 when the TXE bit in SICTR is 1 and transmit FIFO is empty" "0: Transmit FIFO is not empty,1: Transmit FIFO is empty"
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rbitfld.long 0x00 28. "TDREQ,Transmit Data Transfer Request This bit is set when the empty space in the transmit FIFO exceeds the size specified by the TFWM bits in SIFCTR" "0: The size of empty space in the transmit FIFO..,1: The size of empty space in the transmit FIFO.."
rbitfld.long 0x00 24.--27. "Reserved_24,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 23. "TEOF,Frame Transmission End This bit is set when one-frame data transmission is completed" "0: One-frame transmission end is not detected,1: One-frame transmission end is detected"
rbitfld.long 0x00 22. "Reserved_22,Reserved This bit is always read as 0" "0,1"
newline
bitfld.long 0x00 21. "TFSERR,Transmit Frame Synchronization Error This bit is set when the next transmit frame synchronization timing arrives before the previous data transmission has been completed" "0: No transmit frame synchronization error has,1: A transmit frame synchronization error has"
bitfld.long 0x00 20. "TFOVF,Transmit FIFO Overflow A transmit FIFO overflow means that there has been an attempt to write to SITFDR when the transmit FIFO is full" "0: No transmit FIFO overflow has occurred,1: A transmit FIFO overflow has occurred"
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bitfld.long 0x00 19. "TFUDF,Transmit FIFO Underflow A transmit FIFO underflow means that loading for transmission has occurred when the transmit FIFO is empty" "0: No transmit FIFO underflow has occurred,1: A transmit FIFO underflow has occurred"
rbitfld.long 0x00 14.--18. "Reserved_14,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 13. "RFFUL,Receive FIFO Full This bit is valid when the RXE bit in SICTR is 1" "0: Receive FIFO is not full,1: Receive FIFO is full"
rbitfld.long 0x00 12. "RDREQ,Receive Data Transfer Request This bit is set when the valid data space in the receive FIFO exceeds the size specified by the RFWM bits in SIFCTR" "0: The size of valid data space in the receive..,1: The size of valid data space in the receive.."
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rbitfld.long 0x00 8.--11. "Reserved_8,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 7. "REOF,Frame Reception End The MSIOF issues the frame reception end flag upon completion of one-frame data reception" "0: One-frame reception end is not detected,1: One-frame reception end is detected"
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rbitfld.long 0x00 6. "Reserved_6,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 5. "RFSERR,Receive Frame Synchronization Error A receive frame synchronization error occurs when the next receive frame synchronization timing arrives before the previous data reception has been completed" "0: No receive frame synchronization error has,1: A receive frame synchronization error has.."
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bitfld.long 0x00 4. "RFUDF,Receive FIFO Underflow A receive FIFO underflow means that reading of SIRFDR has occurred when the receive FIFO is empty" "0: No receive FIFO underflow has occurred,1: A receive FIFO underflow has occurred"
bitfld.long 0x00 3. "RFOVF,Receive FIFO Overflow A receive FIFO overflow means that writing has been caused by receiving operation when the receive FIFO is full" "0: No receive FIFO overflow has occurred,1: A receive FIFO overflow has occurred"
newline
eventfld.long 0x00 0.--2. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
group.long 0x44++0x03
line.long 0x00 "SIIER3,"
bitfld.long 0x00 31. "TDMAE,Transmit Data DMA Transfer Request Enable Specifies whether to send an interrupt as an interrupt request to the CPU or a transfer request to the DMAC" "0: Sends an interrupt request to the CPU,1: Sends a DMA transfer request to the DMAC"
rbitfld.long 0x00 30. "Reserved_30,Reserved This bit is always read as 0" "0,1"
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bitfld.long 0x00 29. "TFEMPE,Transmit FIFO Empty Enable" "0: Disables interrupts due to transmit FIFO empty,1: Enables interrupts due to transmit FIFO empty"
bitfld.long 0x00 28. "TDREQE,Transmit Data Transfer Request Enable" "0: Disables interrupts due to transmit data,1: Enables interrupts due to transmit data.."
newline
rbitfld.long 0x00 24.--27. "Reserved_24,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 23. "TEOFE,Frame Transmission End Enable" "0: Disables a frame transmission end interrupt,1: Enables a frame transmission end interrupt"
newline
rbitfld.long 0x00 22. "Reserved_22,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 21. "TFSERRE,Transmit Frame Synchronization Error Enable" "0: Disables interrupts due to transmit frame,1: Enables interrupts due to transmit frame"
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bitfld.long 0x00 20. "TFOVFE,Transmit FIFO Overflow Enable" "0: Disables interrupts due to transmit FIFO..,1: Enables interrupts due to transmit FIFO.."
bitfld.long 0x00 19. "TFUDFE,Transmit FIFO Underflow Enable" "0: Disables interrupts due to transmit FIFO..,1: Enables interrupts due to transmit FIFO.."
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rbitfld.long 0x00 16.--18. "Reserved_16,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 15. "RDMAE,Receive Data DMA Transfer Request Enable Specifies whether to send an interrupt as an interrupt request to the CPU or a transfer request to the DMAC" "0: Sends an interrupt request to the CPU,1: Sends a DMA transfer request to the DMAC"
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rbitfld.long 0x00 14. "Reserved_14,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 13. "RFFULE,Receive FIFO Full Enable" "0: Disables interrupts due to receive FIFO full,1: Enables interrupts due to receive FIFO full"
newline
bitfld.long 0x00 12. "RDREQE,Receive Data Transfer Request Enable" "0: Disables interrupts due to receive data..,1: Enables interrupts due to receive data transfer"
rbitfld.long 0x00 8.--11. "Reserved_8,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 7. "REOFE,Frame Reception End Enable" "0: Disables a frame reception end interrupt,1: Enables a frame reception end interrupt"
rbitfld.long 0x00 6. "Reserved_6,Reserved This bit is always read as 0" "0,1"
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bitfld.long 0x00 5. "RFSERRE,Receive Frame Synchronization Error Enable" "0: Disables interrupts due to receive frame,1: Enables interrupts due to receive frame"
bitfld.long 0x00 4. "RFUDFE,Receive FIFO Underflow Enable" "0: Disables interrupts due to receive FIFO..,1: Enables interrupts due to receive FIFO.."
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bitfld.long 0x00 3. "RFOVFE,Receive FIFO Overflow Enable" "0: Disables interrupts due to receive FIFO..,1: Enables interrupts due to receive FIFO overflow"
rbitfld.long 0x00 0.--2. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
group.long 0x50++0x03
line.long 0x00 "SITFDR3,SITFDR is a 32/16/8-bit write-only register that specifies the transmit FIFO data of the MSIOF"
hexmask.long.word 0x00 16.--31. 1. "SITFD1,These bits specify the upper 16 bits of the FIFO data to be output through MSIOF_TXD"
hexmask.long.word 0x00 0.--15. 1. "SITFD2,These bits specify the lower 16 bits of the FIFO data to be output through MSIOF_TXD"
group.long 0x50++0x03
line.long 0x00 "SITFDR3__16_L,SITFDR is a 32/16/8-bit write-only register that specifies the transmit FIFO data of the MSIOF"
hexmask.long.word 0x00 16.--31. 1. "Reserved0,Reserved"
hexmask.long.word 0x00 0.--15. 1. "SITFD2,These bits specify the lower 16 bits of the FIFO data to be output through MSIOF_TXD"
group.long 0x50++0x03
line.long 0x00 "SITFDR3__16_H,SITFDR is a 32/16/8-bit write-only register that specifies the transmit FIFO data of the MSIOF"
hexmask.long.word 0x00 16.--31. 1. "SITFD1,These bits specify the upper 16 bits of the FIFO data to be output through MSIOF_TXD"
hexmask.long.word 0x00 0.--15. 1. "Reserved1,Reserved"
group.long 0x50++0x03
line.long 0x00 "SITFDR3__8_LL,SITFDR is a 32/16/8-bit write-only register that specifies the transmit FIFO data of the MSIOF"
hexmask.long.word 0x00 16.--31. 1. "Reserved0,Reserved"
hexmask.long.byte 0x00 8.--15. 1. "Reserved1,Reserved"
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hexmask.long.byte 0x00 0.--7. 1. "SITFD2,These bits specify the lower 16 bits of the FIFO data to be output through MSIOF_TXD"
group.long 0x50++0x03
line.long 0x00 "SITFDR3__8_LH,SITFDR is a 32/16/8-bit write-only register that specifies the transmit FIFO data of the MSIOF"
hexmask.long.word 0x00 16.--31. 1. "Reserved0,Reserved"
hexmask.long.byte 0x00 8.--15. 1. "SITFD2,These bits specify the lower 16 bits of the FIFO data to be output through MSIOF_TXD"
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hexmask.long.byte 0x00 0.--7. 1. "Reserved1,Reserved"
group.long 0x50++0x03
line.long 0x00 "SITFDR3__8_HL,SITFDR is a 32/16/8-bit write-only register that specifies the transmit FIFO data of the MSIOF"
hexmask.long.byte 0x00 24.--31. 1. "Reserved0,Reserved"
hexmask.long.byte 0x00 16.--23. 1. "SITFD1,These bits specify the upper 16 bits of the FIFO data to be output through MSIOF_TXD"
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hexmask.long.word 0x00 0.--15. 1. "Reserved1,Reserved"
group.long 0x50++0x03
line.long 0x00 "SITFDR3__8_HH,SITFDR is a 32/16/8-bit write-only register that specifies the transmit FIFO data of the MSIOF"
hexmask.long.byte 0x00 24.--31. 1. "SITFD1,These bits specify the upper 16 bits of the FIFO data to be output through MSIOF_TXD"
hexmask.long.byte 0x00 16.--23. 1. "Reserved0,Reserved"
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hexmask.long.word 0x00 0.--15. 1. "Reserved1,Reserved"
group.long 0x60++0x03
line.long 0x00 "SIRFDR3,SIRFDR is a 32/16/8-bit read-only register that stores the receive FIFO data of the MSIOF"
hexmask.long.word 0x00 16.--31. 1. "SIRFD1,Store the upper 16 bits of the FIFO data received through MSIOF_RXD"
hexmask.long.word 0x00 0.--15. 1. "SIRFD2,Store the lower 16 bits of the FIFO data received through MSIOF_RXD"
group.long 0x60++0x03
line.long 0x00 "SIRFDR3__16_L,SIRFDR is a 32/16/8-bit read-only register that stores the receive FIFO data of the MSIOF"
hexmask.long.word 0x00 16.--31. 1. "Reserved0,Reserved"
hexmask.long.word 0x00 0.--15. 1. "SIRFD2,Store the lower 16 bits of the FIFO data received through MSIOF_RXD"
group.long 0x60++0x03
line.long 0x00 "SIRFDR3__16_H,SIRFDR is a 32/16/8-bit read-only register that stores the receive FIFO data of the MSIOF"
hexmask.long.word 0x00 16.--31. 1. "SIRFD1,Store the upper 16 bits of the FIFO data received through MSIOF_RXD"
hexmask.long.word 0x00 0.--15. 1. "Reserved1,Reserved"
group.long 0x60++0x03
line.long 0x00 "SIRFDR3__8_LL,SIRFDR is a 32/16/8-bit read-only register that stores the receive FIFO data of the MSIOF"
hexmask.long.word 0x00 16.--31. 1. "Reserved0,Reserved"
hexmask.long.byte 0x00 8.--15. 1. "Reserved1,Reserved"
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hexmask.long.byte 0x00 0.--7. 1. "SIRFD2,Store the lower 16 bits of the FIFO data received through MSIOF_RXD"
group.long 0x60++0x03
line.long 0x00 "SIRFDR3__8_LH,SIRFDR is a 32/16/8-bit read-only register that stores the receive FIFO data of the MSIOF"
hexmask.long.word 0x00 16.--31. 1. "Reserved0,Reserved"
hexmask.long.byte 0x00 8.--15. 1. "SIRFD2,Store the lower 16 bits of the FIFO data received through MSIOF_RXD"
newline
hexmask.long.byte 0x00 0.--7. 1. "Reserved1,Reserved"
group.long 0x60++0x03
line.long 0x00 "SIRFDR3__8_HL,SIRFDR is a 32/16/8-bit read-only register that stores the receive FIFO data of the MSIOF"
hexmask.long.byte 0x00 24.--31. 1. "Reserved0,Reserved"
hexmask.long.byte 0x00 16.--23. 1. "SIRFD1,Store the upper 16 bits of the FIFO data received through MSIOF_RXD"
newline
hexmask.long.word 0x00 0.--15. 1. "Reserved1,Reserved"
group.long 0x60++0x03
line.long 0x00 "SIRFDR3__8_HH,SIRFDR is a 32/16/8-bit read-only register that stores the receive FIFO data of the MSIOF"
hexmask.long.byte 0x00 24.--31. 1. "SIRFD1,Store the upper 16 bits of the FIFO data received through MSIOF_RXD"
hexmask.long.byte 0x00 16.--23. 1. "Reserved0,Reserved"
newline
hexmask.long.word 0x00 0.--15. 1. "Reserved1,Reserved"
tree.end
tree.end
tree "RPC"
base ad:0xEE200000
group.long 0x00++0x03
line.long 0x00 "CMNCR,CMNCR is a 32-bit register that controls the SPI multi I/O bus controller"
bitfld.long 0x00 31. "MD,Operating Mode Switch Switches the operating modes" "0: External address space read mode,1: Manual mode"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved These bits are always read as initial value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 24. "Reserved_24,Reserved This bit is always read as initial value" "0,1"
bitfld.long 0x00 22.--23. "MOIIO3_1_0,QSPIn_SSL Output Idle Value Fix QSPIn_IO3 Fixes output value of QSPIn_IO3 in QSPIn_SSL negation period" "0: 0,1: 1,2: Output value is the last bit value of the,3: Hi-Z Note1"
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bitfld.long 0x00 20.--21. "MOIIO2_1_0,QSPIn_SSL Output Idle Value Fix QSPIn_IO2 Fixes output value of QSPIn_IO2 in QSPIn_SSL negation period" "0: Output value 0,1: Output value 1,2: Output value is the last bit value of the,3: Output value Hi-Z Note1"
bitfld.long 0x00 18.--19. "MOIIO1_1_0,QSPIn_SSL Output Idle Value Fix QSPIn_IO1 Fixes output value of QSPIn_IO1 in QSPIn_SSL negation period" "0: Output value 0,1: Output value 1,2: Output value is the last bit value of the,3: Output value Hi-Z Note1"
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bitfld.long 0x00 16.--17. "MOIIO0_1_0,QSPIn_SSL Output Idle Value Fix QSPIn_IO0 Fixes output value of QSPIn_IO0 in QSPIn_SSL negation period" "0: Output value 0,1: Output value 1,2: Output value is the last bit value of the,3: Output value Hi-Z Note1"
rbitfld.long 0x00 10.--15. "Reserved_10,Reserved These bits are always read as initial value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--9. "IO0FV_1_0,QSPIn_IO0 Fixed Value for 1-bit Size Input Fixes the output value of QSPIn_IO0 pin for 1-bit size input" "0: Output value 0,1: Output value 1,2: Output value is the last bit value of the,3: Output value Hi-Z"
rbitfld.long 0x00 2.--7. "Reserved_2,Reserved These bits are always read as initial value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0.--1. "BSZ_1_0,Data Bus Size Specifies the number of serial flash memory devices to be connected" "0: Serial flash memory x 1,1: Serial flash memory x 2 or HyperFlash x 1 or,?..."
group.long 0x04++0x03
line.long 0x00 "SSLDR,SSLDR is a 32-bit register that adjusts the timing between the QSPIn_SSL signal and the QSPIn_SPCLK signal"
hexmask.long.word 0x00 19.--31. 1. "Reserved_19,Reserved These bits are always read as 0"
bitfld.long 0x00 16.--18. "SPNDL_2_0,Next Access Delay Sets the period from transfer end to next transfer start (next access)" "0: 1 cycle of QSPIn_SPCLK,1: 2 cycles of QSPIn_SPCLK,2: 3 cycles of QSPIn_SPCLK,3: 4 cycles of QSPIn_SPCLK,4: 5 cycles of QSPIn_SPCLK,5: 6 cycles of QSPIn_SPCLK,6: 7 cycles of QSPIn_SPCLK,7: 8 cycles of QSPIn_SPCLK"
newline
rbitfld.long 0x00 11.--15. "Reserved_11,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "SLNDL_2_0,QSPIn_SSL Negation Delay Sets the period from the time the last QSPIn_SPCLK edge is sent of a transfer to QSPIn_SSL pin negation (QSPIn_SSL negation delay)" "?,?,?,?,4: 5.5 cycles of QSPIn_SPCLK,5: 6.5 cycles of QSPIn_SPCLK,6: 7.5 cycles of QSPIn_SPCLK,7: 8.5 cycles of QSPIn_SPCLK Other than above"
newline
rbitfld.long 0x00 3.--7. "Reserved_3,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--2. "SCKDL_2_0,Clock Delay Sets the period from QSPIn_SSL pin assertion to QSPIn_SPCLK oscillation (clock delay)" "0: 1 cycle of QSPIn_SPCLK,1: 2 cycles of QSPIn_SPCLK,2: 3 cycles of QSPIn_SPCLK,3: 4 cycles of QSPIn_SPCLK,4: 5 cycles of QSPIn_SPCLK,5: 6 cycles of QSPIn_SPCLK,6: 7 cycles of QSPIn_SPCLK,7: 8 cycles of QSPIn_SPCLK"
group.long 0x0C++0x03
line.long 0x00 "DRCR,DRCR is a 32-bit register that sets the operation in the external address space read mode"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as initial value"
bitfld.long 0x00 24. "SSLN,QSPIn_SSL Negation Asserted QSPIn_SSL can be negated by writing 1 to this bit when both the RBE and SSLE bits are 1" "0,1"
newline
rbitfld.long 0x00 21.--23. "Reserved_21,Reserved These bits are always read as initial value" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--20. "RBURST_4_0,Read Data Burst Length Sets the burst length (data unit count) when reading" "0: 1 data unit 0,1: 2 continuous data units,?,?,?,?,?,?,?,?,?,?,?,?,14: 31 continuous data units 1,15: 32 continuous data units One data unit is 64,?..."
newline
rbitfld.long 0x00 10.--15. "Reserved_10,Reserved These bits are always read as initial value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 9. "RCF,Read Cache Flush When 1 is written to this bit all the entries in the read cache are cleared" "0,1"
newline
bitfld.long 0x00 8. "RBE,Read Burst Enables or disables burst" "0: Normal read Data is read according to the..,1: Burst read As many data units as the burst.."
hexmask.long.byte 0x00 1.--7. 1. "Reserved_1,Reserved These bits are always read as initial value"
newline
bitfld.long 0x00 0. "SSLE,QSPIn_SSL Negation Setting Sets the conditions for QSPIn_SSL negation during read burst" "0: QSPIn_SSL is negated after transfer of data set,1: QSPIn_SSL is negated when the accessed address"
group.long 0x10++0x03
line.long 0x00 "DRCMR,DRCMR is a 32-bit register that sets the commands issued in external address space read mode"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as initial value"
hexmask.long.byte 0x00 16.--23. 1. "CMD_7_0,Command Sets the command"
newline
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as initial value"
hexmask.long.byte 0x00 0.--7. 1. "OCMD_7_0,Optional Command Sets the optional command"
group.long 0x14++0x03
line.long 0x00 "DREAR,DREAR is a 32-bit register that sets the address when the serial flash address is output in 32-bit mode"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 16.--23. 1. "EAV_7_0,32-Bit Extended Upper Address Fixed Value Sets the upper address bit values of the external address specified by the EAC[2:0] bits when the serial flash address is output in 32-bit mode"
newline
hexmask.long.word 0x00 3.--15. 1. "Reserved_3,Reserved These bits are always read as 0"
bitfld.long 0x00 0.--2. "EAC_2_0,32-Bit Extended External Address Valid Range Sets the range of the external address to be used as serial flash address when the serial flash address is output in 32-bit mode" "0: External address bits [24:0] enabled,1: External address bits [25:0] enabled Other than,?..."
group.long 0x18++0x03
line.long 0x00 "DROPR,DROPR is a 32-bit register that sets the option data in external address space read mode"
hexmask.long.byte 0x00 24.--31. 1. "OPD3_7_0,Option Data 3 Sets the option data 3"
hexmask.long.byte 0x00 16.--23. 1. "OPD2_7_0,Option Data 2 Sets the option data 2"
newline
hexmask.long.byte 0x00 8.--15. 1. "OPD1_7_0,Option Data 1 Sets the option data 1"
hexmask.long.byte 0x00 0.--7. 1. "OPD0_7_0,Option Data 0 Sets the option data 0"
group.long 0x1C++0x03
line.long 0x00 "DRENR,DRENR is a 32-bit register that sets the bit size of the command optional command address option data and read data in external address space read mode and enables output of data other than read data"
bitfld.long 0x00 30.--31. "CDB_1_0,Command Bit Size Sets the command size in bit units" "0: 1 bit,?,2: 4 bits Other,?..."
bitfld.long 0x00 28.--29. "OCDB_1_0,Optional Command Bit Size Sets the optional command size in bit units" "0: 1 bit,?,2: 4 bits Other,?..."
newline
rbitfld.long 0x00 26.--27. "Reserved_26,Reserved These bits are always read as initial value" "0,1,2,3"
bitfld.long 0x00 24.--25. "ADB_1_0,Address Bit Size Sets the address size in bit units" "0: 1 bit,?,2: 4 bits Other,?..."
newline
rbitfld.long 0x00 22.--23. "Reserved_22,Reserved These bits are always read as initial value" "0,1,2,3"
bitfld.long 0x00 20.--21. "OPDB_1_0,Option Data Bit Size Sets the option data size in bit units" "0: 1 bit,?,2: 4 bits Other,?..."
newline
rbitfld.long 0x00 18.--19. "Reserved_18,Reserved These bits are always read as initial value" "0,1,2,3"
bitfld.long 0x00 16.--17. "DRDB_1_0,Data Read Size in Bit Units Sets the data read size in bit units" "0: 1 bit,?,2: 4 bits Other,?..."
newline
bitfld.long 0x00 15. "DME,Dummy Cycle Enable Enables or disables insertion of a dummy cycle" "0: Insertion of a dummy cycle is disabled,1: Insertion of a dummy cycle is enabled"
bitfld.long 0x00 14. "CDE,Command Enable Enables or disables output of commands" "0: Output disabled,1: Output enabled"
newline
rbitfld.long 0x00 13. "Reserved_13,Reserved This bit is always read as initial value" "0,1"
bitfld.long 0x00 12. "OCDE,Optional Command Enable Enables or Disables output of Optional commands" "0: Output disabled,1: Optional command output enabled"
newline
bitfld.long 0x00 8.--11. "ADE_3_0,Address Enable Sets the address to be output" "0: Output disabled,?,?,?,4: HyperFlash protocol is output,?,?,7: Address[24:1] is output,?,?,?,?,12: Octal-SPI with 8-8-8 protocol is output,?,?,15: Address[32:1] is output"
bitfld.long 0x00 4.--7. "OPDE_3_0,Option Data Enable Sets the option data to be output" "0: Output disabled,?,?,?,?,?,?,?,8: OPD3 is output,?,?,?,12: OPD3 and OPD2 are output,?,14: OPD3 OPD2 and OPD1 are output,15: OPD3 OPD2 OPD1 and OPD0 are output"
newline
rbitfld.long 0x00 0.--3. "Reserved_0,Reserved These bits are always read as 0 initial value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x20++0x03
line.long 0x00 "SMCR,SMCR is a 32-bit register that sets the operation in manual mode"
hexmask.long.tbyte 0x00 9.--31. 1. "Reserved_9,Reserved These bits are always read as 0"
bitfld.long 0x00 8. "SSLKP,QSPIn_SSL Signal Level Determines the QSPIn_SSL status after the end of transfer" "0: QSPIn_SSL signal is negated at the end of..,1: QSPIn_SSL signal level is maintained from the"
newline
rbitfld.long 0x00 3.--7. "Reserved_3,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 2. "SPIRE,Data Read Enable Enables reading in manual mode" "0: Data reading disabled,1: Data reading enabled When the transfer data bit"
newline
bitfld.long 0x00 1. "SPIWE,Data Write Enable Enables writing in manual mode" "0: Data writing disabled,1: Data writing enabled When the transfer data bit"
bitfld.long 0x00 0. "SPIE,SPI Data Transfer Enable Data is transferred by setting this bit to 1" "0,1"
group.long 0x24++0x03
line.long 0x00 "SMCMR,SMCMR is a 32-bit register that sets the commands issued in manual mode"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 16.--23. 1. "CMD_7_0,Command Sets the command"
newline
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "OCMD_7_0,Optional Command Sets the optional command"
group.long 0x28++0x03
line.long 0x00 "SMADR,SMADR is a 32-bit register that sets the addresses in manual mode"
hexmask.long.byte 0x00 24.--31. 1. "ADR_31_24,Address Sets the value of bits 31 to 24 when the serial flash address is output in 32-bit units"
hexmask.long.tbyte 0x00 0.--23. 1. "ADR_23_0,Address Sets the address"
group.long 0x2C++0x03
line.long 0x00 "SMOPR,SMOPR is a 32-bit register that sets the option data in manual mode"
hexmask.long.byte 0x00 24.--31. 1. "OPD3_7_0,Option Data 3 Sets the option data 3"
hexmask.long.byte 0x00 16.--23. 1. "OPD2_7_0,Option Data 2 Sets the option data 2"
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hexmask.long.byte 0x00 8.--15. 1. "OPD1_7_0,Option Data 1 Sets the option data 1"
hexmask.long.byte 0x00 0.--7. 1. "OPD0_7_0,Option Data 0 Sets the option data 0"
group.long 0x30++0x03
line.long 0x00 "SMENR,SMENR is a 32-bit register that sets the bit size of the command optional command address option data and transfer data in manual mode and enables their output"
bitfld.long 0x00 30.--31. "CDB_1_0,Command Bit Size Sets the command size in bit units" "0: 1 bit,?,2: 4 bits Other,?..."
bitfld.long 0x00 28.--29. "OCDB_1_0,Optional Command Bit Size Sets the optional command size in bit units" "0: 1 bit,?,2: 4 bits Other,?..."
newline
rbitfld.long 0x00 26.--27. "Reserved_26,Reserved These bits are always read as 0" "0,1,2,3"
bitfld.long 0x00 24.--25. "ADB_1_0,Address Bit Size Sets the address size in bit units" "0: 1 bit,?,2: 4 bits Other,?..."
newline
rbitfld.long 0x00 22.--23. "Reserved_22,Reserved These bits are always read as 0" "0,1,2,3"
bitfld.long 0x00 20.--21. "OPDB_1_0,Option Data Bit Size Sets the option data size in bit units" "0: 1 bit,?,2: 4 bits Other,?..."
newline
rbitfld.long 0x00 18.--19. "Reserved_18,Reserved These bits are always read as 0" "0,1,2,3"
bitfld.long 0x00 16.--17. "SPIDB_1_0,Transfer Data Bit Size Sets the transfer data size in bit units" "0: 1 bit,?,2: 4 bits Other,?..."
newline
bitfld.long 0x00 15. "DME,Dummy Cycle Enable Enables or disables insertion of the dummy cycle before the read data" "0: Dummy cycle insertion disabled,1: Dummy cycle insertion enabled"
bitfld.long 0x00 14. "CDE,Command Enable Sets the command to be output" "0: Output disabled,1: Output enabled"
newline
rbitfld.long 0x00 13. "Reserved_13,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 12. "OCDE,Optional Command Enable Sets the optional command to be output" "0: Optional command output disabled,1: Optional command output enabled"
newline
bitfld.long 0x00 8.--11. "ADE_3_0,Address Enable Sets the address to be output" "0: Output disabled,?,?,?,4: HyperFlash protocol is output,?,6: ADR[23:8] is output,7: ADR[23:0] is output,?,?,?,?,12: Octal-SPI with 8-8-8 protocol is output,?,?,15: ADR[31:0] is output Other than above"
bitfld.long 0x00 4.--7. "OPDE_3_0,Option Data Enable Sets the option data to be output" "0: Output disabled,?,?,?,?,?,?,?,8: OPD3 is output,?,?,?,12: OPD3 and OPD2 are output,?,14: OPD3 OPD2 and OPD1 are output,15: OPD3 OPD2 OPD1 and OPD0 are output"
newline
bitfld.long 0x00 0.--3. "SPIDE_3_0,Transfer Data Enable Sets valid transfer data" "0: Not transferred,?,?,?,?,?,?,?,8: 16 bits transferred (enables data at..,?,?,?,12: 32 bits transferred (enables data at..,?,?,15: 64 bits transferred (enables data at.."
group.long 0x38++0x03
line.long 0x00 "SMRDR0,SMRDR0 is a 32-bit register that holds the read data in manual mode"
abitfld.long 0x00 0.--31. "RDATA0_31_0,Read Data Holds the data read in manual mode" "0x00000000=0: Read data[31:0] BSZ[1:0] =,0x00000001=1: Read data[63:32]"
group.long 0x3C++0x03
line.long 0x00 "SMRDR1,SMRDR1 is a 32-bit register that holds the read data in manual mode"
abitfld.long 0x00 0.--31. "RDATA1_31_0,Read Data Holds the data read in manual mode" "0x00000000=0: Bits in this register are disabled,0x00000001=1: Read data[31:0]"
group.long 0x40++0x03
line.long 0x00 "SMWDR0,SMWDR0 is a 32-bit register that sets the write data in manual mode"
abitfld.long 0x00 0.--31. "WDATA0_31_0,Write Data Holds the data to be written in manual mode" "0x00000000=0: Write data[31:0],0x00000001=1: Write data[63:32]"
group.long 0x44++0x03
line.long 0x00 "SMWDR1,SMWDR1 is a 32-bit register that sets the write data in manual mode"
abitfld.long 0x00 0.--31. "WDATA1_31_0,Write Data Holds the data to be written in manual mode" "0x00000000=0: Bits in this register are disabled,0x00000001=1: Write data[31:0]"
group.long 0x48++0x03
line.long 0x00 "CMNSR,CMNSR is a 32-bit register that holds flags indicating the operating state"
hexmask.long 0x00 2.--31. 1. "Reserved_2,Reserved These bits are always read as 0"
rbitfld.long 0x00 1. "SSLF,QSPIn_SSL Pin State Monitor" "0: QSPIn_SSL pin is negated,1: QSPIn_SSL pin is asserted"
newline
rbitfld.long 0x00 0. "TEND,Transfer End Flag Indicates whether the data transfer has ended" "0: Indicates that data transfer is in progress,1: Indicates that data transfer has ended"
group.long 0x58++0x03
line.long 0x00 "DRDMCR,DRDMCR is a 32-bit register that sets the size and number of dummy cycles to be inserted in external address space read mode"
hexmask.long 0x00 5.--31. 1. "Reserved_5,Reserved These bits are always read as initial value"
bitfld.long 0x00 0.--4. "DMCYC_4_0,Number of Dummy Cycles Setting Sets the number of dummy cycles to be inserted when the DME bit in the data read enable setting register (DRENR) is 1" "0: 1 cycle 0,1: 2 cycles 0,?,?,?,?,?,?,?,?,10: 19 cycles 1,11: 20 cycles Other than above,?..."
group.long 0x5C++0x03
line.long 0x00 "DRDRENR,DRDRENR is a 32-bit register that specifies the SDR or DDR transfer of the address option data and read data in external address space read mode"
hexmask.long.tbyte 0x00 15.--31. 1. "Reserved_15,Reserved These bits are always read as initial value"
bitfld.long 0x00 12.--14. "HYPE,HyperFlash or Octal-SPI flash in DDR mode Enable" "0: SPI flash mode Other than above,?,?,?,4: Octal-SPI flash to issue only command in DDR..,5: HyperFlash or Octal-SPI flash in DDR mode,?..."
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved These bits are always read as initial value" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8. "ADDRE,Address DDR Enable Specifies the SDR or DDR transfer of the address" "0: SDR transfer,1: DDR transfer"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as initial value" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4. "OPDRE,Option Data DDR Enable Specifies the SDR or DDR transfer of the option data" "0: SDR transfer,1: DDR transfer"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as initial value" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "DRDRE,Data Read DDR Enable Specifies the SDR or DDR transfer of the data" "0: SDR transfer,1: DDR transfer"
group.long 0x60++0x03
line.long 0x00 "SMDMCR,SMDMCR is a 32-bit register that sets the size and number of dummy cycles to be inserted in manual mode"
hexmask.long 0x00 5.--31. 1. "Reserved_5,Reserved These bits are always read as 0"
bitfld.long 0x00 0.--4. "DMCYC_4_0,Number of Dummy Cycles Setting Sets the number of dummy cycles to be inserted when the DME bit in the manual mode enable setting register (SMENR) is 1" "0: 1 cycle 0,1: 2 cycles 0,?,?,?,?,?,?,?,?,10: 19 cycles 1,11: 20 cycles Other than above,?..."
group.long 0x64++0x03
line.long 0x00 "SMDRENR,SMDRENR is a 32-bit register that specifies the SDR or DDR transfer of the address option data and data for transfer in manual mode"
hexmask.long.tbyte 0x00 15.--31. 1. "Reserved_15,Reserved These bits are always read as 0"
bitfld.long 0x00 12.--14. "HYPE,HyperFlash or Octal-SPI flash in DDR mode Enable" "0: SPI flash mode Other than above,?,?,?,4: Octal-SPI flash to issue only command in DDR..,5: HyperFlash or Octal-SPI flash in DDR mode,?..."
newline
rbitfld.long 0x00 9.--11. "Reserved_9,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8. "ADDRE,Address DDR Enable Specifies the SDR or DDR transfer of the address" "0: SDR transfer,1: DDR transfer"
newline
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4. "OPDRE,Option Data DDR Enable Specifies the SDR or DDR transfer of the option data" "0: SDR transfer,1: DDR transfer"
newline
rbitfld.long 0x00 1.--3. "Reserved_1,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "SPIDRE,Transfer Data DDR Enable Specifies the SDR or DDR transfer of the data for transfer" "0: SDR transfer,1: DDR transfer"
group.long 0x7C++0x03
line.long 0x00 "PHYCNT,PHYCNT is a 32-bit register that sets the PHY operating mode"
bitfld.long 0x00 31. "CAL,PHY Calibration Executes calibration of the PHY" "0: Calibration is not executed,1: Calibration is executed"
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as initial value"
newline
bitfld.long 0x00 22.--23. "OCTA,Octal-SPI flash alignment Specify data alignment with Octal-SPI flash memory" "0: HyperFlash or serial flash memory x 1ch or 2ch,1: Support alternate alignment,2: Support sequential alignment,3: Support alternate alignment"
bitfld.long 0x00 21. "EXDS,External Data Strobe Uses external Data Strobe signal with serial flash memory when connecting to serial flash with Data Strobe" "0: Not use external Data Strobe signal,1: Use external Data Strobe signal"
newline
bitfld.long 0x00 20. "OCT,Octal-SPI flash protocol mode" "0: Specify 0 in the other than above mode,1: Use Octal-SPI DDR/SDR protocol mode"
bitfld.long 0x00 19. "DDRCAL,This bit is specified to 1 in SW calibration for DDR transfer of serial flash operation" "0,1"
newline
bitfld.long 0x00 18. "HS,High Speed response mode Specify high speed response mode" "0: The read data is output to bus master after the,1: The read data is output to bus master in"
bitfld.long 0x00 15.--17. "STRTIM_2_0,Strobe Timing Adjustment bit These bits specify the internal strobe delay which is used for the flash device without external strobe like serial flash memory" "0: The delay is biggest,1: The delay is 2nd biggest,?,?,?,?,6: The delay is 2nd smallest,7: The delay is smallest"
newline
hexmask.long.word 0x00 5.--14. 1. "Reserved_5,Reserved These bits are always read as initial value"
bitfld.long 0x00 4. "WBUF2,Write Buffer Enable2 The write buffer is used when the flash memory is written to" "0: The write buffer is not used,1: The write buffer is used to write data to the"
newline
rbitfld.long 0x00 3. "Reserved_3,Reserved This bit is always read as initial value" "0,1"
bitfld.long 0x00 2. "WBUF,Write Buffer Enable The write buffer is used when the flash memory is written to" "0: The write buffer is not used,1: The write buffer is used to write data to the"
newline
bitfld.long 0x00 0.--1. "PHYMEM,Device Selection Selects a device to connect" "0: Serial flash in SDR mode,1: Serial flash in DDR mode,?,3: HyperFlash Other than above"
group.long 0x80++0x03
line.long 0x00 "PHYOFFSET1,PHYOFFSET1 is a 32-bit register that sets the timing adjustment in DDR operation"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved These bits are always read as initial value" "0,1,2,3"
bitfld.long 0x00 28.--29. "DDRTMG,DDR Operation Timing Register Specify the timing adjustment in DDR read operation" "?,?,2: When SMDRENR.DRDRE or DRDRENR.DRDRE = 1 in read,3: When SMDRENR.DRDRE or DRDRENR.DRDRE = 0 in read"
newline
hexmask.long 0x00 0.--27. 1. "Reserved_0,Reserved These bits are always read as initial value"
group.long 0x84++0x03
line.long 0x00 "PHYOFFSET2,PHYOFFSET2 is a 32-bit register that sets the timing adjustment in DDR operation"
hexmask.long.tbyte 0x00 11.--31. 1. "Reserved_11,Reserved These bits are always read as 0"
bitfld.long 0x00 8.--10. "OCTTMG,Octal-SPI flash Operation Timing Specifies the timing adjustment when write to 8-bti Octal-SPI flash" "0: Write Buffer Operation of serial flash with,?,?,3: Octal-SPI flash operation Other than above,4: serial flash or Hyperflash,?..."
newline
hexmask.long.byte 0x00 0.--7. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x88++0x03
line.long 0x00 "PHYINT,PHYINT is a 32-bit register that sets the interrupt signal and the pins for HyperFlash"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved These bits are always read as initial value"
bitfld.long 0x00 24. "INTIE,RPC_INT# Pin Input Enable Input Enables or disables the RPC_INT# pin" "0: The RPC_INT# pin input is disabled,1: The RPC_INT# pin input is enabled"
newline
rbitfld.long 0x00 19.--23. "Reserved_19,Reserved These bits are always read as initial value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 18. "RSTEN,RPC_RESET# Pin Enable Enables or disables the RPC_RESET# pin" "0: The RPC_RESET# pin is disabled,1: The RPC_RESET# pin is enabled and the value on"
newline
bitfld.long 0x00 17. "WPEN,[H3 M3-W V3M V3H and M3-N] RPC_WP# Pin Enable Enables or disables the RPC_WP# pin" "0: The RPC_WP# pin is disabled,1: The RPC_WP# pin is enabled and the settings of"
bitfld.long 0x00 16. "INTEN,RPC_INT# Pin Enable Enables or disables the RPC_INT# pin" "0: The RPC_INT# pin is disabled,1: The RPC_INT# pin is enabled and the interrupt"
newline
hexmask.long.word 0x00 3.--15. 1. "Reserved_3,Reserved These bits are always read as initial value"
bitfld.long 0x00 2. "RSTVAL,RPC_RESET# Pin Output Value Specifies the value output from the RPC_RESET# pin" "0: RPC_RESET# = H,1: RPC_RESET# = L"
newline
bitfld.long 0x00 1. "WPVAL,[H3 M3-W V3M V3H and M3-N] RPC_WP# Pin Output Value Specifies the value output from the RPC_WP# pin" "0: RPC_WP# = H,1: RPC_WP# = L"
rbitfld.long 0x00 0. "INT,Interrupt Status When RPC _INT# is set to L this bit becomes H to notice interrupt occurs in the connected device" "0,1"
group.long 0xAC++0x03
line.long 0x00 "ADD_DIV1,ADD_DIV1 is a 32-bit register that specifies the address which divides the RPC area for security domain"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--19. 1. "ADD_DIV1_19_0,Address Division bit 1 Specifies address boundary of secure domain in RPC area"
group.long 0xB0++0x03
line.long 0x00 "ADD_DIV2,ADD_DIV2 is a 32-bit register that specifies the address which divides the RPC area for security domain"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--19. 1. "ADD_DIV2_19_0,Address Division bit 2 Specifies address boundary of secure domain in RPC area"
group.long 0xB4++0x03
line.long 0x00 "ADD_DIV3,ADD_DIV3 is a 32-bit register that specifies the address which divides the RPC area for security domain"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--19. 1. "ADD_DIV3_19_0,Address Division bit 3 Specifies address boundary of secure domain in RPC area"
group.long 0xB8++0x03
line.long 0x00 "SEC_CONF,SEC_CNF is a 32-bit register that specifies the attribution of each domain which is divided by ADD_DIVn (n=1 2 3)"
hexmask.long.tbyte 0x00 9.--31. 1. "Reserved_9,Reserved These bits are always read as 0"
bitfld.long 0x00 8. "SECEN,Secure function enable bit Enables secure function command restriction" "0: secure,1: non-secure The"
newline
bitfld.long 0x00 6.--7. "AREA3_1_0,Area Attribution 3 Specifies the attribution of Area3 which is specified by ADD_DIVn register in RPC area" "0: secure,1: non-secure The,?..."
bitfld.long 0x00 4.--5. "AREA2_1_0,Area Attribution 2 Specifies the attribution of Area2 which is specified by ADD_DIVn register in RPC area" "0: secure,1: non-secure The,?..."
newline
bitfld.long 0x00 2.--3. "AREA1_1_0,Area Attribution 1 Specifies the attribution of Area1 which is specified by ADD_DIVn register in RPC area" "0: secure,1: non-secure The,?..."
bitfld.long 0x00 0.--1. "AREA0_1_0,Area Attribution 0 Specifies the attribution of Area0 which is specified by ADD_DIVn register in RPC area" "0: secure,1: non-secure The,?..."
group.long 0xBC++0x03
line.long 0x00 "ARIGHT,AWRITE is a 32-bit register that specifies the semaphore function which limits the access to the register of this controller"
hexmask.long 0x00 4.--31. 1. "Reserved_4,Reserved These bits are always read as 0"
rbitfld.long 0x00 3. "RIGHT_NONS,Right Bit for Non-Secure Specifies the right bit for Non-Secure CPU" "0: Non-Secure CPU doesnt have a right to access,1: Non-Secure CPU has a right to access"
newline
rbitfld.long 0x00 2. "Reserved_2,Reserved This bit is always read as 0" "0,1"
rbitfld.long 0x00 1. "RIGHT_SEC,Right Bit for Secure Specifies the right bit for Secure CPU" "0: Secure CPU doesnt have a right to access,1: Secure CPU has a right to access"
newline
bitfld.long 0x00 0. "RIGHT_EN,Access Right Enable Specifies the access right function to enable" "0: Not use access right function,1: Use access right function"
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0xC0)++0x03
line.long 0x00 "SEC_CMD$1,SEC_CMD0 is a 32-bit register that specifies the command which is prohibited for Secure CPU"
bitfld.long 0x00 31. "LIMEN,Command Limitation Enable for Secure CPU Specifies the limited command for Secure CPU" "0: The command specified in LIMCMD[15:0] is not,1: The command specified in LIMCMD[15:0] is.."
hexmask.long.word 0x00 16.--30. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--15. 1. "LIMCMD,Limited Command for Secure CPU Specifies the command which is limited for Secure CPU"
repeat.end
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x100)++0x03
line.long 0x00 "NON_SEC_CMD$1,NON_SEC_CMD0 is a 32-bit register that specifies the command which is prohibited for Non-Secure CPU"
bitfld.long 0x00 31. "LIMEN,Command Limitation Enable for Non-Secure CPU Specifies the limited command for Non-Secure CPU" "0: The command specified in LIMCMD[15:0] is not,1: The command specified in LIMCMD[15:0] is.."
hexmask.long.word 0x00 16.--30. 1. "Reserved_16,Reserved These bits are always read as 0"
newline
hexmask.long.word 0x00 0.--15. 1. "LIMCMD,Limited Command for Non-Secure CPU Specifies the command which is limited for Non-Secure CPU"
repeat.end
repeat 2. (strings "1" "2" )(list 0x00 0x04 )
group.long ($2+0x1E0)++0x03
line.long 0x00 "ERASELIST$1,ERASELIST1 is a 32-bit register that specifies Erase Command to limit"
bitfld.long 0x00 31. "ECMDEN1,Erase Command 1 Enable Enables to limit the erase command which is specified In ECMD1" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "ECMD1,Erase Command 1 Specifies the Erase command to limit"
bitfld.long 0x00 15. "ECMDEN2,Erase Command 2 Enable Enables to limit the erase command which is specified In ECMD2" "0,1"
newline
hexmask.long.byte 0x00 8.--14. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "ECMD2,Erase Command 2 Specifies the Erase command to limit"
repeat.end
repeat 2. (strings "1" "2" )(list 0x00 0x04 )
group.long ($2+0x1E8)++0x03
line.long 0x00 "WRITELIST$1,WRITELIST1 is a 32-bit register that specifies Write Command to limit"
bitfld.long 0x00 31. "WCMDEN1,Write Command 1 Enable Enables to limit the Write command which is specified In WCMD1" "0: Disable to limit the Write command which is,1: Enable to limit the Write command which is"
hexmask.long.byte 0x00 24.--30. 1. "Reserved_24,Reserved These bits are always read as 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "WCMD1,Write Command 1 Specifies the Write command to limit"
bitfld.long 0x00 15. "WCMDEN2,Write Command 2 Enable Enables to limit the Write command which is specified In WCMD2" "0: Disable to limit the Write command which is,1: Enable to limit the Write command which is"
newline
hexmask.long.byte 0x00 8.--14. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "WCMD2,Write Command 2 Specifies the Write command to limit"
repeat.end
tree.end
tree "LIFEC"
base ad:0xE6110000
group.long 0x238++0x03
line.long 0x00 "DBSCRM,DBSCRM controls SDRAM write/read data scramble/de-scramble function"
hexmask.long 0x00 0.--31. 1. "DBSCRM_31_0,All"
tree.end
tree "CRC"
tree "CRC_INST_0"
base ad:0xE7080000
group.long 0x00++0x03
line.long 0x00 "WCRC0_CAIPn_EN,WCRC[m]_CAIPn_EN is a register that sets enable the data transfer to/from each port for CAIP_Lite_n interface in FIFO"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
bitfld.long 0x00 16. "out_en,Output data from Data port in FIFO enable" "0: Disable output from Data port,1: Enable output from Data port"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
bitfld.long 0x00 8. "res_en,Output result data from Result port in FIFO enable" "0: Disable output from Result port,1: Enable output from Result port"
newline
rbitfld.long 0x00 2.--7. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 1. "trans_en,Transferring data from Data port in FIFO to CAIP_Lite_n enable" "0: Disable transferring data to CAIP_Lite_n,1: Enable transferring data to CAIP_Lite_n When"
newline
bitfld.long 0x00 0. "in_en,Input data to Data/Command port in FIFO enable" "0: Disable input to Data/Command port,1: Enable input to Data/Command port"
group.long 0x20++0x03
line.long 0x00 "WCRC0_CAIPn_STOP,WCRC[m]_CAIPn_STOP is a register that stop transfer to CAIP_Lite_n interface"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
bitfld.long 0x00 0. "stop," "0,1"
group.long 0x30++0x03
line.long 0x00 "WCRC0_CAIPn_CMDEN,WCRC[m]_CAIPn_CMDEN is a register that sets enable command function for CAIP_Lite_n module"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
bitfld.long 0x00 0. "cmd_en,Command function enable" "0: Disable command function,1: Enable command function"
group.long 0x80++0x03
line.long 0x00 "WCRC0_CAIPn_WAIT,WCRC[m]_CAIPn_WAIT is a register that wait subsequent command for CAIP_Lite_n interface"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
bitfld.long 0x00 0. "wait," "0,1"
group.long 0x200++0x03
line.long 0x00 "WCRC0_CAIPn_STS,WCRC[m]_CAIPn_STS is a register that indicates the state of operation related to CAIP_Lite_n module"
eventfld.long 0x00 31. "stop_done,Indicates the state of stop operation by WCRC[m]_CAIPn_STOP register" "0: Stop operation in progress or not done,1: Stop operation is done"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
eventfld.long 0x00 24. "cmd_done,Indicates the state of command function" "0: Accessing to register by command in progress or,1: Accessing to register by command is done"
rbitfld.long 0x00 21.--23. "Reserved_21,Reserved" "0,1,2,3,4,5,6,7"
newline
eventfld.long 0x00 20. "res_done,Indicates the state of result data transfer" "0: Transfer in progress or not transferring,1: Transfer is done"
hexmask.long.tbyte 0x00 1.--19. 1. "Reserved_1,Reserved"
newline
eventfld.long 0x00 0. "trans_done,Indicates the state of input data transfer" "0: Transfer in progress or not transferring,1: Transfer is done"
group.long 0x240++0x03
line.long 0x00 "WCRC0_CAIPn_INTEN,WCRC[m]_CAIPn_INTEN is a register that sets enable for the interrupt of operation related to CAIP_Lite_n module"
bitfld.long 0x00 31. "stop_done_ie,Interrupt for the complete of stop operation by WCRC[m]_CAIPn_STOP register" "0: Disable interrupt,1: Enable interrupt"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 24. "cmd_done_ie,Interrupt for the complete of command function enable" "0: Disable interrupt,1: Enable interrupt"
rbitfld.long 0x00 21.--23. "Reserved_21,Reserved" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 20. "res_done_ie,Interrupt for the complete of result data transfer enable" "0: Disable interrupt,1: Enable interrupt"
hexmask.long.tbyte 0x00 1.--19. 1. "Reserved_1,Reserved"
newline
bitfld.long 0x00 0. "trans_done_ie,Interrupt for the complete of input data transfer enable" "0: Disable interrupt,1: Enable interrupt"
group.long 0x2A0++0x03
line.long 0x00 "WCRC0_CAIPn_BUF_STS_RDEN,WCRC[m]_CAIPn_BUF_STS_RDEN is a register that sets enable for the interrupt of operation related to AES-ACC_n module"
hexmask.long.word 0x00 16.--31. 1. "Code_value,Code value (HA5A5) Set Code value to these bits when writing to this register to enable writing to this register"
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved"
newline
bitfld.long 0x00 0. "BUF_STS_RDEN,WCRC[m]_CAIPn_BUF_STS enable" "0: Disable WCRC[m]_CAIPn_BUF_STS,1: Enable WCRC[m]_CAIPn_BUF_STS"
group.long 0x400++0x03
line.long 0x00 "WCRC0_CAIPp_EN,WCRC[m]_CAIPp_EN is a register that sets enable the data transfer to/from each ports for CAIP_Lite_p interface in FIFO"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
bitfld.long 0x00 16. "out_en,Output data from Data port in FIFO enable" "0: Disable output from Data port,1: Enable output from Data port"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
bitfld.long 0x00 8. "res_en,Output result data from Result port in FIFO enable" "0: Disable output from Result port,1: Enable output from Result port"
newline
rbitfld.long 0x00 2.--7. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 1. "trans_en,Transferring data from Data port in FIFO to CAIP_Lite_p enable" "0: Disable transferring data to CAIP_Lite_p,1: Enable transferring data to CAIP_Lite_p When"
newline
bitfld.long 0x00 0. "in_en,Input data to Data/Command port in FIFO enable" "0: Disable input to Data/Command port,1: Enable input to Data/Command port"
group.long 0x420++0x03
line.long 0x00 "WCRC0_CAIPp_STOP,WCRC[m]_CAIPp_STOP is a register that stop transfer to CAIP_Lite_p interface"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
bitfld.long 0x00 0. "stop," "0,1"
group.long 0x430++0x03
line.long 0x00 "WCRC0_CAIPp_CMDEN,WCRC[m]_CAIPp_CMDEN is a register that sets enable command function for CAIP_Lite_p module"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
bitfld.long 0x00 0. "cmd_en,Command function enable" "0: Disable command function,1: Enable command function"
group.long 0x480++0x03
line.long 0x00 "WCRC0_CAIPp_WAIT,WCRC[m]_CAIPp_WAIT is a register that wait subsequent command for CAIP_Lite_p interface"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
bitfld.long 0x00 0. "wait," "0,1"
group.long 0x600++0x03
line.long 0x00 "WCRC0_CAIPp_STS,WCRC[m]_CAIPp_STS is a register that indicates the state of operation related to CAIP_Lite_p module"
eventfld.long 0x00 31. "stop_done,Indicates the state of stop operation by WCRC[m]_CAIPp_STOP register" "0: Stop operation in progress or not done,1: Stop operation is done"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
eventfld.long 0x00 24. "cmd_done,Indicates the state of command function" "0: Accessing to register by command in progress or,1: Accessing to register by command is done"
rbitfld.long 0x00 21.--23. "Reserved_21,Reserved" "0,1,2,3,4,5,6,7"
newline
eventfld.long 0x00 20. "res_done,Indicates the state of result data transfer" "0: Transfer in progress or not transferring,1: Transfer is done"
hexmask.long.tbyte 0x00 1.--19. 1. "Reserved_1,Reserved"
newline
eventfld.long 0x00 0. "trans_done,Indicates the state of input data transfer" "0: Transfer in progress or not transferring,1: Transfer is done"
group.long 0x640++0x03
line.long 0x00 "WCRC0_CAIPp_INTEN,WCRC[m]_CAIPp_INTEN is a register that sets enable for the interrupt of operation related to CAIP_Lite_p module"
bitfld.long 0x00 31. "stop_done_ie,Interrupt for the complete of stop operation by WCRC[m]_CAIPp_STOP register" "0: Disable interrupt,1: Enable interrupt"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 24. "cmd_done_ie,Interrupt for the complete of command function enable" "0: Disable interrupt,1: Enable interrupt"
rbitfld.long 0x00 21.--23. "Reserved_21,Reserved" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 20. "res_done_ie,Interrupt for the complete of result data transfer enable" "0: Disable interrupt,1: Enable interrupt"
hexmask.long.tbyte 0x00 1.--19. 1. "Reserved_1,Reserved"
newline
bitfld.long 0x00 0. "trans_done_ie,Interrupt for the complete of input data transfer enable" "0: Disable interrupt,1: Enable interrupt"
group.long 0x6A0++0x03
line.long 0x00 "WCRC0_CAIPp_BUF_STS_RDEN,WCRC[m]_CAIPp_BUF_STS_RDEN is a register that sets enable for the interrupt of operation related to AES-ACC_p module"
hexmask.long.word 0x00 16.--31. 1. "Code_value,Code value (HA5A5) Set Code value to these bits when writing to this register to enable writing to this register"
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved"
newline
bitfld.long 0x00 0. "BUF_STS_RDEN,WCRC[m]_CAIPp_BUF_STS enable" "0: Disable WCRC[m]_CAIPp_BUF_STS,1: Enable WCRC[m]_CAIPp_BUF_STS"
group.long 0x800++0x03
line.long 0x00 "WCRC0_CRC0_EN,WCRC[m]_CRC[m]_EN is a register that sets enable the data transfer to/from each port for CRC[m] module in FIFO"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
bitfld.long 0x00 16. "out_en,Output data from Data port in FIFO enable" "0: Disable output from Data port,1: Enable output from Data port"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
bitfld.long 0x00 8. "res_en,Output result data from Result port in FIFO enable" "0: Disable output from Result port,1: Enable output from Result port"
newline
rbitfld.long 0x00 2.--7. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 1. "trans_en,Transferring data from Data port in FIFO to CRC[m] enable" "0: Disable transferring data to CRC[m],1: Enable transferring data to CRC[m] When.."
newline
bitfld.long 0x00 0. "in_en,Input data to Data/Command/Expected data port in FIFO enable" "0: Disable input to Data/Command/Expected data..,1: Enable input to Data/Command/Expected data port"
group.long 0x820++0x03
line.long 0x00 "WCRC0_CRC0_STOP,WCRC[m]_CRC[m]_STOP is a register that stop transfer to CRC[m] module"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
bitfld.long 0x00 0. "stop," "0,1"
group.long 0x830++0x03
line.long 0x00 "WCRC0_CRC0_CMDEN,WCRC[m]_CRC[m]_CMDEN is a register that sets enable command function for CRC[m] module"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
bitfld.long 0x00 0. "cmd_en,Command function enable" "0: Disable command function,1: Enable command function"
group.long 0x840++0x03
line.long 0x00 "WCRC0_CRC0_COMP,WCRC[m]_CRC[m]_COMP is a register that sets enable comparing CRC result from CRC[m] module with expected data in FIFO"
hexmask.long.word 0x00 18.--31. 1. "Reserved_18,Reserved"
bitfld.long 0x00 16.--17. "cmp_freq,Set the frequency of comparing" "0,1,2,3"
newline
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved"
bitfld.long 0x00 1. "exp_reqsel,Select DMA Transfer request source for transferring expected data" "0: dmareq_wcrcm_crcm_in,1: dmareq_wcrcm_crcm_res m"
newline
bitfld.long 0x00 0. "cmp_en,Comparing CRC result with expected data enable" "0: Disable comparing function,1: Enable comparing function"
group.long 0x850++0x03
line.long 0x00 "WCRC0_CRC0_COMP_RES,WCRC[m]_CRC[m]_COMP_RES is a register that indicates the result of comparing CRC for CRC[m] module"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved"
abitfld.long 0x00 0.--15. "cmp_res,The result of comparing CRC These bits indicate mismatched point of comparing data in 4-byte units" "0x0000=0: No error,0x0001=1: Mismatch Figure 135.4"
group.long 0x870++0x03
line.long 0x00 "WCRC0_CRC0_CONV,WCRC[m]_CRC[m]_CONV is a register that sets CRC conversion size to once for CRC[m] module"
hexmask.long.word 0x00 21.--31. 1. "Reserved_21,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--20. 1. "conv,CRC conversion size specification Specifies the CRC conversion size in 1-byte units"
group.long 0x880++0x03
line.long 0x00 "WCRC0_CRC0_WAIT,WCRC[m]_CRC[m]_WAIT is a register that wait subsequent command for CRC[m] module"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
bitfld.long 0x00 0. "wait," "0,1"
group.long 0x910++0x03
line.long 0x00 "WCRC0_CRC0_INIT_CRC,WCRC[m]_CRC[m]_INIT_CRC is a register that sets CRC code value to DCRAmCOUT register at auto clear"
hexmask.long 0x00 0.--31. 1. "init_code,CRC code value to DCRAmCOUT register at auto clear"
group.long 0xA00++0x03
line.long 0x00 "WCRC0_CRC0_STS,WCRC[m]_CRC[m]_STS is a register that indicates the state of operation related to CRC[m] module"
eventfld.long 0x00 31. "stop_done,Indicates the state of stop operation by WCRC[m]_CRC[m]_STOP register" "0: Stop operation in progress or not done,1: Stop operation is done"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
eventfld.long 0x00 24. "cmd_done,Indicates the state of command function" "0: Accessing to register by command in progress or,1: Accessing to register by command is done"
rbitfld.long 0x00 21.--23. "Reserved_21,Reserved" "0,1,2,3,4,5,6,7"
newline
eventfld.long 0x00 20. "res_done,Indicates the state of result data transfer" "0: Transfer in progress or not transferring,1: Transfer is done"
rbitfld.long 0x00 14.--19. "Reserved_14,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
eventfld.long 0x00 13. "comp_err,Indicates the error of comparing CRC" "0: No comparing error or not comparing,1: Mismatch has occurred"
eventfld.long 0x00 12. "comp_done,Indicates the state of comparing CRC" "0: Comparison in progress or not comparing,1: Comparing is done"
newline
hexmask.long.word 0x00 1.--11. 1. "Reserved_1,Reserved"
eventfld.long 0x00 0. "trans_done,Indicates the state of input data transfer" "0: Transfer in progress or not transferring,1: Transfer is done"
group.long 0xA40++0x03
line.long 0x00 "WCRC0_CRC0_INTEN,WCRC[m]_CRC[m]_INTEN is a register that sets enable for the interrupt of operation related to CRC[m] module"
bitfld.long 0x00 31. "stop_done_ie,Interrupt for the complete of stop operation by WCRC[m]_CRC[m]_STOP register" "0: Disable interrupt,1: Enable interrupt"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 24. "cmd_done_ie,Interrupt for the complete of command function enable" "0: Disable interrupt,1: Enable interrupt"
rbitfld.long 0x00 21.--23. "Reserved_21,Reserved" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 20. "res_done_ie,Interrupt for the complete of result data transfer enable" "0: Disable interrupt,1: Enable interrupt"
rbitfld.long 0x00 14.--19. "Reserved_14,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 13. "comp_err_ie,Interrupt for the error of comparing CRC enable" "0: Disable interrupt,1: Enable interrupt"
bitfld.long 0x00 12. "comp_done_ie,Interrupt for the complete of comparing CRC enable" "0: Disable interrupt,1: Enable interrupt"
newline
hexmask.long.word 0x00 1.--11. 1. "Reserved_1,Reserved"
bitfld.long 0x00 0. "trans_done_ie,Interrupt for the complete of input data transfer enable" "0: Disable interrupt,1: Enable interrupt"
group.long 0xA80++0x03
line.long 0x00 "WCRC0_CRC0_ECMEN,WCRC[m]_CRC[m]_ECMEN is a register that sets enable for error notification to ECM module on operation related to CRC[m] module"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved"
bitfld.long 0x00 13. "comp_err_oe,Error notification for the error of comparing CRC enable" "0: Disable notification,1: Enable notification"
newline
hexmask.long.word 0x00 0.--12. 1. "Reserved_0,Reserved"
group.long 0xAA0++0x03
line.long 0x00 "WCRC0_CRC0_BUF_STS_RDEN,WCRC[m]_CRC[m]_BUF_STS_RDEN is a register that sets enable for the interrupt of operation related to CRC[m] module"
hexmask.long.word 0x00 16.--31. 1. "Code_value,Code value (HA5A5) Set Code value to these bits when writing to this register to enable writing to this register"
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved"
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bitfld.long 0x00 0. "BUF_STS_RDEN,WCRC[m]_CRC[m]_BUF_STS enable" "0: Disable WCRC[m]_CRC[m]_BUF_STS,1: Enable WCRC[m]_CRC[m]_BUF_STS"
group.long 0xC00++0x03
line.long 0x00 "WCRC0_KCRC0_EN,WCRC[m]_KCRC[m]_EN is a register that sets enable the data transfer to/from each port for KCRC[m] module in FIFO"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
bitfld.long 0x00 16. "out_en,Output data from Data port in FIFO enable" "0: Disable output from Data port,1: Enable output from Data port"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
bitfld.long 0x00 8. "res_en,Output result data from Result port in FIFO enable" "0: Disable output from Result port,1: Enable output from Result port"
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rbitfld.long 0x00 2.--7. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 1. "trans_en,Transferring data from Data port in FIFO to KCRC[m] enable" "0: Disable transferring data to KCRC[m],1: Enable transferring data to KCRC[m] When"
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bitfld.long 0x00 0. "in_en,Input data to Data/Command/Expected data port in FIFO enable" "0: Disable input to Data/Command/Expected data..,1: Enable input to Data/Command/Expected data port"
group.long 0xC20++0x03
line.long 0x00 "WCRC0_KCRC0_STOP,WCRC[m]_KCRC[m]_STOP is a register that stop transfer to KCRC[m] module"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
bitfld.long 0x00 0. "stop," "0,1"
group.long 0xC30++0x03
line.long 0x00 "WCRC0_KCRC0_CMDEN,WCRC[m]_KCRC[m]_CMDEN is a register that sets enable command function for KCRC[m] module"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
bitfld.long 0x00 0. "cmd_en,Command function enable" "0: Disable command function,1: Enable command function"
group.long 0xC40++0x03
line.long 0x00 "WCRC0_KCRC0_COMP,WCRC[m]_KCRC[m]_COMP is a register that sets enable comparing CRC result from KCRC[m] module with expected data in FIFO"
hexmask.long.word 0x00 18.--31. 1. "Reserved_18,Reserved"
bitfld.long 0x00 16.--17. "cmp_freq,Set the frequency of comparing" "0,1,2,3"
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hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved"
bitfld.long 0x00 1. "exp_reqsel,Select DMA Transfer request source for transferring expected data" "0: dmareq_wcrcm_kcrcn_in,1: dmareq_wcrcm_kcrcn_res m"
newline
bitfld.long 0x00 0. "cmp_en,Comparing CRC result with expected data enable" "0: Disable comparing function,1: Enable comparing function"
group.long 0xC50++0x03
line.long 0x00 "WCRC0_KCRC0_COMP_RES,WCRC[m]_KCRC[m]_COMP_RES is a register that indicates the result of comparing CRC for KCRC[m] module"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved"
abitfld.long 0x00 0.--15. "cmp_res,The result of comparing CRC These bits indicate mismatched point of comparing data in 4-byte units" "0x0000=0: No error,0x0001=1: Mismatch Figure 135.4"
group.long 0xC70++0x03
line.long 0x00 "WCRC0_KCRC0_CONV,WCRC[m]_KCRC[m]_CONV is a register that sets CRC conversion size to once for KCRC[m] module"
hexmask.long.word 0x00 21.--31. 1. "Reserved_21,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--20. 1. "conv,CRC conversion size specification Specifies the CRC conversion size in 1-byte units"
group.long 0xC80++0x03
line.long 0x00 "WCRC0_KCRC0_WAIT,WCRC[m]_KCRC[m]_WAIT is a register that wait subsequent command for KCRC[m] module"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
bitfld.long 0x00 0. "wait," "0,1"
group.long 0xD10++0x03
line.long 0x00 "WCRC0_KCRC0_INIT_CRC,WCRC[m]_KCRC[m]_INIT_CRC is a register that sets CRC code value to KCRC[m]COUT register at auto clear"
hexmask.long 0x00 0.--31. 1. "init_code,CRC code value to KCRC[m]DOUT register at auto clear"
group.long 0xE00++0x03
line.long 0x00 "WCRC0_KCRC0_STS,WCRC[m]_KCRC[m]_STS is a register that indicates the state of operation related to KCRC[m] module"
eventfld.long 0x00 31. "stop_done,Indicates the state of stop operation by WCRC[m]_KCRC[m]_STOP register" "0: Stop operation in progress or not done,1: Stop operation is done"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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eventfld.long 0x00 24. "cmd_done,Indicates the state of command function" "0: Accessing to register by command in progress or,1: Accessing to register by command is done"
rbitfld.long 0x00 21.--23. "Reserved_21,Reserved" "0,1,2,3,4,5,6,7"
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eventfld.long 0x00 20. "res_done,Indicates the state of result data transfer" "0: Transfer in progress or not transferring,1: Transfer is done"
rbitfld.long 0x00 14.--19. "Reserved_14,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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eventfld.long 0x00 13. "comp_err,Indicates the error of comparing CRC" "0: No comparing error or not comparing,1: Mismatch has occurred"
eventfld.long 0x00 12. "comp_done,Indicates the state of comparing CRC" "0: Comparison in progress or not comparing,1: Comparing is done"
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hexmask.long.word 0x00 1.--11. 1. "Reserved_1,Reserved"
eventfld.long 0x00 0. "trans_done,Indicates the state of input data transfer" "0: Transfer in progress or not transferring,1: Transfer is done"
group.long 0xE40++0x03
line.long 0x00 "WCRC0_KCRC0_INTEN,WCRC[m]_KCRC[m]_INTEN is a register that sets enable for the interrupt of operation related to KCRC[m] module"
bitfld.long 0x00 31. "stop_done_ie,Interrupt for the complete of stop operation by WCRC[m]_KCRC[m]_STOP register" "0: Disable interrupt,1: Enable interrupt"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 24. "cmd_done_ie,Interrupt for the complete of command function enable" "0: Disable interrupt,1: Enable interrupt"
rbitfld.long 0x00 21.--23. "Reserved_21,Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 20. "res_done_ie,Interrupt for the complete of result data transfer enable" "0: Disable interrupt,1: Enable interrupt"
rbitfld.long 0x00 14.--19. "Reserved_14,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 13. "comp_err_ie,Interrupt for the error of comparing CRC enable" "0: Disable interrupt,1: Enable interrupt"
bitfld.long 0x00 12. "comp_done_ie,Interrupt for the complete of comparing CRC enable" "0: Disable interrupt,1: Enable interrupt"
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hexmask.long.word 0x00 1.--11. 1. "Reserved_1,Reserved"
bitfld.long 0x00 0. "trans_done_ie,Interrupt for the complete of input data transfer enable" "0: Disable interrupt,1: Enable interrupt"
group.long 0xE80++0x03
line.long 0x00 "WCRC0_KCRC0_ECMEN,WCRC[m]_KCRC[m]_ECMEN is a register that sets enable for error notification to ECM module on operation related to KCRC[m] module"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved"
bitfld.long 0x00 13. "comp_err_oe,Error notification for the error of comparing CRC enable" "0: Disable notification,1: Enable notification"
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hexmask.long.word 0x00 0.--12. 1. "Reserved_0,Reserved"
group.long 0xEA0++0x03
line.long 0x00 "WCRC0_KCRC0_BUF_STS_RDEN,WCRC[m]_KCRC[m]_BUF_STS_RDEN is a register that sets enable for the interrupt of operation related to KCRC[m] module"
hexmask.long.word 0x00 16.--31. 1. "Code_value,Code value (HA5A5) Set Code value to these bits when writing to this register to enable writing to this register"
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved"
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bitfld.long 0x00 0. "BUF_STS_RDEN,WCRC[m]_KCRC[m]_BUF_STS enable" "0: Disable WCRC[m]_KCRC[m]_BUF_STS,1: Enable WCRC[m]_KCRC[m]_BUF_STS"
group.long 0xF00++0x03
line.long 0x00 "WCRC0_COMMON_STS,WCRC[m]_COMMON_STS is a register that indicates the state of operation related to WCRC[m] module"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved"
eventfld.long 0x00 16. "edc_err,Indicates the error of EDC" "0: No EDC error,1: EDC error has occurred"
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hexmask.long.word 0x00 0.--15. 1. "Reserved_0,Reserved"
group.long 0xF40++0x03
line.long 0x00 "WCRC0_COMMON_INTEN,WCRC[m]_COMMON_INTEN is a register that sets enable for the interrupt of operation related to WCRC[m] module"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved"
bitfld.long 0x00 16. "edc_err_ie,Interrupt for the error of EDC enable" "0: Disable interrupt,1: Enable interrupt"
newline
hexmask.long.word 0x00 0.--15. 1. "Reserved_0,Reserved"
group.long 0xF80++0x03
line.long 0x00 "WCRC0_COMMON_ECMEN,WCRC[m]_COMMON_ECMEN is a register that sets enable for error notification to ECM module on operation related to WCRC[m] module"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved"
bitfld.long 0x00 16. "edc_err_oe,Error notification for EDC error enable" "0: Disable notification,1: Enable notification"
newline
hexmask.long.word 0x00 0.--15. 1. "Reserved_0,Reserved"
group.long 0xFC0++0x03
line.long 0x00 "WCRC0_ERRINJ,WCRC[m]_ERRINJ is a register that sets enable error injection for bus data signal or EDC code signal"
hexmask.long.word 0x00 16.--31. 1. "code,Code value Set HA5A5 due to enable error injection"
hexmask.long.word 0x00 3.--15. 1. "Reserved_3,Reserved"
newline
bitfld.long 0x00 0.--2. "err_inj_2_0,Error injection enable Bit[0]" "0: Disables error for EDC code signal,1: Enables error for EDC code signal,?..."
tree.end
tree "CRC_INST_1"
base ad:0xE7090000
group.long 0x00++0x03
line.long 0x00 "WCRC1_CAIPn_EN,WCRC[m]_CAIPn_EN is a register that sets enable the data transfer to/from each port for CAIP_Lite_n interface in FIFO"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
bitfld.long 0x00 16. "out_en,Output data from Data port in FIFO enable" "0: Disable output from Data port,1: Enable output from Data port"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
bitfld.long 0x00 8. "res_en,Output result data from Result port in FIFO enable" "0: Disable output from Result port,1: Enable output from Result port"
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rbitfld.long 0x00 2.--7. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 1. "trans_en,Transferring data from Data port in FIFO to CAIP_Lite_n enable" "0: Disable transferring data to CAIP_Lite_n,1: Enable transferring data to CAIP_Lite_n When"
newline
bitfld.long 0x00 0. "in_en,Input data to Data/Command port in FIFO enable" "0: Disable input to Data/Command port,1: Enable input to Data/Command port"
group.long 0x20++0x03
line.long 0x00 "WCRC1_CAIPn_STOP,WCRC[m]_CAIPn_STOP is a register that stop transfer to CAIP_Lite_n interface"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
bitfld.long 0x00 0. "stop," "0,1"
group.long 0x30++0x03
line.long 0x00 "WCRC1_CAIPn_CMDEN,WCRC[m]_CAIPn_CMDEN is a register that sets enable command function for CAIP_Lite_n module"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
bitfld.long 0x00 0. "cmd_en,Command function enable" "0: Disable command function,1: Enable command function"
group.long 0x80++0x03
line.long 0x00 "WCRC1_CAIPn_WAIT,WCRC[m]_CAIPn_WAIT is a register that wait subsequent command for CAIP_Lite_n interface"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
bitfld.long 0x00 0. "wait," "0,1"
group.long 0x200++0x03
line.long 0x00 "WCRC1_CAIPn_STS,WCRC[m]_CAIPn_STS is a register that indicates the state of operation related to CAIP_Lite_n module"
eventfld.long 0x00 31. "stop_done,Indicates the state of stop operation by WCRC[m]_CAIPn_STOP register" "0: Stop operation in progress or not done,1: Stop operation is done"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
eventfld.long 0x00 24. "cmd_done,Indicates the state of command function" "0: Accessing to register by command in progress or,1: Accessing to register by command is done"
rbitfld.long 0x00 21.--23. "Reserved_21,Reserved" "0,1,2,3,4,5,6,7"
newline
eventfld.long 0x00 20. "res_done,Indicates the state of result data transfer" "0: Transfer in progress or not transferring,1: Transfer is done"
hexmask.long.tbyte 0x00 1.--19. 1. "Reserved_1,Reserved"
newline
eventfld.long 0x00 0. "trans_done,Indicates the state of input data transfer" "0: Transfer in progress or not transferring,1: Transfer is done"
group.long 0x240++0x03
line.long 0x00 "WCRC1_CAIPn_INTEN,WCRC[m]_CAIPn_INTEN is a register that sets enable for the interrupt of operation related to CAIP_Lite_n module"
bitfld.long 0x00 31. "stop_done_ie,Interrupt for the complete of stop operation by WCRC[m]_CAIPn_STOP register" "0: Disable interrupt,1: Enable interrupt"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 24. "cmd_done_ie,Interrupt for the complete of command function enable" "0: Disable interrupt,1: Enable interrupt"
rbitfld.long 0x00 21.--23. "Reserved_21,Reserved" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 20. "res_done_ie,Interrupt for the complete of result data transfer enable" "0: Disable interrupt,1: Enable interrupt"
hexmask.long.tbyte 0x00 1.--19. 1. "Reserved_1,Reserved"
newline
bitfld.long 0x00 0. "trans_done_ie,Interrupt for the complete of input data transfer enable" "0: Disable interrupt,1: Enable interrupt"
group.long 0x2A0++0x03
line.long 0x00 "WCRC1_CAIPn_BUF_STS_RDEN,WCRC[m]_CAIPn_BUF_STS_RDEN is a register that sets enable for the interrupt of operation related to AES-ACC_n module"
hexmask.long.word 0x00 16.--31. 1. "Code_value,Code value (HA5A5) Set Code value to these bits when writing to this register to enable writing to this register"
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved"
newline
bitfld.long 0x00 0. "BUF_STS_RDEN,WCRC[m]_CAIPn_BUF_STS enable" "0: Disable WCRC[m]_CAIPn_BUF_STS,1: Enable WCRC[m]_CAIPn_BUF_STS"
group.long 0x400++0x03
line.long 0x00 "WCRC1_CAIPp_EN,WCRC[m]_CAIPp_EN is a register that sets enable the data transfer to/from each ports for CAIP_Lite_p interface in FIFO"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
bitfld.long 0x00 16. "out_en,Output data from Data port in FIFO enable" "0: Disable output from Data port,1: Enable output from Data port"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
bitfld.long 0x00 8. "res_en,Output result data from Result port in FIFO enable" "0: Disable output from Result port,1: Enable output from Result port"
newline
rbitfld.long 0x00 2.--7. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 1. "trans_en,Transferring data from Data port in FIFO to CAIP_Lite_p enable" "0: Disable transferring data to CAIP_Lite_p,1: Enable transferring data to CAIP_Lite_p When"
newline
bitfld.long 0x00 0. "in_en,Input data to Data/Command port in FIFO enable" "0: Disable input to Data/Command port,1: Enable input to Data/Command port"
group.long 0x420++0x03
line.long 0x00 "WCRC1_CAIPp_STOP,WCRC[m]_CAIPp_STOP is a register that stop transfer to CAIP_Lite_p interface"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
bitfld.long 0x00 0. "stop," "0,1"
group.long 0x430++0x03
line.long 0x00 "WCRC1_CAIPp_CMDEN,WCRC[m]_CAIPp_CMDEN is a register that sets enable command function for CAIP_Lite_p module"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
bitfld.long 0x00 0. "cmd_en,Command function enable" "0: Disable command function,1: Enable command function"
group.long 0x480++0x03
line.long 0x00 "WCRC1_CAIPp_WAIT,WCRC[m]_CAIPp_WAIT is a register that wait subsequent command for CAIP_Lite_p interface"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
bitfld.long 0x00 0. "wait," "0,1"
group.long 0x600++0x03
line.long 0x00 "WCRC1_CAIPp_STS,WCRC[m]_CAIPp_STS is a register that indicates the state of operation related to CAIP_Lite_p module"
eventfld.long 0x00 31. "stop_done,Indicates the state of stop operation by WCRC[m]_CAIPp_STOP register" "0: Stop operation in progress or not done,1: Stop operation is done"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
eventfld.long 0x00 24. "cmd_done,Indicates the state of command function" "0: Accessing to register by command in progress or,1: Accessing to register by command is done"
rbitfld.long 0x00 21.--23. "Reserved_21,Reserved" "0,1,2,3,4,5,6,7"
newline
eventfld.long 0x00 20. "res_done,Indicates the state of result data transfer" "0: Transfer in progress or not transferring,1: Transfer is done"
hexmask.long.tbyte 0x00 1.--19. 1. "Reserved_1,Reserved"
newline
eventfld.long 0x00 0. "trans_done,Indicates the state of input data transfer" "0: Transfer in progress or not transferring,1: Transfer is done"
group.long 0x640++0x03
line.long 0x00 "WCRC1_CAIPp_INTEN,WCRC[m]_CAIPp_INTEN is a register that sets enable for the interrupt of operation related to CAIP_Lite_p module"
bitfld.long 0x00 31. "stop_done_ie,Interrupt for the complete of stop operation by WCRC[m]_CAIPp_STOP register" "0: Disable interrupt,1: Enable interrupt"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 24. "cmd_done_ie,Interrupt for the complete of command function enable" "0: Disable interrupt,1: Enable interrupt"
rbitfld.long 0x00 21.--23. "Reserved_21,Reserved" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 20. "res_done_ie,Interrupt for the complete of result data transfer enable" "0: Disable interrupt,1: Enable interrupt"
hexmask.long.tbyte 0x00 1.--19. 1. "Reserved_1,Reserved"
newline
bitfld.long 0x00 0. "trans_done_ie,Interrupt for the complete of input data transfer enable" "0: Disable interrupt,1: Enable interrupt"
group.long 0x6A0++0x03
line.long 0x00 "WCRC1_CAIPp_BUF_STS_RDEN,WCRC[m]_CAIPp_BUF_STS_RDEN is a register that sets enable for the interrupt of operation related to AES-ACC_p module"
hexmask.long.word 0x00 16.--31. 1. "Code_value,Code value (HA5A5) Set Code value to these bits when writing to this register to enable writing to this register"
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved"
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bitfld.long 0x00 0. "BUF_STS_RDEN,WCRC[m]_CAIPp_BUF_STS enable" "0: Disable WCRC[m]_CAIPp_BUF_STS,1: Enable WCRC[m]_CAIPp_BUF_STS"
group.long 0x800++0x03
line.long 0x00 "WCRC1_CRC1_EN,WCRC[m]_CRC[m]_EN is a register that sets enable the data transfer to/from each port for CRC[m] module in FIFO"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
bitfld.long 0x00 16. "out_en,Output data from Data port in FIFO enable" "0: Disable output from Data port,1: Enable output from Data port"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
bitfld.long 0x00 8. "res_en,Output result data from Result port in FIFO enable" "0: Disable output from Result port,1: Enable output from Result port"
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rbitfld.long 0x00 2.--7. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 1. "trans_en,Transferring data from Data port in FIFO to CRC[m] enable" "0: Disable transferring data to CRC[m],1: Enable transferring data to CRC[m] When.."
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bitfld.long 0x00 0. "in_en,Input data to Data/Command/Expected data port in FIFO enable" "0: Disable input to Data/Command/Expected data..,1: Enable input to Data/Command/Expected data port"
group.long 0x820++0x03
line.long 0x00 "WCRC1_CRC1_STOP,WCRC[m]_CRC[m]_STOP is a register that stop transfer to CRC[m] module"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
bitfld.long 0x00 0. "stop," "0,1"
group.long 0x830++0x03
line.long 0x00 "WCRC1_CRC1_CMDEN,WCRC[m]_CRC[m]_CMDEN is a register that sets enable command function for CRC[m] module"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
bitfld.long 0x00 0. "cmd_en,Command function enable" "0: Disable command function,1: Enable command function"
group.long 0x840++0x03
line.long 0x00 "WCRC1_CRC1_COMP,WCRC[m]_CRC[m]_COMP is a register that sets enable comparing CRC result from CRC[m] module with expected data in FIFO"
hexmask.long.word 0x00 18.--31. 1. "Reserved_18,Reserved"
bitfld.long 0x00 16.--17. "cmp_freq,Set the frequency of comparing" "0,1,2,3"
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hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved"
bitfld.long 0x00 1. "exp_reqsel,Select DMA Transfer request source for transferring expected data" "0: dmareq_wcrcm_crcm_in,1: dmareq_wcrcm_crcm_res m"
newline
bitfld.long 0x00 0. "cmp_en,Comparing CRC result with expected data enable" "0: Disable comparing function,1: Enable comparing function"
group.long 0x850++0x03
line.long 0x00 "WCRC1_CRC1_COMP_RES,WCRC[m]_CRC[m]_COMP_RES is a register that indicates the result of comparing CRC for CRC[m] module"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved"
abitfld.long 0x00 0.--15. "cmp_res,The result of comparing CRC These bits indicate mismatched point of comparing data in 4-byte units" "0x0000=0: No error,0x0001=1: Mismatch Figure 135.4"
group.long 0x870++0x03
line.long 0x00 "WCRC1_CRC1_CONV,WCRC[m]_CRC[m]_CONV is a register that sets CRC conversion size to once for CRC[m] module"
hexmask.long.word 0x00 21.--31. 1. "Reserved_21,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--20. 1. "conv,CRC conversion size specification Specifies the CRC conversion size in 1-byte units"
group.long 0x880++0x03
line.long 0x00 "WCRC1_CRC1_WAIT,WCRC[m]_CRC[m]_WAIT is a register that wait subsequent command for CRC[m] module"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
bitfld.long 0x00 0. "wait," "0,1"
group.long 0x910++0x03
line.long 0x00 "WCRC1_CRC1_INIT_CRC,WCRC[m]_CRC[m]_INIT_CRC is a register that sets CRC code value to DCRAmCOUT register at auto clear"
hexmask.long 0x00 0.--31. 1. "init_code,CRC code value to DCRAmCOUT register at auto clear"
group.long 0xA00++0x03
line.long 0x00 "WCRC1_CRC1_STS,WCRC[m]_CRC[m]_STS is a register that indicates the state of operation related to CRC[m] module"
eventfld.long 0x00 31. "stop_done,Indicates the state of stop operation by WCRC[m]_CRC[m]_STOP register" "0: Stop operation in progress or not done,1: Stop operation is done"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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eventfld.long 0x00 24. "cmd_done,Indicates the state of command function" "0: Accessing to register by command in progress or,1: Accessing to register by command is done"
rbitfld.long 0x00 21.--23. "Reserved_21,Reserved" "0,1,2,3,4,5,6,7"
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eventfld.long 0x00 20. "res_done,Indicates the state of result data transfer" "0: Transfer in progress or not transferring,1: Transfer is done"
rbitfld.long 0x00 14.--19. "Reserved_14,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
eventfld.long 0x00 13. "comp_err,Indicates the error of comparing CRC" "0: No comparing error or not comparing,1: Mismatch has occurred"
eventfld.long 0x00 12. "comp_done,Indicates the state of comparing CRC" "0: Comparison in progress or not comparing,1: Comparing is done"
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hexmask.long.word 0x00 1.--11. 1. "Reserved_1,Reserved"
eventfld.long 0x00 0. "trans_done,Indicates the state of input data transfer" "0: Transfer in progress or not transferring,1: Transfer is done"
group.long 0xA40++0x03
line.long 0x00 "WCRC1_CRC1_INTEN,WCRC[m]_CRC[m]_INTEN is a register that sets enable for the interrupt of operation related to CRC[m] module"
bitfld.long 0x00 31. "stop_done_ie,Interrupt for the complete of stop operation by WCRC[m]_CRC[m]_STOP register" "0: Disable interrupt,1: Enable interrupt"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 24. "cmd_done_ie,Interrupt for the complete of command function enable" "0: Disable interrupt,1: Enable interrupt"
rbitfld.long 0x00 21.--23. "Reserved_21,Reserved" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 20. "res_done_ie,Interrupt for the complete of result data transfer enable" "0: Disable interrupt,1: Enable interrupt"
rbitfld.long 0x00 14.--19. "Reserved_14,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 13. "comp_err_ie,Interrupt for the error of comparing CRC enable" "0: Disable interrupt,1: Enable interrupt"
bitfld.long 0x00 12. "comp_done_ie,Interrupt for the complete of comparing CRC enable" "0: Disable interrupt,1: Enable interrupt"
newline
hexmask.long.word 0x00 1.--11. 1. "Reserved_1,Reserved"
bitfld.long 0x00 0. "trans_done_ie,Interrupt for the complete of input data transfer enable" "0: Disable interrupt,1: Enable interrupt"
group.long 0xA80++0x03
line.long 0x00 "WCRC1_CRC1_ECMEN,WCRC[m]_CRC[m]_ECMEN is a register that sets enable for error notification to ECM module on operation related to CRC[m] module"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved"
bitfld.long 0x00 13. "comp_err_oe,Error notification for the error of comparing CRC enable" "0: Disable notification,1: Enable notification"
newline
hexmask.long.word 0x00 0.--12. 1. "Reserved_0,Reserved"
group.long 0xAA0++0x03
line.long 0x00 "WCRC1_CRC1_BUF_STS_RDEN,WCRC[m]_CRC[m]_BUF_STS_RDEN is a register that sets enable for the interrupt of operation related to CRC[m] module"
hexmask.long.word 0x00 16.--31. 1. "Code_value,Code value (HA5A5) Set Code value to these bits when writing to this register to enable writing to this register"
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved"
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bitfld.long 0x00 0. "BUF_STS_RDEN,WCRC[m]_CRC[m]_BUF_STS enable" "0: Disable WCRC[m]_CRC[m]_BUF_STS,1: Enable WCRC[m]_CRC[m]_BUF_STS"
group.long 0xC00++0x03
line.long 0x00 "WCRC1_KCRC1_EN,WCRC[m]_KCRC[m]_EN is a register that sets enable the data transfer to/from each port for KCRC[m] module in FIFO"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
bitfld.long 0x00 16. "out_en,Output data from Data port in FIFO enable" "0: Disable output from Data port,1: Enable output from Data port"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
bitfld.long 0x00 8. "res_en,Output result data from Result port in FIFO enable" "0: Disable output from Result port,1: Enable output from Result port"
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rbitfld.long 0x00 2.--7. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 1. "trans_en,Transferring data from Data port in FIFO to KCRC[m] enable" "0: Disable transferring data to KCRC[m],1: Enable transferring data to KCRC[m] When"
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bitfld.long 0x00 0. "in_en,Input data to Data/Command/Expected data port in FIFO enable" "0: Disable input to Data/Command/Expected data..,1: Enable input to Data/Command/Expected data port"
group.long 0xC20++0x03
line.long 0x00 "WCRC1_KCRC1_STOP,WCRC[m]_KCRC[m]_STOP is a register that stop transfer to KCRC[m] module"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
bitfld.long 0x00 0. "stop," "0,1"
group.long 0xC30++0x03
line.long 0x00 "WCRC1_KCRC1_CMDEN,WCRC[m]_KCRC[m]_CMDEN is a register that sets enable command function for KCRC[m] module"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
bitfld.long 0x00 0. "cmd_en,Command function enable" "0: Disable command function,1: Enable command function"
group.long 0xC40++0x03
line.long 0x00 "WCRC1_KCRC1_COMP,WCRC[m]_KCRC[m]_COMP is a register that sets enable comparing CRC result from KCRC[m] module with expected data in FIFO"
hexmask.long.word 0x00 18.--31. 1. "Reserved_18,Reserved"
bitfld.long 0x00 16.--17. "cmp_freq,Set the frequency of comparing" "0,1,2,3"
newline
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved"
bitfld.long 0x00 1. "exp_reqsel,Select DMA Transfer request source for transferring expected data" "0: dmareq_wcrcm_kcrcn_in,1: dmareq_wcrcm_kcrcn_res m"
newline
bitfld.long 0x00 0. "cmp_en,Comparing CRC result with expected data enable" "0: Disable comparing function,1: Enable comparing function"
group.long 0xC50++0x03
line.long 0x00 "WCRC1_KCRC1_COMP_RES,WCRC[m]_KCRC[m]_COMP_RES is a register that indicates the result of comparing CRC for KCRC[m] module"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved"
abitfld.long 0x00 0.--15. "cmp_res,The result of comparing CRC These bits indicate mismatched point of comparing data in 4-byte units" "0x0000=0: No error,0x0001=1: Mismatch Figure 135.4"
group.long 0xC70++0x03
line.long 0x00 "WCRC1_KCRC1_CONV,WCRC[m]_KCRC[m]_CONV is a register that sets CRC conversion size to once for KCRC[m] module"
hexmask.long.word 0x00 21.--31. 1. "Reserved_21,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--20. 1. "conv,CRC conversion size specification Specifies the CRC conversion size in 1-byte units"
group.long 0xC80++0x03
line.long 0x00 "WCRC1_KCRC1_WAIT,WCRC[m]_KCRC[m]_WAIT is a register that wait subsequent command for KCRC[m] module"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
bitfld.long 0x00 0. "wait," "0,1"
group.long 0xD10++0x03
line.long 0x00 "WCRC1_KCRC1_INIT_CRC,WCRC[m]_KCRC[m]_INIT_CRC is a register that sets CRC code value to KCRC[m]COUT register at auto clear"
hexmask.long 0x00 0.--31. 1. "init_code,CRC code value to KCRC[m]DOUT register at auto clear"
group.long 0xE00++0x03
line.long 0x00 "WCRC1_KCRC1_STS,WCRC[m]_KCRC[m]_STS is a register that indicates the state of operation related to KCRC[m] module"
eventfld.long 0x00 31. "stop_done,Indicates the state of stop operation by WCRC[m]_KCRC[m]_STOP register" "0: Stop operation in progress or not done,1: Stop operation is done"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
eventfld.long 0x00 24. "cmd_done,Indicates the state of command function" "0: Accessing to register by command in progress or,1: Accessing to register by command is done"
rbitfld.long 0x00 21.--23. "Reserved_21,Reserved" "0,1,2,3,4,5,6,7"
newline
eventfld.long 0x00 20. "res_done,Indicates the state of result data transfer" "0: Transfer in progress or not transferring,1: Transfer is done"
rbitfld.long 0x00 14.--19. "Reserved_14,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
eventfld.long 0x00 13. "comp_err,Indicates the error of comparing CRC" "0: No comparing error or not comparing,1: Mismatch has occurred"
eventfld.long 0x00 12. "comp_done,Indicates the state of comparing CRC" "0: Comparison in progress or not comparing,1: Comparing is done"
newline
hexmask.long.word 0x00 1.--11. 1. "Reserved_1,Reserved"
eventfld.long 0x00 0. "trans_done,Indicates the state of input data transfer" "0: Transfer in progress or not transferring,1: Transfer is done"
group.long 0xE40++0x03
line.long 0x00 "WCRC1_KCRC1_INTEN,WCRC[m]_KCRC[m]_INTEN is a register that sets enable for the interrupt of operation related to KCRC[m] module"
bitfld.long 0x00 31. "stop_done_ie,Interrupt for the complete of stop operation by WCRC[m]_KCRC[m]_STOP register" "0: Disable interrupt,1: Enable interrupt"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 24. "cmd_done_ie,Interrupt for the complete of command function enable" "0: Disable interrupt,1: Enable interrupt"
rbitfld.long 0x00 21.--23. "Reserved_21,Reserved" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 20. "res_done_ie,Interrupt for the complete of result data transfer enable" "0: Disable interrupt,1: Enable interrupt"
rbitfld.long 0x00 14.--19. "Reserved_14,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 13. "comp_err_ie,Interrupt for the error of comparing CRC enable" "0: Disable interrupt,1: Enable interrupt"
bitfld.long 0x00 12. "comp_done_ie,Interrupt for the complete of comparing CRC enable" "0: Disable interrupt,1: Enable interrupt"
newline
hexmask.long.word 0x00 1.--11. 1. "Reserved_1,Reserved"
bitfld.long 0x00 0. "trans_done_ie,Interrupt for the complete of input data transfer enable" "0: Disable interrupt,1: Enable interrupt"
group.long 0xE80++0x03
line.long 0x00 "WCRC1_KCRC1_ECMEN,WCRC[m]_KCRC[m]_ECMEN is a register that sets enable for error notification to ECM module on operation related to KCRC[m] module"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved"
bitfld.long 0x00 13. "comp_err_oe,Error notification for the error of comparing CRC enable" "0: Disable notification,1: Enable notification"
newline
hexmask.long.word 0x00 0.--12. 1. "Reserved_0,Reserved"
group.long 0xEA0++0x03
line.long 0x00 "WCRC1_KCRC1_BUF_STS_RDEN,WCRC[m]_KCRC[m]_BUF_STS_RDEN is a register that sets enable for the interrupt of operation related to KCRC[m] module"
hexmask.long.word 0x00 16.--31. 1. "Code_value,Code value (HA5A5) Set Code value to these bits when writing to this register to enable writing to this register"
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved"
newline
bitfld.long 0x00 0. "BUF_STS_RDEN,WCRC[m]_KCRC[m]_BUF_STS enable" "0: Disable WCRC[m]_KCRC[m]_BUF_STS,1: Enable WCRC[m]_KCRC[m]_BUF_STS"
group.long 0xF00++0x03
line.long 0x00 "WCRC1_COMMON_STS,WCRC[m]_COMMON_STS is a register that indicates the state of operation related to WCRC[m] module"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved"
eventfld.long 0x00 16. "edc_err,Indicates the error of EDC" "0: No EDC error,1: EDC error has occurred"
newline
hexmask.long.word 0x00 0.--15. 1. "Reserved_0,Reserved"
group.long 0xF40++0x03
line.long 0x00 "WCRC1_COMMON_INTEN,WCRC[m]_COMMON_INTEN is a register that sets enable for the interrupt of operation related to WCRC[m] module"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved"
bitfld.long 0x00 16. "edc_err_ie,Interrupt for the error of EDC enable" "0: Disable interrupt,1: Enable interrupt"
newline
hexmask.long.word 0x00 0.--15. 1. "Reserved_0,Reserved"
group.long 0xF80++0x03
line.long 0x00 "WCRC1_COMMON_ECMEN,WCRC[m]_COMMON_ECMEN is a register that sets enable for error notification to ECM module on operation related to WCRC[m] module"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved"
bitfld.long 0x00 16. "edc_err_oe,Error notification for EDC error enable" "0: Disable notification,1: Enable notification"
newline
hexmask.long.word 0x00 0.--15. 1. "Reserved_0,Reserved"
group.long 0xFC0++0x03
line.long 0x00 "WCRC1_ERRINJ,WCRC[m]_ERRINJ is a register that sets enable error injection for bus data signal or EDC code signal"
hexmask.long.word 0x00 16.--31. 1. "code,Code value Set HA5A5 due to enable error injection"
hexmask.long.word 0x00 3.--15. 1. "Reserved_3,Reserved"
newline
bitfld.long 0x00 0.--2. "err_inj_2_0,Error injection enable Bit[0]" "0: Disables error for EDC code signal,1: Enables error for EDC code signal,?..."
tree.end
tree "CRC_INST_2"
base ad:0xE70A0000
group.long 0x00++0x03
line.long 0x00 "WCRC2_CAIPn_EN,WCRC[m]_CAIPn_EN is a register that sets enable the data transfer to/from each port for CAIP_Lite_n interface in FIFO"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
bitfld.long 0x00 16. "out_en,Output data from Data port in FIFO enable" "0: Disable output from Data port,1: Enable output from Data port"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
bitfld.long 0x00 8. "res_en,Output result data from Result port in FIFO enable" "0: Disable output from Result port,1: Enable output from Result port"
newline
rbitfld.long 0x00 2.--7. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 1. "trans_en,Transferring data from Data port in FIFO to CAIP_Lite_n enable" "0: Disable transferring data to CAIP_Lite_n,1: Enable transferring data to CAIP_Lite_n When"
newline
bitfld.long 0x00 0. "in_en,Input data to Data/Command port in FIFO enable" "0: Disable input to Data/Command port,1: Enable input to Data/Command port"
group.long 0x20++0x03
line.long 0x00 "WCRC2_CAIPn_STOP,WCRC[m]_CAIPn_STOP is a register that stop transfer to CAIP_Lite_n interface"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
bitfld.long 0x00 0. "stop," "0,1"
group.long 0x30++0x03
line.long 0x00 "WCRC2_CAIPn_CMDEN,WCRC[m]_CAIPn_CMDEN is a register that sets enable command function for CAIP_Lite_n module"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
bitfld.long 0x00 0. "cmd_en,Command function enable" "0: Disable command function,1: Enable command function"
group.long 0x80++0x03
line.long 0x00 "WCRC2_CAIPn_WAIT,WCRC[m]_CAIPn_WAIT is a register that wait subsequent command for CAIP_Lite_n interface"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
bitfld.long 0x00 0. "wait," "0,1"
group.long 0x200++0x03
line.long 0x00 "WCRC2_CAIPn_STS,WCRC[m]_CAIPn_STS is a register that indicates the state of operation related to CAIP_Lite_n module"
eventfld.long 0x00 31. "stop_done,Indicates the state of stop operation by WCRC[m]_CAIPn_STOP register" "0: Stop operation in progress or not done,1: Stop operation is done"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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eventfld.long 0x00 24. "cmd_done,Indicates the state of command function" "0: Accessing to register by command in progress or,1: Accessing to register by command is done"
rbitfld.long 0x00 21.--23. "Reserved_21,Reserved" "0,1,2,3,4,5,6,7"
newline
eventfld.long 0x00 20. "res_done,Indicates the state of result data transfer" "0: Transfer in progress or not transferring,1: Transfer is done"
hexmask.long.tbyte 0x00 1.--19. 1. "Reserved_1,Reserved"
newline
eventfld.long 0x00 0. "trans_done,Indicates the state of input data transfer" "0: Transfer in progress or not transferring,1: Transfer is done"
group.long 0x240++0x03
line.long 0x00 "WCRC2_CAIPn_INTEN,WCRC[m]_CAIPn_INTEN is a register that sets enable for the interrupt of operation related to CAIP_Lite_n module"
bitfld.long 0x00 31. "stop_done_ie,Interrupt for the complete of stop operation by WCRC[m]_CAIPn_STOP register" "0: Disable interrupt,1: Enable interrupt"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 24. "cmd_done_ie,Interrupt for the complete of command function enable" "0: Disable interrupt,1: Enable interrupt"
rbitfld.long 0x00 21.--23. "Reserved_21,Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 20. "res_done_ie,Interrupt for the complete of result data transfer enable" "0: Disable interrupt,1: Enable interrupt"
hexmask.long.tbyte 0x00 1.--19. 1. "Reserved_1,Reserved"
newline
bitfld.long 0x00 0. "trans_done_ie,Interrupt for the complete of input data transfer enable" "0: Disable interrupt,1: Enable interrupt"
group.long 0x2A0++0x03
line.long 0x00 "WCRC2_CAIPn_BUF_STS_RDEN,WCRC[m]_CAIPn_BUF_STS_RDEN is a register that sets enable for the interrupt of operation related to AES-ACC_n module"
hexmask.long.word 0x00 16.--31. 1. "Code_value,Code value (HA5A5) Set Code value to these bits when writing to this register to enable writing to this register"
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved"
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bitfld.long 0x00 0. "BUF_STS_RDEN,WCRC[m]_CAIPn_BUF_STS enable" "0: Disable WCRC[m]_CAIPn_BUF_STS,1: Enable WCRC[m]_CAIPn_BUF_STS"
group.long 0x400++0x03
line.long 0x00 "WCRC2_CAIPp_EN,WCRC[m]_CAIPp_EN is a register that sets enable the data transfer to/from each ports for CAIP_Lite_p interface in FIFO"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
bitfld.long 0x00 16. "out_en,Output data from Data port in FIFO enable" "0: Disable output from Data port,1: Enable output from Data port"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
bitfld.long 0x00 8. "res_en,Output result data from Result port in FIFO enable" "0: Disable output from Result port,1: Enable output from Result port"
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rbitfld.long 0x00 2.--7. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 1. "trans_en,Transferring data from Data port in FIFO to CAIP_Lite_p enable" "0: Disable transferring data to CAIP_Lite_p,1: Enable transferring data to CAIP_Lite_p When"
newline
bitfld.long 0x00 0. "in_en,Input data to Data/Command port in FIFO enable" "0: Disable input to Data/Command port,1: Enable input to Data/Command port"
group.long 0x420++0x03
line.long 0x00 "WCRC2_CAIPp_STOP,WCRC[m]_CAIPp_STOP is a register that stop transfer to CAIP_Lite_p interface"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
bitfld.long 0x00 0. "stop," "0,1"
group.long 0x430++0x03
line.long 0x00 "WCRC2_CAIPp_CMDEN,WCRC[m]_CAIPp_CMDEN is a register that sets enable command function for CAIP_Lite_p module"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
bitfld.long 0x00 0. "cmd_en,Command function enable" "0: Disable command function,1: Enable command function"
group.long 0x480++0x03
line.long 0x00 "WCRC2_CAIPp_WAIT,WCRC[m]_CAIPp_WAIT is a register that wait subsequent command for CAIP_Lite_p interface"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
bitfld.long 0x00 0. "wait," "0,1"
group.long 0x600++0x03
line.long 0x00 "WCRC2_CAIPp_STS,WCRC[m]_CAIPp_STS is a register that indicates the state of operation related to CAIP_Lite_p module"
eventfld.long 0x00 31. "stop_done,Indicates the state of stop operation by WCRC[m]_CAIPp_STOP register" "0: Stop operation in progress or not done,1: Stop operation is done"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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eventfld.long 0x00 24. "cmd_done,Indicates the state of command function" "0: Accessing to register by command in progress or,1: Accessing to register by command is done"
rbitfld.long 0x00 21.--23. "Reserved_21,Reserved" "0,1,2,3,4,5,6,7"
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eventfld.long 0x00 20. "res_done,Indicates the state of result data transfer" "0: Transfer in progress or not transferring,1: Transfer is done"
hexmask.long.tbyte 0x00 1.--19. 1. "Reserved_1,Reserved"
newline
eventfld.long 0x00 0. "trans_done,Indicates the state of input data transfer" "0: Transfer in progress or not transferring,1: Transfer is done"
group.long 0x640++0x03
line.long 0x00 "WCRC2_CAIPp_INTEN,WCRC[m]_CAIPp_INTEN is a register that sets enable for the interrupt of operation related to CAIP_Lite_p module"
bitfld.long 0x00 31. "stop_done_ie,Interrupt for the complete of stop operation by WCRC[m]_CAIPp_STOP register" "0: Disable interrupt,1: Enable interrupt"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 24. "cmd_done_ie,Interrupt for the complete of command function enable" "0: Disable interrupt,1: Enable interrupt"
rbitfld.long 0x00 21.--23. "Reserved_21,Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 20. "res_done_ie,Interrupt for the complete of result data transfer enable" "0: Disable interrupt,1: Enable interrupt"
hexmask.long.tbyte 0x00 1.--19. 1. "Reserved_1,Reserved"
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bitfld.long 0x00 0. "trans_done_ie,Interrupt for the complete of input data transfer enable" "0: Disable interrupt,1: Enable interrupt"
group.long 0x6A0++0x03
line.long 0x00 "WCRC2_CAIPp_BUF_STS_RDEN,WCRC[m]_CAIPp_BUF_STS_RDEN is a register that sets enable for the interrupt of operation related to AES-ACC_p module"
hexmask.long.word 0x00 16.--31. 1. "Code_value,Code value (HA5A5) Set Code value to these bits when writing to this register to enable writing to this register"
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved"
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bitfld.long 0x00 0. "BUF_STS_RDEN,WCRC[m]_CAIPp_BUF_STS enable" "0: Disable WCRC[m]_CAIPp_BUF_STS,1: Enable WCRC[m]_CAIPp_BUF_STS"
group.long 0x800++0x03
line.long 0x00 "WCRC2_CRC2_EN,WCRC[m]_CRC[m]_EN is a register that sets enable the data transfer to/from each port for CRC[m] module in FIFO"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
bitfld.long 0x00 16. "out_en,Output data from Data port in FIFO enable" "0: Disable output from Data port,1: Enable output from Data port"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
bitfld.long 0x00 8. "res_en,Output result data from Result port in FIFO enable" "0: Disable output from Result port,1: Enable output from Result port"
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rbitfld.long 0x00 2.--7. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 1. "trans_en,Transferring data from Data port in FIFO to CRC[m] enable" "0: Disable transferring data to CRC[m],1: Enable transferring data to CRC[m] When.."
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bitfld.long 0x00 0. "in_en,Input data to Data/Command/Expected data port in FIFO enable" "0: Disable input to Data/Command/Expected data..,1: Enable input to Data/Command/Expected data port"
group.long 0x820++0x03
line.long 0x00 "WCRC2_CRC2_STOP,WCRC[m]_CRC[m]_STOP is a register that stop transfer to CRC[m] module"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
bitfld.long 0x00 0. "stop," "0,1"
group.long 0x830++0x03
line.long 0x00 "WCRC2_CRC2_CMDEN,WCRC[m]_CRC[m]_CMDEN is a register that sets enable command function for CRC[m] module"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
bitfld.long 0x00 0. "cmd_en,Command function enable" "0: Disable command function,1: Enable command function"
group.long 0x840++0x03
line.long 0x00 "WCRC2_CRC2_COMP,WCRC[m]_CRC[m]_COMP is a register that sets enable comparing CRC result from CRC[m] module with expected data in FIFO"
hexmask.long.word 0x00 18.--31. 1. "Reserved_18,Reserved"
bitfld.long 0x00 16.--17. "cmp_freq,Set the frequency of comparing" "0,1,2,3"
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hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved"
bitfld.long 0x00 1. "exp_reqsel,Select DMA Transfer request source for transferring expected data" "0: dmareq_wcrcm_crcm_in,1: dmareq_wcrcm_crcm_res m"
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bitfld.long 0x00 0. "cmp_en,Comparing CRC result with expected data enable" "0: Disable comparing function,1: Enable comparing function"
group.long 0x850++0x03
line.long 0x00 "WCRC2_CRC2_COMP_RES,WCRC[m]_CRC[m]_COMP_RES is a register that indicates the result of comparing CRC for CRC[m] module"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved"
abitfld.long 0x00 0.--15. "cmp_res,The result of comparing CRC These bits indicate mismatched point of comparing data in 4-byte units" "0x0000=0: No error,0x0001=1: Mismatch Figure 135.4"
group.long 0x870++0x03
line.long 0x00 "WCRC2_CRC2_CONV,WCRC[m]_CRC[m]_CONV is a register that sets CRC conversion size to once for CRC[m] module"
hexmask.long.word 0x00 21.--31. 1. "Reserved_21,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--20. 1. "conv,CRC conversion size specification Specifies the CRC conversion size in 1-byte units"
group.long 0x880++0x03
line.long 0x00 "WCRC2_CRC2_WAIT,WCRC[m]_CRC[m]_WAIT is a register that wait subsequent command for CRC[m] module"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
bitfld.long 0x00 0. "wait," "0,1"
group.long 0x910++0x03
line.long 0x00 "WCRC2_CRC2_INIT_CRC,WCRC[m]_CRC[m]_INIT_CRC is a register that sets CRC code value to DCRAmCOUT register at auto clear"
hexmask.long 0x00 0.--31. 1. "init_code,CRC code value to DCRAmCOUT register at auto clear"
group.long 0xA00++0x03
line.long 0x00 "WCRC2_CRC2_STS,WCRC[m]_CRC[m]_STS is a register that indicates the state of operation related to CRC[m] module"
eventfld.long 0x00 31. "stop_done,Indicates the state of stop operation by WCRC[m]_CRC[m]_STOP register" "0: Stop operation in progress or not done,1: Stop operation is done"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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eventfld.long 0x00 24. "cmd_done,Indicates the state of command function" "0: Accessing to register by command in progress or,1: Accessing to register by command is done"
rbitfld.long 0x00 21.--23. "Reserved_21,Reserved" "0,1,2,3,4,5,6,7"
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eventfld.long 0x00 20. "res_done,Indicates the state of result data transfer" "0: Transfer in progress or not transferring,1: Transfer is done"
rbitfld.long 0x00 14.--19. "Reserved_14,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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eventfld.long 0x00 13. "comp_err,Indicates the error of comparing CRC" "0: No comparing error or not comparing,1: Mismatch has occurred"
eventfld.long 0x00 12. "comp_done,Indicates the state of comparing CRC" "0: Comparison in progress or not comparing,1: Comparing is done"
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hexmask.long.word 0x00 1.--11. 1. "Reserved_1,Reserved"
eventfld.long 0x00 0. "trans_done,Indicates the state of input data transfer" "0: Transfer in progress or not transferring,1: Transfer is done"
group.long 0xA40++0x03
line.long 0x00 "WCRC2_CRC2_INTEN,WCRC[m]_CRC[m]_INTEN is a register that sets enable for the interrupt of operation related to CRC[m] module"
bitfld.long 0x00 31. "stop_done_ie,Interrupt for the complete of stop operation by WCRC[m]_CRC[m]_STOP register" "0: Disable interrupt,1: Enable interrupt"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 24. "cmd_done_ie,Interrupt for the complete of command function enable" "0: Disable interrupt,1: Enable interrupt"
rbitfld.long 0x00 21.--23. "Reserved_21,Reserved" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 20. "res_done_ie,Interrupt for the complete of result data transfer enable" "0: Disable interrupt,1: Enable interrupt"
rbitfld.long 0x00 14.--19. "Reserved_14,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 13. "comp_err_ie,Interrupt for the error of comparing CRC enable" "0: Disable interrupt,1: Enable interrupt"
bitfld.long 0x00 12. "comp_done_ie,Interrupt for the complete of comparing CRC enable" "0: Disable interrupt,1: Enable interrupt"
newline
hexmask.long.word 0x00 1.--11. 1. "Reserved_1,Reserved"
bitfld.long 0x00 0. "trans_done_ie,Interrupt for the complete of input data transfer enable" "0: Disable interrupt,1: Enable interrupt"
group.long 0xA80++0x03
line.long 0x00 "WCRC2_CRC2_ECMEN,WCRC[m]_CRC[m]_ECMEN is a register that sets enable for error notification to ECM module on operation related to CRC[m] module"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved"
bitfld.long 0x00 13. "comp_err_oe,Error notification for the error of comparing CRC enable" "0: Disable notification,1: Enable notification"
newline
hexmask.long.word 0x00 0.--12. 1. "Reserved_0,Reserved"
group.long 0xAA0++0x03
line.long 0x00 "WCRC2_CRC2_BUF_STS_RDEN,WCRC[m]_CRC[m]_BUF_STS_RDEN is a register that sets enable for the interrupt of operation related to CRC[m] module"
hexmask.long.word 0x00 16.--31. 1. "Code_value,Code value (HA5A5) Set Code value to these bits when writing to this register to enable writing to this register"
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved"
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bitfld.long 0x00 0. "BUF_STS_RDEN,WCRC[m]_CRC[m]_BUF_STS enable" "0: Disable WCRC[m]_CRC[m]_BUF_STS,1: Enable WCRC[m]_CRC[m]_BUF_STS"
group.long 0xC00++0x03
line.long 0x00 "WCRC2_KCRC2_EN,WCRC[m]_KCRC[m]_EN is a register that sets enable the data transfer to/from each port for KCRC[m] module in FIFO"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
bitfld.long 0x00 16. "out_en,Output data from Data port in FIFO enable" "0: Disable output from Data port,1: Enable output from Data port"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
bitfld.long 0x00 8. "res_en,Output result data from Result port in FIFO enable" "0: Disable output from Result port,1: Enable output from Result port"
newline
rbitfld.long 0x00 2.--7. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 1. "trans_en,Transferring data from Data port in FIFO to KCRC[m] enable" "0: Disable transferring data to KCRC[m],1: Enable transferring data to KCRC[m] When"
newline
bitfld.long 0x00 0. "in_en,Input data to Data/Command/Expected data port in FIFO enable" "0: Disable input to Data/Command/Expected data..,1: Enable input to Data/Command/Expected data port"
group.long 0xC20++0x03
line.long 0x00 "WCRC2_KCRC2_STOP,WCRC[m]_KCRC[m]_STOP is a register that stop transfer to KCRC[m] module"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
bitfld.long 0x00 0. "stop," "0,1"
group.long 0xC30++0x03
line.long 0x00 "WCRC2_KCRC2_CMDEN,WCRC[m]_KCRC[m]_CMDEN is a register that sets enable command function for KCRC[m] module"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
bitfld.long 0x00 0. "cmd_en,Command function enable" "0: Disable command function,1: Enable command function"
group.long 0xC40++0x03
line.long 0x00 "WCRC2_KCRC2_COMP,WCRC[m]_KCRC[m]_COMP is a register that sets enable comparing CRC result from KCRC[m] module with expected data in FIFO"
hexmask.long.word 0x00 18.--31. 1. "Reserved_18,Reserved"
bitfld.long 0x00 16.--17. "cmp_freq,Set the frequency of comparing" "0,1,2,3"
newline
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved"
bitfld.long 0x00 1. "exp_reqsel,Select DMA Transfer request source for transferring expected data" "0: dmareq_wcrcm_kcrcn_in,1: dmareq_wcrcm_kcrcn_res m"
newline
bitfld.long 0x00 0. "cmp_en,Comparing CRC result with expected data enable" "0: Disable comparing function,1: Enable comparing function"
group.long 0xC50++0x03
line.long 0x00 "WCRC2_KCRC2_COMP_RES,WCRC[m]_KCRC[m]_COMP_RES is a register that indicates the result of comparing CRC for KCRC[m] module"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved"
abitfld.long 0x00 0.--15. "cmp_res,The result of comparing CRC These bits indicate mismatched point of comparing data in 4-byte units" "0x0000=0: No error,0x0001=1: Mismatch Figure 135.4"
group.long 0xC70++0x03
line.long 0x00 "WCRC2_KCRC2_CONV,WCRC[m]_KCRC[m]_CONV is a register that sets CRC conversion size to once for KCRC[m] module"
hexmask.long.word 0x00 21.--31. 1. "Reserved_21,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--20. 1. "conv,CRC conversion size specification Specifies the CRC conversion size in 1-byte units"
group.long 0xC80++0x03
line.long 0x00 "WCRC2_KCRC2_WAIT,WCRC[m]_KCRC[m]_WAIT is a register that wait subsequent command for KCRC[m] module"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
bitfld.long 0x00 0. "wait," "0,1"
group.long 0xD10++0x03
line.long 0x00 "WCRC2_KCRC2_INIT_CRC,WCRC[m]_KCRC[m]_INIT_CRC is a register that sets CRC code value to KCRC[m]COUT register at auto clear"
hexmask.long 0x00 0.--31. 1. "init_code,CRC code value to KCRC[m]DOUT register at auto clear"
group.long 0xE00++0x03
line.long 0x00 "WCRC2_KCRC2_STS,WCRC[m]_KCRC[m]_STS is a register that indicates the state of operation related to KCRC[m] module"
eventfld.long 0x00 31. "stop_done,Indicates the state of stop operation by WCRC[m]_KCRC[m]_STOP register" "0: Stop operation in progress or not done,1: Stop operation is done"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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eventfld.long 0x00 24. "cmd_done,Indicates the state of command function" "0: Accessing to register by command in progress or,1: Accessing to register by command is done"
rbitfld.long 0x00 21.--23. "Reserved_21,Reserved" "0,1,2,3,4,5,6,7"
newline
eventfld.long 0x00 20. "res_done,Indicates the state of result data transfer" "0: Transfer in progress or not transferring,1: Transfer is done"
rbitfld.long 0x00 14.--19. "Reserved_14,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
eventfld.long 0x00 13. "comp_err,Indicates the error of comparing CRC" "0: No comparing error or not comparing,1: Mismatch has occurred"
eventfld.long 0x00 12. "comp_done,Indicates the state of comparing CRC" "0: Comparison in progress or not comparing,1: Comparing is done"
newline
hexmask.long.word 0x00 1.--11. 1. "Reserved_1,Reserved"
eventfld.long 0x00 0. "trans_done,Indicates the state of input data transfer" "0: Transfer in progress or not transferring,1: Transfer is done"
group.long 0xE40++0x03
line.long 0x00 "WCRC2_KCRC2_INTEN,WCRC[m]_KCRC[m]_INTEN is a register that sets enable for the interrupt of operation related to KCRC[m] module"
bitfld.long 0x00 31. "stop_done_ie,Interrupt for the complete of stop operation by WCRC[m]_KCRC[m]_STOP register" "0: Disable interrupt,1: Enable interrupt"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 24. "cmd_done_ie,Interrupt for the complete of command function enable" "0: Disable interrupt,1: Enable interrupt"
rbitfld.long 0x00 21.--23. "Reserved_21,Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 20. "res_done_ie,Interrupt for the complete of result data transfer enable" "0: Disable interrupt,1: Enable interrupt"
rbitfld.long 0x00 14.--19. "Reserved_14,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 13. "comp_err_ie,Interrupt for the error of comparing CRC enable" "0: Disable interrupt,1: Enable interrupt"
bitfld.long 0x00 12. "comp_done_ie,Interrupt for the complete of comparing CRC enable" "0: Disable interrupt,1: Enable interrupt"
newline
hexmask.long.word 0x00 1.--11. 1. "Reserved_1,Reserved"
bitfld.long 0x00 0. "trans_done_ie,Interrupt for the complete of input data transfer enable" "0: Disable interrupt,1: Enable interrupt"
group.long 0xE80++0x03
line.long 0x00 "WCRC2_KCRC2_ECMEN,WCRC[m]_KCRC[m]_ECMEN is a register that sets enable for error notification to ECM module on operation related to KCRC[m] module"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved"
bitfld.long 0x00 13. "comp_err_oe,Error notification for the error of comparing CRC enable" "0: Disable notification,1: Enable notification"
newline
hexmask.long.word 0x00 0.--12. 1. "Reserved_0,Reserved"
group.long 0xEA0++0x03
line.long 0x00 "WCRC2_KCRC2_BUF_STS_RDEN,WCRC[m]_KCRC[m]_BUF_STS_RDEN is a register that sets enable for the interrupt of operation related to KCRC[m] module"
hexmask.long.word 0x00 16.--31. 1. "Code_value,Code value (HA5A5) Set Code value to these bits when writing to this register to enable writing to this register"
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved"
newline
bitfld.long 0x00 0. "BUF_STS_RDEN,WCRC[m]_KCRC[m]_BUF_STS enable" "0: Disable WCRC[m]_KCRC[m]_BUF_STS,1: Enable WCRC[m]_KCRC[m]_BUF_STS"
group.long 0xF00++0x03
line.long 0x00 "WCRC2_COMMON_STS,WCRC[m]_COMMON_STS is a register that indicates the state of operation related to WCRC[m] module"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved"
eventfld.long 0x00 16. "edc_err,Indicates the error of EDC" "0: No EDC error,1: EDC error has occurred"
newline
hexmask.long.word 0x00 0.--15. 1. "Reserved_0,Reserved"
group.long 0xF40++0x03
line.long 0x00 "WCRC2_COMMON_INTEN,WCRC[m]_COMMON_INTEN is a register that sets enable for the interrupt of operation related to WCRC[m] module"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved"
bitfld.long 0x00 16. "edc_err_ie,Interrupt for the error of EDC enable" "0: Disable interrupt,1: Enable interrupt"
newline
hexmask.long.word 0x00 0.--15. 1. "Reserved_0,Reserved"
group.long 0xF80++0x03
line.long 0x00 "WCRC2_COMMON_ECMEN,WCRC[m]_COMMON_ECMEN is a register that sets enable for error notification to ECM module on operation related to WCRC[m] module"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved"
bitfld.long 0x00 16. "edc_err_oe,Error notification for EDC error enable" "0: Disable notification,1: Enable notification"
newline
hexmask.long.word 0x00 0.--15. 1. "Reserved_0,Reserved"
group.long 0xFC0++0x03
line.long 0x00 "WCRC2_ERRINJ,WCRC[m]_ERRINJ is a register that sets enable error injection for bus data signal or EDC code signal"
hexmask.long.word 0x00 16.--31. 1. "code,Code value Set HA5A5 due to enable error injection"
hexmask.long.word 0x00 3.--15. 1. "Reserved_3,Reserved"
newline
bitfld.long 0x00 0.--2. "err_inj_2_0,Error injection enable Bit[0]" "0: Disables error for EDC code signal,1: Enables error for EDC code signal,?..."
tree.end
tree "CRC_INST_3"
base ad:0xE70B0000
group.long 0x00++0x03
line.long 0x00 "WCRC3_CAIPn_EN,WCRC[m]_CAIPn_EN is a register that sets enable the data transfer to/from each port for CAIP_Lite_n interface in FIFO"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
bitfld.long 0x00 16. "out_en,Output data from Data port in FIFO enable" "0: Disable output from Data port,1: Enable output from Data port"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
bitfld.long 0x00 8. "res_en,Output result data from Result port in FIFO enable" "0: Disable output from Result port,1: Enable output from Result port"
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rbitfld.long 0x00 2.--7. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 1. "trans_en,Transferring data from Data port in FIFO to CAIP_Lite_n enable" "0: Disable transferring data to CAIP_Lite_n,1: Enable transferring data to CAIP_Lite_n When"
newline
bitfld.long 0x00 0. "in_en,Input data to Data/Command port in FIFO enable" "0: Disable input to Data/Command port,1: Enable input to Data/Command port"
group.long 0x20++0x03
line.long 0x00 "WCRC3_CAIPn_STOP,WCRC[m]_CAIPn_STOP is a register that stop transfer to CAIP_Lite_n interface"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
bitfld.long 0x00 0. "stop," "0,1"
group.long 0x30++0x03
line.long 0x00 "WCRC3_CAIPn_CMDEN,WCRC[m]_CAIPn_CMDEN is a register that sets enable command function for CAIP_Lite_n module"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
bitfld.long 0x00 0. "cmd_en,Command function enable" "0: Disable command function,1: Enable command function"
group.long 0x80++0x03
line.long 0x00 "WCRC3_CAIPn_WAIT,WCRC[m]_CAIPn_WAIT is a register that wait subsequent command for CAIP_Lite_n interface"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
bitfld.long 0x00 0. "wait," "0,1"
group.long 0x200++0x03
line.long 0x00 "WCRC3_CAIPn_STS,WCRC[m]_CAIPn_STS is a register that indicates the state of operation related to CAIP_Lite_n module"
eventfld.long 0x00 31. "stop_done,Indicates the state of stop operation by WCRC[m]_CAIPn_STOP register" "0: Stop operation in progress or not done,1: Stop operation is done"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
eventfld.long 0x00 24. "cmd_done,Indicates the state of command function" "0: Accessing to register by command in progress or,1: Accessing to register by command is done"
rbitfld.long 0x00 21.--23. "Reserved_21,Reserved" "0,1,2,3,4,5,6,7"
newline
eventfld.long 0x00 20. "res_done,Indicates the state of result data transfer" "0: Transfer in progress or not transferring,1: Transfer is done"
hexmask.long.tbyte 0x00 1.--19. 1. "Reserved_1,Reserved"
newline
eventfld.long 0x00 0. "trans_done,Indicates the state of input data transfer" "0: Transfer in progress or not transferring,1: Transfer is done"
group.long 0x240++0x03
line.long 0x00 "WCRC3_CAIPn_INTEN,WCRC[m]_CAIPn_INTEN is a register that sets enable for the interrupt of operation related to CAIP_Lite_n module"
bitfld.long 0x00 31. "stop_done_ie,Interrupt for the complete of stop operation by WCRC[m]_CAIPn_STOP register" "0: Disable interrupt,1: Enable interrupt"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 24. "cmd_done_ie,Interrupt for the complete of command function enable" "0: Disable interrupt,1: Enable interrupt"
rbitfld.long 0x00 21.--23. "Reserved_21,Reserved" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 20. "res_done_ie,Interrupt for the complete of result data transfer enable" "0: Disable interrupt,1: Enable interrupt"
hexmask.long.tbyte 0x00 1.--19. 1. "Reserved_1,Reserved"
newline
bitfld.long 0x00 0. "trans_done_ie,Interrupt for the complete of input data transfer enable" "0: Disable interrupt,1: Enable interrupt"
group.long 0x2A0++0x03
line.long 0x00 "WCRC3_CAIPn_BUF_STS_RDEN,WCRC[m]_CAIPn_BUF_STS_RDEN is a register that sets enable for the interrupt of operation related to AES-ACC_n module"
hexmask.long.word 0x00 16.--31. 1. "Code_value,Code value (HA5A5) Set Code value to these bits when writing to this register to enable writing to this register"
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved"
newline
bitfld.long 0x00 0. "BUF_STS_RDEN,WCRC[m]_CAIPn_BUF_STS enable" "0: Disable WCRC[m]_CAIPn_BUF_STS,1: Enable WCRC[m]_CAIPn_BUF_STS"
group.long 0x400++0x03
line.long 0x00 "WCRC3_CAIPp_EN,WCRC[m]_CAIPp_EN is a register that sets enable the data transfer to/from each ports for CAIP_Lite_p interface in FIFO"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
bitfld.long 0x00 16. "out_en,Output data from Data port in FIFO enable" "0: Disable output from Data port,1: Enable output from Data port"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
bitfld.long 0x00 8. "res_en,Output result data from Result port in FIFO enable" "0: Disable output from Result port,1: Enable output from Result port"
newline
rbitfld.long 0x00 2.--7. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 1. "trans_en,Transferring data from Data port in FIFO to CAIP_Lite_p enable" "0: Disable transferring data to CAIP_Lite_p,1: Enable transferring data to CAIP_Lite_p When"
newline
bitfld.long 0x00 0. "in_en,Input data to Data/Command port in FIFO enable" "0: Disable input to Data/Command port,1: Enable input to Data/Command port"
group.long 0x420++0x03
line.long 0x00 "WCRC3_CAIPp_STOP,WCRC[m]_CAIPp_STOP is a register that stop transfer to CAIP_Lite_p interface"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
bitfld.long 0x00 0. "stop," "0,1"
group.long 0x430++0x03
line.long 0x00 "WCRC3_CAIPp_CMDEN,WCRC[m]_CAIPp_CMDEN is a register that sets enable command function for CAIP_Lite_p module"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
bitfld.long 0x00 0. "cmd_en,Command function enable" "0: Disable command function,1: Enable command function"
group.long 0x480++0x03
line.long 0x00 "WCRC3_CAIPp_WAIT,WCRC[m]_CAIPp_WAIT is a register that wait subsequent command for CAIP_Lite_p interface"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
bitfld.long 0x00 0. "wait," "0,1"
group.long 0x600++0x03
line.long 0x00 "WCRC3_CAIPp_STS,WCRC[m]_CAIPp_STS is a register that indicates the state of operation related to CAIP_Lite_p module"
eventfld.long 0x00 31. "stop_done,Indicates the state of stop operation by WCRC[m]_CAIPp_STOP register" "0: Stop operation in progress or not done,1: Stop operation is done"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
eventfld.long 0x00 24. "cmd_done,Indicates the state of command function" "0: Accessing to register by command in progress or,1: Accessing to register by command is done"
rbitfld.long 0x00 21.--23. "Reserved_21,Reserved" "0,1,2,3,4,5,6,7"
newline
eventfld.long 0x00 20. "res_done,Indicates the state of result data transfer" "0: Transfer in progress or not transferring,1: Transfer is done"
hexmask.long.tbyte 0x00 1.--19. 1. "Reserved_1,Reserved"
newline
eventfld.long 0x00 0. "trans_done,Indicates the state of input data transfer" "0: Transfer in progress or not transferring,1: Transfer is done"
group.long 0x640++0x03
line.long 0x00 "WCRC3_CAIPp_INTEN,WCRC[m]_CAIPp_INTEN is a register that sets enable for the interrupt of operation related to CAIP_Lite_p module"
bitfld.long 0x00 31. "stop_done_ie,Interrupt for the complete of stop operation by WCRC[m]_CAIPp_STOP register" "0: Disable interrupt,1: Enable interrupt"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 24. "cmd_done_ie,Interrupt for the complete of command function enable" "0: Disable interrupt,1: Enable interrupt"
rbitfld.long 0x00 21.--23. "Reserved_21,Reserved" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 20. "res_done_ie,Interrupt for the complete of result data transfer enable" "0: Disable interrupt,1: Enable interrupt"
hexmask.long.tbyte 0x00 1.--19. 1. "Reserved_1,Reserved"
newline
bitfld.long 0x00 0. "trans_done_ie,Interrupt for the complete of input data transfer enable" "0: Disable interrupt,1: Enable interrupt"
group.long 0x6A0++0x03
line.long 0x00 "WCRC3_CAIPp_BUF_STS_RDEN,WCRC[m]_CAIPp_BUF_STS_RDEN is a register that sets enable for the interrupt of operation related to AES-ACC_p module"
hexmask.long.word 0x00 16.--31. 1. "Code_value,Code value (HA5A5) Set Code value to these bits when writing to this register to enable writing to this register"
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved"
newline
bitfld.long 0x00 0. "BUF_STS_RDEN,WCRC[m]_CAIPp_BUF_STS enable" "0: Disable WCRC[m]_CAIPp_BUF_STS,1: Enable WCRC[m]_CAIPp_BUF_STS"
group.long 0x800++0x03
line.long 0x00 "WCRC3_CRC3_EN,WCRC[m]_CRC[m]_EN is a register that sets enable the data transfer to/from each port for CRC[m] module in FIFO"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
bitfld.long 0x00 16. "out_en,Output data from Data port in FIFO enable" "0: Disable output from Data port,1: Enable output from Data port"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
bitfld.long 0x00 8. "res_en,Output result data from Result port in FIFO enable" "0: Disable output from Result port,1: Enable output from Result port"
newline
rbitfld.long 0x00 2.--7. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 1. "trans_en,Transferring data from Data port in FIFO to CRC[m] enable" "0: Disable transferring data to CRC[m],1: Enable transferring data to CRC[m] When.."
newline
bitfld.long 0x00 0. "in_en,Input data to Data/Command/Expected data port in FIFO enable" "0: Disable input to Data/Command/Expected data..,1: Enable input to Data/Command/Expected data port"
group.long 0x820++0x03
line.long 0x00 "WCRC3_CRC3_STOP,WCRC[m]_CRC[m]_STOP is a register that stop transfer to CRC[m] module"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
bitfld.long 0x00 0. "stop," "0,1"
group.long 0x830++0x03
line.long 0x00 "WCRC3_CRC3_CMDEN,WCRC[m]_CRC[m]_CMDEN is a register that sets enable command function for CRC[m] module"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
bitfld.long 0x00 0. "cmd_en,Command function enable" "0: Disable command function,1: Enable command function"
group.long 0x840++0x03
line.long 0x00 "WCRC3_CRC3_COMP,WCRC[m]_CRC[m]_COMP is a register that sets enable comparing CRC result from CRC[m] module with expected data in FIFO"
hexmask.long.word 0x00 18.--31. 1. "Reserved_18,Reserved"
bitfld.long 0x00 16.--17. "cmp_freq,Set the frequency of comparing" "0,1,2,3"
newline
hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved"
bitfld.long 0x00 1. "exp_reqsel,Select DMA Transfer request source for transferring expected data" "0: dmareq_wcrcm_crcm_in,1: dmareq_wcrcm_crcm_res m"
newline
bitfld.long 0x00 0. "cmp_en,Comparing CRC result with expected data enable" "0: Disable comparing function,1: Enable comparing function"
group.long 0x850++0x03
line.long 0x00 "WCRC3_CRC3_COMP_RES,WCRC[m]_CRC[m]_COMP_RES is a register that indicates the result of comparing CRC for CRC[m] module"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved"
abitfld.long 0x00 0.--15. "cmp_res,The result of comparing CRC These bits indicate mismatched point of comparing data in 4-byte units" "0x0000=0: No error,0x0001=1: Mismatch Figure 135.4"
group.long 0x870++0x03
line.long 0x00 "WCRC3_CRC3_CONV,WCRC[m]_CRC[m]_CONV is a register that sets CRC conversion size to once for CRC[m] module"
hexmask.long.word 0x00 21.--31. 1. "Reserved_21,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--20. 1. "conv,CRC conversion size specification Specifies the CRC conversion size in 1-byte units"
group.long 0x880++0x03
line.long 0x00 "WCRC3_CRC3_WAIT,WCRC[m]_CRC[m]_WAIT is a register that wait subsequent command for CRC[m] module"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
bitfld.long 0x00 0. "wait," "0,1"
group.long 0x910++0x03
line.long 0x00 "WCRC3_CRC3_INIT_CRC,WCRC[m]_CRC[m]_INIT_CRC is a register that sets CRC code value to DCRAmCOUT register at auto clear"
hexmask.long 0x00 0.--31. 1. "init_code,CRC code value to DCRAmCOUT register at auto clear"
group.long 0xA00++0x03
line.long 0x00 "WCRC3_CRC3_STS,WCRC[m]_CRC[m]_STS is a register that indicates the state of operation related to CRC[m] module"
eventfld.long 0x00 31. "stop_done,Indicates the state of stop operation by WCRC[m]_CRC[m]_STOP register" "0: Stop operation in progress or not done,1: Stop operation is done"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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eventfld.long 0x00 24. "cmd_done,Indicates the state of command function" "0: Accessing to register by command in progress or,1: Accessing to register by command is done"
rbitfld.long 0x00 21.--23. "Reserved_21,Reserved" "0,1,2,3,4,5,6,7"
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eventfld.long 0x00 20. "res_done,Indicates the state of result data transfer" "0: Transfer in progress or not transferring,1: Transfer is done"
rbitfld.long 0x00 14.--19. "Reserved_14,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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eventfld.long 0x00 13. "comp_err,Indicates the error of comparing CRC" "0: No comparing error or not comparing,1: Mismatch has occurred"
eventfld.long 0x00 12. "comp_done,Indicates the state of comparing CRC" "0: Comparison in progress or not comparing,1: Comparing is done"
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hexmask.long.word 0x00 1.--11. 1. "Reserved_1,Reserved"
eventfld.long 0x00 0. "trans_done,Indicates the state of input data transfer" "0: Transfer in progress or not transferring,1: Transfer is done"
group.long 0xA40++0x03
line.long 0x00 "WCRC3_CRC3_INTEN,WCRC[m]_CRC[m]_INTEN is a register that sets enable for the interrupt of operation related to CRC[m] module"
bitfld.long 0x00 31. "stop_done_ie,Interrupt for the complete of stop operation by WCRC[m]_CRC[m]_STOP register" "0: Disable interrupt,1: Enable interrupt"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 24. "cmd_done_ie,Interrupt for the complete of command function enable" "0: Disable interrupt,1: Enable interrupt"
rbitfld.long 0x00 21.--23. "Reserved_21,Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 20. "res_done_ie,Interrupt for the complete of result data transfer enable" "0: Disable interrupt,1: Enable interrupt"
rbitfld.long 0x00 14.--19. "Reserved_14,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 13. "comp_err_ie,Interrupt for the error of comparing CRC enable" "0: Disable interrupt,1: Enable interrupt"
bitfld.long 0x00 12. "comp_done_ie,Interrupt for the complete of comparing CRC enable" "0: Disable interrupt,1: Enable interrupt"
newline
hexmask.long.word 0x00 1.--11. 1. "Reserved_1,Reserved"
bitfld.long 0x00 0. "trans_done_ie,Interrupt for the complete of input data transfer enable" "0: Disable interrupt,1: Enable interrupt"
group.long 0xA80++0x03
line.long 0x00 "WCRC3_CRC3_ECMEN,WCRC[m]_CRC[m]_ECMEN is a register that sets enable for error notification to ECM module on operation related to CRC[m] module"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved"
bitfld.long 0x00 13. "comp_err_oe,Error notification for the error of comparing CRC enable" "0: Disable notification,1: Enable notification"
newline
hexmask.long.word 0x00 0.--12. 1. "Reserved_0,Reserved"
group.long 0xAA0++0x03
line.long 0x00 "WCRC3_CRC3_BUF_STS_RDEN,WCRC[m]_CRC[m]_BUF_STS_RDEN is a register that sets enable for the interrupt of operation related to CRC[m] module"
hexmask.long.word 0x00 16.--31. 1. "Code_value,Code value (HA5A5) Set Code value to these bits when writing to this register to enable writing to this register"
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved"
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bitfld.long 0x00 0. "BUF_STS_RDEN,WCRC[m]_CRC[m]_BUF_STS enable" "0: Disable WCRC[m]_CRC[m]_BUF_STS,1: Enable WCRC[m]_CRC[m]_BUF_STS"
group.long 0xC00++0x03
line.long 0x00 "WCRC3_KCRC3_EN,WCRC[m]_KCRC[m]_EN is a register that sets enable the data transfer to/from each port for KCRC[m] module in FIFO"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved These bits are always read as 0"
bitfld.long 0x00 16. "out_en,Output data from Data port in FIFO enable" "0: Disable output from Data port,1: Enable output from Data port"
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hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
bitfld.long 0x00 8. "res_en,Output result data from Result port in FIFO enable" "0: Disable output from Result port,1: Enable output from Result port"
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rbitfld.long 0x00 2.--7. "Reserved_2,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 1. "trans_en,Transferring data from Data port in FIFO to KCRC[m] enable" "0: Disable transferring data to KCRC[m],1: Enable transferring data to KCRC[m] When"
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bitfld.long 0x00 0. "in_en,Input data to Data/Command/Expected data port in FIFO enable" "0: Disable input to Data/Command/Expected data..,1: Enable input to Data/Command/Expected data port"
group.long 0xC20++0x03
line.long 0x00 "WCRC3_KCRC3_STOP,WCRC[m]_KCRC[m]_STOP is a register that stop transfer to KCRC[m] module"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
bitfld.long 0x00 0. "stop," "0,1"
group.long 0xC30++0x03
line.long 0x00 "WCRC3_KCRC3_CMDEN,WCRC[m]_KCRC[m]_CMDEN is a register that sets enable command function for KCRC[m] module"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
bitfld.long 0x00 0. "cmd_en,Command function enable" "0: Disable command function,1: Enable command function"
group.long 0xC40++0x03
line.long 0x00 "WCRC3_KCRC3_COMP,WCRC[m]_KCRC[m]_COMP is a register that sets enable comparing CRC result from KCRC[m] module with expected data in FIFO"
hexmask.long.word 0x00 18.--31. 1. "Reserved_18,Reserved"
bitfld.long 0x00 16.--17. "cmp_freq,Set the frequency of comparing" "0,1,2,3"
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hexmask.long.word 0x00 2.--15. 1. "Reserved_2,Reserved"
bitfld.long 0x00 1. "exp_reqsel,Select DMA Transfer request source for transferring expected data" "0: dmareq_wcrcm_kcrcn_in,1: dmareq_wcrcm_kcrcn_res m"
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bitfld.long 0x00 0. "cmp_en,Comparing CRC result with expected data enable" "0: Disable comparing function,1: Enable comparing function"
group.long 0xC50++0x03
line.long 0x00 "WCRC3_KCRC3_COMP_RES,WCRC[m]_KCRC[m]_COMP_RES is a register that indicates the result of comparing CRC for KCRC[m] module"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved"
abitfld.long 0x00 0.--15. "cmp_res,The result of comparing CRC These bits indicate mismatched point of comparing data in 4-byte units" "0x0000=0: No error,0x0001=1: Mismatch Figure 135.4"
group.long 0xC70++0x03
line.long 0x00 "WCRC3_KCRC3_CONV,WCRC[m]_KCRC[m]_CONV is a register that sets CRC conversion size to once for KCRC[m] module"
hexmask.long.word 0x00 21.--31. 1. "Reserved_21,Reserved These bits are always read as 0"
hexmask.long.tbyte 0x00 0.--20. 1. "conv,CRC conversion size specification Specifies the CRC conversion size in 1-byte units"
group.long 0xC80++0x03
line.long 0x00 "WCRC3_KCRC3_WAIT,WCRC[m]_KCRC[m]_WAIT is a register that wait subsequent command for KCRC[m] module"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
bitfld.long 0x00 0. "wait," "0,1"
group.long 0xD10++0x03
line.long 0x00 "WCRC3_KCRC3_INIT_CRC,WCRC[m]_KCRC[m]_INIT_CRC is a register that sets CRC code value to KCRC[m]COUT register at auto clear"
hexmask.long 0x00 0.--31. 1. "init_code,CRC code value to KCRC[m]DOUT register at auto clear"
group.long 0xE00++0x03
line.long 0x00 "WCRC3_KCRC3_STS,WCRC[m]_KCRC[m]_STS is a register that indicates the state of operation related to KCRC[m] module"
eventfld.long 0x00 31. "stop_done,Indicates the state of stop operation by WCRC[m]_KCRC[m]_STOP register" "0: Stop operation in progress or not done,1: Stop operation is done"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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eventfld.long 0x00 24. "cmd_done,Indicates the state of command function" "0: Accessing to register by command in progress or,1: Accessing to register by command is done"
rbitfld.long 0x00 21.--23. "Reserved_21,Reserved" "0,1,2,3,4,5,6,7"
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eventfld.long 0x00 20. "res_done,Indicates the state of result data transfer" "0: Transfer in progress or not transferring,1: Transfer is done"
rbitfld.long 0x00 14.--19. "Reserved_14,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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eventfld.long 0x00 13. "comp_err,Indicates the error of comparing CRC" "0: No comparing error or not comparing,1: Mismatch has occurred"
eventfld.long 0x00 12. "comp_done,Indicates the state of comparing CRC" "0: Comparison in progress or not comparing,1: Comparing is done"
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hexmask.long.word 0x00 1.--11. 1. "Reserved_1,Reserved"
eventfld.long 0x00 0. "trans_done,Indicates the state of input data transfer" "0: Transfer in progress or not transferring,1: Transfer is done"
group.long 0xE40++0x03
line.long 0x00 "WCRC3_KCRC3_INTEN,WCRC[m]_KCRC[m]_INTEN is a register that sets enable for the interrupt of operation related to KCRC[m] module"
bitfld.long 0x00 31. "stop_done_ie,Interrupt for the complete of stop operation by WCRC[m]_KCRC[m]_STOP register" "0: Disable interrupt,1: Enable interrupt"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 24. "cmd_done_ie,Interrupt for the complete of command function enable" "0: Disable interrupt,1: Enable interrupt"
rbitfld.long 0x00 21.--23. "Reserved_21,Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 20. "res_done_ie,Interrupt for the complete of result data transfer enable" "0: Disable interrupt,1: Enable interrupt"
rbitfld.long 0x00 14.--19. "Reserved_14,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 13. "comp_err_ie,Interrupt for the error of comparing CRC enable" "0: Disable interrupt,1: Enable interrupt"
bitfld.long 0x00 12. "comp_done_ie,Interrupt for the complete of comparing CRC enable" "0: Disable interrupt,1: Enable interrupt"
newline
hexmask.long.word 0x00 1.--11. 1. "Reserved_1,Reserved"
bitfld.long 0x00 0. "trans_done_ie,Interrupt for the complete of input data transfer enable" "0: Disable interrupt,1: Enable interrupt"
group.long 0xE80++0x03
line.long 0x00 "WCRC3_KCRC3_ECMEN,WCRC[m]_KCRC[m]_ECMEN is a register that sets enable for error notification to ECM module on operation related to KCRC[m] module"
hexmask.long.tbyte 0x00 14.--31. 1. "Reserved_14,Reserved"
bitfld.long 0x00 13. "comp_err_oe,Error notification for the error of comparing CRC enable" "0: Disable notification,1: Enable notification"
newline
hexmask.long.word 0x00 0.--12. 1. "Reserved_0,Reserved"
group.long 0xEA0++0x03
line.long 0x00 "WCRC3_KCRC3_BUF_STS_RDEN,WCRC[m]_KCRC[m]_BUF_STS_RDEN is a register that sets enable for the interrupt of operation related to KCRC[m] module"
hexmask.long.word 0x00 16.--31. 1. "Code_value,Code value (HA5A5) Set Code value to these bits when writing to this register to enable writing to this register"
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved"
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bitfld.long 0x00 0. "BUF_STS_RDEN,WCRC[m]_KCRC[m]_BUF_STS enable" "0: Disable WCRC[m]_KCRC[m]_BUF_STS,1: Enable WCRC[m]_KCRC[m]_BUF_STS"
group.long 0xF00++0x03
line.long 0x00 "WCRC3_COMMON_STS,WCRC[m]_COMMON_STS is a register that indicates the state of operation related to WCRC[m] module"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved"
eventfld.long 0x00 16. "edc_err,Indicates the error of EDC" "0: No EDC error,1: EDC error has occurred"
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hexmask.long.word 0x00 0.--15. 1. "Reserved_0,Reserved"
group.long 0xF40++0x03
line.long 0x00 "WCRC3_COMMON_INTEN,WCRC[m]_COMMON_INTEN is a register that sets enable for the interrupt of operation related to WCRC[m] module"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved"
bitfld.long 0x00 16. "edc_err_ie,Interrupt for the error of EDC enable" "0: Disable interrupt,1: Enable interrupt"
newline
hexmask.long.word 0x00 0.--15. 1. "Reserved_0,Reserved"
group.long 0xF80++0x03
line.long 0x00 "WCRC3_COMMON_ECMEN,WCRC[m]_COMMON_ECMEN is a register that sets enable for error notification to ECM module on operation related to WCRC[m] module"
hexmask.long.word 0x00 17.--31. 1. "Reserved_17,Reserved"
bitfld.long 0x00 16. "edc_err_oe,Error notification for EDC error enable" "0: Disable notification,1: Enable notification"
newline
hexmask.long.word 0x00 0.--15. 1. "Reserved_0,Reserved"
group.long 0xFC0++0x03
line.long 0x00 "WCRC3_ERRINJ,WCRC[m]_ERRINJ is a register that sets enable error injection for bus data signal or EDC code signal"
hexmask.long.word 0x00 16.--31. 1. "code,Code value Set HA5A5 due to enable error injection"
hexmask.long.word 0x00 3.--15. 1. "Reserved_3,Reserved"
newline
bitfld.long 0x00 0.--2. "err_inj_2_0,Error injection enable Bit[0]" "0: Disables error for EDC code signal,1: Enables error for EDC code signal,?..."
tree.end
tree "CRC_INST_4"
base ad:0xE6F00000
group.long 0x00++0x03
line.long 0x00 "DCRA0CIN,DCRA[m]CIN is a register that sets input data"
hexmask.long 0x00 0.--31. 1. "Data_In,Set input data The valid bit position depends on the ISZ bit setting"
group.long 0x04++0x03
line.long 0x00 "DCRA0COUT,DCRA[m]COUT is a register that obtains the CRC codes"
hexmask.long 0x00 0.--31. 1. "CRC_Code,CRC code The valid bit width depends on the DCRAmCTL.POL bit setting"
group.long 0x20++0x03
line.long 0x00 "DCRA0CTL,DCRAmCTL is a register that determines the valid bit width of the input data and generator polynomial for the CRC codes"
hexmask.long 0x00 6.--31. 1. "Reserved_6,Reserved These bits are always read as 0"
bitfld.long 0x00 4.--5. "ISZ_1_0,The value written to this field determines the valid bit width of input data" "0: 32bit (DCRAmCIN31-0),1: 16bit (DCRAmCIN15-0),2: 8bit (DCRAmCIN7-0),3: Setting prohibited (8bit (DCRAmCIN7-0): Do not"
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bitfld.long 0x00 0.--3. "POL_3_0,The value written to this field determines the generator polynomial for the CRC codes" "0: 32 bit Ethernet (CRC-32-IEEE 802.3),1: 16-bit CCITT-FALSE CRC16,2: 8 bit SAE J1850,3: 8 bit 0x2F polynomial,4: 32 bit 0xF4ACFB13 polynomial,5: 32 bit 0x1EDC6F41 polynomial (CRC-32C),6: 21 bit 0x102899 polynomial (CRC-21),7: 17 bit 0x1685B polynomial (CRC-17),8: 15 bit 0x4599 polynomial (CRC-15),9: Reserved 4'b101x,?..."
group.long 0x40++0x03
line.long 0x00 "DCRA0CTL2,DCRA[m]CTL2 is a register that determines the swap exor of input data and output data"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "xorvalmode,The value written to this field determines EXOR ON of output data" "0: data out[31:0],1: HFFFF FFFF ^ data_out[31:0]"
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bitfld.long 0x00 6. "bitswapmode,The value written to this field determines bit swap of output data" "0,1"
bitfld.long 0x00 4.--5. "byteswapmode,The value written to this field determines byte swap of output data" "0,1,2,3"
newline
bitfld.long 0x00 3. "xorvalinmode,The value written to this field determines EXOR ON of input data" "0: data_in[31:0],1: HFFFF FFFF ^ data_in[31:0]"
bitfld.long 0x00 2. "bitswapinmode,The value written to this field determines bit swap of input data" "0,1"
newline
bitfld.long 0x00 0.--1. "byteswapinmode,The value written to this field determines byte swap of input data" "0,1,2,3"
tree.end
tree "CRC_INST_5"
base ad:0xE6F10000
group.long 0x00++0x03
line.long 0x00 "DCRA1CIN,DCRA[m]CIN is a register that sets input data"
hexmask.long 0x00 0.--31. 1. "Data_In,Set input data The valid bit position depends on the ISZ bit setting"
group.long 0x04++0x03
line.long 0x00 "DCRA1COUT,DCRA[m]COUT is a register that obtains the CRC codes"
hexmask.long 0x00 0.--31. 1. "CRC_Code,CRC code The valid bit width depends on the DCRAmCTL.POL bit setting"
group.long 0x20++0x03
line.long 0x00 "DCRA1CTL,DCRAmCTL is a register that determines the valid bit width of the input data and generator polynomial for the CRC codes"
hexmask.long 0x00 6.--31. 1. "Reserved_6,Reserved These bits are always read as 0"
bitfld.long 0x00 4.--5. "ISZ_1_0,The value written to this field determines the valid bit width of input data" "0: 32bit (DCRAmCIN31-0),1: 16bit (DCRAmCIN15-0),2: 8bit (DCRAmCIN7-0),3: Setting prohibited (8bit (DCRAmCIN7-0): Do not"
newline
bitfld.long 0x00 0.--3. "POL_3_0,The value written to this field determines the generator polynomial for the CRC codes" "0: 32 bit Ethernet (CRC-32-IEEE 802.3),1: 16-bit CCITT-FALSE CRC16,2: 8 bit SAE J1850,3: 8 bit 0x2F polynomial,4: 32 bit 0xF4ACFB13 polynomial,5: 32 bit 0x1EDC6F41 polynomial (CRC-32C),6: 21 bit 0x102899 polynomial (CRC-21),7: 17 bit 0x1685B polynomial (CRC-17),8: 15 bit 0x4599 polynomial (CRC-15),9: Reserved 4'b101x,?..."
group.long 0x40++0x03
line.long 0x00 "DCRA1CTL2,DCRA[m]CTL2 is a register that determines the swap exor of input data and output data"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "xorvalmode,The value written to this field determines EXOR ON of output data" "0: data out[31:0],1: HFFFF FFFF ^ data_out[31:0]"
newline
bitfld.long 0x00 6. "bitswapmode,The value written to this field determines bit swap of output data" "0,1"
bitfld.long 0x00 4.--5. "byteswapmode,The value written to this field determines byte swap of output data" "0,1,2,3"
newline
bitfld.long 0x00 3. "xorvalinmode,The value written to this field determines EXOR ON of input data" "0: data_in[31:0],1: HFFFF FFFF ^ data_in[31:0]"
bitfld.long 0x00 2. "bitswapinmode,The value written to this field determines bit swap of input data" "0,1"
newline
bitfld.long 0x00 0.--1. "byteswapinmode,The value written to this field determines byte swap of input data" "0,1,2,3"
tree.end
tree "CRC_INST_6"
base ad:0xE7000000
group.long 0x00++0x03
line.long 0x00 "DCRA2CIN,DCRA[m]CIN is a register that sets input data"
hexmask.long 0x00 0.--31. 1. "Data_In,Set input data The valid bit position depends on the ISZ bit setting"
group.long 0x04++0x03
line.long 0x00 "DCRA2COUT,DCRA[m]COUT is a register that obtains the CRC codes"
hexmask.long 0x00 0.--31. 1. "CRC_Code,CRC code The valid bit width depends on the DCRAmCTL.POL bit setting"
group.long 0x20++0x03
line.long 0x00 "DCRA2CTL,DCRAmCTL is a register that determines the valid bit width of the input data and generator polynomial for the CRC codes"
hexmask.long 0x00 6.--31. 1. "Reserved_6,Reserved These bits are always read as 0"
bitfld.long 0x00 4.--5. "ISZ_1_0,The value written to this field determines the valid bit width of input data" "0: 32bit (DCRAmCIN31-0),1: 16bit (DCRAmCIN15-0),2: 8bit (DCRAmCIN7-0),3: Setting prohibited (8bit (DCRAmCIN7-0): Do not"
newline
bitfld.long 0x00 0.--3. "POL_3_0,The value written to this field determines the generator polynomial for the CRC codes" "0: 32 bit Ethernet (CRC-32-IEEE 802.3),1: 16-bit CCITT-FALSE CRC16,2: 8 bit SAE J1850,3: 8 bit 0x2F polynomial,4: 32 bit 0xF4ACFB13 polynomial,5: 32 bit 0x1EDC6F41 polynomial (CRC-32C),6: 21 bit 0x102899 polynomial (CRC-21),7: 17 bit 0x1685B polynomial (CRC-17),8: 15 bit 0x4599 polynomial (CRC-15),9: Reserved 4'b101x,?..."
group.long 0x40++0x03
line.long 0x00 "DCRA2CTL2,DCRA[m]CTL2 is a register that determines the swap exor of input data and output data"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "xorvalmode,The value written to this field determines EXOR ON of output data" "0: data out[31:0],1: HFFFF FFFF ^ data_out[31:0]"
newline
bitfld.long 0x00 6. "bitswapmode,The value written to this field determines bit swap of output data" "0,1"
bitfld.long 0x00 4.--5. "byteswapmode,The value written to this field determines byte swap of output data" "0,1,2,3"
newline
bitfld.long 0x00 3. "xorvalinmode,The value written to this field determines EXOR ON of input data" "0: data_in[31:0],1: HFFFF FFFF ^ data_in[31:0]"
bitfld.long 0x00 2. "bitswapinmode,The value written to this field determines bit swap of input data" "0,1"
newline
bitfld.long 0x00 0.--1. "byteswapinmode,The value written to this field determines byte swap of input data" "0,1,2,3"
tree.end
tree "CRC_INST_7"
base ad:0xE7010000
group.long 0x00++0x03
line.long 0x00 "DCRA3CIN,DCRA[m]CIN is a register that sets input data"
hexmask.long 0x00 0.--31. 1. "Data_In,Set input data The valid bit position depends on the ISZ bit setting"
group.long 0x04++0x03
line.long 0x00 "DCRA3COUT,DCRA[m]COUT is a register that obtains the CRC codes"
hexmask.long 0x00 0.--31. 1. "CRC_Code,CRC code The valid bit width depends on the DCRAmCTL.POL bit setting"
group.long 0x20++0x03
line.long 0x00 "DCRA3CTL,DCRAmCTL is a register that determines the valid bit width of the input data and generator polynomial for the CRC codes"
hexmask.long 0x00 6.--31. 1. "Reserved_6,Reserved These bits are always read as 0"
bitfld.long 0x00 4.--5. "ISZ_1_0,The value written to this field determines the valid bit width of input data" "0: 32bit (DCRAmCIN31-0),1: 16bit (DCRAmCIN15-0),2: 8bit (DCRAmCIN7-0),3: Setting prohibited (8bit (DCRAmCIN7-0): Do not"
newline
bitfld.long 0x00 0.--3. "POL_3_0,The value written to this field determines the generator polynomial for the CRC codes" "0: 32 bit Ethernet (CRC-32-IEEE 802.3),1: 16-bit CCITT-FALSE CRC16,2: 8 bit SAE J1850,3: 8 bit 0x2F polynomial,4: 32 bit 0xF4ACFB13 polynomial,5: 32 bit 0x1EDC6F41 polynomial (CRC-32C),6: 21 bit 0x102899 polynomial (CRC-21),7: 17 bit 0x1685B polynomial (CRC-17),8: 15 bit 0x4599 polynomial (CRC-15),9: Reserved 4'b101x,?..."
group.long 0x40++0x03
line.long 0x00 "DCRA3CTL2,DCRA[m]CTL2 is a register that determines the swap exor of input data and output data"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
bitfld.long 0x00 7. "xorvalmode,The value written to this field determines EXOR ON of output data" "0: data out[31:0],1: HFFFF FFFF ^ data_out[31:0]"
newline
bitfld.long 0x00 6. "bitswapmode,The value written to this field determines bit swap of output data" "0,1"
bitfld.long 0x00 4.--5. "byteswapmode,The value written to this field determines byte swap of output data" "0,1,2,3"
newline
bitfld.long 0x00 3. "xorvalinmode,The value written to this field determines EXOR ON of input data" "0: data_in[31:0],1: HFFFF FFFF ^ data_in[31:0]"
bitfld.long 0x00 2. "bitswapinmode,The value written to this field determines bit swap of input data" "0,1"
newline
bitfld.long 0x00 0.--1. "byteswapinmode,The value written to this field determines byte swap of input data" "0,1,2,3"
tree.end
tree "CRC_INST_8"
base ad:0xE7020000
group.long 0x00++0x03
line.long 0x00 "KCRC0DIN,"
hexmask.long 0x00 0.--31. 1. "DIN,Input Data for CRC calculation"
group.long 0x80++0x03
line.long 0x00 "KCRC0DOUT,"
hexmask.long 0x00 0.--31. 1. "DOUT,Output Data for CRC calculation"
group.long 0x90++0x03
line.long 0x00 "KCRC0CTL,This register provided CRC calculate setting"
hexmask.long.word 0x00 21.--31. 1. "Reserved_21,Reserved These bits are always read as 0"
bitfld.long 0x00 16.--20. "PSIZE,Polynomial size H7: 8 bit HF: 16 bit H1F: 32bit Other: setting prohibit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "CMD0,Calculate Mode 0" "0: Mode N (normal),1: Mode R (output reflect)"
rbitfld.long 0x00 6.--7. "Reserved_6,Reserved These bits are always read as 0" "0,1,2,3"
bitfld.long 0x00 5. "CMD1,Calculate Mode 1" "0: Mode N (normal),1: Mode R (input reflect)"
newline
bitfld.long 0x00 4. "CMD2,Calculate Mode 2" "0: Mode M (MSB shift),1: Mode L (LSB shift)"
rbitfld.long 0x00 3. "Reserved_3,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 0.--2. "DW,Input Data size select These bits define valid data width of Data input" "0: 32 bit fix mode,1: 16 bit fix mode,?,3: 8 bit fix mode Other,?..."
group.long 0xA0++0x03
line.long 0x00 "KCRC0POLY,"
hexmask.long 0x00 0.--31. 1. "POLY,Polynomial for CRC calculation"
group.long 0xB0++0x03
line.long 0x00 "KCRC0XOR,"
hexmask.long 0x00 0.--31. 1. "XOR,XOR mask for Data output"
tree.end
tree "CRC_INST_9"
base ad:0xE7030000
group.long 0x00++0x03
line.long 0x00 "KCRC1DIN,"
hexmask.long 0x00 0.--31. 1. "DIN,Input Data for CRC calculation"
group.long 0x80++0x03
line.long 0x00 "KCRC1DOUT,"
hexmask.long 0x00 0.--31. 1. "DOUT,Output Data for CRC calculation"
group.long 0x90++0x03
line.long 0x00 "KCRC1CTL,This register provided CRC calculate setting"
hexmask.long.word 0x00 21.--31. 1. "Reserved_21,Reserved These bits are always read as 0"
bitfld.long 0x00 16.--20. "PSIZE,Polynomial size H7: 8 bit HF: 16 bit H1F: 32bit Other: setting prohibit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "CMD0,Calculate Mode 0" "0: Mode N (normal),1: Mode R (output reflect)"
rbitfld.long 0x00 6.--7. "Reserved_6,Reserved These bits are always read as 0" "0,1,2,3"
bitfld.long 0x00 5. "CMD1,Calculate Mode 1" "0: Mode N (normal),1: Mode R (input reflect)"
newline
bitfld.long 0x00 4. "CMD2,Calculate Mode 2" "0: Mode M (MSB shift),1: Mode L (LSB shift)"
rbitfld.long 0x00 3. "Reserved_3,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 0.--2. "DW,Input Data size select These bits define valid data width of Data input" "0: 32 bit fix mode,1: 16 bit fix mode,?,3: 8 bit fix mode Other,?..."
group.long 0xA0++0x03
line.long 0x00 "KCRC1POLY,"
hexmask.long 0x00 0.--31. 1. "POLY,Polynomial for CRC calculation"
group.long 0xB0++0x03
line.long 0x00 "KCRC1XOR,"
hexmask.long 0x00 0.--31. 1. "XOR,XOR mask for Data output"
tree.end
tree "CRC_INST_10"
base ad:0xE7040000
group.long 0x00++0x03
line.long 0x00 "KCRC2DIN,"
hexmask.long 0x00 0.--31. 1. "DIN,Input Data for CRC calculation"
group.long 0x80++0x03
line.long 0x00 "KCRC2DOUT,"
hexmask.long 0x00 0.--31. 1. "DOUT,Output Data for CRC calculation"
group.long 0x90++0x03
line.long 0x00 "KCRC2CTL,This register provided CRC calculate setting"
hexmask.long.word 0x00 21.--31. 1. "Reserved_21,Reserved These bits are always read as 0"
bitfld.long 0x00 16.--20. "PSIZE,Polynomial size H7: 8 bit HF: 16 bit H1F: 32bit Other: setting prohibit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "CMD0,Calculate Mode 0" "0: Mode N (normal),1: Mode R (output reflect)"
rbitfld.long 0x00 6.--7. "Reserved_6,Reserved These bits are always read as 0" "0,1,2,3"
bitfld.long 0x00 5. "CMD1,Calculate Mode 1" "0: Mode N (normal),1: Mode R (input reflect)"
newline
bitfld.long 0x00 4. "CMD2,Calculate Mode 2" "0: Mode M (MSB shift),1: Mode L (LSB shift)"
rbitfld.long 0x00 3. "Reserved_3,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 0.--2. "DW,Input Data size select These bits define valid data width of Data input" "0: 32 bit fix mode,1: 16 bit fix mode,?,3: 8 bit fix mode Other,?..."
group.long 0xA0++0x03
line.long 0x00 "KCRC2POLY,"
hexmask.long 0x00 0.--31. 1. "POLY,Polynomial for CRC calculation"
group.long 0xB0++0x03
line.long 0x00 "KCRC2XOR,"
hexmask.long 0x00 0.--31. 1. "XOR,XOR mask for Data output"
tree.end
tree "CRC_INST_11"
base ad:0xE7050000
group.long 0x00++0x03
line.long 0x00 "KCRC3DIN,"
hexmask.long 0x00 0.--31. 1. "DIN,Input Data for CRC calculation"
group.long 0x80++0x03
line.long 0x00 "KCRC3DOUT,"
hexmask.long 0x00 0.--31. 1. "DOUT,Output Data for CRC calculation"
group.long 0x90++0x03
line.long 0x00 "KCRC3CTL,This register provided CRC calculate setting"
hexmask.long.word 0x00 21.--31. 1. "Reserved_21,Reserved These bits are always read as 0"
bitfld.long 0x00 16.--20. "PSIZE,Polynomial size H7: 8 bit HF: 16 bit H1F: 32bit Other: setting prohibit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved These bits are always read as 0"
newline
bitfld.long 0x00 8. "CMD0,Calculate Mode 0" "0: Mode N (normal),1: Mode R (output reflect)"
rbitfld.long 0x00 6.--7. "Reserved_6,Reserved These bits are always read as 0" "0,1,2,3"
bitfld.long 0x00 5. "CMD1,Calculate Mode 1" "0: Mode N (normal),1: Mode R (input reflect)"
newline
bitfld.long 0x00 4. "CMD2,Calculate Mode 2" "0: Mode M (MSB shift),1: Mode L (LSB shift)"
rbitfld.long 0x00 3. "Reserved_3,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 0.--2. "DW,Input Data size select These bits define valid data width of Data input" "0: 32 bit fix mode,1: 16 bit fix mode,?,3: 8 bit fix mode Other,?..."
group.long 0xA0++0x03
line.long 0x00 "KCRC3POLY,"
hexmask.long 0x00 0.--31. 1. "POLY,Polynomial for CRC calculation"
group.long 0xB0++0x03
line.long 0x00 "KCRC3XOR,"
hexmask.long 0x00 0.--31. 1. "XOR,XOR mask for Data output"
tree.end
tree.end
tree "RFSO"
tree "RFSO_INST_0"
base ad:0xFFE80000
group.long 0x00++0x03
line.long 0x00 "CNT0_CYC0,CNT0_CYC[m] sets the periodical cycle value to the interval timer"
hexmask.long 0x00 0.--31. 1. "CNT0_CYC,Specify the periodical cycle value to the interval timer"
group.long 0x04++0x03
line.long 0x00 "CNT1_CYC0,CNT1_CYC[m] sets the periodical cycle value to the time-out detection timer"
hexmask.long 0x00 0.--31. 1. "CNT1_CYC,Specify the periodical cycle value to the time-out detection timer"
group.long 0x08++0x03
line.long 0x00 "FSO_CTL0,FSO_CTL[m] is a control register of this module"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Register write enable code"
rbitfld.long 0x00 10.--15. "Reserved_10,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 9. "Reserved_9,Reserved" "0,1"
newline
bitfld.long 0x00 8. "ITE,Enables or disables an interval timer (CNT0) interrupt request" "0: Disables the interrupt,1: Enables the interrupt"
rbitfld.long 0x00 7. "TOCUNF,Indicates whether a time-out detection timer (CNT1) has stopped when the value of a time-out detection timer (CNT1) is below the lower limit (CNT1_UNS[m])" "0: A time-out detection timer (CNT1) has stopped,1: A time-out detection timer (CNT1) has stopped"
rbitfld.long 0x00 6. "TOI,Indicates whether a time-out detection timer (CNT1) has stopped under the condition that the value of a time-out detection timer (CNT1) is equal to the upper limit (CNT1_CYC[m]) or whether a time-out detection timer (CNT1) has stopped under the.." "0: There is no interrupt,1: There is an interrupt"
newline
rbitfld.long 0x00 5. "ITI,Indicates whether there is an interval timer (CNT0) interrupt request" "0: There is no interrupt,1: There is an interrupt"
rbitfld.long 0x00 4. "TOES,Indicates that time-out error status is appropriately output to the ECM module" "0,1"
rbitfld.long 0x00 3. "CFES_1,Indicates that the CFEO_1 bit status is appropriately output to the ECM module" "0,1"
newline
bitfld.long 0x00 2. "CFEO_1,Sets the expected value verification result during test routine when the CFEO_0 bit is 1" "0,1"
bitfld.long 0x00 1. "CFEO_0,Sets the expected value verification result during test routine" "0,1"
rbitfld.long 0x00 0. "CFES_0,Indicates that the CFEO_0 bit status is appropriately output to the ECM module" "0,1"
group.long 0x0C++0x03
line.long 0x00 "CNT_DIV0,CNT_DIV[m] sets the interval timer/time-out detection timer counter clock frequency divisor"
hexmask.long 0x00 0.--31. 1. "CNT_DIV,Set the timer counter clock frequency divisor"
group.long 0x10++0x03
line.long 0x00 "FSO_CMD0,FSO_CMD[m] activates this module and clears the interrupts"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Register write enable code"
hexmask.long.word 0x00 4.--15. 1. "Reserved_4,Reserved"
bitfld.long 0x00 3. "TOC,Clears a time-out detection timer (CNT1) interrupt" "0,1"
newline
bitfld.long 0x00 2. "ITC,Clears an interval timer (CNT0) interrupt" "0,1"
bitfld.long 0x00 1. "CNTS1,Activates or stops the time-out detection timer (CNT1)" "0,1"
bitfld.long 0x00 0. "CNTS0,Activates or stops the interval timer (CNT0)" "0,1"
group.long 0x14++0x03
line.long 0x00 "CNT0_STS0,CNT0_STS[m] indicates the interval timer value"
hexmask.long 0x00 0.--31. 1. "CNT0_STS,Indicates the interval timer value"
group.long 0x18++0x03
line.long 0x00 "CNT1_STS0,CNT1_STS[m] indicates the time-out detection timer value"
hexmask.long 0x00 0.--31. 1. "CNT1_STS,Indicates the time-out detection timer value"
group.long 0x1C++0x03
line.long 0x00 "CNT1_UNS0,Set time-out detection timer operation minimum cycle register"
hexmask.long 0x00 0.--31. 1. "CNT1_UNS,Set minimum cycle value to stop Time-out detection timer"
tree.end
tree "RFSO_INST_1"
base ad:0xFFE81000
group.long 0x00++0x03
line.long 0x00 "CNT0_CYC1,CNT0_CYC[m] sets the periodical cycle value to the interval timer"
hexmask.long 0x00 0.--31. 1. "CNT0_CYC,Specify the periodical cycle value to the interval timer"
group.long 0x04++0x03
line.long 0x00 "CNT1_CYC1,CNT1_CYC[m] sets the periodical cycle value to the time-out detection timer"
hexmask.long 0x00 0.--31. 1. "CNT1_CYC,Specify the periodical cycle value to the time-out detection timer"
group.long 0x08++0x03
line.long 0x00 "FSO_CTL1,FSO_CTL[m] is a control register of this module"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Register write enable code"
rbitfld.long 0x00 10.--15. "Reserved_10,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 9. "Reserved_9,Reserved" "0,1"
newline
bitfld.long 0x00 8. "ITE,Enables or disables an interval timer (CNT0) interrupt request" "0: Disables the interrupt,1: Enables the interrupt"
rbitfld.long 0x00 7. "TOCUNF,Indicates whether a time-out detection timer (CNT1) has stopped when the value of a time-out detection timer (CNT1) is below the lower limit (CNT1_UNS[m])" "0: A time-out detection timer (CNT1) has stopped,1: A time-out detection timer (CNT1) has stopped"
rbitfld.long 0x00 6. "TOI,Indicates whether a time-out detection timer (CNT1) has stopped under the condition that the value of a time-out detection timer (CNT1) is equal to the upper limit (CNT1_CYC[m]) or whether a time-out detection timer (CNT1) has stopped under the.." "0: There is no interrupt,1: There is an interrupt"
newline
rbitfld.long 0x00 5. "ITI,Indicates whether there is an interval timer (CNT0) interrupt request" "0: There is no interrupt,1: There is an interrupt"
rbitfld.long 0x00 4. "TOES,Indicates that time-out error status is appropriately output to the ECM module" "0,1"
rbitfld.long 0x00 3. "CFES_1,Indicates that the CFEO_1 bit status is appropriately output to the ECM module" "0,1"
newline
bitfld.long 0x00 2. "CFEO_1,Sets the expected value verification result during test routine when the CFEO_0 bit is 1" "0,1"
bitfld.long 0x00 1. "CFEO_0,Sets the expected value verification result during test routine" "0,1"
rbitfld.long 0x00 0. "CFES_0,Indicates that the CFEO_0 bit status is appropriately output to the ECM module" "0,1"
group.long 0x0C++0x03
line.long 0x00 "CNT_DIV1,CNT_DIV[m] sets the interval timer/time-out detection timer counter clock frequency divisor"
hexmask.long 0x00 0.--31. 1. "CNT_DIV,Set the timer counter clock frequency divisor"
group.long 0x10++0x03
line.long 0x00 "FSO_CMD1,FSO_CMD[m] activates this module and clears the interrupts"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Register write enable code"
hexmask.long.word 0x00 4.--15. 1. "Reserved_4,Reserved"
bitfld.long 0x00 3. "TOC,Clears a time-out detection timer (CNT1) interrupt" "0,1"
newline
bitfld.long 0x00 2. "ITC,Clears an interval timer (CNT0) interrupt" "0,1"
bitfld.long 0x00 1. "CNTS1,Activates or stops the time-out detection timer (CNT1)" "0,1"
bitfld.long 0x00 0. "CNTS0,Activates or stops the interval timer (CNT0)" "0,1"
group.long 0x14++0x03
line.long 0x00 "CNT0_STS1,CNT0_STS[m] indicates the interval timer value"
hexmask.long 0x00 0.--31. 1. "CNT0_STS,Indicates the interval timer value"
group.long 0x18++0x03
line.long 0x00 "CNT1_STS1,CNT1_STS[m] indicates the time-out detection timer value"
hexmask.long 0x00 0.--31. 1. "CNT1_STS,Indicates the time-out detection timer value"
group.long 0x1C++0x03
line.long 0x00 "CNT1_UNS1,Set time-out detection timer operation minimum cycle register"
hexmask.long 0x00 0.--31. 1. "CNT1_UNS,Set minimum cycle value to stop Time-out detection timer"
tree.end
tree "RFSO_INST_2"
base ad:0xFFE82000
group.long 0x00++0x03
line.long 0x00 "CNT0_CYC2,CNT0_CYC[m] sets the periodical cycle value to the interval timer"
hexmask.long 0x00 0.--31. 1. "CNT0_CYC,Specify the periodical cycle value to the interval timer"
group.long 0x04++0x03
line.long 0x00 "CNT1_CYC2,CNT1_CYC[m] sets the periodical cycle value to the time-out detection timer"
hexmask.long 0x00 0.--31. 1. "CNT1_CYC,Specify the periodical cycle value to the time-out detection timer"
group.long 0x08++0x03
line.long 0x00 "FSO_CTL2,FSO_CTL[m] is a control register of this module"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Register write enable code"
rbitfld.long 0x00 10.--15. "Reserved_10,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 9. "Reserved_9,Reserved" "0,1"
newline
bitfld.long 0x00 8. "ITE,Enables or disables an interval timer (CNT0) interrupt request" "0: Disables the interrupt,1: Enables the interrupt"
rbitfld.long 0x00 7. "TOCUNF,Indicates whether a time-out detection timer (CNT1) has stopped when the value of a time-out detection timer (CNT1) is below the lower limit (CNT1_UNS[m])" "0: A time-out detection timer (CNT1) has stopped,1: A time-out detection timer (CNT1) has stopped"
rbitfld.long 0x00 6. "TOI,Indicates whether a time-out detection timer (CNT1) has stopped under the condition that the value of a time-out detection timer (CNT1) is equal to the upper limit (CNT1_CYC[m]) or whether a time-out detection timer (CNT1) has stopped under the.." "0: There is no interrupt,1: There is an interrupt"
newline
rbitfld.long 0x00 5. "ITI,Indicates whether there is an interval timer (CNT0) interrupt request" "0: There is no interrupt,1: There is an interrupt"
rbitfld.long 0x00 4. "TOES,Indicates that time-out error status is appropriately output to the ECM module" "0,1"
rbitfld.long 0x00 3. "CFES_1,Indicates that the CFEO_1 bit status is appropriately output to the ECM module" "0,1"
newline
bitfld.long 0x00 2. "CFEO_1,Sets the expected value verification result during test routine when the CFEO_0 bit is 1" "0,1"
bitfld.long 0x00 1. "CFEO_0,Sets the expected value verification result during test routine" "0,1"
rbitfld.long 0x00 0. "CFES_0,Indicates that the CFEO_0 bit status is appropriately output to the ECM module" "0,1"
group.long 0x0C++0x03
line.long 0x00 "CNT_DIV2,CNT_DIV[m] sets the interval timer/time-out detection timer counter clock frequency divisor"
hexmask.long 0x00 0.--31. 1. "CNT_DIV,Set the timer counter clock frequency divisor"
group.long 0x10++0x03
line.long 0x00 "FSO_CMD2,FSO_CMD[m] activates this module and clears the interrupts"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Register write enable code"
hexmask.long.word 0x00 4.--15. 1. "Reserved_4,Reserved"
bitfld.long 0x00 3. "TOC,Clears a time-out detection timer (CNT1) interrupt" "0,1"
newline
bitfld.long 0x00 2. "ITC,Clears an interval timer (CNT0) interrupt" "0,1"
bitfld.long 0x00 1. "CNTS1,Activates or stops the time-out detection timer (CNT1)" "0,1"
bitfld.long 0x00 0. "CNTS0,Activates or stops the interval timer (CNT0)" "0,1"
group.long 0x14++0x03
line.long 0x00 "CNT0_STS2,CNT0_STS[m] indicates the interval timer value"
hexmask.long 0x00 0.--31. 1. "CNT0_STS,Indicates the interval timer value"
group.long 0x18++0x03
line.long 0x00 "CNT1_STS2,CNT1_STS[m] indicates the time-out detection timer value"
hexmask.long 0x00 0.--31. 1. "CNT1_STS,Indicates the time-out detection timer value"
group.long 0x1C++0x03
line.long 0x00 "CNT1_UNS2,Set time-out detection timer operation minimum cycle register"
hexmask.long 0x00 0.--31. 1. "CNT1_UNS,Set minimum cycle value to stop Time-out detection timer"
tree.end
tree "RFSO_INST_3"
base ad:0xFFE83000
group.long 0x00++0x03
line.long 0x00 "CNT0_CYC3,CNT0_CYC[m] sets the periodical cycle value to the interval timer"
hexmask.long 0x00 0.--31. 1. "CNT0_CYC,Specify the periodical cycle value to the interval timer"
group.long 0x04++0x03
line.long 0x00 "CNT1_CYC3,CNT1_CYC[m] sets the periodical cycle value to the time-out detection timer"
hexmask.long 0x00 0.--31. 1. "CNT1_CYC,Specify the periodical cycle value to the time-out detection timer"
group.long 0x08++0x03
line.long 0x00 "FSO_CTL3,FSO_CTL[m] is a control register of this module"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Register write enable code"
rbitfld.long 0x00 10.--15. "Reserved_10,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 9. "Reserved_9,Reserved" "0,1"
newline
bitfld.long 0x00 8. "ITE,Enables or disables an interval timer (CNT0) interrupt request" "0: Disables the interrupt,1: Enables the interrupt"
rbitfld.long 0x00 7. "TOCUNF,Indicates whether a time-out detection timer (CNT1) has stopped when the value of a time-out detection timer (CNT1) is below the lower limit (CNT1_UNS[m])" "0: A time-out detection timer (CNT1) has stopped,1: A time-out detection timer (CNT1) has stopped"
rbitfld.long 0x00 6. "TOI,Indicates whether a time-out detection timer (CNT1) has stopped under the condition that the value of a time-out detection timer (CNT1) is equal to the upper limit (CNT1_CYC[m]) or whether a time-out detection timer (CNT1) has stopped under the.." "0: There is no interrupt,1: There is an interrupt"
newline
rbitfld.long 0x00 5. "ITI,Indicates whether there is an interval timer (CNT0) interrupt request" "0: There is no interrupt,1: There is an interrupt"
rbitfld.long 0x00 4. "TOES,Indicates that time-out error status is appropriately output to the ECM module" "0,1"
rbitfld.long 0x00 3. "CFES_1,Indicates that the CFEO_1 bit status is appropriately output to the ECM module" "0,1"
newline
bitfld.long 0x00 2. "CFEO_1,Sets the expected value verification result during test routine when the CFEO_0 bit is 1" "0,1"
bitfld.long 0x00 1. "CFEO_0,Sets the expected value verification result during test routine" "0,1"
rbitfld.long 0x00 0. "CFES_0,Indicates that the CFEO_0 bit status is appropriately output to the ECM module" "0,1"
group.long 0x0C++0x03
line.long 0x00 "CNT_DIV3,CNT_DIV[m] sets the interval timer/time-out detection timer counter clock frequency divisor"
hexmask.long 0x00 0.--31. 1. "CNT_DIV,Set the timer counter clock frequency divisor"
group.long 0x10++0x03
line.long 0x00 "FSO_CMD3,FSO_CMD[m] activates this module and clears the interrupts"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Register write enable code"
hexmask.long.word 0x00 4.--15. 1. "Reserved_4,Reserved"
bitfld.long 0x00 3. "TOC,Clears a time-out detection timer (CNT1) interrupt" "0,1"
newline
bitfld.long 0x00 2. "ITC,Clears an interval timer (CNT0) interrupt" "0,1"
bitfld.long 0x00 1. "CNTS1,Activates or stops the time-out detection timer (CNT1)" "0,1"
bitfld.long 0x00 0. "CNTS0,Activates or stops the interval timer (CNT0)" "0,1"
group.long 0x14++0x03
line.long 0x00 "CNT0_STS3,CNT0_STS[m] indicates the interval timer value"
hexmask.long 0x00 0.--31. 1. "CNT0_STS,Indicates the interval timer value"
group.long 0x18++0x03
line.long 0x00 "CNT1_STS3,CNT1_STS[m] indicates the time-out detection timer value"
hexmask.long 0x00 0.--31. 1. "CNT1_STS,Indicates the time-out detection timer value"
group.long 0x1C++0x03
line.long 0x00 "CNT1_UNS3,Set time-out detection timer operation minimum cycle register"
hexmask.long 0x00 0.--31. 1. "CNT1_UNS,Set minimum cycle value to stop Time-out detection timer"
tree.end
tree "RFSO_INST_4"
base ad:0xFFE84000
group.long 0x00++0x03
line.long 0x00 "CNT0_CYC4,CNT0_CYC[m] sets the periodical cycle value to the interval timer"
hexmask.long 0x00 0.--31. 1. "CNT0_CYC,Specify the periodical cycle value to the interval timer"
group.long 0x04++0x03
line.long 0x00 "CNT1_CYC4,CNT1_CYC[m] sets the periodical cycle value to the time-out detection timer"
hexmask.long 0x00 0.--31. 1. "CNT1_CYC,Specify the periodical cycle value to the time-out detection timer"
group.long 0x08++0x03
line.long 0x00 "FSO_CTL4,FSO_CTL[m] is a control register of this module"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Register write enable code"
rbitfld.long 0x00 10.--15. "Reserved_10,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 9. "Reserved_9,Reserved" "0,1"
newline
bitfld.long 0x00 8. "ITE,Enables or disables an interval timer (CNT0) interrupt request" "0: Disables the interrupt,1: Enables the interrupt"
rbitfld.long 0x00 7. "TOCUNF,Indicates whether a time-out detection timer (CNT1) has stopped when the value of a time-out detection timer (CNT1) is below the lower limit (CNT1_UNS[m])" "0: A time-out detection timer (CNT1) has stopped,1: A time-out detection timer (CNT1) has stopped"
rbitfld.long 0x00 6. "TOI,Indicates whether a time-out detection timer (CNT1) has stopped under the condition that the value of a time-out detection timer (CNT1) is equal to the upper limit (CNT1_CYC[m]) or whether a time-out detection timer (CNT1) has stopped under the.." "0: There is no interrupt,1: There is an interrupt"
newline
rbitfld.long 0x00 5. "ITI,Indicates whether there is an interval timer (CNT0) interrupt request" "0: There is no interrupt,1: There is an interrupt"
rbitfld.long 0x00 4. "TOES,Indicates that time-out error status is appropriately output to the ECM module" "0,1"
rbitfld.long 0x00 3. "CFES_1,Indicates that the CFEO_1 bit status is appropriately output to the ECM module" "0,1"
newline
bitfld.long 0x00 2. "CFEO_1,Sets the expected value verification result during test routine when the CFEO_0 bit is 1" "0,1"
bitfld.long 0x00 1. "CFEO_0,Sets the expected value verification result during test routine" "0,1"
rbitfld.long 0x00 0. "CFES_0,Indicates that the CFEO_0 bit status is appropriately output to the ECM module" "0,1"
group.long 0x0C++0x03
line.long 0x00 "CNT_DIV4,CNT_DIV[m] sets the interval timer/time-out detection timer counter clock frequency divisor"
hexmask.long 0x00 0.--31. 1. "CNT_DIV,Set the timer counter clock frequency divisor"
group.long 0x10++0x03
line.long 0x00 "FSO_CMD4,FSO_CMD[m] activates this module and clears the interrupts"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Register write enable code"
hexmask.long.word 0x00 4.--15. 1. "Reserved_4,Reserved"
bitfld.long 0x00 3. "TOC,Clears a time-out detection timer (CNT1) interrupt" "0,1"
newline
bitfld.long 0x00 2. "ITC,Clears an interval timer (CNT0) interrupt" "0,1"
bitfld.long 0x00 1. "CNTS1,Activates or stops the time-out detection timer (CNT1)" "0,1"
bitfld.long 0x00 0. "CNTS0,Activates or stops the interval timer (CNT0)" "0,1"
group.long 0x14++0x03
line.long 0x00 "CNT0_STS4,CNT0_STS[m] indicates the interval timer value"
hexmask.long 0x00 0.--31. 1. "CNT0_STS,Indicates the interval timer value"
group.long 0x18++0x03
line.long 0x00 "CNT1_STS4,CNT1_STS[m] indicates the time-out detection timer value"
hexmask.long 0x00 0.--31. 1. "CNT1_STS,Indicates the time-out detection timer value"
group.long 0x1C++0x03
line.long 0x00 "CNT1_UNS4,Set time-out detection timer operation minimum cycle register"
hexmask.long 0x00 0.--31. 1. "CNT1_UNS,Set minimum cycle value to stop Time-out detection timer"
tree.end
tree "RFSO_INST_5"
base ad:0xFFE85000
group.long 0x00++0x03
line.long 0x00 "CNT0_CYC5,CNT0_CYC[m] sets the periodical cycle value to the interval timer"
hexmask.long 0x00 0.--31. 1. "CNT0_CYC,Specify the periodical cycle value to the interval timer"
group.long 0x04++0x03
line.long 0x00 "CNT1_CYC5,CNT1_CYC[m] sets the periodical cycle value to the time-out detection timer"
hexmask.long 0x00 0.--31. 1. "CNT1_CYC,Specify the periodical cycle value to the time-out detection timer"
group.long 0x08++0x03
line.long 0x00 "FSO_CTL5,FSO_CTL[m] is a control register of this module"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Register write enable code"
rbitfld.long 0x00 10.--15. "Reserved_10,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 9. "Reserved_9,Reserved" "0,1"
newline
bitfld.long 0x00 8. "ITE,Enables or disables an interval timer (CNT0) interrupt request" "0: Disables the interrupt,1: Enables the interrupt"
rbitfld.long 0x00 7. "TOCUNF,Indicates whether a time-out detection timer (CNT1) has stopped when the value of a time-out detection timer (CNT1) is below the lower limit (CNT1_UNS[m])" "0: A time-out detection timer (CNT1) has stopped,1: A time-out detection timer (CNT1) has stopped"
rbitfld.long 0x00 6. "TOI,Indicates whether a time-out detection timer (CNT1) has stopped under the condition that the value of a time-out detection timer (CNT1) is equal to the upper limit (CNT1_CYC[m]) or whether a time-out detection timer (CNT1) has stopped under the.." "0: There is no interrupt,1: There is an interrupt"
newline
rbitfld.long 0x00 5. "ITI,Indicates whether there is an interval timer (CNT0) interrupt request" "0: There is no interrupt,1: There is an interrupt"
rbitfld.long 0x00 4. "TOES,Indicates that time-out error status is appropriately output to the ECM module" "0,1"
rbitfld.long 0x00 3. "CFES_1,Indicates that the CFEO_1 bit status is appropriately output to the ECM module" "0,1"
newline
bitfld.long 0x00 2. "CFEO_1,Sets the expected value verification result during test routine when the CFEO_0 bit is 1" "0,1"
bitfld.long 0x00 1. "CFEO_0,Sets the expected value verification result during test routine" "0,1"
rbitfld.long 0x00 0. "CFES_0,Indicates that the CFEO_0 bit status is appropriately output to the ECM module" "0,1"
group.long 0x0C++0x03
line.long 0x00 "CNT_DIV5,CNT_DIV[m] sets the interval timer/time-out detection timer counter clock frequency divisor"
hexmask.long 0x00 0.--31. 1. "CNT_DIV,Set the timer counter clock frequency divisor"
group.long 0x10++0x03
line.long 0x00 "FSO_CMD5,FSO_CMD[m] activates this module and clears the interrupts"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Register write enable code"
hexmask.long.word 0x00 4.--15. 1. "Reserved_4,Reserved"
bitfld.long 0x00 3. "TOC,Clears a time-out detection timer (CNT1) interrupt" "0,1"
newline
bitfld.long 0x00 2. "ITC,Clears an interval timer (CNT0) interrupt" "0,1"
bitfld.long 0x00 1. "CNTS1,Activates or stops the time-out detection timer (CNT1)" "0,1"
bitfld.long 0x00 0. "CNTS0,Activates or stops the interval timer (CNT0)" "0,1"
group.long 0x14++0x03
line.long 0x00 "CNT0_STS5,CNT0_STS[m] indicates the interval timer value"
hexmask.long 0x00 0.--31. 1. "CNT0_STS,Indicates the interval timer value"
group.long 0x18++0x03
line.long 0x00 "CNT1_STS5,CNT1_STS[m] indicates the time-out detection timer value"
hexmask.long 0x00 0.--31. 1. "CNT1_STS,Indicates the time-out detection timer value"
group.long 0x1C++0x03
line.long 0x00 "CNT1_UNS5,Set time-out detection timer operation minimum cycle register"
hexmask.long 0x00 0.--31. 1. "CNT1_UNS,Set minimum cycle value to stop Time-out detection timer"
tree.end
tree "RFSO_INST_6"
base ad:0xFFE86000
group.long 0x00++0x03
line.long 0x00 "CNT0_CYC6,CNT0_CYC[m] sets the periodical cycle value to the interval timer"
hexmask.long 0x00 0.--31. 1. "CNT0_CYC,Specify the periodical cycle value to the interval timer"
group.long 0x04++0x03
line.long 0x00 "CNT1_CYC6,CNT1_CYC[m] sets the periodical cycle value to the time-out detection timer"
hexmask.long 0x00 0.--31. 1. "CNT1_CYC,Specify the periodical cycle value to the time-out detection timer"
group.long 0x08++0x03
line.long 0x00 "FSO_CTL6,FSO_CTL[m] is a control register of this module"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Register write enable code"
rbitfld.long 0x00 10.--15. "Reserved_10,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 9. "Reserved_9,Reserved" "0,1"
newline
bitfld.long 0x00 8. "ITE,Enables or disables an interval timer (CNT0) interrupt request" "0: Disables the interrupt,1: Enables the interrupt"
rbitfld.long 0x00 7. "TOCUNF,Indicates whether a time-out detection timer (CNT1) has stopped when the value of a time-out detection timer (CNT1) is below the lower limit (CNT1_UNS[m])" "0: A time-out detection timer (CNT1) has stopped,1: A time-out detection timer (CNT1) has stopped"
rbitfld.long 0x00 6. "TOI,Indicates whether a time-out detection timer (CNT1) has stopped under the condition that the value of a time-out detection timer (CNT1) is equal to the upper limit (CNT1_CYC[m]) or whether a time-out detection timer (CNT1) has stopped under the.." "0: There is no interrupt,1: There is an interrupt"
newline
rbitfld.long 0x00 5. "ITI,Indicates whether there is an interval timer (CNT0) interrupt request" "0: There is no interrupt,1: There is an interrupt"
rbitfld.long 0x00 4. "TOES,Indicates that time-out error status is appropriately output to the ECM module" "0,1"
rbitfld.long 0x00 3. "CFES_1,Indicates that the CFEO_1 bit status is appropriately output to the ECM module" "0,1"
newline
bitfld.long 0x00 2. "CFEO_1,Sets the expected value verification result during test routine when the CFEO_0 bit is 1" "0,1"
bitfld.long 0x00 1. "CFEO_0,Sets the expected value verification result during test routine" "0,1"
rbitfld.long 0x00 0. "CFES_0,Indicates that the CFEO_0 bit status is appropriately output to the ECM module" "0,1"
group.long 0x0C++0x03
line.long 0x00 "CNT_DIV6,CNT_DIV[m] sets the interval timer/time-out detection timer counter clock frequency divisor"
hexmask.long 0x00 0.--31. 1. "CNT_DIV,Set the timer counter clock frequency divisor"
group.long 0x10++0x03
line.long 0x00 "FSO_CMD6,FSO_CMD[m] activates this module and clears the interrupts"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Register write enable code"
hexmask.long.word 0x00 4.--15. 1. "Reserved_4,Reserved"
bitfld.long 0x00 3. "TOC,Clears a time-out detection timer (CNT1) interrupt" "0,1"
newline
bitfld.long 0x00 2. "ITC,Clears an interval timer (CNT0) interrupt" "0,1"
bitfld.long 0x00 1. "CNTS1,Activates or stops the time-out detection timer (CNT1)" "0,1"
bitfld.long 0x00 0. "CNTS0,Activates or stops the interval timer (CNT0)" "0,1"
group.long 0x14++0x03
line.long 0x00 "CNT0_STS6,CNT0_STS[m] indicates the interval timer value"
hexmask.long 0x00 0.--31. 1. "CNT0_STS,Indicates the interval timer value"
group.long 0x18++0x03
line.long 0x00 "CNT1_STS6,CNT1_STS[m] indicates the time-out detection timer value"
hexmask.long 0x00 0.--31. 1. "CNT1_STS,Indicates the time-out detection timer value"
group.long 0x1C++0x03
line.long 0x00 "CNT1_UNS6,Set time-out detection timer operation minimum cycle register"
hexmask.long 0x00 0.--31. 1. "CNT1_UNS,Set minimum cycle value to stop Time-out detection timer"
tree.end
tree "RFSO_INST_7"
base ad:0xFFE87000
group.long 0x00++0x03
line.long 0x00 "CNT0_CYC7,CNT0_CYC[m] sets the periodical cycle value to the interval timer"
hexmask.long 0x00 0.--31. 1. "CNT0_CYC,Specify the periodical cycle value to the interval timer"
group.long 0x04++0x03
line.long 0x00 "CNT1_CYC7,CNT1_CYC[m] sets the periodical cycle value to the time-out detection timer"
hexmask.long 0x00 0.--31. 1. "CNT1_CYC,Specify the periodical cycle value to the time-out detection timer"
group.long 0x08++0x03
line.long 0x00 "FSO_CTL7,FSO_CTL[m] is a control register of this module"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Register write enable code"
rbitfld.long 0x00 10.--15. "Reserved_10,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 9. "Reserved_9,Reserved" "0,1"
newline
bitfld.long 0x00 8. "ITE,Enables or disables an interval timer (CNT0) interrupt request" "0: Disables the interrupt,1: Enables the interrupt"
rbitfld.long 0x00 7. "TOCUNF,Indicates whether a time-out detection timer (CNT1) has stopped when the value of a time-out detection timer (CNT1) is below the lower limit (CNT1_UNS[m])" "0: A time-out detection timer (CNT1) has stopped,1: A time-out detection timer (CNT1) has stopped"
rbitfld.long 0x00 6. "TOI,Indicates whether a time-out detection timer (CNT1) has stopped under the condition that the value of a time-out detection timer (CNT1) is equal to the upper limit (CNT1_CYC[m]) or whether a time-out detection timer (CNT1) has stopped under the.." "0: There is no interrupt,1: There is an interrupt"
newline
rbitfld.long 0x00 5. "ITI,Indicates whether there is an interval timer (CNT0) interrupt request" "0: There is no interrupt,1: There is an interrupt"
rbitfld.long 0x00 4. "TOES,Indicates that time-out error status is appropriately output to the ECM module" "0,1"
rbitfld.long 0x00 3. "CFES_1,Indicates that the CFEO_1 bit status is appropriately output to the ECM module" "0,1"
newline
bitfld.long 0x00 2. "CFEO_1,Sets the expected value verification result during test routine when the CFEO_0 bit is 1" "0,1"
bitfld.long 0x00 1. "CFEO_0,Sets the expected value verification result during test routine" "0,1"
rbitfld.long 0x00 0. "CFES_0,Indicates that the CFEO_0 bit status is appropriately output to the ECM module" "0,1"
group.long 0x0C++0x03
line.long 0x00 "CNT_DIV7,CNT_DIV[m] sets the interval timer/time-out detection timer counter clock frequency divisor"
hexmask.long 0x00 0.--31. 1. "CNT_DIV,Set the timer counter clock frequency divisor"
group.long 0x10++0x03
line.long 0x00 "FSO_CMD7,FSO_CMD[m] activates this module and clears the interrupts"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Register write enable code"
hexmask.long.word 0x00 4.--15. 1. "Reserved_4,Reserved"
bitfld.long 0x00 3. "TOC,Clears a time-out detection timer (CNT1) interrupt" "0,1"
newline
bitfld.long 0x00 2. "ITC,Clears an interval timer (CNT0) interrupt" "0,1"
bitfld.long 0x00 1. "CNTS1,Activates or stops the time-out detection timer (CNT1)" "0,1"
bitfld.long 0x00 0. "CNTS0,Activates or stops the interval timer (CNT0)" "0,1"
group.long 0x14++0x03
line.long 0x00 "CNT0_STS7,CNT0_STS[m] indicates the interval timer value"
hexmask.long 0x00 0.--31. 1. "CNT0_STS,Indicates the interval timer value"
group.long 0x18++0x03
line.long 0x00 "CNT1_STS7,CNT1_STS[m] indicates the time-out detection timer value"
hexmask.long 0x00 0.--31. 1. "CNT1_STS,Indicates the time-out detection timer value"
group.long 0x1C++0x03
line.long 0x00 "CNT1_UNS7,Set time-out detection timer operation minimum cycle register"
hexmask.long 0x00 0.--31. 1. "CNT1_UNS,Set minimum cycle value to stop Time-out detection timer"
tree.end
tree "RFSO_INST_8"
base ad:0xFFE88000
group.long 0x00++0x03
line.long 0x00 "CNT0_CYC8,CNT0_CYC[m] sets the periodical cycle value to the interval timer"
hexmask.long 0x00 0.--31. 1. "CNT0_CYC,Specify the periodical cycle value to the interval timer"
group.long 0x04++0x03
line.long 0x00 "CNT1_CYC8,CNT1_CYC[m] sets the periodical cycle value to the time-out detection timer"
hexmask.long 0x00 0.--31. 1. "CNT1_CYC,Specify the periodical cycle value to the time-out detection timer"
group.long 0x08++0x03
line.long 0x00 "FSO_CTL8,FSO_CTL[m] is a control register of this module"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Register write enable code"
rbitfld.long 0x00 10.--15. "Reserved_10,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 9. "Reserved_9,Reserved" "0,1"
newline
bitfld.long 0x00 8. "ITE,Enables or disables an interval timer (CNT0) interrupt request" "0: Disables the interrupt,1: Enables the interrupt"
rbitfld.long 0x00 7. "TOCUNF,Indicates whether a time-out detection timer (CNT1) has stopped when the value of a time-out detection timer (CNT1) is below the lower limit (CNT1_UNS[m])" "0: A time-out detection timer (CNT1) has stopped,1: A time-out detection timer (CNT1) has stopped"
rbitfld.long 0x00 6. "TOI,Indicates whether a time-out detection timer (CNT1) has stopped under the condition that the value of a time-out detection timer (CNT1) is equal to the upper limit (CNT1_CYC[m]) or whether a time-out detection timer (CNT1) has stopped under the.." "0: There is no interrupt,1: There is an interrupt"
newline
rbitfld.long 0x00 5. "ITI,Indicates whether there is an interval timer (CNT0) interrupt request" "0: There is no interrupt,1: There is an interrupt"
rbitfld.long 0x00 4. "TOES,Indicates that time-out error status is appropriately output to the ECM module" "0,1"
rbitfld.long 0x00 3. "CFES_1,Indicates that the CFEO_1 bit status is appropriately output to the ECM module" "0,1"
newline
bitfld.long 0x00 2. "CFEO_1,Sets the expected value verification result during test routine when the CFEO_0 bit is 1" "0,1"
bitfld.long 0x00 1. "CFEO_0,Sets the expected value verification result during test routine" "0,1"
rbitfld.long 0x00 0. "CFES_0,Indicates that the CFEO_0 bit status is appropriately output to the ECM module" "0,1"
group.long 0x0C++0x03
line.long 0x00 "CNT_DIV8,CNT_DIV[m] sets the interval timer/time-out detection timer counter clock frequency divisor"
hexmask.long 0x00 0.--31. 1. "CNT_DIV,Set the timer counter clock frequency divisor"
group.long 0x10++0x03
line.long 0x00 "FSO_CMD8,FSO_CMD[m] activates this module and clears the interrupts"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Register write enable code"
hexmask.long.word 0x00 4.--15. 1. "Reserved_4,Reserved"
bitfld.long 0x00 3. "TOC,Clears a time-out detection timer (CNT1) interrupt" "0,1"
newline
bitfld.long 0x00 2. "ITC,Clears an interval timer (CNT0) interrupt" "0,1"
bitfld.long 0x00 1. "CNTS1,Activates or stops the time-out detection timer (CNT1)" "0,1"
bitfld.long 0x00 0. "CNTS0,Activates or stops the interval timer (CNT0)" "0,1"
group.long 0x14++0x03
line.long 0x00 "CNT0_STS8,CNT0_STS[m] indicates the interval timer value"
hexmask.long 0x00 0.--31. 1. "CNT0_STS,Indicates the interval timer value"
group.long 0x18++0x03
line.long 0x00 "CNT1_STS8,CNT1_STS[m] indicates the time-out detection timer value"
hexmask.long 0x00 0.--31. 1. "CNT1_STS,Indicates the time-out detection timer value"
group.long 0x1C++0x03
line.long 0x00 "CNT1_UNS8,Set time-out detection timer operation minimum cycle register"
hexmask.long 0x00 0.--31. 1. "CNT1_UNS,Set minimum cycle value to stop Time-out detection timer"
tree.end
tree "RFSO_INST_9"
base ad:0xFFE89000
group.long 0x00++0x03
line.long 0x00 "CNT0_CYC9,CNT0_CYC[m] sets the periodical cycle value to the interval timer"
hexmask.long 0x00 0.--31. 1. "CNT0_CYC,Specify the periodical cycle value to the interval timer"
group.long 0x04++0x03
line.long 0x00 "CNT1_CYC9,CNT1_CYC[m] sets the periodical cycle value to the time-out detection timer"
hexmask.long 0x00 0.--31. 1. "CNT1_CYC,Specify the periodical cycle value to the time-out detection timer"
group.long 0x08++0x03
line.long 0x00 "FSO_CTL9,FSO_CTL[m] is a control register of this module"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Register write enable code"
rbitfld.long 0x00 10.--15. "Reserved_10,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 9. "Reserved_9,Reserved" "0,1"
newline
bitfld.long 0x00 8. "ITE,Enables or disables an interval timer (CNT0) interrupt request" "0: Disables the interrupt,1: Enables the interrupt"
rbitfld.long 0x00 7. "TOCUNF,Indicates whether a time-out detection timer (CNT1) has stopped when the value of a time-out detection timer (CNT1) is below the lower limit (CNT1_UNS[m])" "0: A time-out detection timer (CNT1) has stopped,1: A time-out detection timer (CNT1) has stopped"
rbitfld.long 0x00 6. "TOI,Indicates whether a time-out detection timer (CNT1) has stopped under the condition that the value of a time-out detection timer (CNT1) is equal to the upper limit (CNT1_CYC[m]) or whether a time-out detection timer (CNT1) has stopped under the.." "0: There is no interrupt,1: There is an interrupt"
newline
rbitfld.long 0x00 5. "ITI,Indicates whether there is an interval timer (CNT0) interrupt request" "0: There is no interrupt,1: There is an interrupt"
rbitfld.long 0x00 4. "TOES,Indicates that time-out error status is appropriately output to the ECM module" "0,1"
rbitfld.long 0x00 3. "CFES_1,Indicates that the CFEO_1 bit status is appropriately output to the ECM module" "0,1"
newline
bitfld.long 0x00 2. "CFEO_1,Sets the expected value verification result during test routine when the CFEO_0 bit is 1" "0,1"
bitfld.long 0x00 1. "CFEO_0,Sets the expected value verification result during test routine" "0,1"
rbitfld.long 0x00 0. "CFES_0,Indicates that the CFEO_0 bit status is appropriately output to the ECM module" "0,1"
group.long 0x0C++0x03
line.long 0x00 "CNT_DIV9,CNT_DIV[m] sets the interval timer/time-out detection timer counter clock frequency divisor"
hexmask.long 0x00 0.--31. 1. "CNT_DIV,Set the timer counter clock frequency divisor"
group.long 0x10++0x03
line.long 0x00 "FSO_CMD9,FSO_CMD[m] activates this module and clears the interrupts"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Register write enable code"
hexmask.long.word 0x00 4.--15. 1. "Reserved_4,Reserved"
bitfld.long 0x00 3. "TOC,Clears a time-out detection timer (CNT1) interrupt" "0,1"
newline
bitfld.long 0x00 2. "ITC,Clears an interval timer (CNT0) interrupt" "0,1"
bitfld.long 0x00 1. "CNTS1,Activates or stops the time-out detection timer (CNT1)" "0,1"
bitfld.long 0x00 0. "CNTS0,Activates or stops the interval timer (CNT0)" "0,1"
group.long 0x14++0x03
line.long 0x00 "CNT0_STS9,CNT0_STS[m] indicates the interval timer value"
hexmask.long 0x00 0.--31. 1. "CNT0_STS,Indicates the interval timer value"
group.long 0x18++0x03
line.long 0x00 "CNT1_STS9,CNT1_STS[m] indicates the time-out detection timer value"
hexmask.long 0x00 0.--31. 1. "CNT1_STS,Indicates the time-out detection timer value"
group.long 0x1C++0x03
line.long 0x00 "CNT1_UNS9,Set time-out detection timer operation minimum cycle register"
hexmask.long 0x00 0.--31. 1. "CNT1_UNS,Set minimum cycle value to stop Time-out detection timer"
tree.end
tree "RFSO_INST_10"
base ad:0xFFE8A000
group.long 0x00++0x03
line.long 0x00 "CNT0_CYC10,CNT0_CYC[m] sets the periodical cycle value to the interval timer"
hexmask.long 0x00 0.--31. 1. "CNT0_CYC,Specify the periodical cycle value to the interval timer"
group.long 0x04++0x03
line.long 0x00 "CNT1_CYC10,CNT1_CYC[m] sets the periodical cycle value to the time-out detection timer"
hexmask.long 0x00 0.--31. 1. "CNT1_CYC,Specify the periodical cycle value to the time-out detection timer"
group.long 0x08++0x03
line.long 0x00 "FSO_CTL10,FSO_CTL[m] is a control register of this module"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Register write enable code"
rbitfld.long 0x00 10.--15. "Reserved_10,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 9. "Reserved_9,Reserved" "0,1"
newline
bitfld.long 0x00 8. "ITE,Enables or disables an interval timer (CNT0) interrupt request" "0: Disables the interrupt,1: Enables the interrupt"
rbitfld.long 0x00 7. "TOCUNF,Indicates whether a time-out detection timer (CNT1) has stopped when the value of a time-out detection timer (CNT1) is below the lower limit (CNT1_UNS[m])" "0: A time-out detection timer (CNT1) has stopped,1: A time-out detection timer (CNT1) has stopped"
rbitfld.long 0x00 6. "TOI,Indicates whether a time-out detection timer (CNT1) has stopped under the condition that the value of a time-out detection timer (CNT1) is equal to the upper limit (CNT1_CYC[m]) or whether a time-out detection timer (CNT1) has stopped under the.." "0: There is no interrupt,1: There is an interrupt"
newline
rbitfld.long 0x00 5. "ITI,Indicates whether there is an interval timer (CNT0) interrupt request" "0: There is no interrupt,1: There is an interrupt"
rbitfld.long 0x00 4. "TOES,Indicates that time-out error status is appropriately output to the ECM module" "0,1"
rbitfld.long 0x00 3. "CFES_1,Indicates that the CFEO_1 bit status is appropriately output to the ECM module" "0,1"
newline
bitfld.long 0x00 2. "CFEO_1,Sets the expected value verification result during test routine when the CFEO_0 bit is 1" "0,1"
bitfld.long 0x00 1. "CFEO_0,Sets the expected value verification result during test routine" "0,1"
rbitfld.long 0x00 0. "CFES_0,Indicates that the CFEO_0 bit status is appropriately output to the ECM module" "0,1"
group.long 0x0C++0x03
line.long 0x00 "CNT_DIV10,CNT_DIV[m] sets the interval timer/time-out detection timer counter clock frequency divisor"
hexmask.long 0x00 0.--31. 1. "CNT_DIV,Set the timer counter clock frequency divisor"
group.long 0x10++0x03
line.long 0x00 "FSO_CMD10,FSO_CMD[m] activates this module and clears the interrupts"
hexmask.long.word 0x00 16.--31. 1. "KEYCODE,Register write enable code"
hexmask.long.word 0x00 4.--15. 1. "Reserved_4,Reserved"
bitfld.long 0x00 3. "TOC,Clears a time-out detection timer (CNT1) interrupt" "0,1"
newline
bitfld.long 0x00 2. "ITC,Clears an interval timer (CNT0) interrupt" "0,1"
bitfld.long 0x00 1. "CNTS1,Activates or stops the time-out detection timer (CNT1)" "0,1"
bitfld.long 0x00 0. "CNTS0,Activates or stops the interval timer (CNT0)" "0,1"
group.long 0x14++0x03
line.long 0x00 "CNT0_STS10,CNT0_STS[m] indicates the interval timer value"
hexmask.long 0x00 0.--31. 1. "CNT0_STS,Indicates the interval timer value"
group.long 0x18++0x03
line.long 0x00 "CNT1_STS10,CNT1_STS[m] indicates the time-out detection timer value"
hexmask.long 0x00 0.--31. 1. "CNT1_STS,Indicates the time-out detection timer value"
group.long 0x1C++0x03
line.long 0x00 "CNT1_UNS10,Set time-out detection timer operation minimum cycle register"
hexmask.long 0x00 0.--31. 1. "CNT1_UNS,Set minimum cycle value to stop Time-out detection timer"
tree.end
tree.end
tree "SDHI_MMC"
tree "SDHI_MMC_INST_0"
base ad:0xEE140000
group.quad 0x00++0x07
line.quad 0x00 "SD_CMD,For details on the SD_CMD setting refer to section 70.4.15 Example of SD_CMD and MMC_CMD Register Setting"
hexmask.quad.quad 0x00 16.--63. 1. "Reserved_16,Reserved bits These bits are always read as 0"
bitfld.quad 0x00 15. "MD7,Multiple Block Transfer Mode (enabled at multiple block transfer) {MD7 DM6}" "0: CMD12 is automatically issued at multiple block,1: CMD12 is not automatically issued at multiple"
newline
bitfld.quad 0x00 14. "MD6,Refer to MD7 Bit Description" "0,1"
bitfld.quad 0x00 13. "MD5,Single/Multiple Block Transfer (enabled when the command with data is handled)" "0: Single block transfer,1: Multi block transfer"
newline
bitfld.quad 0x00 12. "MD4,Write/Read Mode (enabled when the command with data is handled)" "0: Write (SD host interface -> SD card),1: Read (SD host interface <- SD card)"
bitfld.quad 0x00 11. "MD3,Data Mode (Command Type)" "0: Command without data transfer (bc bcr ac),1: Command with data transfer (adtc)"
newline
bitfld.quad 0x00 10. "MD2,Mode/Response Type {MD2 MD1 MD0}" "0: Normal mode The response type and the transfer,1: Setting prohibited"
bitfld.quad 0x00 9. "MD1,Refer to MD2 Bit Description" "0,1"
newline
bitfld.quad 0x00 8. "MD0,Refer to MD2 Bit Description" "0,1"
bitfld.quad 0x00 7. "C1,{C1 C0}" "0: CMD,1: ACMD"
newline
bitfld.quad 0x00 6. "C0,Refer to C1 Bit Description" "0,1"
bitfld.quad 0x00 5. "CF45,Command Index These bits specify Command Format[45:40] (command index)" "0,1"
newline
bitfld.quad 0x00 4. "CF44,Refer to CF45 Bit Description" "0,1"
bitfld.quad 0x00 3. "CF43,Refer to CF45 Bit Description" "0,1"
newline
bitfld.quad 0x00 2. "CF42,Refer to CF45 Bit Description" "0,1"
bitfld.quad 0x00 1. "CF41,Refer to CF45 Bit Description" "0,1"
newline
bitfld.quad 0x00 0. "CF40,Refer to CF45 Bit Description" "0,1"
group.quad 0x08++0x07
line.quad 0x00 "SD_PORTSEL,The port select register (SD_PORTSEL) selects the ports for SD cards"
hexmask.quad.quad 0x00 12.--63. 1. "Reserved_12,Reserved bits These bits are always read as 0"
rbitfld.quad 0x00 10.--11. "Reserved_10,Reserved bits These bits are always read as 0" "0,1,2,3"
newline
rbitfld.quad 0x00 9. "NP1,Number of ports supported for SD cards [NP1 NP0] =" "0,1"
rbitfld.quad 0x00 8. "NP0,Refer to NP1 Bit Description" "0,1"
newline
rbitfld.quad 0x00 4.--7. "Reserved_4,Reserved bits These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 0.--3. "Reserved_0,Reserved The write value should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.quad 0x10++0x07
line.quad 0x00 "SD_ARG,Command arguments for SD cards are set in the SD command argument registers (SD_ARG)"
hexmask.quad.long 0x00 32.--63. 1. "Reserved_32,Fixed 0"
hexmask.quad.long 0x00 0.--31. 1. "CF_39_8,Set command format[39:8] (argument)"
group.quad 0x18++0x07
line.quad 0x00 "SD_ARG1,Command arguments for SD cards are set in the SD command argument registers (SD_ARG)"
hexmask.quad.quad 0x00 16.--63. 1. "Reserved_16,Fixed 0"
hexmask.quad.word 0x00 0.--15. 1. "CF_39_24,Set command format[39:24] (argument)"
group.quad 0x20++0x07
line.quad 0x00 "SD_STOP,The data stop register (SD_STOP) is used to enable or disable block counting at multiple block transfer and to control the issuing of CMD12 within command sequences"
hexmask.quad.quad 0x00 19.--63. 1. "Reserved_19,Reserved bits These bits are always read as 0"
bitfld.quad 0x00 18. "Reserved_18,Reserved The write value should always be 0" "0,1"
newline
bitfld.quad 0x00 17. "HPIMODE,HPI Mode Enable" "0: Disables HPI mode,1: Enables HPI mode"
bitfld.quad 0x00 16. "HPICMD,HPI Command Issue When HPICMD is set to 1 while HPIMODE is 1 the HPI command (CMD12) is issued" "0,1"
newline
hexmask.quad.byte 0x00 9.--15. 1. "Reserved_9,Reserved bits These bits are always read as 0"
bitfld.quad 0x00 8. "SEC,Block Count Enable" "0: Disables SD_SECCNT setting value,1: Enables SD_SECCNT setting value"
newline
hexmask.quad.byte 0x00 1.--7. 1. "Reserved_1,Reserved bits These bits are always read as 0"
bitfld.quad 0x00 0. "STP,Stop When STP is set to 1 during multiple block transfer CMD12 is issued to halt the transfer through the SD host interface" "0,1"
group.quad 0x28++0x07
line.quad 0x00 "SD_SECCNT,The block count register (SD_SECCNT) is used to specify the number of transfer blocks at multiple block transfer"
hexmask.quad.long 0x00 32.--63. 1. "Reserved_32,Reserved bits These bits are always read as 0"
hexmask.quad.long 0x00 0.--31. 1. "CNT_31_0,Number of Transfer Blocks When H'0000 0001 is set the number of transfer blocks is 1"
group.quad 0x30++0x07
line.quad 0x00 "SD_RSP10,The SD card response registers (SD_RSP) hold the response from the SD card"
hexmask.quad 0x00 0.--63. 1. "R_71_8,Hold the response from the SD card"
group.quad 0x38++0x07
line.quad 0x00 "SD_RSP1,The SD card response registers (SD_RSP) hold the response from the SD card"
hexmask.quad.quad 0x00 16.--63. 1. "Reserved_16,Reserved bits These bits are always read as 0"
hexmask.quad.word 0x00 0.--15. 1. "R_39_24,Hold the response from the SD card"
group.quad 0x40++0x07
line.quad 0x00 "SD_RSP32,The SD card response registers (SD_RSP) hold the response from the SD card.(Mirror of SD_RSP10[63:32])"
hexmask.quad.long 0x00 32.--63. 1. "Reserved_32,Reserved bits These bits are always read as 0"
hexmask.quad.long 0x00 0.--31. 1. "R_71_40,Hold the response from the SD card"
group.quad 0x48++0x07
line.quad 0x00 "SD_RSP3,The SD card response registers (SD_RSP) hold the response from the SD card.(Mirror of SD_RSP32[31:16])"
hexmask.quad.quad 0x00 16.--63. 1. "Reserved_16,Reserved bits These bits are always read as 0"
hexmask.quad.word 0x00 0.--15. 1. "R_71_56,Hold the response from the SD card"
group.quad 0x50++0x07
line.quad 0x00 "SD_RSP54,The SD card response registers (SD_RSP) hold the response from the SD card"
hexmask.quad.byte 0x00 56.--63. 1. "Reserved_56,Reserved bits These bits are always read as 0"
hexmask.quad.quad 0x00 0.--55. 1. "R_127_72,Hold the response from the SD card"
group.quad 0x58++0x07
line.quad 0x00 "SD_RSP5,The SD card response registers (SD_RSP) hold the response from the SD card.(Mirror of SD_RSP54[31:16])"
hexmask.quad.quad 0x00 16.--63. 1. "Reserved_16,Reserved bits These bits are always read as 0"
hexmask.quad.word 0x00 0.--15. 1. "R_103_88,Hold the response from the SD card"
group.quad 0x60++0x07
line.quad 0x00 "SD_RSP76,The SD card response registers (SD_RSP) hold the response from the SD card.(Mirror of SD_RSP54[63:32])"
hexmask.quad.quad 0x00 24.--63. 1. "Reserved_24,Reserved bits These bits are always read as 0"
hexmask.quad.tbyte 0x00 0.--23. 1. "R_127_104,Hold the response from the SD card"
group.quad 0x68++0x07
line.quad 0x00 "SD_RSP7,The SD card response registers (SD_RSP) hold the response from the SD card.(Mirror of SD_RSP76[31:16])"
hexmask.quad.quad 0x00 8.--63. 1. "Reserved_8,Reserved bits These bits are always read as 0"
hexmask.quad.byte 0x00 0.--7. 1. "R_127_120,Hold the response from the SD card"
group.quad 0x70++0x07
line.quad 0x00 "SD_INFO1,The SD card interrupt flag register 1 (SD_INFO1) indicates the response end and access end in the command sequence"
hexmask.quad.quad 0x00 17.--63. 1. "Reserved_17,Reserved bits These bits are always read as 0"
bitfld.quad 0x00 16. "INFO90,Response Reception Completion [Setting condition] When reception of the response to CMD12 that was issued by setting the STP bit to 1 is completed during the CMD6/CMD38 or CMD25 sequence in HPI mode" "0,1"
newline
rbitfld.quad 0x00 11.--15. "Reserved_11,Reserved bits These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rbitfld.quad 0x00 10. "INFO10,Indicates the SDDAT3 state" "0: SDDAT3 is set to 0,1: SDDAT3 is set to 1"
newline
bitfld.quad 0x00 9. "INFO91,SDDAT3 Card Insertion [Setting condition] After change in SDDAT3 from 0 to 1 two cycles of SDx? have elapsed with SDDAT3 held 1" "0,1"
bitfld.quad 0x00 8. "INFO8,SDDAT3 Card Removal [Setting condition] After change in SDDAT3 from 1 to 0 two cycles of SDx? have elapsed with SDDAT3 held 0" "0,1"
newline
rbitfld.quad 0x00 7. "INFO7,Write Protect Indicates the ISDWP state" "0: ISDWP is set to 1,1: ISDWP is set to 0"
rbitfld.quad 0x00 6. "Reserved_6,Reserved bits These bits are always read as 0" "0,1"
newline
rbitfld.quad 0x00 5. "INFO5,Indicates the ISDCD state" "0: Indicates that Mcycle has elapsed with ISDCD,1: Indicates that Mcycle has elapsed with ISDCD"
bitfld.quad 0x00 4. "INFO4,ISDCD Card Insertion [Setting condition] After change in ISDCD from 1 to 0 Mcycle has elapsed with ISDCD held 0" "0,1"
newline
bitfld.quad 0x00 3. "INFO3,ISDCD Card Removal [Setting condition] After change in ISDCD from 0 to 1 Mcycle has elapsed with ISDCD held 1" "0,1"
bitfld.quad 0x00 2. "INFO2,Access End [Setting conditions] 1" "0,1"
newline
rbitfld.quad 0x00 1. "Reserved_1,Reserved bits These bits are always read as 0" "0,1"
bitfld.quad 0x00 0. "INFO0,Response End [Setting conditions] 1" "0,1"
group.quad 0x78++0x07
line.quad 0x00 "SD_INFO2,The SD card interrupt flag register 2 (SD_INFO2) indicates the access status of the SD buffer (SD_BUF) and SD card"
hexmask.quad.quad 0x00 16.--63. 1. "Reserved_16,Reserved bits These bits are always read as 0"
bitfld.quad 0x00 15. "ILA,Illegal Access Error [Setting conditions] 1" "0,1"
newline
rbitfld.quad 0x00 14. "CBSY,Command Type Register Busy" "0: A command sequence has been completed,1: A command sequence is being executed"
rbitfld.quad 0x00 13. "SCLKDIVEN," "0,1"
newline
rbitfld.quad 0x00 12. "Reserved_12,Reserved bits These bits are always read as 0" "0,1"
bitfld.quad 0x00 11. "Reserved_11,Reserved The write value should always be 1" "0,1"
newline
rbitfld.quad 0x00 10. "Reserved_10,Reserved bits These bits are always read as 0" "0,1"
bitfld.quad 0x00 9. "BWE,SD_BUF Write Enable" "0: Data cannot be written in SD_BUF0,1: Data can be written in SD_BUF0"
newline
bitfld.quad 0x00 8. "BRE,SD_BUF Read Enable" "0: Data cannot be read from SD_BUF0,1: Data can be read from SD_BUF0"
rbitfld.quad 0x00 7. "DAT0,SDDAT0 Indicates the SDDAT0 state" "0: SDDAT0 is set to 0,1: SDDAT0 is set to 1"
newline
bitfld.quad 0x00 6. "ERR6,Response Timeout [Setting condition] When a response is not received though a longer time than 640 cycles of SDCLK have elapsed (including a response to a command issued within a command sequence) [Clearing condition] When 0 is written to ERR6 The.." "0,1"
bitfld.quad 0x00 5. "ERR5,SD_BUF Illegal Read Access [Setting conditions] 1" "0,1"
newline
bitfld.quad 0x00 4. "ERR4,SD_BUF Illegal Write Access [Setting conditions] 1" "0,1"
bitfld.quad 0x00 3. "ERR3,Data Timeout (except response timeout) [Setting conditions] 1" "0,1"
newline
bitfld.quad 0x00 2. "ERR2,END Error [Setting conditions] 1" "0,1"
bitfld.quad 0x00 1. "ERR1,CRC Error [Setting conditions] 1" "0,1"
newline
bitfld.quad 0x00 0. "ERR0,CMD Error [Setting conditions] 1" "0,1"
group.quad 0x80++0x07
line.quad 0x00 "SD_INFO1_MASK,The SD_INFO1 interrupt mask register (SD_INFO1_MASK) is used to enable or disable the SD_INFO1 interrupt"
hexmask.quad.quad 0x00 17.--63. 1. "Reserved_17,Reserved bits These bits are always read as 0"
bitfld.quad 0x00 16. "IMASK16,HPIRES interrupt masked" "0,1"
newline
rbitfld.quad 0x00 10.--15. "Reserved_10,Reserved bits These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.quad 0x00 9. "IMASK9,INFO9 interrupt masked" "0,1"
newline
bitfld.quad 0x00 8. "IMASK8,INFO8 interrupt masked" "0,1"
rbitfld.quad 0x00 5.--7. "Reserved_5,Reserved bits These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 4. "IMASK4,INFO4 interrupt masked" "0,1"
bitfld.quad 0x00 3. "IMASK3,INFO3 interrupt masked" "0,1"
newline
bitfld.quad 0x00 2. "IMASK2,INFO2 interrupt masked" "0,1"
rbitfld.quad 0x00 1. "Reserved_1,Reserved bits These bits are always read as 0" "0,1"
newline
bitfld.quad 0x00 0. "IMASK0,INFO0 interrupt masked" "0,1"
group.quad 0x88++0x07
line.quad 0x00 "SD_INFO2_MASK,The SD_INFO2 interrupt mask register (SD_INFO2_MASK) is used to enable or disable the SD_INFO2 interrupt"
hexmask.quad.quad 0x00 16.--63. 1. "Reserved_16,Reserved bits These bits are always read as 0"
bitfld.quad 0x00 15. "IMASK,ILA interrupt masked" "0,1"
newline
rbitfld.quad 0x00 12.--14. "Reserved_12,Reserved bits These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 11. "Reserved_11,Reserved The write value should always be 1" "0,1"
newline
rbitfld.quad 0x00 10. "Reserved_10,Reserved bits These bits are always read as 0" "0,1"
bitfld.quad 0x00 9. "BMASK1,BWE interrupt masked" "0,1"
newline
bitfld.quad 0x00 8. "BMASK0,BRE interrupt masked" "0,1"
rbitfld.quad 0x00 7. "Reserved_7,Reserved bits These bits are always read as 0" "0,1"
newline
bitfld.quad 0x00 6. "EMASK6,ERR6 interrupt masked" "0,1"
bitfld.quad 0x00 5. "EMASK5,ERR5 interrupt masked" "0,1"
newline
bitfld.quad 0x00 4. "EMASK4,ERR4 interrupt masked" "0,1"
bitfld.quad 0x00 3. "EMASK3,ERR3 interrupt masked" "0,1"
newline
bitfld.quad 0x00 2. "EMASK2,ERR2 interrupt masked" "0,1"
bitfld.quad 0x00 1. "EMASK1,ERR1 interrupt masked" "0,1"
newline
bitfld.quad 0x00 0. "EMASK0,ERR0 interrupt masked" "0,1"
group.quad 0x90++0x07
line.quad 0x00 "SD_CLK_CTRL,The SD clock control register (SD_CLK_CTRL) is used to control the SD clock (SDCLK) output and to set the frequency"
hexmask.quad.quad 0x00 17.--63. 1. "Reserved_17,Reserved bits These bits are always read as 0"
bitfld.quad 0x00 16. "Reserved_16,Reserved The write value should always be 0" "0,1"
newline
rbitfld.quad 0x00 11.--15. "Reserved_11,Reserved bits These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 10. "Reserved_10,Reserved The write value should always be 0" "0,1"
newline
bitfld.quad 0x00 9. "SDCLKOFFEN,SD Clock (SD_CLK) Output Automatic Control Enable" "0: Automatic control for SD clock (SD_CLK) output,1: Automatic control for SD clock (SD_CLK) output"
bitfld.quad 0x00 8. "SCLKEN,SD Clock (SD_CLK) Output Control Enable" "0: SD clock (SD_CLK) output is disabled,1: SD clock (SD_CLK) output is enabled"
newline
bitfld.quad 0x00 7. "DIV7,SD Clock (SD_CLK) {DIV7 DIV6 DIV5 DIV4 DIV3 DIV2 DIV1 DIV0} B'1000" "0: SD?/2 B'1111,1: SD?/4 B'0000"
bitfld.quad 0x00 6. "DIV6,Refer to DIV7 Bit Description" "0,1"
newline
bitfld.quad 0x00 5. "DIV5,Refer to DIV7 Bit Description" "0,1"
bitfld.quad 0x00 4. "DIV4,Refer to DIV7 Bit Description" "0,1"
newline
bitfld.quad 0x00 3. "DIV3,Refer to DIV7 Bit Description" "0,1"
bitfld.quad 0x00 2. "DIV2,Refer to DIV7 Bit Description" "0,1"
newline
bitfld.quad 0x00 1. "DIV1,Refer to DIV7 Bit Description" "0,1"
bitfld.quad 0x00 0. "DIV0,Refer to DIV7 Bit Description" "0,1"
group.quad 0x98++0x07
line.quad 0x00 "SD_SIZE,The transfer data length register (SD_SIZE) is used to specify the transfer data size"
hexmask.quad.quad 0x00 12.--63. 1. "Reserved_12,Reserved bits These bits are always read as 0"
rbitfld.quad 0x00 10.--11. "Reserved_10,Reserved" "0,1,2,3"
newline
hexmask.quad.word 0x00 0.--9. 1. "LEN_9_0,Transfer Data Size These bits specify a size between 1 and 512 bytes for single block transfer"
group.quad 0xA0++0x07
line.quad 0x00 "SD_OPTION,The SD card access control option register (SD_OPTION) is used to set the bus width and timeout counter"
hexmask.quad.quad 0x00 16.--63. 1. "Reserved_16,Reserved bits These bits are always read as 0"
bitfld.quad 0x00 15. "WIDTH,Bus width {WIDTH WIDTH8} =" "0: 4-bit width {WIDTH WIDTH8} = 10,1: 8-bit width {WIDTH WIDTH8} ="
newline
rbitfld.quad 0x00 14. "Reserved_14,Reserved bits These bits are always read as 1" "0,1"
bitfld.quad 0x00 13. "WIDTH8,Bus width See the description of the WIDTH bit" "0,1"
newline
rbitfld.quad 0x00 10.--12. "Reserved_10,Reserved bits These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 9. "EXTOP,Timeout Mode Select" "0: Bits TOP27 to TOP24 specify the timeout count,1: Bits TOP27 to TOP24 specify the timeout count"
newline
bitfld.quad 0x00 8. "TOUTMASK,Timeout Mask" "0: Enables timeout,1: Disables timeout"
bitfld.quad 0x00 7. "TOP27,Timeout Counter {TOP27 TOP26 TOP25 TOP24}" "0: SDCLK*213,1: SDCLK*214"
newline
bitfld.quad 0x00 6. "TOP26,Refer to TOP27 Bit Description" "0,1"
bitfld.quad 0x00 5. "TOP25,Refer to TOP27 Bit Description" "0,1"
newline
bitfld.quad 0x00 4. "TOP24,Refer to TOP27 Bit Description" "0,1"
bitfld.quad 0x00 3. "CTOP24,Card Detect Time Counter {CTOP24 CTOP23 CTOP22 CTOP21}" "0: SD? *210,1: SD? *211"
newline
bitfld.quad 0x00 2. "CTOP23,Refer to CTOP24 Bit Description" "0,1"
bitfld.quad 0x00 1. "CTOP22,Refer to CTOP24 Bit Description" "0,1"
newline
bitfld.quad 0x00 0. "CTOP21,Refer to CTOP24 Bit Description" "0,1"
group.quad 0xB0++0x07
line.quad 0x00 "SD_ERR_STS1,The SD error status register 1 (SD_ERR_STS1) indicates the CRC status CRC error End error and CMD error"
hexmask.quad.quad 0x00 15.--63. 1. "Reserved_15,Reserved bits These bits are always read as 0"
rbitfld.quad 0x00 14. "E14,These bits hold the CRC status" "0,1"
newline
rbitfld.quad 0x00 13. "E13,Refer to E14 Bit Description" "0,1"
rbitfld.quad 0x00 12. "E12,Refer to E14 Bit Description" "0,1"
newline
rbitfld.quad 0x00 11. "E11,Set to 1 when an error occurs in the CRC status" "0,1"
rbitfld.quad 0x00 10. "E10,Set to 1 when a CRC error occurs in the read data" "0,1"
newline
rbitfld.quad 0x00 9. "E9,Set to 1 when a CRC error occurs in the response to a command issued within a command sequence" "0,1"
rbitfld.quad 0x00 8. "E8,Set to 1 when a CRC error occurs in a response (other than a response to a command issued within a command sequence)" "0,1"
newline
rbitfld.quad 0x00 6.--7. "Reserved_6,Reserved bits These bits are always read as 0" "0,1,2,3"
rbitfld.quad 0x00 5. "E5,Set to 1 when an error occurs in the CRC status length (and the end bit has not been detected)" "0,1"
newline
rbitfld.quad 0x00 4. "E4,Set to 1 when an error occurs in the read data length (and the end bit has not been detected among the valid bits)" "0,1"
rbitfld.quad 0x00 3. "E3,Set to 1 when an error occurs in the response length to a command issued within a command sequence" "0,1"
newline
rbitfld.quad 0x00 2. "E2,Set to 1 when an error occurs in the response length (other than a response to a command issued within a command sequence)" "0,1"
rbitfld.quad 0x00 1. "E1,Set to 1 when an error occurs in the command index of the response to a command issued within a command sequence" "0,1"
newline
rbitfld.quad 0x00 0. "E0,Set to 1 when an error occurs in the command index of a response (other than a response to a command issued within a command sequence)" "0,1"
group.quad 0xB8++0x07
line.quad 0x00 "SD_ERR_STS2,The SD error status register 2 (SD_ERR_STS2) indicates the timeout state"
hexmask.quad 0x00 7.--63. 1. "Reserved_7,Reserved bits These bits are always read as 0"
rbitfld.quad 0x00 6. "E6,Set to 1 when the busy state continues for longer than Ncycle after the CRC status Note:The initial value is applied at a reset and when the SDRST bit in SOFT_RST is 0" "0,1"
newline
rbitfld.quad 0x00 5. "E5,Set to 1 when the CRC status is not received though a longer time than Ncycle has elapsed after data writing Note:The initial value is applied at a reset and when the SDRST bit in SOFT_RST is 0" "0,1"
rbitfld.quad 0x00 4. "E4,Set to 1 when read data is not received though a longer time than Ncycle has elapsed after read command" "0,1"
newline
rbitfld.quad 0x00 3. "E3,Set to 1 when the busy state for longer than Ncycle continues after CMD12 has been issued within a command sequence" "0,1"
rbitfld.quad 0x00 2. "E2,Set to 1 when the busy state for longer than Ncycle continues after R1b response" "0,1"
newline
rbitfld.quad 0x00 1. "E1,Set to 1 when the response to a command issued within a command sequence is not received though a longer time than 640 cycles of SDCLK have elapsed" "0,1"
rbitfld.quad 0x00 0. "E0,Set to 1 when the response (other than a response to a command issued within a command sequence) is not received though a longer time than 640 cycles of SDCLK have elapsed" "0,1"
group.quad 0xC0++0x07
line.quad 0x00 "SD_BUF0,When using the DMAC the bus width should be fixed at 64 bits"
hexmask.quad 0x00 0.--63. 1. "BUF_63_0,When writing to the SD card the write data is written to this register"
group.quad 0xD0++0x07
line.quad 0x00 "SDIO_MODE,The SDIO mode control register (SDIO_MODE) controls the CMD52 issuance and the read wait state at multiple block transfer and the reception of SDIO interrupt"
hexmask.quad.quad 0x00 10.--63. 1. "Reserved_10,Reserved bits These bits are always read as 0"
bitfld.quad 0x00 9. "C52PUB,SDIO None Abort When C52PUB is set to 1 in the CMD53 (multiple block) write sequence CMD52 is automatically issued between blocks if SD_BUF becomes empty.C52PUB is automatically cleared to 0 after reception of the response to CMD52 is completed" "0,1"
newline
bitfld.quad 0x00 8. "IOABT,SDIO Abort When IOABT is set to 1 in the CMD53 (multiple block) sequence the CMD53 sequence is halted and CMD52 is issued" "0,1"
rbitfld.quad 0x00 3.--7. "Reserved_3,Reserved bits These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 2. "RWREQ,Read Wait Request When RWREQ is set to 1 in the CMD53 (multiple block) read sequence the block transfer enters the read wait state between blocks" "0,1"
rbitfld.quad 0x00 1. "Reserved_1,Reserved bits These bits are always read as 0" "0,1"
newline
bitfld.quad 0x00 0. "IOMOD,SDIO Mode" "0: Disables the SD host interface to receive SDIO,1: Enables the SD host interface to receive SDIO"
group.quad 0xD8++0x07
line.quad 0x00 "SDIO_INFO1,The SDIO interrupt flag register (SDIO_INFO1) indicates the status regarding to the SDIO card access"
hexmask.quad.quad 0x00 16.--63. 1. "Reserved_16,Reserved bits These bits are always read as 0"
bitfld.quad 0x00 15. "EXWT,[Setting condition] While the last block in the CMD53 (multiple block) read sequence is transferred RWREQ in SDIO_MODE is set to 1" "0,1"
newline
bitfld.quad 0x00 14. "EXPUB52,[Setting conditions] 1" "0,1"
hexmask.quad.word 0x00 3.--13. 1. "Reserved_3,Reserved bits These bits are always read as 0"
newline
bitfld.quad 0x00 1.--2. "Reserved_1,Reserved The write value should always be 1" "0,1,2,3"
bitfld.quad 0x00 0. "IOIRQ,[Setting condition] When SDIO interrupt from an SDIO card is received while IOMOD in SDIO_MODE is set to 1" "0,1"
group.quad 0xE0++0x07
line.quad 0x00 "SDIO_INFO1_MASK,The SDIO_INFO1 interrupt mask register (SDIO_INFO1_MASK) enables or disables the SD_INFO1 interrupt"
hexmask.quad.quad 0x00 16.--63. 1. "Reserved_16,Reserved bits These bits are always read as 0"
bitfld.quad 0x00 15. "MEXWT,EXWT interrupt masked" "0,1"
newline
bitfld.quad 0x00 14. "MEXPUB52,EXPUB52 interrupt masked" "0,1"
hexmask.quad.word 0x00 3.--13. 1. "Reserved_3,Reserved bits These bits are always read as 0"
newline
bitfld.quad 0x00 2. "Reserved_2,Reserved The write value should always be 1" "0,1"
bitfld.quad 0x00 1. "Reserved_1,Reserved The write value should always be 1" "0,1"
newline
bitfld.quad 0x00 0. "IOMSK,IOIRQ interrupt masked" "0,1"
group.quad 0x360++0x07
line.quad 0x00 "CC_EXT_MODE,The DMA mode enable register (CC_EXT_MODE) enables the DMA transfer"
hexmask.quad.quad 0x00 13.--63. 1. "Reserved_13,Reserved bits These bits are always read as 0"
rbitfld.quad 0x00 12. "Reserved_12,Reserved bits These bits are always read as 1" "0,1"
newline
rbitfld.quad 0x00 10.--11. "Reserved_10,Reserved bits These bits are always read as 0" "0,1,2,3"
bitfld.quad 0x00 8.--9. "Reserved_8,Reserved The write value should always be 0" "0,1,2,3"
newline
rbitfld.quad 0x00 6.--7. "Reserved_6,Reserved bits These bits are always read as 0" "0,1,2,3"
bitfld.quad 0x00 5. "Reserved_5,Reserved The write value should always be 0" "0,1"
newline
rbitfld.quad 0x00 4. "Reserved_4,Reserved bits These bits are always read as 1" "0,1"
rbitfld.quad 0x00 2.--3. "Reserved_2,Reserved bits These bits are always read as 0" "0,1,2,3"
newline
bitfld.quad 0x00 1. "DMASDRW,SD_BUF Read/Write DMA Transfer" "0: The SD_BUF read/write DMA transfer is disabled,1: The SD_BUF read/write DMA transfer is enabled"
bitfld.quad 0x00 0. "Reserved_0,Reserved The write value should always be 0" "0,1"
group.quad 0x380++0x07
line.quad 0x00 "SOFT_RST,The software reset register (SOFT_RST) sets a software reset"
hexmask.quad 0x00 3.--63. 1. "Reserved_3,Reserved bits These bits are always read as 0"
rbitfld.quad 0x00 2. "Reserved_2,Reserved bits These bits are always read as 1" "0,1"
newline
rbitfld.quad 0x00 1. "Reserved_1,Reserved bits These bits are always read as 1" "0,1"
bitfld.quad 0x00 0. "SDRST,Software Reset of SD Interface Unit" "0: Reset,1: Reset released"
group.quad 0x388++0x07
line.quad 0x00 "VERSION,The version register (VERSION) indicates the version of the SD host interface"
hexmask.quad.quad 0x00 16.--63. 1. "Reserved_16,Reserved bits These bits are always read as 0"
rbitfld.quad 0x00 15. "UR_7,Reserved bits These bits are always read as 1" "0,1"
newline
rbitfld.quad 0x00 14. "UR_6,Reserved bits These bits are always read as 1" "0,1"
rbitfld.quad 0x00 12.--13. "UR_5_4,Reserved bits These bits are always read as 0" "0,1,2,3"
newline
rbitfld.quad 0x00 8.--11. "UR_3_0,Version of Renesas IP Channels 0 and" "?,1: H'C,?,3: H'D,?..."
hexmask.quad.byte 0x00 0.--7. 1. "IP_7_0,Version of introductory IP"
group.quad 0x390++0x07
line.quad 0x00 "HOST_MODE,The host interface mode setting register (HOST_MODE) selects the width for access to the data bus"
hexmask.quad.quad 0x00 9.--63. 1. "Reserved_9,Reserved bits These bits are always read as 0"
bitfld.quad 0x00 8. "BUSWIDTH,Width for Access to SD_BUF Read or write access to SD_BUF0 can be performed with the specified width for access" "0: 16-bit access,1: 32-bit access This bit is enabled"
newline
rbitfld.quad 0x00 2.--7. "Reserved_2,Reserved bits These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.quad 0x00 1. "ENDIAN,SD_BUF0 data swap" "0,1"
newline
bitfld.quad 0x00 0. "WMODE,Width for Access to SD_BUF Read or write access to SD_BUF0 can be performed with the specified width for access" "0: 64-bit access,1: 16-bit or 32-bit access"
group.quad 0x398++0x07
line.quad 0x00 "SDIF_MODE,The SD interface mode setting register (SDIF_MODE) specifies HS400 mode"
hexmask.quad.quad 0x00 10.--63. 1. "Reserved_10,Reserved bits These bits are always read as 0"
bitfld.quad 0x00 9. "Reserved_9,Reserved The write value should always be 0" "0,1"
newline
bitfld.quad 0x00 8. "NOCHKCR,CRC Check Mask (test command for MMC supported) Enables or disables checking of the CRC16 and CRC status" "0: Enables the CRC check,1: Disables the CRC check (the CRC16 value is"
hexmask.quad.byte 0x00 1.--7. 1. "Reserved_1,Reserved bits These bits are always read as 0"
newline
bitfld.quad 0x00 0. "HS400,HS400 Mode Select*2" "0: Normal mode (default high speed or SDR),1: HS400 mode (DDR mode) Set this bit to 0 when.."
group.quad 0x800++0x07
line.quad 0x00 "DM_CM_SEQ_REGSET,This register indicates a DMAC(SEQ) context table setting register"
hexmask.quad.quad 0x00 9.--63. 1. "Reserved_9,Reserved bits These bits are always read as 0"
bitfld.quad 0x00 8. "TABLE_NUM,Sequencer Table number" "0: sequencer table 0,1: sequencer table 1 Software sets the number of"
newline
rbitfld.quad 0x00 2.--7. "Reserved_2,Reserved bits These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.quad 0x00 0.--1. "CTXT_NUM,Context number (0~3) Software sets the number of context storing the value of DM_SEQ_***" "0,1,2,3"
group.quad 0x810++0x07
line.quad 0x00 "DM_CM_SEQ_CTRL,This register indicates a DMAC(SEQ) control register"
hexmask.quad.quad 0x00 29.--63. 1. "Reserved_29,Reserved bits These bits are always read as 0"
bitfld.quad 0x00 28. "SEQ_TABLE,This bit indicates sequencer table number for queuing command" "0,1"
newline
rbitfld.quad 0x00 25.--27. "Reserved_25,Reserved bits These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 24. "T_NUM,Maximum Table number for SDmultiple command stack This bit indicates the maximum number of sequencer table (SEQ_TYPE=01/10)" "0,1"
newline
rbitfld.quad 0x00 18.--23. "Reserved_18,Reserved bits These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.quad 0x00 16.--17. "SEQ_TYPE,Sequencer mode selector" "0: Not use Sequencer,1: SD multiple,2: ,3: "
newline
rbitfld.quad 0x00 14.--15. "Reserved_14,Reserved bits These bits are always read as 0" "0,1,2,3"
bitfld.quad 0x00 12.--13. "START_NUM,These bits indicate start number of context for queuing command (0-3)" "0,1,2,3"
newline
rbitfld.quad 0x00 10.--11. "Reserved_10,Reserved bits These bits are always read as 0" "0,1,2,3"
bitfld.quad 0x00 8.--9. "END_NUM,These bits indicate end number of context for queuing command (0-3)" "0,1,2,3"
newline
rbitfld.quad 0x00 7. "Reserved_7,Reserved bits These bits are always read as 0" "0,1"
bitfld.quad 0x00 6. "PRIORITY_MODE,Priority control mode selector for SD multiple command stack *1" "0: SDIP executes in order from table0 to table1,1: SDIP executes in order of priority (table1 is"
newline
rbitfld.quad 0x00 4.--5. "Reserved_4,Reserved bits These bits are always read as 0" "0,1,2,3"
bitfld.quad 0x00 3. "SEQ_SUSPEND,This bit triggers to suspend sequencer process SDIP clears this bit automatically when SDIP goes to suspend mode or DM_CM_INFO1.SEQEND interrupt is occured" "0,1"
newline
bitfld.quad 0x00 2. "SEQ_RESUME,This bit triggers to resume sequencer process SDIP clears this bit automatically when SDIP recovers from suspend mode" "0,1"
rbitfld.quad 0x00 1. "Reserved_1,Reserved bits These bits are always read as 0" "0,1"
newline
bitfld.quad 0x00 0. "SEQ_START,This bit triggers to queuing command" "0,1"
group.quad 0x820++0x07
line.quad 0x00 "DM_CM_DTRAN_MODE,This register indicates a DMAC(DTRAN) mode select register.High 32 bits (bit 63-32) are read only 0"
hexmask.quad.quad 0x00 18.--63. 1. "Reserved_18,Reserved bits These bits are always read as 0"
bitfld.quad 0x00 16.--17. "CH_NUM,DMAC channel selector 00?: SD down stream" "0: SD down stream,1: SD up stream 10,?,3: Don't set"
newline
hexmask.quad.word 0x00 6.--15. 1. "Reserved_6,Reserved bits These bits are always read as 0"
bitfld.quad 0x00 4.--5. "BUS_WIDTH,Bus width selector" "0: ,1: ,2: ,3: "
newline
rbitfld.quad 0x00 1.--3. "Reserved_1,Reserved bits These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 0. "ADDR_MODE,System address mode selector" "0: fixed address,1: address increment These bits are"
group.quad 0x828++0x07
line.quad 0x00 "DM_CM_DTRAN_CTRL,This register indicates a DMAC(DTRAN) control register"
hexmask.quad.quad 0x00 9.--63. 1. "Reserved_9,Reserved bits These bits are always read as 0"
bitfld.quad 0x00 8. "Reserved_8,Reserved The write value should always be 0" "0,1"
newline
hexmask.quad.byte 0x00 1.--7. 1. "Reserved_1,Reserved bits These bits are always read as 0"
bitfld.quad 0x00 0. "DM_START,DMAC Start Writing 1 to this bit starts DMAC operation" "0,1"
group.quad 0x830++0x07
line.quad 0x00 "DM_CM_RST,High 32 bits (bit 63-32) are read only 0"
hexmask.quad.quad 0x00 10.--63. 1. "Reserved_10,Reserved bits These bits are always read as 1"
bitfld.quad 0x00 8.--9. "DTRANRST,When software sets this bit to 0 SDIP executes soft reset to control FF of each channel" "0,1,2,3"
newline
hexmask.quad.byte 0x00 1.--7. 1. "Reserved_1,Reserved bits These bits are always read as 1"
bitfld.quad 0x00 0. "SEQRST,When software sets this bit to 0 SDIP executes soft reset to control FF of sequencer" "0,1"
group.quad 0x840++0x07
line.quad 0x00 "DM_CM_INFO1,The DMAC interrupt register 1 (DM_CM_INFO1) indicates the status of DMAC and a sequencer"
hexmask.quad.quad 0x00 21.--63. 1. "Reserved_21,Reserved bits These bits are always read as 0"
bitfld.quad 0x00 20. "DTRANEND1,DMAC Channel 1 Transfer End [Setting conditions] 1" "0,1"
newline
rbitfld.quad 0x00 18.--19. "Reserved_18,Reserved bits These bits are always read as 0" "0,1,2,3"
bitfld.quad 0x00 17. "Reserved_17,Reserved The write value should always be 0" "0,1"
newline
bitfld.quad 0x00 16. "DTRANEND0,DMAC Channel 0 Transfer End [Setting conditions] 1" "0,1"
hexmask.quad.byte 0x00 9.--15. 1. "Reserved_9,Reserved bits These bits are always read as 0"
newline
bitfld.quad 0x00 8. "SEQSUSPEND,Interrupt of command sequencer process suspend This bit is asserted when SDIP goes to suspend mode by DM_CM_CTRL.SEQ_SUSPEND at DM_CM_SEQ_CTRL.SEQ_TYPE = 01/10" "0,1"
hexmask.quad.byte 0x00 1.--7. 1. "Reserved_1,Reserved bits These bits are always read as 0"
newline
bitfld.quad 0x00 0. "SEQEND,Sequencer Operation End [Setting conditions] 1" "0,1"
group.quad 0x848++0x07
line.quad 0x00 "DM_CM_INFO1_MASK,The DM_CM_INFO1 interrupt mask register (DM_CM_INFO1_MASK) enables or disables the DM_CM_INFO1 interrupt"
hexmask.quad.long 0x00 32.--63. 1. "Reserved_32,Reserved bits These bits are always read as 0"
hexmask.quad.word 0x00 21.--31. 1. "Reserved_21,Reserved bits These bits are always read as 1"
newline
bitfld.quad 0x00 20. "DTRANEND1_MASK,DTRANEND1 interrupt masked" "0,1"
bitfld.quad 0x00 18.--19. "Reserved_18,Reserved The write value should always be 1" "0,1,2,3"
newline
bitfld.quad 0x00 17. "Reserved_17,Reserved The write value should always be 1" "0,1"
bitfld.quad 0x00 16. "DTRANEND0_MASK,DTRANEND0 interrupt masked" "0,1"
newline
hexmask.quad.byte 0x00 9.--15. 1. "Reserved_9,Reserved bits These bits are always read as 1"
bitfld.quad 0x00 8. "SEQSUSPEND_MASK,Interrupt mask for DM_CM_INFO1.SEQSUSPEND" "0,1"
newline
hexmask.quad.byte 0x00 1.--7. 1. "Reserved_1,Reserved bits These bits are always read as 1"
bitfld.quad 0x00 0. "SEQEND_MASK,SEQEND interrupt masked" "0,1"
group.quad 0x850++0x07
line.quad 0x00 "DM_CM_INFO2,The DMAC interrupt register 2 (DM_CM_INFO2) indicates the status of DMAC and a sequencer"
hexmask.quad.quad 0x00 20.--63. 1. "Reserved_20,Reserved bits These bits are always read as 0"
rbitfld.quad 0x00 18.--19. "Reserved_18,Reserved The write value should always be 0" "0,1,2,3"
newline
bitfld.quad 0x00 17. "DTRANERR1,DMAC Channel 1 Error [Setting condition] When an error occurs on DMAC channel 1 [Clearing condition] When 0 is written to DTRANERR1 Note:The initial value is applied at a reset and when the DTRANRST1 bit in DM_CM_RST is 0" "0,1"
bitfld.quad 0x00 16. "DTRANERR0,DMAC Channel 0 Error [Setting condition] When an error occurs on the DMAC channel 0 [Clearing condition] When 0 is written to DTRANERR0 Note:The initial value is applied at a reset and when the DTRANRST0 bit in DM_CM_RST is 0" "0,1"
newline
hexmask.quad.word 0x00 1.--15. 1. "Reserved_1,Reserved bits These bits are always read as 0"
bitfld.quad 0x00 0. "SEQERR,Sequencer error [Setting condition] When a sequencer error occurs [Clearing condition] When 0 is written to SEQERR Note:The initial value is applied at a reset and when the SEQRST bit in DM_CM_RST is 0" "0,1"
group.quad 0x858++0x07
line.quad 0x00 "DM_CM_INFO2_MASK,The DM_CM_INFO2 interrupt mask register (DM_CM_INFO2_MASK) enables or disables the DM_CM_INFO2 interrupt"
hexmask.quad.long 0x00 32.--63. 1. "Reserved_32,Reserved bits These bits are always read as 0"
hexmask.quad.word 0x00 20.--31. 1. "Reserved_20,Reserved bits These bits are always read as 1 The write value should always be 1"
newline
rbitfld.quad 0x00 18.--19. "Reserved_18,Reserved The write value should always be 1" "0,1,2,3"
bitfld.quad 0x00 17. "DTRANERR1_MASK,DTRANERR1 interrupt masked" "0,1"
newline
bitfld.quad 0x00 16. "DTRANERR0_MASK,DTRANERR0 interrupt masked" "0,1"
hexmask.quad.word 0x00 1.--15. 1. "Reserved_1,Reserved bits These bits are always read as 1"
newline
bitfld.quad 0x00 0. "SEQERR_MASK,SEQERR interrupt masked" "0,1"
group.quad 0x868++0x07
line.quad 0x00 "DM_CM_SEQ_STAT,This register outputs the status register of sequencer process"
hexmask.quad 0x00 2.--63. 1. "Reserved_2,Reserved bits These bits are always read as 0"
bitfld.quad 0x00 0.--1. "SEQTBSTS,busy flag of sequencer process These bits indicate that sequencer process is busy or not for each table (SEQTBSTS[1 :0]={table1 table0})" "0: not busy,1: busy,?..."
group.quad 0x880++0x07
line.quad 0x00 "DM_DTRAN_ADDR,This register indicates system memory address(forwarding/source)"
hexmask.quad.long 0x00 32.--63. 1. "Reserved_32,Reserved bits These bits are always read as 0"
hexmask.quad.long 0x00 7.--31. 1. "DADDR,destination address / source address (128 byte unit) Note that the value of DM_DTRAN_ADDR + transfer data length (more detail refer to chapter 5) is less than or equal to 2^32"
newline
hexmask.quad.byte 0x00 0.--6. 1. "Reserved_0,Reserved bits These bits are always read as 0"
group.quad 0x8A0++0x07
line.quad 0x00 "DM_SEQ_CMD,This register indicates a command controller register for sequencer in DM_CM_SEQ_CTRL.SEQ_TYEP=01"
hexmask.quad.quad 0x00 17.--63. 1. "Reserved_17,Reserved bits These bits are always read as 0"
bitfld.quad 0x00 16. "PRIORITY_MASK,Priority Mask for SD multiple command stack When software sets this bit to 1 SDIP goes to high priority sequencer table after current context is completed" "0,1"
newline
rbitfld.quad 0x00 14.--15. "Reserved_14,Reserved bits These bits are always read as 0" "0,1,2,3"
bitfld.quad 0x00 13. "MULTI,Selects Single or Multiple block transfer" "0: single block transfer ( byte mode ),1: multiple block transfer ( block mode )"
newline
bitfld.quad 0x00 12. "DIO,Selects Write or Read transfer" "0: write transfer,1: read transfer"
bitfld.quad 0x00 11. "CMDTYP,Selects the command with data or without data" "0: without data,1: with data"
newline
bitfld.quad 0x00 8.--10. "RESTYP,Response Type These bits select Response type as shown below" "0: Not Specified,?,?,3: No Response,4: R1 R5 R6 R7,5: R1b R5b,6: R2,7: R3 R4 Others"
bitfld.quad 0x00 7. "NONAUTOSTP,UHS-I only" "0: issue Auto CMD12,1: not issue Auto CMD12"
newline
bitfld.quad 0x00 6. "APP,indicator for application command" "0: regular command,1: application command"
bitfld.quad 0x00 0.--5. "INDEX,Command Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.quad 0x8A8++0x07
line.quad 0x00 "DM_SEQ_ARG,This register indicates a command argument register for sequencer in DM_CM_SEQ_CTRL.SEQ_TYPE=01"
hexmask.quad.long 0x00 32.--63. 1. "Reserved_32,Reserved bits These bits are always read as 0"
hexmask.quad.long 0x00 0.--31. 1. "ARG,command argument"
group.quad 0x8B0++0x07
line.quad 0x00 "DM_SEQ_SIZE,This register indicates the number of bytes per sector register for sequencer in DM_CM_SEQ_CTRL.SEQ_TYPE=01"
hexmask.quad.long 0x00 32.--63. 1. "Reserved_32,Reserved bits These bits are always read as 0"
hexmask.quad.long 0x00 0.--31. 1. "SIZE,Number of bytes per sector (byte unit) Set the value which is equal to or more than 8 and a power-of-two to this register at DM_SEQ_CMD.MULTI=1"
group.quad 0x8B8++0x07
line.quad 0x00 "DM_SEQ_SECCNT,This register indicates the number of sector counts register for sequencer in DM_CM_SEQ_CTRL.SEQ_TYPE=01"
hexmask.quad.long 0x00 32.--63. 1. "Reserved_32,Reserved bits These bits are always read as 0"
hexmask.quad.long 0x00 0.--31. 1. "CNT,The number of sector counts This register is invalid at DM_SEQ_CMD.MULTI=0"
group.quad 0x8C0++0x07
line.quad 0x00 "DM_SEQ_RSP,This register indicates the expected value of argument of command response for sequencer in DM_CM_SEQ_CTRL.SEQ_TYPE=01"
hexmask.quad.long 0x00 32.--63. 1. "Reserved_32,Reserved bits These bits are always read as 0"
hexmask.quad.long 0x00 0.--31. 1. "RSP,The expected value for the argument of response"
group.quad 0x8C8++0x07
line.quad 0x00 "DM_SEQ_RSP_CHK,This register indicates the bit of comparing expected value of argument of command response for sequencer in DM_CM_SEQ_CTRL.SEQ_TYPE=01"
hexmask.quad.long 0x00 32.--63. 1. "Reserved_32,Reserved bits These bits are always read as 0"
abitfld.quad 0x00 0.--31. "RSP_CHK,This register indicates the bit which performs comparison with expected value for the argument of response" "0x00000000=0: SDIP does not compare,0x00000001=1: SDIP compares DM_SEQ_RSP and.."
group.quad 0x8D0++0x07
line.quad 0x00 "DM_SEQ_ADDR,This register indicates system memory address (forwarding/source) for sequencer in DM_CM_SEQ_CTRL.SEQ_TYPE=01"
hexmask.quad.long 0x00 32.--63. 1. "Reserved_32,Reserved bits These bits are always read as 0"
hexmask.quad.long 0x00 7.--31. 1. "SADDR,destination address / source address (128 byte unit) Note that the value of DM_SEQ_ADDR + transfer data length (more detail refer to chapter 5) is less than 2^32"
newline
hexmask.quad.byte 0x00 0.--6. 1. "Reserved_0,Reserved bits These bits are always read as 0"
tree.end
tree "SDHI_MMC_INST_1"
base ad:0xEE141000
group.long 0x00++0x03
line.long 0x00 "SCC_DTCNTL,"
hexmask.long.byte 0x00 24.--31. 1. "Reserved_24,Reserved bits These bits are always read as 0"
hexmask.long.byte 0x00 16.--23. 1. "TAPNUM_7_0,SCC Sampling Clock Selection Width When the SD clock frequency obtained by setting DIV7 to DIV0 in the SD_CLK_CTRL register to 0xFF (1:1 mode) is 200 MHz set these bits to H08"
newline
hexmask.long.word 0x00 1.--15. 1. "Reserved_1,Reserved bits These bits are always read as 0"
bitfld.long 0x00 0. "TAPEN,SCC Sampling Clock Operation Enable" "0: SCC sampling clock operation is disabled,1: SCC sampling clock operation is enabled"
group.long 0x08++0x03
line.long 0x00 "SCC_TAPSET,"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved bits These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "TAPSET_7_0,SCC Sampling Clock Position ? Set the tuning result in the range from 0 to TAPNUM-1"
group.long 0x10++0x03
line.long 0x00 "SCC_DT2FF,This register makes a setting that SD_DATA which has been fetched by the sampling clock at each TAP position is used in the appropriate timing"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved bits These bits are always read as 0"
hexmask.long.byte 0x00 8.--15. 1. "DT2NESET_7_0,Hardware Adjustment 1 The following is the recommended setting value for each SD_CLK frequency"
newline
hexmask.long.byte 0x00 0.--7. 1. "DT2NSSET_7_0,Hardware Adjustment 2 The following is the recommended setting value for each SD_CLK frequency"
group.long 0x18++0x03
line.long 0x00 "SCC_CKSEL,"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved bits These bits are always read as 0"
bitfld.long 0x00 0. "DTSEL,Sampling Clock Selection" "0: An SCC sampling clock is not used (SDR104),1: An SCC sampling clock is used (SDR104)"
group.long 0x20++0x03
line.long 0x00 "SCC_RVSCNTL,"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved bits These bits are always read as 0"
hexmask.long.byte 0x00 8.--15. 1. "TAPSEL_7_0,SCC Sampling Clock Position Display. Displays the SCC sampling clock position selected by hardware"
newline
rbitfld.long 0x00 2.--7. "Reserved_2,Reserved bits These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 1. "RVSW,This bit is read as 0" "0,1"
newline
bitfld.long 0x00 0. "RVSEN,SCC Sampling Clock Position Correction Enable" "0: SCC sampling clock position correction is..,1: SCC sampling clock position correction is.."
group.long 0x28++0x03
line.long 0x00 "SCC_RVSREQ,"
hexmask.long 0x00 3.--31. 1. "Reserved_3,Reserved bits These bits are always read as 0"
bitfld.long 0x00 2. "RVSERR,SCC Sampling Clock Position Correction Error" "0: There is no correction error,1: There is a correction error"
newline
bitfld.long 0x00 1. "REQTAPUP,SCC Sampling Clock Position Positive Direction Correction Request" "0: There is no correction request,1: There is a correction request"
bitfld.long 0x00 0. "REQTAPDWN,SCC Sampling Clock Position Negative Direction Correction Request" "0: There is no correction request,1: There is a correction request"
group.long 0x30++0x03
line.long 0x00 "SCC_SMPCMP,Data comparison register indicates the result of the comparison of the sampling data"
hexmask.long.byte 0x00 25.--31. 1. "Reserved_25,Reserved bits These bits are always read as 0"
abitfld.long 0x00 16.--24. "CMPNGU,Comparison of sampling data with the previous TAP Clock" "0x000=0: Match,0x001=1: Mismatch <"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved_9,Reserved bits These bits are always read as 0"
abitfld.long 0x00 0.--8. "CMPNGD,Comparison of sampling data with the after TAP Clock" "0x000=0: Match,0x001=1: Mismatch <"
group.long 0x38++0x03
line.long 0x00 "SCC_TMPPORT2,"
bitfld.long 0x00 31. "HS400EN,Set this bit to 1 to select operation of this module in HS400 mode" "0: Disables HS400 mode,1: Enables HS400 mode"
hexmask.long 0x00 5.--30. 1. "Reserved_5,Reserved bits These bits are always read as 0"
newline
bitfld.long 0x00 4. "HS400OSEL,Set this bit to 1 to select operation of this module in HS400 mode" "0: Disables HS400 data output timing,1: Enables HS400 data output timing"
rbitfld.long 0x00 0.--3. "Reserved_0,Reserved bits These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x50++0x03
line.long 0x00 "SCC_TMPPORT3,"
hexmask.long 0x00 2.--31. 1. "Reserved_2,Reserved bits These bits are always read as 0"
bitfld.long 0x00 0.--1. "ofsel_1_0,Select offset value of 90 degree phase shifter for HS4000: Match 00 min (offset=3) 11 max (offset=0)" "0,1,2,3"
group.long 0x58++0x03
line.long 0x00 "SCC_TMPPORT4,"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved bits These bits are always read as 0"
bitfld.long 0x00 0. "dll_acc_start,DLL(90 degree phase shifter) register Access Start 0 register access stop 1 register access start" "0,1"
group.long 0x60++0x03
line.long 0x00 "SCC_TMPPORT5,"
hexmask.long.tbyte 0x00 9.--31. 1. "Reserved_9,Reserved bits These bits are always read as 0"
bitfld.long 0x00 8. "dll_rw_sel,DLL(90 degree phase shifter) register read/write select 0 Write 1 Read" "0,1"
newline
rbitfld.long 0x00 6.--7. "Reserved_6,Reserved bits These bits are always read as 0" "0,1,2,3"
bitfld.long 0x00 0.--5. "dll_addr_5_0,DLL(90 degree phase shifter) register address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x68++0x03
line.long 0x00 "SCC_TMPPORT6,"
hexmask.long 0x00 0.--31. 1. "dll_wdata_31_0,DLL(90 degree phase shifter) register write data"
group.long 0x70++0x03
line.long 0x00 "SCC_TMPPORT7,"
hexmask.long 0x00 0.--31. 1. "dll_rdata_31_0,DLL(90 degree phase shifter) register read data"
tree.end
tree.end
tree "UFS"
base ad:0xE6860000
group.long 0x00++0x03
line.long 0x00 "CAP,"
rbitfld.long 0x00 29.--31. "Reserved_29,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 28. "CS,Crypto Support" "0,1"
rbitfld.long 0x00 27. "Reserved_27,Reserved These bit are always read as 0" "0,1"
rbitfld.long 0x00 26. "UICDMETMS,UIC DME_TEST_MODE command supported" "0,1"
rbitfld.long 0x00 25. "OODDS,Out of order data delivery supported" "0,1"
rbitfld.long 0x00 24. "_64AS,64bit addressing supported" "0,1"
newline
rbitfld.long 0x00 23. "AUTOH8,Auto Hibernation Support" "0,1"
rbitfld.long 0x00 19.--22. "Reserved_19,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 16.--18. "NUTMRS,Number of UTP Task Management Request Slots 3b111 : Host controller supports 8 slots of UTP Task Management Request List" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 8.--15. 1. "NORTT,Number of outstanding READY TO TRANSFER (RTT) requests supported 8b"
rbitfld.long 0x00 5.--7. "Reserved_5,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0.--4. "NUTRS,Number of UTP Transfer Request Slots 5b1_1111 : Host controller supports 32 slots of UTP Transfer Request List" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x08++0x03
line.long 0x00 "VER,"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 8.--15. 1. "MJR,Major Version Number 8h03 : Host supports major version 8h03 of BCD"
rbitfld.long 0x00 4.--7. "MNR,Minor Version Number 4h0 : Host supports minor version 4h0 of BCD format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 0.--3. "VS,Version Suffix" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x10++0x03
line.long 0x00 "HCPID,"
hexmask.long 0x00 0.--31. 1. "PID,Product ID"
group.long 0x14++0x03
line.long 0x00 "HCMID,"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 8.--15. 1. "BI,Bank Index"
hexmask.long.byte 0x00 0.--7. 1. "MIC,Manufacturer Identification Code"
group.long 0x18++0x03
line.long 0x00 "AHIT,"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved These bits are always read as 0"
bitfld.long 0x00 10.--12. "TS,Timer scale" "0: Value times 1 us,1: Value times 10 us,2: Value times 100 us,3: Value times 1 ms,4: Value times 10 ms,5: Value times 100 ms 110:111 reserved,?..."
hexmask.long.word 0x00 0.--9. 1. "AH8ITVAuto,Auto Hibern8 Idle Timer Value"
group.long 0x20++0x03
line.long 0x00 "IS,"
hexmask.long.word 0x00 19.--31. 1. "Reserved_19,Reserved These bits are always read as 0"
bitfld.long 0x00 18. "CEFES,Crypto Engine Fatal Error Status" "0,1"
bitfld.long 0x00 17. "SBFES,System Bus Fatal Error Status" "0,1"
bitfld.long 0x00 16. "HCFES,Host Controller Fatal Error Status" "0,1"
rbitfld.long 0x00 13.--15. "Reserved_13,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12. "UTPES,UTP Error Status" "0,1"
newline
bitfld.long 0x00 11. "DFES,Device Fatal Error Status" "0,1"
bitfld.long 0x00 10. "UCCS,UIC Command Completion Status" "0,1"
bitfld.long 0x00 9. "UTMRCS,UTP Task Management Request Completion Status" "0,1"
bitfld.long 0x00 8. "ULSS,UIC Link Startup Status" "0,1"
bitfld.long 0x00 7. "ULLS,UIC Link Lost Status" "0,1"
bitfld.long 0x00 6. "UHES,UIC Hibernate Enter Status" "0,1"
newline
bitfld.long 0x00 5. "UHXS,UIC Hibernate Exit Status" "0,1"
bitfld.long 0x00 4. "UPMS,UIC Power Mode Status" "0,1"
bitfld.long 0x00 3. "UTMS,UIC Test Mode Status" "0,1"
bitfld.long 0x00 2. "UE,UIC Error" "0,1"
bitfld.long 0x00 1. "UDEPRI,UIC DME_ENDPOINTRESET Indication" "0,1"
bitfld.long 0x00 0. "UTRCS,UTP Transfer Request Completion Status" "0,1"
group.long 0x24++0x03
line.long 0x00 "IE,"
hexmask.long.word 0x00 19.--31. 1. "Reserved_19,Reserved These bits are always read as 0"
bitfld.long 0x00 18. "CEFEE,Crypto Engine Fatal Error Enable" "0,1"
bitfld.long 0x00 17. "SBFEE,System Bus Fatal Error Enable" "0,1"
bitfld.long 0x00 16. "HCFEE,Host Controller Fatal Error Enable" "0,1"
rbitfld.long 0x00 13.--15. "Reserved_13,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12. "UTPEE,UTP Error Enable" "0,1"
newline
bitfld.long 0x00 11. "DFEE,Device Fatal Error Enable" "0,1"
bitfld.long 0x00 10. "UCCE,UIC Command Completion Enable" "0,1"
bitfld.long 0x00 9. "UTMRCE,UTP Task Management Request Completion Enable" "0,1"
bitfld.long 0x00 8. "ULSSE,UIC Link Startup Status Enable" "0,1"
bitfld.long 0x00 7. "ULLSE,UIC Link Lost Status Enable" "0,1"
bitfld.long 0x00 6. "UHESE,UIC Hibernate Enter Status Enable" "0,1"
newline
bitfld.long 0x00 5. "UHXSE,UIC Hibernate Exit Status Enable" "0,1"
bitfld.long 0x00 4. "UPMSE,UIC Power Mode Status Enable" "0,1"
bitfld.long 0x00 3. "UTMSE,UIC Test Mode Status Enable" "0,1"
bitfld.long 0x00 2. "UEE,UIC Error Enable" "0,1"
bitfld.long 0x00 1. "UDEPRIE,UIC DME_ENDPOINTRESET Indication Enable" "0,1"
bitfld.long 0x00 0. "UTRCSE,UTP Transfer Request Completion Enable" "0,1"
group.long 0x30++0x03
line.long 0x00 "HCS,"
hexmask.long.byte 0x00 24.--31. 1. "TLUNUTPE,Target LUN of UTP error"
hexmask.long.byte 0x00 16.--23. 1. "TTAGUTPE,Task Tag of UTP error"
rbitfld.long 0x00 12.--15. "UTPEC,UTP Error Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 11. "Reserved_11,Reserved These bit are always read as 0" "0,1"
rbitfld.long 0x00 8.--10. "UPMCRS,UIC Power Mode Change Request Status" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4.--7. "Reserved_4,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 3. "UCRDY,UIC COMMAND Ready" "0,1"
rbitfld.long 0x00 2. "UTMRLRDY,UTP Task Management Request List Ready" "0,1"
rbitfld.long 0x00 1. "UTRLRDY,UTP Transfer Request List Ready" "0,1"
rbitfld.long 0x00 0. "DP,Device Present" "0,1"
group.long 0x34++0x03
line.long 0x00 "HCE,"
hexmask.long 0x00 2.--31. 1. "Reserved_2,Reserved These bits are always read as 0"
bitfld.long 0x00 1. "CGE,Crypto General Enable" "0,1"
bitfld.long 0x00 0. "HCE,Host Controller Enable" "0,1"
group.long 0x38++0x03
line.long 0x00 "UECPA,"
rbitfld.long 0x00 31. "ERR,UIC PHY Adapter Layer Error" "0,1"
hexmask.long 0x00 5.--30. 1. "Reserved_5,Reserved These bits are always read as 0"
rbitfld.long 0x00 0.--4. "EC,UIC PHY Adapter Layer Error Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x3C++0x03
line.long 0x00 "UECDL,"
rbitfld.long 0x00 31. "ERR,UIC Data Link Layer Error" "0,1"
hexmask.long.word 0x00 16.--30. 1. "Reserved_16,Reserved These bits are always read as 0"
hexmask.long.word 0x00 0.--15. 1. "EC,UIC Data Link Layer Error Code"
group.long 0x40++0x03
line.long 0x00 "UECN,"
rbitfld.long 0x00 31. "ERR,UIC Network Layer Error" "0,1"
hexmask.long 0x00 3.--30. 1. "Reserved_3,Reserved These bits are always read as 0"
rbitfld.long 0x00 0.--2. "EC,UIC Network Layer Error Code" "0,1,2,3,4,5,6,7"
group.long 0x44++0x03
line.long 0x00 "UECT,"
rbitfld.long 0x00 31. "ERR,UIC Transport Layer Error" "0,1"
hexmask.long.tbyte 0x00 7.--30. 1. "Reserved_7,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--6. 1. "EC,UIC Transport Layer Error Code"
group.long 0x48++0x03
line.long 0x00 "UECDME,"
rbitfld.long 0x00 31. "ERR,UIC DME Error" "0,1"
hexmask.long 0x00 4.--30. 1. "Reserved_4,Reserved These bits are always read as 0"
rbitfld.long 0x00 0.--3. "EC,UIC DME Error Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4C++0x03
line.long 0x00 "UTRIACR,"
bitfld.long 0x00 31. "IAEN,Interrupt Aggregation Enable/Disable" "0,1"
rbitfld.long 0x00 25.--30. "Reserved_25,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 24. "IAPWEN,Interrupt aggregation parameter write enable" "0,1"
rbitfld.long 0x00 21.--23. "Reserved_21,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 20. "IASB,Interrupt aggregation status bit" "0,1"
rbitfld.long 0x00 17.--19. "Reserved_17,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16. "CTR,Counter and Timer Reset" "0,1"
rbitfld.long 0x00 13.--15. "Reserved_13,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--12. "IACTH,Interrupt aggregation counter threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x00 0.--7. 1. "IATOVAL,Interrupt aggregation timeout value"
group.long 0x50++0x03
line.long 0x00 "UTRLBA,"
hexmask.long.tbyte 0x00 10.--31. 1. "UTRLBA,UTP Transfer Request List Base Address"
hexmask.long.word 0x00 0.--9. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x54++0x03
line.long 0x00 "UTRLBAU,"
hexmask.long 0x00 0.--31. 1. "UTRLBAU,UTP Transfer Request List Base Address Upper"
group.long 0x58++0x03
line.long 0x00 "UTRLDBR,"
hexmask.long 0x00 0.--31. 1. "UTRLDBR,UTP Transfer Request List Door bell Register"
group.long 0x5C++0x03
line.long 0x00 "UTRLCLR,"
hexmask.long 0x00 0.--31. 1. "UTRLCLR,UTP Transfer Request List Clear Register"
group.long 0x60++0x03
line.long 0x00 "UTRLRSR,"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "UTRLRSR,UTP Transfer Request List Run Stop Register" "0,1"
group.long 0x64++0x03
line.long 0x00 "UTRLCNR,"
hexmask.long 0x00 0.--31. 1. "UTRLCNR,UTP Transfer Request List Completion Notification Register"
group.long 0x70++0x03
line.long 0x00 "UTMRLBA,"
hexmask.long.tbyte 0x00 10.--31. 1. "UTMRLBA,UTP Task Management Request List Base Address"
hexmask.long.word 0x00 0.--9. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x74++0x03
line.long 0x00 "UTMRLBAU,"
hexmask.long 0x00 0.--31. 1. "UTMRLBAU,UTP Task Management Request List Base Address"
group.long 0x78++0x03
line.long 0x00 "UTMRLDBR,"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "UTMRLDBR,UTP Task Management Request List Door bell Register"
group.long 0x7C++0x03
line.long 0x00 "UTMRLCLR,"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "UTMRLCLR,UTP Task Management List Clear Register"
group.long 0x80++0x03
line.long 0x00 "UTMRLRSR,"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "UTMRLRSR,UTP Task Management Request List Run Stop Register" "0,1"
group.long 0x90++0x03
line.long 0x00 "UICCMD,"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 0.--7. 1. "CMDOP,Command Opcode"
group.long 0x94++0x03
line.long 0x00 "UICCMDARG1,"
hexmask.long 0x00 0.--31. 1. "ARG1,Argument 1"
group.long 0x98++0x03
line.long 0x00 "UCMDARG2,"
hexmask.long 0x00 0.--31. 1. "ARG2,Argument 2"
group.long 0x9C++0x03
line.long 0x00 "UCMDARG3,"
hexmask.long 0x00 0.--31. 1. "ARG3,Argument 3"
tree.end
tree "RWDT"
base ad:0xE6020000
group.long 0x00++0x03
line.long 0x00 "RWTCNT,1.0 RWTCNT is a 16-bit readable/writable register that increments on the selected clock"
hexmask.long.word 0x00 16.--31. 1. "CODE_VAL,Code value 1 When writing this register write H5A5A to this bit field"
hexmask.long.word 0x00 0.--15. 1. "RWTCNT,Timer Counter Bits"
group.long 0x00++0x03
line.long 0x00 "RWTCNT__16_L,1.0 RWTCNT is a 16-bit readable/writable register that increments on the selected clock"
hexmask.long.word 0x00 16.--31. 1. "Reserved0,Reserved"
hexmask.long.word 0x00 0.--15. 1. "RWTCNT,Timer Counter Bits"
group.long 0x00++0x03
line.long 0x00 "RWTCNT__16_H,1.0 RWTCNT is a 16-bit readable/writable register that increments on the selected clock"
hexmask.long.word 0x00 16.--31. 1. "CODE_VAL,Code value 1 When writing this register write H5A5A to this bit field"
hexmask.long.word 0x00 0.--15. 1. "Reserved1,Reserved"
group.long 0x04++0x03
line.long 0x00 "RWTCSRA,1.0 RWTCSRA is an 8-bit readable/writable register composed of bits to select the clock used for the count overflow flag and enable bit"
hexmask.long.tbyte 0x00 8.--31. 1. "CODE_VAL2,Code value 2 When writing this register write HA5 A5A5 to this bit field"
bitfld.long 0x00 7. "TME,Starts and stops timer operation" "0: Timer disabled,1: Timer enabled"
newline
rbitfld.long 0x00 6. "Reserved_6,Reserved This bit is always read as 0" "0,1"
rbitfld.long 0x00 5. "WRFLG,Write Status Flag When this bit is 1 write access to RWTCNT is prohibited" "0,1"
newline
bitfld.long 0x00 4. "WOVF,Indicates that the RWTCNT has overflowed" "0: No overflow,1: RWTCNT has overflowed"
bitfld.long 0x00 3. "WOVFE,Overflow Interrupt Disable/Enable" "0: Disables interrupts due to overflow,1: Enables interrupts due to overflow"
newline
bitfld.long 0x00 0.--2. "CKS0,RTC Clock Select These bits select the clock to be used for the RWTCNT count from the eight types obtainable by dividing the RCLK" "0: RCLK (RWTCNT: H0000 = 1.9 s (RWTCNT: H'FF00 =,1: RCLK/4 (RWTCNT: H0000 = 7.9 s (RWTCNT:..,2: RCLK/16 (RWTCNT: H0000 = 31.9 s (RWTCNT:..,3: RCLK/32 (RWTCNT: H0000 = 63.9 s (RWTCNT:..,4: RCLK/64 (RWTCNT: H0000 = 127.8 s (RWTCNT,5: RCLK/128 (RWTCNT: H0000 = 255.7 s (RWTCNT,6: RCLK/1024 (RWTCNT: H0000 = 2046.0 s (RWTCNT,7: RCLK select expanded mode The clock cycle.."
group.long 0x04++0x03
line.long 0x00 "RWTCSRA__8_LL,1.0 RWTCSRA is an 8-bit readable/writable register composed of bits to select the clock used for the count overflow flag and enable bit"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved0,Reserved"
bitfld.long 0x00 7. "TME,Starts and stops timer operation" "0: Timer disabled,1: Timer enabled"
newline
rbitfld.long 0x00 6. "Reserved_6,Reserved This bit is always read as 0" "0,1"
rbitfld.long 0x00 5. "WRFLG,Write Status Flag When this bit is 1 write access to RWTCNT is prohibited" "0,1"
newline
bitfld.long 0x00 4. "WOVF,Indicates that the RWTCNT has overflowed" "0: No overflow,1: RWTCNT has overflowed"
bitfld.long 0x00 3. "WOVFE,Overflow Interrupt Disable/Enable" "0: Disables interrupts due to overflow,1: Enables interrupts due to overflow"
newline
bitfld.long 0x00 0.--2. "CKS0,RTC Clock Select These bits select the clock to be used for the RWTCNT count from the eight types obtainable by dividing the RCLK" "0: RCLK (RWTCNT: H0000 = 1.9 s (RWTCNT: H'FF00 =,1: RCLK/4 (RWTCNT: H0000 = 7.9 s (RWTCNT:..,2: RCLK/16 (RWTCNT: H0000 = 31.9 s (RWTCNT:..,3: RCLK/32 (RWTCNT: H0000 = 63.9 s (RWTCNT:..,4: RCLK/64 (RWTCNT: H0000 = 127.8 s (RWTCNT,5: RCLK/128 (RWTCNT: H0000 = 255.7 s (RWTCNT,6: RCLK/1024 (RWTCNT: H0000 = 2046.0 s (RWTCNT,7: RCLK select expanded mode The clock cycle.."
group.long 0x04++0x03
line.long 0x00 "RWTCSRA__8_LH,1.0 RWTCSRA is an 8-bit readable/writable register composed of bits to select the clock used for the count overflow flag and enable bit"
hexmask.long.word 0x00 16.--31. 1. "Reserved0,Reserved"
hexmask.long.byte 0x00 8.--15. 1. "CODE_VAL2,Code value 2 When writing this register write HA5 A5A5 to this bit field"
newline
rbitfld.long 0x00 7. "Reserved1,Reserved" "0,1"
rbitfld.long 0x00 6. "Reserved2,Reserved" "0,1"
newline
rbitfld.long 0x00 5. "Reserved3,Reserved" "0,1"
rbitfld.long 0x00 4. "Reserved4,Reserved" "0,1"
newline
rbitfld.long 0x00 3. "Reserved5,Reserved" "0,1"
rbitfld.long 0x00 0.--2. "Reserved6,Reserved" "0,1,2,3,4,5,6,7"
group.long 0x04++0x03
line.long 0x00 "RWTCSRA__8_HL,1.0 RWTCSRA is an 8-bit readable/writable register composed of bits to select the clock used for the count overflow flag and enable bit"
hexmask.long.word 0x00 16.--31. 1. "CODE_VAL2,Code value 2 When writing this register write HA5 A5A5 to this bit field"
hexmask.long.byte 0x00 8.--15. 1. "Reserved0,Reserved"
newline
rbitfld.long 0x00 7. "Reserved1,Reserved" "0,1"
rbitfld.long 0x00 6. "Reserved2,Reserved" "0,1"
newline
rbitfld.long 0x00 5. "Reserved3,Reserved" "0,1"
rbitfld.long 0x00 4. "Reserved4,Reserved" "0,1"
newline
rbitfld.long 0x00 3. "Reserved5,Reserved" "0,1"
rbitfld.long 0x00 0.--2. "Reserved6,Reserved" "0,1,2,3,4,5,6,7"
group.long 0x04++0x03
line.long 0x00 "RWTCSRA__8_HH,1.0 RWTCSRA is an 8-bit readable/writable register composed of bits to select the clock used for the count overflow flag and enable bit"
hexmask.long.byte 0x00 24.--31. 1. "CODE_VAL2,Code value 2 When writing this register write HA5 A5A5 to this bit field"
hexmask.long.word 0x00 8.--23. 1. "Reserved0,Reserved"
newline
rbitfld.long 0x00 7. "Reserved1,Reserved" "0,1"
rbitfld.long 0x00 6. "Reserved2,Reserved" "0,1"
newline
rbitfld.long 0x00 5. "Reserved3,Reserved" "0,1"
rbitfld.long 0x00 4. "Reserved4,Reserved" "0,1"
newline
rbitfld.long 0x00 3. "Reserved5,Reserved" "0,1"
rbitfld.long 0x00 0.--2. "Reserved6,Reserved" "0,1,2,3,4,5,6,7"
group.long 0x08++0x03
line.long 0x00 "RWTCSRB,1.0 RWTCSRB is an 8-bit readable/writable register composed of bits to select the clock used for the count"
hexmask.long.tbyte 0x00 8.--31. 1. "CODE_VAL3,Code value 3 When writing this register write HA5 A5A5 to this bit field"
rbitfld.long 0x00 6.--7. "Reserved_6,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "CKS1,RCLK Select for RCLK Select Expanded Mode Selects the clock used for the RWTCNT count when the CKS0 bit in RWTCSRA is B'111" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x03
line.long 0x00 "RWTCSRB__8_LL,1.0 RWTCSRB is an 8-bit readable/writable register composed of bits to select the clock used for the count"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved0,Reserved"
rbitfld.long 0x00 6.--7. "Reserved_6,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "CKS1,RCLK Select for RCLK Select Expanded Mode Selects the clock used for the RWTCNT count when the CKS0 bit in RWTCSRA is B'111" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x03
line.long 0x00 "RWTCSRB__8_LH,1.0 RWTCSRB is an 8-bit readable/writable register composed of bits to select the clock used for the count"
hexmask.long.word 0x00 16.--31. 1. "Reserved0,Reserved"
hexmask.long.byte 0x00 8.--15. 1. "CODE_VAL3,Code value 3 When writing this register write HA5 A5A5 to this bit field"
newline
rbitfld.long 0x00 6.--7. "Reserved1,Reserved" "0,1,2,3"
rbitfld.long 0x00 0.--5. "Reserved2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x03
line.long 0x00 "RWTCSRB__8_HL,1.0 RWTCSRB is an 8-bit readable/writable register composed of bits to select the clock used for the count"
hexmask.long.word 0x00 16.--31. 1. "CODE_VAL3,Code value 3 When writing this register write HA5 A5A5 to this bit field"
hexmask.long.byte 0x00 8.--15. 1. "Reserved0,Reserved"
newline
rbitfld.long 0x00 6.--7. "Reserved1,Reserved" "0,1,2,3"
rbitfld.long 0x00 0.--5. "Reserved2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x03
line.long 0x00 "RWTCSRB__8_HH,1.0 RWTCSRB is an 8-bit readable/writable register composed of bits to select the clock used for the count"
hexmask.long.byte 0x00 24.--31. 1. "CODE_VAL3,Code value 3 When writing this register write HA5 A5A5 to this bit field"
hexmask.long.word 0x00 8.--23. 1. "Reserved0,Reserved"
newline
rbitfld.long 0x00 6.--7. "Reserved1,Reserved" "0,1,2,3"
rbitfld.long 0x00 0.--5. "Reserved2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
tree.end
tree "WWDT"
tree "WWDT_INST_0"
base ad:0xFFC90000
group.byte 0x00++0x00
line.byte 0x00 "WDTA0WDTE0,Note: n = 0 to 9 The register is a trigger register"
bitfld.byte 0x00 7. "WDTA0RUN,Watchdog timer count start or stop" "0,1"
hexmask.byte 0x00 0.--6. 1. "Reserved_0,Reserved"
group.byte 0x0C++0x00
line.byte 0x00 "WDTA0MD0,Note: n = 0 to 9 This register is timer mode register"
rbitfld.byte 0x00 7. "Reserved_7,Reserved" "0,1"
bitfld.byte 0x00 6. "WDTA0OVF2,Interval time mode" "0,1"
bitfld.byte 0x00 5. "WDTA0OVF1,Interval time mode" "0,1"
bitfld.byte 0x00 4. "WDTA0OVF0,Interval time mode" "0,1"
bitfld.byte 0x00 3. "WDTA0WIE,75% interrupt enable" "0: 75% interrupt is disabled,1: 75% interrupt is enabled"
bitfld.byte 0x00 2. "WDTA0ERM,Error mode" "0: NMI mode,1: Reset mode (Default)"
bitfld.byte 0x00 1. "WDTA0WS1,Window Size selection Please refer to Figure 154.2.2.1 and Table 154.2.2.1 for details" "0,1"
newline
bitfld.byte 0x00 0. "WDTA0WS0,Window Size selection Please refer to Figure 154.2.2.1 and Table 154.2.2.1 for details" "0,1"
tree.end
tree "WWDT_INST_1"
base ad:0xFFCA0000
group.byte 0x00++0x00
line.byte 0x00 "WDTA0WDTE1,Note: n = 0 to 9 The register is a trigger register"
bitfld.byte 0x00 7. "WDTA0RUN,Watchdog timer count start or stop" "0,1"
hexmask.byte 0x00 0.--6. 1. "Reserved_0,Reserved"
group.byte 0x0C++0x00
line.byte 0x00 "WDTA0MD1,Note: n = 0 to 9 This register is timer mode register"
rbitfld.byte 0x00 7. "Reserved_7,Reserved" "0,1"
bitfld.byte 0x00 6. "WDTA0OVF2,Interval time mode" "0,1"
bitfld.byte 0x00 5. "WDTA0OVF1,Interval time mode" "0,1"
bitfld.byte 0x00 4. "WDTA0OVF0,Interval time mode" "0,1"
bitfld.byte 0x00 3. "WDTA0WIE,75% interrupt enable" "0: 75% interrupt is disabled,1: 75% interrupt is enabled"
bitfld.byte 0x00 2. "WDTA0ERM,Error mode" "0: NMI mode,1: Reset mode (Default)"
bitfld.byte 0x00 1. "WDTA0WS1,Window Size selection Please refer to Figure 154.2.2.1 and Table 154.2.2.1 for details" "0,1"
newline
bitfld.byte 0x00 0. "WDTA0WS0,Window Size selection Please refer to Figure 154.2.2.1 and Table 154.2.2.1 for details" "0,1"
tree.end
tree "WWDT_INST_2"
base ad:0xFFCB0000
group.byte 0x00++0x00
line.byte 0x00 "WDTA0WDTE2,Note: n = 0 to 9 The register is a trigger register"
bitfld.byte 0x00 7. "WDTA0RUN,Watchdog timer count start or stop" "0,1"
hexmask.byte 0x00 0.--6. 1. "Reserved_0,Reserved"
group.byte 0x0C++0x00
line.byte 0x00 "WDTA0MD2,Note: n = 0 to 9 This register is timer mode register"
rbitfld.byte 0x00 7. "Reserved_7,Reserved" "0,1"
bitfld.byte 0x00 6. "WDTA0OVF2,Interval time mode" "0,1"
bitfld.byte 0x00 5. "WDTA0OVF1,Interval time mode" "0,1"
bitfld.byte 0x00 4. "WDTA0OVF0,Interval time mode" "0,1"
bitfld.byte 0x00 3. "WDTA0WIE,75% interrupt enable" "0: 75% interrupt is disabled,1: 75% interrupt is enabled"
bitfld.byte 0x00 2. "WDTA0ERM,Error mode" "0: NMI mode,1: Reset mode (Default)"
bitfld.byte 0x00 1. "WDTA0WS1,Window Size selection Please refer to Figure 154.2.2.1 and Table 154.2.2.1 for details" "0,1"
newline
bitfld.byte 0x00 0. "WDTA0WS0,Window Size selection Please refer to Figure 154.2.2.1 and Table 154.2.2.1 for details" "0,1"
tree.end
tree "WWDT_INST_3"
base ad:0xFFCC0000
group.byte 0x00++0x00
line.byte 0x00 "WDTA0WDTE3,Note: n = 0 to 9 The register is a trigger register"
bitfld.byte 0x00 7. "WDTA0RUN,Watchdog timer count start or stop" "0,1"
hexmask.byte 0x00 0.--6. 1. "Reserved_0,Reserved"
group.byte 0x0C++0x00
line.byte 0x00 "WDTA0MD3,Note: n = 0 to 9 This register is timer mode register"
rbitfld.byte 0x00 7. "Reserved_7,Reserved" "0,1"
bitfld.byte 0x00 6. "WDTA0OVF2,Interval time mode" "0,1"
bitfld.byte 0x00 5. "WDTA0OVF1,Interval time mode" "0,1"
bitfld.byte 0x00 4. "WDTA0OVF0,Interval time mode" "0,1"
bitfld.byte 0x00 3. "WDTA0WIE,75% interrupt enable" "0: 75% interrupt is disabled,1: 75% interrupt is enabled"
bitfld.byte 0x00 2. "WDTA0ERM,Error mode" "0: NMI mode,1: Reset mode (Default)"
bitfld.byte 0x00 1. "WDTA0WS1,Window Size selection Please refer to Figure 154.2.2.1 and Table 154.2.2.1 for details" "0,1"
newline
bitfld.byte 0x00 0. "WDTA0WS0,Window Size selection Please refer to Figure 154.2.2.1 and Table 154.2.2.1 for details" "0,1"
tree.end
tree "WWDT_INST_4"
base ad:0xFFCF0000
group.byte 0x00++0x00
line.byte 0x00 "WDTA0WDTE4,Note: n = 0 to 9 The register is a trigger register"
bitfld.byte 0x00 7. "WDTA0RUN,Watchdog timer count start or stop" "0,1"
hexmask.byte 0x00 0.--6. 1. "Reserved_0,Reserved"
group.byte 0x0C++0x00
line.byte 0x00 "WDTA0MD4,Note: n = 0 to 9 This register is timer mode register"
rbitfld.byte 0x00 7. "Reserved_7,Reserved" "0,1"
bitfld.byte 0x00 6. "WDTA0OVF2,Interval time mode" "0,1"
bitfld.byte 0x00 5. "WDTA0OVF1,Interval time mode" "0,1"
bitfld.byte 0x00 4. "WDTA0OVF0,Interval time mode" "0,1"
bitfld.byte 0x00 3. "WDTA0WIE,75% interrupt enable" "0: 75% interrupt is disabled,1: 75% interrupt is enabled"
bitfld.byte 0x00 2. "WDTA0ERM,Error mode" "0: NMI mode,1: Reset mode (Default)"
bitfld.byte 0x00 1. "WDTA0WS1,Window Size selection Please refer to Figure 154.2.2.1 and Table 154.2.2.1 for details" "0,1"
newline
bitfld.byte 0x00 0. "WDTA0WS0,Window Size selection Please refer to Figure 154.2.2.1 and Table 154.2.2.1 for details" "0,1"
tree.end
tree "WWDT_INST_5"
base ad:0xFFEF0000
group.byte 0x00++0x00
line.byte 0x00 "WDTA0WDTE5,Note: n = 0 to 9 The register is a trigger register"
bitfld.byte 0x00 7. "WDTA0RUN,Watchdog timer count start or stop" "0,1"
hexmask.byte 0x00 0.--6. 1. "Reserved_0,Reserved"
group.byte 0x0C++0x00
line.byte 0x00 "WDTA0MD5,Note: n = 0 to 9 This register is timer mode register"
rbitfld.byte 0x00 7. "Reserved_7,Reserved" "0,1"
bitfld.byte 0x00 6. "WDTA0OVF2,Interval time mode" "0,1"
bitfld.byte 0x00 5. "WDTA0OVF1,Interval time mode" "0,1"
bitfld.byte 0x00 4. "WDTA0OVF0,Interval time mode" "0,1"
bitfld.byte 0x00 3. "WDTA0WIE,75% interrupt enable" "0: 75% interrupt is disabled,1: 75% interrupt is enabled"
bitfld.byte 0x00 2. "WDTA0ERM,Error mode" "0: NMI mode,1: Reset mode (Default)"
bitfld.byte 0x00 1. "WDTA0WS1,Window Size selection Please refer to Figure 154.2.2.1 and Table 154.2.2.1 for details" "0,1"
newline
bitfld.byte 0x00 0. "WDTA0WS0,Window Size selection Please refer to Figure 154.2.2.1 and Table 154.2.2.1 for details" "0,1"
tree.end
tree "WWDT_INST_6"
base ad:0xFFF10000
group.byte 0x00++0x00
line.byte 0x00 "WDTA0WDTE6,Note: n = 0 to 9 The register is a trigger register"
bitfld.byte 0x00 7. "WDTA0RUN,Watchdog timer count start or stop" "0,1"
hexmask.byte 0x00 0.--6. 1. "Reserved_0,Reserved"
group.byte 0x0C++0x00
line.byte 0x00 "WDTA0MD6,Note: n = 0 to 9 This register is timer mode register"
rbitfld.byte 0x00 7. "Reserved_7,Reserved" "0,1"
bitfld.byte 0x00 6. "WDTA0OVF2,Interval time mode" "0,1"
bitfld.byte 0x00 5. "WDTA0OVF1,Interval time mode" "0,1"
bitfld.byte 0x00 4. "WDTA0OVF0,Interval time mode" "0,1"
bitfld.byte 0x00 3. "WDTA0WIE,75% interrupt enable" "0: 75% interrupt is disabled,1: 75% interrupt is enabled"
bitfld.byte 0x00 2. "WDTA0ERM,Error mode" "0: NMI mode,1: Reset mode (Default)"
bitfld.byte 0x00 1. "WDTA0WS1,Window Size selection Please refer to Figure 154.2.2.1 and Table 154.2.2.1 for details" "0,1"
newline
bitfld.byte 0x00 0. "WDTA0WS0,Window Size selection Please refer to Figure 154.2.2.1 and Table 154.2.2.1 for details" "0,1"
tree.end
tree "WWDT_INST_7"
base ad:0xFFF20000
group.byte 0x00++0x00
line.byte 0x00 "WDTA0WDTE7,Note: n = 0 to 9 The register is a trigger register"
bitfld.byte 0x00 7. "WDTA0RUN,Watchdog timer count start or stop" "0,1"
hexmask.byte 0x00 0.--6. 1. "Reserved_0,Reserved"
group.byte 0x0C++0x00
line.byte 0x00 "WDTA0MD7,Note: n = 0 to 9 This register is timer mode register"
rbitfld.byte 0x00 7. "Reserved_7,Reserved" "0,1"
bitfld.byte 0x00 6. "WDTA0OVF2,Interval time mode" "0,1"
bitfld.byte 0x00 5. "WDTA0OVF1,Interval time mode" "0,1"
bitfld.byte 0x00 4. "WDTA0OVF0,Interval time mode" "0,1"
bitfld.byte 0x00 3. "WDTA0WIE,75% interrupt enable" "0: 75% interrupt is disabled,1: 75% interrupt is enabled"
bitfld.byte 0x00 2. "WDTA0ERM,Error mode" "0: NMI mode,1: Reset mode (Default)"
bitfld.byte 0x00 1. "WDTA0WS1,Window Size selection Please refer to Figure 154.2.2.1 and Table 154.2.2.1 for details" "0,1"
newline
bitfld.byte 0x00 0. "WDTA0WS0,Window Size selection Please refer to Figure 154.2.2.1 and Table 154.2.2.1 for details" "0,1"
tree.end
tree "WWDT_INST_8"
base ad:0xFFF30000
group.byte 0x00++0x00
line.byte 0x00 "WDTA0WDTE8,Note: n = 0 to 9 The register is a trigger register"
bitfld.byte 0x00 7. "WDTA0RUN,Watchdog timer count start or stop" "0,1"
hexmask.byte 0x00 0.--6. 1. "Reserved_0,Reserved"
group.byte 0x0C++0x00
line.byte 0x00 "WDTA0MD8,Note: n = 0 to 9 This register is timer mode register"
rbitfld.byte 0x00 7. "Reserved_7,Reserved" "0,1"
bitfld.byte 0x00 6. "WDTA0OVF2,Interval time mode" "0,1"
bitfld.byte 0x00 5. "WDTA0OVF1,Interval time mode" "0,1"
bitfld.byte 0x00 4. "WDTA0OVF0,Interval time mode" "0,1"
bitfld.byte 0x00 3. "WDTA0WIE,75% interrupt enable" "0: 75% interrupt is disabled,1: 75% interrupt is enabled"
bitfld.byte 0x00 2. "WDTA0ERM,Error mode" "0: NMI mode,1: Reset mode (Default)"
bitfld.byte 0x00 1. "WDTA0WS1,Window Size selection Please refer to Figure 154.2.2.1 and Table 154.2.2.1 for details" "0,1"
newline
bitfld.byte 0x00 0. "WDTA0WS0,Window Size selection Please refer to Figure 154.2.2.1 and Table 154.2.2.1 for details" "0,1"
tree.end
tree "WWDT_INST_9"
base ad:0xFFF40000
group.byte 0x00++0x00
line.byte 0x00 "WDTA0WDTE9,Note: n = 0 to 9 The register is a trigger register"
bitfld.byte 0x00 7. "WDTA0RUN,Watchdog timer count start or stop" "0,1"
hexmask.byte 0x00 0.--6. 1. "Reserved_0,Reserved"
group.byte 0x0C++0x00
line.byte 0x00 "WDTA0MD9,Note: n = 0 to 9 This register is timer mode register"
rbitfld.byte 0x00 7. "Reserved_7,Reserved" "0,1"
bitfld.byte 0x00 6. "WDTA0OVF2,Interval time mode" "0,1"
bitfld.byte 0x00 5. "WDTA0OVF1,Interval time mode" "0,1"
bitfld.byte 0x00 4. "WDTA0OVF0,Interval time mode" "0,1"
bitfld.byte 0x00 3. "WDTA0WIE,75% interrupt enable" "0: 75% interrupt is disabled,1: 75% interrupt is enabled"
bitfld.byte 0x00 2. "WDTA0ERM,Error mode" "0: NMI mode,1: Reset mode (Default)"
bitfld.byte 0x00 1. "WDTA0WS1,Window Size selection Please refer to Figure 154.2.2.1 and Table 154.2.2.1 for details" "0,1"
newline
bitfld.byte 0x00 0. "WDTA0WS0,Window Size selection Please refer to Figure 154.2.2.1 and Table 154.2.2.1 for details" "0,1"
tree.end
tree.end
tree "SWDT"
base ad:0xE6030000
group.long 0x00++0x03
line.long 0x00 "SWTCNT,1.0 SWTCNT is a 16-bit readable/writable register that increments on the selected clock"
hexmask.long.word 0x00 16.--31. 1. "CODE_VAL1,Code value 1 When writing this register write H5A5A to this bit field"
hexmask.long.word 0x00 0.--15. 1. "SWTCNT,Timer Counter Bits"
group.long 0x00++0x03
line.long 0x00 "SWTCNT__16_L,1.0 SWTCNT is a 16-bit readable/writable register that increments on the selected clock"
hexmask.long.word 0x00 16.--31. 1. "Reserved0,Reserved"
hexmask.long.word 0x00 0.--15. 1. "SWTCNT,Timer Counter Bits"
group.long 0x00++0x03
line.long 0x00 "SWTCNT__16_H,1.0 SWTCNT is a 16-bit readable/writable register that increments on the selected clock"
hexmask.long.word 0x00 16.--31. 1. "CODE_VAL1,Code value 1 When writing this register write H5A5A to this bit field"
hexmask.long.word 0x00 0.--15. 1. "Reserved1,Reserved"
group.long 0x04++0x03
line.long 0x00 "SWTCSRA,1.0 2.0 SWTCSRA is an 8-bit readable/writable register composed of bits to select the clock used for the count overflow flag and enable bit"
hexmask.long.tbyte 0x00 8.--31. 1. "CODE_VAL2,Code value 2 When writing this register write HA5 A5A5 to this bit field"
bitfld.long 0x00 7. "TME,Starts and stops timer operation" "0: Timer disabled,1: Timer enabled"
newline
rbitfld.long 0x00 6. "Reserved_6,Reserved This bit is always read as 0" "0,1"
rbitfld.long 0x00 5. "WRFLG,Write Status Flag When this bit is 1 write access to SWTCNT is prohibited" "0,1"
newline
bitfld.long 0x00 4. "WOVF,Indicates that the SWTCNT has overflowed" "0: No overflow,1: SWTCNT has overflowed"
bitfld.long 0x00 3. "WOVFE,Overflow Interrupt Disable/Enable" "0: Disables interrupts due to overflow,1: Enables interrupts due to overflow"
newline
bitfld.long 0x00 0.--2. "CKS0,RTC Clock Select These bits select the clock to be used for the SWTCNT count from the eight types obtainable by dividing the OSCCLK" "0: OSCCLK (SWTCNT: H0000 = 491 ms (SWTCNT: HFBFC,1: OSCCLK /4 (SWTCNT: H0000 = 1.9 s (SWTCNT,2: OSCCLK /16 (SWTCNT: H0000 = 7.8 s (SWTCNT,3: OSCCLK /32 (SWTCNT: H0000 = 15.7 s (SWTCNT,4: OSCCLK /64 (SWTCNT: H0000 = 31.4 s (SWTCNT,5: OSCCLK /128 (SWTCNT: H0000 = 62.9 s (SWTCNT,6: OSCCLK /1024 (SWTCNT: H0000 = 503.3 s (SWTCNT,7: OSCCLK select expanded mode The clock cycle"
group.long 0x04++0x03
line.long 0x00 "SWTCSRA__8_LL,1.0 2.0 SWTCSRA is an 8-bit readable/writable register composed of bits to select the clock used for the count overflow flag and enable bit"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved0,Reserved"
bitfld.long 0x00 7. "TME,Starts and stops timer operation" "0: Timer disabled,1: Timer enabled"
newline
rbitfld.long 0x00 6. "Reserved_6,Reserved This bit is always read as 0" "0,1"
rbitfld.long 0x00 5. "WRFLG,Write Status Flag When this bit is 1 write access to SWTCNT is prohibited" "0,1"
newline
bitfld.long 0x00 4. "WOVF,Indicates that the SWTCNT has overflowed" "0: No overflow,1: SWTCNT has overflowed"
bitfld.long 0x00 3. "WOVFE,Overflow Interrupt Disable/Enable" "0: Disables interrupts due to overflow,1: Enables interrupts due to overflow"
newline
bitfld.long 0x00 0.--2. "CKS0,RTC Clock Select These bits select the clock to be used for the SWTCNT count from the eight types obtainable by dividing the OSCCLK" "0: OSCCLK (SWTCNT: H0000 = 491 ms (SWTCNT: HFBFC,1: OSCCLK /4 (SWTCNT: H0000 = 1.9 s (SWTCNT,2: OSCCLK /16 (SWTCNT: H0000 = 7.8 s (SWTCNT,3: OSCCLK /32 (SWTCNT: H0000 = 15.7 s (SWTCNT,4: OSCCLK /64 (SWTCNT: H0000 = 31.4 s (SWTCNT,5: OSCCLK /128 (SWTCNT: H0000 = 62.9 s (SWTCNT,6: OSCCLK /1024 (SWTCNT: H0000 = 503.3 s (SWTCNT,7: OSCCLK select expanded mode The clock cycle"
group.long 0x04++0x03
line.long 0x00 "SWTCSRA__8_LH,1.0 2.0 SWTCSRA is an 8-bit readable/writable register composed of bits to select the clock used for the count overflow flag and enable bit"
hexmask.long.word 0x00 16.--31. 1. "Reserved0,Reserved"
hexmask.long.byte 0x00 8.--15. 1. "CODE_VAL2,Code value 2 When writing this register write HA5 A5A5 to this bit field"
newline
rbitfld.long 0x00 7. "Reserved1,Reserved" "0,1"
rbitfld.long 0x00 6. "Reserved2,Reserved" "0,1"
newline
rbitfld.long 0x00 5. "Reserved3,Reserved" "0,1"
rbitfld.long 0x00 4. "Reserved4,Reserved" "0,1"
newline
rbitfld.long 0x00 3. "Reserved5,Reserved" "0,1"
rbitfld.long 0x00 0.--2. "Reserved6,Reserved" "0,1,2,3,4,5,6,7"
group.long 0x04++0x03
line.long 0x00 "SWTCSRA__8_HL,1.0 2.0 SWTCSRA is an 8-bit readable/writable register composed of bits to select the clock used for the count overflow flag and enable bit"
hexmask.long.word 0x00 16.--31. 1. "CODE_VAL2,Code value 2 When writing this register write HA5 A5A5 to this bit field"
hexmask.long.byte 0x00 8.--15. 1. "Reserved0,Reserved"
newline
rbitfld.long 0x00 7. "Reserved1,Reserved" "0,1"
rbitfld.long 0x00 6. "Reserved2,Reserved" "0,1"
newline
rbitfld.long 0x00 5. "Reserved3,Reserved" "0,1"
rbitfld.long 0x00 4. "Reserved4,Reserved" "0,1"
newline
rbitfld.long 0x00 3. "Reserved5,Reserved" "0,1"
rbitfld.long 0x00 0.--2. "Reserved6,Reserved" "0,1,2,3,4,5,6,7"
group.long 0x04++0x03
line.long 0x00 "SWTCSRA__8_HH,1.0 2.0 SWTCSRA is an 8-bit readable/writable register composed of bits to select the clock used for the count overflow flag and enable bit"
hexmask.long.byte 0x00 24.--31. 1. "CODE_VAL2,Code value 2 When writing this register write HA5 A5A5 to this bit field"
hexmask.long.word 0x00 8.--23. 1. "Reserved0,Reserved"
newline
rbitfld.long 0x00 7. "Reserved1,Reserved" "0,1"
rbitfld.long 0x00 6. "Reserved2,Reserved" "0,1"
newline
rbitfld.long 0x00 5. "Reserved3,Reserved" "0,1"
rbitfld.long 0x00 4. "Reserved4,Reserved" "0,1"
newline
rbitfld.long 0x00 3. "Reserved5,Reserved" "0,1"
rbitfld.long 0x00 0.--2. "Reserved6,Reserved" "0,1,2,3,4,5,6,7"
group.long 0x08++0x03
line.long 0x00 "SWTCSRB,1.0 SWTCSRB is an 8-bit readable/writable register composed of bits to select the clock used for the count"
hexmask.long.tbyte 0x00 8.--31. 1. "CODE_VAL3,Code value 3 When writing this register write HA5 A5A5 to this bit field"
bitfld.long 0x00 6.--7. "Reserved_6,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "CKS1,OSCCLK Select for OSCCLK Select Expanded Mode Selects the clock used for the SWTCNT count when the CKS0 bit in SWTCSRA is B'111" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x03
line.long 0x00 "SWTCSRB__8_LL,1.0 SWTCSRB is an 8-bit readable/writable register composed of bits to select the clock used for the count"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved0,Reserved"
bitfld.long 0x00 6.--7. "Reserved_6,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "CKS1,OSCCLK Select for OSCCLK Select Expanded Mode Selects the clock used for the SWTCNT count when the CKS0 bit in SWTCSRA is B'111" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x03
line.long 0x00 "SWTCSRB__8_LH,1.0 SWTCSRB is an 8-bit readable/writable register composed of bits to select the clock used for the count"
hexmask.long.word 0x00 16.--31. 1. "Reserved0,Reserved"
hexmask.long.byte 0x00 8.--15. 1. "CODE_VAL3,Code value 3 When writing this register write HA5 A5A5 to this bit field"
newline
rbitfld.long 0x00 6.--7. "Reserved1,Reserved" "0,1,2,3"
rbitfld.long 0x00 0.--5. "Reserved2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x03
line.long 0x00 "SWTCSRB__8_HL,1.0 SWTCSRB is an 8-bit readable/writable register composed of bits to select the clock used for the count"
hexmask.long.word 0x00 16.--31. 1. "CODE_VAL3,Code value 3 When writing this register write HA5 A5A5 to this bit field"
hexmask.long.byte 0x00 8.--15. 1. "Reserved0,Reserved"
newline
rbitfld.long 0x00 6.--7. "Reserved1,Reserved" "0,1,2,3"
rbitfld.long 0x00 0.--5. "Reserved2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x03
line.long 0x00 "SWTCSRB__8_HH,1.0 SWTCSRB is an 8-bit readable/writable register composed of bits to select the clock used for the count"
hexmask.long.byte 0x00 24.--31. 1. "CODE_VAL3,Code value 3 When writing this register write HA5 A5A5 to this bit field"
hexmask.long.word 0x00 8.--23. 1. "Reserved0,Reserved"
newline
rbitfld.long 0x00 6.--7. "Reserved1,Reserved" "0,1,2,3"
rbitfld.long 0x00 0.--5. "Reserved2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
tree.end
tree "CMT0"
base ad:0xE60F0000
group.long 0x500++0x03
line.long 0x00 "CMSTR0,CMSTRn (n = 0 and 1) is a 32-bit register which specifies the operation of compare match timer counters (CMCNTn)"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "STR0,Count Start These bits specify start/halt of compare match timer counter (CMCNTn)" "0: CMCNTn halts,1: CMCNTn starts counting"
group.long 0x510++0x03
line.long 0x00 "CMCSR0,CMCSRn (n = 0 and 1) is a 32-bit register that indicates the occurrence of compare matches enables interrupts and sets the counter input clocks"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
bitfld.long 0x00 15. "CMF,Compare Match Flag This flag indicates whether values of the compare match timer counter (CMCNTn) and compare match timer constant register (CMCORn) have matched or not" "0: CMCNTn and CMCORn values have not matched,1: CMCNTn and CMCORn values have matched"
newline
bitfld.long 0x00 14. "OVF,Overflow Flag This flag indicates whether the compare match timer counter (McCants) has overflowed or not" "0: CMCNTn has not overflowed,1: CMCNTn has overflowed"
rbitfld.long 0x00 13. "WRFLG,Write State Flag Write access to CMCNTn is prohibited while this this bit is 1" "0,1"
newline
rbitfld.long 0x00 10.--12. "Reserved_10,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 9. "CMS,Compare Match Timer Counter Size Specify whether the compare match timer counter (CMCNTn) is used as a 16-bit counter or a 32-bit counter" "0: Operates as a 32-bit counter,1: Operates as a 16-bit counter"
newline
bitfld.long 0x00 8. "CMM,Compare Match Mode Specify counter operation mode" "0: One-shot operation,1: Free-running operation"
rbitfld.long 0x00 6.--7. "Reserved_6,Reserved This bit is always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 4.--5. "CMR_1_0,Compare Match Request These bits enable or disable an internal interrupt request in a compare match" "0: Disables an internal interrupt request,1: Setting prohibited,2: Enables an internal interrupt request,3: Setting prohibited"
bitfld.long 0x00 3. "DBGIVD,Debug Mode Operation Select Sets the counter operation in debug mode" "0: Stops the counter operation in debug mode,1: Enables the counter operation even in debug.."
newline
bitfld.long 0x00 0.--2. "CKS_2_0,Clock Select These bits select the input clock to CMCNTn" "0: Setting prohibited,1: Setting prohibited,2: Setting prohibited,3: Setting prohibited,4: RCLK/8,5: RCLK/32,6: RCLK/128,7: RCLK/1"
group.long 0x514++0x03
line.long 0x00 "CMCNT0,CMCNTn (n = 0 and 1) is a 32-bit register that is used as an up-counter"
hexmask.long 0x00 0.--31. 1. "CMCNT_31_0,Compare match timer counter bit31 to 0 Note: Refer to section 155.1.3.5 CMT0 Register Access for the note regarding writing to or reading from this bit"
group.long 0x518++0x03
line.long 0x00 "CMCOR0,CMCORn (n = 0 and 1) is a 32-bit register that sets the compare match period with CMCNTn"
hexmask.long 0x00 0.--31. 1. "CMCOR_31_0,Compare match timer constant register bit31 to 0 Note: Refer to section 155.1.3.5 CMT0 Register Access for the note regarding writing to or reading from this bit"
group.long 0x600++0x03
line.long 0x00 "CMSTR1,CMSTRn (n = 0 and 1) is a 32-bit register which specifies the operation of compare match timer counters (CMCNTn)"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "STR0,Count Start These bits specify start/halt of compare match timer counter (CMCNTn)" "0: CMCNTn halts,1: CMCNTn starts counting"
group.long 0x610++0x03
line.long 0x00 "CMCSR1,CMCSRn (n = 0 and 1) is a 32-bit register that indicates the occurrence of compare matches enables interrupts and sets the counter input clocks"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
bitfld.long 0x00 15. "CMF,Compare Match Flag This flag indicates whether values of the compare match timer counter (CMCNTn) and compare match timer constant register (CMCORn) have matched or not" "0: CMCNTn and CMCORn values have not matched,1: CMCNTn and CMCORn values have matched"
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bitfld.long 0x00 14. "OVF,Overflow Flag This flag indicates whether the compare match timer counter (McCants) has overflowed or not" "0: CMCNTn has not overflowed,1: CMCNTn has overflowed"
rbitfld.long 0x00 13. "WRFLG,Write State Flag Write access to CMCNTn is prohibited while this this bit is 1" "0,1"
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rbitfld.long 0x00 10.--12. "Reserved_10,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 9. "CMS,Compare Match Timer Counter Size Specify whether the compare match timer counter (CMCNTn) is used as a 16-bit counter or a 32-bit counter" "0: Operates as a 32-bit counter,1: Operates as a 16-bit counter"
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bitfld.long 0x00 8. "CMM,Compare Match Mode Specify counter operation mode" "0: One-shot operation,1: Free-running operation"
rbitfld.long 0x00 6.--7. "Reserved_6,Reserved This bit is always read as 0" "0,1,2,3"
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bitfld.long 0x00 4.--5. "CMR_1_0,Compare Match Request These bits enable or disable an internal interrupt request in a compare match" "0: Disables an internal interrupt request,1: Setting prohibited,2: Enables an internal interrupt request,3: Setting prohibited"
bitfld.long 0x00 3. "DBGIVD,Debug Mode Operation Select Sets the counter operation in debug mode" "0: Stops the counter operation in debug mode,1: Enables the counter operation even in debug.."
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bitfld.long 0x00 0.--2. "CKS_2_0,Clock Select These bits select the input clock to CMCNTn" "0: Setting prohibited,1: Setting prohibited,2: Setting prohibited,3: Setting prohibited,4: RCLK/8,5: RCLK/32,6: RCLK/128,7: RCLK/1"
group.long 0x614++0x03
line.long 0x00 "CMCNT1,CMCNTn (n = 0 and 1) is a 32-bit register that is used as an up-counter"
hexmask.long 0x00 0.--31. 1. "CMCNT_31_0,Compare match timer counter bit31 to 0 Note: Refer to section 155.1.3.5 CMT0 Register Access for the note regarding writing to or reading from this bit"
group.long 0x618++0x03
line.long 0x00 "CMCOR1,CMCORn (n = 0 and 1) is a 32-bit register that sets the compare match period with CMCNTn"
hexmask.long 0x00 0.--31. 1. "CMCOR_31_0,Compare match timer constant register bit31 to 0 Note: Refer to section 155.1.3.5 CMT0 Register Access for the note regarding writing to or reading from this bit"
group.long 0x1000++0x03
line.long 0x00 "CMCLKE,CMCLKE is a 32-bit register which specifies clock supply to each channel"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
hexmask.long.word 0x00 7.--15. 1. "Reserved_7,Reserved These bits are always read as 1"
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bitfld.long 0x00 6. "Ch1clke," "0,1"
bitfld.long 0x00 5. "Ch0clke," "0,1"
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rbitfld.long 0x00 0.--4. "Reserved_0,Reserved These bits are always read as 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.end
tree "CMT1"
tree "CMT1_INST_0"
base ad:0xE6130000
group.long 0x00++0x03
line.long 0x00 "CM1STR0,CM[n]STR[m] (n=1-3)(m=0) is a 32-bit register which specify the operation of compare match timer counter (CM[n]CNT[m])"
hexmask.long.tbyte 0x00 9.--31. 1. "Reserved_9,Reserved These bits are always read as 0"
bitfld.long 0x00 8. "STR0RS,RCLK-Synchronous Counter Start/Stop Mode Select" "0: Normal operation Channel 0 starts or stops,1: RCLK-synchronous counter start/stop mode.."
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hexmask.long.byte 0x00 1.--7. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "STR0,Count Start 0 These bits specify start/halt of compare match timer counter 0 (CM[n]CNT0)" "0: CM[n]CNT0 halts,1: CM[n]CNT0 start counting"
group.long 0x10++0x03
line.long 0x00 "CM1CSR0,CM[n]CSR[m](n=1-3)(m=0) is a 32-bit register that indicates the occurrence of compare match enable interrupt and set the counter input clock"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
bitfld.long 0x00 15. "CMF,Compare Match Flag This flag indicates whether values of the compare match timer counter (CM[n]CNT0) and compare match timer constant register (CM[n]COR0) have matched or not" "0: CM[n]CNT0 and CM[n]COR0 values have not matched,1: CM[n]CNT0 and CM[n]COR0 values have matched"
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bitfld.long 0x00 14. "OVF,Overflow Flag This flag indicates whether the compare match timer counter (CM[n]CNT0) has overflowed or not" "0: CM[n]CNT0 has not overflowed [Clearing,1: CM[n]CNT0 has overflowed"
rbitfld.long 0x00 13. "WRFLG,Write State Flag Write access to CM[n]CNT0 is prohibited while this bit is 1" "0,1"
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bitfld.long 0x00 12. "CH0STTF,Channel 0 Start Flag When RCLK-synchronous channel 0 counter start/stop mode is selected this flag indicates whether the counter in channel 0 started on detecting an RCLK rising edge after 1 was written to the STR0 bit in CM[n]STR0" "0: Channel 0 counter has not started,1: Channel 0 counter has started"
bitfld.long 0x00 11. "CH0STPF,Channel 0 Stop Flag When RCLK-synchronous channel 0 counter start/stop mode is selected this flag indicates whether the counter in channel 0 stopped on detecting an RCLK rising edge after 1 was written to the STR0 bit in CM[n]STR0" "0: Channel 0 counter has not stopped,1: Channel 0 counter has stopped"
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bitfld.long 0x00 10. "CH0SSIE,Channel 0 Start/Stop Interrupt Enable When RCLK-synchronous channel 0 counter start/stop mode is selected this bit enables or disables an interrupt due to the start or stop of the counter in channel 0" "0: Disables an interrupt due to start or stop of,1: Enables an interrupt due to start or stop of"
bitfld.long 0x00 9. "CMS,Compare Match Timer Counter Size This bit and CM[n]CSRH0.CMSH select whether the compare match timer counter 0 (CM[n]CNTH0 [15:0] and CM[n]CNT0 [31:0]) is used as a 16-bit counter a 32-bit counter or a 48-bit counter" "0: Operates as a 32-bit counter,1: Operates as a 16-bit counter"
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bitfld.long 0x00 8. "CMM,Compare Match Mode Specify operation mode of the counter" "0: One-shot operation,1: Free-running operation"
rbitfld.long 0x00 7. "Reserved_7,Reserved This bit is always read as 0" "0,1"
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rbitfld.long 0x00 6. "Reserved_6,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 4.--5. "CMR_1_0,Compare Match Request These bits enable or disable internal interrupt request in a compare match" "0: Disables internal interrupt request,1: Setting prohibited,2: Enables an internal interrupt request,3: Setting prohibited"
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bitfld.long 0x00 3. "DBGIVD,Debug Mode Operation Select Sets the counter operation in debugging mode" "0: Stops the counter operation in debugging mode,1: Continues the counter operation even in"
bitfld.long 0x00 0.--2. "CKS_2_0,Clock Select These bits and CM[n]CSRH0.CKSH select the clock input to CM[n]CNT0" "?,?,?,?,4: RCLK/8,5: RCLK/32,6: RCLK/128,7: RCLK/1"
group.long 0x14++0x03
line.long 0x00 "CM1CNT0,CM[n]CNT[m](n=1-3)(m=0-7) is a 32-bit register which is used as an up-counter of each channel"
hexmask.long 0x00 0.--31. 1. "CMCNT_31_0,Compare match timer counter bit31 to 0 Note: For access to this register refer to section 155.2.3.5 Register Access"
group.long 0x18++0x03
line.long 0x00 "CM1COR0,CM[n]COR[m] is a 32-bit register which specify the compare match period of CM[n]CNT[m] for each channel"
hexmask.long 0x00 0.--31. 1. "CMCOR_31_0,Compare match timer constant register bit31 to 0 Note: For access to this register refer to section 155.2.3.5 Register Access"
group.long 0x20++0x03
line.long 0x00 "CM1CSRH0,CM[n]CSRH[m] is a 32-bit register which specify the counter size and input clocks"
hexmask.long.tbyte 0x00 10.--31. 1. "Reserved_10,Reserved These bits are always read as 0"
bitfld.long 0x00 9. "CMSH,Compare Match Timer Counter Size This bit and CM[n]CSR[m].CMS specify whether the compare match timer counter (CM[n]CNTH[m][15:0] and CM[n]CNT[m][31:0]) is used as a 16-bit counter a 32-bit counter or a 48-bit counter" "0: Operates as a 32-bit counter,1: Operates as a 16-bit counter"
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hexmask.long.byte 0x00 1.--8. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CKSH,Clock Select This bit and CM[n]CSR[m].CKS [2:0] select the clock input to CM[n]CNT[m]" "0,1"
group.long 0x24++0x03
line.long 0x00 "CM1CNTH0,CM[n]CNTH[m](n=1-3)(m=0-4) is a 32-bit register which is used as an up-counter for channel0 to 4"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
hexmask.long.word 0x00 0.--15. 1. "CMCNTH_15_0,Compare match timer counter H bit15 to 0 Note: For access to this register refer to section 155.2.3.5 Register Access"
group.long 0x28++0x03
line.long 0x00 "CM1CORH0,CM[n]CORH[m] is a 32-bit register which specify the compare match period with CM[n]CNTH[m] for channel0 to 4"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
hexmask.long.word 0x00 0.--15. 1. "CMCORH_15_0,Compare match timer constant register H bit15 to 0 Note: For access to this register refer to section 155.2.3.5 Register Access"
group.long 0x40++0x03
line.long 0x00 "CM1CSRM0,CM[n]CSRM[m] is a 32-bit register which resets to compare match timer match counter and sets the counter start/halt"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
rbitfld.long 0x00 15. "WRFLG,Write state flag" "0: CPEX?,1: RCLK"
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hexmask.long.word 0x00 2.--14. 1. "Reserved_2,Reserved These bits are always read as 0"
bitfld.long 0x00 1. "CMPCLR,Counter Clear [When writing]" "0: No operation,1: Clears counter When CMPCLR and"
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bitfld.long 0x00 0. "CMPSTART,Count Start This bit specifies start/halt of the compare match timer match counter (CM[n]CNTM[m]) of each channel" "0: CM[n]CNTM[m] Halts,1: CM[n]CNTM[m] Starts counting"
group.long 0x44++0x03
line.long 0x00 "CM1CNTM0,CM[n]CNTM[m] is a 32-bit register which is used as an up-counter"
hexmask.long 0x00 0.--31. 1. "CMCNTM_31_0,Compare match timer match counter bit31 to 0"
group.long 0x100++0x03
line.long 0x00 "CM1STR1,CM[n]STR[m] (n=1-3)(m=1-4) is a 32-bit register which specify the operation of compare match timer counter (CM[n]CNT[m])"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "STR0,Count Start 0 These bits specify start/halt of compare match timer counter (CM[n]STR[m])" "0: CM[n]STR[m] halts,1: CM[n]STR[m] starts counting"
group.long 0x110++0x03
line.long 0x00 "CM1CSR1,CM[n]CSR[m](n=1-3)(m=1-4) is a 32-bit register that indicates the occurrence of compare match enable interrupt and set the counter input clock"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
bitfld.long 0x00 15. "CMF,Compare Match Flag This flag indicates whether values of the compare match timer counter (CM[n]CNT[m]) and compare match timer constant register (CM[n]COR[m]) have matched or not" "0: CM[n]CNT[m] and CM[n]COR[m] values have not,1: CM[n]CNT[m] and CM[n]COR[m] values have matched"
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bitfld.long 0x00 14. "OVF,Overflow Flag This flag indicates whether the compare match timer counter (CM[n]CNT[m]) has overflowed or not" "0: CM[n]CNT[m] has not overflowed [Clearing,1: CM[n]CNT[m] has overflowed"
rbitfld.long 0x00 13. "WRFLG,Write State Flag Write access to CM[n]CNT[m] is prohibited while this this bit is 1" "0,1"
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rbitfld.long 0x00 10.--12. "Reserved_10,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 9. "CMS,Compare Match Timer Counter Size This bit and CM[n]CSRH[m].CMSH specify whether the compare match timer counter (CM[n]CNTH[m][15:0] and CM[n]CNT[m][31:0]) is used as a 16-bit counter a 32-bit counter or a 48-bit counter" "0: Operates as a 32-bit counter,1: Operates as a 16-bit counter"
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bitfld.long 0x00 8. "CMM,Compare Match Mode Specify counter operation mode" "0: One-shot operation,1: Free-running operation"
rbitfld.long 0x00 6.--7. "Reserved_6,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 4.--5. "CMR_1_0,Compare Match Request These bits enable or disable internal interrupt request in a compare match" "0: Disables internal interrupt request,1: Setting prohibited,2: Enables an internal interrupt request,3: Setting prohibited"
bitfld.long 0x00 3. "DBGIVD,Debug Mode Operation Select Sets the counter operation in debugging mode" "0: Stops the counter operation in debugging mode,1: Continues the counter operation even in"
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bitfld.long 0x00 0.--2. "CKS_2_0,Clock Select These bits and CM[n]CSRH[m].CKSH specify the input clock to CM[n]CNT[m]" "?,?,?,?,4: RCLK/8,5: RCLK/32,6: RCLK/128,7: RCLK/1"
group.long 0x114++0x03
line.long 0x00 "CM1CNT1,CM[n]CNT[m](n=1-3)(m=0-7) is a 32-bit register which is used as an up-counter of each channel"
hexmask.long 0x00 0.--31. 1. "CMCNT_31_0,Compare match timer counter bit31 to 0 Note: For access to this register refer to section 155.2.3.5 Register Access"
group.long 0x118++0x03
line.long 0x00 "CM1COR1,CM[n]COR[m] is a 32-bit register which specify the compare match period of CM[n]CNT[m] for each channel"
hexmask.long 0x00 0.--31. 1. "CMCOR_31_0,Compare match timer constant register bit31 to 0 Note: For access to this register refer to section 155.2.3.5 Register Access"
group.long 0x120++0x03
line.long 0x00 "CM1CSRH1,CM[n]CSRH[m] is a 32-bit register which specify the counter size and input clocks"
hexmask.long.tbyte 0x00 10.--31. 1. "Reserved_10,Reserved These bits are always read as 0"
bitfld.long 0x00 9. "CMSH,Compare Match Timer Counter Size This bit and CM[n]CSR[m].CMS specify whether the compare match timer counter (CM[n]CNTH[m][15:0] and CM[n]CNT[m][31:0]) is used as a 16-bit counter a 32-bit counter or a 48-bit counter" "0: Operates as a 32-bit counter,1: Operates as a 16-bit counter"
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hexmask.long.byte 0x00 1.--8. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CKSH,Clock Select This bit and CM[n]CSR[m].CKS [2:0] select the clock input to CM[n]CNT[m]" "0,1"
group.long 0x124++0x03
line.long 0x00 "CM1CNTH1,CM[n]CNTH[m](n=1-3)(m=0-4) is a 32-bit register which is used as an up-counter for channel0 to 4"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
hexmask.long.word 0x00 0.--15. 1. "CMCNTH_15_0,Compare match timer counter H bit15 to 0 Note: For access to this register refer to section 155.2.3.5 Register Access"
group.long 0x128++0x03
line.long 0x00 "CM1CORH1,CM[n]CORH[m] is a 32-bit register which specify the compare match period with CM[n]CNTH[m] for channel0 to 4"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
hexmask.long.word 0x00 0.--15. 1. "CMCORH_15_0,Compare match timer constant register H bit15 to 0 Note: For access to this register refer to section 155.2.3.5 Register Access"
group.long 0x200++0x03
line.long 0x00 "CM1STR2,CM[n]STR[m] (n=1-3)(m=1-4) is a 32-bit register which specify the operation of compare match timer counter (CM[n]CNT[m])"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "STR0,Count Start 0 These bits specify start/halt of compare match timer counter (CM[n]STR[m])" "0: CM[n]STR[m] halts,1: CM[n]STR[m] starts counting"
group.long 0x210++0x03
line.long 0x00 "CM1CSR2,CM[n]CSR[m](n=1-3)(m=1-4) is a 32-bit register that indicates the occurrence of compare match enable interrupt and set the counter input clock"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
bitfld.long 0x00 15. "CMF,Compare Match Flag This flag indicates whether values of the compare match timer counter (CM[n]CNT[m]) and compare match timer constant register (CM[n]COR[m]) have matched or not" "0: CM[n]CNT[m] and CM[n]COR[m] values have not,1: CM[n]CNT[m] and CM[n]COR[m] values have matched"
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bitfld.long 0x00 14. "OVF,Overflow Flag This flag indicates whether the compare match timer counter (CM[n]CNT[m]) has overflowed or not" "0: CM[n]CNT[m] has not overflowed [Clearing,1: CM[n]CNT[m] has overflowed"
rbitfld.long 0x00 13. "WRFLG,Write State Flag Write access to CM[n]CNT[m] is prohibited while this this bit is 1" "0,1"
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rbitfld.long 0x00 10.--12. "Reserved_10,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 9. "CMS,Compare Match Timer Counter Size This bit and CM[n]CSRH[m].CMSH specify whether the compare match timer counter (CM[n]CNTH[m][15:0] and CM[n]CNT[m][31:0]) is used as a 16-bit counter a 32-bit counter or a 48-bit counter" "0: Operates as a 32-bit counter,1: Operates as a 16-bit counter"
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bitfld.long 0x00 8. "CMM,Compare Match Mode Specify counter operation mode" "0: One-shot operation,1: Free-running operation"
rbitfld.long 0x00 6.--7. "Reserved_6,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 4.--5. "CMR_1_0,Compare Match Request These bits enable or disable internal interrupt request in a compare match" "0: Disables internal interrupt request,1: Setting prohibited,2: Enables an internal interrupt request,3: Setting prohibited"
bitfld.long 0x00 3. "DBGIVD,Debug Mode Operation Select Sets the counter operation in debugging mode" "0: Stops the counter operation in debugging mode,1: Continues the counter operation even in"
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bitfld.long 0x00 0.--2. "CKS_2_0,Clock Select These bits and CM[n]CSRH[m].CKSH specify the input clock to CM[n]CNT[m]" "?,?,?,?,4: RCLK/8,5: RCLK/32,6: RCLK/128,7: RCLK/1"
group.long 0x214++0x03
line.long 0x00 "CM1CNT2,CM[n]CNT[m](n=1-3)(m=0-7) is a 32-bit register which is used as an up-counter of each channel"
hexmask.long 0x00 0.--31. 1. "CMCNT_31_0,Compare match timer counter bit31 to 0 Note: For access to this register refer to section 155.2.3.5 Register Access"
group.long 0x218++0x03
line.long 0x00 "CM1COR2,CM[n]COR[m] is a 32-bit register which specify the compare match period of CM[n]CNT[m] for each channel"
hexmask.long 0x00 0.--31. 1. "CMCOR_31_0,Compare match timer constant register bit31 to 0 Note: For access to this register refer to section 155.2.3.5 Register Access"
group.long 0x220++0x03
line.long 0x00 "CM1CSRH2,CM[n]CSRH[m] is a 32-bit register which specify the counter size and input clocks"
hexmask.long.tbyte 0x00 10.--31. 1. "Reserved_10,Reserved These bits are always read as 0"
bitfld.long 0x00 9. "CMSH,Compare Match Timer Counter Size This bit and CM[n]CSR[m].CMS specify whether the compare match timer counter (CM[n]CNTH[m][15:0] and CM[n]CNT[m][31:0]) is used as a 16-bit counter a 32-bit counter or a 48-bit counter" "0: Operates as a 32-bit counter,1: Operates as a 16-bit counter"
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hexmask.long.byte 0x00 1.--8. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CKSH,Clock Select This bit and CM[n]CSR[m].CKS [2:0] select the clock input to CM[n]CNT[m]" "0,1"
group.long 0x224++0x03
line.long 0x00 "CM1CNTH2,CM[n]CNTH[m](n=1-3)(m=0-4) is a 32-bit register which is used as an up-counter for channel0 to 4"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
hexmask.long.word 0x00 0.--15. 1. "CMCNTH_15_0,Compare match timer counter H bit15 to 0 Note: For access to this register refer to section 155.2.3.5 Register Access"
group.long 0x228++0x03
line.long 0x00 "CM1CORH2,CM[n]CORH[m] is a 32-bit register which specify the compare match period with CM[n]CNTH[m] for channel0 to 4"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
hexmask.long.word 0x00 0.--15. 1. "CMCORH_15_0,Compare match timer constant register H bit15 to 0 Note: For access to this register refer to section 155.2.3.5 Register Access"
group.long 0x300++0x03
line.long 0x00 "CM1STR3,CM[n]STR[m] (n=1-3)(m=1-4) is a 32-bit register which specify the operation of compare match timer counter (CM[n]CNT[m])"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "STR0,Count Start 0 These bits specify start/halt of compare match timer counter (CM[n]STR[m])" "0: CM[n]STR[m] halts,1: CM[n]STR[m] starts counting"
group.long 0x310++0x03
line.long 0x00 "CM1CSR3,CM[n]CSR[m](n=1-3)(m=1-4) is a 32-bit register that indicates the occurrence of compare match enable interrupt and set the counter input clock"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
bitfld.long 0x00 15. "CMF,Compare Match Flag This flag indicates whether values of the compare match timer counter (CM[n]CNT[m]) and compare match timer constant register (CM[n]COR[m]) have matched or not" "0: CM[n]CNT[m] and CM[n]COR[m] values have not,1: CM[n]CNT[m] and CM[n]COR[m] values have matched"
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bitfld.long 0x00 14. "OVF,Overflow Flag This flag indicates whether the compare match timer counter (CM[n]CNT[m]) has overflowed or not" "0: CM[n]CNT[m] has not overflowed [Clearing,1: CM[n]CNT[m] has overflowed"
rbitfld.long 0x00 13. "WRFLG,Write State Flag Write access to CM[n]CNT[m] is prohibited while this this bit is 1" "0,1"
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rbitfld.long 0x00 10.--12. "Reserved_10,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 9. "CMS,Compare Match Timer Counter Size This bit and CM[n]CSRH[m].CMSH specify whether the compare match timer counter (CM[n]CNTH[m][15:0] and CM[n]CNT[m][31:0]) is used as a 16-bit counter a 32-bit counter or a 48-bit counter" "0: Operates as a 32-bit counter,1: Operates as a 16-bit counter"
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bitfld.long 0x00 8. "CMM,Compare Match Mode Specify counter operation mode" "0: One-shot operation,1: Free-running operation"
rbitfld.long 0x00 6.--7. "Reserved_6,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 4.--5. "CMR_1_0,Compare Match Request These bits enable or disable internal interrupt request in a compare match" "0: Disables internal interrupt request,1: Setting prohibited,2: Enables an internal interrupt request,3: Setting prohibited"
bitfld.long 0x00 3. "DBGIVD,Debug Mode Operation Select Sets the counter operation in debugging mode" "0: Stops the counter operation in debugging mode,1: Continues the counter operation even in"
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bitfld.long 0x00 0.--2. "CKS_2_0,Clock Select These bits and CM[n]CSRH[m].CKSH specify the input clock to CM[n]CNT[m]" "?,?,?,?,4: RCLK/8,5: RCLK/32,6: RCLK/128,7: RCLK/1"
group.long 0x314++0x03
line.long 0x00 "CM1CNT3,CM[n]CNT[m](n=1-3)(m=0-7) is a 32-bit register which is used as an up-counter of each channel"
hexmask.long 0x00 0.--31. 1. "CMCNT_31_0,Compare match timer counter bit31 to 0 Note: For access to this register refer to section 155.2.3.5 Register Access"
group.long 0x318++0x03
line.long 0x00 "CM1COR3,CM[n]COR[m] is a 32-bit register which specify the compare match period of CM[n]CNT[m] for each channel"
hexmask.long 0x00 0.--31. 1. "CMCOR_31_0,Compare match timer constant register bit31 to 0 Note: For access to this register refer to section 155.2.3.5 Register Access"
group.long 0x320++0x03
line.long 0x00 "CM1CSRH3,CM[n]CSRH[m] is a 32-bit register which specify the counter size and input clocks"
hexmask.long.tbyte 0x00 10.--31. 1. "Reserved_10,Reserved These bits are always read as 0"
bitfld.long 0x00 9. "CMSH,Compare Match Timer Counter Size This bit and CM[n]CSR[m].CMS specify whether the compare match timer counter (CM[n]CNTH[m][15:0] and CM[n]CNT[m][31:0]) is used as a 16-bit counter a 32-bit counter or a 48-bit counter" "0: Operates as a 32-bit counter,1: Operates as a 16-bit counter"
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hexmask.long.byte 0x00 1.--8. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CKSH,Clock Select This bit and CM[n]CSR[m].CKS [2:0] select the clock input to CM[n]CNT[m]" "0,1"
group.long 0x324++0x03
line.long 0x00 "CM1CNTH3,CM[n]CNTH[m](n=1-3)(m=0-4) is a 32-bit register which is used as an up-counter for channel0 to 4"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
hexmask.long.word 0x00 0.--15. 1. "CMCNTH_15_0,Compare match timer counter H bit15 to 0 Note: For access to this register refer to section 155.2.3.5 Register Access"
group.long 0x328++0x03
line.long 0x00 "CM1CORH3,CM[n]CORH[m] is a 32-bit register which specify the compare match period with CM[n]CNTH[m] for channel0 to 4"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
hexmask.long.word 0x00 0.--15. 1. "CMCORH_15_0,Compare match timer constant register H bit15 to 0 Note: For access to this register refer to section 155.2.3.5 Register Access"
group.long 0x330++0x03
line.long 0x00 "CM1CNT3BK0,CM[n]CNT[m]BK0 is a 32-bit register which stores a copy of the CM[n]CNT[m] value immediately after the counter in channel 0 stops in RCLK-synchronous channel 0 counter start/stop mode"
hexmask.long 0x00 0.--31. 1. "CMCNT3BK0_31_0,Compare match timer counter 3 backup 0 bit31 to 0"
group.long 0x334++0x03
line.long 0x00 "CM1CNT3BK1,CM[n]CNT[m]BK1 is a 32-bit register which stores a copy of the CM[n]CNT[m] value immediately after the counter in channel 0 starts in RCLK-synchronous channel 0 counter start/stop mode"
hexmask.long 0x00 0.--31. 1. "CMCNT3BK1_31_0,Compare match timer counter 3 backup 1 bit31 to 0"
group.long 0x340++0x03
line.long 0x00 "CM1CSRM3,CM[n]CSRM[m] is a 32-bit register which resets to compare match timer match counter and sets the counter start/halt"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
rbitfld.long 0x00 15. "WRFLG,Write state flag" "0: CPEX?,1: RCLK"
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hexmask.long.word 0x00 2.--14. 1. "Reserved_2,Reserved These bits are always read as 0"
bitfld.long 0x00 1. "CMPCLR,Counter Clear [When writing]" "0: No operation,1: Clears counter When CMPCLR and"
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bitfld.long 0x00 0. "CMPSTART,Count Start This bit specifies start/halt of the compare match timer match counter (CM[n]CNTM[m]) of each channel" "0: CM[n]CNTM[m] Halts,1: CM[n]CNTM[m] Starts counting"
group.long 0x344++0x03
line.long 0x00 "CM1CNTM3,CM[n]CNTM[m] is a 32-bit register which is used as an up-counter"
hexmask.long 0x00 0.--31. 1. "CMCNTM_31_0,Compare match timer match counter bit31 to 0"
group.long 0x400++0x03
line.long 0x00 "CM1STR4,CM[n]STR[m] (n=1-3)(m=1-4) is a 32-bit register which specify the operation of compare match timer counter (CM[n]CNT[m])"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "STR0,Count Start 0 These bits specify start/halt of compare match timer counter (CM[n]STR[m])" "0: CM[n]STR[m] halts,1: CM[n]STR[m] starts counting"
group.long 0x410++0x03
line.long 0x00 "CM1CSR4,CM[n]CSR[m](n=1-3)(m=1-4) is a 32-bit register that indicates the occurrence of compare match enable interrupt and set the counter input clock"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
bitfld.long 0x00 15. "CMF,Compare Match Flag This flag indicates whether values of the compare match timer counter (CM[n]CNT[m]) and compare match timer constant register (CM[n]COR[m]) have matched or not" "0: CM[n]CNT[m] and CM[n]COR[m] values have not,1: CM[n]CNT[m] and CM[n]COR[m] values have matched"
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bitfld.long 0x00 14. "OVF,Overflow Flag This flag indicates whether the compare match timer counter (CM[n]CNT[m]) has overflowed or not" "0: CM[n]CNT[m] has not overflowed [Clearing,1: CM[n]CNT[m] has overflowed"
rbitfld.long 0x00 13. "WRFLG,Write State Flag Write access to CM[n]CNT[m] is prohibited while this this bit is 1" "0,1"
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rbitfld.long 0x00 10.--12. "Reserved_10,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 9. "CMS,Compare Match Timer Counter Size This bit and CM[n]CSRH[m].CMSH specify whether the compare match timer counter (CM[n]CNTH[m][15:0] and CM[n]CNT[m][31:0]) is used as a 16-bit counter a 32-bit counter or a 48-bit counter" "0: Operates as a 32-bit counter,1: Operates as a 16-bit counter"
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bitfld.long 0x00 8. "CMM,Compare Match Mode Specify counter operation mode" "0: One-shot operation,1: Free-running operation"
rbitfld.long 0x00 6.--7. "Reserved_6,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 4.--5. "CMR_1_0,Compare Match Request These bits enable or disable internal interrupt request in a compare match" "0: Disables internal interrupt request,1: Setting prohibited,2: Enables an internal interrupt request,3: Setting prohibited"
bitfld.long 0x00 3. "DBGIVD,Debug Mode Operation Select Sets the counter operation in debugging mode" "0: Stops the counter operation in debugging mode,1: Continues the counter operation even in"
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bitfld.long 0x00 0.--2. "CKS_2_0,Clock Select These bits and CM[n]CSRH[m].CKSH specify the input clock to CM[n]CNT[m]" "?,?,?,?,4: RCLK/8,5: RCLK/32,6: RCLK/128,7: RCLK/1"
group.long 0x414++0x03
line.long 0x00 "CM1CNT4,CM[n]CNT[m](n=1-3)(m=0-7) is a 32-bit register which is used as an up-counter of each channel"
hexmask.long 0x00 0.--31. 1. "CMCNT_31_0,Compare match timer counter bit31 to 0 Note: For access to this register refer to section 155.2.3.5 Register Access"
group.long 0x418++0x03
line.long 0x00 "CM1COR4,CM[n]COR[m] is a 32-bit register which specify the compare match period of CM[n]CNT[m] for each channel"
hexmask.long 0x00 0.--31. 1. "CMCOR_31_0,Compare match timer constant register bit31 to 0 Note: For access to this register refer to section 155.2.3.5 Register Access"
group.long 0x420++0x03
line.long 0x00 "CM1CSRH4,CM[n]CSRH[m] is a 32-bit register which specify the counter size and input clocks"
hexmask.long.tbyte 0x00 10.--31. 1. "Reserved_10,Reserved These bits are always read as 0"
bitfld.long 0x00 9. "CMSH,Compare Match Timer Counter Size This bit and CM[n]CSR[m].CMS specify whether the compare match timer counter (CM[n]CNTH[m][15:0] and CM[n]CNT[m][31:0]) is used as a 16-bit counter a 32-bit counter or a 48-bit counter" "0: Operates as a 32-bit counter,1: Operates as a 16-bit counter"
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hexmask.long.byte 0x00 1.--8. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CKSH,Clock Select This bit and CM[n]CSR[m].CKS [2:0] select the clock input to CM[n]CNT[m]" "0,1"
group.long 0x424++0x03
line.long 0x00 "CM1CNTH4,CM[n]CNTH[m](n=1-3)(m=0-4) is a 32-bit register which is used as an up-counter for channel0 to 4"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
hexmask.long.word 0x00 0.--15. 1. "CMCNTH_15_0,Compare match timer counter H bit15 to 0 Note: For access to this register refer to section 155.2.3.5 Register Access"
group.long 0x428++0x03
line.long 0x00 "CM1CORH4,CM[n]CORH[m] is a 32-bit register which specify the compare match period with CM[n]CNTH[m] for channel0 to 4"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
hexmask.long.word 0x00 0.--15. 1. "CMCORH_15_0,Compare match timer constant register H bit15 to 0 Note: For access to this register refer to section 155.2.3.5 Register Access"
group.long 0x500++0x03
line.long 0x00 "CM1STR5,CM[n]STR[m] (n=1-3)(m=5-7) is a 32-bit register which specify the operation of compare match timer counter (CM[n]CNT[m])"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "STR0,Count Start 0 These bits specify start/halt of compare match timer counter (CM[n]STR[m])" "0: CM[n]STR[m] halts,1: CM[n]STR[m] starts counting"
group.long 0x510++0x03
line.long 0x00 "CM1CSR5,CM[n]CSR[m](n=1-3)(m=5-7) is a 32-bit register that indicates the occurrence of compare match enable interrupt and set the counter input clock"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
bitfld.long 0x00 15. "CMF,Compare Match Flag This flag indicates whether values of the compare match timer counter (CM[n]CNT[m]) and compare match timer constant register (CM[n]COR[m]) have matched or not" "0: CM[n]CNT[m] and CM[n]COR[m] values have not,1: CM[n]CNT[m] and CM[n]COR[m] values have matched"
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bitfld.long 0x00 14. "OVF,Overflow Flag This flag indicates whether the compare match timer counter (CM[n]CNT[m]) has overflowed or not" "0: CM[n]CNT[m] has not overflowed [Clearing,1: CM[n]CNT[m] has overflowed"
rbitfld.long 0x00 13. "WRFLG,Write State Flag Write access to CM[n]CNT[m] is prohibited while this this bit is 1" "0,1"
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rbitfld.long 0x00 10.--12. "Reserved_10,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 9. "CMS,Compare Match Timer Counter Size Selects whether the compare match timer counter (CM[n]CNT[m]) is used as a 16-bit counter or a 32-bit counter" "0: Operates as a 32-bit counter,1: Operates as a 16-bit counter"
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bitfld.long 0x00 8. "CMM,Compare Match Mode Specify counter operation mode" "0: One-shot operation,1: Free-running operation"
rbitfld.long 0x00 6.--7. "Reserved_6,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 4.--5. "CMR_1_0,Compare Match Request These bits enable or disable internal interrupt request in a compare match" "0: Disables internal interrupt request,1: Setting prohibited,2: Enables an internal interrupt request,3: Setting prohibited"
bitfld.long 0x00 3. "DBGIVD,Debug Mode Operation Select Sets the counter operation in debugging mode" "0: Stops the counter operation in debugging mode,1: Continues the counter operation even in"
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bitfld.long 0x00 0.--2. "CKS_2_0,Clock Select These bits select the clock input to CM[n]CNT[m]" "0: Setting prohibited,1: Setting prohibited,2: Setting prohibited,3: Setting prohibited,4: RCLK/8,5: RCLK/32,6: RCLK/128,7: RCLK/1"
group.long 0x514++0x03
line.long 0x00 "CM1CNT5,CM[n]CNT[m](n=1-3)(m=0-7) is a 32-bit register which is used as an up-counter of each channel"
hexmask.long 0x00 0.--31. 1. "CMCNT_31_0,Compare match timer counter bit31 to 0 Note: For access to this register refer to section 155.2.3.5 Register Access"
group.long 0x518++0x03
line.long 0x00 "CM1COR5,CM[n]COR[m] is a 32-bit register which specify the compare match period of CM[n]CNT[m] for each channel"
hexmask.long 0x00 0.--31. 1. "CMCOR_31_0,Compare match timer constant register bit31 to 0 Note: For access to this register refer to section 155.2.3.5 Register Access"
group.long 0x600++0x03
line.long 0x00 "CM1STR6,CM[n]STR[m] (n=1-3)(m=5-7) is a 32-bit register which specify the operation of compare match timer counter (CM[n]CNT[m])"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "STR0,Count Start 0 These bits specify start/halt of compare match timer counter (CM[n]STR[m])" "0: CM[n]STR[m] halts,1: CM[n]STR[m] starts counting"
group.long 0x610++0x03
line.long 0x00 "CM1CSR6,CM[n]CSR[m](n=1-3)(m=5-7) is a 32-bit register that indicates the occurrence of compare match enable interrupt and set the counter input clock"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
bitfld.long 0x00 15. "CMF,Compare Match Flag This flag indicates whether values of the compare match timer counter (CM[n]CNT[m]) and compare match timer constant register (CM[n]COR[m]) have matched or not" "0: CM[n]CNT[m] and CM[n]COR[m] values have not,1: CM[n]CNT[m] and CM[n]COR[m] values have matched"
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bitfld.long 0x00 14. "OVF,Overflow Flag This flag indicates whether the compare match timer counter (CM[n]CNT[m]) has overflowed or not" "0: CM[n]CNT[m] has not overflowed [Clearing,1: CM[n]CNT[m] has overflowed"
rbitfld.long 0x00 13. "WRFLG,Write State Flag Write access to CM[n]CNT[m] is prohibited while this this bit is 1" "0,1"
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rbitfld.long 0x00 10.--12. "Reserved_10,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 9. "CMS,Compare Match Timer Counter Size Selects whether the compare match timer counter (CM[n]CNT[m]) is used as a 16-bit counter or a 32-bit counter" "0: Operates as a 32-bit counter,1: Operates as a 16-bit counter"
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bitfld.long 0x00 8. "CMM,Compare Match Mode Specify counter operation mode" "0: One-shot operation,1: Free-running operation"
rbitfld.long 0x00 6.--7. "Reserved_6,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 4.--5. "CMR_1_0,Compare Match Request These bits enable or disable internal interrupt request in a compare match" "0: Disables internal interrupt request,1: Setting prohibited,2: Enables an internal interrupt request,3: Setting prohibited"
bitfld.long 0x00 3. "DBGIVD,Debug Mode Operation Select Sets the counter operation in debugging mode" "0: Stops the counter operation in debugging mode,1: Continues the counter operation even in"
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bitfld.long 0x00 0.--2. "CKS_2_0,Clock Select These bits select the clock input to CM[n]CNT[m]" "0: Setting prohibited,1: Setting prohibited,2: Setting prohibited,3: Setting prohibited,4: RCLK/8,5: RCLK/32,6: RCLK/128,7: RCLK/1"
group.long 0x614++0x03
line.long 0x00 "CM1CNT6,CM[n]CNT[m](n=1-3)(m=0-7) is a 32-bit register which is used as an up-counter of each channel"
hexmask.long 0x00 0.--31. 1. "CMCNT_31_0,Compare match timer counter bit31 to 0 Note: For access to this register refer to section 155.2.3.5 Register Access"
group.long 0x618++0x03
line.long 0x00 "CM1COR6,CM[n]COR[m] is a 32-bit register which specify the compare match period of CM[n]CNT[m] for each channel"
hexmask.long 0x00 0.--31. 1. "CMCOR_31_0,Compare match timer constant register bit31 to 0 Note: For access to this register refer to section 155.2.3.5 Register Access"
group.long 0x700++0x03
line.long 0x00 "CM1STR7,CM[n]STR[m] (n=1-3)(m=5-7) is a 32-bit register which specify the operation of compare match timer counter (CM[n]CNT[m])"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "STR0,Count Start 0 These bits specify start/halt of compare match timer counter (CM[n]STR[m])" "0: CM[n]STR[m] halts,1: CM[n]STR[m] starts counting"
group.long 0x710++0x03
line.long 0x00 "CM1CSR7,CM[n]CSR[m](n=1-3)(m=5-7) is a 32-bit register that indicates the occurrence of compare match enable interrupt and set the counter input clock"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
bitfld.long 0x00 15. "CMF,Compare Match Flag This flag indicates whether values of the compare match timer counter (CM[n]CNT[m]) and compare match timer constant register (CM[n]COR[m]) have matched or not" "0: CM[n]CNT[m] and CM[n]COR[m] values have not,1: CM[n]CNT[m] and CM[n]COR[m] values have matched"
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bitfld.long 0x00 14. "OVF,Overflow Flag This flag indicates whether the compare match timer counter (CM[n]CNT[m]) has overflowed or not" "0: CM[n]CNT[m] has not overflowed [Clearing,1: CM[n]CNT[m] has overflowed"
rbitfld.long 0x00 13. "WRFLG,Write State Flag Write access to CM[n]CNT[m] is prohibited while this this bit is 1" "0,1"
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rbitfld.long 0x00 10.--12. "Reserved_10,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 9. "CMS,Compare Match Timer Counter Size Selects whether the compare match timer counter (CM[n]CNT[m]) is used as a 16-bit counter or a 32-bit counter" "0: Operates as a 32-bit counter,1: Operates as a 16-bit counter"
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bitfld.long 0x00 8. "CMM,Compare Match Mode Specify counter operation mode" "0: One-shot operation,1: Free-running operation"
rbitfld.long 0x00 6.--7. "Reserved_6,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 4.--5. "CMR_1_0,Compare Match Request These bits enable or disable internal interrupt request in a compare match" "0: Disables internal interrupt request,1: Setting prohibited,2: Enables an internal interrupt request,3: Setting prohibited"
bitfld.long 0x00 3. "DBGIVD,Debug Mode Operation Select Sets the counter operation in debugging mode" "0: Stops the counter operation in debugging mode,1: Continues the counter operation even in"
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bitfld.long 0x00 0.--2. "CKS_2_0,Clock Select These bits select the clock input to CM[n]CNT[m]" "0: Setting prohibited,1: Setting prohibited,2: Setting prohibited,3: Setting prohibited,4: RCLK/8,5: RCLK/32,6: RCLK/128,7: RCLK/1"
group.long 0x714++0x03
line.long 0x00 "CM1CNT7,CM[n]CNT[m](n=1-3)(m=0-7) is a 32-bit register which is used as an up-counter of each channel"
hexmask.long 0x00 0.--31. 1. "CMCNT_31_0,Compare match timer counter bit31 to 0 Note: For access to this register refer to section 155.2.3.5 Register Access"
group.long 0x718++0x03
line.long 0x00 "CM1COR7,CM[n]COR[m] is a 32-bit register which specify the compare match period of CM[n]CNT[m] for each channel"
hexmask.long 0x00 0.--31. 1. "CMCOR_31_0,Compare match timer constant register bit31 to 0 Note: For access to this register refer to section 155.2.3.5 Register Access"
group.long 0x1000++0x03
line.long 0x00 "CM1CLKE,CM[n]CLKE is a 32bits register which specify clock supply to each channel"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 1"
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bitfld.long 0x00 7. "Ch7clke," "0,1"
bitfld.long 0x00 6. "Ch6clke," "0,1"
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bitfld.long 0x00 5. "Ch5clke," "0,1"
bitfld.long 0x00 4. "Ch4clke," "0,1"
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bitfld.long 0x00 3. "Ch3clke," "0,1"
bitfld.long 0x00 2. "Ch2clke," "0,1"
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bitfld.long 0x00 1. "Ch1clke," "0,1"
bitfld.long 0x00 0. "Ch0clke," "0,1"
tree.end
tree "CMT1_INST_1"
base ad:0xE6140000
group.long 0x00++0x03
line.long 0x00 "CM2STR0,CM[n]STR[m] (n=1-3)(m=0) is a 32-bit register which specify the operation of compare match timer counter (CM[n]CNT[m])"
hexmask.long.tbyte 0x00 9.--31. 1. "Reserved_9,Reserved These bits are always read as 0"
bitfld.long 0x00 8. "STR0RS,RCLK-Synchronous Counter Start/Stop Mode Select" "0: Normal operation Channel 0 starts or stops,1: RCLK-synchronous counter start/stop mode.."
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hexmask.long.byte 0x00 1.--7. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "STR0,Count Start 0 These bits specify start/halt of compare match timer counter 0 (CM[n]CNT0)" "0: CM[n]CNT0 halts,1: CM[n]CNT0 start counting"
group.long 0x10++0x03
line.long 0x00 "CM2CSR0,CM[n]CSR[m](n=1-3)(m=0) is a 32-bit register that indicates the occurrence of compare match enable interrupt and set the counter input clock"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
bitfld.long 0x00 15. "CMF,Compare Match Flag This flag indicates whether values of the compare match timer counter (CM[n]CNT0) and compare match timer constant register (CM[n]COR0) have matched or not" "0: CM[n]CNT0 and CM[n]COR0 values have not matched,1: CM[n]CNT0 and CM[n]COR0 values have matched"
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bitfld.long 0x00 14. "OVF,Overflow Flag This flag indicates whether the compare match timer counter (CM[n]CNT0) has overflowed or not" "0: CM[n]CNT0 has not overflowed [Clearing,1: CM[n]CNT0 has overflowed"
rbitfld.long 0x00 13. "WRFLG,Write State Flag Write access to CM[n]CNT0 is prohibited while this bit is 1" "0,1"
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bitfld.long 0x00 12. "CH0STTF,Channel 0 Start Flag When RCLK-synchronous channel 0 counter start/stop mode is selected this flag indicates whether the counter in channel 0 started on detecting an RCLK rising edge after 1 was written to the STR0 bit in CM[n]STR0" "0: Channel 0 counter has not started,1: Channel 0 counter has started"
bitfld.long 0x00 11. "CH0STPF,Channel 0 Stop Flag When RCLK-synchronous channel 0 counter start/stop mode is selected this flag indicates whether the counter in channel 0 stopped on detecting an RCLK rising edge after 1 was written to the STR0 bit in CM[n]STR0" "0: Channel 0 counter has not stopped,1: Channel 0 counter has stopped"
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bitfld.long 0x00 10. "CH0SSIE,Channel 0 Start/Stop Interrupt Enable When RCLK-synchronous channel 0 counter start/stop mode is selected this bit enables or disables an interrupt due to the start or stop of the counter in channel 0" "0: Disables an interrupt due to start or stop of,1: Enables an interrupt due to start or stop of"
bitfld.long 0x00 9. "CMS,Compare Match Timer Counter Size This bit and CM[n]CSRH0.CMSH select whether the compare match timer counter 0 (CM[n]CNTH0 [15:0] and CM[n]CNT0 [31:0]) is used as a 16-bit counter a 32-bit counter or a 48-bit counter" "0: Operates as a 32-bit counter,1: Operates as a 16-bit counter"
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bitfld.long 0x00 8. "CMM,Compare Match Mode Specify operation mode of the counter" "0: One-shot operation,1: Free-running operation"
rbitfld.long 0x00 7. "Reserved_7,Reserved This bit is always read as 0" "0,1"
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rbitfld.long 0x00 6. "Reserved_6,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 4.--5. "CMR_1_0,Compare Match Request These bits enable or disable internal interrupt request in a compare match" "0: Disables internal interrupt request,1: Setting prohibited,2: Enables an internal interrupt request,3: Setting prohibited"
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bitfld.long 0x00 3. "DBGIVD,Debug Mode Operation Select Sets the counter operation in debugging mode" "0: Stops the counter operation in debugging mode,1: Continues the counter operation even in"
bitfld.long 0x00 0.--2. "CKS_2_0,Clock Select These bits and CM[n]CSRH0.CKSH select the clock input to CM[n]CNT0" "?,?,?,?,4: RCLK/8,5: RCLK/32,6: RCLK/128,7: RCLK/1"
group.long 0x14++0x03
line.long 0x00 "CM2CNT0,CM[n]CNT[m](n=1-3)(m=0-7) is a 32-bit register which is used as an up-counter of each channel"
hexmask.long 0x00 0.--31. 1. "CMCNT_31_0,Compare match timer counter bit31 to 0 Note: For access to this register refer to section 155.2.3.5 Register Access"
group.long 0x18++0x03
line.long 0x00 "CM2COR0,CM[n]COR[m] is a 32-bit register which specify the compare match period of CM[n]CNT[m] for each channel"
hexmask.long 0x00 0.--31. 1. "CMCOR_31_0,Compare match timer constant register bit31 to 0 Note: For access to this register refer to section 155.2.3.5 Register Access"
group.long 0x20++0x03
line.long 0x00 "CM2CSRH0,CM[n]CSRH[m] is a 32-bit register which specify the counter size and input clocks"
hexmask.long.tbyte 0x00 10.--31. 1. "Reserved_10,Reserved These bits are always read as 0"
bitfld.long 0x00 9. "CMSH,Compare Match Timer Counter Size This bit and CM[n]CSR[m].CMS specify whether the compare match timer counter (CM[n]CNTH[m][15:0] and CM[n]CNT[m][31:0]) is used as a 16-bit counter a 32-bit counter or a 48-bit counter" "0: Operates as a 32-bit counter,1: Operates as a 16-bit counter"
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hexmask.long.byte 0x00 1.--8. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CKSH,Clock Select This bit and CM[n]CSR[m].CKS [2:0] select the clock input to CM[n]CNT[m]" "0,1"
group.long 0x24++0x03
line.long 0x00 "CM2CNTH0,CM[n]CNTH[m](n=1-3)(m=0-4) is a 32-bit register which is used as an up-counter for channel0 to 4"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
hexmask.long.word 0x00 0.--15. 1. "CMCNTH_15_0,Compare match timer counter H bit15 to 0 Note: For access to this register refer to section 155.2.3.5 Register Access"
group.long 0x28++0x03
line.long 0x00 "CM2CORH0,CM[n]CORH[m] is a 32-bit register which specify the compare match period with CM[n]CNTH[m] for channel0 to 4"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
hexmask.long.word 0x00 0.--15. 1. "CMCORH_15_0,Compare match timer constant register H bit15 to 0 Note: For access to this register refer to section 155.2.3.5 Register Access"
group.long 0x40++0x03
line.long 0x00 "CM2CSRM0,CM[n]CSRM[m] is a 32-bit register which resets to compare match timer match counter and sets the counter start/halt"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
rbitfld.long 0x00 15. "WRFLG,Write state flag" "0: CPEX?,1: RCLK"
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hexmask.long.word 0x00 2.--14. 1. "Reserved_2,Reserved These bits are always read as 0"
bitfld.long 0x00 1. "CMPCLR,Counter Clear [When writing]" "0: No operation,1: Clears counter When CMPCLR and"
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bitfld.long 0x00 0. "CMPSTART,Count Start This bit specifies start/halt of the compare match timer match counter (CM[n]CNTM[m]) of each channel" "0: CM[n]CNTM[m] Halts,1: CM[n]CNTM[m] Starts counting"
group.long 0x44++0x03
line.long 0x00 "CM2CNTM0,CM[n]CNTM[m] is a 32-bit register which is used as an up-counter"
hexmask.long 0x00 0.--31. 1. "CMCNTM_31_0,Compare match timer match counter bit31 to 0"
group.long 0x100++0x03
line.long 0x00 "CM2STR1,CM[n]STR[m] (n=1-3)(m=1-4) is a 32-bit register which specify the operation of compare match timer counter (CM[n]CNT[m])"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "STR0,Count Start 0 These bits specify start/halt of compare match timer counter (CM[n]STR[m])" "0: CM[n]STR[m] halts,1: CM[n]STR[m] starts counting"
group.long 0x110++0x03
line.long 0x00 "CM2CSR1,CM[n]CSR[m](n=1-3)(m=1-4) is a 32-bit register that indicates the occurrence of compare match enable interrupt and set the counter input clock"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
bitfld.long 0x00 15. "CMF,Compare Match Flag This flag indicates whether values of the compare match timer counter (CM[n]CNT[m]) and compare match timer constant register (CM[n]COR[m]) have matched or not" "0: CM[n]CNT[m] and CM[n]COR[m] values have not,1: CM[n]CNT[m] and CM[n]COR[m] values have matched"
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bitfld.long 0x00 14. "OVF,Overflow Flag This flag indicates whether the compare match timer counter (CM[n]CNT[m]) has overflowed or not" "0: CM[n]CNT[m] has not overflowed [Clearing,1: CM[n]CNT[m] has overflowed"
rbitfld.long 0x00 13. "WRFLG,Write State Flag Write access to CM[n]CNT[m] is prohibited while this this bit is 1" "0,1"
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rbitfld.long 0x00 10.--12. "Reserved_10,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 9. "CMS,Compare Match Timer Counter Size This bit and CM[n]CSRH[m].CMSH specify whether the compare match timer counter (CM[n]CNTH[m][15:0] and CM[n]CNT[m][31:0]) is used as a 16-bit counter a 32-bit counter or a 48-bit counter" "0: Operates as a 32-bit counter,1: Operates as a 16-bit counter"
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bitfld.long 0x00 8. "CMM,Compare Match Mode Specify counter operation mode" "0: One-shot operation,1: Free-running operation"
rbitfld.long 0x00 6.--7. "Reserved_6,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 4.--5. "CMR_1_0,Compare Match Request These bits enable or disable internal interrupt request in a compare match" "0: Disables internal interrupt request,1: Setting prohibited,2: Enables an internal interrupt request,3: Setting prohibited"
bitfld.long 0x00 3. "DBGIVD,Debug Mode Operation Select Sets the counter operation in debugging mode" "0: Stops the counter operation in debugging mode,1: Continues the counter operation even in"
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bitfld.long 0x00 0.--2. "CKS_2_0,Clock Select These bits and CM[n]CSRH[m].CKSH specify the input clock to CM[n]CNT[m]" "?,?,?,?,4: RCLK/8,5: RCLK/32,6: RCLK/128,7: RCLK/1"
group.long 0x114++0x03
line.long 0x00 "CM2CNT1,CM[n]CNT[m](n=1-3)(m=0-7) is a 32-bit register which is used as an up-counter of each channel"
hexmask.long 0x00 0.--31. 1. "CMCNT_31_0,Compare match timer counter bit31 to 0 Note: For access to this register refer to section 155.2.3.5 Register Access"
group.long 0x118++0x03
line.long 0x00 "CM2COR1,CM[n]COR[m] is a 32-bit register which specify the compare match period of CM[n]CNT[m] for each channel"
hexmask.long 0x00 0.--31. 1. "CMCOR_31_0,Compare match timer constant register bit31 to 0 Note: For access to this register refer to section 155.2.3.5 Register Access"
group.long 0x120++0x03
line.long 0x00 "CM2CSRH1,CM[n]CSRH[m] is a 32-bit register which specify the counter size and input clocks"
hexmask.long.tbyte 0x00 10.--31. 1. "Reserved_10,Reserved These bits are always read as 0"
bitfld.long 0x00 9. "CMSH,Compare Match Timer Counter Size This bit and CM[n]CSR[m].CMS specify whether the compare match timer counter (CM[n]CNTH[m][15:0] and CM[n]CNT[m][31:0]) is used as a 16-bit counter a 32-bit counter or a 48-bit counter" "0: Operates as a 32-bit counter,1: Operates as a 16-bit counter"
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hexmask.long.byte 0x00 1.--8. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CKSH,Clock Select This bit and CM[n]CSR[m].CKS [2:0] select the clock input to CM[n]CNT[m]" "0,1"
group.long 0x124++0x03
line.long 0x00 "CM2CNTH1,CM[n]CNTH[m](n=1-3)(m=0-4) is a 32-bit register which is used as an up-counter for channel0 to 4"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
hexmask.long.word 0x00 0.--15. 1. "CMCNTH_15_0,Compare match timer counter H bit15 to 0 Note: For access to this register refer to section 155.2.3.5 Register Access"
group.long 0x128++0x03
line.long 0x00 "CM2CORH1,CM[n]CORH[m] is a 32-bit register which specify the compare match period with CM[n]CNTH[m] for channel0 to 4"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
hexmask.long.word 0x00 0.--15. 1. "CMCORH_15_0,Compare match timer constant register H bit15 to 0 Note: For access to this register refer to section 155.2.3.5 Register Access"
group.long 0x200++0x03
line.long 0x00 "CM2STR2,CM[n]STR[m] (n=1-3)(m=1-4) is a 32-bit register which specify the operation of compare match timer counter (CM[n]CNT[m])"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "STR0,Count Start 0 These bits specify start/halt of compare match timer counter (CM[n]STR[m])" "0: CM[n]STR[m] halts,1: CM[n]STR[m] starts counting"
group.long 0x210++0x03
line.long 0x00 "CM2CSR2,CM[n]CSR[m](n=1-3)(m=1-4) is a 32-bit register that indicates the occurrence of compare match enable interrupt and set the counter input clock"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
bitfld.long 0x00 15. "CMF,Compare Match Flag This flag indicates whether values of the compare match timer counter (CM[n]CNT[m]) and compare match timer constant register (CM[n]COR[m]) have matched or not" "0: CM[n]CNT[m] and CM[n]COR[m] values have not,1: CM[n]CNT[m] and CM[n]COR[m] values have matched"
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bitfld.long 0x00 14. "OVF,Overflow Flag This flag indicates whether the compare match timer counter (CM[n]CNT[m]) has overflowed or not" "0: CM[n]CNT[m] has not overflowed [Clearing,1: CM[n]CNT[m] has overflowed"
rbitfld.long 0x00 13. "WRFLG,Write State Flag Write access to CM[n]CNT[m] is prohibited while this this bit is 1" "0,1"
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rbitfld.long 0x00 10.--12. "Reserved_10,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 9. "CMS,Compare Match Timer Counter Size This bit and CM[n]CSRH[m].CMSH specify whether the compare match timer counter (CM[n]CNTH[m][15:0] and CM[n]CNT[m][31:0]) is used as a 16-bit counter a 32-bit counter or a 48-bit counter" "0: Operates as a 32-bit counter,1: Operates as a 16-bit counter"
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bitfld.long 0x00 8. "CMM,Compare Match Mode Specify counter operation mode" "0: One-shot operation,1: Free-running operation"
rbitfld.long 0x00 6.--7. "Reserved_6,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 4.--5. "CMR_1_0,Compare Match Request These bits enable or disable internal interrupt request in a compare match" "0: Disables internal interrupt request,1: Setting prohibited,2: Enables an internal interrupt request,3: Setting prohibited"
bitfld.long 0x00 3. "DBGIVD,Debug Mode Operation Select Sets the counter operation in debugging mode" "0: Stops the counter operation in debugging mode,1: Continues the counter operation even in"
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bitfld.long 0x00 0.--2. "CKS_2_0,Clock Select These bits and CM[n]CSRH[m].CKSH specify the input clock to CM[n]CNT[m]" "?,?,?,?,4: RCLK/8,5: RCLK/32,6: RCLK/128,7: RCLK/1"
group.long 0x214++0x03
line.long 0x00 "CM2CNT2,CM[n]CNT[m](n=1-3)(m=0-7) is a 32-bit register which is used as an up-counter of each channel"
hexmask.long 0x00 0.--31. 1. "CMCNT_31_0,Compare match timer counter bit31 to 0 Note: For access to this register refer to section 155.2.3.5 Register Access"
group.long 0x218++0x03
line.long 0x00 "CM2COR2,CM[n]COR[m] is a 32-bit register which specify the compare match period of CM[n]CNT[m] for each channel"
hexmask.long 0x00 0.--31. 1. "CMCOR_31_0,Compare match timer constant register bit31 to 0 Note: For access to this register refer to section 155.2.3.5 Register Access"
group.long 0x220++0x03
line.long 0x00 "CM2CSRH2,CM[n]CSRH[m] is a 32-bit register which specify the counter size and input clocks"
hexmask.long.tbyte 0x00 10.--31. 1. "Reserved_10,Reserved These bits are always read as 0"
bitfld.long 0x00 9. "CMSH,Compare Match Timer Counter Size This bit and CM[n]CSR[m].CMS specify whether the compare match timer counter (CM[n]CNTH[m][15:0] and CM[n]CNT[m][31:0]) is used as a 16-bit counter a 32-bit counter or a 48-bit counter" "0: Operates as a 32-bit counter,1: Operates as a 16-bit counter"
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hexmask.long.byte 0x00 1.--8. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CKSH,Clock Select This bit and CM[n]CSR[m].CKS [2:0] select the clock input to CM[n]CNT[m]" "0,1"
group.long 0x224++0x03
line.long 0x00 "CM2CNTH2,CM[n]CNTH[m](n=1-3)(m=0-4) is a 32-bit register which is used as an up-counter for channel0 to 4"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
hexmask.long.word 0x00 0.--15. 1. "CMCNTH_15_0,Compare match timer counter H bit15 to 0 Note: For access to this register refer to section 155.2.3.5 Register Access"
group.long 0x228++0x03
line.long 0x00 "CM2CORH2,CM[n]CORH[m] is a 32-bit register which specify the compare match period with CM[n]CNTH[m] for channel0 to 4"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
hexmask.long.word 0x00 0.--15. 1. "CMCORH_15_0,Compare match timer constant register H bit15 to 0 Note: For access to this register refer to section 155.2.3.5 Register Access"
group.long 0x300++0x03
line.long 0x00 "CM2STR3,CM[n]STR[m] (n=1-3)(m=1-4) is a 32-bit register which specify the operation of compare match timer counter (CM[n]CNT[m])"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "STR0,Count Start 0 These bits specify start/halt of compare match timer counter (CM[n]STR[m])" "0: CM[n]STR[m] halts,1: CM[n]STR[m] starts counting"
group.long 0x310++0x03
line.long 0x00 "CM2CSR3,CM[n]CSR[m](n=1-3)(m=1-4) is a 32-bit register that indicates the occurrence of compare match enable interrupt and set the counter input clock"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
bitfld.long 0x00 15. "CMF,Compare Match Flag This flag indicates whether values of the compare match timer counter (CM[n]CNT[m]) and compare match timer constant register (CM[n]COR[m]) have matched or not" "0: CM[n]CNT[m] and CM[n]COR[m] values have not,1: CM[n]CNT[m] and CM[n]COR[m] values have matched"
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bitfld.long 0x00 14. "OVF,Overflow Flag This flag indicates whether the compare match timer counter (CM[n]CNT[m]) has overflowed or not" "0: CM[n]CNT[m] has not overflowed [Clearing,1: CM[n]CNT[m] has overflowed"
rbitfld.long 0x00 13. "WRFLG,Write State Flag Write access to CM[n]CNT[m] is prohibited while this this bit is 1" "0,1"
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rbitfld.long 0x00 10.--12. "Reserved_10,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 9. "CMS,Compare Match Timer Counter Size This bit and CM[n]CSRH[m].CMSH specify whether the compare match timer counter (CM[n]CNTH[m][15:0] and CM[n]CNT[m][31:0]) is used as a 16-bit counter a 32-bit counter or a 48-bit counter" "0: Operates as a 32-bit counter,1: Operates as a 16-bit counter"
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bitfld.long 0x00 8. "CMM,Compare Match Mode Specify counter operation mode" "0: One-shot operation,1: Free-running operation"
rbitfld.long 0x00 6.--7. "Reserved_6,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 4.--5. "CMR_1_0,Compare Match Request These bits enable or disable internal interrupt request in a compare match" "0: Disables internal interrupt request,1: Setting prohibited,2: Enables an internal interrupt request,3: Setting prohibited"
bitfld.long 0x00 3. "DBGIVD,Debug Mode Operation Select Sets the counter operation in debugging mode" "0: Stops the counter operation in debugging mode,1: Continues the counter operation even in"
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bitfld.long 0x00 0.--2. "CKS_2_0,Clock Select These bits and CM[n]CSRH[m].CKSH specify the input clock to CM[n]CNT[m]" "?,?,?,?,4: RCLK/8,5: RCLK/32,6: RCLK/128,7: RCLK/1"
group.long 0x314++0x03
line.long 0x00 "CM2CNT3,CM[n]CNT[m](n=1-3)(m=0-7) is a 32-bit register which is used as an up-counter of each channel"
hexmask.long 0x00 0.--31. 1. "CMCNT_31_0,Compare match timer counter bit31 to 0 Note: For access to this register refer to section 155.2.3.5 Register Access"
group.long 0x318++0x03
line.long 0x00 "CM2COR3,CM[n]COR[m] is a 32-bit register which specify the compare match period of CM[n]CNT[m] for each channel"
hexmask.long 0x00 0.--31. 1. "CMCOR_31_0,Compare match timer constant register bit31 to 0 Note: For access to this register refer to section 155.2.3.5 Register Access"
group.long 0x320++0x03
line.long 0x00 "CM2CSRH3,CM[n]CSRH[m] is a 32-bit register which specify the counter size and input clocks"
hexmask.long.tbyte 0x00 10.--31. 1. "Reserved_10,Reserved These bits are always read as 0"
bitfld.long 0x00 9. "CMSH,Compare Match Timer Counter Size This bit and CM[n]CSR[m].CMS specify whether the compare match timer counter (CM[n]CNTH[m][15:0] and CM[n]CNT[m][31:0]) is used as a 16-bit counter a 32-bit counter or a 48-bit counter" "0: Operates as a 32-bit counter,1: Operates as a 16-bit counter"
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hexmask.long.byte 0x00 1.--8. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CKSH,Clock Select This bit and CM[n]CSR[m].CKS [2:0] select the clock input to CM[n]CNT[m]" "0,1"
group.long 0x324++0x03
line.long 0x00 "CM2CNTH3,CM[n]CNTH[m](n=1-3)(m=0-4) is a 32-bit register which is used as an up-counter for channel0 to 4"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
hexmask.long.word 0x00 0.--15. 1. "CMCNTH_15_0,Compare match timer counter H bit15 to 0 Note: For access to this register refer to section 155.2.3.5 Register Access"
group.long 0x328++0x03
line.long 0x00 "CM2CORH3,CM[n]CORH[m] is a 32-bit register which specify the compare match period with CM[n]CNTH[m] for channel0 to 4"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
hexmask.long.word 0x00 0.--15. 1. "CMCORH_15_0,Compare match timer constant register H bit15 to 0 Note: For access to this register refer to section 155.2.3.5 Register Access"
group.long 0x330++0x03
line.long 0x00 "CM2CNT3BK0,CM[n]CNT[m]BK0 is a 32-bit register which stores a copy of the CM[n]CNT[m] value immediately after the counter in channel 0 stops in RCLK-synchronous channel 0 counter start/stop mode"
hexmask.long 0x00 0.--31. 1. "CMCNT3BK0_31_0,Compare match timer counter 3 backup 0 bit31 to 0"
group.long 0x334++0x03
line.long 0x00 "CM2CNT3BK1,CM[n]CNT[m]BK1 is a 32-bit register which stores a copy of the CM[n]CNT[m] value immediately after the counter in channel 0 starts in RCLK-synchronous channel 0 counter start/stop mode"
hexmask.long 0x00 0.--31. 1. "CMCNT3BK1_31_0,Compare match timer counter 3 backup 1 bit31 to 0"
group.long 0x340++0x03
line.long 0x00 "CM2CSRM3,CM[n]CSRM[m] is a 32-bit register which resets to compare match timer match counter and sets the counter start/halt"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
rbitfld.long 0x00 15. "WRFLG,Write state flag" "0: CPEX?,1: RCLK"
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hexmask.long.word 0x00 2.--14. 1. "Reserved_2,Reserved These bits are always read as 0"
bitfld.long 0x00 1. "CMPCLR,Counter Clear [When writing]" "0: No operation,1: Clears counter When CMPCLR and"
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bitfld.long 0x00 0. "CMPSTART,Count Start This bit specifies start/halt of the compare match timer match counter (CM[n]CNTM[m]) of each channel" "0: CM[n]CNTM[m] Halts,1: CM[n]CNTM[m] Starts counting"
group.long 0x344++0x03
line.long 0x00 "CM2CNTM3,CM[n]CNTM[m] is a 32-bit register which is used as an up-counter"
hexmask.long 0x00 0.--31. 1. "CMCNTM_31_0,Compare match timer match counter bit31 to 0"
group.long 0x400++0x03
line.long 0x00 "CM2STR4,CM[n]STR[m] (n=1-3)(m=1-4) is a 32-bit register which specify the operation of compare match timer counter (CM[n]CNT[m])"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "STR0,Count Start 0 These bits specify start/halt of compare match timer counter (CM[n]STR[m])" "0: CM[n]STR[m] halts,1: CM[n]STR[m] starts counting"
group.long 0x410++0x03
line.long 0x00 "CM2CSR4,CM[n]CSR[m](n=1-3)(m=1-4) is a 32-bit register that indicates the occurrence of compare match enable interrupt and set the counter input clock"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
bitfld.long 0x00 15. "CMF,Compare Match Flag This flag indicates whether values of the compare match timer counter (CM[n]CNT[m]) and compare match timer constant register (CM[n]COR[m]) have matched or not" "0: CM[n]CNT[m] and CM[n]COR[m] values have not,1: CM[n]CNT[m] and CM[n]COR[m] values have matched"
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bitfld.long 0x00 14. "OVF,Overflow Flag This flag indicates whether the compare match timer counter (CM[n]CNT[m]) has overflowed or not" "0: CM[n]CNT[m] has not overflowed [Clearing,1: CM[n]CNT[m] has overflowed"
rbitfld.long 0x00 13. "WRFLG,Write State Flag Write access to CM[n]CNT[m] is prohibited while this this bit is 1" "0,1"
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rbitfld.long 0x00 10.--12. "Reserved_10,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 9. "CMS,Compare Match Timer Counter Size This bit and CM[n]CSRH[m].CMSH specify whether the compare match timer counter (CM[n]CNTH[m][15:0] and CM[n]CNT[m][31:0]) is used as a 16-bit counter a 32-bit counter or a 48-bit counter" "0: Operates as a 32-bit counter,1: Operates as a 16-bit counter"
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bitfld.long 0x00 8. "CMM,Compare Match Mode Specify counter operation mode" "0: One-shot operation,1: Free-running operation"
rbitfld.long 0x00 6.--7. "Reserved_6,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 4.--5. "CMR_1_0,Compare Match Request These bits enable or disable internal interrupt request in a compare match" "0: Disables internal interrupt request,1: Setting prohibited,2: Enables an internal interrupt request,3: Setting prohibited"
bitfld.long 0x00 3. "DBGIVD,Debug Mode Operation Select Sets the counter operation in debugging mode" "0: Stops the counter operation in debugging mode,1: Continues the counter operation even in"
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bitfld.long 0x00 0.--2. "CKS_2_0,Clock Select These bits and CM[n]CSRH[m].CKSH specify the input clock to CM[n]CNT[m]" "?,?,?,?,4: RCLK/8,5: RCLK/32,6: RCLK/128,7: RCLK/1"
group.long 0x414++0x03
line.long 0x00 "CM2CNT4,CM[n]CNT[m](n=1-3)(m=0-7) is a 32-bit register which is used as an up-counter of each channel"
hexmask.long 0x00 0.--31. 1. "CMCNT_31_0,Compare match timer counter bit31 to 0 Note: For access to this register refer to section 155.2.3.5 Register Access"
group.long 0x418++0x03
line.long 0x00 "CM2COR4,CM[n]COR[m] is a 32-bit register which specify the compare match period of CM[n]CNT[m] for each channel"
hexmask.long 0x00 0.--31. 1. "CMCOR_31_0,Compare match timer constant register bit31 to 0 Note: For access to this register refer to section 155.2.3.5 Register Access"
group.long 0x420++0x03
line.long 0x00 "CM2CSRH4,CM[n]CSRH[m] is a 32-bit register which specify the counter size and input clocks"
hexmask.long.tbyte 0x00 10.--31. 1. "Reserved_10,Reserved These bits are always read as 0"
bitfld.long 0x00 9. "CMSH,Compare Match Timer Counter Size This bit and CM[n]CSR[m].CMS specify whether the compare match timer counter (CM[n]CNTH[m][15:0] and CM[n]CNT[m][31:0]) is used as a 16-bit counter a 32-bit counter or a 48-bit counter" "0: Operates as a 32-bit counter,1: Operates as a 16-bit counter"
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hexmask.long.byte 0x00 1.--8. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CKSH,Clock Select This bit and CM[n]CSR[m].CKS [2:0] select the clock input to CM[n]CNT[m]" "0,1"
group.long 0x424++0x03
line.long 0x00 "CM2CNTH4,CM[n]CNTH[m](n=1-3)(m=0-4) is a 32-bit register which is used as an up-counter for channel0 to 4"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
hexmask.long.word 0x00 0.--15. 1. "CMCNTH_15_0,Compare match timer counter H bit15 to 0 Note: For access to this register refer to section 155.2.3.5 Register Access"
group.long 0x428++0x03
line.long 0x00 "CM2CORH4,CM[n]CORH[m] is a 32-bit register which specify the compare match period with CM[n]CNTH[m] for channel0 to 4"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
hexmask.long.word 0x00 0.--15. 1. "CMCORH_15_0,Compare match timer constant register H bit15 to 0 Note: For access to this register refer to section 155.2.3.5 Register Access"
group.long 0x500++0x03
line.long 0x00 "CM2STR5,CM[n]STR[m] (n=1-3)(m=5-7) is a 32-bit register which specify the operation of compare match timer counter (CM[n]CNT[m])"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "STR0,Count Start 0 These bits specify start/halt of compare match timer counter (CM[n]STR[m])" "0: CM[n]STR[m] halts,1: CM[n]STR[m] starts counting"
group.long 0x510++0x03
line.long 0x00 "CM2CSR5,CM[n]CSR[m](n=1-3)(m=5-7) is a 32-bit register that indicates the occurrence of compare match enable interrupt and set the counter input clock"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
bitfld.long 0x00 15. "CMF,Compare Match Flag This flag indicates whether values of the compare match timer counter (CM[n]CNT[m]) and compare match timer constant register (CM[n]COR[m]) have matched or not" "0: CM[n]CNT[m] and CM[n]COR[m] values have not,1: CM[n]CNT[m] and CM[n]COR[m] values have matched"
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bitfld.long 0x00 14. "OVF,Overflow Flag This flag indicates whether the compare match timer counter (CM[n]CNT[m]) has overflowed or not" "0: CM[n]CNT[m] has not overflowed [Clearing,1: CM[n]CNT[m] has overflowed"
rbitfld.long 0x00 13. "WRFLG,Write State Flag Write access to CM[n]CNT[m] is prohibited while this this bit is 1" "0,1"
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rbitfld.long 0x00 10.--12. "Reserved_10,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 9. "CMS,Compare Match Timer Counter Size Selects whether the compare match timer counter (CM[n]CNT[m]) is used as a 16-bit counter or a 32-bit counter" "0: Operates as a 32-bit counter,1: Operates as a 16-bit counter"
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bitfld.long 0x00 8. "CMM,Compare Match Mode Specify counter operation mode" "0: One-shot operation,1: Free-running operation"
rbitfld.long 0x00 6.--7. "Reserved_6,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 4.--5. "CMR_1_0,Compare Match Request These bits enable or disable internal interrupt request in a compare match" "0: Disables internal interrupt request,1: Setting prohibited,2: Enables an internal interrupt request,3: Setting prohibited"
bitfld.long 0x00 3. "DBGIVD,Debug Mode Operation Select Sets the counter operation in debugging mode" "0: Stops the counter operation in debugging mode,1: Continues the counter operation even in"
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bitfld.long 0x00 0.--2. "CKS_2_0,Clock Select These bits select the clock input to CM[n]CNT[m]" "0: Setting prohibited,1: Setting prohibited,2: Setting prohibited,3: Setting prohibited,4: RCLK/8,5: RCLK/32,6: RCLK/128,7: RCLK/1"
group.long 0x514++0x03
line.long 0x00 "CM2CNT5,CM[n]CNT[m](n=1-3)(m=0-7) is a 32-bit register which is used as an up-counter of each channel"
hexmask.long 0x00 0.--31. 1. "CMCNT_31_0,Compare match timer counter bit31 to 0 Note: For access to this register refer to section 155.2.3.5 Register Access"
group.long 0x518++0x03
line.long 0x00 "CM2COR5,CM[n]COR[m] is a 32-bit register which specify the compare match period of CM[n]CNT[m] for each channel"
hexmask.long 0x00 0.--31. 1. "CMCOR_31_0,Compare match timer constant register bit31 to 0 Note: For access to this register refer to section 155.2.3.5 Register Access"
group.long 0x600++0x03
line.long 0x00 "CM2STR6,CM[n]STR[m] (n=1-3)(m=5-7) is a 32-bit register which specify the operation of compare match timer counter (CM[n]CNT[m])"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "STR0,Count Start 0 These bits specify start/halt of compare match timer counter (CM[n]STR[m])" "0: CM[n]STR[m] halts,1: CM[n]STR[m] starts counting"
group.long 0x610++0x03
line.long 0x00 "CM2CSR6,CM[n]CSR[m](n=1-3)(m=5-7) is a 32-bit register that indicates the occurrence of compare match enable interrupt and set the counter input clock"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
bitfld.long 0x00 15. "CMF,Compare Match Flag This flag indicates whether values of the compare match timer counter (CM[n]CNT[m]) and compare match timer constant register (CM[n]COR[m]) have matched or not" "0: CM[n]CNT[m] and CM[n]COR[m] values have not,1: CM[n]CNT[m] and CM[n]COR[m] values have matched"
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bitfld.long 0x00 14. "OVF,Overflow Flag This flag indicates whether the compare match timer counter (CM[n]CNT[m]) has overflowed or not" "0: CM[n]CNT[m] has not overflowed [Clearing,1: CM[n]CNT[m] has overflowed"
rbitfld.long 0x00 13. "WRFLG,Write State Flag Write access to CM[n]CNT[m] is prohibited while this this bit is 1" "0,1"
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rbitfld.long 0x00 10.--12. "Reserved_10,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 9. "CMS,Compare Match Timer Counter Size Selects whether the compare match timer counter (CM[n]CNT[m]) is used as a 16-bit counter or a 32-bit counter" "0: Operates as a 32-bit counter,1: Operates as a 16-bit counter"
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bitfld.long 0x00 8. "CMM,Compare Match Mode Specify counter operation mode" "0: One-shot operation,1: Free-running operation"
rbitfld.long 0x00 6.--7. "Reserved_6,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 4.--5. "CMR_1_0,Compare Match Request These bits enable or disable internal interrupt request in a compare match" "0: Disables internal interrupt request,1: Setting prohibited,2: Enables an internal interrupt request,3: Setting prohibited"
bitfld.long 0x00 3. "DBGIVD,Debug Mode Operation Select Sets the counter operation in debugging mode" "0: Stops the counter operation in debugging mode,1: Continues the counter operation even in"
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bitfld.long 0x00 0.--2. "CKS_2_0,Clock Select These bits select the clock input to CM[n]CNT[m]" "0: Setting prohibited,1: Setting prohibited,2: Setting prohibited,3: Setting prohibited,4: RCLK/8,5: RCLK/32,6: RCLK/128,7: RCLK/1"
group.long 0x614++0x03
line.long 0x00 "CM2CNT6,CM[n]CNT[m](n=1-3)(m=0-7) is a 32-bit register which is used as an up-counter of each channel"
hexmask.long 0x00 0.--31. 1. "CMCNT_31_0,Compare match timer counter bit31 to 0 Note: For access to this register refer to section 155.2.3.5 Register Access"
group.long 0x618++0x03
line.long 0x00 "CM2COR6,CM[n]COR[m] is a 32-bit register which specify the compare match period of CM[n]CNT[m] for each channel"
hexmask.long 0x00 0.--31. 1. "CMCOR_31_0,Compare match timer constant register bit31 to 0 Note: For access to this register refer to section 155.2.3.5 Register Access"
group.long 0x700++0x03
line.long 0x00 "CM2STR7,CM[n]STR[m] (n=1-3)(m=5-7) is a 32-bit register which specify the operation of compare match timer counter (CM[n]CNT[m])"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "STR0,Count Start 0 These bits specify start/halt of compare match timer counter (CM[n]STR[m])" "0: CM[n]STR[m] halts,1: CM[n]STR[m] starts counting"
group.long 0x710++0x03
line.long 0x00 "CM2CSR7,CM[n]CSR[m](n=1-3)(m=5-7) is a 32-bit register that indicates the occurrence of compare match enable interrupt and set the counter input clock"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
bitfld.long 0x00 15. "CMF,Compare Match Flag This flag indicates whether values of the compare match timer counter (CM[n]CNT[m]) and compare match timer constant register (CM[n]COR[m]) have matched or not" "0: CM[n]CNT[m] and CM[n]COR[m] values have not,1: CM[n]CNT[m] and CM[n]COR[m] values have matched"
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bitfld.long 0x00 14. "OVF,Overflow Flag This flag indicates whether the compare match timer counter (CM[n]CNT[m]) has overflowed or not" "0: CM[n]CNT[m] has not overflowed [Clearing,1: CM[n]CNT[m] has overflowed"
rbitfld.long 0x00 13. "WRFLG,Write State Flag Write access to CM[n]CNT[m] is prohibited while this this bit is 1" "0,1"
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rbitfld.long 0x00 10.--12. "Reserved_10,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 9. "CMS,Compare Match Timer Counter Size Selects whether the compare match timer counter (CM[n]CNT[m]) is used as a 16-bit counter or a 32-bit counter" "0: Operates as a 32-bit counter,1: Operates as a 16-bit counter"
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bitfld.long 0x00 8. "CMM,Compare Match Mode Specify counter operation mode" "0: One-shot operation,1: Free-running operation"
rbitfld.long 0x00 6.--7. "Reserved_6,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 4.--5. "CMR_1_0,Compare Match Request These bits enable or disable internal interrupt request in a compare match" "0: Disables internal interrupt request,1: Setting prohibited,2: Enables an internal interrupt request,3: Setting prohibited"
bitfld.long 0x00 3. "DBGIVD,Debug Mode Operation Select Sets the counter operation in debugging mode" "0: Stops the counter operation in debugging mode,1: Continues the counter operation even in"
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bitfld.long 0x00 0.--2. "CKS_2_0,Clock Select These bits select the clock input to CM[n]CNT[m]" "0: Setting prohibited,1: Setting prohibited,2: Setting prohibited,3: Setting prohibited,4: RCLK/8,5: RCLK/32,6: RCLK/128,7: RCLK/1"
group.long 0x714++0x03
line.long 0x00 "CM2CNT7,CM[n]CNT[m](n=1-3)(m=0-7) is a 32-bit register which is used as an up-counter of each channel"
hexmask.long 0x00 0.--31. 1. "CMCNT_31_0,Compare match timer counter bit31 to 0 Note: For access to this register refer to section 155.2.3.5 Register Access"
group.long 0x718++0x03
line.long 0x00 "CM2COR7,CM[n]COR[m] is a 32-bit register which specify the compare match period of CM[n]CNT[m] for each channel"
hexmask.long 0x00 0.--31. 1. "CMCOR_31_0,Compare match timer constant register bit31 to 0 Note: For access to this register refer to section 155.2.3.5 Register Access"
group.long 0x1000++0x03
line.long 0x00 "CM2CLKE,CM[n]CLKE is a 32bits register which specify clock supply to each channel"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 1"
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bitfld.long 0x00 7. "Ch7clke," "0,1"
bitfld.long 0x00 6. "Ch6clke," "0,1"
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bitfld.long 0x00 5. "Ch5clke," "0,1"
bitfld.long 0x00 4. "Ch4clke," "0,1"
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bitfld.long 0x00 3. "Ch3clke," "0,1"
bitfld.long 0x00 2. "Ch2clke," "0,1"
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bitfld.long 0x00 1. "Ch1clke," "0,1"
bitfld.long 0x00 0. "Ch0clke," "0,1"
tree.end
tree "CMT1_INST_2"
base ad:0xE6148000
group.long 0x00++0x03
line.long 0x00 "CM3STR0,CM[n]STR[m] (n=1-3)(m=0) is a 32-bit register which specify the operation of compare match timer counter (CM[n]CNT[m])"
hexmask.long.tbyte 0x00 9.--31. 1. "Reserved_9,Reserved These bits are always read as 0"
bitfld.long 0x00 8. "STR0RS,RCLK-Synchronous Counter Start/Stop Mode Select" "0: Normal operation Channel 0 starts or stops,1: RCLK-synchronous counter start/stop mode.."
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hexmask.long.byte 0x00 1.--7. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "STR0,Count Start 0 These bits specify start/halt of compare match timer counter 0 (CM[n]CNT0)" "0: CM[n]CNT0 halts,1: CM[n]CNT0 start counting"
group.long 0x10++0x03
line.long 0x00 "CM3CSR0,CM[n]CSR[m](n=1-3)(m=0) is a 32-bit register that indicates the occurrence of compare match enable interrupt and set the counter input clock"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
bitfld.long 0x00 15. "CMF,Compare Match Flag This flag indicates whether values of the compare match timer counter (CM[n]CNT0) and compare match timer constant register (CM[n]COR0) have matched or not" "0: CM[n]CNT0 and CM[n]COR0 values have not matched,1: CM[n]CNT0 and CM[n]COR0 values have matched"
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bitfld.long 0x00 14. "OVF,Overflow Flag This flag indicates whether the compare match timer counter (CM[n]CNT0) has overflowed or not" "0: CM[n]CNT0 has not overflowed [Clearing,1: CM[n]CNT0 has overflowed"
rbitfld.long 0x00 13. "WRFLG,Write State Flag Write access to CM[n]CNT0 is prohibited while this bit is 1" "0,1"
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bitfld.long 0x00 12. "CH0STTF,Channel 0 Start Flag When RCLK-synchronous channel 0 counter start/stop mode is selected this flag indicates whether the counter in channel 0 started on detecting an RCLK rising edge after 1 was written to the STR0 bit in CM[n]STR0" "0: Channel 0 counter has not started,1: Channel 0 counter has started"
bitfld.long 0x00 11. "CH0STPF,Channel 0 Stop Flag When RCLK-synchronous channel 0 counter start/stop mode is selected this flag indicates whether the counter in channel 0 stopped on detecting an RCLK rising edge after 1 was written to the STR0 bit in CM[n]STR0" "0: Channel 0 counter has not stopped,1: Channel 0 counter has stopped"
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bitfld.long 0x00 10. "CH0SSIE,Channel 0 Start/Stop Interrupt Enable When RCLK-synchronous channel 0 counter start/stop mode is selected this bit enables or disables an interrupt due to the start or stop of the counter in channel 0" "0: Disables an interrupt due to start or stop of,1: Enables an interrupt due to start or stop of"
bitfld.long 0x00 9. "CMS,Compare Match Timer Counter Size This bit and CM[n]CSRH0.CMSH select whether the compare match timer counter 0 (CM[n]CNTH0 [15:0] and CM[n]CNT0 [31:0]) is used as a 16-bit counter a 32-bit counter or a 48-bit counter" "0: Operates as a 32-bit counter,1: Operates as a 16-bit counter"
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bitfld.long 0x00 8. "CMM,Compare Match Mode Specify operation mode of the counter" "0: One-shot operation,1: Free-running operation"
rbitfld.long 0x00 7. "Reserved_7,Reserved This bit is always read as 0" "0,1"
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rbitfld.long 0x00 6. "Reserved_6,Reserved This bit is always read as 0" "0,1"
bitfld.long 0x00 4.--5. "CMR_1_0,Compare Match Request These bits enable or disable internal interrupt request in a compare match" "0: Disables internal interrupt request,1: Setting prohibited,2: Enables an internal interrupt request,3: Setting prohibited"
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bitfld.long 0x00 3. "DBGIVD,Debug Mode Operation Select Sets the counter operation in debugging mode" "0: Stops the counter operation in debugging mode,1: Continues the counter operation even in"
bitfld.long 0x00 0.--2. "CKS_2_0,Clock Select These bits and CM[n]CSRH0.CKSH select the clock input to CM[n]CNT0" "?,?,?,?,4: RCLK/8,5: RCLK/32,6: RCLK/128,7: RCLK/1"
group.long 0x14++0x03
line.long 0x00 "CM3CNT0,CM[n]CNT[m](n=1-3)(m=0-7) is a 32-bit register which is used as an up-counter of each channel"
hexmask.long 0x00 0.--31. 1. "CMCNT_31_0,Compare match timer counter bit31 to 0 Note: For access to this register refer to section 155.2.3.5 Register Access"
group.long 0x18++0x03
line.long 0x00 "CM3COR0,CM[n]COR[m] is a 32-bit register which specify the compare match period of CM[n]CNT[m] for each channel"
hexmask.long 0x00 0.--31. 1. "CMCOR_31_0,Compare match timer constant register bit31 to 0 Note: For access to this register refer to section 155.2.3.5 Register Access"
group.long 0x20++0x03
line.long 0x00 "CM3CSRH0,CM[n]CSRH[m] is a 32-bit register which specify the counter size and input clocks"
hexmask.long.tbyte 0x00 10.--31. 1. "Reserved_10,Reserved These bits are always read as 0"
bitfld.long 0x00 9. "CMSH,Compare Match Timer Counter Size This bit and CM[n]CSR[m].CMS specify whether the compare match timer counter (CM[n]CNTH[m][15:0] and CM[n]CNT[m][31:0]) is used as a 16-bit counter a 32-bit counter or a 48-bit counter" "0: Operates as a 32-bit counter,1: Operates as a 16-bit counter"
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hexmask.long.byte 0x00 1.--8. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CKSH,Clock Select This bit and CM[n]CSR[m].CKS [2:0] select the clock input to CM[n]CNT[m]" "0,1"
group.long 0x24++0x03
line.long 0x00 "CM3CNTH0,CM[n]CNTH[m](n=1-3)(m=0-4) is a 32-bit register which is used as an up-counter for channel0 to 4"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
hexmask.long.word 0x00 0.--15. 1. "CMCNTH_15_0,Compare match timer counter H bit15 to 0 Note: For access to this register refer to section 155.2.3.5 Register Access"
group.long 0x28++0x03
line.long 0x00 "CM3CORH0,CM[n]CORH[m] is a 32-bit register which specify the compare match period with CM[n]CNTH[m] for channel0 to 4"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
hexmask.long.word 0x00 0.--15. 1. "CMCORH_15_0,Compare match timer constant register H bit15 to 0 Note: For access to this register refer to section 155.2.3.5 Register Access"
group.long 0x40++0x03
line.long 0x00 "CM3CSRM0,CM[n]CSRM[m] is a 32-bit register which resets to compare match timer match counter and sets the counter start/halt"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
rbitfld.long 0x00 15. "WRFLG,Write state flag" "0: CPEX?,1: RCLK"
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hexmask.long.word 0x00 2.--14. 1. "Reserved_2,Reserved These bits are always read as 0"
bitfld.long 0x00 1. "CMPCLR,Counter Clear [When writing]" "0: No operation,1: Clears counter When CMPCLR and"
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bitfld.long 0x00 0. "CMPSTART,Count Start This bit specifies start/halt of the compare match timer match counter (CM[n]CNTM[m]) of each channel" "0: CM[n]CNTM[m] Halts,1: CM[n]CNTM[m] Starts counting"
group.long 0x44++0x03
line.long 0x00 "CM3CNTM0,CM[n]CNTM[m] is a 32-bit register which is used as an up-counter"
hexmask.long 0x00 0.--31. 1. "CMCNTM_31_0,Compare match timer match counter bit31 to 0"
group.long 0x100++0x03
line.long 0x00 "CM3STR1,CM[n]STR[m] (n=1-3)(m=1-4) is a 32-bit register which specify the operation of compare match timer counter (CM[n]CNT[m])"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "STR0,Count Start 0 These bits specify start/halt of compare match timer counter (CM[n]STR[m])" "0: CM[n]STR[m] halts,1: CM[n]STR[m] starts counting"
group.long 0x110++0x03
line.long 0x00 "CM3CSR1,CM[n]CSR[m](n=1-3)(m=1-4) is a 32-bit register that indicates the occurrence of compare match enable interrupt and set the counter input clock"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
bitfld.long 0x00 15. "CMF,Compare Match Flag This flag indicates whether values of the compare match timer counter (CM[n]CNT[m]) and compare match timer constant register (CM[n]COR[m]) have matched or not" "0: CM[n]CNT[m] and CM[n]COR[m] values have not,1: CM[n]CNT[m] and CM[n]COR[m] values have matched"
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bitfld.long 0x00 14. "OVF,Overflow Flag This flag indicates whether the compare match timer counter (CM[n]CNT[m]) has overflowed or not" "0: CM[n]CNT[m] has not overflowed [Clearing,1: CM[n]CNT[m] has overflowed"
rbitfld.long 0x00 13. "WRFLG,Write State Flag Write access to CM[n]CNT[m] is prohibited while this this bit is 1" "0,1"
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rbitfld.long 0x00 10.--12. "Reserved_10,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 9. "CMS,Compare Match Timer Counter Size This bit and CM[n]CSRH[m].CMSH specify whether the compare match timer counter (CM[n]CNTH[m][15:0] and CM[n]CNT[m][31:0]) is used as a 16-bit counter a 32-bit counter or a 48-bit counter" "0: Operates as a 32-bit counter,1: Operates as a 16-bit counter"
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bitfld.long 0x00 8. "CMM,Compare Match Mode Specify counter operation mode" "0: One-shot operation,1: Free-running operation"
rbitfld.long 0x00 6.--7. "Reserved_6,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 4.--5. "CMR_1_0,Compare Match Request These bits enable or disable internal interrupt request in a compare match" "0: Disables internal interrupt request,1: Setting prohibited,2: Enables an internal interrupt request,3: Setting prohibited"
bitfld.long 0x00 3. "DBGIVD,Debug Mode Operation Select Sets the counter operation in debugging mode" "0: Stops the counter operation in debugging mode,1: Continues the counter operation even in"
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bitfld.long 0x00 0.--2. "CKS_2_0,Clock Select These bits and CM[n]CSRH[m].CKSH specify the input clock to CM[n]CNT[m]" "?,?,?,?,4: RCLK/8,5: RCLK/32,6: RCLK/128,7: RCLK/1"
group.long 0x114++0x03
line.long 0x00 "CM3CNT1,CM[n]CNT[m](n=1-3)(m=0-7) is a 32-bit register which is used as an up-counter of each channel"
hexmask.long 0x00 0.--31. 1. "CMCNT_31_0,Compare match timer counter bit31 to 0 Note: For access to this register refer to section 155.2.3.5 Register Access"
group.long 0x118++0x03
line.long 0x00 "CM3COR1,CM[n]COR[m] is a 32-bit register which specify the compare match period of CM[n]CNT[m] for each channel"
hexmask.long 0x00 0.--31. 1. "CMCOR_31_0,Compare match timer constant register bit31 to 0 Note: For access to this register refer to section 155.2.3.5 Register Access"
group.long 0x120++0x03
line.long 0x00 "CM3CSRH1,CM[n]CSRH[m] is a 32-bit register which specify the counter size and input clocks"
hexmask.long.tbyte 0x00 10.--31. 1. "Reserved_10,Reserved These bits are always read as 0"
bitfld.long 0x00 9. "CMSH,Compare Match Timer Counter Size This bit and CM[n]CSR[m].CMS specify whether the compare match timer counter (CM[n]CNTH[m][15:0] and CM[n]CNT[m][31:0]) is used as a 16-bit counter a 32-bit counter or a 48-bit counter" "0: Operates as a 32-bit counter,1: Operates as a 16-bit counter"
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hexmask.long.byte 0x00 1.--8. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CKSH,Clock Select This bit and CM[n]CSR[m].CKS [2:0] select the clock input to CM[n]CNT[m]" "0,1"
group.long 0x124++0x03
line.long 0x00 "CM3CNTH1,CM[n]CNTH[m](n=1-3)(m=0-4) is a 32-bit register which is used as an up-counter for channel0 to 4"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
hexmask.long.word 0x00 0.--15. 1. "CMCNTH_15_0,Compare match timer counter H bit15 to 0 Note: For access to this register refer to section 155.2.3.5 Register Access"
group.long 0x128++0x03
line.long 0x00 "CM3CORH1,CM[n]CORH[m] is a 32-bit register which specify the compare match period with CM[n]CNTH[m] for channel0 to 4"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
hexmask.long.word 0x00 0.--15. 1. "CMCORH_15_0,Compare match timer constant register H bit15 to 0 Note: For access to this register refer to section 155.2.3.5 Register Access"
group.long 0x200++0x03
line.long 0x00 "CM3STR2,CM[n]STR[m] (n=1-3)(m=1-4) is a 32-bit register which specify the operation of compare match timer counter (CM[n]CNT[m])"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "STR0,Count Start 0 These bits specify start/halt of compare match timer counter (CM[n]STR[m])" "0: CM[n]STR[m] halts,1: CM[n]STR[m] starts counting"
group.long 0x210++0x03
line.long 0x00 "CM3CSR2,CM[n]CSR[m](n=1-3)(m=1-4) is a 32-bit register that indicates the occurrence of compare match enable interrupt and set the counter input clock"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
bitfld.long 0x00 15. "CMF,Compare Match Flag This flag indicates whether values of the compare match timer counter (CM[n]CNT[m]) and compare match timer constant register (CM[n]COR[m]) have matched or not" "0: CM[n]CNT[m] and CM[n]COR[m] values have not,1: CM[n]CNT[m] and CM[n]COR[m] values have matched"
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bitfld.long 0x00 14. "OVF,Overflow Flag This flag indicates whether the compare match timer counter (CM[n]CNT[m]) has overflowed or not" "0: CM[n]CNT[m] has not overflowed [Clearing,1: CM[n]CNT[m] has overflowed"
rbitfld.long 0x00 13. "WRFLG,Write State Flag Write access to CM[n]CNT[m] is prohibited while this this bit is 1" "0,1"
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rbitfld.long 0x00 10.--12. "Reserved_10,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 9. "CMS,Compare Match Timer Counter Size This bit and CM[n]CSRH[m].CMSH specify whether the compare match timer counter (CM[n]CNTH[m][15:0] and CM[n]CNT[m][31:0]) is used as a 16-bit counter a 32-bit counter or a 48-bit counter" "0: Operates as a 32-bit counter,1: Operates as a 16-bit counter"
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bitfld.long 0x00 8. "CMM,Compare Match Mode Specify counter operation mode" "0: One-shot operation,1: Free-running operation"
rbitfld.long 0x00 6.--7. "Reserved_6,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 4.--5. "CMR_1_0,Compare Match Request These bits enable or disable internal interrupt request in a compare match" "0: Disables internal interrupt request,1: Setting prohibited,2: Enables an internal interrupt request,3: Setting prohibited"
bitfld.long 0x00 3. "DBGIVD,Debug Mode Operation Select Sets the counter operation in debugging mode" "0: Stops the counter operation in debugging mode,1: Continues the counter operation even in"
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bitfld.long 0x00 0.--2. "CKS_2_0,Clock Select These bits and CM[n]CSRH[m].CKSH specify the input clock to CM[n]CNT[m]" "?,?,?,?,4: RCLK/8,5: RCLK/32,6: RCLK/128,7: RCLK/1"
group.long 0x214++0x03
line.long 0x00 "CM3CNT2,CM[n]CNT[m](n=1-3)(m=0-7) is a 32-bit register which is used as an up-counter of each channel"
hexmask.long 0x00 0.--31. 1. "CMCNT_31_0,Compare match timer counter bit31 to 0 Note: For access to this register refer to section 155.2.3.5 Register Access"
group.long 0x218++0x03
line.long 0x00 "CM3COR2,CM[n]COR[m] is a 32-bit register which specify the compare match period of CM[n]CNT[m] for each channel"
hexmask.long 0x00 0.--31. 1. "CMCOR_31_0,Compare match timer constant register bit31 to 0 Note: For access to this register refer to section 155.2.3.5 Register Access"
group.long 0x220++0x03
line.long 0x00 "CM3CSRH2,CM[n]CSRH[m] is a 32-bit register which specify the counter size and input clocks"
hexmask.long.tbyte 0x00 10.--31. 1. "Reserved_10,Reserved These bits are always read as 0"
bitfld.long 0x00 9. "CMSH,Compare Match Timer Counter Size This bit and CM[n]CSR[m].CMS specify whether the compare match timer counter (CM[n]CNTH[m][15:0] and CM[n]CNT[m][31:0]) is used as a 16-bit counter a 32-bit counter or a 48-bit counter" "0: Operates as a 32-bit counter,1: Operates as a 16-bit counter"
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hexmask.long.byte 0x00 1.--8. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CKSH,Clock Select This bit and CM[n]CSR[m].CKS [2:0] select the clock input to CM[n]CNT[m]" "0,1"
group.long 0x224++0x03
line.long 0x00 "CM3CNTH2,CM[n]CNTH[m](n=1-3)(m=0-4) is a 32-bit register which is used as an up-counter for channel0 to 4"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
hexmask.long.word 0x00 0.--15. 1. "CMCNTH_15_0,Compare match timer counter H bit15 to 0 Note: For access to this register refer to section 155.2.3.5 Register Access"
group.long 0x228++0x03
line.long 0x00 "CM3CORH2,CM[n]CORH[m] is a 32-bit register which specify the compare match period with CM[n]CNTH[m] for channel0 to 4"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
hexmask.long.word 0x00 0.--15. 1. "CMCORH_15_0,Compare match timer constant register H bit15 to 0 Note: For access to this register refer to section 155.2.3.5 Register Access"
group.long 0x300++0x03
line.long 0x00 "CM3STR3,CM[n]STR[m] (n=1-3)(m=1-4) is a 32-bit register which specify the operation of compare match timer counter (CM[n]CNT[m])"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "STR0,Count Start 0 These bits specify start/halt of compare match timer counter (CM[n]STR[m])" "0: CM[n]STR[m] halts,1: CM[n]STR[m] starts counting"
group.long 0x310++0x03
line.long 0x00 "CM3CSR3,CM[n]CSR[m](n=1-3)(m=1-4) is a 32-bit register that indicates the occurrence of compare match enable interrupt and set the counter input clock"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
bitfld.long 0x00 15. "CMF,Compare Match Flag This flag indicates whether values of the compare match timer counter (CM[n]CNT[m]) and compare match timer constant register (CM[n]COR[m]) have matched or not" "0: CM[n]CNT[m] and CM[n]COR[m] values have not,1: CM[n]CNT[m] and CM[n]COR[m] values have matched"
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bitfld.long 0x00 14. "OVF,Overflow Flag This flag indicates whether the compare match timer counter (CM[n]CNT[m]) has overflowed or not" "0: CM[n]CNT[m] has not overflowed [Clearing,1: CM[n]CNT[m] has overflowed"
rbitfld.long 0x00 13. "WRFLG,Write State Flag Write access to CM[n]CNT[m] is prohibited while this this bit is 1" "0,1"
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rbitfld.long 0x00 10.--12. "Reserved_10,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 9. "CMS,Compare Match Timer Counter Size This bit and CM[n]CSRH[m].CMSH specify whether the compare match timer counter (CM[n]CNTH[m][15:0] and CM[n]CNT[m][31:0]) is used as a 16-bit counter a 32-bit counter or a 48-bit counter" "0: Operates as a 32-bit counter,1: Operates as a 16-bit counter"
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bitfld.long 0x00 8. "CMM,Compare Match Mode Specify counter operation mode" "0: One-shot operation,1: Free-running operation"
rbitfld.long 0x00 6.--7. "Reserved_6,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 4.--5. "CMR_1_0,Compare Match Request These bits enable or disable internal interrupt request in a compare match" "0: Disables internal interrupt request,1: Setting prohibited,2: Enables an internal interrupt request,3: Setting prohibited"
bitfld.long 0x00 3. "DBGIVD,Debug Mode Operation Select Sets the counter operation in debugging mode" "0: Stops the counter operation in debugging mode,1: Continues the counter operation even in"
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bitfld.long 0x00 0.--2. "CKS_2_0,Clock Select These bits and CM[n]CSRH[m].CKSH specify the input clock to CM[n]CNT[m]" "?,?,?,?,4: RCLK/8,5: RCLK/32,6: RCLK/128,7: RCLK/1"
group.long 0x314++0x03
line.long 0x00 "CM3CNT3,CM[n]CNT[m](n=1-3)(m=0-7) is a 32-bit register which is used as an up-counter of each channel"
hexmask.long 0x00 0.--31. 1. "CMCNT_31_0,Compare match timer counter bit31 to 0 Note: For access to this register refer to section 155.2.3.5 Register Access"
group.long 0x318++0x03
line.long 0x00 "CM3COR3,CM[n]COR[m] is a 32-bit register which specify the compare match period of CM[n]CNT[m] for each channel"
hexmask.long 0x00 0.--31. 1. "CMCOR_31_0,Compare match timer constant register bit31 to 0 Note: For access to this register refer to section 155.2.3.5 Register Access"
group.long 0x320++0x03
line.long 0x00 "CM3CSRH3,CM[n]CSRH[m] is a 32-bit register which specify the counter size and input clocks"
hexmask.long.tbyte 0x00 10.--31. 1. "Reserved_10,Reserved These bits are always read as 0"
bitfld.long 0x00 9. "CMSH,Compare Match Timer Counter Size This bit and CM[n]CSR[m].CMS specify whether the compare match timer counter (CM[n]CNTH[m][15:0] and CM[n]CNT[m][31:0]) is used as a 16-bit counter a 32-bit counter or a 48-bit counter" "0: Operates as a 32-bit counter,1: Operates as a 16-bit counter"
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hexmask.long.byte 0x00 1.--8. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CKSH,Clock Select This bit and CM[n]CSR[m].CKS [2:0] select the clock input to CM[n]CNT[m]" "0,1"
group.long 0x324++0x03
line.long 0x00 "CM3CNTH3,CM[n]CNTH[m](n=1-3)(m=0-4) is a 32-bit register which is used as an up-counter for channel0 to 4"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
hexmask.long.word 0x00 0.--15. 1. "CMCNTH_15_0,Compare match timer counter H bit15 to 0 Note: For access to this register refer to section 155.2.3.5 Register Access"
group.long 0x328++0x03
line.long 0x00 "CM3CORH3,CM[n]CORH[m] is a 32-bit register which specify the compare match period with CM[n]CNTH[m] for channel0 to 4"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
hexmask.long.word 0x00 0.--15. 1. "CMCORH_15_0,Compare match timer constant register H bit15 to 0 Note: For access to this register refer to section 155.2.3.5 Register Access"
group.long 0x330++0x03
line.long 0x00 "CM3CNT3BK0,CM[n]CNT[m]BK0 is a 32-bit register which stores a copy of the CM[n]CNT[m] value immediately after the counter in channel 0 stops in RCLK-synchronous channel 0 counter start/stop mode"
hexmask.long 0x00 0.--31. 1. "CMCNT3BK0_31_0,Compare match timer counter 3 backup 0 bit31 to 0"
group.long 0x334++0x03
line.long 0x00 "CM3CNT3BK1,CM[n]CNT[m]BK1 is a 32-bit register which stores a copy of the CM[n]CNT[m] value immediately after the counter in channel 0 starts in RCLK-synchronous channel 0 counter start/stop mode"
hexmask.long 0x00 0.--31. 1. "CMCNT3BK1_31_0,Compare match timer counter 3 backup 1 bit31 to 0"
group.long 0x340++0x03
line.long 0x00 "CM3CSRM3,CM[n]CSRM[m] is a 32-bit register which resets to compare match timer match counter and sets the counter start/halt"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
rbitfld.long 0x00 15. "WRFLG,Write state flag" "0: CPEX?,1: RCLK"
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hexmask.long.word 0x00 2.--14. 1. "Reserved_2,Reserved These bits are always read as 0"
bitfld.long 0x00 1. "CMPCLR,Counter Clear [When writing]" "0: No operation,1: Clears counter When CMPCLR and"
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bitfld.long 0x00 0. "CMPSTART,Count Start This bit specifies start/halt of the compare match timer match counter (CM[n]CNTM[m]) of each channel" "0: CM[n]CNTM[m] Halts,1: CM[n]CNTM[m] Starts counting"
group.long 0x344++0x03
line.long 0x00 "CM3CNTM3,CM[n]CNTM[m] is a 32-bit register which is used as an up-counter"
hexmask.long 0x00 0.--31. 1. "CMCNTM_31_0,Compare match timer match counter bit31 to 0"
group.long 0x400++0x03
line.long 0x00 "CM3STR4,CM[n]STR[m] (n=1-3)(m=1-4) is a 32-bit register which specify the operation of compare match timer counter (CM[n]CNT[m])"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "STR0,Count Start 0 These bits specify start/halt of compare match timer counter (CM[n]STR[m])" "0: CM[n]STR[m] halts,1: CM[n]STR[m] starts counting"
group.long 0x410++0x03
line.long 0x00 "CM3CSR4,CM[n]CSR[m](n=1-3)(m=1-4) is a 32-bit register that indicates the occurrence of compare match enable interrupt and set the counter input clock"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
bitfld.long 0x00 15. "CMF,Compare Match Flag This flag indicates whether values of the compare match timer counter (CM[n]CNT[m]) and compare match timer constant register (CM[n]COR[m]) have matched or not" "0: CM[n]CNT[m] and CM[n]COR[m] values have not,1: CM[n]CNT[m] and CM[n]COR[m] values have matched"
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bitfld.long 0x00 14. "OVF,Overflow Flag This flag indicates whether the compare match timer counter (CM[n]CNT[m]) has overflowed or not" "0: CM[n]CNT[m] has not overflowed [Clearing,1: CM[n]CNT[m] has overflowed"
rbitfld.long 0x00 13. "WRFLG,Write State Flag Write access to CM[n]CNT[m] is prohibited while this this bit is 1" "0,1"
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rbitfld.long 0x00 10.--12. "Reserved_10,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 9. "CMS,Compare Match Timer Counter Size This bit and CM[n]CSRH[m].CMSH specify whether the compare match timer counter (CM[n]CNTH[m][15:0] and CM[n]CNT[m][31:0]) is used as a 16-bit counter a 32-bit counter or a 48-bit counter" "0: Operates as a 32-bit counter,1: Operates as a 16-bit counter"
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bitfld.long 0x00 8. "CMM,Compare Match Mode Specify counter operation mode" "0: One-shot operation,1: Free-running operation"
rbitfld.long 0x00 6.--7. "Reserved_6,Reserved These bits are always read as 0" "0,1,2,3"
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bitfld.long 0x00 4.--5. "CMR_1_0,Compare Match Request These bits enable or disable internal interrupt request in a compare match" "0: Disables internal interrupt request,1: Setting prohibited,2: Enables an internal interrupt request,3: Setting prohibited"
bitfld.long 0x00 3. "DBGIVD,Debug Mode Operation Select Sets the counter operation in debugging mode" "0: Stops the counter operation in debugging mode,1: Continues the counter operation even in"
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bitfld.long 0x00 0.--2. "CKS_2_0,Clock Select These bits and CM[n]CSRH[m].CKSH specify the input clock to CM[n]CNT[m]" "?,?,?,?,4: RCLK/8,5: RCLK/32,6: RCLK/128,7: RCLK/1"
group.long 0x414++0x03
line.long 0x00 "CM3CNT4,CM[n]CNT[m](n=1-3)(m=0-7) is a 32-bit register which is used as an up-counter of each channel"
hexmask.long 0x00 0.--31. 1. "CMCNT_31_0,Compare match timer counter bit31 to 0 Note: For access to this register refer to section 155.2.3.5 Register Access"
group.long 0x418++0x03
line.long 0x00 "CM3COR4,CM[n]COR[m] is a 32-bit register which specify the compare match period of CM[n]CNT[m] for each channel"
hexmask.long 0x00 0.--31. 1. "CMCOR_31_0,Compare match timer constant register bit31 to 0 Note: For access to this register refer to section 155.2.3.5 Register Access"
group.long 0x420++0x03
line.long 0x00 "CM3CSRH4,CM[n]CSRH[m] is a 32-bit register which specify the counter size and input clocks"
hexmask.long.tbyte 0x00 10.--31. 1. "Reserved_10,Reserved These bits are always read as 0"
bitfld.long 0x00 9. "CMSH,Compare Match Timer Counter Size This bit and CM[n]CSR[m].CMS specify whether the compare match timer counter (CM[n]CNTH[m][15:0] and CM[n]CNT[m][31:0]) is used as a 16-bit counter a 32-bit counter or a 48-bit counter" "0: Operates as a 32-bit counter,1: Operates as a 16-bit counter"
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hexmask.long.byte 0x00 1.--8. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "CKSH,Clock Select This bit and CM[n]CSR[m].CKS [2:0] select the clock input to CM[n]CNT[m]" "0,1"
group.long 0x424++0x03
line.long 0x00 "CM3CNTH4,CM[n]CNTH[m](n=1-3)(m=0-4) is a 32-bit register which is used as an up-counter for channel0 to 4"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
hexmask.long.word 0x00 0.--15. 1. "CMCNTH_15_0,Compare match timer counter H bit15 to 0 Note: For access to this register refer to section 155.2.3.5 Register Access"
group.long 0x428++0x03
line.long 0x00 "CM3CORH4,CM[n]CORH[m] is a 32-bit register which specify the compare match period with CM[n]CNTH[m] for channel0 to 4"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
hexmask.long.word 0x00 0.--15. 1. "CMCORH_15_0,Compare match timer constant register H bit15 to 0 Note: For access to this register refer to section 155.2.3.5 Register Access"
group.long 0x500++0x03
line.long 0x00 "CM3STR5,CM[n]STR[m] (n=1-3)(m=5-7) is a 32-bit register which specify the operation of compare match timer counter (CM[n]CNT[m])"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "STR0,Count Start 0 These bits specify start/halt of compare match timer counter (CM[n]STR[m])" "0: CM[n]STR[m] halts,1: CM[n]STR[m] starts counting"
group.long 0x510++0x03
line.long 0x00 "CM3CSR5,CM[n]CSR[m](n=1-3)(m=5-7) is a 32-bit register that indicates the occurrence of compare match enable interrupt and set the counter input clock"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
bitfld.long 0x00 15. "CMF,Compare Match Flag This flag indicates whether values of the compare match timer counter (CM[n]CNT[m]) and compare match timer constant register (CM[n]COR[m]) have matched or not" "0: CM[n]CNT[m] and CM[n]COR[m] values have not,1: CM[n]CNT[m] and CM[n]COR[m] values have matched"
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bitfld.long 0x00 14. "OVF,Overflow Flag This flag indicates whether the compare match timer counter (CM[n]CNT[m]) has overflowed or not" "0: CM[n]CNT[m] has not overflowed [Clearing,1: CM[n]CNT[m] has overflowed"
rbitfld.long 0x00 13. "WRFLG,Write State Flag Write access to CM[n]CNT[m] is prohibited while this this bit is 1" "0,1"
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rbitfld.long 0x00 10.--12. "Reserved_10,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 9. "CMS,Compare Match Timer Counter Size Selects whether the compare match timer counter (CM[n]CNT[m]) is used as a 16-bit counter or a 32-bit counter" "0: Operates as a 32-bit counter,1: Operates as a 16-bit counter"
newline
bitfld.long 0x00 8. "CMM,Compare Match Mode Specify counter operation mode" "0: One-shot operation,1: Free-running operation"
rbitfld.long 0x00 6.--7. "Reserved_6,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 4.--5. "CMR_1_0,Compare Match Request These bits enable or disable internal interrupt request in a compare match" "0: Disables internal interrupt request,1: Setting prohibited,2: Enables an internal interrupt request,3: Setting prohibited"
bitfld.long 0x00 3. "DBGIVD,Debug Mode Operation Select Sets the counter operation in debugging mode" "0: Stops the counter operation in debugging mode,1: Continues the counter operation even in"
newline
bitfld.long 0x00 0.--2. "CKS_2_0,Clock Select These bits select the clock input to CM[n]CNT[m]" "0: Setting prohibited,1: Setting prohibited,2: Setting prohibited,3: Setting prohibited,4: RCLK/8,5: RCLK/32,6: RCLK/128,7: RCLK/1"
group.long 0x514++0x03
line.long 0x00 "CM3CNT5,CM[n]CNT[m](n=1-3)(m=0-7) is a 32-bit register which is used as an up-counter of each channel"
hexmask.long 0x00 0.--31. 1. "CMCNT_31_0,Compare match timer counter bit31 to 0 Note: For access to this register refer to section 155.2.3.5 Register Access"
group.long 0x518++0x03
line.long 0x00 "CM3COR5,CM[n]COR[m] is a 32-bit register which specify the compare match period of CM[n]CNT[m] for each channel"
hexmask.long 0x00 0.--31. 1. "CMCOR_31_0,Compare match timer constant register bit31 to 0 Note: For access to this register refer to section 155.2.3.5 Register Access"
group.long 0x600++0x03
line.long 0x00 "CM3STR6,CM[n]STR[m] (n=1-3)(m=5-7) is a 32-bit register which specify the operation of compare match timer counter (CM[n]CNT[m])"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "STR0,Count Start 0 These bits specify start/halt of compare match timer counter (CM[n]STR[m])" "0: CM[n]STR[m] halts,1: CM[n]STR[m] starts counting"
group.long 0x610++0x03
line.long 0x00 "CM3CSR6,CM[n]CSR[m](n=1-3)(m=5-7) is a 32-bit register that indicates the occurrence of compare match enable interrupt and set the counter input clock"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
bitfld.long 0x00 15. "CMF,Compare Match Flag This flag indicates whether values of the compare match timer counter (CM[n]CNT[m]) and compare match timer constant register (CM[n]COR[m]) have matched or not" "0: CM[n]CNT[m] and CM[n]COR[m] values have not,1: CM[n]CNT[m] and CM[n]COR[m] values have matched"
newline
bitfld.long 0x00 14. "OVF,Overflow Flag This flag indicates whether the compare match timer counter (CM[n]CNT[m]) has overflowed or not" "0: CM[n]CNT[m] has not overflowed [Clearing,1: CM[n]CNT[m] has overflowed"
rbitfld.long 0x00 13. "WRFLG,Write State Flag Write access to CM[n]CNT[m] is prohibited while this this bit is 1" "0,1"
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rbitfld.long 0x00 10.--12. "Reserved_10,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 9. "CMS,Compare Match Timer Counter Size Selects whether the compare match timer counter (CM[n]CNT[m]) is used as a 16-bit counter or a 32-bit counter" "0: Operates as a 32-bit counter,1: Operates as a 16-bit counter"
newline
bitfld.long 0x00 8. "CMM,Compare Match Mode Specify counter operation mode" "0: One-shot operation,1: Free-running operation"
rbitfld.long 0x00 6.--7. "Reserved_6,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 4.--5. "CMR_1_0,Compare Match Request These bits enable or disable internal interrupt request in a compare match" "0: Disables internal interrupt request,1: Setting prohibited,2: Enables an internal interrupt request,3: Setting prohibited"
bitfld.long 0x00 3. "DBGIVD,Debug Mode Operation Select Sets the counter operation in debugging mode" "0: Stops the counter operation in debugging mode,1: Continues the counter operation even in"
newline
bitfld.long 0x00 0.--2. "CKS_2_0,Clock Select These bits select the clock input to CM[n]CNT[m]" "0: Setting prohibited,1: Setting prohibited,2: Setting prohibited,3: Setting prohibited,4: RCLK/8,5: RCLK/32,6: RCLK/128,7: RCLK/1"
group.long 0x614++0x03
line.long 0x00 "CM3CNT6,CM[n]CNT[m](n=1-3)(m=0-7) is a 32-bit register which is used as an up-counter of each channel"
hexmask.long 0x00 0.--31. 1. "CMCNT_31_0,Compare match timer counter bit31 to 0 Note: For access to this register refer to section 155.2.3.5 Register Access"
group.long 0x618++0x03
line.long 0x00 "CM3COR6,CM[n]COR[m] is a 32-bit register which specify the compare match period of CM[n]CNT[m] for each channel"
hexmask.long 0x00 0.--31. 1. "CMCOR_31_0,Compare match timer constant register bit31 to 0 Note: For access to this register refer to section 155.2.3.5 Register Access"
group.long 0x700++0x03
line.long 0x00 "CM3STR7,CM[n]STR[m] (n=1-3)(m=5-7) is a 32-bit register which specify the operation of compare match timer counter (CM[n]CNT[m])"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "STR0,Count Start 0 These bits specify start/halt of compare match timer counter (CM[n]STR[m])" "0: CM[n]STR[m] halts,1: CM[n]STR[m] starts counting"
group.long 0x710++0x03
line.long 0x00 "CM3CSR7,CM[n]CSR[m](n=1-3)(m=5-7) is a 32-bit register that indicates the occurrence of compare match enable interrupt and set the counter input clock"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
bitfld.long 0x00 15. "CMF,Compare Match Flag This flag indicates whether values of the compare match timer counter (CM[n]CNT[m]) and compare match timer constant register (CM[n]COR[m]) have matched or not" "0: CM[n]CNT[m] and CM[n]COR[m] values have not,1: CM[n]CNT[m] and CM[n]COR[m] values have matched"
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bitfld.long 0x00 14. "OVF,Overflow Flag This flag indicates whether the compare match timer counter (CM[n]CNT[m]) has overflowed or not" "0: CM[n]CNT[m] has not overflowed [Clearing,1: CM[n]CNT[m] has overflowed"
rbitfld.long 0x00 13. "WRFLG,Write State Flag Write access to CM[n]CNT[m] is prohibited while this this bit is 1" "0,1"
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rbitfld.long 0x00 10.--12. "Reserved_10,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 9. "CMS,Compare Match Timer Counter Size Selects whether the compare match timer counter (CM[n]CNT[m]) is used as a 16-bit counter or a 32-bit counter" "0: Operates as a 32-bit counter,1: Operates as a 16-bit counter"
newline
bitfld.long 0x00 8. "CMM,Compare Match Mode Specify counter operation mode" "0: One-shot operation,1: Free-running operation"
rbitfld.long 0x00 6.--7. "Reserved_6,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.long 0x00 4.--5. "CMR_1_0,Compare Match Request These bits enable or disable internal interrupt request in a compare match" "0: Disables internal interrupt request,1: Setting prohibited,2: Enables an internal interrupt request,3: Setting prohibited"
bitfld.long 0x00 3. "DBGIVD,Debug Mode Operation Select Sets the counter operation in debugging mode" "0: Stops the counter operation in debugging mode,1: Continues the counter operation even in"
newline
bitfld.long 0x00 0.--2. "CKS_2_0,Clock Select These bits select the clock input to CM[n]CNT[m]" "0: Setting prohibited,1: Setting prohibited,2: Setting prohibited,3: Setting prohibited,4: RCLK/8,5: RCLK/32,6: RCLK/128,7: RCLK/1"
group.long 0x714++0x03
line.long 0x00 "CM3CNT7,CM[n]CNT[m](n=1-3)(m=0-7) is a 32-bit register which is used as an up-counter of each channel"
hexmask.long 0x00 0.--31. 1. "CMCNT_31_0,Compare match timer counter bit31 to 0 Note: For access to this register refer to section 155.2.3.5 Register Access"
group.long 0x718++0x03
line.long 0x00 "CM3COR7,CM[n]COR[m] is a 32-bit register which specify the compare match period of CM[n]CNT[m] for each channel"
hexmask.long 0x00 0.--31. 1. "CMCOR_31_0,Compare match timer constant register bit31 to 0 Note: For access to this register refer to section 155.2.3.5 Register Access"
group.long 0x1000++0x03
line.long 0x00 "CM3CLKE,CM[n]CLKE is a 32bits register which specify clock supply to each channel"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 8.--15. 1. "Reserved_8,Reserved These bits are always read as 1"
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bitfld.long 0x00 7. "Ch7clke," "0,1"
bitfld.long 0x00 6. "Ch6clke," "0,1"
newline
bitfld.long 0x00 5. "Ch5clke," "0,1"
bitfld.long 0x00 4. "Ch4clke," "0,1"
newline
bitfld.long 0x00 3. "Ch3clke," "0,1"
bitfld.long 0x00 2. "Ch2clke," "0,1"
newline
bitfld.long 0x00 1. "Ch1clke," "0,1"
bitfld.long 0x00 0. "Ch0clke," "0,1"
tree.end
tree.end
tree "TMU"
tree "TMU_INST_0"
base ad:0xE61E0000
group.byte 0x04++0x00
line.byte 0x00 "TSTR0,TSTR are 8-bit readable/writable registers that select whether to run or halt the TCNT"
rbitfld.byte 0x00 3.--7. "Reserved_3,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.byte 0x00 2. "STR2,Counter Start 2 Selects whether to run or halt TCNT2" "0: TCNT2 count halted,1: TCNT2 counts"
newline
bitfld.byte 0x00 1. "STR1,Counter Start 1 Selects whether to run or halt TCNT1" "0: TCNT1 count halted,1: TCNT1 counts"
bitfld.byte 0x00 0. "STR0,Counter Start 0 Selects whether to run or halt TCNT0" "0: TCNT0 count halted,1: TCNT0 counts"
group.long 0x08++0x03
line.long 0x00 "TCOR00,TCOR are 32-bit readable/writable registers"
hexmask.long 0x00 0.--31. 1. "TCOR,Timer constant register"
group.long 0x0C++0x03
line.long 0x00 "TCNT00,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR"
hexmask.long 0x00 0.--31. 1. "TCNT,Timer counter"
group.word 0x10++0x01
line.word 0x00 "TCR00,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1"
rbitfld.word 0x00 10.--15. "Reserved_10,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.word 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
newline
bitfld.word 0x00 8. "UNF,Underflow Flag Status flag which indicates the occurrence of a TCNT underflow" "0: TCNT has not underflowed [Clearing condition],1: TCNT has underflowed [Setting condition] When"
rbitfld.word 0x00 6.--7. "Reserved_6,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.word 0x00 5. "UNIE,Underflow Interrupt Control Controls enabling of interrupt generation when the status flag (UNF) indicating TCNT underflow has been set to 1" "0: Interrupt due to underflow (TUNI) is not..,1: Interrupt due to underflow (TUNI) is enabled"
bitfld.word 0x00 3.--4. "CKEG,Clock Edge Select an input edge of the external clock when the external clock is selected or when the input capture function is used" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge..,?..."
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bitfld.word 0x00 0.--2. "TPSC,Timer Pre-scaler 2 to 0 Select the TCNT count clock" "0: Count on (input-clock)/4,1: Count on (input-clock)/16,2: Count on (input-clock)/64,3: Count on (input-clock)/256,4: Count on (input-clock)/1024,5: Setting prohibited,6: Setting prohibited,7: Setting prohibited"
group.long 0x14++0x03
line.long 0x00 "TCOR01,TCOR are 32-bit readable/writable registers"
hexmask.long 0x00 0.--31. 1. "TCOR,Timer constant register"
group.long 0x18++0x03
line.long 0x00 "TCNT01,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR"
hexmask.long 0x00 0.--31. 1. "TCNT,Timer counter"
group.word 0x1C++0x01
line.word 0x00 "TCR01,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1"
rbitfld.word 0x00 10.--15. "Reserved_10,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.word 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
newline
bitfld.word 0x00 8. "UNF,Underflow Flag Status flag which indicates the occurrence of a TCNT underflow" "0: TCNT has not underflowed [Clearing condition],1: TCNT has underflowed [Setting condition] When"
rbitfld.word 0x00 6.--7. "Reserved_6,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.word 0x00 5. "UNIE,Underflow Interrupt Control Controls enabling of interrupt generation when the status flag (UNF) indicating TCNT underflow has been set to 1" "0: Interrupt due to underflow (TUNI) is not..,1: Interrupt due to underflow (TUNI) is enabled"
bitfld.word 0x00 3.--4. "CKEG,Clock Edge Select an input edge of the external clock when the external clock is selected or when the input capture function is used" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge..,?..."
newline
bitfld.word 0x00 0.--2. "TPSC,Timer Pre-scaler 2 to 0 Select the TCNT count clock" "0: Count on (input-clock)/4,1: Count on (input-clock)/16,2: Count on (input-clock)/64,3: Count on (input-clock)/256,4: Count on (input-clock)/1024,5: Setting prohibited,6: Setting prohibited,7: Setting prohibited"
group.long 0x20++0x03
line.long 0x00 "TCOR02,TCOR are 32-bit readable/writable registers"
hexmask.long 0x00 0.--31. 1. "TCOR,Timer constant register"
group.long 0x24++0x03
line.long 0x00 "TCNT02,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR"
hexmask.long 0x00 0.--31. 1. "TCNT,Timer counter"
group.word 0x28++0x01
line.word 0x00 "TCR02,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1"
rbitfld.word 0x00 10.--15. "Reserved_10,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.word 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
newline
bitfld.word 0x00 8. "UNF,Underflow Flag Status flag which indicates the occurrence of a TCNT underflow" "0: TCNT has not underflowed [Clearing condition],1: TCNT has underflowed [Setting condition] When"
rbitfld.word 0x00 6.--7. "Reserved_6,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.word 0x00 5. "UNIE,Underflow Interrupt Control Controls enabling of interrupt generation when the status flag (UNF) indicating TCNT underflow has been set to 1" "0: Interrupt due to underflow (TUNI) is not..,1: Interrupt due to underflow (TUNI) is enabled"
bitfld.word 0x00 3.--4. "CKEG,Clock Edge Select an input edge of the external clock when the external clock is selected or when the input capture function is used" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge..,?..."
newline
bitfld.word 0x00 0.--2. "TPSC,Timer Pre-scaler 2 to 0 Select the TCNT count clock" "0: Count on (input-clock)/4,1: Count on (input-clock)/16,2: Count on (input-clock)/64,3: Count on (input-clock)/256,4: Count on (input-clock)/1024,5: Setting prohibited,6: Setting prohibited,7: Setting prohibited"
tree.end
tree "TMU_INST_1"
base ad:0xE6FC0000
group.byte 0x04++0x00
line.byte 0x00 "TSTR1,TSTR are 8-bit readable/writable registers that select whether to run or halt the TCNT"
rbitfld.byte 0x00 3.--7. "Reserved_3,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.byte 0x00 2. "STR2,Counter Start 2 Selects whether to run or halt TCNT2" "0: TCNT2 count halted,1: TCNT2 counts"
newline
bitfld.byte 0x00 1. "STR1,Counter Start 1 Selects whether to run or halt TCNT1" "0: TCNT1 count halted,1: TCNT1 counts"
bitfld.byte 0x00 0. "STR0,Counter Start 0 Selects whether to run or halt TCNT0" "0: TCNT0 count halted,1: TCNT0 counts"
group.long 0x08++0x03
line.long 0x00 "TCOR10,TCOR are 32-bit readable/writable registers"
hexmask.long 0x00 0.--31. 1. "TCOR,Timer constant register"
group.long 0x0C++0x03
line.long 0x00 "TCNT10,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR"
hexmask.long 0x00 0.--31. 1. "TCNT,Timer counter"
group.word 0x10++0x01
line.word 0x00 "TCR10,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1"
rbitfld.word 0x00 10.--15. "Reserved_10,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.word 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
newline
bitfld.word 0x00 8. "UNF,Underflow Flag Status flag which indicates the occurrence of a TCNT underflow" "0: TCNT has not underflowed [Clearing condition],1: TCNT has underflowed [Setting condition] When"
rbitfld.word 0x00 6.--7. "Reserved_6,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.word 0x00 5. "UNIE,Underflow Interrupt Control Controls enabling of interrupt generation when the status flag (UNF) indicating TCNT underflow has been set to 1" "0: Interrupt due to underflow (TUNI) is not..,1: Interrupt due to underflow (TUNI) is enabled"
bitfld.word 0x00 3.--4. "CKEG,Clock Edge Select an input edge of the external clock when the external clock is selected or when the input capture function is used" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge..,?..."
newline
bitfld.word 0x00 0.--2. "TPSC,Timer Pre-scaler 2 to 0 Select the TCNT count clock" "0: Count on (input-clock)/4,1: Count on (input-clock)/16,2: Count on (input-clock)/64,3: Count on (input-clock)/256,4: Count on (input-clock)/1024,5: Setting prohibited,6: Setting prohibited,7: Count on external clock Channels 3 to 4 TCLK1"
group.long 0x14++0x03
line.long 0x00 "TCOR11,TCOR are 32-bit readable/writable registers"
hexmask.long 0x00 0.--31. 1. "TCOR,Timer constant register"
group.long 0x18++0x03
line.long 0x00 "TCNT11,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR"
hexmask.long 0x00 0.--31. 1. "TCNT,Timer counter"
group.word 0x1C++0x01
line.word 0x00 "TCR11,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1"
rbitfld.word 0x00 10.--15. "Reserved_10,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.word 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
newline
bitfld.word 0x00 8. "UNF,Underflow Flag Status flag which indicates the occurrence of a TCNT underflow" "0: TCNT has not underflowed [Clearing condition],1: TCNT has underflowed [Setting condition] When"
rbitfld.word 0x00 6.--7. "Reserved_6,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.word 0x00 5. "UNIE,Underflow Interrupt Control Controls enabling of interrupt generation when the status flag (UNF) indicating TCNT underflow has been set to 1" "0: Interrupt due to underflow (TUNI) is not..,1: Interrupt due to underflow (TUNI) is enabled"
bitfld.word 0x00 3.--4. "CKEG,Clock Edge Select an input edge of the external clock when the external clock is selected or when the input capture function is used" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge..,?..."
newline
bitfld.word 0x00 0.--2. "TPSC,Timer Pre-scaler 2 to 0 Select the TCNT count clock" "0: Count on (input-clock)/4,1: Count on (input-clock)/16,2: Count on (input-clock)/64,3: Count on (input-clock)/256,4: Count on (input-clock)/1024,5: Setting prohibited,6: Setting prohibited,7: Count on external clock Channels 3 to 4 TCLK1"
group.long 0x20++0x03
line.long 0x00 "TCOR12,TCOR are 32-bit readable/writable registers"
hexmask.long 0x00 0.--31. 1. "TCOR,Timer constant register"
group.long 0x24++0x03
line.long 0x00 "TCNT12,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR"
hexmask.long 0x00 0.--31. 1. "TCNT,Timer counter"
group.word 0x28++0x01
line.word 0x00 "TCR12,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1"
rbitfld.word 0x00 10.--15. "Reserved_10,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.word 0x00 9. "ICPF,Input Capture Interrupt Flag Status flag provided in channels 5 and 8 11 14 only which indicates the occurrence of input capture" "0: No input capture has occurred [Clearing,1: Input capture has occurred [Setting condition]"
newline
bitfld.word 0x00 8. "UNF,Underflow Flag Status flag which indicates the occurrence of a TCNT underflow" "0: TCNT has not underflowed [Clearing condition],1: TCNT has underflowed [Setting condition] When"
bitfld.word 0x00 6.--7. "ICPE,Input Capture Control A function of channels 5 8 11" "0: Input capture function is not used,1: Reserved (setting prohibited),2: Input capture function is used,3: Input capture function is used"
newline
bitfld.word 0x00 5. "UNIE,Underflow Interrupt Control Controls enabling of interrupt generation when the status flag (UNF) indicating TCNT underflow has been set to 1" "0: Interrupt due to underflow (TUNI) is not..,1: Interrupt due to underflow (TUNI) is enabled"
bitfld.word 0x00 3.--4. "CKEG,Clock Edge Select an input edge of the external clock when the external clock is selected or when the input capture function is used" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge..,?..."
newline
bitfld.word 0x00 0.--2. "TPSC,Timer Pre-scaler 2 to 0 Select the TCNT count clock" "0: Count on (input-clock)/4,1: Count on (input-clock)/16,2: Count on (input-clock)/64,3: Count on (input-clock)/256,4: Count on (input-clock)/1024,5: Setting prohibited,6: Setting prohibited,7: Count on external clock Channels 5 TCLK1"
group.long 0x2C++0x03
line.long 0x00 "TCPR12,TCPR12 TCPR22 TCPR32 and TCPR42 are read-only 32-bit registers used for the input capture function provided only in channels 5 8 11 and 14"
hexmask.long 0x00 0.--31. 1. "TCPR,Input capture register"
tree.end
tree "TMU_INST_2"
base ad:0xE6FD0000
group.byte 0x04++0x00
line.byte 0x00 "TSTR2,TSTR are 8-bit readable/writable registers that select whether to run or halt the TCNT"
rbitfld.byte 0x00 3.--7. "Reserved_3,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.byte 0x00 2. "STR2,Counter Start 2 Selects whether to run or halt TCNT2" "0: TCNT2 count halted,1: TCNT2 counts"
newline
bitfld.byte 0x00 1. "STR1,Counter Start 1 Selects whether to run or halt TCNT1" "0: TCNT1 count halted,1: TCNT1 counts"
bitfld.byte 0x00 0. "STR0,Counter Start 0 Selects whether to run or halt TCNT0" "0: TCNT0 count halted,1: TCNT0 counts"
group.long 0x08++0x03
line.long 0x00 "TCOR20,TCOR are 32-bit readable/writable registers"
hexmask.long 0x00 0.--31. 1. "TCOR,Timer constant register"
group.long 0x0C++0x03
line.long 0x00 "TCNT20,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR"
hexmask.long 0x00 0.--31. 1. "TCNT,Timer counter"
group.word 0x10++0x01
line.word 0x00 "TCR20,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1"
rbitfld.word 0x00 10.--15. "Reserved_10,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.word 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
newline
bitfld.word 0x00 8. "UNF,Underflow Flag Status flag which indicates the occurrence of a TCNT underflow" "0: TCNT has not underflowed [Clearing condition],1: TCNT has underflowed [Setting condition] When"
rbitfld.word 0x00 6.--7. "Reserved_6,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.word 0x00 5. "UNIE,Underflow Interrupt Control Controls enabling of interrupt generation when the status flag (UNF) indicating TCNT underflow has been set to 1" "0: Interrupt due to underflow (TUNI) is not..,1: Interrupt due to underflow (TUNI) is enabled"
bitfld.word 0x00 3.--4. "CKEG,Clock Edge Select an input edge of the external clock when the external clock is selected or when the input capture function is used" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge..,?..."
newline
bitfld.word 0x00 0.--2. "TPSC,Timer Pre-scaler 2 to 0 Select the TCNT count clock" "0: Count on (input-clock)/4,1: Count on (input-clock)/16,2: Count on (input-clock)/64,3: Count on (input-clock)/256,4: Count on (input-clock)/1024,5: Setting prohibited,6: Setting prohibited,7: Count on external clock Channels 3 to 4 TCLK1"
group.long 0x14++0x03
line.long 0x00 "TCOR21,TCOR are 32-bit readable/writable registers"
hexmask.long 0x00 0.--31. 1. "TCOR,Timer constant register"
group.long 0x18++0x03
line.long 0x00 "TCNT21,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR"
hexmask.long 0x00 0.--31. 1. "TCNT,Timer counter"
group.word 0x1C++0x01
line.word 0x00 "TCR21,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1"
rbitfld.word 0x00 10.--15. "Reserved_10,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.word 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
newline
bitfld.word 0x00 8. "UNF,Underflow Flag Status flag which indicates the occurrence of a TCNT underflow" "0: TCNT has not underflowed [Clearing condition],1: TCNT has underflowed [Setting condition] When"
rbitfld.word 0x00 6.--7. "Reserved_6,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.word 0x00 5. "UNIE,Underflow Interrupt Control Controls enabling of interrupt generation when the status flag (UNF) indicating TCNT underflow has been set to 1" "0: Interrupt due to underflow (TUNI) is not..,1: Interrupt due to underflow (TUNI) is enabled"
bitfld.word 0x00 3.--4. "CKEG,Clock Edge Select an input edge of the external clock when the external clock is selected or when the input capture function is used" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge..,?..."
newline
bitfld.word 0x00 0.--2. "TPSC,Timer Pre-scaler 2 to 0 Select the TCNT count clock" "0: Count on (input-clock)/4,1: Count on (input-clock)/16,2: Count on (input-clock)/64,3: Count on (input-clock)/256,4: Count on (input-clock)/1024,5: Setting prohibited,6: Setting prohibited,7: Count on external clock Channels 3 to 4 TCLK1"
group.long 0x20++0x03
line.long 0x00 "TCOR22,TCOR are 32-bit readable/writable registers"
hexmask.long 0x00 0.--31. 1. "TCOR,Timer constant register"
group.long 0x24++0x03
line.long 0x00 "TCNT22,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR"
hexmask.long 0x00 0.--31. 1. "TCNT,Timer counter"
group.word 0x28++0x01
line.word 0x00 "TCR22,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1"
rbitfld.word 0x00 10.--15. "Reserved_10,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.word 0x00 9. "ICPF,Input Capture Interrupt Flag Status flag provided in channels 5 and 8 11 14 only which indicates the occurrence of input capture" "0: No input capture has occurred [Clearing,1: Input capture has occurred [Setting condition]"
newline
bitfld.word 0x00 8. "UNF,Underflow Flag Status flag which indicates the occurrence of a TCNT underflow" "0: TCNT has not underflowed [Clearing condition],1: TCNT has underflowed [Setting condition] When"
bitfld.word 0x00 6.--7. "ICPE,Input Capture Control A function of channels 5 8 11" "0: Input capture function is not used,1: Reserved (setting prohibited),2: Input capture function is used,3: Input capture function is used"
newline
bitfld.word 0x00 5. "UNIE,Underflow Interrupt Control Controls enabling of interrupt generation when the status flag (UNF) indicating TCNT underflow has been set to 1" "0: Interrupt due to underflow (TUNI) is not..,1: Interrupt due to underflow (TUNI) is enabled"
bitfld.word 0x00 3.--4. "CKEG,Clock Edge Select an input edge of the external clock when the external clock is selected or when the input capture function is used" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge..,?..."
newline
bitfld.word 0x00 0.--2. "TPSC,Timer Pre-scaler 2 to 0 Select the TCNT count clock" "0: Count on (input-clock)/4,1: Count on (input-clock)/16,2: Count on (input-clock)/64,3: Count on (input-clock)/256,4: Count on (input-clock)/1024,5: Setting prohibited,6: Setting prohibited,7: Count on external clock Channels 5 TCLK1"
group.long 0x2C++0x03
line.long 0x00 "TCPR22,TCPR12 TCPR22 TCPR32 and TCPR42 are read-only 32-bit registers used for the input capture function provided only in channels 5 8 11 and 14"
hexmask.long 0x00 0.--31. 1. "TCPR,Input capture register"
tree.end
tree "TMU_INST_3"
base ad:0xE6FE0000
group.byte 0x04++0x00
line.byte 0x00 "TSTR3,TSTR are 8-bit readable/writable registers that select whether to run or halt the TCNT"
rbitfld.byte 0x00 3.--7. "Reserved_3,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.byte 0x00 2. "STR2,Counter Start 2 Selects whether to run or halt TCNT2" "0: TCNT2 count halted,1: TCNT2 counts"
newline
bitfld.byte 0x00 1. "STR1,Counter Start 1 Selects whether to run or halt TCNT1" "0: TCNT1 count halted,1: TCNT1 counts"
bitfld.byte 0x00 0. "STR0,Counter Start 0 Selects whether to run or halt TCNT0" "0: TCNT0 count halted,1: TCNT0 counts"
group.long 0x08++0x03
line.long 0x00 "TCOR30,TCOR are 32-bit readable/writable registers"
hexmask.long 0x00 0.--31. 1. "TCOR,Timer constant register"
group.long 0x0C++0x03
line.long 0x00 "TCNT30,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR"
hexmask.long 0x00 0.--31. 1. "TCNT,Timer counter"
group.word 0x10++0x01
line.word 0x00 "TCR30,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1"
rbitfld.word 0x00 10.--15. "Reserved_10,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.word 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
newline
bitfld.word 0x00 8. "UNF,Underflow Flag Status flag which indicates the occurrence of a TCNT underflow" "0: TCNT has not underflowed [Clearing condition],1: TCNT has underflowed [Setting condition] When"
rbitfld.word 0x00 6.--7. "Reserved_6,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.word 0x00 5. "UNIE,Underflow Interrupt Control Controls enabling of interrupt generation when the status flag (UNF) indicating TCNT underflow has been set to 1" "0: Interrupt due to underflow (TUNI) is not..,1: Interrupt due to underflow (TUNI) is enabled"
bitfld.word 0x00 3.--4. "CKEG,Clock Edge Select an input edge of the external clock when the external clock is selected or when the input capture function is used" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge..,?..."
newline
bitfld.word 0x00 0.--2. "TPSC,Timer Pre-scaler 2 to 0 Select the TCNT count clock" "0: Count on (input-clock)/4,1: Count on (input-clock)/16,2: Count on (input-clock)/64,3: Count on (input-clock)/256,4: Count on (input-clock)/1024,5: Setting prohibited,6: Setting prohibited,7: Count on external clock Channels 3 to 4 TCLK1"
group.long 0x14++0x03
line.long 0x00 "TCOR31,TCOR are 32-bit readable/writable registers"
hexmask.long 0x00 0.--31. 1. "TCOR,Timer constant register"
group.long 0x18++0x03
line.long 0x00 "TCNT31,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR"
hexmask.long 0x00 0.--31. 1. "TCNT,Timer counter"
group.word 0x1C++0x01
line.word 0x00 "TCR31,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1"
rbitfld.word 0x00 10.--15. "Reserved_10,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.word 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
newline
bitfld.word 0x00 8. "UNF,Underflow Flag Status flag which indicates the occurrence of a TCNT underflow" "0: TCNT has not underflowed [Clearing condition],1: TCNT has underflowed [Setting condition] When"
rbitfld.word 0x00 6.--7. "Reserved_6,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.word 0x00 5. "UNIE,Underflow Interrupt Control Controls enabling of interrupt generation when the status flag (UNF) indicating TCNT underflow has been set to 1" "0: Interrupt due to underflow (TUNI) is not..,1: Interrupt due to underflow (TUNI) is enabled"
bitfld.word 0x00 3.--4. "CKEG,Clock Edge Select an input edge of the external clock when the external clock is selected or when the input capture function is used" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge..,?..."
newline
bitfld.word 0x00 0.--2. "TPSC,Timer Pre-scaler 2 to 0 Select the TCNT count clock" "0: Count on (input-clock)/4,1: Count on (input-clock)/16,2: Count on (input-clock)/64,3: Count on (input-clock)/256,4: Count on (input-clock)/1024,5: Setting prohibited,6: Setting prohibited,7: Count on external clock Channels 3 to 4 TCLK1"
group.long 0x20++0x03
line.long 0x00 "TCOR32,TCOR are 32-bit readable/writable registers"
hexmask.long 0x00 0.--31. 1. "TCOR,Timer constant register"
group.long 0x24++0x03
line.long 0x00 "TCNT32,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR"
hexmask.long 0x00 0.--31. 1. "TCNT,Timer counter"
group.word 0x28++0x01
line.word 0x00 "TCR32,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1"
rbitfld.word 0x00 10.--15. "Reserved_10,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.word 0x00 9. "ICPF,Input Capture Interrupt Flag Status flag provided in channels 5 and 8 11 14 only which indicates the occurrence of input capture" "0: No input capture has occurred [Clearing,1: Input capture has occurred [Setting condition]"
newline
bitfld.word 0x00 8. "UNF,Underflow Flag Status flag which indicates the occurrence of a TCNT underflow" "0: TCNT has not underflowed [Clearing condition],1: TCNT has underflowed [Setting condition] When"
bitfld.word 0x00 6.--7. "ICPE,Input Capture Control A function of channels 5 8 11" "0: Input capture function is not used,1: Reserved (setting prohibited),2: Input capture function is used,3: Input capture function is used"
newline
bitfld.word 0x00 5. "UNIE,Underflow Interrupt Control Controls enabling of interrupt generation when the status flag (UNF) indicating TCNT underflow has been set to 1" "0: Interrupt due to underflow (TUNI) is not..,1: Interrupt due to underflow (TUNI) is enabled"
bitfld.word 0x00 3.--4. "CKEG,Clock Edge Select an input edge of the external clock when the external clock is selected or when the input capture function is used" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge..,?..."
newline
bitfld.word 0x00 0.--2. "TPSC,Timer Pre-scaler 2 to 0 Select the TCNT count clock" "0: Count on (input-clock)/4,1: Count on (input-clock)/16,2: Count on (input-clock)/64,3: Count on (input-clock)/256,4: Count on (input-clock)/1024,5: Setting prohibited,6: Setting prohibited,7: Count on external clock Channels 5 TCLK1"
group.long 0x2C++0x03
line.long 0x00 "TCPR32,TCPR12 TCPR22 TCPR32 and TCPR42 are read-only 32-bit registers used for the input capture function provided only in channels 5 8 11 and 14"
hexmask.long 0x00 0.--31. 1. "TCPR,Input capture register"
tree.end
tree "TMU_INST_4"
base ad:0xFFC00000
group.byte 0x04++0x00
line.byte 0x00 "TSTR4,TSTR are 8-bit readable/writable registers that select whether to run or halt the TCNT"
rbitfld.byte 0x00 3.--7. "Reserved_3,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.byte 0x00 2. "STR2,Counter Start 2 Selects whether to run or halt TCNT2" "0: TCNT2 count halted,1: TCNT2 counts"
newline
bitfld.byte 0x00 1. "STR1,Counter Start 1 Selects whether to run or halt TCNT1" "0: TCNT1 count halted,1: TCNT1 counts"
bitfld.byte 0x00 0. "STR0,Counter Start 0 Selects whether to run or halt TCNT0" "0: TCNT0 count halted,1: TCNT0 counts"
group.long 0x08++0x03
line.long 0x00 "TCOR40,TCOR are 32-bit readable/writable registers"
hexmask.long 0x00 0.--31. 1. "TCOR,Timer constant register"
group.long 0x0C++0x03
line.long 0x00 "TCNT40,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR"
hexmask.long 0x00 0.--31. 1. "TCNT,Timer counter"
group.word 0x10++0x01
line.word 0x00 "TCR40,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1"
rbitfld.word 0x00 10.--15. "Reserved_10,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.word 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
newline
bitfld.word 0x00 8. "UNF,Underflow Flag Status flag which indicates the occurrence of a TCNT underflow" "0: TCNT has not underflowed [Clearing condition],1: TCNT has underflowed [Setting condition] When"
rbitfld.word 0x00 6.--7. "Reserved_6,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.word 0x00 5. "UNIE,Underflow Interrupt Control Controls enabling of interrupt generation when the status flag (UNF) indicating TCNT underflow has been set to 1" "0: Interrupt due to underflow (TUNI) is not..,1: Interrupt due to underflow (TUNI) is enabled"
bitfld.word 0x00 3.--4. "CKEG,Clock Edge Select an input edge of the external clock when the external clock is selected or when the input capture function is used" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge..,?..."
newline
bitfld.word 0x00 0.--2. "TPSC,Timer Pre-scaler 2 to 0 Select the TCNT count clock" "0: Count on (input-clock)/4,1: Count on (input-clock)/16,2: Count on (input-clock)/64,3: Count on (input-clock)/256,4: Count on (input-clock)/1024,5: Setting prohibited,6: Setting prohibited,7: Count on external clock Channels 3 to 4 TCLK1"
group.long 0x14++0x03
line.long 0x00 "TCOR41,TCOR are 32-bit readable/writable registers"
hexmask.long 0x00 0.--31. 1. "TCOR,Timer constant register"
group.long 0x18++0x03
line.long 0x00 "TCNT41,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR"
hexmask.long 0x00 0.--31. 1. "TCNT,Timer counter"
group.word 0x1C++0x01
line.word 0x00 "TCR41,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1"
rbitfld.word 0x00 10.--15. "Reserved_10,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.word 0x00 9. "Reserved_9,Reserved These bits are always read as 0" "0,1"
newline
bitfld.word 0x00 8. "UNF,Underflow Flag Status flag which indicates the occurrence of a TCNT underflow" "0: TCNT has not underflowed [Clearing condition],1: TCNT has underflowed [Setting condition] When"
rbitfld.word 0x00 6.--7. "Reserved_6,Reserved These bits are always read as 0" "0,1,2,3"
newline
bitfld.word 0x00 5. "UNIE,Underflow Interrupt Control Controls enabling of interrupt generation when the status flag (UNF) indicating TCNT underflow has been set to 1" "0: Interrupt due to underflow (TUNI) is not..,1: Interrupt due to underflow (TUNI) is enabled"
bitfld.word 0x00 3.--4. "CKEG,Clock Edge Select an input edge of the external clock when the external clock is selected or when the input capture function is used" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge..,?..."
newline
bitfld.word 0x00 0.--2. "TPSC,Timer Pre-scaler 2 to 0 Select the TCNT count clock" "0: Count on (input-clock)/4,1: Count on (input-clock)/16,2: Count on (input-clock)/64,3: Count on (input-clock)/256,4: Count on (input-clock)/1024,5: Setting prohibited,6: Setting prohibited,7: Count on external clock Channels 3 to 4 TCLK1"
group.long 0x20++0x03
line.long 0x00 "TCOR42,TCOR are 32-bit readable/writable registers"
hexmask.long 0x00 0.--31. 1. "TCOR,Timer constant register"
group.long 0x24++0x03
line.long 0x00 "TCNT42,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR"
hexmask.long 0x00 0.--31. 1. "TCNT,Timer counter"
group.word 0x28++0x01
line.word 0x00 "TCR42,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1"
rbitfld.word 0x00 10.--15. "Reserved_10,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.word 0x00 9. "ICPF,Input Capture Interrupt Flag Status flag provided in channels 5 and 8 11 14 only which indicates the occurrence of input capture" "0: No input capture has occurred [Clearing,1: Input capture has occurred [Setting condition]"
newline
bitfld.word 0x00 8. "UNF,Underflow Flag Status flag which indicates the occurrence of a TCNT underflow" "0: TCNT has not underflowed [Clearing condition],1: TCNT has underflowed [Setting condition] When"
bitfld.word 0x00 6.--7. "ICPE,Input Capture Control A function of channels 5 8 11" "0: Input capture function is not used,1: Reserved (setting prohibited),2: Input capture function is used,3: Input capture function is used"
newline
bitfld.word 0x00 5. "UNIE,Underflow Interrupt Control Controls enabling of interrupt generation when the status flag (UNF) indicating TCNT underflow has been set to 1" "0: Interrupt due to underflow (TUNI) is not..,1: Interrupt due to underflow (TUNI) is enabled"
bitfld.word 0x00 3.--4. "CKEG,Clock Edge Select an input edge of the external clock when the external clock is selected or when the input capture function is used" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge..,?..."
newline
bitfld.word 0x00 0.--2. "TPSC,Timer Pre-scaler 2 to 0 Select the TCNT count clock" "0: Count on (input-clock)/4,1: Count on (input-clock)/16,2: Count on (input-clock)/64,3: Count on (input-clock)/256,4: Count on (input-clock)/1024,5: Setting prohibited,6: Setting prohibited,7: Count on external clock Channels 5 TCLK1"
group.long 0x2C++0x03
line.long 0x00 "TCPR42,TCPR12 TCPR22 TCPR32 and TCPR42 are read-only 32-bit registers used for the input capture function provided only in channels 5 8 11 and 14"
hexmask.long 0x00 0.--31. 1. "TCPR,Input capture register"
tree.end
tree.end
tree "SCMT"
base ad:0xE6040000
group.word 0x00++0x01
line.word 0x00 "CMSSTR,CMSSTR is a 16-bit register which specify whether the compare match timer counter (CMSCNT) is operated or halted"
hexmask.word 0x00 6.--15. 1. "Reserved_6,Reserved These bits are always read as 0"
bitfld.word 0x00 5. "STR5,Count Start Specify halt/counting of compare match timer counter (CMSCNT)" "0: CMSCNT Halts,1: CMSCNT starts counting"
newline
rbitfld.word 0x00 0.--4. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x40++0x01
line.word 0x00 "CMSCSR,CMSCSR is a 16-bit register that indicates the occurrence of compare matches enables interrupts and sets the counter input clocks"
bitfld.word 0x00 15. "CMF,Compare Match Flag This flag indicates whether the values of the compare match timer counter (CMSCNT) and the compare match timer constant register (CMSCOR) have matched or not" "0: CMSCNT and CMSCOR values have not matched,1: CMSCNT and CMSCOR values have matched"
bitfld.word 0x00 14. "OVF,Overflow Flag This flag indicates whether the compare match timer counter (CMSCNT) has overflowed or not" "0: CMSCNT has not overflowed,1: CMSCNT has overflowed"
newline
rbitfld.word 0x00 13. "WRFLG,Write State Flag When this bit is 1 write access to CMSCNT is prohibited" "0,1"
rbitfld.word 0x00 10.--12. "Reserved_10,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.word 0x00 9. "CMS,Compare Match Timer Counter Size This bit selects whether the compare match timer counter (CMSCNT) is used as a 16-bit counter or 32-bit counter" "0: Operates as a 32-bit counter,1: Operates as a 16-bit counter"
bitfld.word 0x00 8. "CMM,Compare Match Mode Specify operation mode of the counter" "0: One-shot operation,1: Free-running operation"
newline
rbitfld.word 0x00 7. "Reserved_7,Reserved These bits are always read as 0" "0,1"
rbitfld.word 0x00 6. "Reserved_6,Reserved These bits are always read as 0" "0,1"
newline
bitfld.word 0x00 4.--5. "CMR_1_0,Compare Match Request These bits enable or disable an internal interrupt request at a compare match" "0: Disables an internal interrupt request,1: Setting prohibited,2: Enables an internal interrupt request,3: Setting prohibited"
bitfld.word 0x00 3. "DBGIVD,Debug Mode Operation Select This bit sets counter operation when in debug mode" "0: Stops counter operation when in debug mode,1: Enables counter operation even when in debug.."
newline
bitfld.word 0x00 0.--2. "CKS_2_0,Clock Select These bits select the clock input to CMSCNT" "0: Setting prohibited,1: Setting prohibited,2: Setting prohibited,3: Setting prohibited,4: clock/8,5: clock/32,6: clock/128,7: clock/1"
group.long 0x44++0x03
line.long 0x00 "CMSCNT,CMSCNT is a 32-bit register which is used as an up-counter"
hexmask.long 0x00 0.--31. 1. "CMSCNT_31_0,Compare match timer counter bit 31 to 0 Note: When Write or Read in this bit refer to 155.4.3.5 Register Access"
group.long 0x48++0x03
line.long 0x00 "CMSCOR,CMSCOR is a 32-bit register which specify the compare match period with the compare match timer counter (CMSCNT)"
hexmask.long 0x00 0.--31. 1. "CMSCOR_31_0,Compare match timer constant register bit31 to 0 Note: When Write or Read in this bit refer to 155.4.3.5 Register Access"
tree.end
tree "SUCMT"
base ad:0xE61D0000
group.word 0x00++0x01
line.word 0x00 "CMUSTR,CMUSTR is a 16-bit register that selects whether the compare match timer counter (CMUCNT) is operated or halted"
hexmask.word 0x00 6.--15. 1. "Reserved_6,Reserved These bits are always read as 0"
bitfld.word 0x00 5. "STR5,Count Start These bits specify start/halt of compare match timer counter (CMUCNT)" "0: CMUCNT halts,1: CMUCNT starts counting"
newline
rbitfld.word 0x00 0.--4. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x40++0x01
line.word 0x00 "CMUCSR,CMUCSR is a 16-bit register which indicates the occurrence of compare matches enables interrupts and sets the counter input clocks"
bitfld.word 0x00 15. "CMF,Compare Match Flag This flag indicates whether the values of the compare match timer counter (CMUCNT) and the compare match timer constant register (CMUCOR) have matched or not" "0: CMUCNT and CMUCOR values have not matched,1: CMUCNT and CMUCOR values have matched"
bitfld.word 0x00 14. "OVF,Overflow Flag This flag indicates whether the compare match timer counter (CMUCNT) has overflowed or not" "0: CMUCNT has not overflowed,1: CMUCNT has overflowed"
newline
rbitfld.word 0x00 13. "WRFLG,Write State Flag When this bit is 1 write access to CMUCNT is prohibited" "0,1"
rbitfld.word 0x00 12. "WERR,Write Access Error Flag This flag indicates whether or not the write access from the public domain" "0: Public domain has not Write access [Clearing,1: Public domain has Write access"
newline
rbitfld.word 0x00 10.--11. "Reserved_10,Reserved These bits are always read as 0" "0,1,2,3"
bitfld.word 0x00 9. "CMS,Compare Match Timer Counter Size This bit selects whether the compare match timer counter (CMUCNT) is used as a 16-bit counter or 32-bit counter" "0: Operates as a 32-bit counter,1: Operates as a 16-bit counter"
newline
bitfld.word 0x00 8. "CMM,Compare Match Mode This bit selects one-shot operation or free-running operation of the counter" "0: One-shot operation,1: Free-running operation"
rbitfld.word 0x00 7. "Reserved_7,Reserved This bit is always read as 0" "0,1"
newline
bitfld.word 0x00 6. "WER,Write Access Error Request This bit Write Access Error interrupt request at the public domain" "0: Disables an internal interrupt request,1: Enables an internal interrupt request"
bitfld.word 0x00 4.--5. "CMR_1_0,Compare Match Request These bits enable or disable an internal interrupt request at a compare match" "0: Disables an internal interrupt request,1: Setting prohibited,2: Enables an internal interrupt request,3: Setting prohibited Note1"
newline
bitfld.word 0x00 3. "DBGIVD,Debug Mode Operation Select This bit sets counter operation when in debug mode" "0: Stops counter operation when in debug mode,1: Enables counter operation even when in debug.."
bitfld.word 0x00 0.--2. "CKS_2_0,Clock Select These bits select the clock input to CMUCNT" "0: Setting prohibited,1: Setting prohibited,2: Setting prohibited,3: Setting prohibited,4: RCLK/8,5: RCLK/32,6: RCLK/128,7: RCLK/1"
group.long 0x44++0x03
line.long 0x00 "CMUCNT,CMUCNT is a 32-bit register which is used as an up-counter"
hexmask.long 0x00 0.--31. 1. "CMUCNT_31_0,Compare match timer counter bit31 to 0 Note: When Write or Read in this bit refer to 155.5.3.5 Register Access"
group.long 0x48++0x03
line.long 0x00 "CMUCOR,CMUCOR is a 32-bit register which specify the compare match period with the compare match timer counter (CMUCNT)"
hexmask.long 0x00 0.--31. 1. "CMUCOR_31_0,Compare match timer counter bit31 to 0 Note: When Write or Read in this bit refer to 155.5.3.5 Register Access"
tree.end
tree "HSSTP_CPU"
base ad:0xF8220000
group.long 0x540++0x03
line.long 0x00 "PCSR2,"
bitfld.long 0x00 29.--31. "Reserved0,Reserved These bits are always read as initial value" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 28. "Reserved1,Reserved This bit is always read as initial value" "0,1"
bitfld.long 0x00 24.--27. "Reserved2,Reserved These bits are always read as initial value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 22.--23. "Reserved3,Reserved These bits are always read as initial value" "0,1,2,3"
bitfld.long 0x00 16.--21. "CC_DURATION,The output period of Clock Compensation [R-Car S4] (CC_DURATION cycles in PCI PIPE?)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.long.word 0x00 0.--15. 1. "Reserved4,Reserved These bits are always read as initial value"
group.long 0x544++0x03
line.long 0x00 "TXFLR,"
hexmask.long.word 0x00 16.--31. 1. "Reserved,Reserved These bits are always read as initial value"
hexmask.long.word 0x00 0.--15. 1. "TX_FRAME_LENGTH,The frame length of Aurora frame"
group.long 0x550++0x03
line.long 0x00 "MCR,"
hexmask.long 0x00 6.--31. 1. "Reserved0,Reserved for future use"
bitfld.long 0x00 4.--5. "ECP_lane_select,B00: ECP is output from Lane0" "0,1,2,3"
bitfld.long 0x00 3. "CRC_octets,B0: (Set this value when CRC is embedded.) B1: (Set this value when CRC is not embedded.)" "0,1"
bitfld.long 0x00 2. "CRC_EN,B0: CRC is not embedded in trace data frame" "0,1"
bitfld.long 0x00 0.--1. "Reserved1,Reserved" "0,1,2,3"
group.long 0x558++0x03
line.long 0x00 "PLMR,"
hexmask.long 0x00 1.--31. 1. "Reserved,Reserved for future use"
bitfld.long 0x00 0. "LTS,[R-Car S4] Reserved for future use" "0,1"
group.long 0x5C0++0x03
line.long 0x00 "TSSR,"
hexmask.long 0x00 4.--31. 1. "Reserved,Reserved These bits are always read as initial value"
bitfld.long 0x00 0.--3. "Trace_Source_Select,Trace source selection [R-Car S4] When using PCIE physical unit for 2-lane H0: System Trace Macrocell is selected" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x630++0x03
line.long 0x00 "APCR,"
rbitfld.long 0x00 29.--31. "Reserved0,Reserved for future use" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24.--28. "Reserved1,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x00 17.--23. 1. "Reserved2,Reserved for future use"
bitfld.long 0x00 16. "Reserved3,Reserved for future use" "0,1"
hexmask.long.byte 0x00 9.--15. 1. "Reserved4,Reserved for future use"
newline
bitfld.long 0x00 8. "Reserved5,Reserved for future use" "0,1"
rbitfld.long 0x00 4.--7. "Reserved6,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 3. "TISDREN,[R-Car S4] Tx Driver Enable" "0: Disabled (default),1: Enabled"
rbitfld.long 0x00 0.--2. "Reserved7,Reserved for future use" "0,1,2,3,4,5,6,7"
group.long 0x638++0x03
line.long 0x00 "APSR,"
hexmask.long 0x00 1.--31. 1. "Reserved,Reserved for future use"
rbitfld.long 0x00 0. "COSPLOCK,PLL Lock Detect" "0: Unlocked,1: Locked"
tree.end
tree "HSSTP_DEBUGGER"
base ad:0x80220000
group.long 0x540++0x03
line.long 0x00 "PCSR2,"
bitfld.long 0x00 29.--31. "Reserved0,Reserved These bits are always read as initial value" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 28. "Reserved1,Reserved This bit is always read as initial value" "0,1"
bitfld.long 0x00 24.--27. "Reserved2,Reserved These bits are always read as initial value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 22.--23. "Reserved3,Reserved These bits are always read as initial value" "0,1,2,3"
bitfld.long 0x00 16.--21. "CC_DURATION,The output period of Clock Compensation [R-Car S4] (CC_DURATION cycles in PCI PIPE?)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.long.word 0x00 0.--15. 1. "Reserved4,Reserved These bits are always read as initial value"
group.long 0x544++0x03
line.long 0x00 "TXFLR,"
hexmask.long.word 0x00 16.--31. 1. "Reserved,Reserved These bits are always read as initial value"
hexmask.long.word 0x00 0.--15. 1. "TX_FRAME_LENGTH,The frame length of Aurora frame"
group.long 0x550++0x03
line.long 0x00 "MCR,"
hexmask.long 0x00 6.--31. 1. "Reserved0,Reserved for future use"
bitfld.long 0x00 4.--5. "ECP_lane_select,B00: ECP is output from Lane0" "0,1,2,3"
bitfld.long 0x00 3. "CRC_octets,B0: (Set this value when CRC is embedded.) B1: (Set this value when CRC is not embedded.)" "0,1"
bitfld.long 0x00 2. "CRC_EN,B0: CRC is not embedded in trace data frame" "0,1"
bitfld.long 0x00 0.--1. "Reserved1,Reserved" "0,1,2,3"
group.long 0x558++0x03
line.long 0x00 "PLMR,"
hexmask.long 0x00 1.--31. 1. "Reserved,Reserved for future use"
bitfld.long 0x00 0. "LTS,[R-Car S4] Reserved for future use" "0,1"
group.long 0x5C0++0x03
line.long 0x00 "TSSR,"
hexmask.long 0x00 4.--31. 1. "Reserved,Reserved These bits are always read as initial value"
bitfld.long 0x00 0.--3. "Trace_Source_Select,Trace source selection [R-Car S4] When using PCIE physical unit for 2-lane H0: System Trace Macrocell is selected" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x630++0x03
line.long 0x00 "APCR,"
rbitfld.long 0x00 29.--31. "Reserved0,Reserved for future use" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24.--28. "Reserved1,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x00 17.--23. 1. "Reserved2,Reserved for future use"
bitfld.long 0x00 16. "Reserved3,Reserved for future use" "0,1"
hexmask.long.byte 0x00 9.--15. 1. "Reserved4,Reserved for future use"
newline
bitfld.long 0x00 8. "Reserved5,Reserved for future use" "0,1"
rbitfld.long 0x00 4.--7. "Reserved6,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 3. "TISDREN,[R-Car S4] Tx Driver Enable" "0: Disabled (default),1: Enabled"
rbitfld.long 0x00 0.--2. "Reserved7,Reserved for future use" "0,1,2,3,4,5,6,7"
group.long 0x638++0x03
line.long 0x00 "APSR,"
hexmask.long 0x00 1.--31. 1. "Reserved,Reserved for future use"
rbitfld.long 0x00 0. "COSPLOCK,PLL Lock Detect" "0: Unlocked,1: Locked"
tree.end
tree "DEBUG_AND_TRACE_CPU"
tree "DEBUG_AND_TRACE_CPU_INST_0"
base ad:0xF81F0000
group.long 0x800++0x03
line.long 0x00 "PMUSNAPSHOTREQ,Address CPU view: H' F81F 0800 Debugger view: H' 801F 0800"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved0,Reserved"
bitfld.long 0x00 7. "CA55SS1_DSU1,Write signal value of PMUSNAPSHOTREQ to CA55SS1 DSU1" "0,1"
bitfld.long 0x00 6. "CA55SS1_DSU0,Write signal value of PMUSNAPSHOTREQ to CA55SS1 DSU0" "0,1"
newline
bitfld.long 0x00 5. "CA55SS0_DSU1,Write signal value of PMUSNAPSHOTREQ to CA55SS0 DSU1" "0,1"
bitfld.long 0x00 4. "CA55SS0_DSU0,Write signal value of PMUSNAPSHOTREQ to CA55SS0 DSU0" "0,1"
bitfld.long 0x00 0.--3. "Reserved1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x804++0x03
line.long 0x00 "PMUSNAPSHOTACK,Address CPU view: H' F81F 0804 Debugger view: H' 801F 0804"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved0,Reserved"
rbitfld.long 0x00 7. "CA55SS1_DSU1,Read signal value of PMUSNAPSHOTACK from CA55SS1 DSU1" "0,1"
rbitfld.long 0x00 6. "CA55SS1_DSU0,Read signal value of PMUSNAPSHOTACK from CA55SS1 DSU0" "0,1"
newline
rbitfld.long 0x00 5. "CA55SS0_DSU1,Read signal value of PMUSNAPSHOTACK from CA55SS0 DSU1" "0,1"
rbitfld.long 0x00 4. "CA55SS0_DSU0,Read signal value of PMUSNAPSHOTACK from CA55SS0 DSU0" "0,1"
rbitfld.long 0x00 0.--3. "Reserved1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xE00++0x03
line.long 0x00 "CSREG_E00,Address CPU view: H' F81F 0E00 Debugger view: H' 801F 0E00"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved"
bitfld.long 0x00 0. "STM0_FIXED_AWBURST_enable,Override AWBURST at input of STM0 to FIXED type" "0: disable,1: enable"
group.long 0xE04++0x03
line.long 0x00 "CSREG_E01,Address CPU view: H' F81F 0E04 Debugger view: H' 801F 0E04"
hexmask.long.word 0x00 20.--31. 1. "Reserved0,Reserved"
bitfld.long 0x00 16.--19. "STM0_Master_ID_Generator_Operating_Mode," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--15. 1. "Reserved1,Reserved"
group.long 0xFB0++0x03
line.long 0x00 "LOCKACCESS,Address CPU view: H' F81F 0FB0 Debugger view: H' 801F 0FB0"
hexmask.long 0x00 0.--31. 1. "KEY_31_0,Lock Access Register"
group.long 0xFB4++0x03
line.long 0x00 "LOCKSTATUS,Address CPU view: H' F81F 0FB4 Debugger view: H' 801F 0FB4"
hexmask.long 0x00 3.--31. 1. "Reserved_3,Lock Status Register"
rbitfld.long 0x00 2. "nTT,Lock Status Register" "0,1"
rbitfld.long 0x00 1. "SLK,Lock Status Register" "0,1"
newline
rbitfld.long 0x00 0. "SLI,Lock Status Register" "0,1"
group.long 0xFD0++0x03
line.long 0x00 "Peripheral_ID4,Address CPU view: H' F81F 0FD0 Debugger view: H' 801F 0FD0"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved"
rbitfld.long 0x00 4.--7. "_4KB_count_3_0,Indicates that the device only occupies 4KB of memory" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 0.--3. "JEP106_continuation_code_3_0,JEDEC code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xFE0++0x03
line.long 0x00 "Peripheral_ID0,Address CPU view: H' F81F 0FE0 Debugger view: H' 801F 0FE0"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved"
hexmask.long.byte 0x00 0.--7. 1. "Part_No_0_7_0,part number of the component"
group.long 0xFE4++0x03
line.long 0x00 "Peripheral_ID1,Address CPU view: H' F81F 0FE4 Debugger view: H' 801F 0FE4"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved"
rbitfld.long 0x00 4.--7. "JEP106_ID_code_3_0,JEDEC code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 0.--3. "Part_No_1_3_0,part number of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xFE8++0x03
line.long 0x00 "Peripheral_ID2,Address CPU view: H' F81F 0FE8 Debugger view: H' 801F 0FE8"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved"
rbitfld.long 0x00 4.--7. "Rev_3_0,Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 3. "Reserved_3,Reserved" "0,1"
newline
rbitfld.long 0x00 0.--2. "JEP106_ID_code_6_4,JEDEC code" "0,1,2,3,4,5,6,7"
group.long 0xFEC++0x03
line.long 0x00 "Peripheral_ID3,Address CPU view: H' F81F 0FEC Debugger view: H' 801F 0FEC"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved"
rbitfld.long 0x00 4.--7. "RevAnd_3_0,Indicates that there are no errata fixes to this component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 0.--3. "CustomerModified_3_0,Indicates that the customer has not modified this component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xFF0++0x03
line.long 0x00 "Component_ID0,Address CPU view: H' F81F 0FF0 Debugger view: H' 801F 0FF0"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved"
hexmask.long.byte 0x00 0.--7. 1. "Preamble_7_0,component identification code"
group.long 0xFF4++0x03
line.long 0x00 "Component_ID1,Address CPU view: H' F81F 0FF4 Debugger view: H' 801F 0FF4"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved"
rbitfld.long 0x00 4.--7. "Component_class_3_0,Class of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 0.--3. "Preamble_3_0,component identification code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xFF8++0x03
line.long 0x00 "Component_ID2,Address CPU view: H' F81F 0FF8 Debugger view: H' 801F 0FF8"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved"
hexmask.long.byte 0x00 0.--7. 1. "Preamble_7_0,component identification code"
group.long 0xFFC++0x03
line.long 0x00 "Component_ID3,Address CPU view: H' F81F 0FFC Debugger view: H' 801F 0FFC"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved_8,Reserved"
hexmask.long.byte 0x00 0.--7. 1. "Preamble_7_0,component identification code"
tree.end
tree "DEBUG_AND_TRACE_CPU_INST_1"
base ad:0xE6100000
group.long 0x20++0x03
line.long 0x00 "DBGREG1,"
rbitfld.long 0x00 31. "MD11,*1:The value of the MD11 pin input is reflected in the initial value" "0,1"
rbitfld.long 0x00 30. "MD10,*1:The value of the MD10 pin input is reflected in the initial value" "0,1"
newline
rbitfld.long 0x00 28.--29. "MD21_MD20,*1:The value of MD21 and MD20 pin input is reflected in the initial value" "0,1,2,3"
hexmask.long.word 0x00 17.--27. 1. "Reserved_17,Reserved These bits are always read as 0"
newline
rbitfld.long 0x00 16. "MDT_0,*1:The value of the MDT0 pin input is reflected in the initial value" "0,1"
hexmask.long.word 0x00 0.--15. 1. "Reserved_0,Reserved These bits are always read as 0"
group.long 0x24++0x03
line.long 0x00 "DBGREG2,"
hexmask.long 0x00 3.--31. 1. "Reserved_3,Reserved These bits are always read as 0"
bitfld.long 0x00 0.--2. "DMON2EN,Selects how PCIe0 or PCIe1 port is used by HSSTP/Nexus Aurora link" "0: PCIe0 or PCIe1 port isnt occupied by,1: HSSTP Aurora link uses PCIe0 port as trace..,2: HSSTP Aurora link uses PCIe1 port as trace..,3: Reserved,4: Nexus Aurora link uses PCIe0 port as trace..,5: Nexus Aurora link uses PCIe1 port as trace..,6: Reserved,7: Reserved"
group.long 0x2C++0x03
line.long 0x00 "DBGREG4,Depends on the setting of the MD21 MD20 MD11 MD10 MDT[1:0] pins and Security state"
hexmask.long.word 0x00 22.--31. 1. "Reserved_22,Reserved These bits are always read as 0"
rbitfld.long 0x00 21. "DEBUG_ENABLE_ICUMH,Indicates disable or enable of ICUMH debug mode" "0: Disable,1: Enable"
newline
rbitfld.long 0x00 20. "DEBUG_ENABLE_G4MH,Indicates disable or enable of G4MH debug mode" "0: Disable,1: Enable"
rbitfld.long 0x00 19. "CA5x_SPNIDEN,Indicates disable or enable of the SPNIDEN of CA55" "0: Disable,1: Enable"
newline
rbitfld.long 0x00 18. "CA5x_SPIDEN,Indicates disable or enable of the SPIDEN of CA55" "0: Disable,1: Enable"
rbitfld.long 0x00 17. "CA5x_NIDEN,Indicates disable or enable of the NIDEN of CA55" "0: Disable,1: Enable"
newline
rbitfld.long 0x00 16. "CA5x_DBGEN,Indicates disable or enable of the DBGEN of CA55" "0: Disable,1: Enable"
rbitfld.long 0x00 13.--15. "Reserved_13,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 12. "CS_DEVEN,Indicates disable or enable of the DAP_DEVICEEN of CoreSight" "0: Disable,1: Enable"
rbitfld.long 0x00 11. "CS_SPNIDEN,Indicates disable or enable of the SPNIDEN of CoreSight" "0: Disable,1: Enable"
newline
rbitfld.long 0x00 10. "CS_SPIDEN,Indicates disable or enable of the SPIDEN of CoreSight" "0: Disable,1: Enable"
rbitfld.long 0x00 9. "CS_NIDEN,Indicates disable or enable of the NIDEN of CoreSight" "0: Disable,1: Enable"
newline
rbitfld.long 0x00 8. "CS_DBGEN,Indicates disable or enable of the DBGEN of CoreSight" "0: Disable,1: Enable"
rbitfld.long 0x00 7. "CR_HNIDEN,Indicates disable or enable of the HNIDEN of Cortex-R52" "0: Disable,1: Enable"
newline
rbitfld.long 0x00 6. "CR_HIDEN,Indicates disable or enable of the HIDEN of Cortex-R52" "0: Disable,1: Enable"
rbitfld.long 0x00 5. "CR_NIDEN,Indicates disable or enable of the NIDEN of Cortex-R52" "0: Disable,1: Enable"
newline
rbitfld.long 0x00 4. "CR_DBGEN,Indicates disable or enable of the DBGEN of Cortex-R52" "0: Disable,1: Enable"
rbitfld.long 0x00 0.--3. "Reserved_0,Reserved These bits are always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x40++0x03
line.long 0x00 "DBGREG9,"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved These bits are always read as 0"
hexmask.long.byte 0x00 8.--15. 1. "AID_7_0,KEY Bit Write Aid Use this bit to write a bit pattern (H'A5) to be written to the KEY bit"
newline
hexmask.long.byte 0x00 1.--7. 1. "Reserved_1,Reserved These bits are always read as 0"
bitfld.long 0x00 0. "KEY,DBGREG2 access control Provides access control to the DBGREG2" "0: It is not possible to perform write operations,1: It is possible to perform write operations to"
tree.end
tree.end
tree "FUNCTIONAL_SAFETY"
tree "FUNCTIONAL_SAFETY_INST_0"
base ad:0xFF820000
group.long 0x00++0x03
line.long 0x00 "RTTEX1,SLFR and SLFE bit of the RTTEX are effective only when KCD bit is H'F1"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved" "0,1,2,3"
bitfld.long 0x00 29. "SLFR,Self-Check Counter Reset for field BIST activator" "0: Counter Reset,1: Counter not Reset"
newline
bitfld.long 0x00 28. "SLFE,Execution of Self-Check for Field BIST activator" "0: Not Execution of Self-Check for Field BIST,1: Execution of Self-Check for Field BIST.."
rbitfld.long 0x00 24.--27. "Reserved_24,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.byte 0x00 16.--23. 1. "KCD,Key Code H'5A: Effective execution of Run Time Test H'F1: Effective execution of Self-Check for field BIST activator"
rbitfld.long 0x00 11.--15. "Reserved_11,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "STM,Single Step Test Mode" "?,1: LBIST,2: MBIST,3: SCAN,?..."
bitfld.long 0x00 6.--7. "INTM,Interrupt mask" "0: non mask *1,?,2: Only at the time of the fail(fba_rt_finish are,?..."
newline
bitfld.long 0x00 5. "SSZ,SCAN Pattern size Valid only when STM=011" "0: 32bit mode,1: 16bit mode"
bitfld.long 0x00 4. "TR,Select the value of the timer" "0: ROM,1: register"
newline
bitfld.long 0x00 3. "WM,Wfi mask" "0: not mask,1: mask"
bitfld.long 0x00 2. "TM,Mask the judgment of timer" "0: not mask,1: mask"
newline
bitfld.long 0x00 1. "STP,Single Step Mode" "0: ROM batch mode,1: Single Step Mode"
bitfld.long 0x00 0. "EX,Execution of Runtime Test" "0: Not Execution of Runtime Test,1: Execution of Runtime Test"
group.long 0x04++0x03
line.long 0x00 "RTTMI11,"
rbitfld.long 0x00 27.--31. "Reserved_27,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 24.--26. "RPROT,Protection type of MEMORY" "0: Unprivileged access,1: Privileged access,?..."
newline
hexmask.long.byte 0x00 16.--23. 1. "MADDR_upper,Memory upper address[39:32] that stores the SCAN pattern"
hexmask.long.word 0x00 0.--15. 1. "MUNIT,Number of units (1 unit = 128 Byte)"
group.long 0x08++0x03
line.long 0x00 "RTTMI21,"
hexmask.long 0x00 0.--31. 1. "MADDR,Memory address that stores the SCAN pattern"
group.long 0x0C++0x03
line.long 0x00 "RTTSISR11,"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved"
hexmask.long.tbyte 0x00 0.--19. 1. "SISR1,SISR-TEST#1 Expected value"
group.long 0x14++0x03
line.long 0x00 "RTTUC1,"
hexmask.long 0x00 0.--31. 1. "U_WDT,Upper counter of Watchdog Timer"
group.long 0x18++0x03
line.long 0x00 "RTTDC1,"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved"
hexmask.long.word 0x00 0.--15. 1. "L_WDT,Lower counter of Watchdog Timer"
group.long 0x80++0x03
line.long 0x00 "RTTSET0_1,"
hexmask.long 0x00 0.--31. 1. "test_clock,Test setting input"
group.long 0x84++0x03
line.long 0x00 "RTTSET1_1,"
hexmask.long 0x00 2.--31. 1. "Reserved_2,Reserved"
bitfld.long 0x00 1. "reset,Test setting input" "0: Reset test disabled,1: Reset test enabled"
newline
bitfld.long 0x00 0. "tt,Test setting input" "0: Selected other clock,1: Selected test clock for test Domain"
group.long 0x88++0x03
line.long 0x00 "RTTSET2_1,"
hexmask.long 0x00 0.--31. 1. "hold0,Test setting input"
group.long 0x8C++0x03
line.long 0x00 "RTTSET3_1,"
hexmask.long.tbyte 0x00 8.--31. 1. "hold1,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "hold0,Test setting input"
group.long 0x90++0x03
line.long 0x00 "RTTSET4_1,"
hexmask.long.word 0x00 16.--31. 1. "hold2,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "hold1,Test setting input"
group.long 0x94++0x03
line.long 0x00 "RTTSET5_1,"
hexmask.long.byte 0x00 24.--31. 1. "hold3,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "hold2,Test setting input"
group.long 0x98++0x03
line.long 0x00 "RTTSET6_1,"
hexmask.long 0x00 0.--31. 1. "hold3,Test setting input"
group.long 0x9C++0x03
line.long 0x00 "RTTSET7_1,"
hexmask.long 0x00 0.--31. 1. "toggle0,Test setting input"
group.long 0xA0++0x03
line.long 0x00 "RTTSET8_1,"
hexmask.long.tbyte 0x00 8.--31. 1. "toggle1,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "toggle0,Test setting input"
group.long 0xA4++0x03
line.long 0x00 "RTTSET9_1,"
hexmask.long.word 0x00 16.--31. 1. "toggle2,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "toggle1,Test setting input"
group.long 0xA8++0x03
line.long 0x00 "RTTSET10_1,"
hexmask.long.byte 0x00 24.--31. 1. "toggle3,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "toggle2,Test setting input"
group.long 0xAC++0x03
line.long 0x00 "RTTSET11_1,"
hexmask.long 0x00 0.--31. 1. "toggle3,Test setting input"
group.long 0xB0++0x03
line.long 0x00 "RTTSET12_1,"
hexmask.long 0x00 0.--31. 1. "switching0,Test setting input"
group.long 0xB4++0x03
line.long 0x00 "RTTSET13_1,"
hexmask.long.tbyte 0x00 8.--31. 1. "switching1,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "switching0,Test setting input"
group.long 0xB8++0x03
line.long 0x00 "RTTSET14_1,"
hexmask.long.word 0x00 16.--31. 1. "switching2,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "switching1,Test setting input"
group.long 0xBC++0x03
line.long 0x00 "RTTSET15_1,"
hexmask.long.byte 0x00 24.--31. 1. "switching3,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "switching2,Test setting input"
group.long 0xC0++0x03
line.long 0x00 "RTTSET16_1,"
hexmask.long 0x00 0.--31. 1. "switching3,Test setting input"
group.long 0xC4++0x03
line.long 0x00 "RTTSET17_1,"
hexmask.long 0x00 0.--31. 1. "hold4,Test setting input"
group.long 0xC8++0x03
line.long 0x00 "RTTSET18_1,"
hexmask.long.tbyte 0x00 8.--31. 1. "hold5,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "hold4,Test setting input"
group.long 0xCC++0x03
line.long 0x00 "RTTSET19_1,"
hexmask.long.word 0x00 16.--31. 1. "hold6,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "hold5,Test setting input"
group.long 0xD0++0x03
line.long 0x00 "RTTSET20_1,"
hexmask.long.byte 0x00 24.--31. 1. "hold7,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "hold6,Test setting input"
group.long 0xD4++0x03
line.long 0x00 "RTTSET21_1,"
hexmask.long 0x00 0.--31. 1. "hold7,Test setting input"
group.long 0xD8++0x03
line.long 0x00 "RTTSET22_1,"
hexmask.long 0x00 0.--31. 1. "toggle4,Test setting input"
group.long 0xDC++0x03
line.long 0x00 "RTTSET23_1,"
hexmask.long.tbyte 0x00 8.--31. 1. "toggle5,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "toggle4,Test setting input"
group.long 0xE0++0x03
line.long 0x00 "RTTSET24_1,"
hexmask.long.word 0x00 16.--31. 1. "toggle6,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "toggle5,Test setting input"
group.long 0xE4++0x03
line.long 0x00 "RTTSET25_1,"
hexmask.long.byte 0x00 24.--31. 1. "toggle7,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "toggle6,Test setting input"
group.long 0xE8++0x03
line.long 0x00 "RTTSET26_1,"
hexmask.long 0x00 0.--31. 1. "toggle7,Test setting input"
group.long 0xEC++0x03
line.long 0x00 "RTTSET27_1,"
hexmask.long 0x00 0.--31. 1. "switching4,Test setting input"
group.long 0xF0++0x03
line.long 0x00 "RTTSET28_1,"
hexmask.long.tbyte 0x00 8.--31. 1. "switching5,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "switching4,Test setting input"
group.long 0xF4++0x03
line.long 0x00 "RTTSET29_1,"
hexmask.long.word 0x00 16.--31. 1. "switching6,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "switching5,Test setting input"
group.long 0xF8++0x03
line.long 0x00 "RTTSET30_1,"
hexmask.long.byte 0x00 24.--31. 1. "switching7,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "switching6,Test setting input"
group.long 0xFC++0x03
line.long 0x00 "RTTSET31_1,"
hexmask.long 0x00 0.--31. 1. "switching7,Test setting input"
group.long 0x100++0x03
line.long 0x00 "RTTSET32_1,"
hexmask.long 0x00 0.--31. 1. "clknum_31_0,Test setting input"
group.long 0x104++0x03
line.long 0x00 "RTTSET33_1,"
hexmask.long 0x00 0.--31. 1. "Testmat_31_0,Test setting input"
group.long 0x108++0x03
line.long 0x00 "RTTSET34_1,"
hexmask.long 0x00 0.--31. 1. "Testmat_63_32,Test setting input"
group.long 0x10C++0x03
line.long 0x00 "RTTSET35_1,"
hexmask.long 0x00 0.--31. 1. "Testmat_95_64,Test setting input"
group.long 0x110++0x03
line.long 0x00 "RTTSET36_1,"
hexmask.long 0x00 0.--31. 1. "Testmat_127_96,Test setting input"
group.long 0x114++0x03
line.long 0x00 "RTTSET37_1,"
hexmask.long 0x00 0.--31. 1. "Testmat_159_128,Test setting input"
group.long 0x118++0x03
line.long 0x00 "RTTSET38_1,"
hexmask.long 0x00 0.--31. 1. "Testmat_191_160,Test setting input"
group.long 0x11C++0x03
line.long 0x00 "RTTSET39_1,"
hexmask.long 0x00 0.--31. 1. "Testmat_223_192,Test setting input"
group.long 0x120++0x03
line.long 0x00 "RTTSET40_1,"
hexmask.long 0x00 0.--31. 1. "Testmat_255_224,Test setting input"
group.long 0x124++0x03
line.long 0x00 "RTTSET41_1,"
hexmask.long.word 0x00 18.--31. 1. "Reserved_18,Reserved The bit or field is readable only"
hexmask.long.byte 0x00 10.--17. 1. "apbsel,Test setting input"
newline
bitfld.long 0x00 6.--9. "mbsel,Test setting input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--5. "coreselect,Test setting input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x128++0x03
line.long 0x00 "RTTSET42_1,"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved The bit or field is readable only" "0,1,2,3"
hexmask.long.word 0x00 16.--29. 1. "Y_address,Test setting input"
newline
rbitfld.long 0x00 14.--15. "Reserved_14,Reserved The bit or field is readable only" "0,1,2,3"
hexmask.long.word 0x00 0.--13. 1. "X_address,Test setting input"
group.long 0x12C++0x03
line.long 0x00 "RTTSET43_1,"
rbitfld.long 0x00 31. "Reserved_31,Reserved The bit or field is readable only" "0,1"
hexmask.long.tbyte 0x00 14.--30. 1. "XY,Test setting input"
newline
hexmask.long.word 0x00 0.--13. 1. "Z_address,Test setting input"
group.long 0x130++0x03
line.long 0x00 "RTTSET44_1,"
rbitfld.long 0x00 26.--31. "Reserved_26,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x00 16.--25. 1. "scanchain,Test setting input for hardware-SCAN"
newline
hexmask.long.word 0x00 0.--15. 1. "scanpat,Test setting input for hardware-SCAN"
group.long 0x400++0x03
line.long 0x00 "PSTRSTT1,"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved"
rbitfld.long 0x00 12. "R_rst_T,BIST Redundant result" "0: pass,1: fail"
newline
rbitfld.long 0x00 11. "Reserved_11,Reserved" "0,1"
rbitfld.long 0x00 8.--10. "error_T,BIST error" "0: Pass,1: Fail,2: TimeOut,?,4: BUS error,?..."
newline
rbitfld.long 0x00 4.--7. "testnum_T,Number of tests" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 2.--3. "status_R,BIST Redundant status (Safety function)" "0: unexec,1: wait,2: exec,3: finish"
newline
rbitfld.long 0x00 0.--1. "status_T,BIST status" "0: unexec,1: wait,2: exec,3: finish"
group.long 0x440++0x03
line.long 0x00 "PSTCNT1,"
hexmask.long 0x00 0.--31. 1. "Stop,FieldBIST internal WDT (high counter) stop value"
group.long 0x444++0x03
line.long 0x00 "RTTRSTT1,When status_T in the RTTRSTT register is"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved" "0,1,2,3"
rbitfld.long 0x00 29. "IL_flag2,Runtime Test Illegal suspension flag-2" "0,1"
newline
rbitfld.long 0x00 28. "IL_flag1,Runtime Test Illegal suspension flag-1" "0,1"
rbitfld.long 0x00 27. "CONDF,Debug monitor of FieldBIST condition" "0: not response,1: responded"
newline
rbitfld.long 0x00 24.--26. "BUS_cond,Debug code of BUS condition" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 13.--23. 1. "Reserved_13,Reserved"
newline
rbitfld.long 0x00 12. "R_rst_T,BIST Redundant result (Safety function)" "0: Pass,1: Fail"
rbitfld.long 0x00 11. "Achk,Debug code of address check" "0: normal,1: warning"
newline
rbitfld.long 0x00 8.--10. "error_T,BIST error" "0: Pass,1: Fail,2: TimeOut,?,4: BUS error,?..."
rbitfld.long 0x00 4.--7. "testnum_T,Number of tests" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 2.--3. "R_status_T,BIST redundant status" "0: unexec,1: wait,2: exec,3: finish"
rbitfld.long 0x00 0.--1. "status_T,BIST status" "0: unexec,1: wait,2: exec,3: finish"
group.long 0x458++0x03
line.long 0x00 "RTTCNT1,"
hexmask.long 0x00 0.--31. 1. "Stop,WDT (high counter) stop value"
group.long 0x4A0++0x03
line.long 0x00 "SLFRVS1,"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved"
hexmask.long.tbyte 0x00 0.--19. 1. "REVERS,Expected value reverse for Self-Check SISR"
group.long 0x4A4++0x03
line.long 0x00 "SLFRST1,In case of the SLFR bits of the RTTRSTT register is 1B'1 SCNT bit returns to 1"
rbitfld.long 0x00 26.--31. "SCNT,Self-Check counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 24.--25. "STS,Self-Check status" "0: unexec,1: exec,?,3: finish"
newline
hexmask.long.tbyte 0x00 1.--23. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "STR,Self -Check Result" "0: Pass,1: Fail"
group.long 0x4C0++0x03
line.long 0x00 "ERRSET1,"
hexmask.long 0x00 3.--31. 1. "Reserved_3,Reserved"
bitfld.long 0x00 2. "DSB,Dummy set BUS-Error (set of fbc_rt_safetyerr)" "0,1"
newline
bitfld.long 0x00 1. "DST,Dummy set Time out (set of fbc_rt_overerr)" "0,1"
bitfld.long 0x00 0. "DSF,Dummy set Fail (set of fbc_rt_fail)" "0,1"
tree.end
tree "FUNCTIONAL_SAFETY_INST_1"
base ad:0xE6450000
group.long 0x00++0x03
line.long 0x00 "RTTEX2,SLFR and SLFE bit of the RTTEX are effective only when KCD bit is H'F1"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved" "0,1,2,3"
bitfld.long 0x00 29. "SLFR,Self-Check Counter Reset for field BIST activator" "0: Counter Reset,1: Counter not Reset"
newline
bitfld.long 0x00 28. "SLFE,Execution of Self-Check for Field BIST activator" "0: Not Execution of Self-Check for Field BIST,1: Execution of Self-Check for Field BIST.."
rbitfld.long 0x00 24.--27. "Reserved_24,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.byte 0x00 16.--23. 1. "KCD,Key Code H'5A: Effective execution of Run Time Test H'F1: Effective execution of Self-Check for field BIST activator"
rbitfld.long 0x00 11.--15. "Reserved_11,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "STM,Single Step Test Mode" "?,1: LBIST,2: MBIST,3: SCAN,?..."
bitfld.long 0x00 6.--7. "INTM,Interrupt mask" "0: non mask *1,?,2: Only at the time of the fail(fba_rt_finish are,?..."
newline
bitfld.long 0x00 5. "SSZ,SCAN Pattern size Valid only when STM=011" "0: 32bit mode,1: 16bit mode"
bitfld.long 0x00 4. "TR,Select the value of the timer" "0: ROM,1: register"
newline
bitfld.long 0x00 3. "WM,Wfi mask" "0: not mask,1: mask"
bitfld.long 0x00 2. "TM,Mask the judgment of timer" "0: not mask,1: mask"
newline
bitfld.long 0x00 1. "STP,Single Step Mode" "0: ROM batch mode,1: Single Step Mode"
bitfld.long 0x00 0. "EX,Execution of Runtime Test" "0: Not Execution of Runtime Test,1: Execution of Runtime Test"
group.long 0x04++0x03
line.long 0x00 "RTTMI12,"
rbitfld.long 0x00 27.--31. "Reserved_27,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 24.--26. "RPROT,Protection type of MEMORY" "0: Unprivileged access,1: Privileged access,?..."
newline
hexmask.long.byte 0x00 16.--23. 1. "MADDR_upper,Memory upper address[39:32] that stores the SCAN pattern"
hexmask.long.word 0x00 0.--15. 1. "MUNIT,Number of units (1 unit = 128 Byte)"
group.long 0x08++0x03
line.long 0x00 "RTTMI22,"
hexmask.long 0x00 0.--31. 1. "MADDR,Memory address that stores the SCAN pattern"
group.long 0x0C++0x03
line.long 0x00 "RTTSISR12,"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved"
hexmask.long.tbyte 0x00 0.--19. 1. "SISR1,SISR-TEST#1 Expected value"
group.long 0x14++0x03
line.long 0x00 "RTTUC2,"
hexmask.long 0x00 0.--31. 1. "U_WDT,Upper counter of Watchdog Timer"
group.long 0x18++0x03
line.long 0x00 "RTTDC2,"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved"
hexmask.long.word 0x00 0.--15. 1. "L_WDT,Lower counter of Watchdog Timer"
group.long 0x80++0x03
line.long 0x00 "RTTSET0_2,"
hexmask.long 0x00 0.--31. 1. "test_clock,Test setting input"
group.long 0x84++0x03
line.long 0x00 "RTTSET1_2,"
hexmask.long 0x00 2.--31. 1. "Reserved_2,Reserved"
bitfld.long 0x00 1. "reset,Test setting input" "0: Reset test disabled,1: Reset test enabled"
newline
bitfld.long 0x00 0. "tt,Test setting input" "0: Selected other clock,1: Selected test clock for test Domain"
group.long 0x88++0x03
line.long 0x00 "RTTSET2_2,"
hexmask.long 0x00 0.--31. 1. "hold0,Test setting input"
group.long 0x8C++0x03
line.long 0x00 "RTTSET3_2,"
hexmask.long.tbyte 0x00 8.--31. 1. "hold1,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "hold0,Test setting input"
group.long 0x90++0x03
line.long 0x00 "RTTSET4_2,"
hexmask.long.word 0x00 16.--31. 1. "hold2,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "hold1,Test setting input"
group.long 0x94++0x03
line.long 0x00 "RTTSET5_2,"
hexmask.long.byte 0x00 24.--31. 1. "hold3,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "hold2,Test setting input"
group.long 0x98++0x03
line.long 0x00 "RTTSET6_2,"
hexmask.long 0x00 0.--31. 1. "hold3,Test setting input"
group.long 0x9C++0x03
line.long 0x00 "RTTSET7_2,"
hexmask.long 0x00 0.--31. 1. "toggle0,Test setting input"
group.long 0xA0++0x03
line.long 0x00 "RTTSET8_2,"
hexmask.long.tbyte 0x00 8.--31. 1. "toggle1,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "toggle0,Test setting input"
group.long 0xA4++0x03
line.long 0x00 "RTTSET9_2,"
hexmask.long.word 0x00 16.--31. 1. "toggle2,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "toggle1,Test setting input"
group.long 0xA8++0x03
line.long 0x00 "RTTSET10_2,"
hexmask.long.byte 0x00 24.--31. 1. "toggle3,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "toggle2,Test setting input"
group.long 0xAC++0x03
line.long 0x00 "RTTSET11_2,"
hexmask.long 0x00 0.--31. 1. "toggle3,Test setting input"
group.long 0xB0++0x03
line.long 0x00 "RTTSET12_2,"
hexmask.long 0x00 0.--31. 1. "switching0,Test setting input"
group.long 0xB4++0x03
line.long 0x00 "RTTSET13_2,"
hexmask.long.tbyte 0x00 8.--31. 1. "switching1,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "switching0,Test setting input"
group.long 0xB8++0x03
line.long 0x00 "RTTSET14_2,"
hexmask.long.word 0x00 16.--31. 1. "switching2,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "switching1,Test setting input"
group.long 0xBC++0x03
line.long 0x00 "RTTSET15_2,"
hexmask.long.byte 0x00 24.--31. 1. "switching3,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "switching2,Test setting input"
group.long 0xC0++0x03
line.long 0x00 "RTTSET16_2,"
hexmask.long 0x00 0.--31. 1. "switching3,Test setting input"
group.long 0xC4++0x03
line.long 0x00 "RTTSET17_2,"
hexmask.long 0x00 0.--31. 1. "hold4,Test setting input"
group.long 0xC8++0x03
line.long 0x00 "RTTSET18_2,"
hexmask.long.tbyte 0x00 8.--31. 1. "hold5,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "hold4,Test setting input"
group.long 0xCC++0x03
line.long 0x00 "RTTSET19_2,"
hexmask.long.word 0x00 16.--31. 1. "hold6,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "hold5,Test setting input"
group.long 0xD0++0x03
line.long 0x00 "RTTSET20_2,"
hexmask.long.byte 0x00 24.--31. 1. "hold7,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "hold6,Test setting input"
group.long 0xD4++0x03
line.long 0x00 "RTTSET21_2,"
hexmask.long 0x00 0.--31. 1. "hold7,Test setting input"
group.long 0xD8++0x03
line.long 0x00 "RTTSET22_2,"
hexmask.long 0x00 0.--31. 1. "toggle4,Test setting input"
group.long 0xDC++0x03
line.long 0x00 "RTTSET23_2,"
hexmask.long.tbyte 0x00 8.--31. 1. "toggle5,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "toggle4,Test setting input"
group.long 0xE0++0x03
line.long 0x00 "RTTSET24_2,"
hexmask.long.word 0x00 16.--31. 1. "toggle6,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "toggle5,Test setting input"
group.long 0xE4++0x03
line.long 0x00 "RTTSET25_2,"
hexmask.long.byte 0x00 24.--31. 1. "toggle7,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "toggle6,Test setting input"
group.long 0xE8++0x03
line.long 0x00 "RTTSET26_2,"
hexmask.long 0x00 0.--31. 1. "toggle7,Test setting input"
group.long 0xEC++0x03
line.long 0x00 "RTTSET27_2,"
hexmask.long 0x00 0.--31. 1. "switching4,Test setting input"
group.long 0xF0++0x03
line.long 0x00 "RTTSET28_2,"
hexmask.long.tbyte 0x00 8.--31. 1. "switching5,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "switching4,Test setting input"
group.long 0xF4++0x03
line.long 0x00 "RTTSET29_2,"
hexmask.long.word 0x00 16.--31. 1. "switching6,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "switching5,Test setting input"
group.long 0xF8++0x03
line.long 0x00 "RTTSET30_2,"
hexmask.long.byte 0x00 24.--31. 1. "switching7,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "switching6,Test setting input"
group.long 0xFC++0x03
line.long 0x00 "RTTSET31_2,"
hexmask.long 0x00 0.--31. 1. "switching7,Test setting input"
group.long 0x100++0x03
line.long 0x00 "RTTSET32_2,"
hexmask.long 0x00 0.--31. 1. "clknum_31_0,Test setting input"
group.long 0x104++0x03
line.long 0x00 "RTTSET33_2,"
hexmask.long 0x00 0.--31. 1. "Testmat_31_0,Test setting input"
group.long 0x108++0x03
line.long 0x00 "RTTSET34_2,"
hexmask.long 0x00 0.--31. 1. "Testmat_63_32,Test setting input"
group.long 0x10C++0x03
line.long 0x00 "RTTSET35_2,"
hexmask.long 0x00 0.--31. 1. "Testmat_95_64,Test setting input"
group.long 0x110++0x03
line.long 0x00 "RTTSET36_2,"
hexmask.long 0x00 0.--31. 1. "Testmat_127_96,Test setting input"
group.long 0x114++0x03
line.long 0x00 "RTTSET37_2,"
hexmask.long 0x00 0.--31. 1. "Testmat_159_128,Test setting input"
group.long 0x118++0x03
line.long 0x00 "RTTSET38_2,"
hexmask.long 0x00 0.--31. 1. "Testmat_191_160,Test setting input"
group.long 0x11C++0x03
line.long 0x00 "RTTSET39_2,"
hexmask.long 0x00 0.--31. 1. "Testmat_223_192,Test setting input"
group.long 0x120++0x03
line.long 0x00 "RTTSET40_2,"
hexmask.long 0x00 0.--31. 1. "Testmat_255_224,Test setting input"
group.long 0x124++0x03
line.long 0x00 "RTTSET41_2,"
hexmask.long.word 0x00 18.--31. 1. "Reserved_18,Reserved The bit or field is readable only"
hexmask.long.byte 0x00 10.--17. 1. "apbsel,Test setting input"
newline
bitfld.long 0x00 6.--9. "mbsel,Test setting input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--5. "coreselect,Test setting input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x128++0x03
line.long 0x00 "RTTSET42_2,"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved The bit or field is readable only" "0,1,2,3"
hexmask.long.word 0x00 16.--29. 1. "Y_address,Test setting input"
newline
rbitfld.long 0x00 14.--15. "Reserved_14,Reserved The bit or field is readable only" "0,1,2,3"
hexmask.long.word 0x00 0.--13. 1. "X_address,Test setting input"
group.long 0x12C++0x03
line.long 0x00 "RTTSET43_2,"
rbitfld.long 0x00 31. "Reserved_31,Reserved The bit or field is readable only" "0,1"
hexmask.long.tbyte 0x00 14.--30. 1. "XY,Test setting input"
newline
hexmask.long.word 0x00 0.--13. 1. "Z_address,Test setting input"
group.long 0x130++0x03
line.long 0x00 "RTTSET44_2,"
rbitfld.long 0x00 26.--31. "Reserved_26,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x00 16.--25. 1. "scanchain,Test setting input for hardware-SCAN"
newline
hexmask.long.word 0x00 0.--15. 1. "scanpat,Test setting input for hardware-SCAN"
group.long 0x400++0x03
line.long 0x00 "PSTRSTT2,"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved"
rbitfld.long 0x00 12. "R_rst_T,BIST Redundant result" "0: pass,1: fail"
newline
rbitfld.long 0x00 11. "Reserved_11,Reserved" "0,1"
rbitfld.long 0x00 8.--10. "error_T,BIST error" "0: Pass,1: Fail,2: TimeOut,?,4: BUS error,?..."
newline
rbitfld.long 0x00 4.--7. "testnum_T,Number of tests" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 2.--3. "status_R,BIST Redundant status (Safety function)" "0: unexec,1: wait,2: exec,3: finish"
newline
rbitfld.long 0x00 0.--1. "status_T,BIST status" "0: unexec,1: wait,2: exec,3: finish"
group.long 0x440++0x03
line.long 0x00 "PSTCNT2,"
hexmask.long 0x00 0.--31. 1. "Stop,FieldBIST internal WDT (high counter) stop value"
group.long 0x444++0x03
line.long 0x00 "RTTRSTT2,When status_T in the RTTRSTT register is"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved" "0,1,2,3"
rbitfld.long 0x00 29. "IL_flag2,Runtime Test Illegal suspension flag-2" "0,1"
newline
rbitfld.long 0x00 28. "IL_flag1,Runtime Test Illegal suspension flag-1" "0,1"
rbitfld.long 0x00 27. "CONDF,Debug monitor of FieldBIST condition" "0: not response,1: responded"
newline
rbitfld.long 0x00 24.--26. "BUS_cond,Debug code of BUS condition" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 13.--23. 1. "Reserved_13,Reserved"
newline
rbitfld.long 0x00 12. "R_rst_T,BIST Redundant result (Safety function)" "0: Pass,1: Fail"
rbitfld.long 0x00 11. "Achk,Debug code of address check" "0: normal,1: warning"
newline
rbitfld.long 0x00 8.--10. "error_T,BIST error" "0: Pass,1: Fail,2: TimeOut,?,4: BUS error,?..."
rbitfld.long 0x00 4.--7. "testnum_T,Number of tests" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 2.--3. "R_status_T,BIST redundant status" "0: unexec,1: wait,2: exec,3: finish"
rbitfld.long 0x00 0.--1. "status_T,BIST status" "0: unexec,1: wait,2: exec,3: finish"
group.long 0x458++0x03
line.long 0x00 "RTTCNT2,"
hexmask.long 0x00 0.--31. 1. "Stop,WDT (high counter) stop value"
group.long 0x4A0++0x03
line.long 0x00 "SLFRVS2,"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved"
hexmask.long.tbyte 0x00 0.--19. 1. "REVERS,Expected value reverse for Self-Check SISR"
group.long 0x4A4++0x03
line.long 0x00 "SLFRST2,In case of the SLFR bits of the RTTRSTT register is 1B'1 SCNT bit returns to 1"
rbitfld.long 0x00 26.--31. "SCNT,Self-Check counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 24.--25. "STS,Self-Check status" "0: unexec,1: exec,?,3: finish"
newline
hexmask.long.tbyte 0x00 1.--23. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "STR,Self -Check Result" "0: Pass,1: Fail"
group.long 0x4C0++0x03
line.long 0x00 "ERRSET2,"
hexmask.long 0x00 3.--31. 1. "Reserved_3,Reserved"
bitfld.long 0x00 2. "DSB,Dummy set BUS-Error (set of fbc_rt_safetyerr)" "0,1"
newline
bitfld.long 0x00 1. "DST,Dummy set Time out (set of fbc_rt_overerr)" "0,1"
bitfld.long 0x00 0. "DSF,Dummy set Fail (set of fbc_rt_fail)" "0,1"
tree.end
tree "FUNCTIONAL_SAFETY_INST_2"
base ad:0xE67A0000
group.long 0x00++0x03
line.long 0x00 "RTTEX3,SLFR and SLFE bit of the RTTEX are effective only when KCD bit is H'F1"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved" "0,1,2,3"
bitfld.long 0x00 29. "SLFR,Self-Check Counter Reset for field BIST activator" "0: Counter Reset,1: Counter not Reset"
newline
bitfld.long 0x00 28. "SLFE,Execution of Self-Check for Field BIST activator" "0: Not Execution of Self-Check for Field BIST,1: Execution of Self-Check for Field BIST.."
rbitfld.long 0x00 24.--27. "Reserved_24,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.byte 0x00 16.--23. 1. "KCD,Key Code H'5A: Effective execution of Run Time Test H'F1: Effective execution of Self-Check for field BIST activator"
rbitfld.long 0x00 11.--15. "Reserved_11,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "STM,Single Step Test Mode" "?,1: LBIST,2: MBIST,3: SCAN,?..."
bitfld.long 0x00 6.--7. "INTM,Interrupt mask" "0: non mask *1,?,2: Only at the time of the fail(fba_rt_finish are,?..."
newline
bitfld.long 0x00 5. "SSZ,SCAN Pattern size Valid only when STM=011" "0: 32bit mode,1: 16bit mode"
bitfld.long 0x00 4. "TR,Select the value of the timer" "0: ROM,1: register"
newline
bitfld.long 0x00 3. "WM,Wfi mask" "0: not mask,1: mask"
bitfld.long 0x00 2. "TM,Mask the judgment of timer" "0: not mask,1: mask"
newline
bitfld.long 0x00 1. "STP,Single Step Mode" "0: ROM batch mode,1: Single Step Mode"
bitfld.long 0x00 0. "EX,Execution of Runtime Test" "0: Not Execution of Runtime Test,1: Execution of Runtime Test"
group.long 0x04++0x03
line.long 0x00 "RTTMI13,"
rbitfld.long 0x00 27.--31. "Reserved_27,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 24.--26. "RPROT,Protection type of MEMORY" "0: Unprivileged access,1: Privileged access,?..."
newline
hexmask.long.byte 0x00 16.--23. 1. "MADDR_upper,Memory upper address[39:32] that stores the SCAN pattern"
hexmask.long.word 0x00 0.--15. 1. "MUNIT,Number of units (1 unit = 128 Byte)"
group.long 0x08++0x03
line.long 0x00 "RTTMI23,"
hexmask.long 0x00 0.--31. 1. "MADDR,Memory address that stores the SCAN pattern"
group.long 0x0C++0x03
line.long 0x00 "RTTSISR13,"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved"
hexmask.long.tbyte 0x00 0.--19. 1. "SISR1,SISR-TEST#1 Expected value"
group.long 0x14++0x03
line.long 0x00 "RTTUC3,"
hexmask.long 0x00 0.--31. 1. "U_WDT,Upper counter of Watchdog Timer"
group.long 0x18++0x03
line.long 0x00 "RTTDC3,"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved"
hexmask.long.word 0x00 0.--15. 1. "L_WDT,Lower counter of Watchdog Timer"
group.long 0x80++0x03
line.long 0x00 "RTTSET0_3,"
hexmask.long 0x00 0.--31. 1. "test_clock,Test setting input"
group.long 0x84++0x03
line.long 0x00 "RTTSET1_3,"
hexmask.long 0x00 2.--31. 1. "Reserved_2,Reserved"
bitfld.long 0x00 1. "reset,Test setting input" "0: Reset test disabled,1: Reset test enabled"
newline
bitfld.long 0x00 0. "tt,Test setting input" "0: Selected other clock,1: Selected test clock for test Domain"
group.long 0x88++0x03
line.long 0x00 "RTTSET2_3,"
hexmask.long 0x00 0.--31. 1. "hold0,Test setting input"
group.long 0x8C++0x03
line.long 0x00 "RTTSET3_3,"
hexmask.long.tbyte 0x00 8.--31. 1. "hold1,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "hold0,Test setting input"
group.long 0x90++0x03
line.long 0x00 "RTTSET4_3,"
hexmask.long.word 0x00 16.--31. 1. "hold2,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "hold1,Test setting input"
group.long 0x94++0x03
line.long 0x00 "RTTSET5_3,"
hexmask.long.byte 0x00 24.--31. 1. "hold3,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "hold2,Test setting input"
group.long 0x98++0x03
line.long 0x00 "RTTSET6_3,"
hexmask.long 0x00 0.--31. 1. "hold3,Test setting input"
group.long 0x9C++0x03
line.long 0x00 "RTTSET7_3,"
hexmask.long 0x00 0.--31. 1. "toggle0,Test setting input"
group.long 0xA0++0x03
line.long 0x00 "RTTSET8_3,"
hexmask.long.tbyte 0x00 8.--31. 1. "toggle1,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "toggle0,Test setting input"
group.long 0xA4++0x03
line.long 0x00 "RTTSET9_3,"
hexmask.long.word 0x00 16.--31. 1. "toggle2,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "toggle1,Test setting input"
group.long 0xA8++0x03
line.long 0x00 "RTTSET10_3,"
hexmask.long.byte 0x00 24.--31. 1. "toggle3,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "toggle2,Test setting input"
group.long 0xAC++0x03
line.long 0x00 "RTTSET11_3,"
hexmask.long 0x00 0.--31. 1. "toggle3,Test setting input"
group.long 0xB0++0x03
line.long 0x00 "RTTSET12_3,"
hexmask.long 0x00 0.--31. 1. "switching0,Test setting input"
group.long 0xB4++0x03
line.long 0x00 "RTTSET13_3,"
hexmask.long.tbyte 0x00 8.--31. 1. "switching1,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "switching0,Test setting input"
group.long 0xB8++0x03
line.long 0x00 "RTTSET14_3,"
hexmask.long.word 0x00 16.--31. 1. "switching2,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "switching1,Test setting input"
group.long 0xBC++0x03
line.long 0x00 "RTTSET15_3,"
hexmask.long.byte 0x00 24.--31. 1. "switching3,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "switching2,Test setting input"
group.long 0xC0++0x03
line.long 0x00 "RTTSET16_3,"
hexmask.long 0x00 0.--31. 1. "switching3,Test setting input"
group.long 0xC4++0x03
line.long 0x00 "RTTSET17_3,"
hexmask.long 0x00 0.--31. 1. "hold4,Test setting input"
group.long 0xC8++0x03
line.long 0x00 "RTTSET18_3,"
hexmask.long.tbyte 0x00 8.--31. 1. "hold5,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "hold4,Test setting input"
group.long 0xCC++0x03
line.long 0x00 "RTTSET19_3,"
hexmask.long.word 0x00 16.--31. 1. "hold6,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "hold5,Test setting input"
group.long 0xD0++0x03
line.long 0x00 "RTTSET20_3,"
hexmask.long.byte 0x00 24.--31. 1. "hold7,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "hold6,Test setting input"
group.long 0xD4++0x03
line.long 0x00 "RTTSET21_3,"
hexmask.long 0x00 0.--31. 1. "hold7,Test setting input"
group.long 0xD8++0x03
line.long 0x00 "RTTSET22_3,"
hexmask.long 0x00 0.--31. 1. "toggle4,Test setting input"
group.long 0xDC++0x03
line.long 0x00 "RTTSET23_3,"
hexmask.long.tbyte 0x00 8.--31. 1. "toggle5,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "toggle4,Test setting input"
group.long 0xE0++0x03
line.long 0x00 "RTTSET24_3,"
hexmask.long.word 0x00 16.--31. 1. "toggle6,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "toggle5,Test setting input"
group.long 0xE4++0x03
line.long 0x00 "RTTSET25_3,"
hexmask.long.byte 0x00 24.--31. 1. "toggle7,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "toggle6,Test setting input"
group.long 0xE8++0x03
line.long 0x00 "RTTSET26_3,"
hexmask.long 0x00 0.--31. 1. "toggle7,Test setting input"
group.long 0xEC++0x03
line.long 0x00 "RTTSET27_3,"
hexmask.long 0x00 0.--31. 1. "switching4,Test setting input"
group.long 0xF0++0x03
line.long 0x00 "RTTSET28_3,"
hexmask.long.tbyte 0x00 8.--31. 1. "switching5,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "switching4,Test setting input"
group.long 0xF4++0x03
line.long 0x00 "RTTSET29_3,"
hexmask.long.word 0x00 16.--31. 1. "switching6,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "switching5,Test setting input"
group.long 0xF8++0x03
line.long 0x00 "RTTSET30_3,"
hexmask.long.byte 0x00 24.--31. 1. "switching7,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "switching6,Test setting input"
group.long 0xFC++0x03
line.long 0x00 "RTTSET31_3,"
hexmask.long 0x00 0.--31. 1. "switching7,Test setting input"
group.long 0x100++0x03
line.long 0x00 "RTTSET32_3,"
hexmask.long 0x00 0.--31. 1. "clknum_31_0,Test setting input"
group.long 0x104++0x03
line.long 0x00 "RTTSET33_3,"
hexmask.long 0x00 0.--31. 1. "Testmat_31_0,Test setting input"
group.long 0x108++0x03
line.long 0x00 "RTTSET34_3,"
hexmask.long 0x00 0.--31. 1. "Testmat_63_32,Test setting input"
group.long 0x10C++0x03
line.long 0x00 "RTTSET35_3,"
hexmask.long 0x00 0.--31. 1. "Testmat_95_64,Test setting input"
group.long 0x110++0x03
line.long 0x00 "RTTSET36_3,"
hexmask.long 0x00 0.--31. 1. "Testmat_127_96,Test setting input"
group.long 0x114++0x03
line.long 0x00 "RTTSET37_3,"
hexmask.long 0x00 0.--31. 1. "Testmat_159_128,Test setting input"
group.long 0x118++0x03
line.long 0x00 "RTTSET38_3,"
hexmask.long 0x00 0.--31. 1. "Testmat_191_160,Test setting input"
group.long 0x11C++0x03
line.long 0x00 "RTTSET39_3,"
hexmask.long 0x00 0.--31. 1. "Testmat_223_192,Test setting input"
group.long 0x120++0x03
line.long 0x00 "RTTSET40_3,"
hexmask.long 0x00 0.--31. 1. "Testmat_255_224,Test setting input"
group.long 0x124++0x03
line.long 0x00 "RTTSET41_3,"
hexmask.long.word 0x00 18.--31. 1. "Reserved_18,Reserved The bit or field is readable only"
hexmask.long.byte 0x00 10.--17. 1. "apbsel,Test setting input"
newline
bitfld.long 0x00 6.--9. "mbsel,Test setting input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--5. "coreselect,Test setting input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x128++0x03
line.long 0x00 "RTTSET42_3,"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved The bit or field is readable only" "0,1,2,3"
hexmask.long.word 0x00 16.--29. 1. "Y_address,Test setting input"
newline
rbitfld.long 0x00 14.--15. "Reserved_14,Reserved The bit or field is readable only" "0,1,2,3"
hexmask.long.word 0x00 0.--13. 1. "X_address,Test setting input"
group.long 0x12C++0x03
line.long 0x00 "RTTSET43_3,"
rbitfld.long 0x00 31. "Reserved_31,Reserved The bit or field is readable only" "0,1"
hexmask.long.tbyte 0x00 14.--30. 1. "XY,Test setting input"
newline
hexmask.long.word 0x00 0.--13. 1. "Z_address,Test setting input"
group.long 0x130++0x03
line.long 0x00 "RTTSET44_3,"
rbitfld.long 0x00 26.--31. "Reserved_26,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x00 16.--25. 1. "scanchain,Test setting input for hardware-SCAN"
newline
hexmask.long.word 0x00 0.--15. 1. "scanpat,Test setting input for hardware-SCAN"
group.long 0x400++0x03
line.long 0x00 "PSTRSTT3,"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved"
rbitfld.long 0x00 12. "R_rst_T,BIST Redundant result" "0: pass,1: fail"
newline
rbitfld.long 0x00 11. "Reserved_11,Reserved" "0,1"
rbitfld.long 0x00 8.--10. "error_T,BIST error" "0: Pass,1: Fail,2: TimeOut,?,4: BUS error,?..."
newline
rbitfld.long 0x00 4.--7. "testnum_T,Number of tests" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 2.--3. "status_R,BIST Redundant status (Safety function)" "0: unexec,1: wait,2: exec,3: finish"
newline
rbitfld.long 0x00 0.--1. "status_T,BIST status" "0: unexec,1: wait,2: exec,3: finish"
group.long 0x440++0x03
line.long 0x00 "PSTCNT3,"
hexmask.long 0x00 0.--31. 1. "Stop,FieldBIST internal WDT (high counter) stop value"
group.long 0x444++0x03
line.long 0x00 "RTTRSTT3,When status_T in the RTTRSTT register is"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved" "0,1,2,3"
rbitfld.long 0x00 29. "IL_flag2,Runtime Test Illegal suspension flag-2" "0,1"
newline
rbitfld.long 0x00 28. "IL_flag1,Runtime Test Illegal suspension flag-1" "0,1"
rbitfld.long 0x00 27. "CONDF,Debug monitor of FieldBIST condition" "0: not response,1: responded"
newline
rbitfld.long 0x00 24.--26. "BUS_cond,Debug code of BUS condition" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 13.--23. 1. "Reserved_13,Reserved"
newline
rbitfld.long 0x00 12. "R_rst_T,BIST Redundant result (Safety function)" "0: Pass,1: Fail"
rbitfld.long 0x00 11. "Achk,Debug code of address check" "0: normal,1: warning"
newline
rbitfld.long 0x00 8.--10. "error_T,BIST error" "0: Pass,1: Fail,2: TimeOut,?,4: BUS error,?..."
rbitfld.long 0x00 4.--7. "testnum_T,Number of tests" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 2.--3. "R_status_T,BIST redundant status" "0: unexec,1: wait,2: exec,3: finish"
rbitfld.long 0x00 0.--1. "status_T,BIST status" "0: unexec,1: wait,2: exec,3: finish"
group.long 0x458++0x03
line.long 0x00 "RTTCNT3,"
hexmask.long 0x00 0.--31. 1. "Stop,WDT (high counter) stop value"
group.long 0x4A0++0x03
line.long 0x00 "SLFRVS3,"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved"
hexmask.long.tbyte 0x00 0.--19. 1. "REVERS,Expected value reverse for Self-Check SISR"
group.long 0x4A4++0x03
line.long 0x00 "SLFRST3,In case of the SLFR bits of the RTTRSTT register is 1B'1 SCNT bit returns to 1"
rbitfld.long 0x00 26.--31. "SCNT,Self-Check counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 24.--25. "STS,Self-Check status" "0: unexec,1: exec,?,3: finish"
newline
hexmask.long.tbyte 0x00 1.--23. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "STR,Self -Check Result" "0: Pass,1: Fail"
group.long 0x4C0++0x03
line.long 0x00 "ERRSET3,"
hexmask.long 0x00 3.--31. 1. "Reserved_3,Reserved"
bitfld.long 0x00 2. "DSB,Dummy set BUS-Error (set of fbc_rt_safetyerr)" "0,1"
newline
bitfld.long 0x00 1. "DST,Dummy set Time out (set of fbc_rt_overerr)" "0,1"
bitfld.long 0x00 0. "DSF,Dummy set Fail (set of fbc_rt_fail)" "0,1"
tree.end
tree "FUNCTIONAL_SAFETY_INST_3"
base ad:0xE6680000
group.long 0x00++0x03
line.long 0x00 "RTTEX4,SLFR and SLFE bit of the RTTEX are effective only when KCD bit is H'F1"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved" "0,1,2,3"
bitfld.long 0x00 29. "SLFR,Self-Check Counter Reset for field BIST activator" "0: Counter Reset,1: Counter not Reset"
newline
bitfld.long 0x00 28. "SLFE,Execution of Self-Check for Field BIST activator" "0: Not Execution of Self-Check for Field BIST,1: Execution of Self-Check for Field BIST.."
rbitfld.long 0x00 24.--27. "Reserved_24,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.byte 0x00 16.--23. 1. "KCD,Key Code H'5A: Effective execution of Run Time Test H'F1: Effective execution of Self-Check for field BIST activator"
rbitfld.long 0x00 11.--15. "Reserved_11,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "STM,Single Step Test Mode" "?,1: LBIST,2: MBIST,3: SCAN,?..."
bitfld.long 0x00 6.--7. "INTM,Interrupt mask" "0: non mask *1,?,2: Only at the time of the fail(fba_rt_finish are,?..."
newline
bitfld.long 0x00 5. "SSZ,SCAN Pattern size Valid only when STM=011" "0: 32bit mode,1: 16bit mode"
bitfld.long 0x00 4. "TR,Select the value of the timer" "0: ROM,1: register"
newline
bitfld.long 0x00 3. "WM,Wfi mask" "0: not mask,1: mask"
bitfld.long 0x00 2. "TM,Mask the judgment of timer" "0: not mask,1: mask"
newline
bitfld.long 0x00 1. "STP,Single Step Mode" "0: ROM batch mode,1: Single Step Mode"
bitfld.long 0x00 0. "EX,Execution of Runtime Test" "0: Not Execution of Runtime Test,1: Execution of Runtime Test"
group.long 0x04++0x03
line.long 0x00 "RTTMI14,"
rbitfld.long 0x00 27.--31. "Reserved_27,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 24.--26. "RPROT,Protection type of MEMORY" "0: Unprivileged access,1: Privileged access,?..."
newline
hexmask.long.byte 0x00 16.--23. 1. "MADDR_upper,Memory upper address[39:32] that stores the SCAN pattern"
hexmask.long.word 0x00 0.--15. 1. "MUNIT,Number of units (1 unit = 128 Byte)"
group.long 0x08++0x03
line.long 0x00 "RTTMI24,"
hexmask.long 0x00 0.--31. 1. "MADDR,Memory address that stores the SCAN pattern"
group.long 0x0C++0x03
line.long 0x00 "RTTSISR14,"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved"
hexmask.long.tbyte 0x00 0.--19. 1. "SISR1,SISR-TEST#1 Expected value"
group.long 0x14++0x03
line.long 0x00 "RTTUC4,"
hexmask.long 0x00 0.--31. 1. "U_WDT,Upper counter of Watchdog Timer"
group.long 0x18++0x03
line.long 0x00 "RTTDC4,"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved"
hexmask.long.word 0x00 0.--15. 1. "L_WDT,Lower counter of Watchdog Timer"
group.long 0x80++0x03
line.long 0x00 "RTTSET0_4,"
hexmask.long 0x00 0.--31. 1. "test_clock,Test setting input"
group.long 0x84++0x03
line.long 0x00 "RTTSET1_4,"
hexmask.long 0x00 2.--31. 1. "Reserved_2,Reserved"
bitfld.long 0x00 1. "reset,Test setting input" "0: Reset test disabled,1: Reset test enabled"
newline
bitfld.long 0x00 0. "tt,Test setting input" "0: Selected other clock,1: Selected test clock for test Domain"
group.long 0x88++0x03
line.long 0x00 "RTTSET2_4,"
hexmask.long 0x00 0.--31. 1. "hold0,Test setting input"
group.long 0x8C++0x03
line.long 0x00 "RTTSET3_4,"
hexmask.long.tbyte 0x00 8.--31. 1. "hold1,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "hold0,Test setting input"
group.long 0x90++0x03
line.long 0x00 "RTTSET4_4,"
hexmask.long.word 0x00 16.--31. 1. "hold2,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "hold1,Test setting input"
group.long 0x94++0x03
line.long 0x00 "RTTSET5_4,"
hexmask.long.byte 0x00 24.--31. 1. "hold3,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "hold2,Test setting input"
group.long 0x98++0x03
line.long 0x00 "RTTSET6_4,"
hexmask.long 0x00 0.--31. 1. "hold3,Test setting input"
group.long 0x9C++0x03
line.long 0x00 "RTTSET7_4,"
hexmask.long 0x00 0.--31. 1. "toggle0,Test setting input"
group.long 0xA0++0x03
line.long 0x00 "RTTSET8_4,"
hexmask.long.tbyte 0x00 8.--31. 1. "toggle1,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "toggle0,Test setting input"
group.long 0xA4++0x03
line.long 0x00 "RTTSET9_4,"
hexmask.long.word 0x00 16.--31. 1. "toggle2,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "toggle1,Test setting input"
group.long 0xA8++0x03
line.long 0x00 "RTTSET10_4,"
hexmask.long.byte 0x00 24.--31. 1. "toggle3,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "toggle2,Test setting input"
group.long 0xAC++0x03
line.long 0x00 "RTTSET11_4,"
hexmask.long 0x00 0.--31. 1. "toggle3,Test setting input"
group.long 0xB0++0x03
line.long 0x00 "RTTSET12_4,"
hexmask.long 0x00 0.--31. 1. "switching0,Test setting input"
group.long 0xB4++0x03
line.long 0x00 "RTTSET13_4,"
hexmask.long.tbyte 0x00 8.--31. 1. "switching1,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "switching0,Test setting input"
group.long 0xB8++0x03
line.long 0x00 "RTTSET14_4,"
hexmask.long.word 0x00 16.--31. 1. "switching2,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "switching1,Test setting input"
group.long 0xBC++0x03
line.long 0x00 "RTTSET15_4,"
hexmask.long.byte 0x00 24.--31. 1. "switching3,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "switching2,Test setting input"
group.long 0xC0++0x03
line.long 0x00 "RTTSET16_4,"
hexmask.long 0x00 0.--31. 1. "switching3,Test setting input"
group.long 0xC4++0x03
line.long 0x00 "RTTSET17_4,"
hexmask.long 0x00 0.--31. 1. "hold4,Test setting input"
group.long 0xC8++0x03
line.long 0x00 "RTTSET18_4,"
hexmask.long.tbyte 0x00 8.--31. 1. "hold5,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "hold4,Test setting input"
group.long 0xCC++0x03
line.long 0x00 "RTTSET19_4,"
hexmask.long.word 0x00 16.--31. 1. "hold6,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "hold5,Test setting input"
group.long 0xD0++0x03
line.long 0x00 "RTTSET20_4,"
hexmask.long.byte 0x00 24.--31. 1. "hold7,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "hold6,Test setting input"
group.long 0xD4++0x03
line.long 0x00 "RTTSET21_4,"
hexmask.long 0x00 0.--31. 1. "hold7,Test setting input"
group.long 0xD8++0x03
line.long 0x00 "RTTSET22_4,"
hexmask.long 0x00 0.--31. 1. "toggle4,Test setting input"
group.long 0xDC++0x03
line.long 0x00 "RTTSET23_4,"
hexmask.long.tbyte 0x00 8.--31. 1. "toggle5,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "toggle4,Test setting input"
group.long 0xE0++0x03
line.long 0x00 "RTTSET24_4,"
hexmask.long.word 0x00 16.--31. 1. "toggle6,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "toggle5,Test setting input"
group.long 0xE4++0x03
line.long 0x00 "RTTSET25_4,"
hexmask.long.byte 0x00 24.--31. 1. "toggle7,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "toggle6,Test setting input"
group.long 0xE8++0x03
line.long 0x00 "RTTSET26_4,"
hexmask.long 0x00 0.--31. 1. "toggle7,Test setting input"
group.long 0xEC++0x03
line.long 0x00 "RTTSET27_4,"
hexmask.long 0x00 0.--31. 1. "switching4,Test setting input"
group.long 0xF0++0x03
line.long 0x00 "RTTSET28_4,"
hexmask.long.tbyte 0x00 8.--31. 1. "switching5,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "switching4,Test setting input"
group.long 0xF4++0x03
line.long 0x00 "RTTSET29_4,"
hexmask.long.word 0x00 16.--31. 1. "switching6,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "switching5,Test setting input"
group.long 0xF8++0x03
line.long 0x00 "RTTSET30_4,"
hexmask.long.byte 0x00 24.--31. 1. "switching7,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "switching6,Test setting input"
group.long 0xFC++0x03
line.long 0x00 "RTTSET31_4,"
hexmask.long 0x00 0.--31. 1. "switching7,Test setting input"
group.long 0x100++0x03
line.long 0x00 "RTTSET32_4,"
hexmask.long 0x00 0.--31. 1. "clknum_31_0,Test setting input"
group.long 0x104++0x03
line.long 0x00 "RTTSET33_4,"
hexmask.long 0x00 0.--31. 1. "Testmat_31_0,Test setting input"
group.long 0x108++0x03
line.long 0x00 "RTTSET34_4,"
hexmask.long 0x00 0.--31. 1. "Testmat_63_32,Test setting input"
group.long 0x10C++0x03
line.long 0x00 "RTTSET35_4,"
hexmask.long 0x00 0.--31. 1. "Testmat_95_64,Test setting input"
group.long 0x110++0x03
line.long 0x00 "RTTSET36_4,"
hexmask.long 0x00 0.--31. 1. "Testmat_127_96,Test setting input"
group.long 0x114++0x03
line.long 0x00 "RTTSET37_4,"
hexmask.long 0x00 0.--31. 1. "Testmat_159_128,Test setting input"
group.long 0x118++0x03
line.long 0x00 "RTTSET38_4,"
hexmask.long 0x00 0.--31. 1. "Testmat_191_160,Test setting input"
group.long 0x11C++0x03
line.long 0x00 "RTTSET39_4,"
hexmask.long 0x00 0.--31. 1. "Testmat_223_192,Test setting input"
group.long 0x120++0x03
line.long 0x00 "RTTSET40_4,"
hexmask.long 0x00 0.--31. 1. "Testmat_255_224,Test setting input"
group.long 0x124++0x03
line.long 0x00 "RTTSET41_4,"
hexmask.long.word 0x00 18.--31. 1. "Reserved_18,Reserved The bit or field is readable only"
hexmask.long.byte 0x00 10.--17. 1. "apbsel,Test setting input"
newline
bitfld.long 0x00 6.--9. "mbsel,Test setting input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--5. "coreselect,Test setting input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x128++0x03
line.long 0x00 "RTTSET42_4,"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved The bit or field is readable only" "0,1,2,3"
hexmask.long.word 0x00 16.--29. 1. "Y_address,Test setting input"
newline
rbitfld.long 0x00 14.--15. "Reserved_14,Reserved The bit or field is readable only" "0,1,2,3"
hexmask.long.word 0x00 0.--13. 1. "X_address,Test setting input"
group.long 0x12C++0x03
line.long 0x00 "RTTSET43_4,"
rbitfld.long 0x00 31. "Reserved_31,Reserved The bit or field is readable only" "0,1"
hexmask.long.tbyte 0x00 14.--30. 1. "XY,Test setting input"
newline
hexmask.long.word 0x00 0.--13. 1. "Z_address,Test setting input"
group.long 0x130++0x03
line.long 0x00 "RTTSET44_4,"
rbitfld.long 0x00 26.--31. "Reserved_26,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x00 16.--25. 1. "scanchain,Test setting input for hardware-SCAN"
newline
hexmask.long.word 0x00 0.--15. 1. "scanpat,Test setting input for hardware-SCAN"
group.long 0x400++0x03
line.long 0x00 "PSTRSTT4,"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved"
rbitfld.long 0x00 12. "R_rst_T,BIST Redundant result" "0: pass,1: fail"
newline
rbitfld.long 0x00 11. "Reserved_11,Reserved" "0,1"
rbitfld.long 0x00 8.--10. "error_T,BIST error" "0: Pass,1: Fail,2: TimeOut,?,4: BUS error,?..."
newline
rbitfld.long 0x00 4.--7. "testnum_T,Number of tests" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 2.--3. "status_R,BIST Redundant status (Safety function)" "0: unexec,1: wait,2: exec,3: finish"
newline
rbitfld.long 0x00 0.--1. "status_T,BIST status" "0: unexec,1: wait,2: exec,3: finish"
group.long 0x440++0x03
line.long 0x00 "PSTCNT4,"
hexmask.long 0x00 0.--31. 1. "Stop,FieldBIST internal WDT (high counter) stop value"
group.long 0x444++0x03
line.long 0x00 "RTTRSTT4,When status_T in the RTTRSTT register is"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved" "0,1,2,3"
rbitfld.long 0x00 29. "IL_flag2,Runtime Test Illegal suspension flag-2" "0,1"
newline
rbitfld.long 0x00 28. "IL_flag1,Runtime Test Illegal suspension flag-1" "0,1"
rbitfld.long 0x00 27. "CONDF,Debug monitor of FieldBIST condition" "0: not response,1: responded"
newline
rbitfld.long 0x00 24.--26. "BUS_cond,Debug code of BUS condition" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 13.--23. 1. "Reserved_13,Reserved"
newline
rbitfld.long 0x00 12. "R_rst_T,BIST Redundant result (Safety function)" "0: Pass,1: Fail"
rbitfld.long 0x00 11. "Achk,Debug code of address check" "0: normal,1: warning"
newline
rbitfld.long 0x00 8.--10. "error_T,BIST error" "0: Pass,1: Fail,2: TimeOut,?,4: BUS error,?..."
rbitfld.long 0x00 4.--7. "testnum_T,Number of tests" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 2.--3. "R_status_T,BIST redundant status" "0: unexec,1: wait,2: exec,3: finish"
rbitfld.long 0x00 0.--1. "status_T,BIST status" "0: unexec,1: wait,2: exec,3: finish"
group.long 0x458++0x03
line.long 0x00 "RTTCNT4,"
hexmask.long 0x00 0.--31. 1. "Stop,WDT (high counter) stop value"
group.long 0x4A0++0x03
line.long 0x00 "SLFRVS4,"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved"
hexmask.long.tbyte 0x00 0.--19. 1. "REVERS,Expected value reverse for Self-Check SISR"
group.long 0x4A4++0x03
line.long 0x00 "SLFRST4,In case of the SLFR bits of the RTTRSTT register is 1B'1 SCNT bit returns to 1"
rbitfld.long 0x00 26.--31. "SCNT,Self-Check counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 24.--25. "STS,Self-Check status" "0: unexec,1: exec,?,3: finish"
newline
hexmask.long.tbyte 0x00 1.--23. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "STR,Self -Check Result" "0: Pass,1: Fail"
group.long 0x4C0++0x03
line.long 0x00 "ERRSET4,"
hexmask.long 0x00 3.--31. 1. "Reserved_3,Reserved"
bitfld.long 0x00 2. "DSB,Dummy set BUS-Error (set of fbc_rt_safetyerr)" "0,1"
newline
bitfld.long 0x00 1. "DST,Dummy set Time out (set of fbc_rt_overerr)" "0,1"
bitfld.long 0x00 0. "DSF,Dummy set Fail (set of fbc_rt_fail)" "0,1"
tree.end
tree "FUNCTIONAL_SAFETY_INST_4"
base ad:0xFFFE0000
group.long 0x00++0x03
line.long 0x00 "RTTEX5,SLFR and SLFE bit of the RTTEX are effective only when KCD bit is H'F1"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved" "0,1,2,3"
bitfld.long 0x00 29. "SLFR,Self-Check Counter Reset for field BIST activator" "0: Counter Reset,1: Counter not Reset"
newline
bitfld.long 0x00 28. "SLFE,Execution of Self-Check for Field BIST activator" "0: Not Execution of Self-Check for Field BIST,1: Execution of Self-Check for Field BIST.."
rbitfld.long 0x00 24.--27. "Reserved_24,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.byte 0x00 16.--23. 1. "KCD,Key Code H'5A: Effective execution of Run Time Test H'F1: Effective execution of Self-Check for field BIST activator"
rbitfld.long 0x00 11.--15. "Reserved_11,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "STM,Single Step Test Mode" "?,1: LBIST,2: MBIST,3: SCAN,?..."
bitfld.long 0x00 6.--7. "INTM,Interrupt mask" "0: non mask *1,?,2: Only at the time of the fail(fba_rt_finish are,?..."
newline
bitfld.long 0x00 5. "SSZ,SCAN Pattern size Valid only when STM=011" "0: 32bit mode,1: 16bit mode"
bitfld.long 0x00 4. "TR,Select the value of the timer" "0: ROM,1: register"
newline
bitfld.long 0x00 3. "WM,Wfi mask" "0: not mask,1: mask"
bitfld.long 0x00 2. "TM,Mask the judgment of timer" "0: not mask,1: mask"
newline
bitfld.long 0x00 1. "STP,Single Step Mode" "0: ROM batch mode,1: Single Step Mode"
bitfld.long 0x00 0. "EX,Execution of Runtime Test" "0: Not Execution of Runtime Test,1: Execution of Runtime Test"
group.long 0x04++0x03
line.long 0x00 "RTTMI15,"
rbitfld.long 0x00 27.--31. "Reserved_27,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 24.--26. "RPROT,Protection type of MEMORY" "0: Unprivileged access,1: Privileged access,?..."
newline
hexmask.long.byte 0x00 16.--23. 1. "MADDR_upper,Memory upper address[39:32] that stores the SCAN pattern"
hexmask.long.word 0x00 0.--15. 1. "MUNIT,Number of units (1 unit = 128 Byte)"
group.long 0x08++0x03
line.long 0x00 "RTTMI25,"
hexmask.long 0x00 0.--31. 1. "MADDR,Memory address that stores the SCAN pattern"
group.long 0x0C++0x03
line.long 0x00 "RTTSISR15,"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved"
hexmask.long.tbyte 0x00 0.--19. 1. "SISR1,SISR-TEST#1 Expected value"
group.long 0x14++0x03
line.long 0x00 "RTTUC5,"
hexmask.long 0x00 0.--31. 1. "U_WDT,Upper counter of Watchdog Timer"
group.long 0x18++0x03
line.long 0x00 "RTTDC5,"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved"
hexmask.long.word 0x00 0.--15. 1. "L_WDT,Lower counter of Watchdog Timer"
group.long 0x80++0x03
line.long 0x00 "RTTSET0_5,"
hexmask.long 0x00 0.--31. 1. "test_clock,Test setting input"
group.long 0x84++0x03
line.long 0x00 "RTTSET1_5,"
hexmask.long 0x00 2.--31. 1. "Reserved_2,Reserved"
bitfld.long 0x00 1. "reset,Test setting input" "0: Reset test disabled,1: Reset test enabled"
newline
bitfld.long 0x00 0. "tt,Test setting input" "0: Selected other clock,1: Selected test clock for test Domain"
group.long 0x88++0x03
line.long 0x00 "RTTSET2_5,"
hexmask.long 0x00 0.--31. 1. "hold0,Test setting input"
group.long 0x8C++0x03
line.long 0x00 "RTTSET3_5,"
hexmask.long.tbyte 0x00 8.--31. 1. "hold1,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "hold0,Test setting input"
group.long 0x90++0x03
line.long 0x00 "RTTSET4_5,"
hexmask.long.word 0x00 16.--31. 1. "hold2,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "hold1,Test setting input"
group.long 0x94++0x03
line.long 0x00 "RTTSET5_5,"
hexmask.long.byte 0x00 24.--31. 1. "hold3,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "hold2,Test setting input"
group.long 0x98++0x03
line.long 0x00 "RTTSET6_5,"
hexmask.long 0x00 0.--31. 1. "hold3,Test setting input"
group.long 0x9C++0x03
line.long 0x00 "RTTSET7_5,"
hexmask.long 0x00 0.--31. 1. "toggle0,Test setting input"
group.long 0xA0++0x03
line.long 0x00 "RTTSET8_5,"
hexmask.long.tbyte 0x00 8.--31. 1. "toggle1,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "toggle0,Test setting input"
group.long 0xA4++0x03
line.long 0x00 "RTTSET9_5,"
hexmask.long.word 0x00 16.--31. 1. "toggle2,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "toggle1,Test setting input"
group.long 0xA8++0x03
line.long 0x00 "RTTSET10_5,"
hexmask.long.byte 0x00 24.--31. 1. "toggle3,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "toggle2,Test setting input"
group.long 0xAC++0x03
line.long 0x00 "RTTSET11_5,"
hexmask.long 0x00 0.--31. 1. "toggle3,Test setting input"
group.long 0xB0++0x03
line.long 0x00 "RTTSET12_5,"
hexmask.long 0x00 0.--31. 1. "switching0,Test setting input"
group.long 0xB4++0x03
line.long 0x00 "RTTSET13_5,"
hexmask.long.tbyte 0x00 8.--31. 1. "switching1,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "switching0,Test setting input"
group.long 0xB8++0x03
line.long 0x00 "RTTSET14_5,"
hexmask.long.word 0x00 16.--31. 1. "switching2,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "switching1,Test setting input"
group.long 0xBC++0x03
line.long 0x00 "RTTSET15_5,"
hexmask.long.byte 0x00 24.--31. 1. "switching3,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "switching2,Test setting input"
group.long 0xC0++0x03
line.long 0x00 "RTTSET16_5,"
hexmask.long 0x00 0.--31. 1. "switching3,Test setting input"
group.long 0xC4++0x03
line.long 0x00 "RTTSET17_5,"
hexmask.long 0x00 0.--31. 1. "hold4,Test setting input"
group.long 0xC8++0x03
line.long 0x00 "RTTSET18_5,"
hexmask.long.tbyte 0x00 8.--31. 1. "hold5,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "hold4,Test setting input"
group.long 0xCC++0x03
line.long 0x00 "RTTSET19_5,"
hexmask.long.word 0x00 16.--31. 1. "hold6,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "hold5,Test setting input"
group.long 0xD0++0x03
line.long 0x00 "RTTSET20_5,"
hexmask.long.byte 0x00 24.--31. 1. "hold7,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "hold6,Test setting input"
group.long 0xD4++0x03
line.long 0x00 "RTTSET21_5,"
hexmask.long 0x00 0.--31. 1. "hold7,Test setting input"
group.long 0xD8++0x03
line.long 0x00 "RTTSET22_5,"
hexmask.long 0x00 0.--31. 1. "toggle4,Test setting input"
group.long 0xDC++0x03
line.long 0x00 "RTTSET23_5,"
hexmask.long.tbyte 0x00 8.--31. 1. "toggle5,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "toggle4,Test setting input"
group.long 0xE0++0x03
line.long 0x00 "RTTSET24_5,"
hexmask.long.word 0x00 16.--31. 1. "toggle6,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "toggle5,Test setting input"
group.long 0xE4++0x03
line.long 0x00 "RTTSET25_5,"
hexmask.long.byte 0x00 24.--31. 1. "toggle7,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "toggle6,Test setting input"
group.long 0xE8++0x03
line.long 0x00 "RTTSET26_5,"
hexmask.long 0x00 0.--31. 1. "toggle7,Test setting input"
group.long 0xEC++0x03
line.long 0x00 "RTTSET27_5,"
hexmask.long 0x00 0.--31. 1. "switching4,Test setting input"
group.long 0xF0++0x03
line.long 0x00 "RTTSET28_5,"
hexmask.long.tbyte 0x00 8.--31. 1. "switching5,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "switching4,Test setting input"
group.long 0xF4++0x03
line.long 0x00 "RTTSET29_5,"
hexmask.long.word 0x00 16.--31. 1. "switching6,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "switching5,Test setting input"
group.long 0xF8++0x03
line.long 0x00 "RTTSET30_5,"
hexmask.long.byte 0x00 24.--31. 1. "switching7,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "switching6,Test setting input"
group.long 0xFC++0x03
line.long 0x00 "RTTSET31_5,"
hexmask.long 0x00 0.--31. 1. "switching7,Test setting input"
group.long 0x100++0x03
line.long 0x00 "RTTSET32_5,"
hexmask.long 0x00 0.--31. 1. "clknum_31_0,Test setting input"
group.long 0x104++0x03
line.long 0x00 "RTTSET33_5,"
hexmask.long 0x00 0.--31. 1. "Testmat_31_0,Test setting input"
group.long 0x108++0x03
line.long 0x00 "RTTSET34_5,"
hexmask.long 0x00 0.--31. 1. "Testmat_63_32,Test setting input"
group.long 0x10C++0x03
line.long 0x00 "RTTSET35_5,"
hexmask.long 0x00 0.--31. 1. "Testmat_95_64,Test setting input"
group.long 0x110++0x03
line.long 0x00 "RTTSET36_5,"
hexmask.long 0x00 0.--31. 1. "Testmat_127_96,Test setting input"
group.long 0x114++0x03
line.long 0x00 "RTTSET37_5,"
hexmask.long 0x00 0.--31. 1. "Testmat_159_128,Test setting input"
group.long 0x118++0x03
line.long 0x00 "RTTSET38_5,"
hexmask.long 0x00 0.--31. 1. "Testmat_191_160,Test setting input"
group.long 0x11C++0x03
line.long 0x00 "RTTSET39_5,"
hexmask.long 0x00 0.--31. 1. "Testmat_223_192,Test setting input"
group.long 0x120++0x03
line.long 0x00 "RTTSET40_5,"
hexmask.long 0x00 0.--31. 1. "Testmat_255_224,Test setting input"
group.long 0x124++0x03
line.long 0x00 "RTTSET41_5,"
hexmask.long.word 0x00 18.--31. 1. "Reserved_18,Reserved The bit or field is readable only"
hexmask.long.byte 0x00 10.--17. 1. "apbsel,Test setting input"
newline
bitfld.long 0x00 6.--9. "mbsel,Test setting input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--5. "coreselect,Test setting input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x128++0x03
line.long 0x00 "RTTSET42_5,"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved The bit or field is readable only" "0,1,2,3"
hexmask.long.word 0x00 16.--29. 1. "Y_address,Test setting input"
newline
rbitfld.long 0x00 14.--15. "Reserved_14,Reserved The bit or field is readable only" "0,1,2,3"
hexmask.long.word 0x00 0.--13. 1. "X_address,Test setting input"
group.long 0x12C++0x03
line.long 0x00 "RTTSET43_5,"
rbitfld.long 0x00 31. "Reserved_31,Reserved The bit or field is readable only" "0,1"
hexmask.long.tbyte 0x00 14.--30. 1. "XY,Test setting input"
newline
hexmask.long.word 0x00 0.--13. 1. "Z_address,Test setting input"
group.long 0x130++0x03
line.long 0x00 "RTTSET44_5,"
rbitfld.long 0x00 26.--31. "Reserved_26,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x00 16.--25. 1. "scanchain,Test setting input for hardware-SCAN"
newline
hexmask.long.word 0x00 0.--15. 1. "scanpat,Test setting input for hardware-SCAN"
group.long 0x400++0x03
line.long 0x00 "PSTRSTT5,"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved"
rbitfld.long 0x00 12. "R_rst_T,BIST Redundant result" "0: pass,1: fail"
newline
rbitfld.long 0x00 11. "Reserved_11,Reserved" "0,1"
rbitfld.long 0x00 8.--10. "error_T,BIST error" "0: Pass,1: Fail,2: TimeOut,?,4: BUS error,?..."
newline
rbitfld.long 0x00 4.--7. "testnum_T,Number of tests" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 2.--3. "status_R,BIST Redundant status (Safety function)" "0: unexec,1: wait,2: exec,3: finish"
newline
rbitfld.long 0x00 0.--1. "status_T,BIST status" "0: unexec,1: wait,2: exec,3: finish"
group.long 0x440++0x03
line.long 0x00 "PSTCNT5,"
hexmask.long 0x00 0.--31. 1. "Stop,FieldBIST internal WDT (high counter) stop value"
group.long 0x444++0x03
line.long 0x00 "RTTRSTT5,When status_T in the RTTRSTT register is"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved" "0,1,2,3"
rbitfld.long 0x00 29. "IL_flag2,Runtime Test Illegal suspension flag-2" "0,1"
newline
rbitfld.long 0x00 28. "IL_flag1,Runtime Test Illegal suspension flag-1" "0,1"
rbitfld.long 0x00 27. "CONDF,Debug monitor of FieldBIST condition" "0: not response,1: responded"
newline
rbitfld.long 0x00 24.--26. "BUS_cond,Debug code of BUS condition" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 13.--23. 1. "Reserved_13,Reserved"
newline
rbitfld.long 0x00 12. "R_rst_T,BIST Redundant result (Safety function)" "0: Pass,1: Fail"
rbitfld.long 0x00 11. "Achk,Debug code of address check" "0: normal,1: warning"
newline
rbitfld.long 0x00 8.--10. "error_T,BIST error" "0: Pass,1: Fail,2: TimeOut,?,4: BUS error,?..."
rbitfld.long 0x00 4.--7. "testnum_T,Number of tests" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 2.--3. "R_status_T,BIST redundant status" "0: unexec,1: wait,2: exec,3: finish"
rbitfld.long 0x00 0.--1. "status_T,BIST status" "0: unexec,1: wait,2: exec,3: finish"
group.long 0x458++0x03
line.long 0x00 "RTTCNT5,"
hexmask.long 0x00 0.--31. 1. "Stop,WDT (high counter) stop value"
group.long 0x4A0++0x03
line.long 0x00 "SLFRVS5,"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved"
hexmask.long.tbyte 0x00 0.--19. 1. "REVERS,Expected value reverse for Self-Check SISR"
group.long 0x4A4++0x03
line.long 0x00 "SLFRST5,In case of the SLFR bits of the RTTRSTT register is 1B'1 SCNT bit returns to 1"
rbitfld.long 0x00 26.--31. "SCNT,Self-Check counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 24.--25. "STS,Self-Check status" "0: unexec,1: exec,?,3: finish"
newline
hexmask.long.tbyte 0x00 1.--23. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "STR,Self -Check Result" "0: Pass,1: Fail"
group.long 0x4C0++0x03
line.long 0x00 "ERRSET5,"
hexmask.long 0x00 3.--31. 1. "Reserved_3,Reserved"
bitfld.long 0x00 2. "DSB,Dummy set BUS-Error (set of fbc_rt_safetyerr)" "0,1"
newline
bitfld.long 0x00 1. "DST,Dummy set Time out (set of fbc_rt_overerr)" "0,1"
bitfld.long 0x00 0. "DSF,Dummy set Fail (set of fbc_rt_fail)" "0,1"
tree.end
tree "FUNCTIONAL_SAFETY_INST_5"
base ad:0xFFFC0000
group.long 0x00++0x03
line.long 0x00 "RTTEX6,SLFR and SLFE bit of the RTTEX are effective only when KCD bit is H'F1"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved" "0,1,2,3"
bitfld.long 0x00 29. "SLFR,Self-Check Counter Reset for field BIST activator" "0: Counter Reset,1: Counter not Reset"
newline
bitfld.long 0x00 28. "SLFE,Execution of Self-Check for Field BIST activator" "0: Not Execution of Self-Check for Field BIST,1: Execution of Self-Check for Field BIST.."
rbitfld.long 0x00 24.--27. "Reserved_24,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.byte 0x00 16.--23. 1. "KCD,Key Code H'5A: Effective execution of Run Time Test H'F1: Effective execution of Self-Check for field BIST activator"
rbitfld.long 0x00 11.--15. "Reserved_11,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "STM,Single Step Test Mode" "?,1: LBIST,2: MBIST,3: SCAN,?..."
bitfld.long 0x00 6.--7. "INTM,Interrupt mask" "0: non mask *1,?,2: Only at the time of the fail(fba_rt_finish are,?..."
newline
bitfld.long 0x00 5. "SSZ,SCAN Pattern size Valid only when STM=011" "0: 32bit mode,1: 16bit mode"
bitfld.long 0x00 4. "TR,Select the value of the timer" "0: ROM,1: register"
newline
bitfld.long 0x00 3. "WM,Wfi mask" "0: not mask,1: mask"
bitfld.long 0x00 2. "TM,Mask the judgment of timer" "0: not mask,1: mask"
newline
bitfld.long 0x00 1. "STP,Single Step Mode" "0: ROM batch mode,1: Single Step Mode"
bitfld.long 0x00 0. "EX,Execution of Runtime Test" "0: Not Execution of Runtime Test,1: Execution of Runtime Test"
group.long 0x04++0x03
line.long 0x00 "RTTMI16,"
rbitfld.long 0x00 27.--31. "Reserved_27,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 24.--26. "RPROT,Protection type of MEMORY" "0: Unprivileged access,1: Privileged access,?..."
newline
hexmask.long.byte 0x00 16.--23. 1. "MADDR_upper,Memory upper address[39:32] that stores the SCAN pattern"
hexmask.long.word 0x00 0.--15. 1. "MUNIT,Number of units (1 unit = 128 Byte)"
group.long 0x08++0x03
line.long 0x00 "RTTMI26,"
hexmask.long 0x00 0.--31. 1. "MADDR,Memory address that stores the SCAN pattern"
group.long 0x0C++0x03
line.long 0x00 "RTTSISR16,"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved"
hexmask.long.tbyte 0x00 0.--19. 1. "SISR1,SISR-TEST#1 Expected value"
group.long 0x14++0x03
line.long 0x00 "RTTUC6,"
hexmask.long 0x00 0.--31. 1. "U_WDT,Upper counter of Watchdog Timer"
group.long 0x18++0x03
line.long 0x00 "RTTDC6,"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved"
hexmask.long.word 0x00 0.--15. 1. "L_WDT,Lower counter of Watchdog Timer"
group.long 0x80++0x03
line.long 0x00 "RTTSET0_6,"
hexmask.long 0x00 0.--31. 1. "test_clock,Test setting input"
group.long 0x84++0x03
line.long 0x00 "RTTSET1_6,"
hexmask.long 0x00 2.--31. 1. "Reserved_2,Reserved"
bitfld.long 0x00 1. "reset,Test setting input" "0: Reset test disabled,1: Reset test enabled"
newline
bitfld.long 0x00 0. "tt,Test setting input" "0: Selected other clock,1: Selected test clock for test Domain"
group.long 0x88++0x03
line.long 0x00 "RTTSET2_6,"
hexmask.long 0x00 0.--31. 1. "hold0,Test setting input"
group.long 0x8C++0x03
line.long 0x00 "RTTSET3_6,"
hexmask.long.tbyte 0x00 8.--31. 1. "hold1,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "hold0,Test setting input"
group.long 0x90++0x03
line.long 0x00 "RTTSET4_6,"
hexmask.long.word 0x00 16.--31. 1. "hold2,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "hold1,Test setting input"
group.long 0x94++0x03
line.long 0x00 "RTTSET5_6,"
hexmask.long.byte 0x00 24.--31. 1. "hold3,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "hold2,Test setting input"
group.long 0x98++0x03
line.long 0x00 "RTTSET6_6,"
hexmask.long 0x00 0.--31. 1. "hold3,Test setting input"
group.long 0x9C++0x03
line.long 0x00 "RTTSET7_6,"
hexmask.long 0x00 0.--31. 1. "toggle0,Test setting input"
group.long 0xA0++0x03
line.long 0x00 "RTTSET8_6,"
hexmask.long.tbyte 0x00 8.--31. 1. "toggle1,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "toggle0,Test setting input"
group.long 0xA4++0x03
line.long 0x00 "RTTSET9_6,"
hexmask.long.word 0x00 16.--31. 1. "toggle2,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "toggle1,Test setting input"
group.long 0xA8++0x03
line.long 0x00 "RTTSET10_6,"
hexmask.long.byte 0x00 24.--31. 1. "toggle3,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "toggle2,Test setting input"
group.long 0xAC++0x03
line.long 0x00 "RTTSET11_6,"
hexmask.long 0x00 0.--31. 1. "toggle3,Test setting input"
group.long 0xB0++0x03
line.long 0x00 "RTTSET12_6,"
hexmask.long 0x00 0.--31. 1. "switching0,Test setting input"
group.long 0xB4++0x03
line.long 0x00 "RTTSET13_6,"
hexmask.long.tbyte 0x00 8.--31. 1. "switching1,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "switching0,Test setting input"
group.long 0xB8++0x03
line.long 0x00 "RTTSET14_6,"
hexmask.long.word 0x00 16.--31. 1. "switching2,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "switching1,Test setting input"
group.long 0xBC++0x03
line.long 0x00 "RTTSET15_6,"
hexmask.long.byte 0x00 24.--31. 1. "switching3,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "switching2,Test setting input"
group.long 0xC0++0x03
line.long 0x00 "RTTSET16_6,"
hexmask.long 0x00 0.--31. 1. "switching3,Test setting input"
group.long 0xC4++0x03
line.long 0x00 "RTTSET17_6,"
hexmask.long 0x00 0.--31. 1. "hold4,Test setting input"
group.long 0xC8++0x03
line.long 0x00 "RTTSET18_6,"
hexmask.long.tbyte 0x00 8.--31. 1. "hold5,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "hold4,Test setting input"
group.long 0xCC++0x03
line.long 0x00 "RTTSET19_6,"
hexmask.long.word 0x00 16.--31. 1. "hold6,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "hold5,Test setting input"
group.long 0xD0++0x03
line.long 0x00 "RTTSET20_6,"
hexmask.long.byte 0x00 24.--31. 1. "hold7,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "hold6,Test setting input"
group.long 0xD4++0x03
line.long 0x00 "RTTSET21_6,"
hexmask.long 0x00 0.--31. 1. "hold7,Test setting input"
group.long 0xD8++0x03
line.long 0x00 "RTTSET22_6,"
hexmask.long 0x00 0.--31. 1. "toggle4,Test setting input"
group.long 0xDC++0x03
line.long 0x00 "RTTSET23_6,"
hexmask.long.tbyte 0x00 8.--31. 1. "toggle5,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "toggle4,Test setting input"
group.long 0xE0++0x03
line.long 0x00 "RTTSET24_6,"
hexmask.long.word 0x00 16.--31. 1. "toggle6,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "toggle5,Test setting input"
group.long 0xE4++0x03
line.long 0x00 "RTTSET25_6,"
hexmask.long.byte 0x00 24.--31. 1. "toggle7,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "toggle6,Test setting input"
group.long 0xE8++0x03
line.long 0x00 "RTTSET26_6,"
hexmask.long 0x00 0.--31. 1. "toggle7,Test setting input"
group.long 0xEC++0x03
line.long 0x00 "RTTSET27_6,"
hexmask.long 0x00 0.--31. 1. "switching4,Test setting input"
group.long 0xF0++0x03
line.long 0x00 "RTTSET28_6,"
hexmask.long.tbyte 0x00 8.--31. 1. "switching5,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "switching4,Test setting input"
group.long 0xF4++0x03
line.long 0x00 "RTTSET29_6,"
hexmask.long.word 0x00 16.--31. 1. "switching6,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "switching5,Test setting input"
group.long 0xF8++0x03
line.long 0x00 "RTTSET30_6,"
hexmask.long.byte 0x00 24.--31. 1. "switching7,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "switching6,Test setting input"
group.long 0xFC++0x03
line.long 0x00 "RTTSET31_6,"
hexmask.long 0x00 0.--31. 1. "switching7,Test setting input"
group.long 0x100++0x03
line.long 0x00 "RTTSET32_6,"
hexmask.long 0x00 0.--31. 1. "clknum_31_0,Test setting input"
group.long 0x104++0x03
line.long 0x00 "RTTSET33_6,"
hexmask.long 0x00 0.--31. 1. "Testmat_31_0,Test setting input"
group.long 0x108++0x03
line.long 0x00 "RTTSET34_6,"
hexmask.long 0x00 0.--31. 1. "Testmat_63_32,Test setting input"
group.long 0x10C++0x03
line.long 0x00 "RTTSET35_6,"
hexmask.long 0x00 0.--31. 1. "Testmat_95_64,Test setting input"
group.long 0x110++0x03
line.long 0x00 "RTTSET36_6,"
hexmask.long 0x00 0.--31. 1. "Testmat_127_96,Test setting input"
group.long 0x114++0x03
line.long 0x00 "RTTSET37_6,"
hexmask.long 0x00 0.--31. 1. "Testmat_159_128,Test setting input"
group.long 0x118++0x03
line.long 0x00 "RTTSET38_6,"
hexmask.long 0x00 0.--31. 1. "Testmat_191_160,Test setting input"
group.long 0x11C++0x03
line.long 0x00 "RTTSET39_6,"
hexmask.long 0x00 0.--31. 1. "Testmat_223_192,Test setting input"
group.long 0x120++0x03
line.long 0x00 "RTTSET40_6,"
hexmask.long 0x00 0.--31. 1. "Testmat_255_224,Test setting input"
group.long 0x124++0x03
line.long 0x00 "RTTSET41_6,"
hexmask.long.word 0x00 18.--31. 1. "Reserved_18,Reserved The bit or field is readable only"
hexmask.long.byte 0x00 10.--17. 1. "apbsel,Test setting input"
newline
bitfld.long 0x00 6.--9. "mbsel,Test setting input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--5. "coreselect,Test setting input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x128++0x03
line.long 0x00 "RTTSET42_6,"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved The bit or field is readable only" "0,1,2,3"
hexmask.long.word 0x00 16.--29. 1. "Y_address,Test setting input"
newline
rbitfld.long 0x00 14.--15. "Reserved_14,Reserved The bit or field is readable only" "0,1,2,3"
hexmask.long.word 0x00 0.--13. 1. "X_address,Test setting input"
group.long 0x12C++0x03
line.long 0x00 "RTTSET43_6,"
rbitfld.long 0x00 31. "Reserved_31,Reserved The bit or field is readable only" "0,1"
hexmask.long.tbyte 0x00 14.--30. 1. "XY,Test setting input"
newline
hexmask.long.word 0x00 0.--13. 1. "Z_address,Test setting input"
group.long 0x130++0x03
line.long 0x00 "RTTSET44_6,"
rbitfld.long 0x00 26.--31. "Reserved_26,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x00 16.--25. 1. "scanchain,Test setting input for hardware-SCAN"
newline
hexmask.long.word 0x00 0.--15. 1. "scanpat,Test setting input for hardware-SCAN"
group.long 0x400++0x03
line.long 0x00 "PSTRSTT6,"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved"
rbitfld.long 0x00 12. "R_rst_T,BIST Redundant result" "0: pass,1: fail"
newline
rbitfld.long 0x00 11. "Reserved_11,Reserved" "0,1"
rbitfld.long 0x00 8.--10. "error_T,BIST error" "0: Pass,1: Fail,2: TimeOut,?,4: BUS error,?..."
newline
rbitfld.long 0x00 4.--7. "testnum_T,Number of tests" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 2.--3. "status_R,BIST Redundant status (Safety function)" "0: unexec,1: wait,2: exec,3: finish"
newline
rbitfld.long 0x00 0.--1. "status_T,BIST status" "0: unexec,1: wait,2: exec,3: finish"
group.long 0x440++0x03
line.long 0x00 "PSTCNT6,"
hexmask.long 0x00 0.--31. 1. "Stop,FieldBIST internal WDT (high counter) stop value"
group.long 0x444++0x03
line.long 0x00 "RTTRSTT6,When status_T in the RTTRSTT register is"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved" "0,1,2,3"
rbitfld.long 0x00 29. "IL_flag2,Runtime Test Illegal suspension flag-2" "0,1"
newline
rbitfld.long 0x00 28. "IL_flag1,Runtime Test Illegal suspension flag-1" "0,1"
rbitfld.long 0x00 27. "CONDF,Debug monitor of FieldBIST condition" "0: not response,1: responded"
newline
rbitfld.long 0x00 24.--26. "BUS_cond,Debug code of BUS condition" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 13.--23. 1. "Reserved_13,Reserved"
newline
rbitfld.long 0x00 12. "R_rst_T,BIST Redundant result (Safety function)" "0: Pass,1: Fail"
rbitfld.long 0x00 11. "Achk,Debug code of address check" "0: normal,1: warning"
newline
rbitfld.long 0x00 8.--10. "error_T,BIST error" "0: Pass,1: Fail,2: TimeOut,?,4: BUS error,?..."
rbitfld.long 0x00 4.--7. "testnum_T,Number of tests" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 2.--3. "R_status_T,BIST redundant status" "0: unexec,1: wait,2: exec,3: finish"
rbitfld.long 0x00 0.--1. "status_T,BIST status" "0: unexec,1: wait,2: exec,3: finish"
group.long 0x458++0x03
line.long 0x00 "RTTCNT6,"
hexmask.long 0x00 0.--31. 1. "Stop,WDT (high counter) stop value"
group.long 0x4A0++0x03
line.long 0x00 "SLFRVS6,"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved"
hexmask.long.tbyte 0x00 0.--19. 1. "REVERS,Expected value reverse for Self-Check SISR"
group.long 0x4A4++0x03
line.long 0x00 "SLFRST6,In case of the SLFR bits of the RTTRSTT register is 1B'1 SCNT bit returns to 1"
rbitfld.long 0x00 26.--31. "SCNT,Self-Check counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 24.--25. "STS,Self-Check status" "0: unexec,1: exec,?,3: finish"
newline
hexmask.long.tbyte 0x00 1.--23. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "STR,Self -Check Result" "0: Pass,1: Fail"
group.long 0x4C0++0x03
line.long 0x00 "ERRSET6,"
hexmask.long 0x00 3.--31. 1. "Reserved_3,Reserved"
bitfld.long 0x00 2. "DSB,Dummy set BUS-Error (set of fbc_rt_safetyerr)" "0,1"
newline
bitfld.long 0x00 1. "DST,Dummy set Time out (set of fbc_rt_overerr)" "0,1"
bitfld.long 0x00 0. "DSF,Dummy set Fail (set of fbc_rt_fail)" "0,1"
tree.end
tree "FUNCTIONAL_SAFETY_INST_6"
base ad:0xFF87A000
group.long 0x00++0x03
line.long 0x00 "RTTEX7,SLFR and SLFE bit of the RTTEX are effective only when KCD bit is H'F1"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved" "0,1,2,3"
bitfld.long 0x00 29. "SLFR,Self-Check Counter Reset for field BIST activator" "0: Counter Reset,1: Counter not Reset"
newline
bitfld.long 0x00 28. "SLFE,Execution of Self-Check for Field BIST activator" "0: Not Execution of Self-Check for Field BIST,1: Execution of Self-Check for Field BIST.."
rbitfld.long 0x00 24.--27. "Reserved_24,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.byte 0x00 16.--23. 1. "KCD,Key Code H'5A: Effective execution of Run Time Test H'F1: Effective execution of Self-Check for field BIST activator"
rbitfld.long 0x00 11.--15. "Reserved_11,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "STM,Single Step Test Mode" "?,1: LBIST,2: MBIST,3: SCAN,?..."
bitfld.long 0x00 6.--7. "INTM,Interrupt mask" "0: non mask *1,?,2: Only at the time of the fail(fba_rt_finish are,?..."
newline
bitfld.long 0x00 5. "SSZ,SCAN Pattern size Valid only when STM=011" "0: 32bit mode,1: 16bit mode"
bitfld.long 0x00 4. "TR,Select the value of the timer" "0: ROM,1: register"
newline
bitfld.long 0x00 3. "WM,Wfi mask" "0: not mask,1: mask"
bitfld.long 0x00 2. "TM,Mask the judgment of timer" "0: not mask,1: mask"
newline
bitfld.long 0x00 1. "STP,Single Step Mode" "0: ROM batch mode,1: Single Step Mode"
bitfld.long 0x00 0. "EX,Execution of Runtime Test" "0: Not Execution of Runtime Test,1: Execution of Runtime Test"
group.long 0x04++0x03
line.long 0x00 "RTTMI17,"
rbitfld.long 0x00 27.--31. "Reserved_27,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 24.--26. "RPROT,Protection type of MEMORY" "0: Unprivileged access,1: Privileged access,?..."
newline
hexmask.long.byte 0x00 16.--23. 1. "MADDR_upper,Memory upper address[39:32] that stores the SCAN pattern"
hexmask.long.word 0x00 0.--15. 1. "MUNIT,Number of units (1 unit = 128 Byte)"
group.long 0x08++0x03
line.long 0x00 "RTTMI27,"
hexmask.long 0x00 0.--31. 1. "MADDR,Memory address that stores the SCAN pattern"
group.long 0x0C++0x03
line.long 0x00 "RTTSISR17,"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved"
hexmask.long.tbyte 0x00 0.--19. 1. "SISR1,SISR-TEST#1 Expected value"
group.long 0x14++0x03
line.long 0x00 "RTTUC7,"
hexmask.long 0x00 0.--31. 1. "U_WDT,Upper counter of Watchdog Timer"
group.long 0x18++0x03
line.long 0x00 "RTTDC7,"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved"
hexmask.long.word 0x00 0.--15. 1. "L_WDT,Lower counter of Watchdog Timer"
group.long 0x80++0x03
line.long 0x00 "RTTSET0_7,"
hexmask.long 0x00 0.--31. 1. "test_clock,Test setting input"
group.long 0x84++0x03
line.long 0x00 "RTTSET1_7,"
hexmask.long 0x00 2.--31. 1. "Reserved_2,Reserved"
bitfld.long 0x00 1. "reset,Test setting input" "0: Reset test disabled,1: Reset test enabled"
newline
bitfld.long 0x00 0. "tt,Test setting input" "0: Selected other clock,1: Selected test clock for test Domain"
group.long 0x88++0x03
line.long 0x00 "RTTSET2_7,"
hexmask.long 0x00 0.--31. 1. "hold0,Test setting input"
group.long 0x8C++0x03
line.long 0x00 "RTTSET3_7,"
hexmask.long.tbyte 0x00 8.--31. 1. "hold1,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "hold0,Test setting input"
group.long 0x90++0x03
line.long 0x00 "RTTSET4_7,"
hexmask.long.word 0x00 16.--31. 1. "hold2,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "hold1,Test setting input"
group.long 0x94++0x03
line.long 0x00 "RTTSET5_7,"
hexmask.long.byte 0x00 24.--31. 1. "hold3,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "hold2,Test setting input"
group.long 0x98++0x03
line.long 0x00 "RTTSET6_7,"
hexmask.long 0x00 0.--31. 1. "hold3,Test setting input"
group.long 0x9C++0x03
line.long 0x00 "RTTSET7_7,"
hexmask.long 0x00 0.--31. 1. "toggle0,Test setting input"
group.long 0xA0++0x03
line.long 0x00 "RTTSET8_7,"
hexmask.long.tbyte 0x00 8.--31. 1. "toggle1,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "toggle0,Test setting input"
group.long 0xA4++0x03
line.long 0x00 "RTTSET9_7,"
hexmask.long.word 0x00 16.--31. 1. "toggle2,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "toggle1,Test setting input"
group.long 0xA8++0x03
line.long 0x00 "RTTSET10_7,"
hexmask.long.byte 0x00 24.--31. 1. "toggle3,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "toggle2,Test setting input"
group.long 0xAC++0x03
line.long 0x00 "RTTSET11_7,"
hexmask.long 0x00 0.--31. 1. "toggle3,Test setting input"
group.long 0xB0++0x03
line.long 0x00 "RTTSET12_7,"
hexmask.long 0x00 0.--31. 1. "switching0,Test setting input"
group.long 0xB4++0x03
line.long 0x00 "RTTSET13_7,"
hexmask.long.tbyte 0x00 8.--31. 1. "switching1,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "switching0,Test setting input"
group.long 0xB8++0x03
line.long 0x00 "RTTSET14_7,"
hexmask.long.word 0x00 16.--31. 1. "switching2,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "switching1,Test setting input"
group.long 0xBC++0x03
line.long 0x00 "RTTSET15_7,"
hexmask.long.byte 0x00 24.--31. 1. "switching3,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "switching2,Test setting input"
group.long 0xC0++0x03
line.long 0x00 "RTTSET16_7,"
hexmask.long 0x00 0.--31. 1. "switching3,Test setting input"
group.long 0xC4++0x03
line.long 0x00 "RTTSET17_7,"
hexmask.long 0x00 0.--31. 1. "hold4,Test setting input"
group.long 0xC8++0x03
line.long 0x00 "RTTSET18_7,"
hexmask.long.tbyte 0x00 8.--31. 1. "hold5,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "hold4,Test setting input"
group.long 0xCC++0x03
line.long 0x00 "RTTSET19_7,"
hexmask.long.word 0x00 16.--31. 1. "hold6,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "hold5,Test setting input"
group.long 0xD0++0x03
line.long 0x00 "RTTSET20_7,"
hexmask.long.byte 0x00 24.--31. 1. "hold7,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "hold6,Test setting input"
group.long 0xD4++0x03
line.long 0x00 "RTTSET21_7,"
hexmask.long 0x00 0.--31. 1. "hold7,Test setting input"
group.long 0xD8++0x03
line.long 0x00 "RTTSET22_7,"
hexmask.long 0x00 0.--31. 1. "toggle4,Test setting input"
group.long 0xDC++0x03
line.long 0x00 "RTTSET23_7,"
hexmask.long.tbyte 0x00 8.--31. 1. "toggle5,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "toggle4,Test setting input"
group.long 0xE0++0x03
line.long 0x00 "RTTSET24_7,"
hexmask.long.word 0x00 16.--31. 1. "toggle6,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "toggle5,Test setting input"
group.long 0xE4++0x03
line.long 0x00 "RTTSET25_7,"
hexmask.long.byte 0x00 24.--31. 1. "toggle7,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "toggle6,Test setting input"
group.long 0xE8++0x03
line.long 0x00 "RTTSET26_7,"
hexmask.long 0x00 0.--31. 1. "toggle7,Test setting input"
group.long 0xEC++0x03
line.long 0x00 "RTTSET27_7,"
hexmask.long 0x00 0.--31. 1. "switching4,Test setting input"
group.long 0xF0++0x03
line.long 0x00 "RTTSET28_7,"
hexmask.long.tbyte 0x00 8.--31. 1. "switching5,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "switching4,Test setting input"
group.long 0xF4++0x03
line.long 0x00 "RTTSET29_7,"
hexmask.long.word 0x00 16.--31. 1. "switching6,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "switching5,Test setting input"
group.long 0xF8++0x03
line.long 0x00 "RTTSET30_7,"
hexmask.long.byte 0x00 24.--31. 1. "switching7,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "switching6,Test setting input"
group.long 0xFC++0x03
line.long 0x00 "RTTSET31_7,"
hexmask.long 0x00 0.--31. 1. "switching7,Test setting input"
group.long 0x100++0x03
line.long 0x00 "RTTSET32_7,"
hexmask.long 0x00 0.--31. 1. "clknum_31_0,Test setting input"
group.long 0x104++0x03
line.long 0x00 "RTTSET33_7,"
hexmask.long 0x00 0.--31. 1. "Testmat_31_0,Test setting input"
group.long 0x108++0x03
line.long 0x00 "RTTSET34_7,"
hexmask.long 0x00 0.--31. 1. "Testmat_63_32,Test setting input"
group.long 0x10C++0x03
line.long 0x00 "RTTSET35_7,"
hexmask.long 0x00 0.--31. 1. "Testmat_95_64,Test setting input"
group.long 0x110++0x03
line.long 0x00 "RTTSET36_7,"
hexmask.long 0x00 0.--31. 1. "Testmat_127_96,Test setting input"
group.long 0x114++0x03
line.long 0x00 "RTTSET37_7,"
hexmask.long 0x00 0.--31. 1. "Testmat_159_128,Test setting input"
group.long 0x118++0x03
line.long 0x00 "RTTSET38_7,"
hexmask.long 0x00 0.--31. 1. "Testmat_191_160,Test setting input"
group.long 0x11C++0x03
line.long 0x00 "RTTSET39_7,"
hexmask.long 0x00 0.--31. 1. "Testmat_223_192,Test setting input"
group.long 0x120++0x03
line.long 0x00 "RTTSET40_7,"
hexmask.long 0x00 0.--31. 1. "Testmat_255_224,Test setting input"
group.long 0x124++0x03
line.long 0x00 "RTTSET41_7,"
hexmask.long.word 0x00 18.--31. 1. "Reserved_18,Reserved The bit or field is readable only"
hexmask.long.byte 0x00 10.--17. 1. "apbsel,Test setting input"
newline
bitfld.long 0x00 6.--9. "mbsel,Test setting input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--5. "coreselect,Test setting input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x128++0x03
line.long 0x00 "RTTSET42_7,"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved The bit or field is readable only" "0,1,2,3"
hexmask.long.word 0x00 16.--29. 1. "Y_address,Test setting input"
newline
rbitfld.long 0x00 14.--15. "Reserved_14,Reserved The bit or field is readable only" "0,1,2,3"
hexmask.long.word 0x00 0.--13. 1. "X_address,Test setting input"
group.long 0x12C++0x03
line.long 0x00 "RTTSET43_7,"
rbitfld.long 0x00 31. "Reserved_31,Reserved The bit or field is readable only" "0,1"
hexmask.long.tbyte 0x00 14.--30. 1. "XY,Test setting input"
newline
hexmask.long.word 0x00 0.--13. 1. "Z_address,Test setting input"
group.long 0x130++0x03
line.long 0x00 "RTTSET44_7,"
rbitfld.long 0x00 26.--31. "Reserved_26,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x00 16.--25. 1. "scanchain,Test setting input for hardware-SCAN"
newline
hexmask.long.word 0x00 0.--15. 1. "scanpat,Test setting input for hardware-SCAN"
group.long 0x400++0x03
line.long 0x00 "PSTRSTT7,"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved"
rbitfld.long 0x00 12. "R_rst_T,BIST Redundant result" "0: pass,1: fail"
newline
rbitfld.long 0x00 11. "Reserved_11,Reserved" "0,1"
rbitfld.long 0x00 8.--10. "error_T,BIST error" "0: Pass,1: Fail,2: TimeOut,?,4: BUS error,?..."
newline
rbitfld.long 0x00 4.--7. "testnum_T,Number of tests" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 2.--3. "status_R,BIST Redundant status (Safety function)" "0: unexec,1: wait,2: exec,3: finish"
newline
rbitfld.long 0x00 0.--1. "status_T,BIST status" "0: unexec,1: wait,2: exec,3: finish"
group.long 0x440++0x03
line.long 0x00 "PSTCNT7,"
hexmask.long 0x00 0.--31. 1. "Stop,FieldBIST internal WDT (high counter) stop value"
group.long 0x444++0x03
line.long 0x00 "RTTRSTT7,When status_T in the RTTRSTT register is"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved" "0,1,2,3"
rbitfld.long 0x00 29. "IL_flag2,Runtime Test Illegal suspension flag-2" "0,1"
newline
rbitfld.long 0x00 28. "IL_flag1,Runtime Test Illegal suspension flag-1" "0,1"
rbitfld.long 0x00 27. "CONDF,Debug monitor of FieldBIST condition" "0: not response,1: responded"
newline
rbitfld.long 0x00 24.--26. "BUS_cond,Debug code of BUS condition" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 13.--23. 1. "Reserved_13,Reserved"
newline
rbitfld.long 0x00 12. "R_rst_T,BIST Redundant result (Safety function)" "0: Pass,1: Fail"
rbitfld.long 0x00 11. "Achk,Debug code of address check" "0: normal,1: warning"
newline
rbitfld.long 0x00 8.--10. "error_T,BIST error" "0: Pass,1: Fail,2: TimeOut,?,4: BUS error,?..."
rbitfld.long 0x00 4.--7. "testnum_T,Number of tests" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 2.--3. "R_status_T,BIST redundant status" "0: unexec,1: wait,2: exec,3: finish"
rbitfld.long 0x00 0.--1. "status_T,BIST status" "0: unexec,1: wait,2: exec,3: finish"
group.long 0x458++0x03
line.long 0x00 "RTTCNT7,"
hexmask.long 0x00 0.--31. 1. "Stop,WDT (high counter) stop value"
group.long 0x4A0++0x03
line.long 0x00 "SLFRVS7,"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved"
hexmask.long.tbyte 0x00 0.--19. 1. "REVERS,Expected value reverse for Self-Check SISR"
group.long 0x4A4++0x03
line.long 0x00 "SLFRST7,In case of the SLFR bits of the RTTRSTT register is 1B'1 SCNT bit returns to 1"
rbitfld.long 0x00 26.--31. "SCNT,Self-Check counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 24.--25. "STS,Self-Check status" "0: unexec,1: exec,?,3: finish"
newline
hexmask.long.tbyte 0x00 1.--23. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "STR,Self -Check Result" "0: Pass,1: Fail"
group.long 0x4C0++0x03
line.long 0x00 "ERRSET7,"
hexmask.long 0x00 3.--31. 1. "Reserved_3,Reserved"
bitfld.long 0x00 2. "DSB,Dummy set BUS-Error (set of fbc_rt_safetyerr)" "0,1"
newline
bitfld.long 0x00 1. "DST,Dummy set Time out (set of fbc_rt_overerr)" "0,1"
bitfld.long 0x00 0. "DSF,Dummy set Fail (set of fbc_rt_fail)" "0,1"
tree.end
tree "FUNCTIONAL_SAFETY_INST_7"
base ad:0xFF878000
group.long 0x00++0x03
line.long 0x00 "RTTEX8,SLFR and SLFE bit of the RTTEX are effective only when KCD bit is H'F1"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved" "0,1,2,3"
bitfld.long 0x00 29. "SLFR,Self-Check Counter Reset for field BIST activator" "0: Counter Reset,1: Counter not Reset"
newline
bitfld.long 0x00 28. "SLFE,Execution of Self-Check for Field BIST activator" "0: Not Execution of Self-Check for Field BIST,1: Execution of Self-Check for Field BIST.."
rbitfld.long 0x00 24.--27. "Reserved_24,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.byte 0x00 16.--23. 1. "KCD,Key Code H'5A: Effective execution of Run Time Test H'F1: Effective execution of Self-Check for field BIST activator"
rbitfld.long 0x00 11.--15. "Reserved_11,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "STM,Single Step Test Mode" "?,1: LBIST,2: MBIST,3: SCAN,?..."
bitfld.long 0x00 6.--7. "INTM,Interrupt mask" "0: non mask *1,?,2: Only at the time of the fail(fba_rt_finish are,?..."
newline
bitfld.long 0x00 5. "SSZ,SCAN Pattern size Valid only when STM=011" "0: 32bit mode,1: 16bit mode"
bitfld.long 0x00 4. "TR,Select the value of the timer" "0: ROM,1: register"
newline
bitfld.long 0x00 3. "WM,Wfi mask" "0: not mask,1: mask"
bitfld.long 0x00 2. "TM,Mask the judgment of timer" "0: not mask,1: mask"
newline
bitfld.long 0x00 1. "STP,Single Step Mode" "0: ROM batch mode,1: Single Step Mode"
bitfld.long 0x00 0. "EX,Execution of Runtime Test" "0: Not Execution of Runtime Test,1: Execution of Runtime Test"
group.long 0x04++0x03
line.long 0x00 "RTTMI18,"
rbitfld.long 0x00 27.--31. "Reserved_27,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 24.--26. "RPROT,Protection type of MEMORY" "0: Unprivileged access,1: Privileged access,?..."
newline
hexmask.long.byte 0x00 16.--23. 1. "MADDR_upper,Memory upper address[39:32] that stores the SCAN pattern"
hexmask.long.word 0x00 0.--15. 1. "MUNIT,Number of units (1 unit = 128 Byte)"
group.long 0x08++0x03
line.long 0x00 "RTTMI28,"
hexmask.long 0x00 0.--31. 1. "MADDR,Memory address that stores the SCAN pattern"
group.long 0x0C++0x03
line.long 0x00 "RTTSISR18,"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved"
hexmask.long.tbyte 0x00 0.--19. 1. "SISR1,SISR-TEST#1 Expected value"
group.long 0x14++0x03
line.long 0x00 "RTTUC8,"
hexmask.long 0x00 0.--31. 1. "U_WDT,Upper counter of Watchdog Timer"
group.long 0x18++0x03
line.long 0x00 "RTTDC8,"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved"
hexmask.long.word 0x00 0.--15. 1. "L_WDT,Lower counter of Watchdog Timer"
group.long 0x80++0x03
line.long 0x00 "RTTSET0_8,"
hexmask.long 0x00 0.--31. 1. "test_clock,Test setting input"
group.long 0x84++0x03
line.long 0x00 "RTTSET1_8,"
hexmask.long 0x00 2.--31. 1. "Reserved_2,Reserved"
bitfld.long 0x00 1. "reset,Test setting input" "0: Reset test disabled,1: Reset test enabled"
newline
bitfld.long 0x00 0. "tt,Test setting input" "0: Selected other clock,1: Selected test clock for test Domain"
group.long 0x88++0x03
line.long 0x00 "RTTSET2_8,"
hexmask.long 0x00 0.--31. 1. "hold0,Test setting input"
group.long 0x8C++0x03
line.long 0x00 "RTTSET3_8,"
hexmask.long.tbyte 0x00 8.--31. 1. "hold1,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "hold0,Test setting input"
group.long 0x90++0x03
line.long 0x00 "RTTSET4_8,"
hexmask.long.word 0x00 16.--31. 1. "hold2,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "hold1,Test setting input"
group.long 0x94++0x03
line.long 0x00 "RTTSET5_8,"
hexmask.long.byte 0x00 24.--31. 1. "hold3,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "hold2,Test setting input"
group.long 0x98++0x03
line.long 0x00 "RTTSET6_8,"
hexmask.long 0x00 0.--31. 1. "hold3,Test setting input"
group.long 0x9C++0x03
line.long 0x00 "RTTSET7_8,"
hexmask.long 0x00 0.--31. 1. "toggle0,Test setting input"
group.long 0xA0++0x03
line.long 0x00 "RTTSET8_8,"
hexmask.long.tbyte 0x00 8.--31. 1. "toggle1,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "toggle0,Test setting input"
group.long 0xA4++0x03
line.long 0x00 "RTTSET9_8,"
hexmask.long.word 0x00 16.--31. 1. "toggle2,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "toggle1,Test setting input"
group.long 0xA8++0x03
line.long 0x00 "RTTSET10_8,"
hexmask.long.byte 0x00 24.--31. 1. "toggle3,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "toggle2,Test setting input"
group.long 0xAC++0x03
line.long 0x00 "RTTSET11_8,"
hexmask.long 0x00 0.--31. 1. "toggle3,Test setting input"
group.long 0xB0++0x03
line.long 0x00 "RTTSET12_8,"
hexmask.long 0x00 0.--31. 1. "switching0,Test setting input"
group.long 0xB4++0x03
line.long 0x00 "RTTSET13_8,"
hexmask.long.tbyte 0x00 8.--31. 1. "switching1,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "switching0,Test setting input"
group.long 0xB8++0x03
line.long 0x00 "RTTSET14_8,"
hexmask.long.word 0x00 16.--31. 1. "switching2,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "switching1,Test setting input"
group.long 0xBC++0x03
line.long 0x00 "RTTSET15_8,"
hexmask.long.byte 0x00 24.--31. 1. "switching3,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "switching2,Test setting input"
group.long 0xC0++0x03
line.long 0x00 "RTTSET16_8,"
hexmask.long 0x00 0.--31. 1. "switching3,Test setting input"
group.long 0xC4++0x03
line.long 0x00 "RTTSET17_8,"
hexmask.long 0x00 0.--31. 1. "hold4,Test setting input"
group.long 0xC8++0x03
line.long 0x00 "RTTSET18_8,"
hexmask.long.tbyte 0x00 8.--31. 1. "hold5,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "hold4,Test setting input"
group.long 0xCC++0x03
line.long 0x00 "RTTSET19_8,"
hexmask.long.word 0x00 16.--31. 1. "hold6,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "hold5,Test setting input"
group.long 0xD0++0x03
line.long 0x00 "RTTSET20_8,"
hexmask.long.byte 0x00 24.--31. 1. "hold7,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "hold6,Test setting input"
group.long 0xD4++0x03
line.long 0x00 "RTTSET21_8,"
hexmask.long 0x00 0.--31. 1. "hold7,Test setting input"
group.long 0xD8++0x03
line.long 0x00 "RTTSET22_8,"
hexmask.long 0x00 0.--31. 1. "toggle4,Test setting input"
group.long 0xDC++0x03
line.long 0x00 "RTTSET23_8,"
hexmask.long.tbyte 0x00 8.--31. 1. "toggle5,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "toggle4,Test setting input"
group.long 0xE0++0x03
line.long 0x00 "RTTSET24_8,"
hexmask.long.word 0x00 16.--31. 1. "toggle6,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "toggle5,Test setting input"
group.long 0xE4++0x03
line.long 0x00 "RTTSET25_8,"
hexmask.long.byte 0x00 24.--31. 1. "toggle7,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "toggle6,Test setting input"
group.long 0xE8++0x03
line.long 0x00 "RTTSET26_8,"
hexmask.long 0x00 0.--31. 1. "toggle7,Test setting input"
group.long 0xEC++0x03
line.long 0x00 "RTTSET27_8,"
hexmask.long 0x00 0.--31. 1. "switching4,Test setting input"
group.long 0xF0++0x03
line.long 0x00 "RTTSET28_8,"
hexmask.long.tbyte 0x00 8.--31. 1. "switching5,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "switching4,Test setting input"
group.long 0xF4++0x03
line.long 0x00 "RTTSET29_8,"
hexmask.long.word 0x00 16.--31. 1. "switching6,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "switching5,Test setting input"
group.long 0xF8++0x03
line.long 0x00 "RTTSET30_8,"
hexmask.long.byte 0x00 24.--31. 1. "switching7,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "switching6,Test setting input"
group.long 0xFC++0x03
line.long 0x00 "RTTSET31_8,"
hexmask.long 0x00 0.--31. 1. "switching7,Test setting input"
group.long 0x100++0x03
line.long 0x00 "RTTSET32_8,"
hexmask.long 0x00 0.--31. 1. "clknum_31_0,Test setting input"
group.long 0x104++0x03
line.long 0x00 "RTTSET33_8,"
hexmask.long 0x00 0.--31. 1. "Testmat_31_0,Test setting input"
group.long 0x108++0x03
line.long 0x00 "RTTSET34_8,"
hexmask.long 0x00 0.--31. 1. "Testmat_63_32,Test setting input"
group.long 0x10C++0x03
line.long 0x00 "RTTSET35_8,"
hexmask.long 0x00 0.--31. 1. "Testmat_95_64,Test setting input"
group.long 0x110++0x03
line.long 0x00 "RTTSET36_8,"
hexmask.long 0x00 0.--31. 1. "Testmat_127_96,Test setting input"
group.long 0x114++0x03
line.long 0x00 "RTTSET37_8,"
hexmask.long 0x00 0.--31. 1. "Testmat_159_128,Test setting input"
group.long 0x118++0x03
line.long 0x00 "RTTSET38_8,"
hexmask.long 0x00 0.--31. 1. "Testmat_191_160,Test setting input"
group.long 0x11C++0x03
line.long 0x00 "RTTSET39_8,"
hexmask.long 0x00 0.--31. 1. "Testmat_223_192,Test setting input"
group.long 0x120++0x03
line.long 0x00 "RTTSET40_8,"
hexmask.long 0x00 0.--31. 1. "Testmat_255_224,Test setting input"
group.long 0x124++0x03
line.long 0x00 "RTTSET41_8,"
hexmask.long.word 0x00 18.--31. 1. "Reserved_18,Reserved The bit or field is readable only"
hexmask.long.byte 0x00 10.--17. 1. "apbsel,Test setting input"
newline
bitfld.long 0x00 6.--9. "mbsel,Test setting input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--5. "coreselect,Test setting input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x128++0x03
line.long 0x00 "RTTSET42_8,"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved The bit or field is readable only" "0,1,2,3"
hexmask.long.word 0x00 16.--29. 1. "Y_address,Test setting input"
newline
rbitfld.long 0x00 14.--15. "Reserved_14,Reserved The bit or field is readable only" "0,1,2,3"
hexmask.long.word 0x00 0.--13. 1. "X_address,Test setting input"
group.long 0x12C++0x03
line.long 0x00 "RTTSET43_8,"
rbitfld.long 0x00 31. "Reserved_31,Reserved The bit or field is readable only" "0,1"
hexmask.long.tbyte 0x00 14.--30. 1. "XY,Test setting input"
newline
hexmask.long.word 0x00 0.--13. 1. "Z_address,Test setting input"
group.long 0x130++0x03
line.long 0x00 "RTTSET44_8,"
rbitfld.long 0x00 26.--31. "Reserved_26,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x00 16.--25. 1. "scanchain,Test setting input for hardware-SCAN"
newline
hexmask.long.word 0x00 0.--15. 1. "scanpat,Test setting input for hardware-SCAN"
group.long 0x400++0x03
line.long 0x00 "PSTRSTT8,"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved"
rbitfld.long 0x00 12. "R_rst_T,BIST Redundant result" "0: pass,1: fail"
newline
rbitfld.long 0x00 11. "Reserved_11,Reserved" "0,1"
rbitfld.long 0x00 8.--10. "error_T,BIST error" "0: Pass,1: Fail,2: TimeOut,?,4: BUS error,?..."
newline
rbitfld.long 0x00 4.--7. "testnum_T,Number of tests" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 2.--3. "status_R,BIST Redundant status (Safety function)" "0: unexec,1: wait,2: exec,3: finish"
newline
rbitfld.long 0x00 0.--1. "status_T,BIST status" "0: unexec,1: wait,2: exec,3: finish"
group.long 0x440++0x03
line.long 0x00 "PSTCNT8,"
hexmask.long 0x00 0.--31. 1. "Stop,FieldBIST internal WDT (high counter) stop value"
group.long 0x444++0x03
line.long 0x00 "RTTRSTT8,When status_T in the RTTRSTT register is"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved" "0,1,2,3"
rbitfld.long 0x00 29. "IL_flag2,Runtime Test Illegal suspension flag-2" "0,1"
newline
rbitfld.long 0x00 28. "IL_flag1,Runtime Test Illegal suspension flag-1" "0,1"
rbitfld.long 0x00 27. "CONDF,Debug monitor of FieldBIST condition" "0: not response,1: responded"
newline
rbitfld.long 0x00 24.--26. "BUS_cond,Debug code of BUS condition" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 13.--23. 1. "Reserved_13,Reserved"
newline
rbitfld.long 0x00 12. "R_rst_T,BIST Redundant result (Safety function)" "0: Pass,1: Fail"
rbitfld.long 0x00 11. "Achk,Debug code of address check" "0: normal,1: warning"
newline
rbitfld.long 0x00 8.--10. "error_T,BIST error" "0: Pass,1: Fail,2: TimeOut,?,4: BUS error,?..."
rbitfld.long 0x00 4.--7. "testnum_T,Number of tests" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 2.--3. "R_status_T,BIST redundant status" "0: unexec,1: wait,2: exec,3: finish"
rbitfld.long 0x00 0.--1. "status_T,BIST status" "0: unexec,1: wait,2: exec,3: finish"
group.long 0x458++0x03
line.long 0x00 "RTTCNT8,"
hexmask.long 0x00 0.--31. 1. "Stop,WDT (high counter) stop value"
group.long 0x4A0++0x03
line.long 0x00 "SLFRVS8,"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved"
hexmask.long.tbyte 0x00 0.--19. 1. "REVERS,Expected value reverse for Self-Check SISR"
group.long 0x4A4++0x03
line.long 0x00 "SLFRST8,In case of the SLFR bits of the RTTRSTT register is 1B'1 SCNT bit returns to 1"
rbitfld.long 0x00 26.--31. "SCNT,Self-Check counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 24.--25. "STS,Self-Check status" "0: unexec,1: exec,?,3: finish"
newline
hexmask.long.tbyte 0x00 1.--23. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "STR,Self -Check Result" "0: Pass,1: Fail"
group.long 0x4C0++0x03
line.long 0x00 "ERRSET8,"
hexmask.long 0x00 3.--31. 1. "Reserved_3,Reserved"
bitfld.long 0x00 2. "DSB,Dummy set BUS-Error (set of fbc_rt_safetyerr)" "0,1"
newline
bitfld.long 0x00 1. "DST,Dummy set Time out (set of fbc_rt_overerr)" "0,1"
bitfld.long 0x00 0. "DSF,Dummy set Fail (set of fbc_rt_fail)" "0,1"
tree.end
tree "FUNCTIONAL_SAFETY_INST_8"
base ad:0xFF879000
group.long 0x00++0x03
line.long 0x00 "RTTEX9,SLFR and SLFE bit of the RTTEX are effective only when KCD bit is H'F1"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved" "0,1,2,3"
bitfld.long 0x00 29. "SLFR,Self-Check Counter Reset for field BIST activator" "0: Counter Reset,1: Counter not Reset"
newline
bitfld.long 0x00 28. "SLFE,Execution of Self-Check for Field BIST activator" "0: Not Execution of Self-Check for Field BIST,1: Execution of Self-Check for Field BIST.."
rbitfld.long 0x00 24.--27. "Reserved_24,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.byte 0x00 16.--23. 1. "KCD,Key Code H'5A: Effective execution of Run Time Test H'F1: Effective execution of Self-Check for field BIST activator"
rbitfld.long 0x00 11.--15. "Reserved_11,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "STM,Single Step Test Mode" "?,1: LBIST,2: MBIST,3: SCAN,?..."
bitfld.long 0x00 6.--7. "INTM,Interrupt mask" "0: non mask *1,?,2: Only at the time of the fail(fba_rt_finish are,?..."
newline
bitfld.long 0x00 5. "SSZ,SCAN Pattern size Valid only when STM=011" "0: 32bit mode,1: 16bit mode"
bitfld.long 0x00 4. "TR,Select the value of the timer" "0: ROM,1: register"
newline
bitfld.long 0x00 3. "WM,Wfi mask" "0: not mask,1: mask"
bitfld.long 0x00 2. "TM,Mask the judgment of timer" "0: not mask,1: mask"
newline
bitfld.long 0x00 1. "STP,Single Step Mode" "0: ROM batch mode,1: Single Step Mode"
bitfld.long 0x00 0. "EX,Execution of Runtime Test" "0: Not Execution of Runtime Test,1: Execution of Runtime Test"
group.long 0x04++0x03
line.long 0x00 "RTTMI19,"
rbitfld.long 0x00 27.--31. "Reserved_27,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 24.--26. "RPROT,Protection type of MEMORY" "0: Unprivileged access,1: Privileged access,?..."
newline
hexmask.long.byte 0x00 16.--23. 1. "MADDR_upper,Memory upper address[39:32] that stores the SCAN pattern"
hexmask.long.word 0x00 0.--15. 1. "MUNIT,Number of units (1 unit = 128 Byte)"
group.long 0x08++0x03
line.long 0x00 "RTTMI29,"
hexmask.long 0x00 0.--31. 1. "MADDR,Memory address that stores the SCAN pattern"
group.long 0x0C++0x03
line.long 0x00 "RTTSISR19,"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved"
hexmask.long.tbyte 0x00 0.--19. 1. "SISR1,SISR-TEST#1 Expected value"
group.long 0x14++0x03
line.long 0x00 "RTTUC9,"
hexmask.long 0x00 0.--31. 1. "U_WDT,Upper counter of Watchdog Timer"
group.long 0x18++0x03
line.long 0x00 "RTTDC9,"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved"
hexmask.long.word 0x00 0.--15. 1. "L_WDT,Lower counter of Watchdog Timer"
group.long 0x80++0x03
line.long 0x00 "RTTSET0_9,"
hexmask.long 0x00 0.--31. 1. "test_clock,Test setting input"
group.long 0x84++0x03
line.long 0x00 "RTTSET1_9,"
hexmask.long 0x00 2.--31. 1. "Reserved_2,Reserved"
bitfld.long 0x00 1. "reset,Test setting input" "0: Reset test disabled,1: Reset test enabled"
newline
bitfld.long 0x00 0. "tt,Test setting input" "0: Selected other clock,1: Selected test clock for test Domain"
group.long 0x88++0x03
line.long 0x00 "RTTSET2_9,"
hexmask.long 0x00 0.--31. 1. "hold0,Test setting input"
group.long 0x8C++0x03
line.long 0x00 "RTTSET3_9,"
hexmask.long.tbyte 0x00 8.--31. 1. "hold1,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "hold0,Test setting input"
group.long 0x90++0x03
line.long 0x00 "RTTSET4_9,"
hexmask.long.word 0x00 16.--31. 1. "hold2,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "hold1,Test setting input"
group.long 0x94++0x03
line.long 0x00 "RTTSET5_9,"
hexmask.long.byte 0x00 24.--31. 1. "hold3,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "hold2,Test setting input"
group.long 0x98++0x03
line.long 0x00 "RTTSET6_9,"
hexmask.long 0x00 0.--31. 1. "hold3,Test setting input"
group.long 0x9C++0x03
line.long 0x00 "RTTSET7_9,"
hexmask.long 0x00 0.--31. 1. "toggle0,Test setting input"
group.long 0xA0++0x03
line.long 0x00 "RTTSET8_9,"
hexmask.long.tbyte 0x00 8.--31. 1. "toggle1,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "toggle0,Test setting input"
group.long 0xA4++0x03
line.long 0x00 "RTTSET9_9,"
hexmask.long.word 0x00 16.--31. 1. "toggle2,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "toggle1,Test setting input"
group.long 0xA8++0x03
line.long 0x00 "RTTSET10_9,"
hexmask.long.byte 0x00 24.--31. 1. "toggle3,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "toggle2,Test setting input"
group.long 0xAC++0x03
line.long 0x00 "RTTSET11_9,"
hexmask.long 0x00 0.--31. 1. "toggle3,Test setting input"
group.long 0xB0++0x03
line.long 0x00 "RTTSET12_9,"
hexmask.long 0x00 0.--31. 1. "switching0,Test setting input"
group.long 0xB4++0x03
line.long 0x00 "RTTSET13_9,"
hexmask.long.tbyte 0x00 8.--31. 1. "switching1,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "switching0,Test setting input"
group.long 0xB8++0x03
line.long 0x00 "RTTSET14_9,"
hexmask.long.word 0x00 16.--31. 1. "switching2,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "switching1,Test setting input"
group.long 0xBC++0x03
line.long 0x00 "RTTSET15_9,"
hexmask.long.byte 0x00 24.--31. 1. "switching3,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "switching2,Test setting input"
group.long 0xC0++0x03
line.long 0x00 "RTTSET16_9,"
hexmask.long 0x00 0.--31. 1. "switching3,Test setting input"
group.long 0xC4++0x03
line.long 0x00 "RTTSET17_9,"
hexmask.long 0x00 0.--31. 1. "hold4,Test setting input"
group.long 0xC8++0x03
line.long 0x00 "RTTSET18_9,"
hexmask.long.tbyte 0x00 8.--31. 1. "hold5,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "hold4,Test setting input"
group.long 0xCC++0x03
line.long 0x00 "RTTSET19_9,"
hexmask.long.word 0x00 16.--31. 1. "hold6,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "hold5,Test setting input"
group.long 0xD0++0x03
line.long 0x00 "RTTSET20_9,"
hexmask.long.byte 0x00 24.--31. 1. "hold7,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "hold6,Test setting input"
group.long 0xD4++0x03
line.long 0x00 "RTTSET21_9,"
hexmask.long 0x00 0.--31. 1. "hold7,Test setting input"
group.long 0xD8++0x03
line.long 0x00 "RTTSET22_9,"
hexmask.long 0x00 0.--31. 1. "toggle4,Test setting input"
group.long 0xDC++0x03
line.long 0x00 "RTTSET23_9,"
hexmask.long.tbyte 0x00 8.--31. 1. "toggle5,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "toggle4,Test setting input"
group.long 0xE0++0x03
line.long 0x00 "RTTSET24_9,"
hexmask.long.word 0x00 16.--31. 1. "toggle6,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "toggle5,Test setting input"
group.long 0xE4++0x03
line.long 0x00 "RTTSET25_9,"
hexmask.long.byte 0x00 24.--31. 1. "toggle7,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "toggle6,Test setting input"
group.long 0xE8++0x03
line.long 0x00 "RTTSET26_9,"
hexmask.long 0x00 0.--31. 1. "toggle7,Test setting input"
group.long 0xEC++0x03
line.long 0x00 "RTTSET27_9,"
hexmask.long 0x00 0.--31. 1. "switching4,Test setting input"
group.long 0xF0++0x03
line.long 0x00 "RTTSET28_9,"
hexmask.long.tbyte 0x00 8.--31. 1. "switching5,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "switching4,Test setting input"
group.long 0xF4++0x03
line.long 0x00 "RTTSET29_9,"
hexmask.long.word 0x00 16.--31. 1. "switching6,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "switching5,Test setting input"
group.long 0xF8++0x03
line.long 0x00 "RTTSET30_9,"
hexmask.long.byte 0x00 24.--31. 1. "switching7,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "switching6,Test setting input"
group.long 0xFC++0x03
line.long 0x00 "RTTSET31_9,"
hexmask.long 0x00 0.--31. 1. "switching7,Test setting input"
group.long 0x100++0x03
line.long 0x00 "RTTSET32_9,"
hexmask.long 0x00 0.--31. 1. "clknum_31_0,Test setting input"
group.long 0x104++0x03
line.long 0x00 "RTTSET33_9,"
hexmask.long 0x00 0.--31. 1. "Testmat_31_0,Test setting input"
group.long 0x108++0x03
line.long 0x00 "RTTSET34_9,"
hexmask.long 0x00 0.--31. 1. "Testmat_63_32,Test setting input"
group.long 0x10C++0x03
line.long 0x00 "RTTSET35_9,"
hexmask.long 0x00 0.--31. 1. "Testmat_95_64,Test setting input"
group.long 0x110++0x03
line.long 0x00 "RTTSET36_9,"
hexmask.long 0x00 0.--31. 1. "Testmat_127_96,Test setting input"
group.long 0x114++0x03
line.long 0x00 "RTTSET37_9,"
hexmask.long 0x00 0.--31. 1. "Testmat_159_128,Test setting input"
group.long 0x118++0x03
line.long 0x00 "RTTSET38_9,"
hexmask.long 0x00 0.--31. 1. "Testmat_191_160,Test setting input"
group.long 0x11C++0x03
line.long 0x00 "RTTSET39_9,"
hexmask.long 0x00 0.--31. 1. "Testmat_223_192,Test setting input"
group.long 0x120++0x03
line.long 0x00 "RTTSET40_9,"
hexmask.long 0x00 0.--31. 1. "Testmat_255_224,Test setting input"
group.long 0x124++0x03
line.long 0x00 "RTTSET41_9,"
hexmask.long.word 0x00 18.--31. 1. "Reserved_18,Reserved The bit or field is readable only"
hexmask.long.byte 0x00 10.--17. 1. "apbsel,Test setting input"
newline
bitfld.long 0x00 6.--9. "mbsel,Test setting input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--5. "coreselect,Test setting input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x128++0x03
line.long 0x00 "RTTSET42_9,"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved The bit or field is readable only" "0,1,2,3"
hexmask.long.word 0x00 16.--29. 1. "Y_address,Test setting input"
newline
rbitfld.long 0x00 14.--15. "Reserved_14,Reserved The bit or field is readable only" "0,1,2,3"
hexmask.long.word 0x00 0.--13. 1. "X_address,Test setting input"
group.long 0x12C++0x03
line.long 0x00 "RTTSET43_9,"
rbitfld.long 0x00 31. "Reserved_31,Reserved The bit or field is readable only" "0,1"
hexmask.long.tbyte 0x00 14.--30. 1. "XY,Test setting input"
newline
hexmask.long.word 0x00 0.--13. 1. "Z_address,Test setting input"
group.long 0x130++0x03
line.long 0x00 "RTTSET44_9,"
rbitfld.long 0x00 26.--31. "Reserved_26,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x00 16.--25. 1. "scanchain,Test setting input for hardware-SCAN"
newline
hexmask.long.word 0x00 0.--15. 1. "scanpat,Test setting input for hardware-SCAN"
group.long 0x400++0x03
line.long 0x00 "PSTRSTT9,"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved"
rbitfld.long 0x00 12. "R_rst_T,BIST Redundant result" "0: pass,1: fail"
newline
rbitfld.long 0x00 11. "Reserved_11,Reserved" "0,1"
rbitfld.long 0x00 8.--10. "error_T,BIST error" "0: Pass,1: Fail,2: TimeOut,?,4: BUS error,?..."
newline
rbitfld.long 0x00 4.--7. "testnum_T,Number of tests" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 2.--3. "status_R,BIST Redundant status (Safety function)" "0: unexec,1: wait,2: exec,3: finish"
newline
rbitfld.long 0x00 0.--1. "status_T,BIST status" "0: unexec,1: wait,2: exec,3: finish"
group.long 0x440++0x03
line.long 0x00 "PSTCNT9,"
hexmask.long 0x00 0.--31. 1. "Stop,FieldBIST internal WDT (high counter) stop value"
group.long 0x444++0x03
line.long 0x00 "RTTRSTT9,When status_T in the RTTRSTT register is"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved" "0,1,2,3"
rbitfld.long 0x00 29. "IL_flag2,Runtime Test Illegal suspension flag-2" "0,1"
newline
rbitfld.long 0x00 28. "IL_flag1,Runtime Test Illegal suspension flag-1" "0,1"
rbitfld.long 0x00 27. "CONDF,Debug monitor of FieldBIST condition" "0: not response,1: responded"
newline
rbitfld.long 0x00 24.--26. "BUS_cond,Debug code of BUS condition" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 13.--23. 1. "Reserved_13,Reserved"
newline
rbitfld.long 0x00 12. "R_rst_T,BIST Redundant result (Safety function)" "0: Pass,1: Fail"
rbitfld.long 0x00 11. "Achk,Debug code of address check" "0: normal,1: warning"
newline
rbitfld.long 0x00 8.--10. "error_T,BIST error" "0: Pass,1: Fail,2: TimeOut,?,4: BUS error,?..."
rbitfld.long 0x00 4.--7. "testnum_T,Number of tests" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 2.--3. "R_status_T,BIST redundant status" "0: unexec,1: wait,2: exec,3: finish"
rbitfld.long 0x00 0.--1. "status_T,BIST status" "0: unexec,1: wait,2: exec,3: finish"
group.long 0x458++0x03
line.long 0x00 "RTTCNT9,"
hexmask.long 0x00 0.--31. 1. "Stop,WDT (high counter) stop value"
group.long 0x4A0++0x03
line.long 0x00 "SLFRVS9,"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved"
hexmask.long.tbyte 0x00 0.--19. 1. "REVERS,Expected value reverse for Self-Check SISR"
group.long 0x4A4++0x03
line.long 0x00 "SLFRST9,In case of the SLFR bits of the RTTRSTT register is 1B'1 SCNT bit returns to 1"
rbitfld.long 0x00 26.--31. "SCNT,Self-Check counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 24.--25. "STS,Self-Check status" "0: unexec,1: exec,?,3: finish"
newline
hexmask.long.tbyte 0x00 1.--23. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "STR,Self -Check Result" "0: Pass,1: Fail"
group.long 0x4C0++0x03
line.long 0x00 "ERRSET9,"
hexmask.long 0x00 3.--31. 1. "Reserved_3,Reserved"
bitfld.long 0x00 2. "DSB,Dummy set BUS-Error (set of fbc_rt_safetyerr)" "0,1"
newline
bitfld.long 0x00 1. "DST,Dummy set Time out (set of fbc_rt_overerr)" "0,1"
bitfld.long 0x00 0. "DSF,Dummy set Fail (set of fbc_rt_fail)" "0,1"
tree.end
tree "FUNCTIONAL_SAFETY_INST_9"
base ad:0xFF870000
group.long 0x00++0x03
line.long 0x00 "RTTEX10,SLFR and SLFE bit of the RTTEX are effective only when KCD bit is H'F1"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved" "0,1,2,3"
bitfld.long 0x00 29. "SLFR,Self-Check Counter Reset for field BIST activator" "0: Counter Reset,1: Counter not Reset"
newline
bitfld.long 0x00 28. "SLFE,Execution of Self-Check for Field BIST activator" "0: Not Execution of Self-Check for Field BIST,1: Execution of Self-Check for Field BIST.."
rbitfld.long 0x00 24.--27. "Reserved_24,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.byte 0x00 16.--23. 1. "KCD,Key Code H'5A: Effective execution of Run Time Test H'F1: Effective execution of Self-Check for field BIST activator"
rbitfld.long 0x00 11.--15. "Reserved_11,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "STM,Single Step Test Mode" "?,1: LBIST,2: MBIST,3: SCAN,?..."
bitfld.long 0x00 6.--7. "INTM,Interrupt mask" "0: non mask *1,?,2: Only at the time of the fail(fba_rt_finish are,?..."
newline
bitfld.long 0x00 5. "SSZ,SCAN Pattern size Valid only when STM=011" "0: 32bit mode,1: 16bit mode"
bitfld.long 0x00 4. "TR,Select the value of the timer" "0: ROM,1: register"
newline
bitfld.long 0x00 3. "WM,Wfi mask" "0: not mask,1: mask"
bitfld.long 0x00 2. "TM,Mask the judgment of timer" "0: not mask,1: mask"
newline
bitfld.long 0x00 1. "STP,Single Step Mode" "0: ROM batch mode,1: Single Step Mode"
bitfld.long 0x00 0. "EX,Execution of Runtime Test" "0: Not Execution of Runtime Test,1: Execution of Runtime Test"
group.long 0x04++0x03
line.long 0x00 "RTTMI110,"
rbitfld.long 0x00 27.--31. "Reserved_27,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 24.--26. "RPROT,Protection type of MEMORY" "0: Unprivileged access,1: Privileged access,?..."
newline
hexmask.long.byte 0x00 16.--23. 1. "MADDR_upper,Memory upper address[39:32] that stores the SCAN pattern"
hexmask.long.word 0x00 0.--15. 1. "MUNIT,Number of units (1 unit = 128 Byte)"
group.long 0x08++0x03
line.long 0x00 "RTTMI210,"
hexmask.long 0x00 0.--31. 1. "MADDR,Memory address that stores the SCAN pattern"
group.long 0x0C++0x03
line.long 0x00 "RTTSISR110,"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved"
hexmask.long.tbyte 0x00 0.--19. 1. "SISR1,SISR-TEST#1 Expected value"
group.long 0x14++0x03
line.long 0x00 "RTTUC10,"
hexmask.long 0x00 0.--31. 1. "U_WDT,Upper counter of Watchdog Timer"
group.long 0x18++0x03
line.long 0x00 "RTTDC10,"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved"
hexmask.long.word 0x00 0.--15. 1. "L_WDT,Lower counter of Watchdog Timer"
group.long 0x80++0x03
line.long 0x00 "RTTSET0_10,"
hexmask.long 0x00 0.--31. 1. "test_clock,Test setting input"
group.long 0x84++0x03
line.long 0x00 "RTTSET1_10,"
hexmask.long 0x00 2.--31. 1. "Reserved_2,Reserved"
bitfld.long 0x00 1. "reset,Test setting input" "0: Reset test disabled,1: Reset test enabled"
newline
bitfld.long 0x00 0. "tt,Test setting input" "0: Selected other clock,1: Selected test clock for test Domain"
group.long 0x88++0x03
line.long 0x00 "RTTSET2_10,"
hexmask.long 0x00 0.--31. 1. "hold0,Test setting input"
group.long 0x8C++0x03
line.long 0x00 "RTTSET3_10,"
hexmask.long.tbyte 0x00 8.--31. 1. "hold1,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "hold0,Test setting input"
group.long 0x90++0x03
line.long 0x00 "RTTSET4_10,"
hexmask.long.word 0x00 16.--31. 1. "hold2,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "hold1,Test setting input"
group.long 0x94++0x03
line.long 0x00 "RTTSET5_10,"
hexmask.long.byte 0x00 24.--31. 1. "hold3,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "hold2,Test setting input"
group.long 0x98++0x03
line.long 0x00 "RTTSET6_10,"
hexmask.long 0x00 0.--31. 1. "hold3,Test setting input"
group.long 0x9C++0x03
line.long 0x00 "RTTSET7_10,"
hexmask.long 0x00 0.--31. 1. "toggle0,Test setting input"
group.long 0xA0++0x03
line.long 0x00 "RTTSET8_10,"
hexmask.long.tbyte 0x00 8.--31. 1. "toggle1,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "toggle0,Test setting input"
group.long 0xA4++0x03
line.long 0x00 "RTTSET9_10,"
hexmask.long.word 0x00 16.--31. 1. "toggle2,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "toggle1,Test setting input"
group.long 0xA8++0x03
line.long 0x00 "RTTSET10_10,"
hexmask.long.byte 0x00 24.--31. 1. "toggle3,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "toggle2,Test setting input"
group.long 0xAC++0x03
line.long 0x00 "RTTSET11_10,"
hexmask.long 0x00 0.--31. 1. "toggle3,Test setting input"
group.long 0xB0++0x03
line.long 0x00 "RTTSET12_10,"
hexmask.long 0x00 0.--31. 1. "switching0,Test setting input"
group.long 0xB4++0x03
line.long 0x00 "RTTSET13_10,"
hexmask.long.tbyte 0x00 8.--31. 1. "switching1,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "switching0,Test setting input"
group.long 0xB8++0x03
line.long 0x00 "RTTSET14_10,"
hexmask.long.word 0x00 16.--31. 1. "switching2,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "switching1,Test setting input"
group.long 0xBC++0x03
line.long 0x00 "RTTSET15_10,"
hexmask.long.byte 0x00 24.--31. 1. "switching3,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "switching2,Test setting input"
group.long 0xC0++0x03
line.long 0x00 "RTTSET16_10,"
hexmask.long 0x00 0.--31. 1. "switching3,Test setting input"
group.long 0xC4++0x03
line.long 0x00 "RTTSET17_10,"
hexmask.long 0x00 0.--31. 1. "hold4,Test setting input"
group.long 0xC8++0x03
line.long 0x00 "RTTSET18_10,"
hexmask.long.tbyte 0x00 8.--31. 1. "hold5,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "hold4,Test setting input"
group.long 0xCC++0x03
line.long 0x00 "RTTSET19_10,"
hexmask.long.word 0x00 16.--31. 1. "hold6,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "hold5,Test setting input"
group.long 0xD0++0x03
line.long 0x00 "RTTSET20_10,"
hexmask.long.byte 0x00 24.--31. 1. "hold7,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "hold6,Test setting input"
group.long 0xD4++0x03
line.long 0x00 "RTTSET21_10,"
hexmask.long 0x00 0.--31. 1. "hold7,Test setting input"
group.long 0xD8++0x03
line.long 0x00 "RTTSET22_10,"
hexmask.long 0x00 0.--31. 1. "toggle4,Test setting input"
group.long 0xDC++0x03
line.long 0x00 "RTTSET23_10,"
hexmask.long.tbyte 0x00 8.--31. 1. "toggle5,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "toggle4,Test setting input"
group.long 0xE0++0x03
line.long 0x00 "RTTSET24_10,"
hexmask.long.word 0x00 16.--31. 1. "toggle6,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "toggle5,Test setting input"
group.long 0xE4++0x03
line.long 0x00 "RTTSET25_10,"
hexmask.long.byte 0x00 24.--31. 1. "toggle7,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "toggle6,Test setting input"
group.long 0xE8++0x03
line.long 0x00 "RTTSET26_10,"
hexmask.long 0x00 0.--31. 1. "toggle7,Test setting input"
group.long 0xEC++0x03
line.long 0x00 "RTTSET27_10,"
hexmask.long 0x00 0.--31. 1. "switching4,Test setting input"
group.long 0xF0++0x03
line.long 0x00 "RTTSET28_10,"
hexmask.long.tbyte 0x00 8.--31. 1. "switching5,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "switching4,Test setting input"
group.long 0xF4++0x03
line.long 0x00 "RTTSET29_10,"
hexmask.long.word 0x00 16.--31. 1. "switching6,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "switching5,Test setting input"
group.long 0xF8++0x03
line.long 0x00 "RTTSET30_10,"
hexmask.long.byte 0x00 24.--31. 1. "switching7,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "switching6,Test setting input"
group.long 0xFC++0x03
line.long 0x00 "RTTSET31_10,"
hexmask.long 0x00 0.--31. 1. "switching7,Test setting input"
group.long 0x100++0x03
line.long 0x00 "RTTSET32_10,"
hexmask.long 0x00 0.--31. 1. "clknum_31_0,Test setting input"
group.long 0x104++0x03
line.long 0x00 "RTTSET33_10,"
hexmask.long 0x00 0.--31. 1. "Testmat_31_0,Test setting input"
group.long 0x108++0x03
line.long 0x00 "RTTSET34_10,"
hexmask.long 0x00 0.--31. 1. "Testmat_63_32,Test setting input"
group.long 0x10C++0x03
line.long 0x00 "RTTSET35_10,"
hexmask.long 0x00 0.--31. 1. "Testmat_95_64,Test setting input"
group.long 0x110++0x03
line.long 0x00 "RTTSET36_10,"
hexmask.long 0x00 0.--31. 1. "Testmat_127_96,Test setting input"
group.long 0x114++0x03
line.long 0x00 "RTTSET37_10,"
hexmask.long 0x00 0.--31. 1. "Testmat_159_128,Test setting input"
group.long 0x118++0x03
line.long 0x00 "RTTSET38_10,"
hexmask.long 0x00 0.--31. 1. "Testmat_191_160,Test setting input"
group.long 0x11C++0x03
line.long 0x00 "RTTSET39_10,"
hexmask.long 0x00 0.--31. 1. "Testmat_223_192,Test setting input"
group.long 0x120++0x03
line.long 0x00 "RTTSET40_10,"
hexmask.long 0x00 0.--31. 1. "Testmat_255_224,Test setting input"
group.long 0x124++0x03
line.long 0x00 "RTTSET41_10,"
hexmask.long.word 0x00 18.--31. 1. "Reserved_18,Reserved The bit or field is readable only"
hexmask.long.byte 0x00 10.--17. 1. "apbsel,Test setting input"
newline
bitfld.long 0x00 6.--9. "mbsel,Test setting input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--5. "coreselect,Test setting input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x128++0x03
line.long 0x00 "RTTSET42_10,"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved The bit or field is readable only" "0,1,2,3"
hexmask.long.word 0x00 16.--29. 1. "Y_address,Test setting input"
newline
rbitfld.long 0x00 14.--15. "Reserved_14,Reserved The bit or field is readable only" "0,1,2,3"
hexmask.long.word 0x00 0.--13. 1. "X_address,Test setting input"
group.long 0x12C++0x03
line.long 0x00 "RTTSET43_10,"
rbitfld.long 0x00 31. "Reserved_31,Reserved The bit or field is readable only" "0,1"
hexmask.long.tbyte 0x00 14.--30. 1. "XY,Test setting input"
newline
hexmask.long.word 0x00 0.--13. 1. "Z_address,Test setting input"
group.long 0x130++0x03
line.long 0x00 "RTTSET44_10,"
rbitfld.long 0x00 26.--31. "Reserved_26,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x00 16.--25. 1. "scanchain,Test setting input for hardware-SCAN"
newline
hexmask.long.word 0x00 0.--15. 1. "scanpat,Test setting input for hardware-SCAN"
group.long 0x400++0x03
line.long 0x00 "PSTRSTT10,"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved"
rbitfld.long 0x00 12. "R_rst_T,BIST Redundant result" "0: pass,1: fail"
newline
rbitfld.long 0x00 11. "Reserved_11,Reserved" "0,1"
rbitfld.long 0x00 8.--10. "error_T,BIST error" "0: Pass,1: Fail,2: TimeOut,?,4: BUS error,?..."
newline
rbitfld.long 0x00 4.--7. "testnum_T,Number of tests" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 2.--3. "status_R,BIST Redundant status (Safety function)" "0: unexec,1: wait,2: exec,3: finish"
newline
rbitfld.long 0x00 0.--1. "status_T,BIST status" "0: unexec,1: wait,2: exec,3: finish"
group.long 0x440++0x03
line.long 0x00 "PSTCNT10,"
hexmask.long 0x00 0.--31. 1. "Stop,FieldBIST internal WDT (high counter) stop value"
group.long 0x444++0x03
line.long 0x00 "RTTRSTT10,When status_T in the RTTRSTT register is"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved" "0,1,2,3"
rbitfld.long 0x00 29. "IL_flag2,Runtime Test Illegal suspension flag-2" "0,1"
newline
rbitfld.long 0x00 28. "IL_flag1,Runtime Test Illegal suspension flag-1" "0,1"
rbitfld.long 0x00 27. "CONDF,Debug monitor of FieldBIST condition" "0: not response,1: responded"
newline
rbitfld.long 0x00 24.--26. "BUS_cond,Debug code of BUS condition" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 13.--23. 1. "Reserved_13,Reserved"
newline
rbitfld.long 0x00 12. "R_rst_T,BIST Redundant result (Safety function)" "0: Pass,1: Fail"
rbitfld.long 0x00 11. "Achk,Debug code of address check" "0: normal,1: warning"
newline
rbitfld.long 0x00 8.--10. "error_T,BIST error" "0: Pass,1: Fail,2: TimeOut,?,4: BUS error,?..."
rbitfld.long 0x00 4.--7. "testnum_T,Number of tests" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 2.--3. "R_status_T,BIST redundant status" "0: unexec,1: wait,2: exec,3: finish"
rbitfld.long 0x00 0.--1. "status_T,BIST status" "0: unexec,1: wait,2: exec,3: finish"
group.long 0x458++0x03
line.long 0x00 "RTTCNT10,"
hexmask.long 0x00 0.--31. 1. "Stop,WDT (high counter) stop value"
group.long 0x4A0++0x03
line.long 0x00 "SLFRVS10,"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved"
hexmask.long.tbyte 0x00 0.--19. 1. "REVERS,Expected value reverse for Self-Check SISR"
group.long 0x4A4++0x03
line.long 0x00 "SLFRST10,In case of the SLFR bits of the RTTRSTT register is 1B'1 SCNT bit returns to 1"
rbitfld.long 0x00 26.--31. "SCNT,Self-Check counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 24.--25. "STS,Self-Check status" "0: unexec,1: exec,?,3: finish"
newline
hexmask.long.tbyte 0x00 1.--23. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "STR,Self -Check Result" "0: Pass,1: Fail"
group.long 0x4C0++0x03
line.long 0x00 "ERRSET10,"
hexmask.long 0x00 3.--31. 1. "Reserved_3,Reserved"
bitfld.long 0x00 2. "DSB,Dummy set BUS-Error (set of fbc_rt_safetyerr)" "0,1"
newline
bitfld.long 0x00 1. "DST,Dummy set Time out (set of fbc_rt_overerr)" "0,1"
bitfld.long 0x00 0. "DSF,Dummy set Fail (set of fbc_rt_fail)" "0,1"
tree.end
tree "FUNCTIONAL_SAFETY_INST_10"
base ad:0xFF872000
group.long 0x00++0x03
line.long 0x00 "RTTEX11,SLFR and SLFE bit of the RTTEX are effective only when KCD bit is H'F1"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved" "0,1,2,3"
bitfld.long 0x00 29. "SLFR,Self-Check Counter Reset for field BIST activator" "0: Counter Reset,1: Counter not Reset"
newline
bitfld.long 0x00 28. "SLFE,Execution of Self-Check for Field BIST activator" "0: Not Execution of Self-Check for Field BIST,1: Execution of Self-Check for Field BIST.."
rbitfld.long 0x00 24.--27. "Reserved_24,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.byte 0x00 16.--23. 1. "KCD,Key Code H'5A: Effective execution of Run Time Test H'F1: Effective execution of Self-Check for field BIST activator"
rbitfld.long 0x00 11.--15. "Reserved_11,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "STM,Single Step Test Mode" "?,1: LBIST,2: MBIST,3: SCAN,?..."
bitfld.long 0x00 6.--7. "INTM,Interrupt mask" "0: non mask *1,?,2: Only at the time of the fail(fba_rt_finish are,?..."
newline
bitfld.long 0x00 5. "SSZ,SCAN Pattern size Valid only when STM=011" "0: 32bit mode,1: 16bit mode"
bitfld.long 0x00 4. "TR,Select the value of the timer" "0: ROM,1: register"
newline
bitfld.long 0x00 3. "WM,Wfi mask" "0: not mask,1: mask"
bitfld.long 0x00 2. "TM,Mask the judgment of timer" "0: not mask,1: mask"
newline
bitfld.long 0x00 1. "STP,Single Step Mode" "0: ROM batch mode,1: Single Step Mode"
bitfld.long 0x00 0. "EX,Execution of Runtime Test" "0: Not Execution of Runtime Test,1: Execution of Runtime Test"
group.long 0x04++0x03
line.long 0x00 "RTTMI111,"
rbitfld.long 0x00 27.--31. "Reserved_27,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 24.--26. "RPROT,Protection type of MEMORY" "0: Unprivileged access,1: Privileged access,?..."
newline
hexmask.long.byte 0x00 16.--23. 1. "MADDR_upper,Memory upper address[39:32] that stores the SCAN pattern"
hexmask.long.word 0x00 0.--15. 1. "MUNIT,Number of units (1 unit = 128 Byte)"
group.long 0x08++0x03
line.long 0x00 "RTTMI211,"
hexmask.long 0x00 0.--31. 1. "MADDR,Memory address that stores the SCAN pattern"
group.long 0x0C++0x03
line.long 0x00 "RTTSISR111,"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved"
hexmask.long.tbyte 0x00 0.--19. 1. "SISR1,SISR-TEST#1 Expected value"
group.long 0x14++0x03
line.long 0x00 "RTTUC11,"
hexmask.long 0x00 0.--31. 1. "U_WDT,Upper counter of Watchdog Timer"
group.long 0x18++0x03
line.long 0x00 "RTTDC11,"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved"
hexmask.long.word 0x00 0.--15. 1. "L_WDT,Lower counter of Watchdog Timer"
group.long 0x80++0x03
line.long 0x00 "RTTSET0_11,"
hexmask.long 0x00 0.--31. 1. "test_clock,Test setting input"
group.long 0x84++0x03
line.long 0x00 "RTTSET1_11,"
hexmask.long 0x00 2.--31. 1. "Reserved_2,Reserved"
bitfld.long 0x00 1. "reset,Test setting input" "0: Reset test disabled,1: Reset test enabled"
newline
bitfld.long 0x00 0. "tt,Test setting input" "0: Selected other clock,1: Selected test clock for test Domain"
group.long 0x88++0x03
line.long 0x00 "RTTSET2_11,"
hexmask.long 0x00 0.--31. 1. "hold0,Test setting input"
group.long 0x8C++0x03
line.long 0x00 "RTTSET3_11,"
hexmask.long.tbyte 0x00 8.--31. 1. "hold1,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "hold0,Test setting input"
group.long 0x90++0x03
line.long 0x00 "RTTSET4_11,"
hexmask.long.word 0x00 16.--31. 1. "hold2,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "hold1,Test setting input"
group.long 0x94++0x03
line.long 0x00 "RTTSET5_11,"
hexmask.long.byte 0x00 24.--31. 1. "hold3,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "hold2,Test setting input"
group.long 0x98++0x03
line.long 0x00 "RTTSET6_11,"
hexmask.long 0x00 0.--31. 1. "hold3,Test setting input"
group.long 0x9C++0x03
line.long 0x00 "RTTSET7_11,"
hexmask.long 0x00 0.--31. 1. "toggle0,Test setting input"
group.long 0xA0++0x03
line.long 0x00 "RTTSET8_11,"
hexmask.long.tbyte 0x00 8.--31. 1. "toggle1,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "toggle0,Test setting input"
group.long 0xA4++0x03
line.long 0x00 "RTTSET9_11,"
hexmask.long.word 0x00 16.--31. 1. "toggle2,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "toggle1,Test setting input"
group.long 0xA8++0x03
line.long 0x00 "RTTSET10_11,"
hexmask.long.byte 0x00 24.--31. 1. "toggle3,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "toggle2,Test setting input"
group.long 0xAC++0x03
line.long 0x00 "RTTSET11_11,"
hexmask.long 0x00 0.--31. 1. "toggle3,Test setting input"
group.long 0xB0++0x03
line.long 0x00 "RTTSET12_11,"
hexmask.long 0x00 0.--31. 1. "switching0,Test setting input"
group.long 0xB4++0x03
line.long 0x00 "RTTSET13_11,"
hexmask.long.tbyte 0x00 8.--31. 1. "switching1,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "switching0,Test setting input"
group.long 0xB8++0x03
line.long 0x00 "RTTSET14_11,"
hexmask.long.word 0x00 16.--31. 1. "switching2,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "switching1,Test setting input"
group.long 0xBC++0x03
line.long 0x00 "RTTSET15_11,"
hexmask.long.byte 0x00 24.--31. 1. "switching3,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "switching2,Test setting input"
group.long 0xC0++0x03
line.long 0x00 "RTTSET16_11,"
hexmask.long 0x00 0.--31. 1. "switching3,Test setting input"
group.long 0xC4++0x03
line.long 0x00 "RTTSET17_11,"
hexmask.long 0x00 0.--31. 1. "hold4,Test setting input"
group.long 0xC8++0x03
line.long 0x00 "RTTSET18_11,"
hexmask.long.tbyte 0x00 8.--31. 1. "hold5,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "hold4,Test setting input"
group.long 0xCC++0x03
line.long 0x00 "RTTSET19_11,"
hexmask.long.word 0x00 16.--31. 1. "hold6,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "hold5,Test setting input"
group.long 0xD0++0x03
line.long 0x00 "RTTSET20_11,"
hexmask.long.byte 0x00 24.--31. 1. "hold7,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "hold6,Test setting input"
group.long 0xD4++0x03
line.long 0x00 "RTTSET21_11,"
hexmask.long 0x00 0.--31. 1. "hold7,Test setting input"
group.long 0xD8++0x03
line.long 0x00 "RTTSET22_11,"
hexmask.long 0x00 0.--31. 1. "toggle4,Test setting input"
group.long 0xDC++0x03
line.long 0x00 "RTTSET23_11,"
hexmask.long.tbyte 0x00 8.--31. 1. "toggle5,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "toggle4,Test setting input"
group.long 0xE0++0x03
line.long 0x00 "RTTSET24_11,"
hexmask.long.word 0x00 16.--31. 1. "toggle6,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "toggle5,Test setting input"
group.long 0xE4++0x03
line.long 0x00 "RTTSET25_11,"
hexmask.long.byte 0x00 24.--31. 1. "toggle7,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "toggle6,Test setting input"
group.long 0xE8++0x03
line.long 0x00 "RTTSET26_11,"
hexmask.long 0x00 0.--31. 1. "toggle7,Test setting input"
group.long 0xEC++0x03
line.long 0x00 "RTTSET27_11,"
hexmask.long 0x00 0.--31. 1. "switching4,Test setting input"
group.long 0xF0++0x03
line.long 0x00 "RTTSET28_11,"
hexmask.long.tbyte 0x00 8.--31. 1. "switching5,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "switching4,Test setting input"
group.long 0xF4++0x03
line.long 0x00 "RTTSET29_11,"
hexmask.long.word 0x00 16.--31. 1. "switching6,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "switching5,Test setting input"
group.long 0xF8++0x03
line.long 0x00 "RTTSET30_11,"
hexmask.long.byte 0x00 24.--31. 1. "switching7,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "switching6,Test setting input"
group.long 0xFC++0x03
line.long 0x00 "RTTSET31_11,"
hexmask.long 0x00 0.--31. 1. "switching7,Test setting input"
group.long 0x100++0x03
line.long 0x00 "RTTSET32_11,"
hexmask.long 0x00 0.--31. 1. "clknum_31_0,Test setting input"
group.long 0x104++0x03
line.long 0x00 "RTTSET33_11,"
hexmask.long 0x00 0.--31. 1. "Testmat_31_0,Test setting input"
group.long 0x108++0x03
line.long 0x00 "RTTSET34_11,"
hexmask.long 0x00 0.--31. 1. "Testmat_63_32,Test setting input"
group.long 0x10C++0x03
line.long 0x00 "RTTSET35_11,"
hexmask.long 0x00 0.--31. 1. "Testmat_95_64,Test setting input"
group.long 0x110++0x03
line.long 0x00 "RTTSET36_11,"
hexmask.long 0x00 0.--31. 1. "Testmat_127_96,Test setting input"
group.long 0x114++0x03
line.long 0x00 "RTTSET37_11,"
hexmask.long 0x00 0.--31. 1. "Testmat_159_128,Test setting input"
group.long 0x118++0x03
line.long 0x00 "RTTSET38_11,"
hexmask.long 0x00 0.--31. 1. "Testmat_191_160,Test setting input"
group.long 0x11C++0x03
line.long 0x00 "RTTSET39_11,"
hexmask.long 0x00 0.--31. 1. "Testmat_223_192,Test setting input"
group.long 0x120++0x03
line.long 0x00 "RTTSET40_11,"
hexmask.long 0x00 0.--31. 1. "Testmat_255_224,Test setting input"
group.long 0x124++0x03
line.long 0x00 "RTTSET41_11,"
hexmask.long.word 0x00 18.--31. 1. "Reserved_18,Reserved The bit or field is readable only"
hexmask.long.byte 0x00 10.--17. 1. "apbsel,Test setting input"
newline
bitfld.long 0x00 6.--9. "mbsel,Test setting input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--5. "coreselect,Test setting input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x128++0x03
line.long 0x00 "RTTSET42_11,"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved The bit or field is readable only" "0,1,2,3"
hexmask.long.word 0x00 16.--29. 1. "Y_address,Test setting input"
newline
rbitfld.long 0x00 14.--15. "Reserved_14,Reserved The bit or field is readable only" "0,1,2,3"
hexmask.long.word 0x00 0.--13. 1. "X_address,Test setting input"
group.long 0x12C++0x03
line.long 0x00 "RTTSET43_11,"
rbitfld.long 0x00 31. "Reserved_31,Reserved The bit or field is readable only" "0,1"
hexmask.long.tbyte 0x00 14.--30. 1. "XY,Test setting input"
newline
hexmask.long.word 0x00 0.--13. 1. "Z_address,Test setting input"
group.long 0x130++0x03
line.long 0x00 "RTTSET44_11,"
rbitfld.long 0x00 26.--31. "Reserved_26,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x00 16.--25. 1. "scanchain,Test setting input for hardware-SCAN"
newline
hexmask.long.word 0x00 0.--15. 1. "scanpat,Test setting input for hardware-SCAN"
group.long 0x400++0x03
line.long 0x00 "PSTRSTT11,"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved"
rbitfld.long 0x00 12. "R_rst_T,BIST Redundant result" "0: pass,1: fail"
newline
rbitfld.long 0x00 11. "Reserved_11,Reserved" "0,1"
rbitfld.long 0x00 8.--10. "error_T,BIST error" "0: Pass,1: Fail,2: TimeOut,?,4: BUS error,?..."
newline
rbitfld.long 0x00 4.--7. "testnum_T,Number of tests" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 2.--3. "status_R,BIST Redundant status (Safety function)" "0: unexec,1: wait,2: exec,3: finish"
newline
rbitfld.long 0x00 0.--1. "status_T,BIST status" "0: unexec,1: wait,2: exec,3: finish"
group.long 0x440++0x03
line.long 0x00 "PSTCNT11,"
hexmask.long 0x00 0.--31. 1. "Stop,FieldBIST internal WDT (high counter) stop value"
group.long 0x444++0x03
line.long 0x00 "RTTRSTT11,When status_T in the RTTRSTT register is"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved" "0,1,2,3"
rbitfld.long 0x00 29. "IL_flag2,Runtime Test Illegal suspension flag-2" "0,1"
newline
rbitfld.long 0x00 28. "IL_flag1,Runtime Test Illegal suspension flag-1" "0,1"
rbitfld.long 0x00 27. "CONDF,Debug monitor of FieldBIST condition" "0: not response,1: responded"
newline
rbitfld.long 0x00 24.--26. "BUS_cond,Debug code of BUS condition" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 13.--23. 1. "Reserved_13,Reserved"
newline
rbitfld.long 0x00 12. "R_rst_T,BIST Redundant result (Safety function)" "0: Pass,1: Fail"
rbitfld.long 0x00 11. "Achk,Debug code of address check" "0: normal,1: warning"
newline
rbitfld.long 0x00 8.--10. "error_T,BIST error" "0: Pass,1: Fail,2: TimeOut,?,4: BUS error,?..."
rbitfld.long 0x00 4.--7. "testnum_T,Number of tests" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 2.--3. "R_status_T,BIST redundant status" "0: unexec,1: wait,2: exec,3: finish"
rbitfld.long 0x00 0.--1. "status_T,BIST status" "0: unexec,1: wait,2: exec,3: finish"
group.long 0x458++0x03
line.long 0x00 "RTTCNT11,"
hexmask.long 0x00 0.--31. 1. "Stop,WDT (high counter) stop value"
group.long 0x4A0++0x03
line.long 0x00 "SLFRVS11,"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved"
hexmask.long.tbyte 0x00 0.--19. 1. "REVERS,Expected value reverse for Self-Check SISR"
group.long 0x4A4++0x03
line.long 0x00 "SLFRST11,In case of the SLFR bits of the RTTRSTT register is 1B'1 SCNT bit returns to 1"
rbitfld.long 0x00 26.--31. "SCNT,Self-Check counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 24.--25. "STS,Self-Check status" "0: unexec,1: exec,?,3: finish"
newline
hexmask.long.tbyte 0x00 1.--23. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "STR,Self -Check Result" "0: Pass,1: Fail"
group.long 0x4C0++0x03
line.long 0x00 "ERRSET11,"
hexmask.long 0x00 3.--31. 1. "Reserved_3,Reserved"
bitfld.long 0x00 2. "DSB,Dummy set BUS-Error (set of fbc_rt_safetyerr)" "0,1"
newline
bitfld.long 0x00 1. "DST,Dummy set Time out (set of fbc_rt_overerr)" "0,1"
bitfld.long 0x00 0. "DSF,Dummy set Fail (set of fbc_rt_fail)" "0,1"
tree.end
tree "FUNCTIONAL_SAFETY_INST_11"
base ad:0xFF873000
group.long 0x00++0x03
line.long 0x00 "RTTEX12,SLFR and SLFE bit of the RTTEX are effective only when KCD bit is H'F1"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved" "0,1,2,3"
bitfld.long 0x00 29. "SLFR,Self-Check Counter Reset for field BIST activator" "0: Counter Reset,1: Counter not Reset"
newline
bitfld.long 0x00 28. "SLFE,Execution of Self-Check for Field BIST activator" "0: Not Execution of Self-Check for Field BIST,1: Execution of Self-Check for Field BIST.."
rbitfld.long 0x00 24.--27. "Reserved_24,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.byte 0x00 16.--23. 1. "KCD,Key Code H'5A: Effective execution of Run Time Test H'F1: Effective execution of Self-Check for field BIST activator"
rbitfld.long 0x00 11.--15. "Reserved_11,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "STM,Single Step Test Mode" "?,1: LBIST,2: MBIST,3: SCAN,?..."
bitfld.long 0x00 6.--7. "INTM,Interrupt mask" "0: non mask *1,?,2: Only at the time of the fail(fba_rt_finish are,?..."
newline
bitfld.long 0x00 5. "SSZ,SCAN Pattern size Valid only when STM=011" "0: 32bit mode,1: 16bit mode"
bitfld.long 0x00 4. "TR,Select the value of the timer" "0: ROM,1: register"
newline
bitfld.long 0x00 3. "WM,Wfi mask" "0: not mask,1: mask"
bitfld.long 0x00 2. "TM,Mask the judgment of timer" "0: not mask,1: mask"
newline
bitfld.long 0x00 1. "STP,Single Step Mode" "0: ROM batch mode,1: Single Step Mode"
bitfld.long 0x00 0. "EX,Execution of Runtime Test" "0: Not Execution of Runtime Test,1: Execution of Runtime Test"
group.long 0x04++0x03
line.long 0x00 "RTTMI112,"
rbitfld.long 0x00 27.--31. "Reserved_27,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 24.--26. "RPROT,Protection type of MEMORY" "0: Unprivileged access,1: Privileged access,?..."
newline
hexmask.long.byte 0x00 16.--23. 1. "MADDR_upper,Memory upper address[39:32] that stores the SCAN pattern"
hexmask.long.word 0x00 0.--15. 1. "MUNIT,Number of units (1 unit = 128 Byte)"
group.long 0x08++0x03
line.long 0x00 "RTTMI212,"
hexmask.long 0x00 0.--31. 1. "MADDR,Memory address that stores the SCAN pattern"
group.long 0x0C++0x03
line.long 0x00 "RTTSISR112,"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved"
hexmask.long.tbyte 0x00 0.--19. 1. "SISR1,SISR-TEST#1 Expected value"
group.long 0x14++0x03
line.long 0x00 "RTTUC12,"
hexmask.long 0x00 0.--31. 1. "U_WDT,Upper counter of Watchdog Timer"
group.long 0x18++0x03
line.long 0x00 "RTTDC12,"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved"
hexmask.long.word 0x00 0.--15. 1. "L_WDT,Lower counter of Watchdog Timer"
group.long 0x80++0x03
line.long 0x00 "RTTSET0_12,"
hexmask.long 0x00 0.--31. 1. "test_clock,Test setting input"
group.long 0x84++0x03
line.long 0x00 "RTTSET1_12,"
hexmask.long 0x00 2.--31. 1. "Reserved_2,Reserved"
bitfld.long 0x00 1. "reset,Test setting input" "0: Reset test disabled,1: Reset test enabled"
newline
bitfld.long 0x00 0. "tt,Test setting input" "0: Selected other clock,1: Selected test clock for test Domain"
group.long 0x88++0x03
line.long 0x00 "RTTSET2_12,"
hexmask.long 0x00 0.--31. 1. "hold0,Test setting input"
group.long 0x8C++0x03
line.long 0x00 "RTTSET3_12,"
hexmask.long.tbyte 0x00 8.--31. 1. "hold1,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "hold0,Test setting input"
group.long 0x90++0x03
line.long 0x00 "RTTSET4_12,"
hexmask.long.word 0x00 16.--31. 1. "hold2,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "hold1,Test setting input"
group.long 0x94++0x03
line.long 0x00 "RTTSET5_12,"
hexmask.long.byte 0x00 24.--31. 1. "hold3,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "hold2,Test setting input"
group.long 0x98++0x03
line.long 0x00 "RTTSET6_12,"
hexmask.long 0x00 0.--31. 1. "hold3,Test setting input"
group.long 0x9C++0x03
line.long 0x00 "RTTSET7_12,"
hexmask.long 0x00 0.--31. 1. "toggle0,Test setting input"
group.long 0xA0++0x03
line.long 0x00 "RTTSET8_12,"
hexmask.long.tbyte 0x00 8.--31. 1. "toggle1,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "toggle0,Test setting input"
group.long 0xA4++0x03
line.long 0x00 "RTTSET9_12,"
hexmask.long.word 0x00 16.--31. 1. "toggle2,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "toggle1,Test setting input"
group.long 0xA8++0x03
line.long 0x00 "RTTSET10_12,"
hexmask.long.byte 0x00 24.--31. 1. "toggle3,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "toggle2,Test setting input"
group.long 0xAC++0x03
line.long 0x00 "RTTSET11_12,"
hexmask.long 0x00 0.--31. 1. "toggle3,Test setting input"
group.long 0xB0++0x03
line.long 0x00 "RTTSET12_12,"
hexmask.long 0x00 0.--31. 1. "switching0,Test setting input"
group.long 0xB4++0x03
line.long 0x00 "RTTSET13_12,"
hexmask.long.tbyte 0x00 8.--31. 1. "switching1,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "switching0,Test setting input"
group.long 0xB8++0x03
line.long 0x00 "RTTSET14_12,"
hexmask.long.word 0x00 16.--31. 1. "switching2,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "switching1,Test setting input"
group.long 0xBC++0x03
line.long 0x00 "RTTSET15_12,"
hexmask.long.byte 0x00 24.--31. 1. "switching3,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "switching2,Test setting input"
group.long 0xC0++0x03
line.long 0x00 "RTTSET16_12,"
hexmask.long 0x00 0.--31. 1. "switching3,Test setting input"
group.long 0xC4++0x03
line.long 0x00 "RTTSET17_12,"
hexmask.long 0x00 0.--31. 1. "hold4,Test setting input"
group.long 0xC8++0x03
line.long 0x00 "RTTSET18_12,"
hexmask.long.tbyte 0x00 8.--31. 1. "hold5,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "hold4,Test setting input"
group.long 0xCC++0x03
line.long 0x00 "RTTSET19_12,"
hexmask.long.word 0x00 16.--31. 1. "hold6,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "hold5,Test setting input"
group.long 0xD0++0x03
line.long 0x00 "RTTSET20_12,"
hexmask.long.byte 0x00 24.--31. 1. "hold7,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "hold6,Test setting input"
group.long 0xD4++0x03
line.long 0x00 "RTTSET21_12,"
hexmask.long 0x00 0.--31. 1. "hold7,Test setting input"
group.long 0xD8++0x03
line.long 0x00 "RTTSET22_12,"
hexmask.long 0x00 0.--31. 1. "toggle4,Test setting input"
group.long 0xDC++0x03
line.long 0x00 "RTTSET23_12,"
hexmask.long.tbyte 0x00 8.--31. 1. "toggle5,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "toggle4,Test setting input"
group.long 0xE0++0x03
line.long 0x00 "RTTSET24_12,"
hexmask.long.word 0x00 16.--31. 1. "toggle6,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "toggle5,Test setting input"
group.long 0xE4++0x03
line.long 0x00 "RTTSET25_12,"
hexmask.long.byte 0x00 24.--31. 1. "toggle7,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "toggle6,Test setting input"
group.long 0xE8++0x03
line.long 0x00 "RTTSET26_12,"
hexmask.long 0x00 0.--31. 1. "toggle7,Test setting input"
group.long 0xEC++0x03
line.long 0x00 "RTTSET27_12,"
hexmask.long 0x00 0.--31. 1. "switching4,Test setting input"
group.long 0xF0++0x03
line.long 0x00 "RTTSET28_12,"
hexmask.long.tbyte 0x00 8.--31. 1. "switching5,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "switching4,Test setting input"
group.long 0xF4++0x03
line.long 0x00 "RTTSET29_12,"
hexmask.long.word 0x00 16.--31. 1. "switching6,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "switching5,Test setting input"
group.long 0xF8++0x03
line.long 0x00 "RTTSET30_12,"
hexmask.long.byte 0x00 24.--31. 1. "switching7,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "switching6,Test setting input"
group.long 0xFC++0x03
line.long 0x00 "RTTSET31_12,"
hexmask.long 0x00 0.--31. 1. "switching7,Test setting input"
group.long 0x100++0x03
line.long 0x00 "RTTSET32_12,"
hexmask.long 0x00 0.--31. 1. "clknum_31_0,Test setting input"
group.long 0x104++0x03
line.long 0x00 "RTTSET33_12,"
hexmask.long 0x00 0.--31. 1. "Testmat_31_0,Test setting input"
group.long 0x108++0x03
line.long 0x00 "RTTSET34_12,"
hexmask.long 0x00 0.--31. 1. "Testmat_63_32,Test setting input"
group.long 0x10C++0x03
line.long 0x00 "RTTSET35_12,"
hexmask.long 0x00 0.--31. 1. "Testmat_95_64,Test setting input"
group.long 0x110++0x03
line.long 0x00 "RTTSET36_12,"
hexmask.long 0x00 0.--31. 1. "Testmat_127_96,Test setting input"
group.long 0x114++0x03
line.long 0x00 "RTTSET37_12,"
hexmask.long 0x00 0.--31. 1. "Testmat_159_128,Test setting input"
group.long 0x118++0x03
line.long 0x00 "RTTSET38_12,"
hexmask.long 0x00 0.--31. 1. "Testmat_191_160,Test setting input"
group.long 0x11C++0x03
line.long 0x00 "RTTSET39_12,"
hexmask.long 0x00 0.--31. 1. "Testmat_223_192,Test setting input"
group.long 0x120++0x03
line.long 0x00 "RTTSET40_12,"
hexmask.long 0x00 0.--31. 1. "Testmat_255_224,Test setting input"
group.long 0x124++0x03
line.long 0x00 "RTTSET41_12,"
hexmask.long.word 0x00 18.--31. 1. "Reserved_18,Reserved The bit or field is readable only"
hexmask.long.byte 0x00 10.--17. 1. "apbsel,Test setting input"
newline
bitfld.long 0x00 6.--9. "mbsel,Test setting input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--5. "coreselect,Test setting input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x128++0x03
line.long 0x00 "RTTSET42_12,"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved The bit or field is readable only" "0,1,2,3"
hexmask.long.word 0x00 16.--29. 1. "Y_address,Test setting input"
newline
rbitfld.long 0x00 14.--15. "Reserved_14,Reserved The bit or field is readable only" "0,1,2,3"
hexmask.long.word 0x00 0.--13. 1. "X_address,Test setting input"
group.long 0x12C++0x03
line.long 0x00 "RTTSET43_12,"
rbitfld.long 0x00 31. "Reserved_31,Reserved The bit or field is readable only" "0,1"
hexmask.long.tbyte 0x00 14.--30. 1. "XY,Test setting input"
newline
hexmask.long.word 0x00 0.--13. 1. "Z_address,Test setting input"
group.long 0x130++0x03
line.long 0x00 "RTTSET44_12,"
rbitfld.long 0x00 26.--31. "Reserved_26,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x00 16.--25. 1. "scanchain,Test setting input for hardware-SCAN"
newline
hexmask.long.word 0x00 0.--15. 1. "scanpat,Test setting input for hardware-SCAN"
group.long 0x400++0x03
line.long 0x00 "PSTRSTT12,"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved"
rbitfld.long 0x00 12. "R_rst_T,BIST Redundant result" "0: pass,1: fail"
newline
rbitfld.long 0x00 11. "Reserved_11,Reserved" "0,1"
rbitfld.long 0x00 8.--10. "error_T,BIST error" "0: Pass,1: Fail,2: TimeOut,?,4: BUS error,?..."
newline
rbitfld.long 0x00 4.--7. "testnum_T,Number of tests" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 2.--3. "status_R,BIST Redundant status (Safety function)" "0: unexec,1: wait,2: exec,3: finish"
newline
rbitfld.long 0x00 0.--1. "status_T,BIST status" "0: unexec,1: wait,2: exec,3: finish"
group.long 0x440++0x03
line.long 0x00 "PSTCNT12,"
hexmask.long 0x00 0.--31. 1. "Stop,FieldBIST internal WDT (high counter) stop value"
group.long 0x444++0x03
line.long 0x00 "RTTRSTT12,When status_T in the RTTRSTT register is"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved" "0,1,2,3"
rbitfld.long 0x00 29. "IL_flag2,Runtime Test Illegal suspension flag-2" "0,1"
newline
rbitfld.long 0x00 28. "IL_flag1,Runtime Test Illegal suspension flag-1" "0,1"
rbitfld.long 0x00 27. "CONDF,Debug monitor of FieldBIST condition" "0: not response,1: responded"
newline
rbitfld.long 0x00 24.--26. "BUS_cond,Debug code of BUS condition" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 13.--23. 1. "Reserved_13,Reserved"
newline
rbitfld.long 0x00 12. "R_rst_T,BIST Redundant result (Safety function)" "0: Pass,1: Fail"
rbitfld.long 0x00 11. "Achk,Debug code of address check" "0: normal,1: warning"
newline
rbitfld.long 0x00 8.--10. "error_T,BIST error" "0: Pass,1: Fail,2: TimeOut,?,4: BUS error,?..."
rbitfld.long 0x00 4.--7. "testnum_T,Number of tests" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 2.--3. "R_status_T,BIST redundant status" "0: unexec,1: wait,2: exec,3: finish"
rbitfld.long 0x00 0.--1. "status_T,BIST status" "0: unexec,1: wait,2: exec,3: finish"
group.long 0x458++0x03
line.long 0x00 "RTTCNT12,"
hexmask.long 0x00 0.--31. 1. "Stop,WDT (high counter) stop value"
group.long 0x4A0++0x03
line.long 0x00 "SLFRVS12,"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved"
hexmask.long.tbyte 0x00 0.--19. 1. "REVERS,Expected value reverse for Self-Check SISR"
group.long 0x4A4++0x03
line.long 0x00 "SLFRST12,In case of the SLFR bits of the RTTRSTT register is 1B'1 SCNT bit returns to 1"
rbitfld.long 0x00 26.--31. "SCNT,Self-Check counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 24.--25. "STS,Self-Check status" "0: unexec,1: exec,?,3: finish"
newline
hexmask.long.tbyte 0x00 1.--23. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "STR,Self -Check Result" "0: Pass,1: Fail"
group.long 0x4C0++0x03
line.long 0x00 "ERRSET12,"
hexmask.long 0x00 3.--31. 1. "Reserved_3,Reserved"
bitfld.long 0x00 2. "DSB,Dummy set BUS-Error (set of fbc_rt_safetyerr)" "0,1"
newline
bitfld.long 0x00 1. "DST,Dummy set Time out (set of fbc_rt_overerr)" "0,1"
bitfld.long 0x00 0. "DSF,Dummy set Fail (set of fbc_rt_fail)" "0,1"
tree.end
tree "FUNCTIONAL_SAFETY_INST_12"
base ad:0xFF871000
group.long 0x00++0x03
line.long 0x00 "RTTEX13,SLFR and SLFE bit of the RTTEX are effective only when KCD bit is H'F1"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved" "0,1,2,3"
bitfld.long 0x00 29. "SLFR,Self-Check Counter Reset for field BIST activator" "0: Counter Reset,1: Counter not Reset"
newline
bitfld.long 0x00 28. "SLFE,Execution of Self-Check for Field BIST activator" "0: Not Execution of Self-Check for Field BIST,1: Execution of Self-Check for Field BIST.."
rbitfld.long 0x00 24.--27. "Reserved_24,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.byte 0x00 16.--23. 1. "KCD,Key Code H'5A: Effective execution of Run Time Test H'F1: Effective execution of Self-Check for field BIST activator"
rbitfld.long 0x00 11.--15. "Reserved_11,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "STM,Single Step Test Mode" "?,1: LBIST,2: MBIST,3: SCAN,?..."
bitfld.long 0x00 6.--7. "INTM,Interrupt mask" "0: non mask *1,?,2: Only at the time of the fail(fba_rt_finish are,?..."
newline
bitfld.long 0x00 5. "SSZ,SCAN Pattern size Valid only when STM=011" "0: 32bit mode,1: 16bit mode"
bitfld.long 0x00 4. "TR,Select the value of the timer" "0: ROM,1: register"
newline
bitfld.long 0x00 3. "WM,Wfi mask" "0: not mask,1: mask"
bitfld.long 0x00 2. "TM,Mask the judgment of timer" "0: not mask,1: mask"
newline
bitfld.long 0x00 1. "STP,Single Step Mode" "0: ROM batch mode,1: Single Step Mode"
bitfld.long 0x00 0. "EX,Execution of Runtime Test" "0: Not Execution of Runtime Test,1: Execution of Runtime Test"
group.long 0x04++0x03
line.long 0x00 "RTTMI113,"
rbitfld.long 0x00 27.--31. "Reserved_27,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 24.--26. "RPROT,Protection type of MEMORY" "0: Unprivileged access,1: Privileged access,?..."
newline
hexmask.long.byte 0x00 16.--23. 1. "MADDR_upper,Memory upper address[39:32] that stores the SCAN pattern"
hexmask.long.word 0x00 0.--15. 1. "MUNIT,Number of units (1 unit = 128 Byte)"
group.long 0x08++0x03
line.long 0x00 "RTTMI213,"
hexmask.long 0x00 0.--31. 1. "MADDR,Memory address that stores the SCAN pattern"
group.long 0x0C++0x03
line.long 0x00 "RTTSISR113,"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved"
hexmask.long.tbyte 0x00 0.--19. 1. "SISR1,SISR-TEST#1 Expected value"
group.long 0x14++0x03
line.long 0x00 "RTTUC13,"
hexmask.long 0x00 0.--31. 1. "U_WDT,Upper counter of Watchdog Timer"
group.long 0x18++0x03
line.long 0x00 "RTTDC13,"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved"
hexmask.long.word 0x00 0.--15. 1. "L_WDT,Lower counter of Watchdog Timer"
group.long 0x80++0x03
line.long 0x00 "RTTSET0_13,"
hexmask.long 0x00 0.--31. 1. "test_clock,Test setting input"
group.long 0x84++0x03
line.long 0x00 "RTTSET1_13,"
hexmask.long 0x00 2.--31. 1. "Reserved_2,Reserved"
bitfld.long 0x00 1. "reset,Test setting input" "0: Reset test disabled,1: Reset test enabled"
newline
bitfld.long 0x00 0. "tt,Test setting input" "0: Selected other clock,1: Selected test clock for test Domain"
group.long 0x88++0x03
line.long 0x00 "RTTSET2_13,"
hexmask.long 0x00 0.--31. 1. "hold0,Test setting input"
group.long 0x8C++0x03
line.long 0x00 "RTTSET3_13,"
hexmask.long.tbyte 0x00 8.--31. 1. "hold1,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "hold0,Test setting input"
group.long 0x90++0x03
line.long 0x00 "RTTSET4_13,"
hexmask.long.word 0x00 16.--31. 1. "hold2,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "hold1,Test setting input"
group.long 0x94++0x03
line.long 0x00 "RTTSET5_13,"
hexmask.long.byte 0x00 24.--31. 1. "hold3,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "hold2,Test setting input"
group.long 0x98++0x03
line.long 0x00 "RTTSET6_13,"
hexmask.long 0x00 0.--31. 1. "hold3,Test setting input"
group.long 0x9C++0x03
line.long 0x00 "RTTSET7_13,"
hexmask.long 0x00 0.--31. 1. "toggle0,Test setting input"
group.long 0xA0++0x03
line.long 0x00 "RTTSET8_13,"
hexmask.long.tbyte 0x00 8.--31. 1. "toggle1,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "toggle0,Test setting input"
group.long 0xA4++0x03
line.long 0x00 "RTTSET9_13,"
hexmask.long.word 0x00 16.--31. 1. "toggle2,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "toggle1,Test setting input"
group.long 0xA8++0x03
line.long 0x00 "RTTSET10_13,"
hexmask.long.byte 0x00 24.--31. 1. "toggle3,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "toggle2,Test setting input"
group.long 0xAC++0x03
line.long 0x00 "RTTSET11_13,"
hexmask.long 0x00 0.--31. 1. "toggle3,Test setting input"
group.long 0xB0++0x03
line.long 0x00 "RTTSET12_13,"
hexmask.long 0x00 0.--31. 1. "switching0,Test setting input"
group.long 0xB4++0x03
line.long 0x00 "RTTSET13_13,"
hexmask.long.tbyte 0x00 8.--31. 1. "switching1,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "switching0,Test setting input"
group.long 0xB8++0x03
line.long 0x00 "RTTSET14_13,"
hexmask.long.word 0x00 16.--31. 1. "switching2,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "switching1,Test setting input"
group.long 0xBC++0x03
line.long 0x00 "RTTSET15_13,"
hexmask.long.byte 0x00 24.--31. 1. "switching3,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "switching2,Test setting input"
group.long 0xC0++0x03
line.long 0x00 "RTTSET16_13,"
hexmask.long 0x00 0.--31. 1. "switching3,Test setting input"
group.long 0xC4++0x03
line.long 0x00 "RTTSET17_13,"
hexmask.long 0x00 0.--31. 1. "hold4,Test setting input"
group.long 0xC8++0x03
line.long 0x00 "RTTSET18_13,"
hexmask.long.tbyte 0x00 8.--31. 1. "hold5,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "hold4,Test setting input"
group.long 0xCC++0x03
line.long 0x00 "RTTSET19_13,"
hexmask.long.word 0x00 16.--31. 1. "hold6,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "hold5,Test setting input"
group.long 0xD0++0x03
line.long 0x00 "RTTSET20_13,"
hexmask.long.byte 0x00 24.--31. 1. "hold7,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "hold6,Test setting input"
group.long 0xD4++0x03
line.long 0x00 "RTTSET21_13,"
hexmask.long 0x00 0.--31. 1. "hold7,Test setting input"
group.long 0xD8++0x03
line.long 0x00 "RTTSET22_13,"
hexmask.long 0x00 0.--31. 1. "toggle4,Test setting input"
group.long 0xDC++0x03
line.long 0x00 "RTTSET23_13,"
hexmask.long.tbyte 0x00 8.--31. 1. "toggle5,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "toggle4,Test setting input"
group.long 0xE0++0x03
line.long 0x00 "RTTSET24_13,"
hexmask.long.word 0x00 16.--31. 1. "toggle6,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "toggle5,Test setting input"
group.long 0xE4++0x03
line.long 0x00 "RTTSET25_13,"
hexmask.long.byte 0x00 24.--31. 1. "toggle7,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "toggle6,Test setting input"
group.long 0xE8++0x03
line.long 0x00 "RTTSET26_13,"
hexmask.long 0x00 0.--31. 1. "toggle7,Test setting input"
group.long 0xEC++0x03
line.long 0x00 "RTTSET27_13,"
hexmask.long 0x00 0.--31. 1. "switching4,Test setting input"
group.long 0xF0++0x03
line.long 0x00 "RTTSET28_13,"
hexmask.long.tbyte 0x00 8.--31. 1. "switching5,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "switching4,Test setting input"
group.long 0xF4++0x03
line.long 0x00 "RTTSET29_13,"
hexmask.long.word 0x00 16.--31. 1. "switching6,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "switching5,Test setting input"
group.long 0xF8++0x03
line.long 0x00 "RTTSET30_13,"
hexmask.long.byte 0x00 24.--31. 1. "switching7,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "switching6,Test setting input"
group.long 0xFC++0x03
line.long 0x00 "RTTSET31_13,"
hexmask.long 0x00 0.--31. 1. "switching7,Test setting input"
group.long 0x100++0x03
line.long 0x00 "RTTSET32_13,"
hexmask.long 0x00 0.--31. 1. "clknum_31_0,Test setting input"
group.long 0x104++0x03
line.long 0x00 "RTTSET33_13,"
hexmask.long 0x00 0.--31. 1. "Testmat_31_0,Test setting input"
group.long 0x108++0x03
line.long 0x00 "RTTSET34_13,"
hexmask.long 0x00 0.--31. 1. "Testmat_63_32,Test setting input"
group.long 0x10C++0x03
line.long 0x00 "RTTSET35_13,"
hexmask.long 0x00 0.--31. 1. "Testmat_95_64,Test setting input"
group.long 0x110++0x03
line.long 0x00 "RTTSET36_13,"
hexmask.long 0x00 0.--31. 1. "Testmat_127_96,Test setting input"
group.long 0x114++0x03
line.long 0x00 "RTTSET37_13,"
hexmask.long 0x00 0.--31. 1. "Testmat_159_128,Test setting input"
group.long 0x118++0x03
line.long 0x00 "RTTSET38_13,"
hexmask.long 0x00 0.--31. 1. "Testmat_191_160,Test setting input"
group.long 0x11C++0x03
line.long 0x00 "RTTSET39_13,"
hexmask.long 0x00 0.--31. 1. "Testmat_223_192,Test setting input"
group.long 0x120++0x03
line.long 0x00 "RTTSET40_13,"
hexmask.long 0x00 0.--31. 1. "Testmat_255_224,Test setting input"
group.long 0x124++0x03
line.long 0x00 "RTTSET41_13,"
hexmask.long.word 0x00 18.--31. 1. "Reserved_18,Reserved The bit or field is readable only"
hexmask.long.byte 0x00 10.--17. 1. "apbsel,Test setting input"
newline
bitfld.long 0x00 6.--9. "mbsel,Test setting input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--5. "coreselect,Test setting input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x128++0x03
line.long 0x00 "RTTSET42_13,"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved The bit or field is readable only" "0,1,2,3"
hexmask.long.word 0x00 16.--29. 1. "Y_address,Test setting input"
newline
rbitfld.long 0x00 14.--15. "Reserved_14,Reserved The bit or field is readable only" "0,1,2,3"
hexmask.long.word 0x00 0.--13. 1. "X_address,Test setting input"
group.long 0x12C++0x03
line.long 0x00 "RTTSET43_13,"
rbitfld.long 0x00 31. "Reserved_31,Reserved The bit or field is readable only" "0,1"
hexmask.long.tbyte 0x00 14.--30. 1. "XY,Test setting input"
newline
hexmask.long.word 0x00 0.--13. 1. "Z_address,Test setting input"
group.long 0x130++0x03
line.long 0x00 "RTTSET44_13,"
rbitfld.long 0x00 26.--31. "Reserved_26,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x00 16.--25. 1. "scanchain,Test setting input for hardware-SCAN"
newline
hexmask.long.word 0x00 0.--15. 1. "scanpat,Test setting input for hardware-SCAN"
group.long 0x400++0x03
line.long 0x00 "PSTRSTT13,"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved"
rbitfld.long 0x00 12. "R_rst_T,BIST Redundant result" "0: pass,1: fail"
newline
rbitfld.long 0x00 11. "Reserved_11,Reserved" "0,1"
rbitfld.long 0x00 8.--10. "error_T,BIST error" "0: Pass,1: Fail,2: TimeOut,?,4: BUS error,?..."
newline
rbitfld.long 0x00 4.--7. "testnum_T,Number of tests" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 2.--3. "status_R,BIST Redundant status (Safety function)" "0: unexec,1: wait,2: exec,3: finish"
newline
rbitfld.long 0x00 0.--1. "status_T,BIST status" "0: unexec,1: wait,2: exec,3: finish"
group.long 0x440++0x03
line.long 0x00 "PSTCNT13,"
hexmask.long 0x00 0.--31. 1. "Stop,FieldBIST internal WDT (high counter) stop value"
group.long 0x444++0x03
line.long 0x00 "RTTRSTT13,When status_T in the RTTRSTT register is"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved" "0,1,2,3"
rbitfld.long 0x00 29. "IL_flag2,Runtime Test Illegal suspension flag-2" "0,1"
newline
rbitfld.long 0x00 28. "IL_flag1,Runtime Test Illegal suspension flag-1" "0,1"
rbitfld.long 0x00 27. "CONDF,Debug monitor of FieldBIST condition" "0: not response,1: responded"
newline
rbitfld.long 0x00 24.--26. "BUS_cond,Debug code of BUS condition" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 13.--23. 1. "Reserved_13,Reserved"
newline
rbitfld.long 0x00 12. "R_rst_T,BIST Redundant result (Safety function)" "0: Pass,1: Fail"
rbitfld.long 0x00 11. "Achk,Debug code of address check" "0: normal,1: warning"
newline
rbitfld.long 0x00 8.--10. "error_T,BIST error" "0: Pass,1: Fail,2: TimeOut,?,4: BUS error,?..."
rbitfld.long 0x00 4.--7. "testnum_T,Number of tests" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 2.--3. "R_status_T,BIST redundant status" "0: unexec,1: wait,2: exec,3: finish"
rbitfld.long 0x00 0.--1. "status_T,BIST status" "0: unexec,1: wait,2: exec,3: finish"
group.long 0x458++0x03
line.long 0x00 "RTTCNT13,"
hexmask.long 0x00 0.--31. 1. "Stop,WDT (high counter) stop value"
group.long 0x4A0++0x03
line.long 0x00 "SLFRVS13,"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved"
hexmask.long.tbyte 0x00 0.--19. 1. "REVERS,Expected value reverse for Self-Check SISR"
group.long 0x4A4++0x03
line.long 0x00 "SLFRST13,In case of the SLFR bits of the RTTRSTT register is 1B'1 SCNT bit returns to 1"
rbitfld.long 0x00 26.--31. "SCNT,Self-Check counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 24.--25. "STS,Self-Check status" "0: unexec,1: exec,?,3: finish"
newline
hexmask.long.tbyte 0x00 1.--23. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "STR,Self -Check Result" "0: Pass,1: Fail"
group.long 0x4C0++0x03
line.long 0x00 "ERRSET13,"
hexmask.long 0x00 3.--31. 1. "Reserved_3,Reserved"
bitfld.long 0x00 2. "DSB,Dummy set BUS-Error (set of fbc_rt_safetyerr)" "0,1"
newline
bitfld.long 0x00 1. "DST,Dummy set Time out (set of fbc_rt_overerr)" "0,1"
bitfld.long 0x00 0. "DSF,Dummy set Fail (set of fbc_rt_fail)" "0,1"
tree.end
tree "FUNCTIONAL_SAFETY_INST_13"
base ad:0xFF874000
group.long 0x00++0x03
line.long 0x00 "RTTEX14,SLFR and SLFE bit of the RTTEX are effective only when KCD bit is H'F1"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved" "0,1,2,3"
bitfld.long 0x00 29. "SLFR,Self-Check Counter Reset for field BIST activator" "0: Counter Reset,1: Counter not Reset"
newline
bitfld.long 0x00 28. "SLFE,Execution of Self-Check for Field BIST activator" "0: Not Execution of Self-Check for Field BIST,1: Execution of Self-Check for Field BIST.."
rbitfld.long 0x00 24.--27. "Reserved_24,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.byte 0x00 16.--23. 1. "KCD,Key Code H'5A: Effective execution of Run Time Test H'F1: Effective execution of Self-Check for field BIST activator"
rbitfld.long 0x00 11.--15. "Reserved_11,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "STM,Single Step Test Mode" "?,1: LBIST,2: MBIST,3: SCAN,?..."
bitfld.long 0x00 6.--7. "INTM,Interrupt mask" "0: non mask *1,?,2: Only at the time of the fail(fba_rt_finish are,?..."
newline
bitfld.long 0x00 5. "SSZ,SCAN Pattern size Valid only when STM=011" "0: 32bit mode,1: 16bit mode"
bitfld.long 0x00 4. "TR,Select the value of the timer" "0: ROM,1: register"
newline
bitfld.long 0x00 3. "WM,Wfi mask" "0: not mask,1: mask"
bitfld.long 0x00 2. "TM,Mask the judgment of timer" "0: not mask,1: mask"
newline
bitfld.long 0x00 1. "STP,Single Step Mode" "0: ROM batch mode,1: Single Step Mode"
bitfld.long 0x00 0. "EX,Execution of Runtime Test" "0: Not Execution of Runtime Test,1: Execution of Runtime Test"
group.long 0x04++0x03
line.long 0x00 "RTTMI114,"
rbitfld.long 0x00 27.--31. "Reserved_27,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 24.--26. "RPROT,Protection type of MEMORY" "0: Unprivileged access,1: Privileged access,?..."
newline
hexmask.long.byte 0x00 16.--23. 1. "MADDR_upper,Memory upper address[39:32] that stores the SCAN pattern"
hexmask.long.word 0x00 0.--15. 1. "MUNIT,Number of units (1 unit = 128 Byte)"
group.long 0x08++0x03
line.long 0x00 "RTTMI214,"
hexmask.long 0x00 0.--31. 1. "MADDR,Memory address that stores the SCAN pattern"
group.long 0x0C++0x03
line.long 0x00 "RTTSISR114,"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved"
hexmask.long.tbyte 0x00 0.--19. 1. "SISR1,SISR-TEST#1 Expected value"
group.long 0x14++0x03
line.long 0x00 "RTTUC14,"
hexmask.long 0x00 0.--31. 1. "U_WDT,Upper counter of Watchdog Timer"
group.long 0x18++0x03
line.long 0x00 "RTTDC14,"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved"
hexmask.long.word 0x00 0.--15. 1. "L_WDT,Lower counter of Watchdog Timer"
group.long 0x80++0x03
line.long 0x00 "RTTSET0_14,"
hexmask.long 0x00 0.--31. 1. "test_clock,Test setting input"
group.long 0x84++0x03
line.long 0x00 "RTTSET1_14,"
hexmask.long 0x00 2.--31. 1. "Reserved_2,Reserved"
bitfld.long 0x00 1. "reset,Test setting input" "0: Reset test disabled,1: Reset test enabled"
newline
bitfld.long 0x00 0. "tt,Test setting input" "0: Selected other clock,1: Selected test clock for test Domain"
group.long 0x88++0x03
line.long 0x00 "RTTSET2_14,"
hexmask.long 0x00 0.--31. 1. "hold0,Test setting input"
group.long 0x8C++0x03
line.long 0x00 "RTTSET3_14,"
hexmask.long.tbyte 0x00 8.--31. 1. "hold1,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "hold0,Test setting input"
group.long 0x90++0x03
line.long 0x00 "RTTSET4_14,"
hexmask.long.word 0x00 16.--31. 1. "hold2,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "hold1,Test setting input"
group.long 0x94++0x03
line.long 0x00 "RTTSET5_14,"
hexmask.long.byte 0x00 24.--31. 1. "hold3,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "hold2,Test setting input"
group.long 0x98++0x03
line.long 0x00 "RTTSET6_14,"
hexmask.long 0x00 0.--31. 1. "hold3,Test setting input"
group.long 0x9C++0x03
line.long 0x00 "RTTSET7_14,"
hexmask.long 0x00 0.--31. 1. "toggle0,Test setting input"
group.long 0xA0++0x03
line.long 0x00 "RTTSET8_14,"
hexmask.long.tbyte 0x00 8.--31. 1. "toggle1,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "toggle0,Test setting input"
group.long 0xA4++0x03
line.long 0x00 "RTTSET9_14,"
hexmask.long.word 0x00 16.--31. 1. "toggle2,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "toggle1,Test setting input"
group.long 0xA8++0x03
line.long 0x00 "RTTSET10_14,"
hexmask.long.byte 0x00 24.--31. 1. "toggle3,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "toggle2,Test setting input"
group.long 0xAC++0x03
line.long 0x00 "RTTSET11_14,"
hexmask.long 0x00 0.--31. 1. "toggle3,Test setting input"
group.long 0xB0++0x03
line.long 0x00 "RTTSET12_14,"
hexmask.long 0x00 0.--31. 1. "switching0,Test setting input"
group.long 0xB4++0x03
line.long 0x00 "RTTSET13_14,"
hexmask.long.tbyte 0x00 8.--31. 1. "switching1,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "switching0,Test setting input"
group.long 0xB8++0x03
line.long 0x00 "RTTSET14_14,"
hexmask.long.word 0x00 16.--31. 1. "switching2,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "switching1,Test setting input"
group.long 0xBC++0x03
line.long 0x00 "RTTSET15_14,"
hexmask.long.byte 0x00 24.--31. 1. "switching3,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "switching2,Test setting input"
group.long 0xC0++0x03
line.long 0x00 "RTTSET16_14,"
hexmask.long 0x00 0.--31. 1. "switching3,Test setting input"
group.long 0xC4++0x03
line.long 0x00 "RTTSET17_14,"
hexmask.long 0x00 0.--31. 1. "hold4,Test setting input"
group.long 0xC8++0x03
line.long 0x00 "RTTSET18_14,"
hexmask.long.tbyte 0x00 8.--31. 1. "hold5,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "hold4,Test setting input"
group.long 0xCC++0x03
line.long 0x00 "RTTSET19_14,"
hexmask.long.word 0x00 16.--31. 1. "hold6,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "hold5,Test setting input"
group.long 0xD0++0x03
line.long 0x00 "RTTSET20_14,"
hexmask.long.byte 0x00 24.--31. 1. "hold7,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "hold6,Test setting input"
group.long 0xD4++0x03
line.long 0x00 "RTTSET21_14,"
hexmask.long 0x00 0.--31. 1. "hold7,Test setting input"
group.long 0xD8++0x03
line.long 0x00 "RTTSET22_14,"
hexmask.long 0x00 0.--31. 1. "toggle4,Test setting input"
group.long 0xDC++0x03
line.long 0x00 "RTTSET23_14,"
hexmask.long.tbyte 0x00 8.--31. 1. "toggle5,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "toggle4,Test setting input"
group.long 0xE0++0x03
line.long 0x00 "RTTSET24_14,"
hexmask.long.word 0x00 16.--31. 1. "toggle6,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "toggle5,Test setting input"
group.long 0xE4++0x03
line.long 0x00 "RTTSET25_14,"
hexmask.long.byte 0x00 24.--31. 1. "toggle7,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "toggle6,Test setting input"
group.long 0xE8++0x03
line.long 0x00 "RTTSET26_14,"
hexmask.long 0x00 0.--31. 1. "toggle7,Test setting input"
group.long 0xEC++0x03
line.long 0x00 "RTTSET27_14,"
hexmask.long 0x00 0.--31. 1. "switching4,Test setting input"
group.long 0xF0++0x03
line.long 0x00 "RTTSET28_14,"
hexmask.long.tbyte 0x00 8.--31. 1. "switching5,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "switching4,Test setting input"
group.long 0xF4++0x03
line.long 0x00 "RTTSET29_14,"
hexmask.long.word 0x00 16.--31. 1. "switching6,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "switching5,Test setting input"
group.long 0xF8++0x03
line.long 0x00 "RTTSET30_14,"
hexmask.long.byte 0x00 24.--31. 1. "switching7,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "switching6,Test setting input"
group.long 0xFC++0x03
line.long 0x00 "RTTSET31_14,"
hexmask.long 0x00 0.--31. 1. "switching7,Test setting input"
group.long 0x100++0x03
line.long 0x00 "RTTSET32_14,"
hexmask.long 0x00 0.--31. 1. "clknum_31_0,Test setting input"
group.long 0x104++0x03
line.long 0x00 "RTTSET33_14,"
hexmask.long 0x00 0.--31. 1. "Testmat_31_0,Test setting input"
group.long 0x108++0x03
line.long 0x00 "RTTSET34_14,"
hexmask.long 0x00 0.--31. 1. "Testmat_63_32,Test setting input"
group.long 0x10C++0x03
line.long 0x00 "RTTSET35_14,"
hexmask.long 0x00 0.--31. 1. "Testmat_95_64,Test setting input"
group.long 0x110++0x03
line.long 0x00 "RTTSET36_14,"
hexmask.long 0x00 0.--31. 1. "Testmat_127_96,Test setting input"
group.long 0x114++0x03
line.long 0x00 "RTTSET37_14,"
hexmask.long 0x00 0.--31. 1. "Testmat_159_128,Test setting input"
group.long 0x118++0x03
line.long 0x00 "RTTSET38_14,"
hexmask.long 0x00 0.--31. 1. "Testmat_191_160,Test setting input"
group.long 0x11C++0x03
line.long 0x00 "RTTSET39_14,"
hexmask.long 0x00 0.--31. 1. "Testmat_223_192,Test setting input"
group.long 0x120++0x03
line.long 0x00 "RTTSET40_14,"
hexmask.long 0x00 0.--31. 1. "Testmat_255_224,Test setting input"
group.long 0x124++0x03
line.long 0x00 "RTTSET41_14,"
hexmask.long.word 0x00 18.--31. 1. "Reserved_18,Reserved The bit or field is readable only"
hexmask.long.byte 0x00 10.--17. 1. "apbsel,Test setting input"
newline
bitfld.long 0x00 6.--9. "mbsel,Test setting input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--5. "coreselect,Test setting input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x128++0x03
line.long 0x00 "RTTSET42_14,"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved The bit or field is readable only" "0,1,2,3"
hexmask.long.word 0x00 16.--29. 1. "Y_address,Test setting input"
newline
rbitfld.long 0x00 14.--15. "Reserved_14,Reserved The bit or field is readable only" "0,1,2,3"
hexmask.long.word 0x00 0.--13. 1. "X_address,Test setting input"
group.long 0x12C++0x03
line.long 0x00 "RTTSET43_14,"
rbitfld.long 0x00 31. "Reserved_31,Reserved The bit or field is readable only" "0,1"
hexmask.long.tbyte 0x00 14.--30. 1. "XY,Test setting input"
newline
hexmask.long.word 0x00 0.--13. 1. "Z_address,Test setting input"
group.long 0x130++0x03
line.long 0x00 "RTTSET44_14,"
rbitfld.long 0x00 26.--31. "Reserved_26,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x00 16.--25. 1. "scanchain,Test setting input for hardware-SCAN"
newline
hexmask.long.word 0x00 0.--15. 1. "scanpat,Test setting input for hardware-SCAN"
group.long 0x400++0x03
line.long 0x00 "PSTRSTT14,"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved"
rbitfld.long 0x00 12. "R_rst_T,BIST Redundant result" "0: pass,1: fail"
newline
rbitfld.long 0x00 11. "Reserved_11,Reserved" "0,1"
rbitfld.long 0x00 8.--10. "error_T,BIST error" "0: Pass,1: Fail,2: TimeOut,?,4: BUS error,?..."
newline
rbitfld.long 0x00 4.--7. "testnum_T,Number of tests" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 2.--3. "status_R,BIST Redundant status (Safety function)" "0: unexec,1: wait,2: exec,3: finish"
newline
rbitfld.long 0x00 0.--1. "status_T,BIST status" "0: unexec,1: wait,2: exec,3: finish"
group.long 0x440++0x03
line.long 0x00 "PSTCNT14,"
hexmask.long 0x00 0.--31. 1. "Stop,FieldBIST internal WDT (high counter) stop value"
group.long 0x444++0x03
line.long 0x00 "RTTRSTT14,When status_T in the RTTRSTT register is"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved" "0,1,2,3"
rbitfld.long 0x00 29. "IL_flag2,Runtime Test Illegal suspension flag-2" "0,1"
newline
rbitfld.long 0x00 28. "IL_flag1,Runtime Test Illegal suspension flag-1" "0,1"
rbitfld.long 0x00 27. "CONDF,Debug monitor of FieldBIST condition" "0: not response,1: responded"
newline
rbitfld.long 0x00 24.--26. "BUS_cond,Debug code of BUS condition" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 13.--23. 1. "Reserved_13,Reserved"
newline
rbitfld.long 0x00 12. "R_rst_T,BIST Redundant result (Safety function)" "0: Pass,1: Fail"
rbitfld.long 0x00 11. "Achk,Debug code of address check" "0: normal,1: warning"
newline
rbitfld.long 0x00 8.--10. "error_T,BIST error" "0: Pass,1: Fail,2: TimeOut,?,4: BUS error,?..."
rbitfld.long 0x00 4.--7. "testnum_T,Number of tests" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 2.--3. "R_status_T,BIST redundant status" "0: unexec,1: wait,2: exec,3: finish"
rbitfld.long 0x00 0.--1. "status_T,BIST status" "0: unexec,1: wait,2: exec,3: finish"
group.long 0x458++0x03
line.long 0x00 "RTTCNT14,"
hexmask.long 0x00 0.--31. 1. "Stop,WDT (high counter) stop value"
group.long 0x4A0++0x03
line.long 0x00 "SLFRVS14,"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved"
hexmask.long.tbyte 0x00 0.--19. 1. "REVERS,Expected value reverse for Self-Check SISR"
group.long 0x4A4++0x03
line.long 0x00 "SLFRST14,In case of the SLFR bits of the RTTRSTT register is 1B'1 SCNT bit returns to 1"
rbitfld.long 0x00 26.--31. "SCNT,Self-Check counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 24.--25. "STS,Self-Check status" "0: unexec,1: exec,?,3: finish"
newline
hexmask.long.tbyte 0x00 1.--23. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "STR,Self -Check Result" "0: Pass,1: Fail"
group.long 0x4C0++0x03
line.long 0x00 "ERRSET14,"
hexmask.long 0x00 3.--31. 1. "Reserved_3,Reserved"
bitfld.long 0x00 2. "DSB,Dummy set BUS-Error (set of fbc_rt_safetyerr)" "0,1"
newline
bitfld.long 0x00 1. "DST,Dummy set Time out (set of fbc_rt_overerr)" "0,1"
bitfld.long 0x00 0. "DSF,Dummy set Fail (set of fbc_rt_fail)" "0,1"
tree.end
tree "FUNCTIONAL_SAFETY_INST_14"
base ad:0xFF875000
group.long 0x00++0x03
line.long 0x00 "RTTEX15,SLFR and SLFE bit of the RTTEX are effective only when KCD bit is H'F1"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved" "0,1,2,3"
bitfld.long 0x00 29. "SLFR,Self-Check Counter Reset for field BIST activator" "0: Counter Reset,1: Counter not Reset"
newline
bitfld.long 0x00 28. "SLFE,Execution of Self-Check for Field BIST activator" "0: Not Execution of Self-Check for Field BIST,1: Execution of Self-Check for Field BIST.."
rbitfld.long 0x00 24.--27. "Reserved_24,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.byte 0x00 16.--23. 1. "KCD,Key Code H'5A: Effective execution of Run Time Test H'F1: Effective execution of Self-Check for field BIST activator"
rbitfld.long 0x00 11.--15. "Reserved_11,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "STM,Single Step Test Mode" "?,1: LBIST,2: MBIST,3: SCAN,?..."
bitfld.long 0x00 6.--7. "INTM,Interrupt mask" "0: non mask *1,?,2: Only at the time of the fail(fba_rt_finish are,?..."
newline
bitfld.long 0x00 5. "SSZ,SCAN Pattern size Valid only when STM=011" "0: 32bit mode,1: 16bit mode"
bitfld.long 0x00 4. "TR,Select the value of the timer" "0: ROM,1: register"
newline
bitfld.long 0x00 3. "WM,Wfi mask" "0: not mask,1: mask"
bitfld.long 0x00 2. "TM,Mask the judgment of timer" "0: not mask,1: mask"
newline
bitfld.long 0x00 1. "STP,Single Step Mode" "0: ROM batch mode,1: Single Step Mode"
bitfld.long 0x00 0. "EX,Execution of Runtime Test" "0: Not Execution of Runtime Test,1: Execution of Runtime Test"
group.long 0x04++0x03
line.long 0x00 "RTTMI115,"
rbitfld.long 0x00 27.--31. "Reserved_27,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 24.--26. "RPROT,Protection type of MEMORY" "0: Unprivileged access,1: Privileged access,?..."
newline
hexmask.long.byte 0x00 16.--23. 1. "MADDR_upper,Memory upper address[39:32] that stores the SCAN pattern"
hexmask.long.word 0x00 0.--15. 1. "MUNIT,Number of units (1 unit = 128 Byte)"
group.long 0x08++0x03
line.long 0x00 "RTTMI215,"
hexmask.long 0x00 0.--31. 1. "MADDR,Memory address that stores the SCAN pattern"
group.long 0x0C++0x03
line.long 0x00 "RTTSISR115,"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved"
hexmask.long.tbyte 0x00 0.--19. 1. "SISR1,SISR-TEST#1 Expected value"
group.long 0x14++0x03
line.long 0x00 "RTTUC15,"
hexmask.long 0x00 0.--31. 1. "U_WDT,Upper counter of Watchdog Timer"
group.long 0x18++0x03
line.long 0x00 "RTTDC15,"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved"
hexmask.long.word 0x00 0.--15. 1. "L_WDT,Lower counter of Watchdog Timer"
group.long 0x80++0x03
line.long 0x00 "RTTSET0_15,"
hexmask.long 0x00 0.--31. 1. "test_clock,Test setting input"
group.long 0x84++0x03
line.long 0x00 "RTTSET1_15,"
hexmask.long 0x00 2.--31. 1. "Reserved_2,Reserved"
bitfld.long 0x00 1. "reset,Test setting input" "0: Reset test disabled,1: Reset test enabled"
newline
bitfld.long 0x00 0. "tt,Test setting input" "0: Selected other clock,1: Selected test clock for test Domain"
group.long 0x88++0x03
line.long 0x00 "RTTSET2_15,"
hexmask.long 0x00 0.--31. 1. "hold0,Test setting input"
group.long 0x8C++0x03
line.long 0x00 "RTTSET3_15,"
hexmask.long.tbyte 0x00 8.--31. 1. "hold1,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "hold0,Test setting input"
group.long 0x90++0x03
line.long 0x00 "RTTSET4_15,"
hexmask.long.word 0x00 16.--31. 1. "hold2,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "hold1,Test setting input"
group.long 0x94++0x03
line.long 0x00 "RTTSET5_15,"
hexmask.long.byte 0x00 24.--31. 1. "hold3,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "hold2,Test setting input"
group.long 0x98++0x03
line.long 0x00 "RTTSET6_15,"
hexmask.long 0x00 0.--31. 1. "hold3,Test setting input"
group.long 0x9C++0x03
line.long 0x00 "RTTSET7_15,"
hexmask.long 0x00 0.--31. 1. "toggle0,Test setting input"
group.long 0xA0++0x03
line.long 0x00 "RTTSET8_15,"
hexmask.long.tbyte 0x00 8.--31. 1. "toggle1,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "toggle0,Test setting input"
group.long 0xA4++0x03
line.long 0x00 "RTTSET9_15,"
hexmask.long.word 0x00 16.--31. 1. "toggle2,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "toggle1,Test setting input"
group.long 0xA8++0x03
line.long 0x00 "RTTSET10_15,"
hexmask.long.byte 0x00 24.--31. 1. "toggle3,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "toggle2,Test setting input"
group.long 0xAC++0x03
line.long 0x00 "RTTSET11_15,"
hexmask.long 0x00 0.--31. 1. "toggle3,Test setting input"
group.long 0xB0++0x03
line.long 0x00 "RTTSET12_15,"
hexmask.long 0x00 0.--31. 1. "switching0,Test setting input"
group.long 0xB4++0x03
line.long 0x00 "RTTSET13_15,"
hexmask.long.tbyte 0x00 8.--31. 1. "switching1,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "switching0,Test setting input"
group.long 0xB8++0x03
line.long 0x00 "RTTSET14_15,"
hexmask.long.word 0x00 16.--31. 1. "switching2,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "switching1,Test setting input"
group.long 0xBC++0x03
line.long 0x00 "RTTSET15_15,"
hexmask.long.byte 0x00 24.--31. 1. "switching3,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "switching2,Test setting input"
group.long 0xC0++0x03
line.long 0x00 "RTTSET16_15,"
hexmask.long 0x00 0.--31. 1. "switching3,Test setting input"
group.long 0xC4++0x03
line.long 0x00 "RTTSET17_15,"
hexmask.long 0x00 0.--31. 1. "hold4,Test setting input"
group.long 0xC8++0x03
line.long 0x00 "RTTSET18_15,"
hexmask.long.tbyte 0x00 8.--31. 1. "hold5,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "hold4,Test setting input"
group.long 0xCC++0x03
line.long 0x00 "RTTSET19_15,"
hexmask.long.word 0x00 16.--31. 1. "hold6,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "hold5,Test setting input"
group.long 0xD0++0x03
line.long 0x00 "RTTSET20_15,"
hexmask.long.byte 0x00 24.--31. 1. "hold7,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "hold6,Test setting input"
group.long 0xD4++0x03
line.long 0x00 "RTTSET21_15,"
hexmask.long 0x00 0.--31. 1. "hold7,Test setting input"
group.long 0xD8++0x03
line.long 0x00 "RTTSET22_15,"
hexmask.long 0x00 0.--31. 1. "toggle4,Test setting input"
group.long 0xDC++0x03
line.long 0x00 "RTTSET23_15,"
hexmask.long.tbyte 0x00 8.--31. 1. "toggle5,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "toggle4,Test setting input"
group.long 0xE0++0x03
line.long 0x00 "RTTSET24_15,"
hexmask.long.word 0x00 16.--31. 1. "toggle6,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "toggle5,Test setting input"
group.long 0xE4++0x03
line.long 0x00 "RTTSET25_15,"
hexmask.long.byte 0x00 24.--31. 1. "toggle7,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "toggle6,Test setting input"
group.long 0xE8++0x03
line.long 0x00 "RTTSET26_15,"
hexmask.long 0x00 0.--31. 1. "toggle7,Test setting input"
group.long 0xEC++0x03
line.long 0x00 "RTTSET27_15,"
hexmask.long 0x00 0.--31. 1. "switching4,Test setting input"
group.long 0xF0++0x03
line.long 0x00 "RTTSET28_15,"
hexmask.long.tbyte 0x00 8.--31. 1. "switching5,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "switching4,Test setting input"
group.long 0xF4++0x03
line.long 0x00 "RTTSET29_15,"
hexmask.long.word 0x00 16.--31. 1. "switching6,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "switching5,Test setting input"
group.long 0xF8++0x03
line.long 0x00 "RTTSET30_15,"
hexmask.long.byte 0x00 24.--31. 1. "switching7,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "switching6,Test setting input"
group.long 0xFC++0x03
line.long 0x00 "RTTSET31_15,"
hexmask.long 0x00 0.--31. 1. "switching7,Test setting input"
group.long 0x100++0x03
line.long 0x00 "RTTSET32_15,"
hexmask.long 0x00 0.--31. 1. "clknum_31_0,Test setting input"
group.long 0x104++0x03
line.long 0x00 "RTTSET33_15,"
hexmask.long 0x00 0.--31. 1. "Testmat_31_0,Test setting input"
group.long 0x108++0x03
line.long 0x00 "RTTSET34_15,"
hexmask.long 0x00 0.--31. 1. "Testmat_63_32,Test setting input"
group.long 0x10C++0x03
line.long 0x00 "RTTSET35_15,"
hexmask.long 0x00 0.--31. 1. "Testmat_95_64,Test setting input"
group.long 0x110++0x03
line.long 0x00 "RTTSET36_15,"
hexmask.long 0x00 0.--31. 1. "Testmat_127_96,Test setting input"
group.long 0x114++0x03
line.long 0x00 "RTTSET37_15,"
hexmask.long 0x00 0.--31. 1. "Testmat_159_128,Test setting input"
group.long 0x118++0x03
line.long 0x00 "RTTSET38_15,"
hexmask.long 0x00 0.--31. 1. "Testmat_191_160,Test setting input"
group.long 0x11C++0x03
line.long 0x00 "RTTSET39_15,"
hexmask.long 0x00 0.--31. 1. "Testmat_223_192,Test setting input"
group.long 0x120++0x03
line.long 0x00 "RTTSET40_15,"
hexmask.long 0x00 0.--31. 1. "Testmat_255_224,Test setting input"
group.long 0x124++0x03
line.long 0x00 "RTTSET41_15,"
hexmask.long.word 0x00 18.--31. 1. "Reserved_18,Reserved The bit or field is readable only"
hexmask.long.byte 0x00 10.--17. 1. "apbsel,Test setting input"
newline
bitfld.long 0x00 6.--9. "mbsel,Test setting input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--5. "coreselect,Test setting input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x128++0x03
line.long 0x00 "RTTSET42_15,"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved The bit or field is readable only" "0,1,2,3"
hexmask.long.word 0x00 16.--29. 1. "Y_address,Test setting input"
newline
rbitfld.long 0x00 14.--15. "Reserved_14,Reserved The bit or field is readable only" "0,1,2,3"
hexmask.long.word 0x00 0.--13. 1. "X_address,Test setting input"
group.long 0x12C++0x03
line.long 0x00 "RTTSET43_15,"
rbitfld.long 0x00 31. "Reserved_31,Reserved The bit or field is readable only" "0,1"
hexmask.long.tbyte 0x00 14.--30. 1. "XY,Test setting input"
newline
hexmask.long.word 0x00 0.--13. 1. "Z_address,Test setting input"
group.long 0x130++0x03
line.long 0x00 "RTTSET44_15,"
rbitfld.long 0x00 26.--31. "Reserved_26,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x00 16.--25. 1. "scanchain,Test setting input for hardware-SCAN"
newline
hexmask.long.word 0x00 0.--15. 1. "scanpat,Test setting input for hardware-SCAN"
group.long 0x400++0x03
line.long 0x00 "PSTRSTT15,"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved"
rbitfld.long 0x00 12. "R_rst_T,BIST Redundant result" "0: pass,1: fail"
newline
rbitfld.long 0x00 11. "Reserved_11,Reserved" "0,1"
rbitfld.long 0x00 8.--10. "error_T,BIST error" "0: Pass,1: Fail,2: TimeOut,?,4: BUS error,?..."
newline
rbitfld.long 0x00 4.--7. "testnum_T,Number of tests" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 2.--3. "status_R,BIST Redundant status (Safety function)" "0: unexec,1: wait,2: exec,3: finish"
newline
rbitfld.long 0x00 0.--1. "status_T,BIST status" "0: unexec,1: wait,2: exec,3: finish"
group.long 0x440++0x03
line.long 0x00 "PSTCNT15,"
hexmask.long 0x00 0.--31. 1. "Stop,FieldBIST internal WDT (high counter) stop value"
group.long 0x444++0x03
line.long 0x00 "RTTRSTT15,When status_T in the RTTRSTT register is"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved" "0,1,2,3"
rbitfld.long 0x00 29. "IL_flag2,Runtime Test Illegal suspension flag-2" "0,1"
newline
rbitfld.long 0x00 28. "IL_flag1,Runtime Test Illegal suspension flag-1" "0,1"
rbitfld.long 0x00 27. "CONDF,Debug monitor of FieldBIST condition" "0: not response,1: responded"
newline
rbitfld.long 0x00 24.--26. "BUS_cond,Debug code of BUS condition" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 13.--23. 1. "Reserved_13,Reserved"
newline
rbitfld.long 0x00 12. "R_rst_T,BIST Redundant result (Safety function)" "0: Pass,1: Fail"
rbitfld.long 0x00 11. "Achk,Debug code of address check" "0: normal,1: warning"
newline
rbitfld.long 0x00 8.--10. "error_T,BIST error" "0: Pass,1: Fail,2: TimeOut,?,4: BUS error,?..."
rbitfld.long 0x00 4.--7. "testnum_T,Number of tests" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 2.--3. "R_status_T,BIST redundant status" "0: unexec,1: wait,2: exec,3: finish"
rbitfld.long 0x00 0.--1. "status_T,BIST status" "0: unexec,1: wait,2: exec,3: finish"
group.long 0x458++0x03
line.long 0x00 "RTTCNT15,"
hexmask.long 0x00 0.--31. 1. "Stop,WDT (high counter) stop value"
group.long 0x4A0++0x03
line.long 0x00 "SLFRVS15,"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved"
hexmask.long.tbyte 0x00 0.--19. 1. "REVERS,Expected value reverse for Self-Check SISR"
group.long 0x4A4++0x03
line.long 0x00 "SLFRST15,In case of the SLFR bits of the RTTRSTT register is 1B'1 SCNT bit returns to 1"
rbitfld.long 0x00 26.--31. "SCNT,Self-Check counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 24.--25. "STS,Self-Check status" "0: unexec,1: exec,?,3: finish"
newline
hexmask.long.tbyte 0x00 1.--23. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "STR,Self -Check Result" "0: Pass,1: Fail"
group.long 0x4C0++0x03
line.long 0x00 "ERRSET15,"
hexmask.long 0x00 3.--31. 1. "Reserved_3,Reserved"
bitfld.long 0x00 2. "DSB,Dummy set BUS-Error (set of fbc_rt_safetyerr)" "0,1"
newline
bitfld.long 0x00 1. "DST,Dummy set Time out (set of fbc_rt_overerr)" "0,1"
bitfld.long 0x00 0. "DSF,Dummy set Fail (set of fbc_rt_fail)" "0,1"
tree.end
tree "FUNCTIONAL_SAFETY_INST_15"
base ad:0xFF859000
group.long 0x00++0x03
line.long 0x00 "RTTEX16,SLFR and SLFE bit of the RTTEX are effective only when KCD bit is H'F1"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved" "0,1,2,3"
bitfld.long 0x00 29. "SLFR,Self-Check Counter Reset for field BIST activator" "0: Counter Reset,1: Counter not Reset"
newline
bitfld.long 0x00 28. "SLFE,Execution of Self-Check for Field BIST activator" "0: Not Execution of Self-Check for Field BIST,1: Execution of Self-Check for Field BIST.."
rbitfld.long 0x00 24.--27. "Reserved_24,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.byte 0x00 16.--23. 1. "KCD,Key Code H'5A: Effective execution of Run Time Test H'F1: Effective execution of Self-Check for field BIST activator"
rbitfld.long 0x00 11.--15. "Reserved_11,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "STM,Single Step Test Mode" "?,1: LBIST,2: MBIST,3: SCAN,?..."
bitfld.long 0x00 6.--7. "INTM,Interrupt mask" "0: non mask *1,?,2: Only at the time of the fail(fba_rt_finish are,?..."
newline
bitfld.long 0x00 5. "SSZ,SCAN Pattern size Valid only when STM=011" "0: 32bit mode,1: 16bit mode"
bitfld.long 0x00 4. "TR,Select the value of the timer" "0: ROM,1: register"
newline
bitfld.long 0x00 3. "WM,Wfi mask" "0: not mask,1: mask"
bitfld.long 0x00 2. "TM,Mask the judgment of timer" "0: not mask,1: mask"
newline
bitfld.long 0x00 1. "STP,Single Step Mode" "0: ROM batch mode,1: Single Step Mode"
bitfld.long 0x00 0. "EX,Execution of Runtime Test" "0: Not Execution of Runtime Test,1: Execution of Runtime Test"
group.long 0x04++0x03
line.long 0x00 "RTTMI116,"
rbitfld.long 0x00 27.--31. "Reserved_27,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 24.--26. "RPROT,Protection type of MEMORY" "0: Unprivileged access,1: Privileged access,?..."
newline
hexmask.long.byte 0x00 16.--23. 1. "MADDR_upper,Memory upper address[39:32] that stores the SCAN pattern"
hexmask.long.word 0x00 0.--15. 1. "MUNIT,Number of units (1 unit = 128 Byte)"
group.long 0x08++0x03
line.long 0x00 "RTTMI216,"
hexmask.long 0x00 0.--31. 1. "MADDR,Memory address that stores the SCAN pattern"
group.long 0x0C++0x03
line.long 0x00 "RTTSISR116,"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved"
hexmask.long.tbyte 0x00 0.--19. 1. "SISR1,SISR-TEST#1 Expected value"
group.long 0x14++0x03
line.long 0x00 "RTTUC16,"
hexmask.long 0x00 0.--31. 1. "U_WDT,Upper counter of Watchdog Timer"
group.long 0x18++0x03
line.long 0x00 "RTTDC16,"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved"
hexmask.long.word 0x00 0.--15. 1. "L_WDT,Lower counter of Watchdog Timer"
group.long 0x80++0x03
line.long 0x00 "RTTSET0_16,"
hexmask.long 0x00 0.--31. 1. "test_clock,Test setting input"
group.long 0x84++0x03
line.long 0x00 "RTTSET1_16,"
hexmask.long 0x00 2.--31. 1. "Reserved_2,Reserved"
bitfld.long 0x00 1. "reset,Test setting input" "0: Reset test disabled,1: Reset test enabled"
newline
bitfld.long 0x00 0. "tt,Test setting input" "0: Selected other clock,1: Selected test clock for test Domain"
group.long 0x88++0x03
line.long 0x00 "RTTSET2_16,"
hexmask.long 0x00 0.--31. 1. "hold0,Test setting input"
group.long 0x8C++0x03
line.long 0x00 "RTTSET3_16,"
hexmask.long.tbyte 0x00 8.--31. 1. "hold1,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "hold0,Test setting input"
group.long 0x90++0x03
line.long 0x00 "RTTSET4_16,"
hexmask.long.word 0x00 16.--31. 1. "hold2,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "hold1,Test setting input"
group.long 0x94++0x03
line.long 0x00 "RTTSET5_16,"
hexmask.long.byte 0x00 24.--31. 1. "hold3,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "hold2,Test setting input"
group.long 0x98++0x03
line.long 0x00 "RTTSET6_16,"
hexmask.long 0x00 0.--31. 1. "hold3,Test setting input"
group.long 0x9C++0x03
line.long 0x00 "RTTSET7_16,"
hexmask.long 0x00 0.--31. 1. "toggle0,Test setting input"
group.long 0xA0++0x03
line.long 0x00 "RTTSET8_16,"
hexmask.long.tbyte 0x00 8.--31. 1. "toggle1,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "toggle0,Test setting input"
group.long 0xA4++0x03
line.long 0x00 "RTTSET9_16,"
hexmask.long.word 0x00 16.--31. 1. "toggle2,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "toggle1,Test setting input"
group.long 0xA8++0x03
line.long 0x00 "RTTSET10_16,"
hexmask.long.byte 0x00 24.--31. 1. "toggle3,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "toggle2,Test setting input"
group.long 0xAC++0x03
line.long 0x00 "RTTSET11_16,"
hexmask.long 0x00 0.--31. 1. "toggle3,Test setting input"
group.long 0xB0++0x03
line.long 0x00 "RTTSET12_16,"
hexmask.long 0x00 0.--31. 1. "switching0,Test setting input"
group.long 0xB4++0x03
line.long 0x00 "RTTSET13_16,"
hexmask.long.tbyte 0x00 8.--31. 1. "switching1,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "switching0,Test setting input"
group.long 0xB8++0x03
line.long 0x00 "RTTSET14_16,"
hexmask.long.word 0x00 16.--31. 1. "switching2,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "switching1,Test setting input"
group.long 0xBC++0x03
line.long 0x00 "RTTSET15_16,"
hexmask.long.byte 0x00 24.--31. 1. "switching3,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "switching2,Test setting input"
group.long 0xC0++0x03
line.long 0x00 "RTTSET16_16,"
hexmask.long 0x00 0.--31. 1. "switching3,Test setting input"
group.long 0xC4++0x03
line.long 0x00 "RTTSET17_16,"
hexmask.long 0x00 0.--31. 1. "hold4,Test setting input"
group.long 0xC8++0x03
line.long 0x00 "RTTSET18_16,"
hexmask.long.tbyte 0x00 8.--31. 1. "hold5,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "hold4,Test setting input"
group.long 0xCC++0x03
line.long 0x00 "RTTSET19_16,"
hexmask.long.word 0x00 16.--31. 1. "hold6,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "hold5,Test setting input"
group.long 0xD0++0x03
line.long 0x00 "RTTSET20_16,"
hexmask.long.byte 0x00 24.--31. 1. "hold7,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "hold6,Test setting input"
group.long 0xD4++0x03
line.long 0x00 "RTTSET21_16,"
hexmask.long 0x00 0.--31. 1. "hold7,Test setting input"
group.long 0xD8++0x03
line.long 0x00 "RTTSET22_16,"
hexmask.long 0x00 0.--31. 1. "toggle4,Test setting input"
group.long 0xDC++0x03
line.long 0x00 "RTTSET23_16,"
hexmask.long.tbyte 0x00 8.--31. 1. "toggle5,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "toggle4,Test setting input"
group.long 0xE0++0x03
line.long 0x00 "RTTSET24_16,"
hexmask.long.word 0x00 16.--31. 1. "toggle6,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "toggle5,Test setting input"
group.long 0xE4++0x03
line.long 0x00 "RTTSET25_16,"
hexmask.long.byte 0x00 24.--31. 1. "toggle7,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "toggle6,Test setting input"
group.long 0xE8++0x03
line.long 0x00 "RTTSET26_16,"
hexmask.long 0x00 0.--31. 1. "toggle7,Test setting input"
group.long 0xEC++0x03
line.long 0x00 "RTTSET27_16,"
hexmask.long 0x00 0.--31. 1. "switching4,Test setting input"
group.long 0xF0++0x03
line.long 0x00 "RTTSET28_16,"
hexmask.long.tbyte 0x00 8.--31. 1. "switching5,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "switching4,Test setting input"
group.long 0xF4++0x03
line.long 0x00 "RTTSET29_16,"
hexmask.long.word 0x00 16.--31. 1. "switching6,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "switching5,Test setting input"
group.long 0xF8++0x03
line.long 0x00 "RTTSET30_16,"
hexmask.long.byte 0x00 24.--31. 1. "switching7,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "switching6,Test setting input"
group.long 0xFC++0x03
line.long 0x00 "RTTSET31_16,"
hexmask.long 0x00 0.--31. 1. "switching7,Test setting input"
group.long 0x100++0x03
line.long 0x00 "RTTSET32_16,"
hexmask.long 0x00 0.--31. 1. "clknum_31_0,Test setting input"
group.long 0x104++0x03
line.long 0x00 "RTTSET33_16,"
hexmask.long 0x00 0.--31. 1. "Testmat_31_0,Test setting input"
group.long 0x108++0x03
line.long 0x00 "RTTSET34_16,"
hexmask.long 0x00 0.--31. 1. "Testmat_63_32,Test setting input"
group.long 0x10C++0x03
line.long 0x00 "RTTSET35_16,"
hexmask.long 0x00 0.--31. 1. "Testmat_95_64,Test setting input"
group.long 0x110++0x03
line.long 0x00 "RTTSET36_16,"
hexmask.long 0x00 0.--31. 1. "Testmat_127_96,Test setting input"
group.long 0x114++0x03
line.long 0x00 "RTTSET37_16,"
hexmask.long 0x00 0.--31. 1. "Testmat_159_128,Test setting input"
group.long 0x118++0x03
line.long 0x00 "RTTSET38_16,"
hexmask.long 0x00 0.--31. 1. "Testmat_191_160,Test setting input"
group.long 0x11C++0x03
line.long 0x00 "RTTSET39_16,"
hexmask.long 0x00 0.--31. 1. "Testmat_223_192,Test setting input"
group.long 0x120++0x03
line.long 0x00 "RTTSET40_16,"
hexmask.long 0x00 0.--31. 1. "Testmat_255_224,Test setting input"
group.long 0x124++0x03
line.long 0x00 "RTTSET41_16,"
hexmask.long.word 0x00 18.--31. 1. "Reserved_18,Reserved The bit or field is readable only"
hexmask.long.byte 0x00 10.--17. 1. "apbsel,Test setting input"
newline
bitfld.long 0x00 6.--9. "mbsel,Test setting input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--5. "coreselect,Test setting input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x128++0x03
line.long 0x00 "RTTSET42_16,"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved The bit or field is readable only" "0,1,2,3"
hexmask.long.word 0x00 16.--29. 1. "Y_address,Test setting input"
newline
rbitfld.long 0x00 14.--15. "Reserved_14,Reserved The bit or field is readable only" "0,1,2,3"
hexmask.long.word 0x00 0.--13. 1. "X_address,Test setting input"
group.long 0x12C++0x03
line.long 0x00 "RTTSET43_16,"
rbitfld.long 0x00 31. "Reserved_31,Reserved The bit or field is readable only" "0,1"
hexmask.long.tbyte 0x00 14.--30. 1. "XY,Test setting input"
newline
hexmask.long.word 0x00 0.--13. 1. "Z_address,Test setting input"
group.long 0x130++0x03
line.long 0x00 "RTTSET44_16,"
rbitfld.long 0x00 26.--31. "Reserved_26,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x00 16.--25. 1. "scanchain,Test setting input for hardware-SCAN"
newline
hexmask.long.word 0x00 0.--15. 1. "scanpat,Test setting input for hardware-SCAN"
group.long 0x400++0x03
line.long 0x00 "PSTRSTT16,"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved"
rbitfld.long 0x00 12. "R_rst_T,BIST Redundant result" "0: pass,1: fail"
newline
rbitfld.long 0x00 11. "Reserved_11,Reserved" "0,1"
rbitfld.long 0x00 8.--10. "error_T,BIST error" "0: Pass,1: Fail,2: TimeOut,?,4: BUS error,?..."
newline
rbitfld.long 0x00 4.--7. "testnum_T,Number of tests" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 2.--3. "status_R,BIST Redundant status (Safety function)" "0: unexec,1: wait,2: exec,3: finish"
newline
rbitfld.long 0x00 0.--1. "status_T,BIST status" "0: unexec,1: wait,2: exec,3: finish"
group.long 0x440++0x03
line.long 0x00 "PSTCNT16,"
hexmask.long 0x00 0.--31. 1. "Stop,FieldBIST internal WDT (high counter) stop value"
group.long 0x444++0x03
line.long 0x00 "RTTRSTT16,When status_T in the RTTRSTT register is"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved" "0,1,2,3"
rbitfld.long 0x00 29. "IL_flag2,Runtime Test Illegal suspension flag-2" "0,1"
newline
rbitfld.long 0x00 28. "IL_flag1,Runtime Test Illegal suspension flag-1" "0,1"
rbitfld.long 0x00 27. "CONDF,Debug monitor of FieldBIST condition" "0: not response,1: responded"
newline
rbitfld.long 0x00 24.--26. "BUS_cond,Debug code of BUS condition" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 13.--23. 1. "Reserved_13,Reserved"
newline
rbitfld.long 0x00 12. "R_rst_T,BIST Redundant result (Safety function)" "0: Pass,1: Fail"
rbitfld.long 0x00 11. "Achk,Debug code of address check" "0: normal,1: warning"
newline
rbitfld.long 0x00 8.--10. "error_T,BIST error" "0: Pass,1: Fail,2: TimeOut,?,4: BUS error,?..."
rbitfld.long 0x00 4.--7. "testnum_T,Number of tests" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 2.--3. "R_status_T,BIST redundant status" "0: unexec,1: wait,2: exec,3: finish"
rbitfld.long 0x00 0.--1. "status_T,BIST status" "0: unexec,1: wait,2: exec,3: finish"
group.long 0x458++0x03
line.long 0x00 "RTTCNT16,"
hexmask.long 0x00 0.--31. 1. "Stop,WDT (high counter) stop value"
group.long 0x4A0++0x03
line.long 0x00 "SLFRVS16,"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved"
hexmask.long.tbyte 0x00 0.--19. 1. "REVERS,Expected value reverse for Self-Check SISR"
group.long 0x4A4++0x03
line.long 0x00 "SLFRST16,In case of the SLFR bits of the RTTRSTT register is 1B'1 SCNT bit returns to 1"
rbitfld.long 0x00 26.--31. "SCNT,Self-Check counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 24.--25. "STS,Self-Check status" "0: unexec,1: exec,?,3: finish"
newline
hexmask.long.tbyte 0x00 1.--23. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "STR,Self -Check Result" "0: Pass,1: Fail"
group.long 0x4C0++0x03
line.long 0x00 "ERRSET16,"
hexmask.long 0x00 3.--31. 1. "Reserved_3,Reserved"
bitfld.long 0x00 2. "DSB,Dummy set BUS-Error (set of fbc_rt_safetyerr)" "0,1"
newline
bitfld.long 0x00 1. "DST,Dummy set Time out (set of fbc_rt_overerr)" "0,1"
bitfld.long 0x00 0. "DSF,Dummy set Fail (set of fbc_rt_fail)" "0,1"
tree.end
tree "FUNCTIONAL_SAFETY_INST_16"
base ad:0xFF85A000
group.long 0x00++0x03
line.long 0x00 "RTTEX17,SLFR and SLFE bit of the RTTEX are effective only when KCD bit is H'F1"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved" "0,1,2,3"
bitfld.long 0x00 29. "SLFR,Self-Check Counter Reset for field BIST activator" "0: Counter Reset,1: Counter not Reset"
newline
bitfld.long 0x00 28. "SLFE,Execution of Self-Check for Field BIST activator" "0: Not Execution of Self-Check for Field BIST,1: Execution of Self-Check for Field BIST.."
rbitfld.long 0x00 24.--27. "Reserved_24,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.byte 0x00 16.--23. 1. "KCD,Key Code H'5A: Effective execution of Run Time Test H'F1: Effective execution of Self-Check for field BIST activator"
rbitfld.long 0x00 11.--15. "Reserved_11,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "STM,Single Step Test Mode" "?,1: LBIST,2: MBIST,3: SCAN,?..."
bitfld.long 0x00 6.--7. "INTM,Interrupt mask" "0: non mask *1,?,2: Only at the time of the fail(fba_rt_finish are,?..."
newline
bitfld.long 0x00 5. "SSZ,SCAN Pattern size Valid only when STM=011" "0: 32bit mode,1: 16bit mode"
bitfld.long 0x00 4. "TR,Select the value of the timer" "0: ROM,1: register"
newline
bitfld.long 0x00 3. "WM,Wfi mask" "0: not mask,1: mask"
bitfld.long 0x00 2. "TM,Mask the judgment of timer" "0: not mask,1: mask"
newline
bitfld.long 0x00 1. "STP,Single Step Mode" "0: ROM batch mode,1: Single Step Mode"
bitfld.long 0x00 0. "EX,Execution of Runtime Test" "0: Not Execution of Runtime Test,1: Execution of Runtime Test"
group.long 0x04++0x03
line.long 0x00 "RTTMI117,"
rbitfld.long 0x00 27.--31. "Reserved_27,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 24.--26. "RPROT,Protection type of MEMORY" "0: Unprivileged access,1: Privileged access,?..."
newline
hexmask.long.byte 0x00 16.--23. 1. "MADDR_upper,Memory upper address[39:32] that stores the SCAN pattern"
hexmask.long.word 0x00 0.--15. 1. "MUNIT,Number of units (1 unit = 128 Byte)"
group.long 0x08++0x03
line.long 0x00 "RTTMI217,"
hexmask.long 0x00 0.--31. 1. "MADDR,Memory address that stores the SCAN pattern"
group.long 0x0C++0x03
line.long 0x00 "RTTSISR117,"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved"
hexmask.long.tbyte 0x00 0.--19. 1. "SISR1,SISR-TEST#1 Expected value"
group.long 0x14++0x03
line.long 0x00 "RTTUC17,"
hexmask.long 0x00 0.--31. 1. "U_WDT,Upper counter of Watchdog Timer"
group.long 0x18++0x03
line.long 0x00 "RTTDC17,"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved"
hexmask.long.word 0x00 0.--15. 1. "L_WDT,Lower counter of Watchdog Timer"
group.long 0x80++0x03
line.long 0x00 "RTTSET0_17,"
hexmask.long 0x00 0.--31. 1. "test_clock,Test setting input"
group.long 0x84++0x03
line.long 0x00 "RTTSET1_17,"
hexmask.long 0x00 2.--31. 1. "Reserved_2,Reserved"
bitfld.long 0x00 1. "reset,Test setting input" "0: Reset test disabled,1: Reset test enabled"
newline
bitfld.long 0x00 0. "tt,Test setting input" "0: Selected other clock,1: Selected test clock for test Domain"
group.long 0x88++0x03
line.long 0x00 "RTTSET2_17,"
hexmask.long 0x00 0.--31. 1. "hold0,Test setting input"
group.long 0x8C++0x03
line.long 0x00 "RTTSET3_17,"
hexmask.long.tbyte 0x00 8.--31. 1. "hold1,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "hold0,Test setting input"
group.long 0x90++0x03
line.long 0x00 "RTTSET4_17,"
hexmask.long.word 0x00 16.--31. 1. "hold2,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "hold1,Test setting input"
group.long 0x94++0x03
line.long 0x00 "RTTSET5_17,"
hexmask.long.byte 0x00 24.--31. 1. "hold3,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "hold2,Test setting input"
group.long 0x98++0x03
line.long 0x00 "RTTSET6_17,"
hexmask.long 0x00 0.--31. 1. "hold3,Test setting input"
group.long 0x9C++0x03
line.long 0x00 "RTTSET7_17,"
hexmask.long 0x00 0.--31. 1. "toggle0,Test setting input"
group.long 0xA0++0x03
line.long 0x00 "RTTSET8_17,"
hexmask.long.tbyte 0x00 8.--31. 1. "toggle1,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "toggle0,Test setting input"
group.long 0xA4++0x03
line.long 0x00 "RTTSET9_17,"
hexmask.long.word 0x00 16.--31. 1. "toggle2,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "toggle1,Test setting input"
group.long 0xA8++0x03
line.long 0x00 "RTTSET10_17,"
hexmask.long.byte 0x00 24.--31. 1. "toggle3,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "toggle2,Test setting input"
group.long 0xAC++0x03
line.long 0x00 "RTTSET11_17,"
hexmask.long 0x00 0.--31. 1. "toggle3,Test setting input"
group.long 0xB0++0x03
line.long 0x00 "RTTSET12_17,"
hexmask.long 0x00 0.--31. 1. "switching0,Test setting input"
group.long 0xB4++0x03
line.long 0x00 "RTTSET13_17,"
hexmask.long.tbyte 0x00 8.--31. 1. "switching1,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "switching0,Test setting input"
group.long 0xB8++0x03
line.long 0x00 "RTTSET14_17,"
hexmask.long.word 0x00 16.--31. 1. "switching2,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "switching1,Test setting input"
group.long 0xBC++0x03
line.long 0x00 "RTTSET15_17,"
hexmask.long.byte 0x00 24.--31. 1. "switching3,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "switching2,Test setting input"
group.long 0xC0++0x03
line.long 0x00 "RTTSET16_17,"
hexmask.long 0x00 0.--31. 1. "switching3,Test setting input"
group.long 0xC4++0x03
line.long 0x00 "RTTSET17_17,"
hexmask.long 0x00 0.--31. 1. "hold4,Test setting input"
group.long 0xC8++0x03
line.long 0x00 "RTTSET18_17,"
hexmask.long.tbyte 0x00 8.--31. 1. "hold5,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "hold4,Test setting input"
group.long 0xCC++0x03
line.long 0x00 "RTTSET19_17,"
hexmask.long.word 0x00 16.--31. 1. "hold6,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "hold5,Test setting input"
group.long 0xD0++0x03
line.long 0x00 "RTTSET20_17,"
hexmask.long.byte 0x00 24.--31. 1. "hold7,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "hold6,Test setting input"
group.long 0xD4++0x03
line.long 0x00 "RTTSET21_17,"
hexmask.long 0x00 0.--31. 1. "hold7,Test setting input"
group.long 0xD8++0x03
line.long 0x00 "RTTSET22_17,"
hexmask.long 0x00 0.--31. 1. "toggle4,Test setting input"
group.long 0xDC++0x03
line.long 0x00 "RTTSET23_17,"
hexmask.long.tbyte 0x00 8.--31. 1. "toggle5,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "toggle4,Test setting input"
group.long 0xE0++0x03
line.long 0x00 "RTTSET24_17,"
hexmask.long.word 0x00 16.--31. 1. "toggle6,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "toggle5,Test setting input"
group.long 0xE4++0x03
line.long 0x00 "RTTSET25_17,"
hexmask.long.byte 0x00 24.--31. 1. "toggle7,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "toggle6,Test setting input"
group.long 0xE8++0x03
line.long 0x00 "RTTSET26_17,"
hexmask.long 0x00 0.--31. 1. "toggle7,Test setting input"
group.long 0xEC++0x03
line.long 0x00 "RTTSET27_17,"
hexmask.long 0x00 0.--31. 1. "switching4,Test setting input"
group.long 0xF0++0x03
line.long 0x00 "RTTSET28_17,"
hexmask.long.tbyte 0x00 8.--31. 1. "switching5,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "switching4,Test setting input"
group.long 0xF4++0x03
line.long 0x00 "RTTSET29_17,"
hexmask.long.word 0x00 16.--31. 1. "switching6,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "switching5,Test setting input"
group.long 0xF8++0x03
line.long 0x00 "RTTSET30_17,"
hexmask.long.byte 0x00 24.--31. 1. "switching7,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "switching6,Test setting input"
group.long 0xFC++0x03
line.long 0x00 "RTTSET31_17,"
hexmask.long 0x00 0.--31. 1. "switching7,Test setting input"
group.long 0x100++0x03
line.long 0x00 "RTTSET32_17,"
hexmask.long 0x00 0.--31. 1. "clknum_31_0,Test setting input"
group.long 0x104++0x03
line.long 0x00 "RTTSET33_17,"
hexmask.long 0x00 0.--31. 1. "Testmat_31_0,Test setting input"
group.long 0x108++0x03
line.long 0x00 "RTTSET34_17,"
hexmask.long 0x00 0.--31. 1. "Testmat_63_32,Test setting input"
group.long 0x10C++0x03
line.long 0x00 "RTTSET35_17,"
hexmask.long 0x00 0.--31. 1. "Testmat_95_64,Test setting input"
group.long 0x110++0x03
line.long 0x00 "RTTSET36_17,"
hexmask.long 0x00 0.--31. 1. "Testmat_127_96,Test setting input"
group.long 0x114++0x03
line.long 0x00 "RTTSET37_17,"
hexmask.long 0x00 0.--31. 1. "Testmat_159_128,Test setting input"
group.long 0x118++0x03
line.long 0x00 "RTTSET38_17,"
hexmask.long 0x00 0.--31. 1. "Testmat_191_160,Test setting input"
group.long 0x11C++0x03
line.long 0x00 "RTTSET39_17,"
hexmask.long 0x00 0.--31. 1. "Testmat_223_192,Test setting input"
group.long 0x120++0x03
line.long 0x00 "RTTSET40_17,"
hexmask.long 0x00 0.--31. 1. "Testmat_255_224,Test setting input"
group.long 0x124++0x03
line.long 0x00 "RTTSET41_17,"
hexmask.long.word 0x00 18.--31. 1. "Reserved_18,Reserved The bit or field is readable only"
hexmask.long.byte 0x00 10.--17. 1. "apbsel,Test setting input"
newline
bitfld.long 0x00 6.--9. "mbsel,Test setting input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--5. "coreselect,Test setting input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x128++0x03
line.long 0x00 "RTTSET42_17,"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved The bit or field is readable only" "0,1,2,3"
hexmask.long.word 0x00 16.--29. 1. "Y_address,Test setting input"
newline
rbitfld.long 0x00 14.--15. "Reserved_14,Reserved The bit or field is readable only" "0,1,2,3"
hexmask.long.word 0x00 0.--13. 1. "X_address,Test setting input"
group.long 0x12C++0x03
line.long 0x00 "RTTSET43_17,"
rbitfld.long 0x00 31. "Reserved_31,Reserved The bit or field is readable only" "0,1"
hexmask.long.tbyte 0x00 14.--30. 1. "XY,Test setting input"
newline
hexmask.long.word 0x00 0.--13. 1. "Z_address,Test setting input"
group.long 0x130++0x03
line.long 0x00 "RTTSET44_17,"
rbitfld.long 0x00 26.--31. "Reserved_26,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x00 16.--25. 1. "scanchain,Test setting input for hardware-SCAN"
newline
hexmask.long.word 0x00 0.--15. 1. "scanpat,Test setting input for hardware-SCAN"
group.long 0x400++0x03
line.long 0x00 "PSTRSTT17,"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved"
rbitfld.long 0x00 12. "R_rst_T,BIST Redundant result" "0: pass,1: fail"
newline
rbitfld.long 0x00 11. "Reserved_11,Reserved" "0,1"
rbitfld.long 0x00 8.--10. "error_T,BIST error" "0: Pass,1: Fail,2: TimeOut,?,4: BUS error,?..."
newline
rbitfld.long 0x00 4.--7. "testnum_T,Number of tests" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 2.--3. "status_R,BIST Redundant status (Safety function)" "0: unexec,1: wait,2: exec,3: finish"
newline
rbitfld.long 0x00 0.--1. "status_T,BIST status" "0: unexec,1: wait,2: exec,3: finish"
group.long 0x440++0x03
line.long 0x00 "PSTCNT17,"
hexmask.long 0x00 0.--31. 1. "Stop,FieldBIST internal WDT (high counter) stop value"
group.long 0x444++0x03
line.long 0x00 "RTTRSTT17,When status_T in the RTTRSTT register is"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved" "0,1,2,3"
rbitfld.long 0x00 29. "IL_flag2,Runtime Test Illegal suspension flag-2" "0,1"
newline
rbitfld.long 0x00 28. "IL_flag1,Runtime Test Illegal suspension flag-1" "0,1"
rbitfld.long 0x00 27. "CONDF,Debug monitor of FieldBIST condition" "0: not response,1: responded"
newline
rbitfld.long 0x00 24.--26. "BUS_cond,Debug code of BUS condition" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 13.--23. 1. "Reserved_13,Reserved"
newline
rbitfld.long 0x00 12. "R_rst_T,BIST Redundant result (Safety function)" "0: Pass,1: Fail"
rbitfld.long 0x00 11. "Achk,Debug code of address check" "0: normal,1: warning"
newline
rbitfld.long 0x00 8.--10. "error_T,BIST error" "0: Pass,1: Fail,2: TimeOut,?,4: BUS error,?..."
rbitfld.long 0x00 4.--7. "testnum_T,Number of tests" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 2.--3. "R_status_T,BIST redundant status" "0: unexec,1: wait,2: exec,3: finish"
rbitfld.long 0x00 0.--1. "status_T,BIST status" "0: unexec,1: wait,2: exec,3: finish"
group.long 0x458++0x03
line.long 0x00 "RTTCNT17,"
hexmask.long 0x00 0.--31. 1. "Stop,WDT (high counter) stop value"
group.long 0x4A0++0x03
line.long 0x00 "SLFRVS17,"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved"
hexmask.long.tbyte 0x00 0.--19. 1. "REVERS,Expected value reverse for Self-Check SISR"
group.long 0x4A4++0x03
line.long 0x00 "SLFRST17,In case of the SLFR bits of the RTTRSTT register is 1B'1 SCNT bit returns to 1"
rbitfld.long 0x00 26.--31. "SCNT,Self-Check counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 24.--25. "STS,Self-Check status" "0: unexec,1: exec,?,3: finish"
newline
hexmask.long.tbyte 0x00 1.--23. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "STR,Self -Check Result" "0: Pass,1: Fail"
group.long 0x4C0++0x03
line.long 0x00 "ERRSET17,"
hexmask.long 0x00 3.--31. 1. "Reserved_3,Reserved"
bitfld.long 0x00 2. "DSB,Dummy set BUS-Error (set of fbc_rt_safetyerr)" "0,1"
newline
bitfld.long 0x00 1. "DST,Dummy set Time out (set of fbc_rt_overerr)" "0,1"
bitfld.long 0x00 0. "DSF,Dummy set Fail (set of fbc_rt_fail)" "0,1"
tree.end
tree "FUNCTIONAL_SAFETY_INST_17"
base ad:0xFF850000
group.long 0x00++0x03
line.long 0x00 "RTTEX18,SLFR and SLFE bit of the RTTEX are effective only when KCD bit is H'F1"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved" "0,1,2,3"
bitfld.long 0x00 29. "SLFR,Self-Check Counter Reset for field BIST activator" "0: Counter Reset,1: Counter not Reset"
newline
bitfld.long 0x00 28. "SLFE,Execution of Self-Check for Field BIST activator" "0: Not Execution of Self-Check for Field BIST,1: Execution of Self-Check for Field BIST.."
rbitfld.long 0x00 24.--27. "Reserved_24,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.byte 0x00 16.--23. 1. "KCD,Key Code H'5A: Effective execution of Run Time Test H'F1: Effective execution of Self-Check for field BIST activator"
rbitfld.long 0x00 11.--15. "Reserved_11,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "STM,Single Step Test Mode" "?,1: LBIST,2: MBIST,3: SCAN,?..."
bitfld.long 0x00 6.--7. "INTM,Interrupt mask" "0: non mask *1,?,2: Only at the time of the fail(fba_rt_finish are,?..."
newline
bitfld.long 0x00 5. "SSZ,SCAN Pattern size Valid only when STM=011" "0: 32bit mode,1: 16bit mode"
bitfld.long 0x00 4. "TR,Select the value of the timer" "0: ROM,1: register"
newline
bitfld.long 0x00 3. "WM,Wfi mask" "0: not mask,1: mask"
bitfld.long 0x00 2. "TM,Mask the judgment of timer" "0: not mask,1: mask"
newline
bitfld.long 0x00 1. "STP,Single Step Mode" "0: ROM batch mode,1: Single Step Mode"
bitfld.long 0x00 0. "EX,Execution of Runtime Test" "0: Not Execution of Runtime Test,1: Execution of Runtime Test"
group.long 0x04++0x03
line.long 0x00 "RTTMI118,"
rbitfld.long 0x00 27.--31. "Reserved_27,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 24.--26. "RPROT,Protection type of MEMORY" "0: Unprivileged access,1: Privileged access,?..."
newline
hexmask.long.byte 0x00 16.--23. 1. "MADDR_upper,Memory upper address[39:32] that stores the SCAN pattern"
hexmask.long.word 0x00 0.--15. 1. "MUNIT,Number of units (1 unit = 128 Byte)"
group.long 0x08++0x03
line.long 0x00 "RTTMI218,"
hexmask.long 0x00 0.--31. 1. "MADDR,Memory address that stores the SCAN pattern"
group.long 0x0C++0x03
line.long 0x00 "RTTSISR118,"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved"
hexmask.long.tbyte 0x00 0.--19. 1. "SISR1,SISR-TEST#1 Expected value"
group.long 0x14++0x03
line.long 0x00 "RTTUC18,"
hexmask.long 0x00 0.--31. 1. "U_WDT,Upper counter of Watchdog Timer"
group.long 0x18++0x03
line.long 0x00 "RTTDC18,"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved"
hexmask.long.word 0x00 0.--15. 1. "L_WDT,Lower counter of Watchdog Timer"
group.long 0x80++0x03
line.long 0x00 "RTTSET0_18,"
hexmask.long 0x00 0.--31. 1. "test_clock,Test setting input"
group.long 0x84++0x03
line.long 0x00 "RTTSET1_18,"
hexmask.long 0x00 2.--31. 1. "Reserved_2,Reserved"
bitfld.long 0x00 1. "reset,Test setting input" "0: Reset test disabled,1: Reset test enabled"
newline
bitfld.long 0x00 0. "tt,Test setting input" "0: Selected other clock,1: Selected test clock for test Domain"
group.long 0x88++0x03
line.long 0x00 "RTTSET2_18,"
hexmask.long 0x00 0.--31. 1. "hold0,Test setting input"
group.long 0x8C++0x03
line.long 0x00 "RTTSET3_18,"
hexmask.long.tbyte 0x00 8.--31. 1. "hold1,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "hold0,Test setting input"
group.long 0x90++0x03
line.long 0x00 "RTTSET4_18,"
hexmask.long.word 0x00 16.--31. 1. "hold2,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "hold1,Test setting input"
group.long 0x94++0x03
line.long 0x00 "RTTSET5_18,"
hexmask.long.byte 0x00 24.--31. 1. "hold3,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "hold2,Test setting input"
group.long 0x98++0x03
line.long 0x00 "RTTSET6_18,"
hexmask.long 0x00 0.--31. 1. "hold3,Test setting input"
group.long 0x9C++0x03
line.long 0x00 "RTTSET7_18,"
hexmask.long 0x00 0.--31. 1. "toggle0,Test setting input"
group.long 0xA0++0x03
line.long 0x00 "RTTSET8_18,"
hexmask.long.tbyte 0x00 8.--31. 1. "toggle1,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "toggle0,Test setting input"
group.long 0xA4++0x03
line.long 0x00 "RTTSET9_18,"
hexmask.long.word 0x00 16.--31. 1. "toggle2,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "toggle1,Test setting input"
group.long 0xA8++0x03
line.long 0x00 "RTTSET10_18,"
hexmask.long.byte 0x00 24.--31. 1. "toggle3,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "toggle2,Test setting input"
group.long 0xAC++0x03
line.long 0x00 "RTTSET11_18,"
hexmask.long 0x00 0.--31. 1. "toggle3,Test setting input"
group.long 0xB0++0x03
line.long 0x00 "RTTSET12_18,"
hexmask.long 0x00 0.--31. 1. "switching0,Test setting input"
group.long 0xB4++0x03
line.long 0x00 "RTTSET13_18,"
hexmask.long.tbyte 0x00 8.--31. 1. "switching1,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "switching0,Test setting input"
group.long 0xB8++0x03
line.long 0x00 "RTTSET14_18,"
hexmask.long.word 0x00 16.--31. 1. "switching2,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "switching1,Test setting input"
group.long 0xBC++0x03
line.long 0x00 "RTTSET15_18,"
hexmask.long.byte 0x00 24.--31. 1. "switching3,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "switching2,Test setting input"
group.long 0xC0++0x03
line.long 0x00 "RTTSET16_18,"
hexmask.long 0x00 0.--31. 1. "switching3,Test setting input"
group.long 0xC4++0x03
line.long 0x00 "RTTSET17_18,"
hexmask.long 0x00 0.--31. 1. "hold4,Test setting input"
group.long 0xC8++0x03
line.long 0x00 "RTTSET18_18,"
hexmask.long.tbyte 0x00 8.--31. 1. "hold5,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "hold4,Test setting input"
group.long 0xCC++0x03
line.long 0x00 "RTTSET19_18,"
hexmask.long.word 0x00 16.--31. 1. "hold6,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "hold5,Test setting input"
group.long 0xD0++0x03
line.long 0x00 "RTTSET20_18,"
hexmask.long.byte 0x00 24.--31. 1. "hold7,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "hold6,Test setting input"
group.long 0xD4++0x03
line.long 0x00 "RTTSET21_18,"
hexmask.long 0x00 0.--31. 1. "hold7,Test setting input"
group.long 0xD8++0x03
line.long 0x00 "RTTSET22_18,"
hexmask.long 0x00 0.--31. 1. "toggle4,Test setting input"
group.long 0xDC++0x03
line.long 0x00 "RTTSET23_18,"
hexmask.long.tbyte 0x00 8.--31. 1. "toggle5,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "toggle4,Test setting input"
group.long 0xE0++0x03
line.long 0x00 "RTTSET24_18,"
hexmask.long.word 0x00 16.--31. 1. "toggle6,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "toggle5,Test setting input"
group.long 0xE4++0x03
line.long 0x00 "RTTSET25_18,"
hexmask.long.byte 0x00 24.--31. 1. "toggle7,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "toggle6,Test setting input"
group.long 0xE8++0x03
line.long 0x00 "RTTSET26_18,"
hexmask.long 0x00 0.--31. 1. "toggle7,Test setting input"
group.long 0xEC++0x03
line.long 0x00 "RTTSET27_18,"
hexmask.long 0x00 0.--31. 1. "switching4,Test setting input"
group.long 0xF0++0x03
line.long 0x00 "RTTSET28_18,"
hexmask.long.tbyte 0x00 8.--31. 1. "switching5,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "switching4,Test setting input"
group.long 0xF4++0x03
line.long 0x00 "RTTSET29_18,"
hexmask.long.word 0x00 16.--31. 1. "switching6,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "switching5,Test setting input"
group.long 0xF8++0x03
line.long 0x00 "RTTSET30_18,"
hexmask.long.byte 0x00 24.--31. 1. "switching7,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "switching6,Test setting input"
group.long 0xFC++0x03
line.long 0x00 "RTTSET31_18,"
hexmask.long 0x00 0.--31. 1. "switching7,Test setting input"
group.long 0x100++0x03
line.long 0x00 "RTTSET32_18,"
hexmask.long 0x00 0.--31. 1. "clknum_31_0,Test setting input"
group.long 0x104++0x03
line.long 0x00 "RTTSET33_18,"
hexmask.long 0x00 0.--31. 1. "Testmat_31_0,Test setting input"
group.long 0x108++0x03
line.long 0x00 "RTTSET34_18,"
hexmask.long 0x00 0.--31. 1. "Testmat_63_32,Test setting input"
group.long 0x10C++0x03
line.long 0x00 "RTTSET35_18,"
hexmask.long 0x00 0.--31. 1. "Testmat_95_64,Test setting input"
group.long 0x110++0x03
line.long 0x00 "RTTSET36_18,"
hexmask.long 0x00 0.--31. 1. "Testmat_127_96,Test setting input"
group.long 0x114++0x03
line.long 0x00 "RTTSET37_18,"
hexmask.long 0x00 0.--31. 1. "Testmat_159_128,Test setting input"
group.long 0x118++0x03
line.long 0x00 "RTTSET38_18,"
hexmask.long 0x00 0.--31. 1. "Testmat_191_160,Test setting input"
group.long 0x11C++0x03
line.long 0x00 "RTTSET39_18,"
hexmask.long 0x00 0.--31. 1. "Testmat_223_192,Test setting input"
group.long 0x120++0x03
line.long 0x00 "RTTSET40_18,"
hexmask.long 0x00 0.--31. 1. "Testmat_255_224,Test setting input"
group.long 0x124++0x03
line.long 0x00 "RTTSET41_18,"
hexmask.long.word 0x00 18.--31. 1. "Reserved_18,Reserved The bit or field is readable only"
hexmask.long.byte 0x00 10.--17. 1. "apbsel,Test setting input"
newline
bitfld.long 0x00 6.--9. "mbsel,Test setting input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--5. "coreselect,Test setting input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x128++0x03
line.long 0x00 "RTTSET42_18,"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved The bit or field is readable only" "0,1,2,3"
hexmask.long.word 0x00 16.--29. 1. "Y_address,Test setting input"
newline
rbitfld.long 0x00 14.--15. "Reserved_14,Reserved The bit or field is readable only" "0,1,2,3"
hexmask.long.word 0x00 0.--13. 1. "X_address,Test setting input"
group.long 0x12C++0x03
line.long 0x00 "RTTSET43_18,"
rbitfld.long 0x00 31. "Reserved_31,Reserved The bit or field is readable only" "0,1"
hexmask.long.tbyte 0x00 14.--30. 1. "XY,Test setting input"
newline
hexmask.long.word 0x00 0.--13. 1. "Z_address,Test setting input"
group.long 0x130++0x03
line.long 0x00 "RTTSET44_18,"
rbitfld.long 0x00 26.--31. "Reserved_26,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x00 16.--25. 1. "scanchain,Test setting input for hardware-SCAN"
newline
hexmask.long.word 0x00 0.--15. 1. "scanpat,Test setting input for hardware-SCAN"
group.long 0x400++0x03
line.long 0x00 "PSTRSTT18,"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved"
rbitfld.long 0x00 12. "R_rst_T,BIST Redundant result" "0: pass,1: fail"
newline
rbitfld.long 0x00 11. "Reserved_11,Reserved" "0,1"
rbitfld.long 0x00 8.--10. "error_T,BIST error" "0: Pass,1: Fail,2: TimeOut,?,4: BUS error,?..."
newline
rbitfld.long 0x00 4.--7. "testnum_T,Number of tests" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 2.--3. "status_R,BIST Redundant status (Safety function)" "0: unexec,1: wait,2: exec,3: finish"
newline
rbitfld.long 0x00 0.--1. "status_T,BIST status" "0: unexec,1: wait,2: exec,3: finish"
group.long 0x440++0x03
line.long 0x00 "PSTCNT18,"
hexmask.long 0x00 0.--31. 1. "Stop,FieldBIST internal WDT (high counter) stop value"
group.long 0x444++0x03
line.long 0x00 "RTTRSTT18,When status_T in the RTTRSTT register is"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved" "0,1,2,3"
rbitfld.long 0x00 29. "IL_flag2,Runtime Test Illegal suspension flag-2" "0,1"
newline
rbitfld.long 0x00 28. "IL_flag1,Runtime Test Illegal suspension flag-1" "0,1"
rbitfld.long 0x00 27. "CONDF,Debug monitor of FieldBIST condition" "0: not response,1: responded"
newline
rbitfld.long 0x00 24.--26. "BUS_cond,Debug code of BUS condition" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 13.--23. 1. "Reserved_13,Reserved"
newline
rbitfld.long 0x00 12. "R_rst_T,BIST Redundant result (Safety function)" "0: Pass,1: Fail"
rbitfld.long 0x00 11. "Achk,Debug code of address check" "0: normal,1: warning"
newline
rbitfld.long 0x00 8.--10. "error_T,BIST error" "0: Pass,1: Fail,2: TimeOut,?,4: BUS error,?..."
rbitfld.long 0x00 4.--7. "testnum_T,Number of tests" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 2.--3. "R_status_T,BIST redundant status" "0: unexec,1: wait,2: exec,3: finish"
rbitfld.long 0x00 0.--1. "status_T,BIST status" "0: unexec,1: wait,2: exec,3: finish"
group.long 0x458++0x03
line.long 0x00 "RTTCNT18,"
hexmask.long 0x00 0.--31. 1. "Stop,WDT (high counter) stop value"
group.long 0x4A0++0x03
line.long 0x00 "SLFRVS18,"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved"
hexmask.long.tbyte 0x00 0.--19. 1. "REVERS,Expected value reverse for Self-Check SISR"
group.long 0x4A4++0x03
line.long 0x00 "SLFRST18,In case of the SLFR bits of the RTTRSTT register is 1B'1 SCNT bit returns to 1"
rbitfld.long 0x00 26.--31. "SCNT,Self-Check counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 24.--25. "STS,Self-Check status" "0: unexec,1: exec,?,3: finish"
newline
hexmask.long.tbyte 0x00 1.--23. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "STR,Self -Check Result" "0: Pass,1: Fail"
group.long 0x4C0++0x03
line.long 0x00 "ERRSET18,"
hexmask.long 0x00 3.--31. 1. "Reserved_3,Reserved"
bitfld.long 0x00 2. "DSB,Dummy set BUS-Error (set of fbc_rt_safetyerr)" "0,1"
newline
bitfld.long 0x00 1. "DST,Dummy set Time out (set of fbc_rt_overerr)" "0,1"
bitfld.long 0x00 0. "DSF,Dummy set Fail (set of fbc_rt_fail)" "0,1"
tree.end
tree "FUNCTIONAL_SAFETY_INST_18"
base ad:0xFF852000
group.long 0x00++0x03
line.long 0x00 "RTTEX19,SLFR and SLFE bit of the RTTEX are effective only when KCD bit is H'F1"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved" "0,1,2,3"
bitfld.long 0x00 29. "SLFR,Self-Check Counter Reset for field BIST activator" "0: Counter Reset,1: Counter not Reset"
newline
bitfld.long 0x00 28. "SLFE,Execution of Self-Check for Field BIST activator" "0: Not Execution of Self-Check for Field BIST,1: Execution of Self-Check for Field BIST.."
rbitfld.long 0x00 24.--27. "Reserved_24,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.byte 0x00 16.--23. 1. "KCD,Key Code H'5A: Effective execution of Run Time Test H'F1: Effective execution of Self-Check for field BIST activator"
rbitfld.long 0x00 11.--15. "Reserved_11,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "STM,Single Step Test Mode" "?,1: LBIST,2: MBIST,3: SCAN,?..."
bitfld.long 0x00 6.--7. "INTM,Interrupt mask" "0: non mask *1,?,2: Only at the time of the fail(fba_rt_finish are,?..."
newline
bitfld.long 0x00 5. "SSZ,SCAN Pattern size Valid only when STM=011" "0: 32bit mode,1: 16bit mode"
bitfld.long 0x00 4. "TR,Select the value of the timer" "0: ROM,1: register"
newline
bitfld.long 0x00 3. "WM,Wfi mask" "0: not mask,1: mask"
bitfld.long 0x00 2. "TM,Mask the judgment of timer" "0: not mask,1: mask"
newline
bitfld.long 0x00 1. "STP,Single Step Mode" "0: ROM batch mode,1: Single Step Mode"
bitfld.long 0x00 0. "EX,Execution of Runtime Test" "0: Not Execution of Runtime Test,1: Execution of Runtime Test"
group.long 0x04++0x03
line.long 0x00 "RTTMI119,"
rbitfld.long 0x00 27.--31. "Reserved_27,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 24.--26. "RPROT,Protection type of MEMORY" "0: Unprivileged access,1: Privileged access,?..."
newline
hexmask.long.byte 0x00 16.--23. 1. "MADDR_upper,Memory upper address[39:32] that stores the SCAN pattern"
hexmask.long.word 0x00 0.--15. 1. "MUNIT,Number of units (1 unit = 128 Byte)"
group.long 0x08++0x03
line.long 0x00 "RTTMI219,"
hexmask.long 0x00 0.--31. 1. "MADDR,Memory address that stores the SCAN pattern"
group.long 0x0C++0x03
line.long 0x00 "RTTSISR119,"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved"
hexmask.long.tbyte 0x00 0.--19. 1. "SISR1,SISR-TEST#1 Expected value"
group.long 0x14++0x03
line.long 0x00 "RTTUC19,"
hexmask.long 0x00 0.--31. 1. "U_WDT,Upper counter of Watchdog Timer"
group.long 0x18++0x03
line.long 0x00 "RTTDC19,"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved"
hexmask.long.word 0x00 0.--15. 1. "L_WDT,Lower counter of Watchdog Timer"
group.long 0x80++0x03
line.long 0x00 "RTTSET0_19,"
hexmask.long 0x00 0.--31. 1. "test_clock,Test setting input"
group.long 0x84++0x03
line.long 0x00 "RTTSET1_19,"
hexmask.long 0x00 2.--31. 1. "Reserved_2,Reserved"
bitfld.long 0x00 1. "reset,Test setting input" "0: Reset test disabled,1: Reset test enabled"
newline
bitfld.long 0x00 0. "tt,Test setting input" "0: Selected other clock,1: Selected test clock for test Domain"
group.long 0x88++0x03
line.long 0x00 "RTTSET2_19,"
hexmask.long 0x00 0.--31. 1. "hold0,Test setting input"
group.long 0x8C++0x03
line.long 0x00 "RTTSET3_19,"
hexmask.long.tbyte 0x00 8.--31. 1. "hold1,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "hold0,Test setting input"
group.long 0x90++0x03
line.long 0x00 "RTTSET4_19,"
hexmask.long.word 0x00 16.--31. 1. "hold2,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "hold1,Test setting input"
group.long 0x94++0x03
line.long 0x00 "RTTSET5_19,"
hexmask.long.byte 0x00 24.--31. 1. "hold3,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "hold2,Test setting input"
group.long 0x98++0x03
line.long 0x00 "RTTSET6_19,"
hexmask.long 0x00 0.--31. 1. "hold3,Test setting input"
group.long 0x9C++0x03
line.long 0x00 "RTTSET7_19,"
hexmask.long 0x00 0.--31. 1. "toggle0,Test setting input"
group.long 0xA0++0x03
line.long 0x00 "RTTSET8_19,"
hexmask.long.tbyte 0x00 8.--31. 1. "toggle1,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "toggle0,Test setting input"
group.long 0xA4++0x03
line.long 0x00 "RTTSET9_19,"
hexmask.long.word 0x00 16.--31. 1. "toggle2,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "toggle1,Test setting input"
group.long 0xA8++0x03
line.long 0x00 "RTTSET10_19,"
hexmask.long.byte 0x00 24.--31. 1. "toggle3,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "toggle2,Test setting input"
group.long 0xAC++0x03
line.long 0x00 "RTTSET11_19,"
hexmask.long 0x00 0.--31. 1. "toggle3,Test setting input"
group.long 0xB0++0x03
line.long 0x00 "RTTSET12_19,"
hexmask.long 0x00 0.--31. 1. "switching0,Test setting input"
group.long 0xB4++0x03
line.long 0x00 "RTTSET13_19,"
hexmask.long.tbyte 0x00 8.--31. 1. "switching1,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "switching0,Test setting input"
group.long 0xB8++0x03
line.long 0x00 "RTTSET14_19,"
hexmask.long.word 0x00 16.--31. 1. "switching2,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "switching1,Test setting input"
group.long 0xBC++0x03
line.long 0x00 "RTTSET15_19,"
hexmask.long.byte 0x00 24.--31. 1. "switching3,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "switching2,Test setting input"
group.long 0xC0++0x03
line.long 0x00 "RTTSET16_19,"
hexmask.long 0x00 0.--31. 1. "switching3,Test setting input"
group.long 0xC4++0x03
line.long 0x00 "RTTSET17_19,"
hexmask.long 0x00 0.--31. 1. "hold4,Test setting input"
group.long 0xC8++0x03
line.long 0x00 "RTTSET18_19,"
hexmask.long.tbyte 0x00 8.--31. 1. "hold5,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "hold4,Test setting input"
group.long 0xCC++0x03
line.long 0x00 "RTTSET19_19,"
hexmask.long.word 0x00 16.--31. 1. "hold6,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "hold5,Test setting input"
group.long 0xD0++0x03
line.long 0x00 "RTTSET20_19,"
hexmask.long.byte 0x00 24.--31. 1. "hold7,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "hold6,Test setting input"
group.long 0xD4++0x03
line.long 0x00 "RTTSET21_19,"
hexmask.long 0x00 0.--31. 1. "hold7,Test setting input"
group.long 0xD8++0x03
line.long 0x00 "RTTSET22_19,"
hexmask.long 0x00 0.--31. 1. "toggle4,Test setting input"
group.long 0xDC++0x03
line.long 0x00 "RTTSET23_19,"
hexmask.long.tbyte 0x00 8.--31. 1. "toggle5,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "toggle4,Test setting input"
group.long 0xE0++0x03
line.long 0x00 "RTTSET24_19,"
hexmask.long.word 0x00 16.--31. 1. "toggle6,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "toggle5,Test setting input"
group.long 0xE4++0x03
line.long 0x00 "RTTSET25_19,"
hexmask.long.byte 0x00 24.--31. 1. "toggle7,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "toggle6,Test setting input"
group.long 0xE8++0x03
line.long 0x00 "RTTSET26_19,"
hexmask.long 0x00 0.--31. 1. "toggle7,Test setting input"
group.long 0xEC++0x03
line.long 0x00 "RTTSET27_19,"
hexmask.long 0x00 0.--31. 1. "switching4,Test setting input"
group.long 0xF0++0x03
line.long 0x00 "RTTSET28_19,"
hexmask.long.tbyte 0x00 8.--31. 1. "switching5,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "switching4,Test setting input"
group.long 0xF4++0x03
line.long 0x00 "RTTSET29_19,"
hexmask.long.word 0x00 16.--31. 1. "switching6,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "switching5,Test setting input"
group.long 0xF8++0x03
line.long 0x00 "RTTSET30_19,"
hexmask.long.byte 0x00 24.--31. 1. "switching7,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "switching6,Test setting input"
group.long 0xFC++0x03
line.long 0x00 "RTTSET31_19,"
hexmask.long 0x00 0.--31. 1. "switching7,Test setting input"
group.long 0x100++0x03
line.long 0x00 "RTTSET32_19,"
hexmask.long 0x00 0.--31. 1. "clknum_31_0,Test setting input"
group.long 0x104++0x03
line.long 0x00 "RTTSET33_19,"
hexmask.long 0x00 0.--31. 1. "Testmat_31_0,Test setting input"
group.long 0x108++0x03
line.long 0x00 "RTTSET34_19,"
hexmask.long 0x00 0.--31. 1. "Testmat_63_32,Test setting input"
group.long 0x10C++0x03
line.long 0x00 "RTTSET35_19,"
hexmask.long 0x00 0.--31. 1. "Testmat_95_64,Test setting input"
group.long 0x110++0x03
line.long 0x00 "RTTSET36_19,"
hexmask.long 0x00 0.--31. 1. "Testmat_127_96,Test setting input"
group.long 0x114++0x03
line.long 0x00 "RTTSET37_19,"
hexmask.long 0x00 0.--31. 1. "Testmat_159_128,Test setting input"
group.long 0x118++0x03
line.long 0x00 "RTTSET38_19,"
hexmask.long 0x00 0.--31. 1. "Testmat_191_160,Test setting input"
group.long 0x11C++0x03
line.long 0x00 "RTTSET39_19,"
hexmask.long 0x00 0.--31. 1. "Testmat_223_192,Test setting input"
group.long 0x120++0x03
line.long 0x00 "RTTSET40_19,"
hexmask.long 0x00 0.--31. 1. "Testmat_255_224,Test setting input"
group.long 0x124++0x03
line.long 0x00 "RTTSET41_19,"
hexmask.long.word 0x00 18.--31. 1. "Reserved_18,Reserved The bit or field is readable only"
hexmask.long.byte 0x00 10.--17. 1. "apbsel,Test setting input"
newline
bitfld.long 0x00 6.--9. "mbsel,Test setting input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--5. "coreselect,Test setting input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x128++0x03
line.long 0x00 "RTTSET42_19,"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved The bit or field is readable only" "0,1,2,3"
hexmask.long.word 0x00 16.--29. 1. "Y_address,Test setting input"
newline
rbitfld.long 0x00 14.--15. "Reserved_14,Reserved The bit or field is readable only" "0,1,2,3"
hexmask.long.word 0x00 0.--13. 1. "X_address,Test setting input"
group.long 0x12C++0x03
line.long 0x00 "RTTSET43_19,"
rbitfld.long 0x00 31. "Reserved_31,Reserved The bit or field is readable only" "0,1"
hexmask.long.tbyte 0x00 14.--30. 1. "XY,Test setting input"
newline
hexmask.long.word 0x00 0.--13. 1. "Z_address,Test setting input"
group.long 0x130++0x03
line.long 0x00 "RTTSET44_19,"
rbitfld.long 0x00 26.--31. "Reserved_26,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x00 16.--25. 1. "scanchain,Test setting input for hardware-SCAN"
newline
hexmask.long.word 0x00 0.--15. 1. "scanpat,Test setting input for hardware-SCAN"
group.long 0x400++0x03
line.long 0x00 "PSTRSTT19,"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved"
rbitfld.long 0x00 12. "R_rst_T,BIST Redundant result" "0: pass,1: fail"
newline
rbitfld.long 0x00 11. "Reserved_11,Reserved" "0,1"
rbitfld.long 0x00 8.--10. "error_T,BIST error" "0: Pass,1: Fail,2: TimeOut,?,4: BUS error,?..."
newline
rbitfld.long 0x00 4.--7. "testnum_T,Number of tests" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 2.--3. "status_R,BIST Redundant status (Safety function)" "0: unexec,1: wait,2: exec,3: finish"
newline
rbitfld.long 0x00 0.--1. "status_T,BIST status" "0: unexec,1: wait,2: exec,3: finish"
group.long 0x440++0x03
line.long 0x00 "PSTCNT19,"
hexmask.long 0x00 0.--31. 1. "Stop,FieldBIST internal WDT (high counter) stop value"
group.long 0x444++0x03
line.long 0x00 "RTTRSTT19,When status_T in the RTTRSTT register is"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved" "0,1,2,3"
rbitfld.long 0x00 29. "IL_flag2,Runtime Test Illegal suspension flag-2" "0,1"
newline
rbitfld.long 0x00 28. "IL_flag1,Runtime Test Illegal suspension flag-1" "0,1"
rbitfld.long 0x00 27. "CONDF,Debug monitor of FieldBIST condition" "0: not response,1: responded"
newline
rbitfld.long 0x00 24.--26. "BUS_cond,Debug code of BUS condition" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 13.--23. 1. "Reserved_13,Reserved"
newline
rbitfld.long 0x00 12. "R_rst_T,BIST Redundant result (Safety function)" "0: Pass,1: Fail"
rbitfld.long 0x00 11. "Achk,Debug code of address check" "0: normal,1: warning"
newline
rbitfld.long 0x00 8.--10. "error_T,BIST error" "0: Pass,1: Fail,2: TimeOut,?,4: BUS error,?..."
rbitfld.long 0x00 4.--7. "testnum_T,Number of tests" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 2.--3. "R_status_T,BIST redundant status" "0: unexec,1: wait,2: exec,3: finish"
rbitfld.long 0x00 0.--1. "status_T,BIST status" "0: unexec,1: wait,2: exec,3: finish"
group.long 0x458++0x03
line.long 0x00 "RTTCNT19,"
hexmask.long 0x00 0.--31. 1. "Stop,WDT (high counter) stop value"
group.long 0x4A0++0x03
line.long 0x00 "SLFRVS19,"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved"
hexmask.long.tbyte 0x00 0.--19. 1. "REVERS,Expected value reverse for Self-Check SISR"
group.long 0x4A4++0x03
line.long 0x00 "SLFRST19,In case of the SLFR bits of the RTTRSTT register is 1B'1 SCNT bit returns to 1"
rbitfld.long 0x00 26.--31. "SCNT,Self-Check counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 24.--25. "STS,Self-Check status" "0: unexec,1: exec,?,3: finish"
newline
hexmask.long.tbyte 0x00 1.--23. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "STR,Self -Check Result" "0: Pass,1: Fail"
group.long 0x4C0++0x03
line.long 0x00 "ERRSET19,"
hexmask.long 0x00 3.--31. 1. "Reserved_3,Reserved"
bitfld.long 0x00 2. "DSB,Dummy set BUS-Error (set of fbc_rt_safetyerr)" "0,1"
newline
bitfld.long 0x00 1. "DST,Dummy set Time out (set of fbc_rt_overerr)" "0,1"
bitfld.long 0x00 0. "DSF,Dummy set Fail (set of fbc_rt_fail)" "0,1"
tree.end
tree "FUNCTIONAL_SAFETY_INST_19"
base ad:0xFF853000
group.long 0x00++0x03
line.long 0x00 "RTTEX20,SLFR and SLFE bit of the RTTEX are effective only when KCD bit is H'F1"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved" "0,1,2,3"
bitfld.long 0x00 29. "SLFR,Self-Check Counter Reset for field BIST activator" "0: Counter Reset,1: Counter not Reset"
newline
bitfld.long 0x00 28. "SLFE,Execution of Self-Check for Field BIST activator" "0: Not Execution of Self-Check for Field BIST,1: Execution of Self-Check for Field BIST.."
rbitfld.long 0x00 24.--27. "Reserved_24,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.byte 0x00 16.--23. 1. "KCD,Key Code H'5A: Effective execution of Run Time Test H'F1: Effective execution of Self-Check for field BIST activator"
rbitfld.long 0x00 11.--15. "Reserved_11,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "STM,Single Step Test Mode" "?,1: LBIST,2: MBIST,3: SCAN,?..."
bitfld.long 0x00 6.--7. "INTM,Interrupt mask" "0: non mask *1,?,2: Only at the time of the fail(fba_rt_finish are,?..."
newline
bitfld.long 0x00 5. "SSZ,SCAN Pattern size Valid only when STM=011" "0: 32bit mode,1: 16bit mode"
bitfld.long 0x00 4. "TR,Select the value of the timer" "0: ROM,1: register"
newline
bitfld.long 0x00 3. "WM,Wfi mask" "0: not mask,1: mask"
bitfld.long 0x00 2. "TM,Mask the judgment of timer" "0: not mask,1: mask"
newline
bitfld.long 0x00 1. "STP,Single Step Mode" "0: ROM batch mode,1: Single Step Mode"
bitfld.long 0x00 0. "EX,Execution of Runtime Test" "0: Not Execution of Runtime Test,1: Execution of Runtime Test"
group.long 0x04++0x03
line.long 0x00 "RTTMI120,"
rbitfld.long 0x00 27.--31. "Reserved_27,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 24.--26. "RPROT,Protection type of MEMORY" "0: Unprivileged access,1: Privileged access,?..."
newline
hexmask.long.byte 0x00 16.--23. 1. "MADDR_upper,Memory upper address[39:32] that stores the SCAN pattern"
hexmask.long.word 0x00 0.--15. 1. "MUNIT,Number of units (1 unit = 128 Byte)"
group.long 0x08++0x03
line.long 0x00 "RTTMI220,"
hexmask.long 0x00 0.--31. 1. "MADDR,Memory address that stores the SCAN pattern"
group.long 0x0C++0x03
line.long 0x00 "RTTSISR120,"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved"
hexmask.long.tbyte 0x00 0.--19. 1. "SISR1,SISR-TEST#1 Expected value"
group.long 0x14++0x03
line.long 0x00 "RTTUC20,"
hexmask.long 0x00 0.--31. 1. "U_WDT,Upper counter of Watchdog Timer"
group.long 0x18++0x03
line.long 0x00 "RTTDC20,"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved"
hexmask.long.word 0x00 0.--15. 1. "L_WDT,Lower counter of Watchdog Timer"
group.long 0x80++0x03
line.long 0x00 "RTTSET0_20,"
hexmask.long 0x00 0.--31. 1. "test_clock,Test setting input"
group.long 0x84++0x03
line.long 0x00 "RTTSET1_20,"
hexmask.long 0x00 2.--31. 1. "Reserved_2,Reserved"
bitfld.long 0x00 1. "reset,Test setting input" "0: Reset test disabled,1: Reset test enabled"
newline
bitfld.long 0x00 0. "tt,Test setting input" "0: Selected other clock,1: Selected test clock for test Domain"
group.long 0x88++0x03
line.long 0x00 "RTTSET2_20,"
hexmask.long 0x00 0.--31. 1. "hold0,Test setting input"
group.long 0x8C++0x03
line.long 0x00 "RTTSET3_20,"
hexmask.long.tbyte 0x00 8.--31. 1. "hold1,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "hold0,Test setting input"
group.long 0x90++0x03
line.long 0x00 "RTTSET4_20,"
hexmask.long.word 0x00 16.--31. 1. "hold2,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "hold1,Test setting input"
group.long 0x94++0x03
line.long 0x00 "RTTSET5_20,"
hexmask.long.byte 0x00 24.--31. 1. "hold3,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "hold2,Test setting input"
group.long 0x98++0x03
line.long 0x00 "RTTSET6_20,"
hexmask.long 0x00 0.--31. 1. "hold3,Test setting input"
group.long 0x9C++0x03
line.long 0x00 "RTTSET7_20,"
hexmask.long 0x00 0.--31. 1. "toggle0,Test setting input"
group.long 0xA0++0x03
line.long 0x00 "RTTSET8_20,"
hexmask.long.tbyte 0x00 8.--31. 1. "toggle1,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "toggle0,Test setting input"
group.long 0xA4++0x03
line.long 0x00 "RTTSET9_20,"
hexmask.long.word 0x00 16.--31. 1. "toggle2,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "toggle1,Test setting input"
group.long 0xA8++0x03
line.long 0x00 "RTTSET10_20,"
hexmask.long.byte 0x00 24.--31. 1. "toggle3,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "toggle2,Test setting input"
group.long 0xAC++0x03
line.long 0x00 "RTTSET11_20,"
hexmask.long 0x00 0.--31. 1. "toggle3,Test setting input"
group.long 0xB0++0x03
line.long 0x00 "RTTSET12_20,"
hexmask.long 0x00 0.--31. 1. "switching0,Test setting input"
group.long 0xB4++0x03
line.long 0x00 "RTTSET13_20,"
hexmask.long.tbyte 0x00 8.--31. 1. "switching1,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "switching0,Test setting input"
group.long 0xB8++0x03
line.long 0x00 "RTTSET14_20,"
hexmask.long.word 0x00 16.--31. 1. "switching2,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "switching1,Test setting input"
group.long 0xBC++0x03
line.long 0x00 "RTTSET15_20,"
hexmask.long.byte 0x00 24.--31. 1. "switching3,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "switching2,Test setting input"
group.long 0xC0++0x03
line.long 0x00 "RTTSET16_20,"
hexmask.long 0x00 0.--31. 1. "switching3,Test setting input"
group.long 0xC4++0x03
line.long 0x00 "RTTSET17_20,"
hexmask.long 0x00 0.--31. 1. "hold4,Test setting input"
group.long 0xC8++0x03
line.long 0x00 "RTTSET18_20,"
hexmask.long.tbyte 0x00 8.--31. 1. "hold5,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "hold4,Test setting input"
group.long 0xCC++0x03
line.long 0x00 "RTTSET19_20,"
hexmask.long.word 0x00 16.--31. 1. "hold6,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "hold5,Test setting input"
group.long 0xD0++0x03
line.long 0x00 "RTTSET20_20,"
hexmask.long.byte 0x00 24.--31. 1. "hold7,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "hold6,Test setting input"
group.long 0xD4++0x03
line.long 0x00 "RTTSET21_20,"
hexmask.long 0x00 0.--31. 1. "hold7,Test setting input"
group.long 0xD8++0x03
line.long 0x00 "RTTSET22_20,"
hexmask.long 0x00 0.--31. 1. "toggle4,Test setting input"
group.long 0xDC++0x03
line.long 0x00 "RTTSET23_20,"
hexmask.long.tbyte 0x00 8.--31. 1. "toggle5,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "toggle4,Test setting input"
group.long 0xE0++0x03
line.long 0x00 "RTTSET24_20,"
hexmask.long.word 0x00 16.--31. 1. "toggle6,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "toggle5,Test setting input"
group.long 0xE4++0x03
line.long 0x00 "RTTSET25_20,"
hexmask.long.byte 0x00 24.--31. 1. "toggle7,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "toggle6,Test setting input"
group.long 0xE8++0x03
line.long 0x00 "RTTSET26_20,"
hexmask.long 0x00 0.--31. 1. "toggle7,Test setting input"
group.long 0xEC++0x03
line.long 0x00 "RTTSET27_20,"
hexmask.long 0x00 0.--31. 1. "switching4,Test setting input"
group.long 0xF0++0x03
line.long 0x00 "RTTSET28_20,"
hexmask.long.tbyte 0x00 8.--31. 1. "switching5,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "switching4,Test setting input"
group.long 0xF4++0x03
line.long 0x00 "RTTSET29_20,"
hexmask.long.word 0x00 16.--31. 1. "switching6,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "switching5,Test setting input"
group.long 0xF8++0x03
line.long 0x00 "RTTSET30_20,"
hexmask.long.byte 0x00 24.--31. 1. "switching7,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "switching6,Test setting input"
group.long 0xFC++0x03
line.long 0x00 "RTTSET31_20,"
hexmask.long 0x00 0.--31. 1. "switching7,Test setting input"
group.long 0x100++0x03
line.long 0x00 "RTTSET32_20,"
hexmask.long 0x00 0.--31. 1. "clknum_31_0,Test setting input"
group.long 0x104++0x03
line.long 0x00 "RTTSET33_20,"
hexmask.long 0x00 0.--31. 1. "Testmat_31_0,Test setting input"
group.long 0x108++0x03
line.long 0x00 "RTTSET34_20,"
hexmask.long 0x00 0.--31. 1. "Testmat_63_32,Test setting input"
group.long 0x10C++0x03
line.long 0x00 "RTTSET35_20,"
hexmask.long 0x00 0.--31. 1. "Testmat_95_64,Test setting input"
group.long 0x110++0x03
line.long 0x00 "RTTSET36_20,"
hexmask.long 0x00 0.--31. 1. "Testmat_127_96,Test setting input"
group.long 0x114++0x03
line.long 0x00 "RTTSET37_20,"
hexmask.long 0x00 0.--31. 1. "Testmat_159_128,Test setting input"
group.long 0x118++0x03
line.long 0x00 "RTTSET38_20,"
hexmask.long 0x00 0.--31. 1. "Testmat_191_160,Test setting input"
group.long 0x11C++0x03
line.long 0x00 "RTTSET39_20,"
hexmask.long 0x00 0.--31. 1. "Testmat_223_192,Test setting input"
group.long 0x120++0x03
line.long 0x00 "RTTSET40_20,"
hexmask.long 0x00 0.--31. 1. "Testmat_255_224,Test setting input"
group.long 0x124++0x03
line.long 0x00 "RTTSET41_20,"
hexmask.long.word 0x00 18.--31. 1. "Reserved_18,Reserved The bit or field is readable only"
hexmask.long.byte 0x00 10.--17. 1. "apbsel,Test setting input"
newline
bitfld.long 0x00 6.--9. "mbsel,Test setting input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--5. "coreselect,Test setting input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x128++0x03
line.long 0x00 "RTTSET42_20,"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved The bit or field is readable only" "0,1,2,3"
hexmask.long.word 0x00 16.--29. 1. "Y_address,Test setting input"
newline
rbitfld.long 0x00 14.--15. "Reserved_14,Reserved The bit or field is readable only" "0,1,2,3"
hexmask.long.word 0x00 0.--13. 1. "X_address,Test setting input"
group.long 0x12C++0x03
line.long 0x00 "RTTSET43_20,"
rbitfld.long 0x00 31. "Reserved_31,Reserved The bit or field is readable only" "0,1"
hexmask.long.tbyte 0x00 14.--30. 1. "XY,Test setting input"
newline
hexmask.long.word 0x00 0.--13. 1. "Z_address,Test setting input"
group.long 0x130++0x03
line.long 0x00 "RTTSET44_20,"
rbitfld.long 0x00 26.--31. "Reserved_26,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x00 16.--25. 1. "scanchain,Test setting input for hardware-SCAN"
newline
hexmask.long.word 0x00 0.--15. 1. "scanpat,Test setting input for hardware-SCAN"
group.long 0x400++0x03
line.long 0x00 "PSTRSTT20,"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved"
rbitfld.long 0x00 12. "R_rst_T,BIST Redundant result" "0: pass,1: fail"
newline
rbitfld.long 0x00 11. "Reserved_11,Reserved" "0,1"
rbitfld.long 0x00 8.--10. "error_T,BIST error" "0: Pass,1: Fail,2: TimeOut,?,4: BUS error,?..."
newline
rbitfld.long 0x00 4.--7. "testnum_T,Number of tests" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 2.--3. "status_R,BIST Redundant status (Safety function)" "0: unexec,1: wait,2: exec,3: finish"
newline
rbitfld.long 0x00 0.--1. "status_T,BIST status" "0: unexec,1: wait,2: exec,3: finish"
group.long 0x440++0x03
line.long 0x00 "PSTCNT20,"
hexmask.long 0x00 0.--31. 1. "Stop,FieldBIST internal WDT (high counter) stop value"
group.long 0x444++0x03
line.long 0x00 "RTTRSTT20,When status_T in the RTTRSTT register is"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved" "0,1,2,3"
rbitfld.long 0x00 29. "IL_flag2,Runtime Test Illegal suspension flag-2" "0,1"
newline
rbitfld.long 0x00 28. "IL_flag1,Runtime Test Illegal suspension flag-1" "0,1"
rbitfld.long 0x00 27. "CONDF,Debug monitor of FieldBIST condition" "0: not response,1: responded"
newline
rbitfld.long 0x00 24.--26. "BUS_cond,Debug code of BUS condition" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 13.--23. 1. "Reserved_13,Reserved"
newline
rbitfld.long 0x00 12. "R_rst_T,BIST Redundant result (Safety function)" "0: Pass,1: Fail"
rbitfld.long 0x00 11. "Achk,Debug code of address check" "0: normal,1: warning"
newline
rbitfld.long 0x00 8.--10. "error_T,BIST error" "0: Pass,1: Fail,2: TimeOut,?,4: BUS error,?..."
rbitfld.long 0x00 4.--7. "testnum_T,Number of tests" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 2.--3. "R_status_T,BIST redundant status" "0: unexec,1: wait,2: exec,3: finish"
rbitfld.long 0x00 0.--1. "status_T,BIST status" "0: unexec,1: wait,2: exec,3: finish"
group.long 0x458++0x03
line.long 0x00 "RTTCNT20,"
hexmask.long 0x00 0.--31. 1. "Stop,WDT (high counter) stop value"
group.long 0x4A0++0x03
line.long 0x00 "SLFRVS20,"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved"
hexmask.long.tbyte 0x00 0.--19. 1. "REVERS,Expected value reverse for Self-Check SISR"
group.long 0x4A4++0x03
line.long 0x00 "SLFRST20,In case of the SLFR bits of the RTTRSTT register is 1B'1 SCNT bit returns to 1"
rbitfld.long 0x00 26.--31. "SCNT,Self-Check counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 24.--25. "STS,Self-Check status" "0: unexec,1: exec,?,3: finish"
newline
hexmask.long.tbyte 0x00 1.--23. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "STR,Self -Check Result" "0: Pass,1: Fail"
group.long 0x4C0++0x03
line.long 0x00 "ERRSET20,"
hexmask.long 0x00 3.--31. 1. "Reserved_3,Reserved"
bitfld.long 0x00 2. "DSB,Dummy set BUS-Error (set of fbc_rt_safetyerr)" "0,1"
newline
bitfld.long 0x00 1. "DST,Dummy set Time out (set of fbc_rt_overerr)" "0,1"
bitfld.long 0x00 0. "DSF,Dummy set Fail (set of fbc_rt_fail)" "0,1"
tree.end
tree "FUNCTIONAL_SAFETY_INST_20"
base ad:0xFF851000
group.long 0x00++0x03
line.long 0x00 "RTTEX21,SLFR and SLFE bit of the RTTEX are effective only when KCD bit is H'F1"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved" "0,1,2,3"
bitfld.long 0x00 29. "SLFR,Self-Check Counter Reset for field BIST activator" "0: Counter Reset,1: Counter not Reset"
newline
bitfld.long 0x00 28. "SLFE,Execution of Self-Check for Field BIST activator" "0: Not Execution of Self-Check for Field BIST,1: Execution of Self-Check for Field BIST.."
rbitfld.long 0x00 24.--27. "Reserved_24,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.byte 0x00 16.--23. 1. "KCD,Key Code H'5A: Effective execution of Run Time Test H'F1: Effective execution of Self-Check for field BIST activator"
rbitfld.long 0x00 11.--15. "Reserved_11,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "STM,Single Step Test Mode" "?,1: LBIST,2: MBIST,3: SCAN,?..."
bitfld.long 0x00 6.--7. "INTM,Interrupt mask" "0: non mask *1,?,2: Only at the time of the fail(fba_rt_finish are,?..."
newline
bitfld.long 0x00 5. "SSZ,SCAN Pattern size Valid only when STM=011" "0: 32bit mode,1: 16bit mode"
bitfld.long 0x00 4. "TR,Select the value of the timer" "0: ROM,1: register"
newline
bitfld.long 0x00 3. "WM,Wfi mask" "0: not mask,1: mask"
bitfld.long 0x00 2. "TM,Mask the judgment of timer" "0: not mask,1: mask"
newline
bitfld.long 0x00 1. "STP,Single Step Mode" "0: ROM batch mode,1: Single Step Mode"
bitfld.long 0x00 0. "EX,Execution of Runtime Test" "0: Not Execution of Runtime Test,1: Execution of Runtime Test"
group.long 0x04++0x03
line.long 0x00 "RTTMI121,"
rbitfld.long 0x00 27.--31. "Reserved_27,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 24.--26. "RPROT,Protection type of MEMORY" "0: Unprivileged access,1: Privileged access,?..."
newline
hexmask.long.byte 0x00 16.--23. 1. "MADDR_upper,Memory upper address[39:32] that stores the SCAN pattern"
hexmask.long.word 0x00 0.--15. 1. "MUNIT,Number of units (1 unit = 128 Byte)"
group.long 0x08++0x03
line.long 0x00 "RTTMI221,"
hexmask.long 0x00 0.--31. 1. "MADDR,Memory address that stores the SCAN pattern"
group.long 0x0C++0x03
line.long 0x00 "RTTSISR121,"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved"
hexmask.long.tbyte 0x00 0.--19. 1. "SISR1,SISR-TEST#1 Expected value"
group.long 0x14++0x03
line.long 0x00 "RTTUC21,"
hexmask.long 0x00 0.--31. 1. "U_WDT,Upper counter of Watchdog Timer"
group.long 0x18++0x03
line.long 0x00 "RTTDC21,"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved"
hexmask.long.word 0x00 0.--15. 1. "L_WDT,Lower counter of Watchdog Timer"
group.long 0x80++0x03
line.long 0x00 "RTTSET0_21,"
hexmask.long 0x00 0.--31. 1. "test_clock,Test setting input"
group.long 0x84++0x03
line.long 0x00 "RTTSET1_21,"
hexmask.long 0x00 2.--31. 1. "Reserved_2,Reserved"
bitfld.long 0x00 1. "reset,Test setting input" "0: Reset test disabled,1: Reset test enabled"
newline
bitfld.long 0x00 0. "tt,Test setting input" "0: Selected other clock,1: Selected test clock for test Domain"
group.long 0x88++0x03
line.long 0x00 "RTTSET2_21,"
hexmask.long 0x00 0.--31. 1. "hold0,Test setting input"
group.long 0x8C++0x03
line.long 0x00 "RTTSET3_21,"
hexmask.long.tbyte 0x00 8.--31. 1. "hold1,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "hold0,Test setting input"
group.long 0x90++0x03
line.long 0x00 "RTTSET4_21,"
hexmask.long.word 0x00 16.--31. 1. "hold2,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "hold1,Test setting input"
group.long 0x94++0x03
line.long 0x00 "RTTSET5_21,"
hexmask.long.byte 0x00 24.--31. 1. "hold3,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "hold2,Test setting input"
group.long 0x98++0x03
line.long 0x00 "RTTSET6_21,"
hexmask.long 0x00 0.--31. 1. "hold3,Test setting input"
group.long 0x9C++0x03
line.long 0x00 "RTTSET7_21,"
hexmask.long 0x00 0.--31. 1. "toggle0,Test setting input"
group.long 0xA0++0x03
line.long 0x00 "RTTSET8_21,"
hexmask.long.tbyte 0x00 8.--31. 1. "toggle1,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "toggle0,Test setting input"
group.long 0xA4++0x03
line.long 0x00 "RTTSET9_21,"
hexmask.long.word 0x00 16.--31. 1. "toggle2,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "toggle1,Test setting input"
group.long 0xA8++0x03
line.long 0x00 "RTTSET10_21,"
hexmask.long.byte 0x00 24.--31. 1. "toggle3,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "toggle2,Test setting input"
group.long 0xAC++0x03
line.long 0x00 "RTTSET11_21,"
hexmask.long 0x00 0.--31. 1. "toggle3,Test setting input"
group.long 0xB0++0x03
line.long 0x00 "RTTSET12_21,"
hexmask.long 0x00 0.--31. 1. "switching0,Test setting input"
group.long 0xB4++0x03
line.long 0x00 "RTTSET13_21,"
hexmask.long.tbyte 0x00 8.--31. 1. "switching1,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "switching0,Test setting input"
group.long 0xB8++0x03
line.long 0x00 "RTTSET14_21,"
hexmask.long.word 0x00 16.--31. 1. "switching2,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "switching1,Test setting input"
group.long 0xBC++0x03
line.long 0x00 "RTTSET15_21,"
hexmask.long.byte 0x00 24.--31. 1. "switching3,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "switching2,Test setting input"
group.long 0xC0++0x03
line.long 0x00 "RTTSET16_21,"
hexmask.long 0x00 0.--31. 1. "switching3,Test setting input"
group.long 0xC4++0x03
line.long 0x00 "RTTSET17_21,"
hexmask.long 0x00 0.--31. 1. "hold4,Test setting input"
group.long 0xC8++0x03
line.long 0x00 "RTTSET18_21,"
hexmask.long.tbyte 0x00 8.--31. 1. "hold5,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "hold4,Test setting input"
group.long 0xCC++0x03
line.long 0x00 "RTTSET19_21,"
hexmask.long.word 0x00 16.--31. 1. "hold6,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "hold5,Test setting input"
group.long 0xD0++0x03
line.long 0x00 "RTTSET20_21,"
hexmask.long.byte 0x00 24.--31. 1. "hold7,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "hold6,Test setting input"
group.long 0xD4++0x03
line.long 0x00 "RTTSET21_21,"
hexmask.long 0x00 0.--31. 1. "hold7,Test setting input"
group.long 0xD8++0x03
line.long 0x00 "RTTSET22_21,"
hexmask.long 0x00 0.--31. 1. "toggle4,Test setting input"
group.long 0xDC++0x03
line.long 0x00 "RTTSET23_21,"
hexmask.long.tbyte 0x00 8.--31. 1. "toggle5,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "toggle4,Test setting input"
group.long 0xE0++0x03
line.long 0x00 "RTTSET24_21,"
hexmask.long.word 0x00 16.--31. 1. "toggle6,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "toggle5,Test setting input"
group.long 0xE4++0x03
line.long 0x00 "RTTSET25_21,"
hexmask.long.byte 0x00 24.--31. 1. "toggle7,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "toggle6,Test setting input"
group.long 0xE8++0x03
line.long 0x00 "RTTSET26_21,"
hexmask.long 0x00 0.--31. 1. "toggle7,Test setting input"
group.long 0xEC++0x03
line.long 0x00 "RTTSET27_21,"
hexmask.long 0x00 0.--31. 1. "switching4,Test setting input"
group.long 0xF0++0x03
line.long 0x00 "RTTSET28_21,"
hexmask.long.tbyte 0x00 8.--31. 1. "switching5,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "switching4,Test setting input"
group.long 0xF4++0x03
line.long 0x00 "RTTSET29_21,"
hexmask.long.word 0x00 16.--31. 1. "switching6,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "switching5,Test setting input"
group.long 0xF8++0x03
line.long 0x00 "RTTSET30_21,"
hexmask.long.byte 0x00 24.--31. 1. "switching7,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "switching6,Test setting input"
group.long 0xFC++0x03
line.long 0x00 "RTTSET31_21,"
hexmask.long 0x00 0.--31. 1. "switching7,Test setting input"
group.long 0x100++0x03
line.long 0x00 "RTTSET32_21,"
hexmask.long 0x00 0.--31. 1. "clknum_31_0,Test setting input"
group.long 0x104++0x03
line.long 0x00 "RTTSET33_21,"
hexmask.long 0x00 0.--31. 1. "Testmat_31_0,Test setting input"
group.long 0x108++0x03
line.long 0x00 "RTTSET34_21,"
hexmask.long 0x00 0.--31. 1. "Testmat_63_32,Test setting input"
group.long 0x10C++0x03
line.long 0x00 "RTTSET35_21,"
hexmask.long 0x00 0.--31. 1. "Testmat_95_64,Test setting input"
group.long 0x110++0x03
line.long 0x00 "RTTSET36_21,"
hexmask.long 0x00 0.--31. 1. "Testmat_127_96,Test setting input"
group.long 0x114++0x03
line.long 0x00 "RTTSET37_21,"
hexmask.long 0x00 0.--31. 1. "Testmat_159_128,Test setting input"
group.long 0x118++0x03
line.long 0x00 "RTTSET38_21,"
hexmask.long 0x00 0.--31. 1. "Testmat_191_160,Test setting input"
group.long 0x11C++0x03
line.long 0x00 "RTTSET39_21,"
hexmask.long 0x00 0.--31. 1. "Testmat_223_192,Test setting input"
group.long 0x120++0x03
line.long 0x00 "RTTSET40_21,"
hexmask.long 0x00 0.--31. 1. "Testmat_255_224,Test setting input"
group.long 0x124++0x03
line.long 0x00 "RTTSET41_21,"
hexmask.long.word 0x00 18.--31. 1. "Reserved_18,Reserved The bit or field is readable only"
hexmask.long.byte 0x00 10.--17. 1. "apbsel,Test setting input"
newline
bitfld.long 0x00 6.--9. "mbsel,Test setting input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--5. "coreselect,Test setting input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x128++0x03
line.long 0x00 "RTTSET42_21,"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved The bit or field is readable only" "0,1,2,3"
hexmask.long.word 0x00 16.--29. 1. "Y_address,Test setting input"
newline
rbitfld.long 0x00 14.--15. "Reserved_14,Reserved The bit or field is readable only" "0,1,2,3"
hexmask.long.word 0x00 0.--13. 1. "X_address,Test setting input"
group.long 0x12C++0x03
line.long 0x00 "RTTSET43_21,"
rbitfld.long 0x00 31. "Reserved_31,Reserved The bit or field is readable only" "0,1"
hexmask.long.tbyte 0x00 14.--30. 1. "XY,Test setting input"
newline
hexmask.long.word 0x00 0.--13. 1. "Z_address,Test setting input"
group.long 0x130++0x03
line.long 0x00 "RTTSET44_21,"
rbitfld.long 0x00 26.--31. "Reserved_26,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x00 16.--25. 1. "scanchain,Test setting input for hardware-SCAN"
newline
hexmask.long.word 0x00 0.--15. 1. "scanpat,Test setting input for hardware-SCAN"
group.long 0x400++0x03
line.long 0x00 "PSTRSTT21,"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved"
rbitfld.long 0x00 12. "R_rst_T,BIST Redundant result" "0: pass,1: fail"
newline
rbitfld.long 0x00 11. "Reserved_11,Reserved" "0,1"
rbitfld.long 0x00 8.--10. "error_T,BIST error" "0: Pass,1: Fail,2: TimeOut,?,4: BUS error,?..."
newline
rbitfld.long 0x00 4.--7. "testnum_T,Number of tests" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 2.--3. "status_R,BIST Redundant status (Safety function)" "0: unexec,1: wait,2: exec,3: finish"
newline
rbitfld.long 0x00 0.--1. "status_T,BIST status" "0: unexec,1: wait,2: exec,3: finish"
group.long 0x440++0x03
line.long 0x00 "PSTCNT21,"
hexmask.long 0x00 0.--31. 1. "Stop,FieldBIST internal WDT (high counter) stop value"
group.long 0x444++0x03
line.long 0x00 "RTTRSTT21,When status_T in the RTTRSTT register is"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved" "0,1,2,3"
rbitfld.long 0x00 29. "IL_flag2,Runtime Test Illegal suspension flag-2" "0,1"
newline
rbitfld.long 0x00 28. "IL_flag1,Runtime Test Illegal suspension flag-1" "0,1"
rbitfld.long 0x00 27. "CONDF,Debug monitor of FieldBIST condition" "0: not response,1: responded"
newline
rbitfld.long 0x00 24.--26. "BUS_cond,Debug code of BUS condition" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 13.--23. 1. "Reserved_13,Reserved"
newline
rbitfld.long 0x00 12. "R_rst_T,BIST Redundant result (Safety function)" "0: Pass,1: Fail"
rbitfld.long 0x00 11. "Achk,Debug code of address check" "0: normal,1: warning"
newline
rbitfld.long 0x00 8.--10. "error_T,BIST error" "0: Pass,1: Fail,2: TimeOut,?,4: BUS error,?..."
rbitfld.long 0x00 4.--7. "testnum_T,Number of tests" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 2.--3. "R_status_T,BIST redundant status" "0: unexec,1: wait,2: exec,3: finish"
rbitfld.long 0x00 0.--1. "status_T,BIST status" "0: unexec,1: wait,2: exec,3: finish"
group.long 0x458++0x03
line.long 0x00 "RTTCNT21,"
hexmask.long 0x00 0.--31. 1. "Stop,WDT (high counter) stop value"
group.long 0x4A0++0x03
line.long 0x00 "SLFRVS21,"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved"
hexmask.long.tbyte 0x00 0.--19. 1. "REVERS,Expected value reverse for Self-Check SISR"
group.long 0x4A4++0x03
line.long 0x00 "SLFRST21,In case of the SLFR bits of the RTTRSTT register is 1B'1 SCNT bit returns to 1"
rbitfld.long 0x00 26.--31. "SCNT,Self-Check counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 24.--25. "STS,Self-Check status" "0: unexec,1: exec,?,3: finish"
newline
hexmask.long.tbyte 0x00 1.--23. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "STR,Self -Check Result" "0: Pass,1: Fail"
group.long 0x4C0++0x03
line.long 0x00 "ERRSET21,"
hexmask.long 0x00 3.--31. 1. "Reserved_3,Reserved"
bitfld.long 0x00 2. "DSB,Dummy set BUS-Error (set of fbc_rt_safetyerr)" "0,1"
newline
bitfld.long 0x00 1. "DST,Dummy set Time out (set of fbc_rt_overerr)" "0,1"
bitfld.long 0x00 0. "DSF,Dummy set Fail (set of fbc_rt_fail)" "0,1"
tree.end
tree "FUNCTIONAL_SAFETY_INST_21"
base ad:0xFF854000
group.long 0x00++0x03
line.long 0x00 "RTTEX22,SLFR and SLFE bit of the RTTEX are effective only when KCD bit is H'F1"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved" "0,1,2,3"
bitfld.long 0x00 29. "SLFR,Self-Check Counter Reset for field BIST activator" "0: Counter Reset,1: Counter not Reset"
newline
bitfld.long 0x00 28. "SLFE,Execution of Self-Check for Field BIST activator" "0: Not Execution of Self-Check for Field BIST,1: Execution of Self-Check for Field BIST.."
rbitfld.long 0x00 24.--27. "Reserved_24,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.byte 0x00 16.--23. 1. "KCD,Key Code H'5A: Effective execution of Run Time Test H'F1: Effective execution of Self-Check for field BIST activator"
rbitfld.long 0x00 11.--15. "Reserved_11,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "STM,Single Step Test Mode" "?,1: LBIST,2: MBIST,3: SCAN,?..."
bitfld.long 0x00 6.--7. "INTM,Interrupt mask" "0: non mask *1,?,2: Only at the time of the fail(fba_rt_finish are,?..."
newline
bitfld.long 0x00 5. "SSZ,SCAN Pattern size Valid only when STM=011" "0: 32bit mode,1: 16bit mode"
bitfld.long 0x00 4. "TR,Select the value of the timer" "0: ROM,1: register"
newline
bitfld.long 0x00 3. "WM,Wfi mask" "0: not mask,1: mask"
bitfld.long 0x00 2. "TM,Mask the judgment of timer" "0: not mask,1: mask"
newline
bitfld.long 0x00 1. "STP,Single Step Mode" "0: ROM batch mode,1: Single Step Mode"
bitfld.long 0x00 0. "EX,Execution of Runtime Test" "0: Not Execution of Runtime Test,1: Execution of Runtime Test"
group.long 0x04++0x03
line.long 0x00 "RTTMI122,"
rbitfld.long 0x00 27.--31. "Reserved_27,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 24.--26. "RPROT,Protection type of MEMORY" "0: Unprivileged access,1: Privileged access,?..."
newline
hexmask.long.byte 0x00 16.--23. 1. "MADDR_upper,Memory upper address[39:32] that stores the SCAN pattern"
hexmask.long.word 0x00 0.--15. 1. "MUNIT,Number of units (1 unit = 128 Byte)"
group.long 0x08++0x03
line.long 0x00 "RTTMI222,"
hexmask.long 0x00 0.--31. 1. "MADDR,Memory address that stores the SCAN pattern"
group.long 0x0C++0x03
line.long 0x00 "RTTSISR122,"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved"
hexmask.long.tbyte 0x00 0.--19. 1. "SISR1,SISR-TEST#1 Expected value"
group.long 0x14++0x03
line.long 0x00 "RTTUC22,"
hexmask.long 0x00 0.--31. 1. "U_WDT,Upper counter of Watchdog Timer"
group.long 0x18++0x03
line.long 0x00 "RTTDC22,"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved"
hexmask.long.word 0x00 0.--15. 1. "L_WDT,Lower counter of Watchdog Timer"
group.long 0x80++0x03
line.long 0x00 "RTTSET0_22,"
hexmask.long 0x00 0.--31. 1. "test_clock,Test setting input"
group.long 0x84++0x03
line.long 0x00 "RTTSET1_22,"
hexmask.long 0x00 2.--31. 1. "Reserved_2,Reserved"
bitfld.long 0x00 1. "reset,Test setting input" "0: Reset test disabled,1: Reset test enabled"
newline
bitfld.long 0x00 0. "tt,Test setting input" "0: Selected other clock,1: Selected test clock for test Domain"
group.long 0x88++0x03
line.long 0x00 "RTTSET2_22,"
hexmask.long 0x00 0.--31. 1. "hold0,Test setting input"
group.long 0x8C++0x03
line.long 0x00 "RTTSET3_22,"
hexmask.long.tbyte 0x00 8.--31. 1. "hold1,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "hold0,Test setting input"
group.long 0x90++0x03
line.long 0x00 "RTTSET4_22,"
hexmask.long.word 0x00 16.--31. 1. "hold2,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "hold1,Test setting input"
group.long 0x94++0x03
line.long 0x00 "RTTSET5_22,"
hexmask.long.byte 0x00 24.--31. 1. "hold3,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "hold2,Test setting input"
group.long 0x98++0x03
line.long 0x00 "RTTSET6_22,"
hexmask.long 0x00 0.--31. 1. "hold3,Test setting input"
group.long 0x9C++0x03
line.long 0x00 "RTTSET7_22,"
hexmask.long 0x00 0.--31. 1. "toggle0,Test setting input"
group.long 0xA0++0x03
line.long 0x00 "RTTSET8_22,"
hexmask.long.tbyte 0x00 8.--31. 1. "toggle1,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "toggle0,Test setting input"
group.long 0xA4++0x03
line.long 0x00 "RTTSET9_22,"
hexmask.long.word 0x00 16.--31. 1. "toggle2,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "toggle1,Test setting input"
group.long 0xA8++0x03
line.long 0x00 "RTTSET10_22,"
hexmask.long.byte 0x00 24.--31. 1. "toggle3,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "toggle2,Test setting input"
group.long 0xAC++0x03
line.long 0x00 "RTTSET11_22,"
hexmask.long 0x00 0.--31. 1. "toggle3,Test setting input"
group.long 0xB0++0x03
line.long 0x00 "RTTSET12_22,"
hexmask.long 0x00 0.--31. 1. "switching0,Test setting input"
group.long 0xB4++0x03
line.long 0x00 "RTTSET13_22,"
hexmask.long.tbyte 0x00 8.--31. 1. "switching1,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "switching0,Test setting input"
group.long 0xB8++0x03
line.long 0x00 "RTTSET14_22,"
hexmask.long.word 0x00 16.--31. 1. "switching2,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "switching1,Test setting input"
group.long 0xBC++0x03
line.long 0x00 "RTTSET15_22,"
hexmask.long.byte 0x00 24.--31. 1. "switching3,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "switching2,Test setting input"
group.long 0xC0++0x03
line.long 0x00 "RTTSET16_22,"
hexmask.long 0x00 0.--31. 1. "switching3,Test setting input"
group.long 0xC4++0x03
line.long 0x00 "RTTSET17_22,"
hexmask.long 0x00 0.--31. 1. "hold4,Test setting input"
group.long 0xC8++0x03
line.long 0x00 "RTTSET18_22,"
hexmask.long.tbyte 0x00 8.--31. 1. "hold5,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "hold4,Test setting input"
group.long 0xCC++0x03
line.long 0x00 "RTTSET19_22,"
hexmask.long.word 0x00 16.--31. 1. "hold6,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "hold5,Test setting input"
group.long 0xD0++0x03
line.long 0x00 "RTTSET20_22,"
hexmask.long.byte 0x00 24.--31. 1. "hold7,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "hold6,Test setting input"
group.long 0xD4++0x03
line.long 0x00 "RTTSET21_22,"
hexmask.long 0x00 0.--31. 1. "hold7,Test setting input"
group.long 0xD8++0x03
line.long 0x00 "RTTSET22_22,"
hexmask.long 0x00 0.--31. 1. "toggle4,Test setting input"
group.long 0xDC++0x03
line.long 0x00 "RTTSET23_22,"
hexmask.long.tbyte 0x00 8.--31. 1. "toggle5,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "toggle4,Test setting input"
group.long 0xE0++0x03
line.long 0x00 "RTTSET24_22,"
hexmask.long.word 0x00 16.--31. 1. "toggle6,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "toggle5,Test setting input"
group.long 0xE4++0x03
line.long 0x00 "RTTSET25_22,"
hexmask.long.byte 0x00 24.--31. 1. "toggle7,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "toggle6,Test setting input"
group.long 0xE8++0x03
line.long 0x00 "RTTSET26_22,"
hexmask.long 0x00 0.--31. 1. "toggle7,Test setting input"
group.long 0xEC++0x03
line.long 0x00 "RTTSET27_22,"
hexmask.long 0x00 0.--31. 1. "switching4,Test setting input"
group.long 0xF0++0x03
line.long 0x00 "RTTSET28_22,"
hexmask.long.tbyte 0x00 8.--31. 1. "switching5,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "switching4,Test setting input"
group.long 0xF4++0x03
line.long 0x00 "RTTSET29_22,"
hexmask.long.word 0x00 16.--31. 1. "switching6,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "switching5,Test setting input"
group.long 0xF8++0x03
line.long 0x00 "RTTSET30_22,"
hexmask.long.byte 0x00 24.--31. 1. "switching7,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "switching6,Test setting input"
group.long 0xFC++0x03
line.long 0x00 "RTTSET31_22,"
hexmask.long 0x00 0.--31. 1. "switching7,Test setting input"
group.long 0x100++0x03
line.long 0x00 "RTTSET32_22,"
hexmask.long 0x00 0.--31. 1. "clknum_31_0,Test setting input"
group.long 0x104++0x03
line.long 0x00 "RTTSET33_22,"
hexmask.long 0x00 0.--31. 1. "Testmat_31_0,Test setting input"
group.long 0x108++0x03
line.long 0x00 "RTTSET34_22,"
hexmask.long 0x00 0.--31. 1. "Testmat_63_32,Test setting input"
group.long 0x10C++0x03
line.long 0x00 "RTTSET35_22,"
hexmask.long 0x00 0.--31. 1. "Testmat_95_64,Test setting input"
group.long 0x110++0x03
line.long 0x00 "RTTSET36_22,"
hexmask.long 0x00 0.--31. 1. "Testmat_127_96,Test setting input"
group.long 0x114++0x03
line.long 0x00 "RTTSET37_22,"
hexmask.long 0x00 0.--31. 1. "Testmat_159_128,Test setting input"
group.long 0x118++0x03
line.long 0x00 "RTTSET38_22,"
hexmask.long 0x00 0.--31. 1. "Testmat_191_160,Test setting input"
group.long 0x11C++0x03
line.long 0x00 "RTTSET39_22,"
hexmask.long 0x00 0.--31. 1. "Testmat_223_192,Test setting input"
group.long 0x120++0x03
line.long 0x00 "RTTSET40_22,"
hexmask.long 0x00 0.--31. 1. "Testmat_255_224,Test setting input"
group.long 0x124++0x03
line.long 0x00 "RTTSET41_22,"
hexmask.long.word 0x00 18.--31. 1. "Reserved_18,Reserved The bit or field is readable only"
hexmask.long.byte 0x00 10.--17. 1. "apbsel,Test setting input"
newline
bitfld.long 0x00 6.--9. "mbsel,Test setting input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--5. "coreselect,Test setting input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x128++0x03
line.long 0x00 "RTTSET42_22,"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved The bit or field is readable only" "0,1,2,3"
hexmask.long.word 0x00 16.--29. 1. "Y_address,Test setting input"
newline
rbitfld.long 0x00 14.--15. "Reserved_14,Reserved The bit or field is readable only" "0,1,2,3"
hexmask.long.word 0x00 0.--13. 1. "X_address,Test setting input"
group.long 0x12C++0x03
line.long 0x00 "RTTSET43_22,"
rbitfld.long 0x00 31. "Reserved_31,Reserved The bit or field is readable only" "0,1"
hexmask.long.tbyte 0x00 14.--30. 1. "XY,Test setting input"
newline
hexmask.long.word 0x00 0.--13. 1. "Z_address,Test setting input"
group.long 0x130++0x03
line.long 0x00 "RTTSET44_22,"
rbitfld.long 0x00 26.--31. "Reserved_26,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x00 16.--25. 1. "scanchain,Test setting input for hardware-SCAN"
newline
hexmask.long.word 0x00 0.--15. 1. "scanpat,Test setting input for hardware-SCAN"
group.long 0x400++0x03
line.long 0x00 "PSTRSTT22,"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved"
rbitfld.long 0x00 12. "R_rst_T,BIST Redundant result" "0: pass,1: fail"
newline
rbitfld.long 0x00 11. "Reserved_11,Reserved" "0,1"
rbitfld.long 0x00 8.--10. "error_T,BIST error" "0: Pass,1: Fail,2: TimeOut,?,4: BUS error,?..."
newline
rbitfld.long 0x00 4.--7. "testnum_T,Number of tests" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 2.--3. "status_R,BIST Redundant status (Safety function)" "0: unexec,1: wait,2: exec,3: finish"
newline
rbitfld.long 0x00 0.--1. "status_T,BIST status" "0: unexec,1: wait,2: exec,3: finish"
group.long 0x440++0x03
line.long 0x00 "PSTCNT22,"
hexmask.long 0x00 0.--31. 1. "Stop,FieldBIST internal WDT (high counter) stop value"
group.long 0x444++0x03
line.long 0x00 "RTTRSTT22,When status_T in the RTTRSTT register is"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved" "0,1,2,3"
rbitfld.long 0x00 29. "IL_flag2,Runtime Test Illegal suspension flag-2" "0,1"
newline
rbitfld.long 0x00 28. "IL_flag1,Runtime Test Illegal suspension flag-1" "0,1"
rbitfld.long 0x00 27. "CONDF,Debug monitor of FieldBIST condition" "0: not response,1: responded"
newline
rbitfld.long 0x00 24.--26. "BUS_cond,Debug code of BUS condition" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 13.--23. 1. "Reserved_13,Reserved"
newline
rbitfld.long 0x00 12. "R_rst_T,BIST Redundant result (Safety function)" "0: Pass,1: Fail"
rbitfld.long 0x00 11. "Achk,Debug code of address check" "0: normal,1: warning"
newline
rbitfld.long 0x00 8.--10. "error_T,BIST error" "0: Pass,1: Fail,2: TimeOut,?,4: BUS error,?..."
rbitfld.long 0x00 4.--7. "testnum_T,Number of tests" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 2.--3. "R_status_T,BIST redundant status" "0: unexec,1: wait,2: exec,3: finish"
rbitfld.long 0x00 0.--1. "status_T,BIST status" "0: unexec,1: wait,2: exec,3: finish"
group.long 0x458++0x03
line.long 0x00 "RTTCNT22,"
hexmask.long 0x00 0.--31. 1. "Stop,WDT (high counter) stop value"
group.long 0x4A0++0x03
line.long 0x00 "SLFRVS22,"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved"
hexmask.long.tbyte 0x00 0.--19. 1. "REVERS,Expected value reverse for Self-Check SISR"
group.long 0x4A4++0x03
line.long 0x00 "SLFRST22,In case of the SLFR bits of the RTTRSTT register is 1B'1 SCNT bit returns to 1"
rbitfld.long 0x00 26.--31. "SCNT,Self-Check counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 24.--25. "STS,Self-Check status" "0: unexec,1: exec,?,3: finish"
newline
hexmask.long.tbyte 0x00 1.--23. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "STR,Self -Check Result" "0: Pass,1: Fail"
group.long 0x4C0++0x03
line.long 0x00 "ERRSET22,"
hexmask.long 0x00 3.--31. 1. "Reserved_3,Reserved"
bitfld.long 0x00 2. "DSB,Dummy set BUS-Error (set of fbc_rt_safetyerr)" "0,1"
newline
bitfld.long 0x00 1. "DST,Dummy set Time out (set of fbc_rt_overerr)" "0,1"
bitfld.long 0x00 0. "DSF,Dummy set Fail (set of fbc_rt_fail)" "0,1"
tree.end
tree "FUNCTIONAL_SAFETY_INST_22"
base ad:0xFF855000
group.long 0x00++0x03
line.long 0x00 "RTTEX23,SLFR and SLFE bit of the RTTEX are effective only when KCD bit is H'F1"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved" "0,1,2,3"
bitfld.long 0x00 29. "SLFR,Self-Check Counter Reset for field BIST activator" "0: Counter Reset,1: Counter not Reset"
newline
bitfld.long 0x00 28. "SLFE,Execution of Self-Check for Field BIST activator" "0: Not Execution of Self-Check for Field BIST,1: Execution of Self-Check for Field BIST.."
rbitfld.long 0x00 24.--27. "Reserved_24,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.byte 0x00 16.--23. 1. "KCD,Key Code H'5A: Effective execution of Run Time Test H'F1: Effective execution of Self-Check for field BIST activator"
rbitfld.long 0x00 11.--15. "Reserved_11,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "STM,Single Step Test Mode" "?,1: LBIST,2: MBIST,3: SCAN,?..."
bitfld.long 0x00 6.--7. "INTM,Interrupt mask" "0: non mask *1,?,2: Only at the time of the fail(fba_rt_finish are,?..."
newline
bitfld.long 0x00 5. "SSZ,SCAN Pattern size Valid only when STM=011" "0: 32bit mode,1: 16bit mode"
bitfld.long 0x00 4. "TR,Select the value of the timer" "0: ROM,1: register"
newline
bitfld.long 0x00 3. "WM,Wfi mask" "0: not mask,1: mask"
bitfld.long 0x00 2. "TM,Mask the judgment of timer" "0: not mask,1: mask"
newline
bitfld.long 0x00 1. "STP,Single Step Mode" "0: ROM batch mode,1: Single Step Mode"
bitfld.long 0x00 0. "EX,Execution of Runtime Test" "0: Not Execution of Runtime Test,1: Execution of Runtime Test"
group.long 0x04++0x03
line.long 0x00 "RTTMI123,"
rbitfld.long 0x00 27.--31. "Reserved_27,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 24.--26. "RPROT,Protection type of MEMORY" "0: Unprivileged access,1: Privileged access,?..."
newline
hexmask.long.byte 0x00 16.--23. 1. "MADDR_upper,Memory upper address[39:32] that stores the SCAN pattern"
hexmask.long.word 0x00 0.--15. 1. "MUNIT,Number of units (1 unit = 128 Byte)"
group.long 0x08++0x03
line.long 0x00 "RTTMI223,"
hexmask.long 0x00 0.--31. 1. "MADDR,Memory address that stores the SCAN pattern"
group.long 0x0C++0x03
line.long 0x00 "RTTSISR123,"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved"
hexmask.long.tbyte 0x00 0.--19. 1. "SISR1,SISR-TEST#1 Expected value"
group.long 0x14++0x03
line.long 0x00 "RTTUC23,"
hexmask.long 0x00 0.--31. 1. "U_WDT,Upper counter of Watchdog Timer"
group.long 0x18++0x03
line.long 0x00 "RTTDC23,"
hexmask.long.word 0x00 16.--31. 1. "Reserved_16,Reserved"
hexmask.long.word 0x00 0.--15. 1. "L_WDT,Lower counter of Watchdog Timer"
group.long 0x80++0x03
line.long 0x00 "RTTSET0_23,"
hexmask.long 0x00 0.--31. 1. "test_clock,Test setting input"
group.long 0x84++0x03
line.long 0x00 "RTTSET1_23,"
hexmask.long 0x00 2.--31. 1. "Reserved_2,Reserved"
bitfld.long 0x00 1. "reset,Test setting input" "0: Reset test disabled,1: Reset test enabled"
newline
bitfld.long 0x00 0. "tt,Test setting input" "0: Selected other clock,1: Selected test clock for test Domain"
group.long 0x88++0x03
line.long 0x00 "RTTSET2_23,"
hexmask.long 0x00 0.--31. 1. "hold0,Test setting input"
group.long 0x8C++0x03
line.long 0x00 "RTTSET3_23,"
hexmask.long.tbyte 0x00 8.--31. 1. "hold1,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "hold0,Test setting input"
group.long 0x90++0x03
line.long 0x00 "RTTSET4_23,"
hexmask.long.word 0x00 16.--31. 1. "hold2,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "hold1,Test setting input"
group.long 0x94++0x03
line.long 0x00 "RTTSET5_23,"
hexmask.long.byte 0x00 24.--31. 1. "hold3,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "hold2,Test setting input"
group.long 0x98++0x03
line.long 0x00 "RTTSET6_23,"
hexmask.long 0x00 0.--31. 1. "hold3,Test setting input"
group.long 0x9C++0x03
line.long 0x00 "RTTSET7_23,"
hexmask.long 0x00 0.--31. 1. "toggle0,Test setting input"
group.long 0xA0++0x03
line.long 0x00 "RTTSET8_23,"
hexmask.long.tbyte 0x00 8.--31. 1. "toggle1,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "toggle0,Test setting input"
group.long 0xA4++0x03
line.long 0x00 "RTTSET9_23,"
hexmask.long.word 0x00 16.--31. 1. "toggle2,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "toggle1,Test setting input"
group.long 0xA8++0x03
line.long 0x00 "RTTSET10_23,"
hexmask.long.byte 0x00 24.--31. 1. "toggle3,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "toggle2,Test setting input"
group.long 0xAC++0x03
line.long 0x00 "RTTSET11_23,"
hexmask.long 0x00 0.--31. 1. "toggle3,Test setting input"
group.long 0xB0++0x03
line.long 0x00 "RTTSET12_23,"
hexmask.long 0x00 0.--31. 1. "switching0,Test setting input"
group.long 0xB4++0x03
line.long 0x00 "RTTSET13_23,"
hexmask.long.tbyte 0x00 8.--31. 1. "switching1,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "switching0,Test setting input"
group.long 0xB8++0x03
line.long 0x00 "RTTSET14_23,"
hexmask.long.word 0x00 16.--31. 1. "switching2,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "switching1,Test setting input"
group.long 0xBC++0x03
line.long 0x00 "RTTSET15_23,"
hexmask.long.byte 0x00 24.--31. 1. "switching3,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "switching2,Test setting input"
group.long 0xC0++0x03
line.long 0x00 "RTTSET16_23,"
hexmask.long 0x00 0.--31. 1. "switching3,Test setting input"
group.long 0xC4++0x03
line.long 0x00 "RTTSET17_23,"
hexmask.long 0x00 0.--31. 1. "hold4,Test setting input"
group.long 0xC8++0x03
line.long 0x00 "RTTSET18_23,"
hexmask.long.tbyte 0x00 8.--31. 1. "hold5,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "hold4,Test setting input"
group.long 0xCC++0x03
line.long 0x00 "RTTSET19_23,"
hexmask.long.word 0x00 16.--31. 1. "hold6,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "hold5,Test setting input"
group.long 0xD0++0x03
line.long 0x00 "RTTSET20_23,"
hexmask.long.byte 0x00 24.--31. 1. "hold7,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "hold6,Test setting input"
group.long 0xD4++0x03
line.long 0x00 "RTTSET21_23,"
hexmask.long 0x00 0.--31. 1. "hold7,Test setting input"
group.long 0xD8++0x03
line.long 0x00 "RTTSET22_23,"
hexmask.long 0x00 0.--31. 1. "toggle4,Test setting input"
group.long 0xDC++0x03
line.long 0x00 "RTTSET23_23,"
hexmask.long.tbyte 0x00 8.--31. 1. "toggle5,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "toggle4,Test setting input"
group.long 0xE0++0x03
line.long 0x00 "RTTSET24_23,"
hexmask.long.word 0x00 16.--31. 1. "toggle6,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "toggle5,Test setting input"
group.long 0xE4++0x03
line.long 0x00 "RTTSET25_23,"
hexmask.long.byte 0x00 24.--31. 1. "toggle7,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "toggle6,Test setting input"
group.long 0xE8++0x03
line.long 0x00 "RTTSET26_23,"
hexmask.long 0x00 0.--31. 1. "toggle7,Test setting input"
group.long 0xEC++0x03
line.long 0x00 "RTTSET27_23,"
hexmask.long 0x00 0.--31. 1. "switching4,Test setting input"
group.long 0xF0++0x03
line.long 0x00 "RTTSET28_23,"
hexmask.long.tbyte 0x00 8.--31. 1. "switching5,Test setting input"
hexmask.long.byte 0x00 0.--7. 1. "switching4,Test setting input"
group.long 0xF4++0x03
line.long 0x00 "RTTSET29_23,"
hexmask.long.word 0x00 16.--31. 1. "switching6,Test setting input"
hexmask.long.word 0x00 0.--15. 1. "switching5,Test setting input"
group.long 0xF8++0x03
line.long 0x00 "RTTSET30_23,"
hexmask.long.byte 0x00 24.--31. 1. "switching7,Test setting input"
hexmask.long.tbyte 0x00 0.--23. 1. "switching6,Test setting input"
group.long 0xFC++0x03
line.long 0x00 "RTTSET31_23,"
hexmask.long 0x00 0.--31. 1. "switching7,Test setting input"
group.long 0x100++0x03
line.long 0x00 "RTTSET32_23,"
hexmask.long 0x00 0.--31. 1. "clknum_31_0,Test setting input"
group.long 0x104++0x03
line.long 0x00 "RTTSET33_23,"
hexmask.long 0x00 0.--31. 1. "Testmat_31_0,Test setting input"
group.long 0x108++0x03
line.long 0x00 "RTTSET34_23,"
hexmask.long 0x00 0.--31. 1. "Testmat_63_32,Test setting input"
group.long 0x10C++0x03
line.long 0x00 "RTTSET35_23,"
hexmask.long 0x00 0.--31. 1. "Testmat_95_64,Test setting input"
group.long 0x110++0x03
line.long 0x00 "RTTSET36_23,"
hexmask.long 0x00 0.--31. 1. "Testmat_127_96,Test setting input"
group.long 0x114++0x03
line.long 0x00 "RTTSET37_23,"
hexmask.long 0x00 0.--31. 1. "Testmat_159_128,Test setting input"
group.long 0x118++0x03
line.long 0x00 "RTTSET38_23,"
hexmask.long 0x00 0.--31. 1. "Testmat_191_160,Test setting input"
group.long 0x11C++0x03
line.long 0x00 "RTTSET39_23,"
hexmask.long 0x00 0.--31. 1. "Testmat_223_192,Test setting input"
group.long 0x120++0x03
line.long 0x00 "RTTSET40_23,"
hexmask.long 0x00 0.--31. 1. "Testmat_255_224,Test setting input"
group.long 0x124++0x03
line.long 0x00 "RTTSET41_23,"
hexmask.long.word 0x00 18.--31. 1. "Reserved_18,Reserved The bit or field is readable only"
hexmask.long.byte 0x00 10.--17. 1. "apbsel,Test setting input"
newline
bitfld.long 0x00 6.--9. "mbsel,Test setting input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--5. "coreselect,Test setting input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x128++0x03
line.long 0x00 "RTTSET42_23,"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved The bit or field is readable only" "0,1,2,3"
hexmask.long.word 0x00 16.--29. 1. "Y_address,Test setting input"
newline
rbitfld.long 0x00 14.--15. "Reserved_14,Reserved The bit or field is readable only" "0,1,2,3"
hexmask.long.word 0x00 0.--13. 1. "X_address,Test setting input"
group.long 0x12C++0x03
line.long 0x00 "RTTSET43_23,"
rbitfld.long 0x00 31. "Reserved_31,Reserved The bit or field is readable only" "0,1"
hexmask.long.tbyte 0x00 14.--30. 1. "XY,Test setting input"
newline
hexmask.long.word 0x00 0.--13. 1. "Z_address,Test setting input"
group.long 0x130++0x03
line.long 0x00 "RTTSET44_23,"
rbitfld.long 0x00 26.--31. "Reserved_26,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x00 16.--25. 1. "scanchain,Test setting input for hardware-SCAN"
newline
hexmask.long.word 0x00 0.--15. 1. "scanpat,Test setting input for hardware-SCAN"
group.long 0x400++0x03
line.long 0x00 "PSTRSTT23,"
hexmask.long.tbyte 0x00 13.--31. 1. "Reserved_13,Reserved"
rbitfld.long 0x00 12. "R_rst_T,BIST Redundant result" "0: pass,1: fail"
newline
rbitfld.long 0x00 11. "Reserved_11,Reserved" "0,1"
rbitfld.long 0x00 8.--10. "error_T,BIST error" "0: Pass,1: Fail,2: TimeOut,?,4: BUS error,?..."
newline
rbitfld.long 0x00 4.--7. "testnum_T,Number of tests" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 2.--3. "status_R,BIST Redundant status (Safety function)" "0: unexec,1: wait,2: exec,3: finish"
newline
rbitfld.long 0x00 0.--1. "status_T,BIST status" "0: unexec,1: wait,2: exec,3: finish"
group.long 0x440++0x03
line.long 0x00 "PSTCNT23,"
hexmask.long 0x00 0.--31. 1. "Stop,FieldBIST internal WDT (high counter) stop value"
group.long 0x444++0x03
line.long 0x00 "RTTRSTT23,When status_T in the RTTRSTT register is"
rbitfld.long 0x00 30.--31. "Reserved_30,Reserved" "0,1,2,3"
rbitfld.long 0x00 29. "IL_flag2,Runtime Test Illegal suspension flag-2" "0,1"
newline
rbitfld.long 0x00 28. "IL_flag1,Runtime Test Illegal suspension flag-1" "0,1"
rbitfld.long 0x00 27. "CONDF,Debug monitor of FieldBIST condition" "0: not response,1: responded"
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rbitfld.long 0x00 24.--26. "BUS_cond,Debug code of BUS condition" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 13.--23. 1. "Reserved_13,Reserved"
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rbitfld.long 0x00 12. "R_rst_T,BIST Redundant result (Safety function)" "0: Pass,1: Fail"
rbitfld.long 0x00 11. "Achk,Debug code of address check" "0: normal,1: warning"
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rbitfld.long 0x00 8.--10. "error_T,BIST error" "0: Pass,1: Fail,2: TimeOut,?,4: BUS error,?..."
rbitfld.long 0x00 4.--7. "testnum_T,Number of tests" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 2.--3. "R_status_T,BIST redundant status" "0: unexec,1: wait,2: exec,3: finish"
rbitfld.long 0x00 0.--1. "status_T,BIST status" "0: unexec,1: wait,2: exec,3: finish"
group.long 0x458++0x03
line.long 0x00 "RTTCNT23,"
hexmask.long 0x00 0.--31. 1. "Stop,WDT (high counter) stop value"
group.long 0x4A0++0x03
line.long 0x00 "SLFRVS23,"
hexmask.long.word 0x00 20.--31. 1. "Reserved_20,Reserved"
hexmask.long.tbyte 0x00 0.--19. 1. "REVERS,Expected value reverse for Self-Check SISR"
group.long 0x4A4++0x03
line.long 0x00 "SLFRST23,In case of the SLFR bits of the RTTRSTT register is 1B'1 SCNT bit returns to 1"
rbitfld.long 0x00 26.--31. "SCNT,Self-Check counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 24.--25. "STS,Self-Check status" "0: unexec,1: exec,?,3: finish"
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hexmask.long.tbyte 0x00 1.--23. 1. "Reserved_1,Reserved"
rbitfld.long 0x00 0. "STR,Self -Check Result" "0: Pass,1: Fail"
group.long 0x4C0++0x03
line.long 0x00 "ERRSET23,"
hexmask.long 0x00 3.--31. 1. "Reserved_3,Reserved"
bitfld.long 0x00 2. "DSB,Dummy set BUS-Error (set of fbc_rt_safetyerr)" "0,1"
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bitfld.long 0x00 1. "DST,Dummy set Time out (set of fbc_rt_overerr)" "0,1"
bitfld.long 0x00 0. "DSF,Dummy set Fail (set of fbc_rt_fail)" "0,1"
tree.end
tree "FUNCTIONAL_SAFETY_INST_23"
base ad:0xFF830000
group.long 0x100++0x03
line.long 0x00 "RTTFINISH1,"
hexmask.long.word 0x00 23.--31. 1. "Reserved_23,Reserved.The bit is always read as 0"
rbitfld.long 0x00 22. "CA55SS1_Core7,finish interrupt observation Cortex-A55 CPU core 7 Hierarchy (A1 domain)" "0,1"
rbitfld.long 0x00 21. "CA55SS1_Core6,finish interrupt observation Cortex-A55 CPU core 6 Hierarchy (A1 domain)" "0,1"
rbitfld.long 0x00 20. "CA55SS1_Cluster3,finish interrupt observation Cortex-A55 CPU cluster 3 Hierarchy (A2 domain)" "0,1"
rbitfld.long 0x00 19. "CA55SS1_Core5,finish interrupt observation Cortex-A55 CPU core 5 Hierarchy (A1 domain)" "0,1"
rbitfld.long 0x00 18. "CA55SS1_Core4,finish interrupt observation Cortex-A55 CPU core 4 Hierarchy (A1 domain)" "0,1"
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rbitfld.long 0x00 17. "CA55SS1_Cluster2,finish interrupt observation Cortex-A55 CPU cluster 2 Hierarchy (A2 domain)" "0,1"
rbitfld.long 0x00 15.--16. "Reserved_15,Reserved.These bits are always read as 0" "0,1,2,3"
rbitfld.long 0x00 14. "CA55SS0_Core3,finish interrupt observation Cortex-A55 CPU core 3 Hierarchy (A1 domain)" "0,1"
rbitfld.long 0x00 13. "CA55SS0_Core2,finish interrupt observation Cortex-A55 CPU core 2 Hierarchy (A1 domain)" "0,1"
rbitfld.long 0x00 12. "CA55SS0_Cluster1,finish interrupt observation Cortex-A55 CPU cluster 1 Hierarchy (A2 domain)" "0,1"
rbitfld.long 0x00 11. "CA55SS0_Core1,finish interrupt observation Cortex-A55 CPU core 1 Hierarchy (A1 domain)" "0,1"
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rbitfld.long 0x00 10. "CA55SS0_Core0,finish interrupt observation Cortex-A55 CPU core 0 Hierarchy (A1 domain)" "0,1"
rbitfld.long 0x00 9. "CA55SS0_Cluster0,finish interrupt observation Cortex-A55 CPU cluster 0 Hierarchy (A2 domain)" "0,1"
hexmask.long.word 0x00 0.--8. 1. "Reserved_0,Reserved.These bits are always read as 0"
repeat 2. (strings "2" "3" )(list 0x00 0x04 )
group.long ($2+0x104)++0x03
line.long 0x00 "RTTFINISH$1,"
hexmask.long 0x00 0.--31. 1. "Reserved_0,Reserved.These bits are always read as 0"
repeat.end
tree.end
tree.end
tree "E-FUSE"
base ad:0xE6078800
group.long 0xC0++0x03
line.long 0x00 "FUSE_MON0,CA55 crypt extention (fuse_ca55crypt)"
hexmask.long.word 0x00 23.--31. 1. "fuse_mon0_31_23,Reserved"
rbitfld.long 0x00 22. "fuse_mon0_22," "0,1"
rbitfld.long 0x00 21. "fuse_mon0_21," "0,1"
rbitfld.long 0x00 20. "fuse_mon0_20," "0,1"
rbitfld.long 0x00 19. "fuse_mon0_19,Reserved" "0,1"
rbitfld.long 0x00 18. "fuse_mon0_18,This bit is always read as 0" "0,1"
rbitfld.long 0x00 17. "fuse_mon0_17,This bit is always read as 0" "0,1"
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rbitfld.long 0x00 15.--16. "fuse_mon0_16_15,This bit is always read as 0" "0,1,2,3"
rbitfld.long 0x00 14. "fuse_mon0_14,This bit is always read as 0" "0,1"
rbitfld.long 0x00 12.--13. "fuse_mon0_13_12,This bit is always read as 0" "0,1,2,3"
rbitfld.long 0x00 11. "fuse_mon0_11,This bit is always read as 0" "0,1"
rbitfld.long 0x00 9.--10. "fuse_mon0_10_9," "0,1,2,3"
rbitfld.long 0x00 8. "fuse_mon0_8," "0,1"
rbitfld.long 0x00 6.--7. "fuse_mon0_7_6," "0,1,2,3"
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rbitfld.long 0x00 5. "fuse_mon0_5," "0,1"
rbitfld.long 0x00 4. "fuse_mon0_4," "0,1"
rbitfld.long 0x00 3. "fuse_mon0_3," "0,1"
rbitfld.long 0x00 2. "fuse_mon0_2,This bit is always read as 0" "0,1"
rbitfld.long 0x00 1. "fuse_mon0_1,This bit is always read as 0" "0,1"
rbitfld.long 0x00 0. "fuse_mon0_0,This bit is always read as 0" "0,1"
group.long 0xD8++0x03
line.long 0x00 "FUSE_MON6,Power domain power control (fuse_pdid)"
hexmask.long.tbyte 0x00 14.--31. 1. "fuse_mon6_31_14,Reserved"
hexmask.long.word 0x00 0.--13. 1. "fuse_mon6_13_0,These bits are always read as 0"
group.long 0x140++0x03
line.long 0x00 "LTM0_MON0,S4/S4N product_bit (fuse_aging0)"
hexmask.long 0x00 1.--31. 1. "ltm0_mon0_31_1,Reserved"
rbitfld.long 0x00 0. "ltm0_mon0_0," "0,1"
group.long 0x144++0x03
line.long 0x00 "LTM0_MON1,UFS PLLCalibration (fuse_aging0)"
hexmask.long.byte 0x00 24.--31. 1. "ltm0_mon1_31_24,UFS PLL Tune RateB"
hexmask.long.byte 0x00 16.--23. 1. "ltm0_mon1_23_16,UFS PLL Tune RateA"
hexmask.long.byte 0x00 8.--15. 1. "ltm0_mon1_15_8,UFS PLL Tune RateB Redundancy"
hexmask.long.byte 0x00 0.--7. 1. "ltm0_mon1_7_0,UFS PLL Tune RateA Redundancy"
group.long 0x148++0x03
line.long 0x00 "LTM0_MON2,UFS AFE CTLE/ATT (fuse_aging0)"
hexmask.long.byte 0x00 24.--31. 1. "ltm0_mon2_31_24,UFS AFE CTLE Tune"
hexmask.long.byte 0x00 16.--23. 1. "ltm0_mon2_23_16,UFS AFE ATT Tune"
hexmask.long.byte 0x00 8.--15. 1. "ltm0_mon2_15_8,UFS AFE CTLE Tune Redundancy"
hexmask.long.byte 0x00 0.--7. 1. "ltm0_mon2_7_0,UFS AFE ATT Tune Redundancy"
tree.end
tree "ROM"
base ad:0xEB120000
group.long 0xD000++0x03
line.long 0x00 "ACCERRSTS1,This register indicates the status of access error to ICUMX code area from ICUP in ICUMX"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved The read value of these bits are always 0"
rbitfld.long 0x00 0. "err," "0,1"
group.long 0xD004++0x03
line.long 0x00 "ACCERRSTS2,This register indicates the status of access error to ICUMX code area from non ICUP masters"
hexmask.long 0x00 1.--31. 1. "Reserved_1,Reserved The read value of these bits are always 0"
rbitfld.long 0x00 0. "err," "0,1"
group.long 0xE000++0x03
line.long 0x00 "INJ_ERR_S2,Access read to this register will trigger error injection for EDC single bit error2"
hexmask.long 0x00 0.--31. 1. "err_inj,trigger of error injection for EDC single bit error2"
group.long 0xE004++0x03
line.long 0x00 "INJ_ERR_M2,Access read to this register will trigger error injection for EDC multiple bit error2"
hexmask.long 0x00 0.--31. 1. "err_inj,trigger of error injection for EDC single and multi bit error2"
group.long 0xE008++0x03
line.long 0x00 "INJ_ERR_S,Access read to this register will trigger error injection for EDC single error"
hexmask.long 0x00 0.--31. 1. "err_inj,trigger of error injection for EDC single bit error"
group.long 0xE00C++0x03
line.long 0x00 "INJ_ERR_M,Access read to this register will trigger error injection for EDC multiple error"
hexmask.long 0x00 0.--31. 1. "err_inj,trigger of error injection for EDC single and multi bit error"
repeat 4. (strings "0" "2" "3" "1" )(list 0x00 0x100 0x300 0x800 )
group.long ($2+0xF000)++0x03
line.long 0x00 "INJ_ERR_CTR$1,These registers control the enable of error injection"
hexmask.long 0x00 0.--31. 1. "err_inj_ctr,error injection enable control"
repeat.end
tree.end
autoindent.off
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